--- /dev/null
+# Atmel SAMA5D2x Software Package\r
+\r
+\r
+## Version 1.2 - 2015-12\r
+\r
+### New drivers/examples\r
+\r
+- USB Device examples and stack: CDC Serial, HID Keyboard, HID Mouse, Audio,\r
+ Mass Storage and some composite examples.\r
+- NAND flash driver and examples: supports MLC/SLC, up to 32-bit ECC.\r
+- SDMMC/eMMC driver and example\r
+- Low Power examples: power_consumption_pll, pmc_clock_switching,\r
+ low_power_mode\r
+- New storagemedia library to abstract storage devices (only supports RAM disk\r
+ for now, but will support SDMMC/eMMC and NAND flash in later releases)\r
+\r
+### Enhancements\r
+\r
+- Several new functions in PMC driver, notably 'pmc_set_custom_pck_mck' that\r
+ allow changing easily the main clock settings.\r
+- IAR project generator now uses defines and include directories from\r
+ CFLAGS_DEFS and CFLAGS_INC mkefile variables. It also generates projects with\r
+ CMSIS-DAP debugger selected and proper optimization level.\r
+\r
+### Fixes\r
+\r
+- Fix CP15 driver to invalidate caches before enable. This fixes some lock-ups\r
+ when caches were previously enabled and still contain stale data.\r
+\r
+\r
+\r
+## Version 1.1 - 2015-10\r
+\r
+### New drivers\r
+\r
+- Class-D audio driver + example\r
+\r
+### Enhancements\r
+\r
+- Support for ISO7816 and LIN modes to UART driver + example\r
+- Several functions added to PMC driver, mostly UPLL and AudioPLL support\r
+- ISC/sensors: support for new capture modes / resolutions\r
+\r
+### Fixes\r
+\r
+- Several fixes to ADC driver and example\r
+- Fixed MMU setup (some memory regions where not defined)\r
+\r
+\r
+\r
+## Version 1.0 - 2015-09\r
+\r
+### New drivers\r
+\r
+- MCAN driver + example\r
+\r
+### Changes\r
+\r
+- sama5d2-xplained target adapted for final revA board\r
+\r
+### Enhancements\r
+\r
+- Clock initialization changed to be more reliable\r
+- PMC driver now supports setting generated clocks on sama5d2\r
+- Add support for new memory models to at25 driver (MX25L12835F, MX25L4005,\r
+ N25Q032, S25FL127S)\r
+\r
+\r
+\r
+## Version 0.3 -- 2015-08\r
+\r
+### New drivers\r
+\r
+- ACC driver\r
+- ADC driver + example\r
+- AES / TDES / SHA drivers + examples\r
+- L2CC driver\r
+- GMAC driver + examples (using ad-hoc / LWIP / UIP stacks)\r
+- QT1070 driver\r
+- SHDWC driver\r
+\r
+### Enhancements\r
+\r
+- FPU is now enabled in GCC startup (was already enabled for IAR)\r
+- ISC example now demonstrates Auto White Balance / Auto Exposure\r
+- SPID/TWID/USARTD drivers now switch the Flexcom mode when appropriate\r
+- MMU is now has a non-cacheable DDR region (used by LCD and GMAC examples)\r
+\r
+### Fixes\r
+\r
+- RAM timings / configuration adjusted for sama5d2-xplained target\r
+- Component headers in target/sama5d2/components updated to reflect latest\r
+ datasheet updates\r
+- PIO and TRNG callbacks now have a configurable user-defined argument\r
--- /dev/null
+Copyright (c) 2015, Atmel Corporation All rights reserved.\r
+----------------------------------------------------------\r
+\r
+* Redistribution and use in source and binary forms, with or without\r
+* modification, are permitted provided that the following conditions are met:\r
+*\r
+* - Redistributions of source code must retain the above copyright notice,\r
+* this list of conditions and the disclaimer below.\r
+*\r
+* Atmel's name may not be used to endorse or promote products derived from\r
+* this software without specific prior written permission.\r
+*\r
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+\r
+# Atmel SAMA5D2x Software Package\r
+\r
+## Overview\r
+\r
+This softpack comes as an early delivery and all presented APIs are subject to change.\r
+\r
+Each software module is provided with full source code, example of usage, and ready-to-use projects.\r
+\r
+### Supported Platforms\r
+\r
+Windows and Linux with the gnu GCC ARM Embedded toolchain. It is downloadable at this address: https://launchpad.net/gcc-arm-embedded (Mac OS X should also work but as not been tested yet).\r
+Dependencies:\r
+- GNU make (from MinGW, Cygwin or GnuWin32 for Windows architectures)\r
+- bash (from MinGW, Cygwin for Windows architectures)\r
+\r
+Windows with IAR Embedded Workbench.\r
+Dependencies:\r
+- IAR Embedded Workbench (Tested on version 7.40)\r
+- bash (from MinGW, Cygwin or GnuWin32) for IAR project generation\r
+- GNU make (from MinGW, Cygwin or GnuWin32) for IAR project generation\r
+- mktemp (from MinGW, Cygwin or GnuWin32) for IAR project generation\r
+\r
+Notice: This softpack comes as an early delivery and all presented APIs are subject to change.\r
+\r
+## Contents \r
+\r
+### Directory Architecture\r
+\r
+- target/sama5d2\r
+ All chip and board specific source files\r
+\r
+- target/sama5d2/toolchain/\r
+ Linker and debugger scripts\r
+\r
+- scripts/\r
+ generators and build script templates (Makefiles)\r
+\r
+- drivers/\r
+ Driver source files\r
+\r
+- examples/\r
+ All examples \r
+\r
+### Examples\r
+\r
+This release contains the following examples:\r
+\r
+adc: Example using ADC\r
+\r
+can: Example using CAN\r
+\r
+crypto_aes: AES hardware computation (with and without DMA)\r
+\r
+crypto_sha: SHA hardware computation (with and without DMA)\r
+\r
+crypto_tdes: Triple-DES hardware computation (with and without DMA)\r
+\r
+fifo: Test Flexcom USART FIFO\r
+\r
+gettting-started: LED blink (uses PIT and PIO)\r
+\r
+gmac: GMAC example using a simple IP stack\r
+\r
+gmac_lwip: GMAC example using LWIP stack\r
+\r
+gmac_uip_helloworld: GMAC example using UIP stack (UIP helloworld example)\r
+\r
+gmac_uip_telnetd: GMAC example using UIP stack (UIP telnetd example)\r
+\r
+gmac_uip_webserver: GMAC example using UIP stack (UIP webserver example)\r
+\r
+isc: Example using ISC controller (OV7740 sensor)\r
+\r
+lcd: Example using LCD controller\r
+\r
+qspi_flash: Read/Write/Delete commands to a QSPI serial flash\r
+\r
+rtc: RTC Example\r
+\r
+spi_serialflash: Read/Write/Delete commands to an SPI serial flash\r
+\r
+trng: Example using hardware RNG (interrupt mode)\r
+\r
+twi_eeprom: Read/Write/Delete commands to an Two-Wire EEPROM\r
+\r
+wdt: Example using watchdog timer\r
+\r
+xdma: Memory-to-memory DMA transfert example\r
+\r
+xdma_usart: Bidirectionnal Usart-memory DMA transfert example\r
+\r
+## Usage (GCC ARM Embedded)\r
+\r
+### Environment Variable\r
+\r
+TARGET: Name of the wanted target (sama5d2-xplained for samad52 XPLAINED ULTRA boards). This variable is mandatory to launch any build.\r
+\r
+DEBUG: Build with debug flags (default).\r
+\r
+TRACE_LEVEL: The wanted log level, 5 correspond to full, 0 to none (default to 5)\r
+\r
+RELEASE: Build with the release flags\r
+\r
+only TARGET must be provided or set at each make invocation.\r
+\r
+### Build\r
+\r
+Run:\r
+\r
+make\r
+#or\r
+make TARGET=wanted_target # if TARGET is not set\r
+\r
+### Run and Debug (with GDB)\r
+\r
+To run examples with gdb, first, JLinkGDBServer must be started. It can be downloaded for each platform at http://www.segger.com\r
+\r
+A make target is provided to launch the test with the correct gdb command arguments, run:\r
+\r
+make debug\r
+#or\r
+make TARGET=wanted_target debug # if TARGET is not set\r
+\r
+## Usage (IAR)\r
+\r
+The Win version of this softpack release comes with pregenerated IAR projects compatible with IAR Systems Embedded Workbench for ARM version 7.40.\r
+\r
+The C-SPY device description files and device selections files are not included and must be installed manually.\r
+\r
+### IAR Project generation\r
+\r
+An IAR project can be generated with GNU make, run in the example directory:\r
+\r
+make iar\r
+#or\r
+make TARGET=wanted_target iar # if TARGET is not set\r
+\r
+All needed IAR project files will be put in the example directory, including a default workspace one.\r
+\r
+Notice:\r
+GNU make may fail on Windows platforms if the Makefile contains UNIX line endings.\r
+You can use unix2dos on all Makefile files in scripts/ directory to fix this issue.\r
--- /dev/null
+-- *****************************************************************************\r
+\r
+-- BSDL file for design top\r
+\r
+-- Created by Synopsys Version I-2013.12-SP3 (Apr 18, 2014)\r
+\r
+-- Designer: \r
+-- Company: \r
+\r
+-- Date: Thu Feb 5 22:28:17 2015\r
+\r
+-- *****************************************************************************\r
+\r
+\r
+ entity top is\r
+ \r
+-- This section identifies the default device package selected.\r
+ \r
+ generic (PHYSICAL_PIN_MAP: string:= "BGA196");\r
+ \r
+-- This section declares all the ports in the design.\r
+ \r
+ port ( \r
+ PD14 : in bit;\r
+ PD15 : in bit;\r
+ PD17 : in bit;\r
+ PD18 : in bit;\r
+ -- PA0 : linkage bit; -- NC Port\r
+ -- PA1 : linkage bit; -- NC Port\r
+ -- PA10 : linkage bit; -- NC Port\r
+ -- PA11 : linkage bit; -- NC Port\r
+ -- PA12 : linkage bit; -- NC Port\r
+ -- PA13 : linkage bit; -- NC Port\r
+ -- PA14 : linkage bit; -- NC Port\r
+ -- PA15 : linkage bit; -- NC Port\r
+ -- PA16 : linkage bit; -- NC Port\r
+ -- PA17 : linkage bit; -- NC Port\r
+ PA18 : inout bit;\r
+ PA19 : inout bit;\r
+ -- PA2 : linkage bit; -- NC Port\r
+ PA20 : inout bit;\r
+ PA21 : inout bit;\r
+ PA22 : inout bit;\r
+ PA23 : inout bit;\r
+ PA24 : inout bit;\r
+ PA25 : inout bit;\r
+ PA26 : inout bit;\r
+ PA27 : inout bit;\r
+ PA28 : inout bit;\r
+ PA29 : inout bit;\r
+ -- PA3 : linkage bit; -- NC Port\r
+ PA30 : inout bit;\r
+ PA31 : inout bit;\r
+ -- PA4 : linkage bit; -- NC Port\r
+ -- PA5 : linkage bit; -- NC Port\r
+ -- PA6 : linkage bit; -- NC Port\r
+ -- PA7 : linkage bit; -- NC Port\r
+ -- PA8 : linkage bit; -- NC Port\r
+ -- PA9 : linkage bit; -- NC Port\r
+ PB0 : inout bit;\r
+ PB1 : inout bit;\r
+ PB10 : inout bit;\r
+ PB11 : inout bit;\r
+ PB12 : inout bit;\r
+ PB13 : inout bit;\r
+ PB14 : inout bit;\r
+ PB15 : inout bit;\r
+ PB16 : inout bit;\r
+ PB17 : inout bit;\r
+ PB18 : inout bit;\r
+ PB19 : inout bit;\r
+ PB2 : inout bit;\r
+ PB20 : inout bit;\r
+ PB21 : inout bit;\r
+ PB22 : inout bit;\r
+ PB23 : inout bit;\r
+ PB24 : inout bit;\r
+ PB25 : inout bit;\r
+ PB26 : inout bit;\r
+ PB27 : inout bit;\r
+ PB28 : inout bit;\r
+ PB29 : inout bit;\r
+ PB3 : inout bit;\r
+ PB30 : inout bit;\r
+ PB31 : inout bit;\r
+ PB4 : inout bit;\r
+ PB5 : inout bit;\r
+ PB6 : inout bit;\r
+ PB7 : inout bit;\r
+ PB8 : inout bit;\r
+ PB9 : inout bit;\r
+ PC0 : inout bit;\r
+ PC1 : inout bit;\r
+ -- PC10 : linkage bit; -- NC Port\r
+ -- PC11 : linkage bit; -- NC Port\r
+ -- PC12 : linkage bit; -- NC Port\r
+ -- PC13 : linkage bit; -- NC Port\r
+ -- PC14 : linkage bit; -- NC Port\r
+ -- PC15 : linkage bit; -- NC Port\r
+ -- PC16 : linkage bit; -- NC Port\r
+ -- PC17 : linkage bit; -- NC Port\r
+ -- PC18 : linkage bit; -- NC Port\r
+ -- PC19 : linkage bit; -- NC Port\r
+ PC2 : inout bit;\r
+ -- PC20 : linkage bit; -- NC Port\r
+ -- PC21 : linkage bit; -- NC Port\r
+ -- PC22 : linkage bit; -- NC Port\r
+ -- PC23 : linkage bit; -- NC Port\r
+ -- PC24 : linkage bit; -- NC Port\r
+ -- PC25 : linkage bit; -- NC Port\r
+ -- PC26 : linkage bit; -- NC Port\r
+ -- PC27 : linkage bit; -- NC Port\r
+ -- PC28 : linkage bit; -- NC Port\r
+ -- PC29 : linkage bit; -- NC Port\r
+ PC3 : inout bit;\r
+ -- PC30 : linkage bit; -- NC Port\r
+ -- PC31 : linkage bit; -- NC Port\r
+ PC4 : inout bit;\r
+ PC5 : inout bit;\r
+ PC6 : inout bit;\r
+ PC7 : inout bit;\r
+ PC8 : inout bit;\r
+ -- PC9 : linkage bit; -- NC Port\r
+ -- PD0 : linkage bit; -- NC Port\r
+ -- PD1 : linkage bit; -- NC Port\r
+ PD10 : inout bit;\r
+ PD11 : inout bit;\r
+ PD12 : inout bit;\r
+ PD13 : inout bit;\r
+ PD19 : inout bit;\r
+ -- PD2 : linkage bit; -- NC Port\r
+ PD20 : inout bit;\r
+ PD21 : inout bit;\r
+ PD22 : inout bit;\r
+ PD23 : inout bit;\r
+ -- PD24 : linkage bit; -- NC Port\r
+ -- PD25 : linkage bit; -- NC Port\r
+ -- PD26 : linkage bit; -- NC Port\r
+ -- PD27 : linkage bit; -- NC Port\r
+ -- PD28 : linkage bit; -- NC Port\r
+ -- PD29 : linkage bit; -- NC Port\r
+ -- PD3 : linkage bit; -- NC Port\r
+ -- PD30 : linkage bit; -- NC Port\r
+ -- PD31 : linkage bit; -- NC Port\r
+ -- PD4 : linkage bit; -- NC Port\r
+ -- PD5 : linkage bit; -- NC Port\r
+ -- PD6 : linkage bit; -- NC Port\r
+ PD7 : inout bit;\r
+ PD8 : inout bit;\r
+ PD9 : inout bit;\r
+ DDR_D : inout bit_vector (0 to 15);\r
+ DDR_DQS : inout bit_vector (0 to 1);\r
+ DDR_DQSN : inout bit_vector (0 to 1);\r
+ DDR_CAS : out bit;\r
+ DDR_CKE : out bit;\r
+ DDR_CLK : out bit;\r
+ DDR_CLKN : out bit;\r
+ DDR_CS : out bit;\r
+ DDR_RAS : out bit;\r
+ DDR_RESETN : out bit;\r
+ DDR_WE : out bit;\r
+ PD16 : out bit;\r
+ DDR_A : out bit_vector (0 to 13);\r
+ DDR_BA : out bit_vector (0 to 2);\r
+ DDR_DQM : out bit_vector (0 to 1);\r
+ -- ADVREFN : linkage bit;\r
+ ADVREFP : linkage bit;\r
+ CLK_AUDIO : linkage bit;\r
+ COMPN : linkage bit;\r
+ COMPP : linkage bit;\r
+ DDR_CAL : linkage bit;\r
+ DDR_VREF : linkage bit; -- DDR_VREFB0 : linkage bit;\r
+ -- DDR_VREFB1 : linkage bit;\r
+ -- DDR_VREFB2 : linkage bit;\r
+ -- DDR_VREFB3 : linkage bit;\r
+ -- DDR_VREFCM : linkage bit;\r
+ HHSDMA : linkage bit;\r
+ HHSDMB : linkage bit;\r
+ -- HHSDMSTRC : linkage bit; -- NC Port\r
+ HHSDPA : linkage bit;\r
+ HHSDPB : linkage bit;\r
+ -- HHSDPDATC : linkage bit; -- NC Port\r
+ JTAGSEL : in bit;\r
+ NRST : linkage bit;\r
+ -- RXD : linkage bit; -- NC Port\r
+ -- SDCAL : linkage bit; -- NC Port\r
+ SHDN : linkage bit;\r
+ TST : in bit;\r
+ VBG : linkage bit;\r
+ WKUP : linkage bit;\r
+ XIN : linkage bit;\r
+ XIN32 : linkage bit;\r
+ XOUT : linkage bit;\r
+ XOUT32 : linkage bit;\r
+ -- tst_drst_ana : linkage bit; -- NC Port\r
+ -- tst_drst_ddr : linkage bit; -- NC Port\r
+ -- tst_drst_iop0 : linkage bit; -- NC Port\r
+ -- tst_drst_iop1 : linkage bit; -- NC Port\r
+ -- tst_drst_iop2 : linkage bit; -- NC Port\r
+ -- tst_drst_isi : linkage bit; -- NC Port\r
+ -- tst_drst_osc : linkage bit; -- NC Port\r
+ -- tst_drst_sdhc : linkage bit; -- NC Port\r
+ -- tst_lft_plla : linkage bit; -- NC Port\r
+ -- tst_lft_utmi : linkage bit; -- NC Port\r
+ -- tst_por_1v2 : linkage bit; -- NC Port\r
+ -- tst_por_1v8 : linkage bit; -- NC Port\r
+ -- tst_por_bu : linkage bit; -- NC Port\r
+ -- tst_psw_bu : linkage bit; -- NC Port\r
+ -- tst_psw_fuse : linkage bit; -- NC Port\r
+ PIOBU : linkage bit_vector (0 to 5)\r
+ );\r
+ \r
+ use STD_1149_1_1994.all;\r
+ \r
+ attribute COMPONENT_CONFORMANCE of top: entity is "STD_1149_1_1993";\r
+ \r
+ attribute PIN_MAP of top: entity is PHYSICAL_PIN_MAP;\r
+ \r
+-- This section specifies the pin map for each port. This information is \r
+-- extracted from the port-to-pin map file that was read in using the \r
+-- "read_pin_map" command.\r
+ \r
+ constant BGA196: PIN_MAP_STRING := \r
+ "PD14 : G6," &\r
+ "PD15 : H5," &\r
+ "PD17 : G2," &\r
+ "PD18 : G3," &\r
+ "PA18 : L9," &\r
+ "PA19 : N9," &\r
+ "PA20 : M9," &\r
+ "PA21 : M10," &\r
+ "PA22 : P9," &\r
+ "PA23 : P10," &\r
+ "PA24 : N10," &\r
+ "PA25 : L10," &\r
+ "PA26 : P11," &\r
+ "PA27 : P12," &\r
+ "PA28 : M11," &\r
+ "PA29 : N11," &\r
+ "PA30 : N12," &\r
+ "PA31 : M12," &\r
+ "PB0 : A6," &\r
+ "PB1 : A5," &\r
+ "PB10 : A1," &\r
+ "PB11 : B1," &\r
+ "PB12 : B2," &\r
+ "PB13 : C1," &\r
+ "PB14 : D5," &\r
+ "PB15 : E5," &\r
+ "PB16 : C5," &\r
+ "PB17 : C2," &\r
+ "PB18 : D4," &\r
+ "PB19 : C4," &\r
+ "PB2 : B6," &\r
+ "PB20 : C3," &\r
+ "PB21 : D1," &\r
+ "PB22 : D2," &\r
+ "PB23 : E1," &\r
+ "PB24 : D3," &\r
+ "PB25 : E3," &\r
+ "PB26 : E2," &\r
+ "PB27 : E6," &\r
+ "PB28 : F1," &\r
+ "PB29 : F6," &\r
+ "PB3 : B5," &\r
+ "PB30 : F2," &\r
+ "PB31 : F7," &\r
+ "PB4 : A4," &\r
+ "PB5 : D6," &\r
+ "PB6 : A3," &\r
+ "PB7 : B4," &\r
+ "PB8 : A2," &\r
+ "PB9 : B3," &\r
+ "PC0 : M13," &\r
+ "PC1 : P13," &\r
+ "PC2 : N13," &\r
+ "PC3 : K10," &\r
+ "PC4 : P14," &\r
+ "PC5 : J8," &\r
+ "PC6 : N14," &\r
+ "PC7 : M14," &\r
+ "PC8 : J9," &\r
+ "PD10 : G4," &\r
+ "PD11 : H1," &\r
+ "PD12 : H6," &\r
+ "PD13 : H3," &\r
+ "PD19 : H4," &\r
+ "PD20 : J1," &\r
+ "PD21 : K1," &\r
+ "PD22 : J3," &\r
+ "PD23 : K2," &\r
+ "PD7 : F5," &\r
+ "PD8 : F3," &\r
+ "PD9 : G5," &\r
+ "DDR_D : (B7, A7, C8, B9, A9, C9, A10, B10, H13, H14, J13, J14, L13, L14, J12, K12)," &\r
+ "DDR_DQS : (B8, K14)," &\r
+ "DDR_DQSN : (A8, K13)," &\r
+ "DDR_CAS : C13," &\r
+ "DDR_CKE : E14," &\r
+ "DDR_CLK : A13," &\r
+ "DDR_CLKN : B13," &\r
+ "DDR_CS : F11," &\r
+ "DDR_DQM : (D8, G14)," &\r
+ "DDR_RAS : C14," &\r
+ "DDR_RESETN : D13," &\r
+ "DDR_WE : A14," &\r
+ "PD16 : G1," &\r
+ "DDR_A : (E11, C11, B12, A12, D11, D14, B14, D9, C10, D10, " &\r
+ "F9, A11, B11, E13)," &\r
+ "DDR_BA : (F13, G13, F14)," &\r
+ "ADVREFP : L2," &\r
+ "CLK_AUDIO : J7," &\r
+ "COMPN : P2," &\r
+ "COMPP : N2," &\r
+ "DDR_CAL : F10," &\r
+ "HHSDMA : P7," &\r
+ "HHSDMB : P8," &\r
+ "HHSDPA : N7," &\r
+ "HHSDPB : N8," &\r
+ "JTAGSEL : L4," &\r
+ "NRST : N3," &\r
+ "SHDN : N1," &\r
+ "TST : M2," &\r
+ "VBG : L7," &\r
+ "WKUP : P1," &\r
+ "XIN : P5," &\r
+ "XIN32 : M1," &\r
+ "XOUT : P6," &\r
+ "XOUT32 : L1," &\r
+ "PIOBU : (K5, L3, M3, N4, L5, M6)";\r
+ \r
+-- This section specifies the differential IO port groupings.\r
+ \r
+ attribute PORT_GROUPING of top: entity is \r
+ "Differential_Voltage ( " &\r
+ "(DDR_CLK,DDR_CLKN))";\r
+\r
+-- This section specifies the TAP ports. For the TAP TCK port, the parameters in \r
+-- the brackets are:\r
+-- First Field : Maximum TCK frequency.\r
+-- Second Field: Allowable states TCK may be stopped in.\r
+ \r
+ attribute TAP_SCAN_CLOCK of PD14: signal is (10.0e6, BOTH);\r
+ attribute TAP_SCAN_IN of PD15: signal is true;\r
+ attribute TAP_SCAN_MODE of PD17: signal is true;\r
+ attribute TAP_SCAN_OUT of PD16: signal is true;\r
+ attribute TAP_SCAN_RESET of PD18: signal is true;\r
+ \r
+-- Specifies the compliance enable patterns for the design. It lists a set of \r
+-- design ports and the values that they should be set to, in order to enable \r
+-- compliance to IEEE Std 1149.1\r
+ \r
+ attribute COMPLIANCE_PATTERNS of top: entity is \r
+ "(JTAGSEL, TST) (10)";\r
+ \r
+-- Specifies the number of bits in the instruction register.\r
+ \r
+ attribute INSTRUCTION_LENGTH of top: entity is 4;\r
+ \r
+-- Specifies the boundary-scan instructions implemented in the design and their \r
+-- opcodes.\r
+ \r
+ attribute INSTRUCTION_OPCODE of top: entity is \r
+ "BYPASS (1111, 0001, 0101, 0110, 1100, 0111, 1101, 1000, 1001, 1011, " &\r
+ "1110)," &\r
+ "EXTEST (0000)," &\r
+ "SAMPLE (0100)," &\r
+ "INTEST (0010)," &\r
+ "IDCODE (0011)," &\r
+ "RUNBIST (1010)";\r
+ \r
+-- Specifies the bit pattern that is loaded into the instruction register when \r
+-- the TAP controller passes through the Capture-IR state. The standard mandates \r
+-- that the two LSBs must be "01". The remaining bits are design specific.\r
+ \r
+ attribute INSTRUCTION_CAPTURE of top: entity is "0001";\r
+ \r
+-- Specifies the bit pattern that is loaded into the DEVICE_ID register during \r
+-- the IDCODE instruction when the TAP controller passes through the Capture-DR \r
+-- state.\r
+ \r
+ attribute IDCODE_REGISTER of top: entity is \r
+ "0000" & \r
+ -- 4-bit version number\r
+ "0101101100111111" & \r
+ -- 16-bit part number\r
+ "00000011111" & \r
+ -- 11-bit identity of the manufacturer\r
+ "1"; \r
+ -- Required by IEEE Std 1149.1\r
+ \r
+-- This section specifies the test data register placed between TDI and TDO for \r
+-- each implemented instruction.\r
+ \r
+ attribute REGISTER_ACCESS of top: entity is \r
+ "BYPASS (BYPASS)," &\r
+ "BOUNDARY (EXTEST, SAMPLE, INTEST)," &\r
+ "DEVICE_ID (IDCODE)," &\r
+ "UTDR1[41] (RUNBIST)";\r
+ \r
+-- Specifies the length of the boundary scan register.\r
+ \r
+ attribute BOUNDARY_LENGTH of top: entity is 374;\r
+ \r
+-- The following list specifies the characteristics of each cell in the boundary \r
+-- scan register from TDI to TDO. The following is a description of the label \r
+-- fields:\r
+-- num : Is the cell number.\r
+-- cell : Is the cell type as defined by the standard.\r
+-- port : Is the design port name. Control cells do not have a port \r
+-- name.\r
+-- function: Is the function of the cell as defined by the standard. Is one \r
+-- of input, output2, output3, bidir, control or controlr.\r
+-- safe : Specifies the value that the BSR cell should be loaded with \r
+-- for safe operation when the software might otherwise choose a \r
+-- random value.\r
+-- ccell : The control cell number. Specifies the control cell that \r
+-- drives the output enable for this port.\r
+-- disval : Specifies the value that is loaded into the control cell to \r
+-- disable the output enable for the corresponding port.\r
+-- rslt : Resulting state. Shows the state of the driver when it is \r
+-- disabled.\r
+ \r
+ attribute BOUNDARY_REGISTER of top: entity is \r
+-- \r
+-- num cell port function safe [ccell disval rslt]\r
+-- \r
+ "373 (BC_1, *, control, 1), " &\r
+ "372 (BC_7, PD13, bidir, X, 373, 1, Z), " &\r
+ "371 (BC_1, *, control, 1), " &\r
+ "370 (BC_7, PD12, bidir, X, 371, 1, Z), " &\r
+ "369 (BC_1, *, control, 1), " &\r
+ "368 (BC_7, PD11, bidir, X, 369, 1, Z), " &\r
+ "367 (BC_1, *, control, 1), " &\r
+ "366 (BC_7, PD19, bidir, X, 367, 1, Z), " &\r
+ "365 (BC_1, *, control, 1), " &\r
+ "364 (BC_7, PD20, bidir, X, 365, 1, Z), " &\r
+ "363 (BC_0, *, internal, X), " &\r
+ "362 (BC_0, *, internal, X), " &\r
+ "361 (BC_1, *, control, 1), " &\r
+ "360 (BC_7, PD21, bidir, X, 361, 1, Z), " &\r
+ "359 (BC_0, *, internal, X), " &\r
+ "358 (BC_0, *, internal, X), " &\r
+ "357 (BC_0, *, internal, X), " &\r
+ "356 (BC_0, *, internal, X), " &\r
+ "355 (BC_1, *, control, 1), " &\r
+ "354 (BC_7, PD22, bidir, X, 355, 1, Z), " &\r
+ "353 (BC_0, *, internal, X), " &\r
+ "352 (BC_0, *, internal, X), " &\r
+ "351 (BC_1, *, control, 1), " &\r
+ "350 (BC_7, PD23, bidir, X, 351, 1, Z), " &\r
+ "349 (BC_0, *, internal, X), " &\r
+ "348 (BC_0, *, internal, X), " &\r
+ "347 (BC_0, *, internal, X), " &\r
+ "346 (BC_0, *, internal, X), " &\r
+ "345 (BC_0, *, internal, X), " &\r
+ "344 (BC_0, *, internal, X), " &\r
+ "343 (BC_0, *, internal, X), " &\r
+ "342 (BC_0, *, internal, X), " &\r
+ "341 (BC_0, *, internal, X), " &\r
+ "340 (BC_0, *, internal, X), " &\r
+ "339 (BC_0, *, internal, X), " &\r
+ "338 (BC_0, *, internal, X), " &\r
+ "337 (BC_0, *, internal, X), " &\r
+ "336 (BC_0, *, internal, X), " &\r
+ "335 (BC_0, *, internal, X), " &\r
+ "334 (BC_0, *, internal, X), " &\r
+ "333 (BC_0, *, internal, X), " &\r
+ "332 (BC_0, *, internal, X), " &\r
+ "331 (BC_0, *, internal, X), " &\r
+ "330 (BC_0, *, internal, X), " &\r
+ "329 (BC_0, *, internal, X), " &\r
+ "328 (BC_0, *, internal, X), " &\r
+ "327 (BC_0, *, internal, X), " &\r
+ "326 (BC_0, *, internal, X), " &\r
+ "325 (BC_0, *, internal, X), " &\r
+ "324 (BC_0, *, internal, X), " &\r
+ "323 (BC_0, *, internal, X), " &\r
+ "322 (BC_0, *, internal, X), " &\r
+ "321 (BC_0, *, internal, X), " &\r
+ "320 (BC_0, *, internal, X), " &\r
+ "319 (BC_1, *, control, 1), " &\r
+ "318 (BC_7, PA18, bidir, X, 319, 1, Z), " &\r
+ "317 (BC_1, *, control, 1), " &\r
+ "316 (BC_7, PA20, bidir, X, 317, 1, Z), " &\r
+ "315 (BC_1, *, control, 1), " &\r
+ "314 (BC_7, PA19, bidir, X, 315, 1, Z), " &\r
+ "313 (BC_1, *, control, 1), " &\r
+ "312 (BC_7, PA21, bidir, X, 313, 1, Z), " &\r
+ "311 (BC_1, *, control, 1), " &\r
+ "310 (BC_7, PA22, bidir, X, 311, 1, Z), " &\r
+ "309 (BC_1, *, control, 1), " &\r
+ "308 (BC_7, PA23, bidir, X, 309, 1, Z), " &\r
+ "307 (BC_1, *, control, 1), " &\r
+ "306 (BC_7, PA24, bidir, X, 307, 1, Z), " &\r
+ "305 (BC_1, *, control, 1), " &\r
+ "304 (BC_7, PA25, bidir, X, 305, 1, Z), " &\r
+ "303 (BC_1, *, control, 1), " &\r
+ "302 (BC_7, PA26, bidir, X, 303, 1, Z), " &\r
+ "301 (BC_1, *, control, 1), " &\r
+ "300 (BC_7, PA27, bidir, X, 301, 1, Z), " &\r
+ "299 (BC_1, *, control, 1), " &\r
+ "298 (BC_7, PA28, bidir, X, 299, 1, Z), " &\r
+ "297 (BC_1, *, control, 1), " &\r
+ "296 (BC_7, PA30, bidir, X, 297, 1, Z), " &\r
+ "295 (BC_1, *, control, 1), " &\r
+ "294 (BC_7, PA29, bidir, X, 295, 1, Z), " &\r
+ "293 (BC_1, *, control, 1), " &\r
+ "292 (BC_7, PA31, bidir, X, 293, 1, Z), " &\r
+ "291 (BC_1, *, control, 1), " &\r
+ "290 (BC_7, PC0, bidir, X, 291, 1, Z), " &\r
+ "289 (BC_0, *, internal, X), " &\r
+ "288 (BC_0, *, internal, X), " &\r
+ "287 (BC_1, *, control, 1), " &\r
+ "286 (BC_7, PC1, bidir, X, 287, 1, Z), " &\r
+ "285 (BC_0, *, internal, X), " &\r
+ "284 (BC_0, *, internal, X), " &\r
+ "283 (BC_0, *, internal, X), " &\r
+ "282 (BC_0, *, internal, X), " &\r
+ "281 (BC_1, *, control, 1), " &\r
+ "280 (BC_7, PC2, bidir, X, 281, 1, Z), " &\r
+ "279 (BC_0, *, internal, X), " &\r
+ "278 (BC_0, *, internal, X), " &\r
+ "277 (BC_0, *, internal, X), " &\r
+ "276 (BC_0, *, internal, X), " &\r
+ "275 (BC_1, *, control, 1), " &\r
+ "274 (BC_7, PC3, bidir, X, 275, 1, Z), " &\r
+ "273 (BC_1, *, control, 1), " &\r
+ "272 (BC_7, PC4, bidir, X, 273, 1, Z), " &\r
+ "271 (BC_0, *, internal, X), " &\r
+ "270 (BC_0, *, internal, X), " &\r
+ "269 (BC_0, *, internal, X), " &\r
+ "268 (BC_0, *, internal, X), " &\r
+ "267 (BC_1, *, control, 1), " &\r
+ "266 (BC_7, PC5, bidir, X, 267, 1, Z), " &\r
+ "265 (BC_1, *, control, 1), " &\r
+ "264 (BC_7, PC7, bidir, X, 265, 1, Z), " &\r
+ "263 (BC_1, *, control, 1), " &\r
+ "262 (BC_7, PC6, bidir, X, 263, 1, Z), " &\r
+ "261 (BC_1, *, control, 1), " &\r
+ "260 (BC_7, PC8, bidir, X, 261, 1, Z), " &\r
+ "259 (BC_0, *, internal, X), " &\r
+ "258 (BC_0, *, internal, X), " &\r
+ "257 (BC_0, *, internal, X), " &\r
+ "256 (BC_0, *, internal, X), " &\r
+ "255 (BC_0, *, internal, X), " &\r
+ "254 (BC_0, *, internal, X), " &\r
+ "253 (BC_0, *, internal, X), " &\r
+ "252 (BC_0, *, internal, X), " &\r
+ "251 (BC_0, *, internal, X), " &\r
+ "250 (BC_0, *, internal, X), " &\r
+ "249 (BC_0, *, internal, X), " &\r
+ "248 (BC_0, *, internal, X), " &\r
+ "247 (BC_0, *, internal, X), " &\r
+ "246 (BC_0, *, internal, X), " &\r
+ "245 (BC_0, *, internal, X), " &\r
+ "244 (BC_0, *, internal, X), " &\r
+ "243 (BC_0, *, internal, X), " &\r
+ "242 (BC_0, *, internal, X), " &\r
+ "241 (BC_0, *, internal, X), " &\r
+ "240 (BC_0, *, internal, X), " &\r
+ "239 (BC_1, *, control, 1), " &\r
+ "238 (BC_7, DDR_D(15), bidir, X, 239, 1, Z), " &\r
+ "237 (BC_1, *, control, 1), " &\r
+ "236 (BC_7, DDR_D(14), bidir, X, 237, 1, Z), " &\r
+ "235 (BC_1, *, control, 1), " &\r
+ "234 (BC_7, DDR_D(13), bidir, X, 235, 1, Z), " &\r
+ "233 (BC_1, *, control, 1), " &\r
+ "232 (BC_7, DDR_D(12), bidir, X, 233, 1, Z), " &\r
+ "231 (BC_1, *, control, 1), " &\r
+ "230 (BC_7, DDR_DQS(1), bidir, X, 231, 1, Z), " &\r
+ "229 (BC_1, *, control, 1), " &\r
+ "228 (BC_7, DDR_D(11), bidir, X, 229, 1, Z), " &\r
+ "227 (BC_1, *, control, 1), " &\r
+ "226 (BC_7, DDR_D(10), bidir, X, 227, 1, Z), " &\r
+ "225 (BC_1, *, control, 1), " &\r
+ "224 (BC_7, DDR_D(9), bidir, X, 225, 1, Z), " &\r
+ "223 (BC_1, *, control, 1), " &\r
+ "222 (BC_7, DDR_D(8), bidir, X, 223, 1, Z), " &\r
+ "221 (BC_0, *, control, 1), " &\r
+ "220 (BC_0, DDR_DQM(1), output3, X, 221, 1, Z), " &\r
+ "219 (BC_0, *, control, 1), " &\r
+ "218 (BC_0, DDR_BA(2), output3, X, 219, 1, Z), " &\r
+ "217 (BC_0, *, control, 1), " &\r
+ "216 (BC_0, DDR_BA(1), output3, X, 217, 1, Z), " &\r
+ "215 (BC_0, *, control, 1), " &\r
+ "214 (BC_0, DDR_BA(0), output3, X, 215, 1, Z), " &\r
+ "213 (BC_0, *, control, 1), " &\r
+ "212 (BC_0, DDR_CKE, output3, X, 213, 1, Z), " &\r
+ "211 (BC_0, *, control, 1), " &\r
+ "210 (BC_0, DDR_CS, output3, X, 211, 1, Z), " &\r
+ "209 (BC_0, *, control, 1), " &\r
+ "208 (BC_0, DDR_A(13), output3, X, 209, 1, Z), " &\r
+ "207 (BC_0, *, control, 1), " &\r
+ "206 (BC_0, DDR_RESETN, output3, X, 207, 1, Z), " &\r
+ "205 (BC_0, *, control, 1), " &\r
+ "204 (BC_0, DDR_A(5), output3, X, 205, 1, Z), " &\r
+ "203 (BC_0, *, control, 1), " &\r
+ "202 (BC_0, DDR_A(6), output3, X, 203, 1, Z), " &\r
+ "201 (BC_0, *, control, 1), " &\r
+ "200 (BC_0, DDR_RAS, output3, X, 201, 1, Z), " &\r
+ "199 (BC_0, *, control, 1), " &\r
+ "198 (BC_0, DDR_CAS, output3, X, 199, 1, Z), " &\r
+ "197 (BC_0, *, control, 1), " &\r
+ "196 (BC_0, DDR_WE, output3, X, 197, 1, Z), " &\r
+ "195 (BC_0, *, control, 1), " &\r
+ "194 (BC_0, DDR_CLK, output3, X, 195, 1, Z), " &\r
+ "193 (BC_0, *, control, 1), " &\r
+ "192 (BC_0, DDR_A(0), output3, X, 193, 1, Z), " &\r
+ "191 (BC_0, *, control, 1), " &\r
+ "190 (BC_0, DDR_A(1), output3, X, 191, 1, Z), " &\r
+ "189 (BC_0, *, control, 1), " &\r
+ "188 (BC_0, DDR_A(2), output3, X, 189, 1, Z), " &\r
+ "187 (BC_0, *, control, 1), " &\r
+ "186 (BC_0, DDR_A(3), output3, X, 187, 1, Z), " &\r
+ "185 (BC_0, *, control, 1), " &\r
+ "184 (BC_0, DDR_A(4), output3, X, 185, 1, Z), " &\r
+ "183 (BC_0, *, control, 1), " &\r
+ "182 (BC_0, DDR_A(12), output3, X, 183, 1, Z), " &\r
+ "181 (BC_0, *, control, 1), " &\r
+ "180 (BC_0, DDR_A(11), output3, X, 181, 1, Z), " &\r
+ "179 (BC_0, *, control, 1), " &\r
+ "178 (BC_0, DDR_A(10), output3, X, 179, 1, Z), " &\r
+ "177 (BC_0, *, control, 1), " &\r
+ "176 (BC_0, DDR_A(9), output3, X, 177, 1, Z), " &\r
+ "175 (BC_0, *, control, 1), " &\r
+ "174 (BC_0, DDR_A(8), output3, X, 175, 1, Z), " &\r
+ "173 (BC_0, *, control, 1), " &\r
+ "172 (BC_0, DDR_A(7), output3, X, 173, 1, Z), " &\r
+ "171 (BC_1, *, control, 1), " &\r
+ "170 (BC_7, DDR_D(7), bidir, X, 171, 1, Z), " &\r
+ "169 (BC_1, *, control, 1), " &\r
+ "168 (BC_7, DDR_D(6), bidir, X, 169, 1, Z), " &\r
+ "167 (BC_1, *, control, 1), " &\r
+ "166 (BC_7, DDR_D(5), bidir, X, 167, 1, Z), " &\r
+ "165 (BC_1, *, control, 1), " &\r
+ "164 (BC_7, DDR_D(4), bidir, X, 165, 1, Z), " &\r
+ "163 (BC_1, *, control, 1), " &\r
+ "162 (BC_7, DDR_DQS(0), bidir, X, 163, 1, Z), " &\r
+ "161 (BC_1, *, control, 1), " &\r
+ "160 (BC_7, DDR_D(3), bidir, X, 161, 1, Z), " &\r
+ "159 (BC_1, *, control, 1), " &\r
+ "158 (BC_7, DDR_D(2), bidir, X, 159, 1, Z), " &\r
+ "157 (BC_1, *, control, 1), " &\r
+ "156 (BC_7, DDR_D(1), bidir, X, 157, 1, Z), " &\r
+ "155 (BC_1, *, control, 1), " &\r
+ "154 (BC_7, DDR_D(0), bidir, X, 155, 1, Z), " &\r
+ "153 (BC_0, *, control, 1), " &\r
+ "152 (BC_0, DDR_DQM(0), output3, X, 153, 1, Z), " &\r
+ "151 (BC_0, *, internal, X), " &\r
+ "150 (BC_0, *, internal, X), " &\r
+ "149 (BC_0, *, internal, X), " &\r
+ "148 (BC_0, *, internal, X), " &\r
+ "147 (BC_0, *, internal, X), " &\r
+ "146 (BC_0, *, internal, X), " &\r
+ "145 (BC_0, *, internal, X), " &\r
+ "144 (BC_0, *, internal, X), " &\r
+ "143 (BC_0, *, internal, X), " &\r
+ "142 (BC_0, *, internal, X), " &\r
+ "141 (BC_0, *, internal, X), " &\r
+ "140 (BC_0, *, internal, X), " &\r
+ "139 (BC_0, *, internal, X), " &\r
+ "138 (BC_0, *, internal, X), " &\r
+ "137 (BC_0, *, internal, X), " &\r
+ "136 (BC_0, *, internal, X), " &\r
+ "135 (BC_0, *, internal, X), " &\r
+ "134 (BC_0, *, internal, X), " &\r
+ "133 (BC_0, *, internal, X), " &\r
+ "132 (BC_0, *, internal, X), " &\r
+ "131 (BC_0, *, internal, X), " &\r
+ "130 (BC_0, *, internal, X), " &\r
+ "129 (BC_0, *, internal, X), " &\r
+ "128 (BC_0, *, internal, X), " &\r
+ "127 (BC_0, *, internal, X), " &\r
+ "126 (BC_0, *, internal, X), " &\r
+ "125 (BC_0, *, internal, X), " &\r
+ "124 (BC_0, *, internal, X), " &\r
+ "123 (BC_0, *, internal, X), " &\r
+ "122 (BC_0, *, internal, X), " &\r
+ "121 (BC_0, *, internal, X), " &\r
+ "120 (BC_0, *, internal, X), " &\r
+ "119 (BC_0, *, internal, X), " &\r
+ "118 (BC_0, *, internal, X), " &\r
+ "117 (BC_0, *, internal, X), " &\r
+ "116 (BC_0, *, internal, X), " &\r
+ "115 (BC_0, *, internal, X), " &\r
+ "114 (BC_0, *, internal, X), " &\r
+ "113 (BC_1, *, control, 1), " &\r
+ "112 (BC_7, PB0, bidir, X, 113, 1, Z), " &\r
+ "111 (BC_1, *, control, 1), " &\r
+ "110 (BC_7, PB2, bidir, X, 111, 1, Z), " &\r
+ "109 (BC_1, *, control, 1), " &\r
+ "108 (BC_7, PB1, bidir, X, 109, 1, Z), " &\r
+ "107 (BC_1, *, control, 1), " &\r
+ "106 (BC_7, PB3, bidir, X, 107, 1, Z), " &\r
+ "105 (BC_1, *, control, 1), " &\r
+ "104 (BC_7, PB4, bidir, X, 105, 1, Z), " &\r
+ "103 (BC_1, *, control, 1), " &\r
+ "102 (BC_7, PB5, bidir, X, 103, 1, Z), " &\r
+ "101 (BC_1, *, control, 1), " &\r
+ "100 (BC_7, PB6, bidir, X, 101, 1, Z), " &\r
+ "99 (BC_1, *, control, 1), " &\r
+ "98 (BC_7, PB8, bidir, X, 99, 1, Z), " &\r
+ "97 (BC_1, *, control, 1), " &\r
+ "96 (BC_7, PB7, bidir, X, 97, 1, Z), " &\r
+ "95 (BC_1, *, control, 1), " &\r
+ "94 (BC_7, PB10, bidir, X, 95, 1, Z), " &\r
+ "93 (BC_1, *, control, 1), " &\r
+ "92 (BC_7, PB9, bidir, X, 93, 1, Z), " &\r
+ "91 (BC_1, *, control, 1), " &\r
+ "90 (BC_7, PB11, bidir, X, 91, 1, Z), " &\r
+ "89 (BC_1, *, control, 1), " &\r
+ "88 (BC_7, PB12, bidir, X, 89, 1, Z), " &\r
+ "87 (BC_1, *, control, 1), " &\r
+ "86 (BC_7, PB14, bidir, X, 87, 1, Z), " &\r
+ "85 (BC_1, *, control, 1), " &\r
+ "84 (BC_7, PB13, bidir, X, 85, 1, Z), " &\r
+ "83 (BC_1, *, control, 1), " &\r
+ "82 (BC_7, PB15, bidir, X, 83, 1, Z), " &\r
+ "81 (BC_1, *, control, 1), " &\r
+ "80 (BC_7, PB16, bidir, X, 81, 1, Z), " &\r
+ "79 (BC_1, *, control, 1), " &\r
+ "78 (BC_7, PB17, bidir, X, 79, 1, Z), " &\r
+ "77 (BC_1, *, control, 1), " &\r
+ "76 (BC_7, PB19, bidir, X, 77, 1, Z), " &\r
+ "75 (BC_1, *, control, 1), " &\r
+ "74 (BC_7, PB18, bidir, X, 75, 1, Z), " &\r
+ "73 (BC_1, *, control, 1), " &\r
+ "72 (BC_7, PB20, bidir, X, 73, 1, Z), " &\r
+ "71 (BC_1, *, control, 1), " &\r
+ "70 (BC_7, PB21, bidir, X, 71, 1, Z), " &\r
+ "69 (BC_1, *, control, 1), " &\r
+ "68 (BC_7, PB23, bidir, X, 69, 1, Z), " &\r
+ "67 (BC_1, *, control, 1), " &\r
+ "66 (BC_7, PB22, bidir, X, 67, 1, Z), " &\r
+ "65 (BC_1, *, control, 1), " &\r
+ "64 (BC_7, PB25, bidir, X, 65, 1, Z), " &\r
+ "63 (BC_1, *, control, 1), " &\r
+ "62 (BC_7, PB24, bidir, X, 63, 1, Z), " &\r
+ "61 (BC_1, *, control, 1), " &\r
+ "60 (BC_7, PB26, bidir, X, 61, 1, Z), " &\r
+ "59 (BC_1, *, control, 1), " &\r
+ "58 (BC_7, PB28, bidir, X, 59, 1, Z), " &\r
+ "57 (BC_1, *, control, 1), " &\r
+ "56 (BC_7, PB27, bidir, X, 57, 1, Z), " &\r
+ "55 (BC_1, *, control, 1), " &\r
+ "54 (BC_7, PB30, bidir, X, 55, 1, Z), " &\r
+ "53 (BC_1, *, control, 1), " &\r
+ "52 (BC_7, PB29, bidir, X, 53, 1, Z), " &\r
+ "51 (BC_1, *, control, 1), " &\r
+ "50 (BC_7, PB31, bidir, X, 51, 1, Z), " &\r
+ "49 (BC_0, *, internal, X), " &\r
+ "48 (BC_0, *, internal, X), " &\r
+ "47 (BC_0, *, internal, X), " &\r
+ "46 (BC_0, *, internal, X), " &\r
+ "45 (BC_0, *, internal, X), " &\r
+ "44 (BC_0, *, internal, X), " &\r
+ "43 (BC_0, *, internal, X), " &\r
+ "42 (BC_0, *, internal, X), " &\r
+ "41 (BC_0, *, internal, X), " &\r
+ "40 (BC_0, *, internal, X), " &\r
+ "39 (BC_0, *, internal, X), " &\r
+ "38 (BC_0, *, internal, X), " &\r
+ "37 (BC_0, *, internal, X), " &\r
+ "36 (BC_0, *, internal, X), " &\r
+ "35 (BC_0, *, internal, X), " &\r
+ "34 (BC_0, *, internal, X), " &\r
+ "33 (BC_0, *, internal, X), " &\r
+ "32 (BC_0, *, internal, X), " &\r
+ "31 (BC_0, *, internal, X), " &\r
+ "30 (BC_0, *, internal, X), " &\r
+ "29 (BC_0, *, internal, X), " &\r
+ "28 (BC_0, *, internal, X), " &\r
+ "27 (BC_0, *, internal, X), " &\r
+ "26 (BC_0, *, internal, X), " &\r
+ "25 (BC_0, *, internal, X), " &\r
+ "24 (BC_0, *, internal, X), " &\r
+ "23 (BC_0, *, internal, X), " &\r
+ "22 (BC_0, *, internal, X), " &\r
+ "21 (BC_0, *, internal, X), " &\r
+ "20 (BC_0, *, internal, X), " &\r
+ "19 (BC_0, *, internal, X), " &\r
+ "18 (BC_0, *, internal, X), " &\r
+ "17 (BC_0, *, internal, X), " &\r
+ "16 (BC_0, *, internal, X), " &\r
+ "15 (BC_1, *, control, 1), " &\r
+ "14 (BC_7, PD10, bidir, X, 15, 1, Z), " &\r
+ "13 (BC_1, *, control, 1), " &\r
+ "12 (BC_7, PD9, bidir, X, 13, 1, Z), " &\r
+ "11 (BC_1, *, control, 1), " &\r
+ "10 (BC_7, PD8, bidir, X, 11, 1, Z), " &\r
+ "9 (BC_1, *, control, 1), " &\r
+ "8 (BC_7, PD7, bidir, X, 9, 1, Z), " &\r
+ "7 (BC_0, *, internal, X), " &\r
+ "6 (BC_0, *, internal, X), " &\r
+ "5 (BC_0, *, internal, X), " &\r
+ "4 (BC_0, *, internal, X), " &\r
+ "3 (BC_0, *, internal, X), " &\r
+ "2 (BC_0, *, internal, X), " &\r
+ "1 (BC_0, *, internal, X), " &\r
+ "0 (BC_0, *, internal, X) ";\r
+ \r
+ end top;\r
--- /dev/null
+-- *****************************************************************************\r
+\r
+-- BSDL file for design top\r
+\r
+-- Created by Synopsys Version I-2013.12-SP3 (Apr 18, 2014)\r
+\r
+-- Designer: \r
+-- Company: \r
+\r
+-- Date: Thu Feb 5 22:56:11 2015\r
+\r
+-- *****************************************************************************\r
+\r
+\r
+ entity top is\r
+ \r
+-- This section identifies the default device package selected.\r
+ \r
+ generic (PHYSICAL_PIN_MAP: string:= "BGA256");\r
+ \r
+-- This section declares all the ports in the design.\r
+ \r
+ port ( \r
+ PD14 : in bit;\r
+ PD15 : in bit;\r
+ PD17 : in bit;\r
+ PD18 : in bit;\r
+ PA0 : inout bit;\r
+ PA1 : inout bit;\r
+ PA10 : inout bit;\r
+ PA11 : inout bit;\r
+ PA12 : inout bit;\r
+ PA13 : inout bit;\r
+ PA14 : inout bit;\r
+ PA15 : inout bit;\r
+ PA16 : inout bit;\r
+ PA17 : inout bit;\r
+ PA18 : inout bit;\r
+ PA19 : inout bit;\r
+ PA2 : inout bit;\r
+ PA20 : inout bit;\r
+ PA21 : inout bit;\r
+ PA22 : inout bit;\r
+ PA23 : inout bit;\r
+ PA24 : inout bit;\r
+ PA25 : inout bit;\r
+ PA26 : inout bit;\r
+ PA27 : inout bit;\r
+ PA28 : inout bit;\r
+ PA29 : inout bit;\r
+ PA3 : inout bit;\r
+ PA30 : inout bit;\r
+ PA31 : inout bit;\r
+ PA4 : inout bit;\r
+ PA5 : inout bit;\r
+ PA6 : inout bit;\r
+ PA7 : inout bit;\r
+ PA8 : inout bit;\r
+ PA9 : inout bit;\r
+ PB0 : inout bit;\r
+ PB1 : inout bit;\r
+ PB10 : inout bit;\r
+ PB11 : inout bit;\r
+ PB12 : inout bit;\r
+ PB13 : inout bit;\r
+ PB14 : inout bit;\r
+ PB15 : inout bit;\r
+ PB16 : inout bit;\r
+ PB17 : inout bit;\r
+ PB18 : inout bit;\r
+ PB19 : inout bit;\r
+ PB2 : inout bit;\r
+ PB20 : inout bit;\r
+ PB21 : inout bit;\r
+ PB22 : inout bit;\r
+ PB23 : inout bit;\r
+ PB24 : inout bit;\r
+ PB25 : inout bit;\r
+ PB26 : inout bit;\r
+ PB27 : inout bit;\r
+ PB28 : inout bit;\r
+ PB29 : inout bit;\r
+ PB3 : inout bit;\r
+ PB30 : inout bit;\r
+ PB31 : inout bit;\r
+ PB4 : inout bit;\r
+ PB5 : inout bit;\r
+ PB6 : inout bit;\r
+ PB7 : inout bit;\r
+ PB8 : inout bit;\r
+ PB9 : inout bit;\r
+ PC0 : inout bit;\r
+ PC1 : inout bit;\r
+ -- PC10 : linkage bit; -- NC(No Connect) Port\r
+ -- PC11 : linkage bit; -- NC Port\r
+ -- PC12 : linkage bit; -- NC Port\r
+ -- PC13 : linkage bit; -- NC Port\r
+ -- PC14 : linkage bit; -- NC Port\r
+ -- PC15 : linkage bit; -- NC Port\r
+ -- PC16 : linkage bit; -- NC Port\r
+ -- PC17 : linkage bit; -- NC Port\r
+ -- PC18 : linkage bit; -- NC Port\r
+ -- PC19 : linkage bit; -- NC Port\r
+ PC2 : inout bit;\r
+ -- PC20 : linkage bit; -- NC Port\r
+ -- PC21 : linkage bit; -- NC Port\r
+ -- PC22 : linkage bit; -- NC Port\r
+ -- PC23 : linkage bit; -- NC Port\r
+ -- PC24 : linkage bit; -- NC Port\r
+ -- PC25 : linkage bit; -- NC Port\r
+ -- PC26 : linkage bit; -- NC Port\r
+ -- PC27 : linkage bit; -- NC Port\r
+ -- PC28 : linkage bit; -- NC Port\r
+ -- PC29 : linkage bit; -- NC Port\r
+ PC3 : inout bit;\r
+ -- PC30 : linkage bit; -- NC Port\r
+ -- PC31 : linkage bit; -- NC Port\r
+ PC4 : inout bit;\r
+ PC5 : inout bit;\r
+ PC6 : inout bit;\r
+ PC7 : inout bit;\r
+ PC8 : inout bit;\r
+ -- PC9 : linkage bit; -- NC Port\r
+ PD0 : inout bit;\r
+ PD1 : inout bit;\r
+ PD10 : inout bit;\r
+ PD11 : inout bit;\r
+ PD12 : inout bit;\r
+ PD13 : inout bit;\r
+ PD19 : inout bit;\r
+ PD2 : inout bit;\r
+ PD20 : inout bit;\r
+ PD21 : inout bit;\r
+ PD22 : inout bit;\r
+ PD23 : inout bit;\r
+ PD24 : inout bit;\r
+ PD25 : inout bit;\r
+ PD26 : inout bit;\r
+ PD27 : inout bit;\r
+ PD28 : inout bit;\r
+ PD29 : inout bit;\r
+ PD3 : inout bit;\r
+ PD30 : inout bit;\r
+ PD31 : inout bit;\r
+ PD4 : inout bit;\r
+ PD5 : inout bit;\r
+ PD6 : inout bit;\r
+ PD7 : inout bit;\r
+ PD8 : inout bit;\r
+ PD9 : inout bit;\r
+ DDR_D : inout bit_vector (0 to 31);\r
+ DDR_DQS : inout bit_vector (0 to 3);\r
+ DDR_DQSN : inout bit_vector (0 to 3);\r
+ DDR_CAS : out bit;\r
+ DDR_CKE : out bit;\r
+ DDR_CLK : out bit;\r
+ DDR_CLKN : out bit;\r
+ DDR_CS : out bit;\r
+ DDR_RAS : out bit;\r
+ DDR_RESETN : out bit;\r
+ DDR_WE : out bit;\r
+ PD16 : out bit;\r
+ DDR_A : out bit_vector (0 to 13);\r
+ DDR_BA : out bit_vector (0 to 2);\r
+ DDR_DQM : out bit_vector (0 to 3);\r
+ -- ADVREFN : linkage bit;\r
+ ADVREFP : linkage bit;\r
+ CLK_AUDIO : linkage bit;\r
+ COMPN : linkage bit;\r
+ COMPP : linkage bit;\r
+ DDR_CAL : linkage bit;\r
+ DDR_VREF : linkage bit; -- DDR_VREFB0 : linkage bit;\r
+ -- DDR_VREFB1 : linkage bit;\r
+ -- DDR_VREFB2 : linkage bit;\r
+ -- DDR_VREFB3 : linkage bit;\r
+ -- DDR_VREFCM : linkage bit;\r
+ HHSDMA : linkage bit;\r
+ HHSDMB : linkage bit;\r
+ HHSDMSTRC : linkage bit;\r
+ HHSDPA : linkage bit;\r
+ HHSDPB : linkage bit;\r
+ HHSDPDATC : linkage bit;\r
+ JTAGSEL : in bit;\r
+ NRST : linkage bit;\r
+ RXD : linkage bit;\r
+ SDCAL : linkage bit;\r
+ SHDN : linkage bit;\r
+ TST : in bit;\r
+ VBG : linkage bit;\r
+ WKUP : linkage bit;\r
+ XIN : linkage bit;\r
+ XIN32 : linkage bit;\r
+ XOUT : linkage bit;\r
+ XOUT32 : linkage bit;\r
+ -- tst_drst_ana : linkage bit; -- NC Port\r
+ -- tst_drst_ddr : linkage bit; -- NC Port\r
+ -- tst_drst_iop0 : linkage bit; -- NC Port\r
+ -- tst_drst_iop1 : linkage bit; -- NC Port\r
+ -- tst_drst_iop2 : linkage bit; -- NC Port\r
+ -- tst_drst_isi : linkage bit; -- NC Port\r
+ -- tst_drst_osc : linkage bit; -- NC Port\r
+ -- tst_drst_sdhc : linkage bit; -- NC Port\r
+ -- tst_lft_plla : linkage bit; -- NC Port\r
+ -- tst_lft_utmi : linkage bit; -- NC Port\r
+ -- tst_por_1v2 : linkage bit; -- NC Port\r
+ -- tst_por_1v8 : linkage bit; -- NC Port\r
+ -- tst_por_bu : linkage bit; -- NC Port\r
+ -- tst_psw_bu : linkage bit; -- NC Port\r
+ -- tst_psw_fuse : linkage bit; -- NC Port\r
+ PIOBU : linkage bit_vector (0 to 1)\r
+ );\r
+ \r
+ use STD_1149_1_1994.all;\r
+ \r
+ attribute COMPONENT_CONFORMANCE of top: entity is "STD_1149_1_1993";\r
+ \r
+ attribute PIN_MAP of top: entity is PHYSICAL_PIN_MAP;\r
+ \r
+-- This section specifies the pin map for each port. This information is \r
+-- extracted from the port-to-pin map file that was read in using the \r
+-- "read_pin_map" command.\r
+ \r
+ constant BGA256: PIN_MAP_STRING := \r
+ "PD14 : K6," &\r
+ "PD15 : K4," &\r
+ "PD17 : K2," &\r
+ "PD18 : L5," &\r
+ "PA0 : R10," &\r
+ "PA1 : R9," &\r
+ "PA10 : U13," &\r
+ "PA11 : R14," &\r
+ "PA12 : N13," &\r
+ "PA13 : P14," &\r
+ "PA14 : P17," &\r
+ "PA15 : R18," &\r
+ "PA16 : N15," &\r
+ "PA17 : P18," &\r
+ "PA18 : M9," &\r
+ "PA19 : V13," &\r
+ "PA2 : U11," &\r
+ "PA20 : L9," &\r
+ "PA21 : M10," &\r
+ "PA22 : V14," &\r
+ "PA23 : U14," &\r
+ "PA24 : R13," &\r
+ "PA25 : U15," &\r
+ "PA26 : L10," &\r
+ "PA27 : V17," &\r
+ "PA28 : U16," &\r
+ "PA29 : U17," &\r
+ "PA3 : P10," &\r
+ "PA30 : V18," &\r
+ "PA31 : U18," &\r
+ "PA4 : P11," &\r
+ "PA5 : V11," &\r
+ "PA6 : U12," &\r
+ "PA7 : V12," &\r
+ "PA8 : N11," &\r
+ "PA9 : P12," &\r
+ "PB0 : G9," &\r
+ "PB1 : A7," &\r
+ "PB10 : D6," &\r
+ "PB11 : A4," &\r
+ "PB12 : B3," &\r
+ "PB13 : A3," &\r
+ "PB14 : B4," &\r
+ "PB15 : G8," &\r
+ "PB16 : E5," &\r
+ "PB17 : G7," &\r
+ "PB18 : A2," &\r
+ "PB19 : H7," &\r
+ "PB2 : B7," &\r
+ "PB20 : A1," &\r
+ "PB21 : D2," &\r
+ "PB22 : G5," &\r
+ "PB23 : C2," &\r
+ "PB24 : F4," &\r
+ "PB25 : C1," &\r
+ "PB26 : E4," &\r
+ "PB27 : F1," &\r
+ "PB28 : D1," &\r
+ "PB29 : F2," &\r
+ "PB3 : B6," &\r
+ "PB30 : E2," &\r
+ "PB31 : E1," &\r
+ "PB4 : A6," &\r
+ "PB5 : D7," &\r
+ "PB6 : B5," &\r
+ "PB7 : A5," &\r
+ "PB8 : E7," &\r
+ "PB9 : F6," &\r
+ "PC0 : R15," &\r
+ "PC1 : M11," &\r
+ "PC2 : P15," &\r
+ "PC3 : K9," &\r
+ "PC4 : K10," &\r
+ "PC5 : L11," &\r
+ "PC6 : L12," &\r
+ "PC7 : M12," &\r
+ "PC8 : K11," &\r
+ "PD0 : E9," &\r
+ "PD1 : F8," &\r
+ "PD10 : G2," &\r
+ "PD11 : H2," &\r
+ "PD12 : K5," &\r
+ "PD13 : J5," &\r
+ "PD19 : L4," &\r
+ "PD2 : F9," &\r
+ "PD20 : M1," &\r
+ "PD21 : M2," &\r
+ "PD22 : M4," &\r
+ "PD23 : P1," &\r
+ "PD24 : L6," &\r
+ "PD25 : M5," &\r
+ "PD26 : N1," &\r
+ "PD27 : N2," &\r
+ "PD28 : P2," &\r
+ "PD29 : R1," &\r
+ "PD3 : J4," &\r
+ "PD30 : N4," &\r
+ "PD31 : T1," &\r
+ "PD4 : H6," &\r
+ "PD5 : H1," &\r
+ "PD6 : G4," &\r
+ "PD7 : H5," &\r
+ "PD8 : G1," &\r
+ "PD9 : H4," &\r
+ "DDR_D : (B12, B13, D13, A13, A15, D14, B15, B16, G18, K17, " &\r
+ "J13, H15, J15, J14, K13, K18, A8, B9, D9, A9, B11, D10, A11, A12, " &\r
+ "L18, K15, K14, M18, N17, M14, M15, N18)," &\r
+ "DDR_DQS : (A14, H18, A10, M17)," &\r
+ "DDR_DQSN : (B14, J18, B10, L17)," &\r
+ "DDR_CAS : E17," &\r
+ "DDR_CKE : F18," &\r
+ "DDR_CLK : C18," &\r
+ "DDR_CLKN : C17," &\r
+ "DDR_CS : J12," &\r
+ "DDR_RAS : E18," &\r
+ "DDR_RESETN : F17," &\r
+ "DDR_WE : D18," &\r
+ "PD16 : K1," &\r
+ "DDR_A : (D17, A17, A18, F15, G12, H12, F13, H10, A16, E12, " &\r
+ "H11, J10, D15, J11)," &\r
+ "DDR_BA : (H13, K12, H17)," &\r
+ "DDR_DQM : (D11, H14, B8, L13)," &\r
+ "ADVREFP : P5," &\r
+ "CLK_AUDIO : M8," &\r
+ "COMPN : V4," &\r
+ "COMPP : V3," &\r
+ "DDR_CAL : G17," &\r
+ "HHSDMA : V8," &\r
+ "HHSDMB : V9," &\r
+ "HHSDMSTRC : V10," &\r
+ "HHSDPA : U8," &\r
+ "HHSDPB : U9," &\r
+ "HHSDPDATC : U10," &\r
+ "JTAGSEL : V2," &\r
+ "NRST : V1," &\r
+ "RXD : U2," &\r
+ "SDCAL : N10," &\r
+ "SHDN : U1," &\r
+ "TST : P4," &\r
+ "VBG : R7," &\r
+ "WKUP : R5," &\r
+ "XIN : V7," &\r
+ "XIN32 : T2," &\r
+ "XOUT : V6," &\r
+ "XOUT32 : R2," &\r
+ "PIOBU : (R6, R4)";\r
+ \r
+-- This section specifies the differential IO port groupings.\r
+ \r
+ attribute PORT_GROUPING of top: entity is \r
+ "Differential_Voltage ( " &\r
+ "(DDR_CLK,DDR_CLKN))";\r
+\r
+-- This section specifies the TAP ports. For the TAP TCK port, the parameters in \r
+-- the brackets are:\r
+-- First Field : Maximum TCK frequency.\r
+-- Second Field: Allowable states TCK may be stopped in.\r
+ \r
+ attribute TAP_SCAN_CLOCK of PD14: signal is (10.0e6, BOTH);\r
+ attribute TAP_SCAN_IN of PD15: signal is true;\r
+ attribute TAP_SCAN_MODE of PD17: signal is true;\r
+ attribute TAP_SCAN_OUT of PD16: signal is true;\r
+ attribute TAP_SCAN_RESET of PD18: signal is true;\r
+ \r
+-- Specifies the compliance enable patterns for the design. It lists a set of \r
+-- design ports and the values that they should be set to, in order to enable \r
+-- compliance to IEEE Std 1149.1\r
+ \r
+ attribute COMPLIANCE_PATTERNS of top: entity is \r
+ "(JTAGSEL, TST) (10)";\r
+ \r
+-- Specifies the number of bits in the instruction register.\r
+ \r
+ attribute INSTRUCTION_LENGTH of top: entity is 4;\r
+ \r
+-- Specifies the boundary-scan instructions implemented in the design and their \r
+-- opcodes.\r
+ \r
+ attribute INSTRUCTION_OPCODE of top: entity is \r
+ "BYPASS (1111, 0001, 0101, 0110, 1100, 0111, 1101, 1000, 1001, 1011, " &\r
+ "1110)," &\r
+ "EXTEST (0000)," &\r
+ "SAMPLE (0100)," &\r
+ "INTEST (0010)," &\r
+ "IDCODE (0011)," &\r
+ "RUNBIST (1010)";\r
+ \r
+-- Specifies the bit pattern that is loaded into the instruction register when \r
+-- the TAP controller passes through the Capture-IR state. The standard mandates \r
+-- that the two LSBs must be "01". The remaining bits are design specific.\r
+ \r
+ attribute INSTRUCTION_CAPTURE of top: entity is "0001";\r
+ \r
+-- Specifies the bit pattern that is loaded into the DEVICE_ID register during \r
+-- the IDCODE instruction when the TAP controller passes through the Capture-DR \r
+-- state.\r
+ \r
+ attribute IDCODE_REGISTER of top: entity is \r
+ "0000" & \r
+ -- 4-bit version number\r
+ "0101101100111111" & \r
+ -- 16-bit part number\r
+ "00000011111" & \r
+ -- 11-bit identity of the manufacturer\r
+ "1"; \r
+ -- Required by IEEE Std 1149.1\r
+ \r
+-- This section specifies the test data register placed between TDI and TDO for \r
+-- each implemented instruction.\r
+ \r
+ attribute REGISTER_ACCESS of top: entity is \r
+ "BYPASS (BYPASS)," &\r
+ "BOUNDARY (EXTEST, SAMPLE, INTEST)," &\r
+ "DEVICE_ID (IDCODE)," &\r
+ "UTDR1[41] (RUNBIST)";\r
+ \r
+-- Specifies the length of the boundary scan register.\r
+ \r
+ attribute BOUNDARY_LENGTH of top: entity is 374;\r
+ \r
+-- The following list specifies the characteristics of each cell in the boundary \r
+-- scan register from TDI to TDO. The following is a description of the label \r
+-- fields:\r
+-- num : Is the cell number.\r
+-- cell : Is the cell type as defined by the standard.\r
+-- port : Is the design port name. Control cells do not have a port \r
+-- name.\r
+-- function: Is the function of the cell as defined by the standard. Is one \r
+-- of input, output2, output3, bidir, control or controlr.\r
+-- safe : Specifies the value that the BSR cell should be loaded with \r
+-- for safe operation when the software might otherwise choose a \r
+-- random value.\r
+-- ccell : The control cell number. Specifies the control cell that \r
+-- drives the output enable for this port.\r
+-- disval : Specifies the value that is loaded into the control cell to \r
+-- disable the output enable for the corresponding port.\r
+-- rslt : Resulting state. Shows the state of the driver when it is \r
+-- disabled.\r
+ \r
+ attribute BOUNDARY_REGISTER of top: entity is \r
+-- \r
+-- num cell port function safe [ccell disval rslt]\r
+-- \r
+ "373 (BC_1, *, control, 1), " &\r
+ "372 (BC_7, PD13, bidir, X, 373, 1, Z), " &\r
+ "371 (BC_1, *, control, 1), " &\r
+ "370 (BC_7, PD12, bidir, X, 371, 1, Z), " &\r
+ "369 (BC_1, *, control, 1), " &\r
+ "368 (BC_7, PD11, bidir, X, 369, 1, Z), " &\r
+ "367 (BC_1, *, control, 1), " &\r
+ "366 (BC_7, PD19, bidir, X, 367, 1, Z), " &\r
+ "365 (BC_1, *, control, 1), " &\r
+ "364 (BC_7, PD20, bidir, X, 365, 1, Z), " &\r
+ "363 (BC_1, *, control, 1), " &\r
+ "362 (BC_7, PD24, bidir, X, 363, 1, Z), " &\r
+ "361 (BC_1, *, control, 1), " &\r
+ "360 (BC_7, PD21, bidir, X, 361, 1, Z), " &\r
+ "359 (BC_1, *, control, 1), " &\r
+ "358 (BC_7, PD25, bidir, X, 359, 1, Z), " &\r
+ "357 (BC_1, *, control, 1), " &\r
+ "356 (BC_7, PD26, bidir, X, 357, 1, Z), " &\r
+ "355 (BC_1, *, control, 1), " &\r
+ "354 (BC_7, PD22, bidir, X, 355, 1, Z), " &\r
+ "353 (BC_1, *, control, 1), " &\r
+ "352 (BC_7, PD27, bidir, X, 353, 1, Z), " &\r
+ "351 (BC_1, *, control, 1), " &\r
+ "350 (BC_7, PD23, bidir, X, 351, 1, Z), " &\r
+ "349 (BC_1, *, control, 1), " &\r
+ "348 (BC_7, PD28, bidir, X, 349, 1, Z), " &\r
+ "347 (BC_1, *, control, 1), " &\r
+ "346 (BC_7, PD30, bidir, X, 347, 1, Z), " &\r
+ "345 (BC_1, *, control, 1), " &\r
+ "344 (BC_7, PD29, bidir, X, 345, 1, Z), " &\r
+ "343 (BC_1, *, control, 1), " &\r
+ "342 (BC_7, PD31, bidir, X, 343, 1, Z), " &\r
+ "341 (BC_1, *, control, 1), " &\r
+ "340 (BC_7, PA0, bidir, X, 341, 1, Z), " &\r
+ "339 (BC_1, *, control, 1), " &\r
+ "338 (BC_7, PA1, bidir, X, 339, 1, Z), " &\r
+ "337 (BC_1, *, control, 1), " &\r
+ "336 (BC_7, PA2, bidir, X, 337, 1, Z), " &\r
+ "335 (BC_1, *, control, 1), " &\r
+ "334 (BC_7, PA3, bidir, X, 335, 1, Z), " &\r
+ "333 (BC_1, *, control, 1), " &\r
+ "332 (BC_7, PA4, bidir, X, 333, 1, Z), " &\r
+ "331 (BC_1, *, control, 1), " &\r
+ "330 (BC_7, PA5, bidir, X, 331, 1, Z), " &\r
+ "329 (BC_1, *, control, 1), " &\r
+ "328 (BC_7, PA6, bidir, X, 329, 1, Z), " &\r
+ "327 (BC_1, *, control, 1), " &\r
+ "326 (BC_7, PA7, bidir, X, 327, 1, Z), " &\r
+ "325 (BC_1, *, control, 1), " &\r
+ "324 (BC_7, PA8, bidir, X, 325, 1, Z), " &\r
+ "323 (BC_1, *, control, 1), " &\r
+ "322 (BC_7, PA9, bidir, X, 323, 1, Z), " &\r
+ "321 (BC_1, *, control, 1), " &\r
+ "320 (BC_7, PA10, bidir, X, 321, 1, Z), " &\r
+ "319 (BC_1, *, control, 1), " &\r
+ "318 (BC_7, PA18, bidir, X, 319, 1, Z), " &\r
+ "317 (BC_1, *, control, 1), " &\r
+ "316 (BC_7, PA20, bidir, X, 317, 1, Z), " &\r
+ "315 (BC_1, *, control, 1), " &\r
+ "314 (BC_7, PA19, bidir, X, 315, 1, Z), " &\r
+ "313 (BC_1, *, control, 1), " &\r
+ "312 (BC_7, PA21, bidir, X, 313, 1, Z), " &\r
+ "311 (BC_1, *, control, 1), " &\r
+ "310 (BC_7, PA22, bidir, X, 311, 1, Z), " &\r
+ "309 (BC_1, *, control, 1), " &\r
+ "308 (BC_7, PA23, bidir, X, 309, 1, Z), " &\r
+ "307 (BC_1, *, control, 1), " &\r
+ "306 (BC_7, PA24, bidir, X, 307, 1, Z), " &\r
+ "305 (BC_1, *, control, 1), " &\r
+ "304 (BC_7, PA25, bidir, X, 305, 1, Z), " &\r
+ "303 (BC_1, *, control, 1), " &\r
+ "302 (BC_7, PA26, bidir, X, 303, 1, Z), " &\r
+ "301 (BC_1, *, control, 1), " &\r
+ "300 (BC_7, PA27, bidir, X, 301, 1, Z), " &\r
+ "299 (BC_1, *, control, 1), " &\r
+ "298 (BC_7, PA28, bidir, X, 299, 1, Z), " &\r
+ "297 (BC_1, *, control, 1), " &\r
+ "296 (BC_7, PA30, bidir, X, 297, 1, Z), " &\r
+ "295 (BC_1, *, control, 1), " &\r
+ "294 (BC_7, PA29, bidir, X, 295, 1, Z), " &\r
+ "293 (BC_1, *, control, 1), " &\r
+ "292 (BC_7, PA31, bidir, X, 293, 1, Z), " &\r
+ "291 (BC_1, *, control, 1), " &\r
+ "290 (BC_7, PC0, bidir, X, 291, 1, Z), " &\r
+ "289 (BC_1, *, control, 1), " &\r
+ "288 (BC_7, PA11, bidir, X, 289, 1, Z), " &\r
+ "287 (BC_1, *, control, 1), " &\r
+ "286 (BC_7, PC1, bidir, X, 287, 1, Z), " &\r
+ "285 (BC_1, *, control, 1), " &\r
+ "284 (BC_7, PA13, bidir, X, 285, 1, Z), " &\r
+ "283 (BC_1, *, control, 1), " &\r
+ "282 (BC_7, PA12, bidir, X, 283, 1, Z), " &\r
+ "281 (BC_1, *, control, 1), " &\r
+ "280 (BC_7, PC2, bidir, X, 281, 1, Z), " &\r
+ "279 (BC_1, *, control, 1), " &\r
+ "278 (BC_7, PA14, bidir, X, 279, 1, Z), " &\r
+ "277 (BC_1, *, control, 1), " &\r
+ "276 (BC_7, PA15, bidir, X, 277, 1, Z), " &\r
+ "275 (BC_1, *, control, 1), " &\r
+ "274 (BC_7, PC3, bidir, X, 275, 1, Z), " &\r
+ "273 (BC_1, *, control, 1), " &\r
+ "272 (BC_7, PC4, bidir, X, 273, 1, Z), " &\r
+ "271 (BC_1, *, control, 1), " &\r
+ "270 (BC_7, PA16, bidir, X, 271, 1, Z), " &\r
+ "269 (BC_1, *, control, 1), " &\r
+ "268 (BC_7, PA17, bidir, X, 269, 1, Z), " &\r
+ "267 (BC_1, *, control, 1), " &\r
+ "266 (BC_7, PC5, bidir, X, 267, 1, Z), " &\r
+ "265 (BC_1, *, control, 1), " &\r
+ "264 (BC_7, PC7, bidir, X, 265, 1, Z), " &\r
+ "263 (BC_1, *, control, 1), " &\r
+ "262 (BC_7, PC6, bidir, X, 263, 1, Z), " &\r
+ "261 (BC_1, *, control, 1), " &\r
+ "260 (BC_7, PC8, bidir, X, 261, 1, Z), " &\r
+ "259 (BC_1, *, control, 1), " &\r
+ "258 (BC_7, DDR_D(31), bidir, X, 259, 1, Z), " &\r
+ "257 (BC_1, *, control, 1), " &\r
+ "256 (BC_7, DDR_D(30), bidir, X, 257, 1, Z), " &\r
+ "255 (BC_1, *, control, 1), " &\r
+ "254 (BC_7, DDR_D(29), bidir, X, 255, 1, Z), " &\r
+ "253 (BC_1, *, control, 1), " &\r
+ "252 (BC_7, DDR_D(28), bidir, X, 253, 1, Z), " &\r
+ "251 (BC_1, *, control, 1), " &\r
+ "250 (BC_7, DDR_DQS(3), bidir, X, 251, 1, Z), " &\r
+ "249 (BC_1, *, control, 1), " &\r
+ "248 (BC_7, DDR_D(27), bidir, X, 249, 1, Z), " &\r
+ "247 (BC_1, *, control, 1), " &\r
+ "246 (BC_7, DDR_D(26), bidir, X, 247, 1, Z), " &\r
+ "245 (BC_1, *, control, 1), " &\r
+ "244 (BC_7, DDR_D(25), bidir, X, 245, 1, Z), " &\r
+ "243 (BC_1, *, control, 1), " &\r
+ "242 (BC_7, DDR_D(24), bidir, X, 243, 1, Z), " &\r
+ "241 (BC_0, *, control, 1), " &\r
+ "240 (BC_0, DDR_DQM(3), output3, X, 241, 1, Z), " &\r
+ "239 (BC_1, *, control, 1), " &\r
+ "238 (BC_7, DDR_D(15), bidir, X, 239, 1, Z), " &\r
+ "237 (BC_1, *, control, 1), " &\r
+ "236 (BC_7, DDR_D(14), bidir, X, 237, 1, Z), " &\r
+ "235 (BC_1, *, control, 1), " &\r
+ "234 (BC_7, DDR_D(13), bidir, X, 235, 1, Z), " &\r
+ "233 (BC_1, *, control, 1), " &\r
+ "232 (BC_7, DDR_D(12), bidir, X, 233, 1, Z), " &\r
+ "231 (BC_1, *, control, 1), " &\r
+ "230 (BC_7, DDR_DQS(1), bidir, X, 231, 1, Z), " &\r
+ "229 (BC_1, *, control, 1), " &\r
+ "228 (BC_7, DDR_D(11), bidir, X, 229, 1, Z), " &\r
+ "227 (BC_1, *, control, 1), " &\r
+ "226 (BC_7, DDR_D(10), bidir, X, 227, 1, Z), " &\r
+ "225 (BC_1, *, control, 1), " &\r
+ "224 (BC_7, DDR_D(9), bidir, X, 225, 1, Z), " &\r
+ "223 (BC_1, *, control, 1), " &\r
+ "222 (BC_7, DDR_D(8), bidir, X, 223, 1, Z), " &\r
+ "221 (BC_0, *, control, 1), " &\r
+ "220 (BC_0, DDR_DQM(1), output3, X, 221, 1, Z), " &\r
+ "219 (BC_0, *, control, 1), " &\r
+ "218 (BC_0, DDR_BA(2), output3, X, 219, 1, Z), " &\r
+ "217 (BC_0, *, control, 1), " &\r
+ "216 (BC_0, DDR_BA(1), output3, X, 217, 1, Z), " &\r
+ "215 (BC_0, *, control, 1), " &\r
+ "214 (BC_0, DDR_BA(0), output3, X, 215, 1, Z), " &\r
+ "213 (BC_0, *, control, 1), " &\r
+ "212 (BC_0, DDR_CKE, output3, X, 213, 1, Z), " &\r
+ "211 (BC_0, *, control, 1), " &\r
+ "210 (BC_0, DDR_CS, output3, X, 211, 1, Z), " &\r
+ "209 (BC_0, *, control, 1), " &\r
+ "208 (BC_0, DDR_A(13), output3, X, 209, 1, Z), " &\r
+ "207 (BC_0, *, control, 1), " &\r
+ "206 (BC_0, DDR_RESETN, output3, X, 207, 1, Z), " &\r
+ "205 (BC_0, *, control, 1), " &\r
+ "204 (BC_0, DDR_A(5), output3, X, 205, 1, Z), " &\r
+ "203 (BC_0, *, control, 1), " &\r
+ "202 (BC_0, DDR_A(6), output3, X, 203, 1, Z), " &\r
+ "201 (BC_0, *, control, 1), " &\r
+ "200 (BC_0, DDR_RAS, output3, X, 201, 1, Z), " &\r
+ "199 (BC_0, *, control, 1), " &\r
+ "198 (BC_0, DDR_CAS, output3, X, 199, 1, Z), " &\r
+ "197 (BC_0, *, control, 1), " &\r
+ "196 (BC_0, DDR_WE, output3, X, 197, 1, Z), " &\r
+ "195 (BC_0, *, control, 1), " &\r
+ "194 (BC_0, DDR_CLK, output3, X, 195, 1, Z), " &\r
+ "193 (BC_0, *, control, 1), " &\r
+ "192 (BC_0, DDR_A(0), output3, X, 193, 1, Z), " &\r
+ "191 (BC_0, *, control, 1), " &\r
+ "190 (BC_0, DDR_A(1), output3, X, 191, 1, Z), " &\r
+ "189 (BC_0, *, control, 1), " &\r
+ "188 (BC_0, DDR_A(2), output3, X, 189, 1, Z), " &\r
+ "187 (BC_0, *, control, 1), " &\r
+ "186 (BC_0, DDR_A(3), output3, X, 187, 1, Z), " &\r
+ "185 (BC_0, *, control, 1), " &\r
+ "184 (BC_0, DDR_A(4), output3, X, 185, 1, Z), " &\r
+ "183 (BC_0, *, control, 1), " &\r
+ "182 (BC_0, DDR_A(12), output3, X, 183, 1, Z), " &\r
+ "181 (BC_0, *, control, 1), " &\r
+ "180 (BC_0, DDR_A(11), output3, X, 181, 1, Z), " &\r
+ "179 (BC_0, *, control, 1), " &\r
+ "178 (BC_0, DDR_A(10), output3, X, 179, 1, Z), " &\r
+ "177 (BC_0, *, control, 1), " &\r
+ "176 (BC_0, DDR_A(9), output3, X, 177, 1, Z), " &\r
+ "175 (BC_0, *, control, 1), " &\r
+ "174 (BC_0, DDR_A(8), output3, X, 175, 1, Z), " &\r
+ "173 (BC_0, *, control, 1), " &\r
+ "172 (BC_0, DDR_A(7), output3, X, 173, 1, Z), " &\r
+ "171 (BC_1, *, control, 1), " &\r
+ "170 (BC_7, DDR_D(7), bidir, X, 171, 1, Z), " &\r
+ "169 (BC_1, *, control, 1), " &\r
+ "168 (BC_7, DDR_D(6), bidir, X, 169, 1, Z), " &\r
+ "167 (BC_1, *, control, 1), " &\r
+ "166 (BC_7, DDR_D(5), bidir, X, 167, 1, Z), " &\r
+ "165 (BC_1, *, control, 1), " &\r
+ "164 (BC_7, DDR_D(4), bidir, X, 165, 1, Z), " &\r
+ "163 (BC_1, *, control, 1), " &\r
+ "162 (BC_7, DDR_DQS(0), bidir, X, 163, 1, Z), " &\r
+ "161 (BC_1, *, control, 1), " &\r
+ "160 (BC_7, DDR_D(3), bidir, X, 161, 1, Z), " &\r
+ "159 (BC_1, *, control, 1), " &\r
+ "158 (BC_7, DDR_D(2), bidir, X, 159, 1, Z), " &\r
+ "157 (BC_1, *, control, 1), " &\r
+ "156 (BC_7, DDR_D(1), bidir, X, 157, 1, Z), " &\r
+ "155 (BC_1, *, control, 1), " &\r
+ "154 (BC_7, DDR_D(0), bidir, X, 155, 1, Z), " &\r
+ "153 (BC_0, *, control, 1), " &\r
+ "152 (BC_0, DDR_DQM(0), output3, X, 153, 1, Z), " &\r
+ "151 (BC_1, *, control, 1), " &\r
+ "150 (BC_7, DDR_D(23), bidir, X, 151, 1, Z), " &\r
+ "149 (BC_1, *, control, 1), " &\r
+ "148 (BC_7, DDR_D(22), bidir, X, 149, 1, Z), " &\r
+ "147 (BC_1, *, control, 1), " &\r
+ "146 (BC_7, DDR_D(21), bidir, X, 147, 1, Z), " &\r
+ "145 (BC_1, *, control, 1), " &\r
+ "144 (BC_7, DDR_D(20), bidir, X, 145, 1, Z), " &\r
+ "143 (BC_1, *, control, 1), " &\r
+ "142 (BC_7, DDR_DQS(2), bidir, X, 143, 1, Z), " &\r
+ "141 (BC_1, *, control, 1), " &\r
+ "140 (BC_7, DDR_D(19), bidir, X, 141, 1, Z), " &\r
+ "139 (BC_1, *, control, 1), " &\r
+ "138 (BC_7, DDR_D(18), bidir, X, 139, 1, Z), " &\r
+ "137 (BC_1, *, control, 1), " &\r
+ "136 (BC_7, DDR_D(17), bidir, X, 137, 1, Z), " &\r
+ "135 (BC_1, *, control, 1), " &\r
+ "134 (BC_7, DDR_D(16), bidir, X, 135, 1, Z), " &\r
+ "133 (BC_0, *, control, 1), " &\r
+ "132 (BC_0, DDR_DQM(2), output3, X, 133, 1, Z), " &\r
+ "131 (BC_1, *, control, 1), " &\r
+ "130 (BC_7, PD0, bidir, X, 131, 1, Z), " &\r
+ "129 (BC_1, *, control, 1), " &\r
+ "128 (BC_7, PD1, bidir, X, 129, 1, Z), " &\r
+ "127 (BC_1, *, control, 1), " &\r
+ "126 (BC_7, PD2, bidir, X, 127, 1, Z), " &\r
+ "125 (BC_0, *, internal, X), " &\r
+ "124 (BC_0, *, internal, X), " &\r
+ "123 (BC_0, *, internal, X), " &\r
+ "122 (BC_0, *, internal, X), " &\r
+ "121 (BC_0, *, internal, X), " &\r
+ "120 (BC_0, *, internal, X), " &\r
+ "119 (BC_0, *, internal, X), " &\r
+ "118 (BC_0, *, internal, X), " &\r
+ "117 (BC_0, *, internal, X), " &\r
+ "116 (BC_0, *, internal, X), " &\r
+ "115 (BC_0, *, internal, X), " &\r
+ "114 (BC_0, *, internal, X), " &\r
+ "113 (BC_1, *, control, 1), " &\r
+ "112 (BC_7, PB0, bidir, X, 113, 1, Z), " &\r
+ "111 (BC_1, *, control, 1), " &\r
+ "110 (BC_7, PB2, bidir, X, 111, 1, Z), " &\r
+ "109 (BC_1, *, control, 1), " &\r
+ "108 (BC_7, PB1, bidir, X, 109, 1, Z), " &\r
+ "107 (BC_1, *, control, 1), " &\r
+ "106 (BC_7, PB3, bidir, X, 107, 1, Z), " &\r
+ "105 (BC_1, *, control, 1), " &\r
+ "104 (BC_7, PB4, bidir, X, 105, 1, Z), " &\r
+ "103 (BC_1, *, control, 1), " &\r
+ "102 (BC_7, PB5, bidir, X, 103, 1, Z), " &\r
+ "101 (BC_1, *, control, 1), " &\r
+ "100 (BC_7, PB6, bidir, X, 101, 1, Z), " &\r
+ "99 (BC_1, *, control, 1), " &\r
+ "98 (BC_7, PB8, bidir, X, 99, 1, Z), " &\r
+ "97 (BC_1, *, control, 1), " &\r
+ "96 (BC_7, PB7, bidir, X, 97, 1, Z), " &\r
+ "95 (BC_1, *, control, 1), " &\r
+ "94 (BC_7, PB10, bidir, X, 95, 1, Z), " &\r
+ "93 (BC_1, *, control, 1), " &\r
+ "92 (BC_7, PB9, bidir, X, 93, 1, Z), " &\r
+ "91 (BC_1, *, control, 1), " &\r
+ "90 (BC_7, PB11, bidir, X, 91, 1, Z), " &\r
+ "89 (BC_1, *, control, 1), " &\r
+ "88 (BC_7, PB12, bidir, X, 89, 1, Z), " &\r
+ "87 (BC_1, *, control, 1), " &\r
+ "86 (BC_7, PB14, bidir, X, 87, 1, Z), " &\r
+ "85 (BC_1, *, control, 1), " &\r
+ "84 (BC_7, PB13, bidir, X, 85, 1, Z), " &\r
+ "83 (BC_1, *, control, 1), " &\r
+ "82 (BC_7, PB15, bidir, X, 83, 1, Z), " &\r
+ "81 (BC_1, *, control, 1), " &\r
+ "80 (BC_7, PB16, bidir, X, 81, 1, Z), " &\r
+ "79 (BC_1, *, control, 1), " &\r
+ "78 (BC_7, PB17, bidir, X, 79, 1, Z), " &\r
+ "77 (BC_1, *, control, 1), " &\r
+ "76 (BC_7, PB19, bidir, X, 77, 1, Z), " &\r
+ "75 (BC_1, *, control, 1), " &\r
+ "74 (BC_7, PB18, bidir, X, 75, 1, Z), " &\r
+ "73 (BC_1, *, control, 1), " &\r
+ "72 (BC_7, PB20, bidir, X, 73, 1, Z), " &\r
+ "71 (BC_1, *, control, 1), " &\r
+ "70 (BC_7, PB21, bidir, X, 71, 1, Z), " &\r
+ "69 (BC_1, *, control, 1), " &\r
+ "68 (BC_7, PB23, bidir, X, 69, 1, Z), " &\r
+ "67 (BC_1, *, control, 1), " &\r
+ "66 (BC_7, PB22, bidir, X, 67, 1, Z), " &\r
+ "65 (BC_1, *, control, 1), " &\r
+ "64 (BC_7, PB25, bidir, X, 65, 1, Z), " &\r
+ "63 (BC_1, *, control, 1), " &\r
+ "62 (BC_7, PB24, bidir, X, 63, 1, Z), " &\r
+ "61 (BC_1, *, control, 1), " &\r
+ "60 (BC_7, PB26, bidir, X, 61, 1, Z), " &\r
+ "59 (BC_1, *, control, 1), " &\r
+ "58 (BC_7, PB28, bidir, X, 59, 1, Z), " &\r
+ "57 (BC_1, *, control, 1), " &\r
+ "56 (BC_7, PB27, bidir, X, 57, 1, Z), " &\r
+ "55 (BC_1, *, control, 1), " &\r
+ "54 (BC_7, PB30, bidir, X, 55, 1, Z), " &\r
+ "53 (BC_1, *, control, 1), " &\r
+ "52 (BC_7, PB29, bidir, X, 53, 1, Z), " &\r
+ "51 (BC_1, *, control, 1), " &\r
+ "50 (BC_7, PB31, bidir, X, 51, 1, Z), " &\r
+ "49 (BC_0, *, internal, X), " &\r
+ "48 (BC_0, *, internal, X), " &\r
+ "47 (BC_0, *, internal, X), " &\r
+ "46 (BC_0, *, internal, X), " &\r
+ "45 (BC_0, *, internal, X), " &\r
+ "44 (BC_0, *, internal, X), " &\r
+ "43 (BC_0, *, internal, X), " &\r
+ "42 (BC_0, *, internal, X), " &\r
+ "41 (BC_0, *, internal, X), " &\r
+ "40 (BC_0, *, internal, X), " &\r
+ "39 (BC_0, *, internal, X), " &\r
+ "38 (BC_0, *, internal, X), " &\r
+ "37 (BC_0, *, internal, X), " &\r
+ "36 (BC_0, *, internal, X), " &\r
+ "35 (BC_0, *, internal, X), " &\r
+ "34 (BC_0, *, internal, X), " &\r
+ "33 (BC_0, *, internal, X), " &\r
+ "32 (BC_0, *, internal, X), " &\r
+ "31 (BC_0, *, internal, X), " &\r
+ "30 (BC_0, *, internal, X), " &\r
+ "29 (BC_0, *, internal, X), " &\r
+ "28 (BC_0, *, internal, X), " &\r
+ "27 (BC_0, *, internal, X), " &\r
+ "26 (BC_0, *, internal, X), " &\r
+ "25 (BC_0, *, internal, X), " &\r
+ "24 (BC_0, *, internal, X), " &\r
+ "23 (BC_0, *, internal, X), " &\r
+ "22 (BC_0, *, internal, X), " &\r
+ "21 (BC_0, *, internal, X), " &\r
+ "20 (BC_0, *, internal, X), " &\r
+ "19 (BC_0, *, internal, X), " &\r
+ "18 (BC_0, *, internal, X), " &\r
+ "17 (BC_0, *, internal, X), " &\r
+ "16 (BC_0, *, internal, X), " &\r
+ "15 (BC_1, *, control, 1), " &\r
+ "14 (BC_7, PD10, bidir, X, 15, 1, Z), " &\r
+ "13 (BC_1, *, control, 1), " &\r
+ "12 (BC_7, PD9, bidir, X, 13, 1, Z), " &\r
+ "11 (BC_1, *, control, 1), " &\r
+ "10 (BC_7, PD8, bidir, X, 11, 1, Z), " &\r
+ "9 (BC_1, *, control, 1), " &\r
+ "8 (BC_7, PD7, bidir, X, 9, 1, Z), " &\r
+ "7 (BC_1, *, control, 1), " &\r
+ "6 (BC_7, PD6, bidir, X, 7, 1, Z), " &\r
+ "5 (BC_1, *, control, 1), " &\r
+ "4 (BC_7, PD5, bidir, X, 5, 1, Z), " &\r
+ "3 (BC_1, *, control, 1), " &\r
+ "2 (BC_7, PD4, bidir, X, 3, 1, Z), " &\r
+ "1 (BC_1, *, control, 1), " &\r
+ "0 (BC_7, PD3, bidir, X, 1, 1, Z) ";\r
+ \r
+ end top;\r
--- /dev/null
+-- *****************************************************************************\r
+\r
+-- BSDL file for design top\r
+\r
+-- Created by Synopsys Version I-2013.12-SP3 (Apr 18, 2014)\r
+\r
+-- Designer:\r
+-- Company:\r
+\r
+-- Date: Thu Feb 5 23:41:59 2015\r
+\r
+-- *****************************************************************************\r
+\r
+\r
+ entity top is\r
+\r
+-- This section identifies the default device package selected.\r
+\r
+ generic (PHYSICAL_PIN_MAP: string:= "BGA289");\r
+\r
+-- This section declares all the ports in the design.\r
+\r
+ port (\r
+ PD14 : in bit;\r
+ PD15 : in bit;\r
+ PD17 : in bit;\r
+ PD18 : in bit;\r
+ PA0 : inout bit;\r
+ PA1 : inout bit;\r
+ PA10 : inout bit;\r
+ PA11 : inout bit;\r
+ PA12 : inout bit;\r
+ PA13 : inout bit;\r
+ PA14 : inout bit;\r
+ PA15 : inout bit;\r
+ PA16 : inout bit;\r
+ PA17 : inout bit;\r
+ PA18 : inout bit;\r
+ PA19 : inout bit;\r
+ PA2 : inout bit;\r
+ PA20 : inout bit;\r
+ PA21 : inout bit;\r
+ PA22 : inout bit;\r
+ PA23 : inout bit;\r
+ PA24 : inout bit;\r
+ PA25 : inout bit;\r
+ PA26 : inout bit;\r
+ PA27 : inout bit;\r
+ PA28 : inout bit;\r
+ PA29 : inout bit;\r
+ PA3 : inout bit;\r
+ PA30 : inout bit;\r
+ PA31 : inout bit;\r
+ PA4 : inout bit;\r
+ PA5 : inout bit;\r
+ PA6 : inout bit;\r
+ PA7 : inout bit;\r
+ PA8 : inout bit;\r
+ PA9 : inout bit;\r
+ PB0 : inout bit;\r
+ PB1 : inout bit;\r
+ PB10 : inout bit;\r
+ PB11 : inout bit;\r
+ PB12 : inout bit;\r
+ PB13 : inout bit;\r
+ PB14 : inout bit;\r
+ PB15 : inout bit;\r
+ PB16 : inout bit;\r
+ PB17 : inout bit;\r
+ PB18 : inout bit;\r
+ PB19 : inout bit;\r
+ PB2 : inout bit;\r
+ PB20 : inout bit;\r
+ PB21 : inout bit;\r
+ PB22 : inout bit;\r
+ PB23 : inout bit;\r
+ PB24 : inout bit;\r
+ PB25 : inout bit;\r
+ PB26 : inout bit;\r
+ PB27 : inout bit;\r
+ PB28 : inout bit;\r
+ PB29 : inout bit;\r
+ PB3 : inout bit;\r
+ PB30 : inout bit;\r
+ PB31 : inout bit;\r
+ PB4 : inout bit;\r
+ PB5 : inout bit;\r
+ PB6 : inout bit;\r
+ PB7 : inout bit;\r
+ PB8 : inout bit;\r
+ PB9 : inout bit;\r
+ PC0 : inout bit;\r
+ PC1 : inout bit;\r
+ PC10 : inout bit;\r
+ PC11 : inout bit;\r
+ PC12 : inout bit;\r
+ PC13 : inout bit;\r
+ PC14 : inout bit;\r
+ PC15 : inout bit;\r
+ PC16 : inout bit;\r
+ PC17 : inout bit;\r
+ PC18 : inout bit;\r
+ PC19 : inout bit;\r
+ PC2 : inout bit;\r
+ PC20 : inout bit;\r
+ PC21 : inout bit;\r
+ PC22 : inout bit;\r
+ PC23 : inout bit;\r
+ PC24 : inout bit;\r
+ PC25 : inout bit;\r
+ PC26 : inout bit;\r
+ PC27 : inout bit;\r
+ PC28 : inout bit;\r
+ PC29 : inout bit;\r
+ PC3 : inout bit;\r
+ PC30 : inout bit;\r
+ PC31 : inout bit;\r
+ PC4 : inout bit;\r
+ PC5 : inout bit;\r
+ PC6 : inout bit;\r
+ PC7 : inout bit;\r
+ PC8 : inout bit;\r
+ PC9 : inout bit;\r
+ PD0 : inout bit;\r
+ PD1 : inout bit;\r
+ PD10 : inout bit;\r
+ PD11 : inout bit;\r
+ PD12 : inout bit;\r
+ PD13 : inout bit;\r
+ PD19 : inout bit;\r
+ PD2 : inout bit;\r
+ PD20 : inout bit;\r
+ PD21 : inout bit;\r
+ PD22 : inout bit;\r
+ PD23 : inout bit;\r
+ PD24 : inout bit;\r
+ PD25 : inout bit;\r
+ PD26 : inout bit;\r
+ PD27 : inout bit;\r
+ PD28 : inout bit;\r
+ PD29 : inout bit;\r
+ PD3 : inout bit;\r
+ PD30 : inout bit;\r
+ PD31 : inout bit;\r
+ PD4 : inout bit;\r
+ PD5 : inout bit;\r
+ PD6 : inout bit;\r
+ PD7 : inout bit;\r
+ PD8 : inout bit;\r
+ PD9 : inout bit;\r
+ DDR_D : inout bit_vector (0 to 31);\r
+ DDR_DQS : inout bit_vector (0 to 3);\r
+ DDR_DQSN : inout bit_vector (0 to 3);\r
+ DDR_CAS : out bit;\r
+ DDR_CKE : out bit;\r
+ DDR_CLK : out bit;\r
+ DDR_CLKN : out bit;\r
+ DDR_CS : out bit;\r
+ DDR_RAS : out bit;\r
+ DDR_RESETN : out bit;\r
+ DDR_WE : out bit;\r
+ PD16 : out bit;\r
+ DDR_A : out bit_vector (0 to 13);\r
+ DDR_BA : out bit_vector (0 to 2);\r
+ DDR_DQM : out bit_vector (0 to 3);\r
+ -- ADVREFN : linkage bit;\r
+ ADVREFP : linkage bit;\r
+ CLK_AUDIO : linkage bit;\r
+ COMPN : linkage bit;\r
+ COMPP : linkage bit;\r
+ DDR_CAL : linkage bit;\r
+ DDR_VREF : linkage bit; -- DDR_VREFB0 : linkage bit;\r
+ -- DDR_VREFB1 : linkage bit;\r
+ -- DDR_VREFB2 : linkage bit;\r
+ -- DDR_VREFB3 : linkage bit;\r
+ -- DDR_VREFCM : linkage bit;\r
+ HHSDMA : linkage bit;\r
+ HHSDMB : linkage bit;\r
+ HHSDMSTRC : linkage bit;\r
+ HHSDPA : linkage bit;\r
+ HHSDPB : linkage bit;\r
+ HHSDPDATC : linkage bit;\r
+ JTAGSEL : in bit;\r
+ NRST : linkage bit;\r
+ RXD : linkage bit;\r
+ SDCAL : linkage bit;\r
+ SHDN : linkage bit;\r
+ TST : in bit;\r
+ VBG : linkage bit;\r
+ WKUP : linkage bit;\r
+ XIN : linkage bit;\r
+ XIN32 : linkage bit;\r
+ XOUT : linkage bit;\r
+ XOUT32 : linkage bit;\r
+ -- tst_drst_ana : linkage bit; -- NC Port\r
+ -- tst_drst_ddr : linkage bit; -- NC Port\r
+ -- tst_drst_iop0 : linkage bit; -- NC Port\r
+ -- tst_drst_iop1 : linkage bit; -- NC Port\r
+ -- tst_drst_iop2 : linkage bit; -- NC Port\r
+ -- tst_drst_isi : linkage bit; -- NC Port\r
+ -- tst_drst_osc : linkage bit; -- NC Port\r
+ -- tst_drst_sdhc : linkage bit; -- NC Port\r
+ -- tst_lft_plla : linkage bit; -- NC Port\r
+ -- tst_lft_utmi : linkage bit; -- NC Port\r
+ -- tst_por_1v2 : linkage bit; -- NC Port\r
+ -- tst_por_1v8 : linkage bit; -- NC Port\r
+ -- tst_por_bu : linkage bit; -- NC Port\r
+ -- tst_psw_bu : linkage bit; -- NC Port\r
+ -- tst_psw_fuse : linkage bit; -- NC Port\r
+ PIOBU : linkage bit_vector (0 to 7)\r
+ );\r
+\r
+ use STD_1149_1_1994.all;\r
+\r
+ attribute COMPONENT_CONFORMANCE of top: entity is "STD_1149_1_1993";\r
+\r
+ attribute PIN_MAP of top: entity is PHYSICAL_PIN_MAP;\r
+\r
+-- This section specifies the pin map for each port. This information is\r
+-- extracted from the port-to-pin map file that was read in using the\r
+-- "read_pin_map" command.\r
+\r
+ constant BGA289: PIN_MAP_STRING :=\r
+ "PD14 : K4," &\r
+ "PD15 : K7," &\r
+ "PD17 : K2," &\r
+ "PD18 : J5," &\r
+ "PA0 : U11," &\r
+ "PA1 : P10," &\r
+ "PA10 : U13," &\r
+ "PA11 : P15," &\r
+ "PA12 : N15," &\r
+ "PA13 : P16," &\r
+ "PA14 : M14," &\r
+ "PA15 : N16," &\r
+ "PA16 : M10," &\r
+ "PA17 : N17," &\r
+ "PA18 : U14," &\r
+ "PA19 : T14," &\r
+ "PA2 : T11," &\r
+ "PA20 : P12," &\r
+ "PA21 : R13," &\r
+ "PA22 : U15," &\r
+ "PA23 : U16," &\r
+ "PA24 : T15," &\r
+ "PA25 : U17," &\r
+ "PA26 : P13," &\r
+ "PA27 : T16," &\r
+ "PA28 : R16," &\r
+ "PA29 : T17," &\r
+ "PA3 : R10," &\r
+ "PA30 : R15," &\r
+ "PA31 : R17," &\r
+ "PA4 : U12," &\r
+ "PA5 : T12," &\r
+ "PA6 : R12," &\r
+ "PA7 : T13," &\r
+ "PA8 : N10," &\r
+ "PA9 : N11," &\r
+ "PB0 : J8," &\r
+ "PB1 : A8," &\r
+ "PB10 : H8," &\r
+ "PB11 : B5," &\r
+ "PB12 : D6," &\r
+ "PB13 : B4," &\r
+ "PB14 : C5," &\r
+ "PB15 : H7," &\r
+ "PB16 : D5," &\r
+ "PB17 : C4," &\r
+ "PB18 : A3," &\r
+ "PB19 : D4," &\r
+ "PB2 : A7," &\r
+ "PB20 : B3," &\r
+ "PB21 : A2," &\r
+ "PB22 : C3," &\r
+ "PB23 : A1," &\r
+ "PB24 : E5," &\r
+ "PB25 : B2," &\r
+ "PB26 : E4," &\r
+ "PB27 : B1," &\r
+ "PB28 : C2," &\r
+ "PB29 : D3," &\r
+ "PB3 : A6," &\r
+ "PB30 : D2," &\r
+ "PB31 : C1," &\r
+ "PB4 : B6," &\r
+ "PB5 : B7," &\r
+ "PB6 : C7," &\r
+ "PB7 : C6," &\r
+ "PB8 : A5," &\r
+ "PB9 : A4," &\r
+ "PC0 : P17," &\r
+ "PC1 : N12," &\r
+ "PC10 : E3," &\r
+ "PC11 : E2," &\r
+ "PC12 : E1," &\r
+ "PC13 : F3," &\r
+ "PC14 : F5," &\r
+ "PC15 : F2," &\r
+ "PC16 : G6," &\r
+ "PC17 : F1," &\r
+ "PC18 : H6," &\r
+ "PC19 : G2," &\r
+ "PC2 : N14," &\r
+ "PC20 : G3," &\r
+ "PC21 : G1," &\r
+ "PC22 : H2," &\r
+ "PC23 : G5," &\r
+ "PC24 : H1," &\r
+ "PC25 : H5," &\r
+ "PC26 : J9," &\r
+ "PC27 : H9," &\r
+ "PC28 : E8," &\r
+ "PC29 : G8," &\r
+ "PC3 : M15," &\r
+ "PC30 : F8," &\r
+ "PC31 : D8," &\r
+ "PC4 : M11," &\r
+ "PC5 : L10," &\r
+ "PC6 : K10," &\r
+ "PC7 : M16," &\r
+ "PC8 : J10," &\r
+ "PC9 : D1," &\r
+ "PD0 : G10," &\r
+ "PD1 : E10," &\r
+ "PD10 : J3," &\r
+ "PD11 : M1," &\r
+ "PD12 : K8," &\r
+ "PD13 : L2," &\r
+ "PD19 : K6," &\r
+ "PD2 : G9," &\r
+ "PD20 : M2," &\r
+ "PD21 : N1," &\r
+ "PD22 : L4," &\r
+ "PD23 : M3," &\r
+ "PD24 : L7," &\r
+ "PD25 : L6," &\r
+ "PD26 : N2," &\r
+ "PD27 : L8," &\r
+ "PD28 : M4," &\r
+ "PD29 : N3," &\r
+ "PD3 : K1," &\r
+ "PD30 : L9," &\r
+ "PD31 : M7," &\r
+ "PD4 : J6," &\r
+ "PD5 : J4," &\r
+ "PD6 : J2," &\r
+ "PD7 : J7," &\r
+ "PD8 : J1," &\r
+ "PD9 : K9," &\r
+ "DDR_D : (B12, A12, C12, A13, A14, C13, A15, B15, G17, G16, " &\r
+ "H17, K17, K16, J13, K14, K15, B8, B9, C9, A9, A10, D10, B11, A11, " &\r
+ "J12, H10, J11, K11, L13, L11, L12, M17)," &\r
+ "DDR_DQS : (B13, J17, C10, L17)," &\r
+ "DDR_DQSN : (B14, J16, B10, L16)," &\r
+ "DDR_CAS : G12," &\r
+ "DDR_CKE : F16," &\r
+ "DDR_CLK : E17," &\r
+ "DDR_CLKN : D17," &\r
+ "DDR_CS : G13," &\r
+ "DDR_RAS : F13," &\r
+ "DDR_RESETN : E16," &\r
+ "DDR_WE : F15," &\r
+ "PD16 : L1," &\r
+ "DDR_A : (F12, C17, B17, B16, C16, G14, F14, F11, C14, D13, " &\r
+ "C15, A16, A17, G11)," &\r
+ "DDR_BA : (H12, H13, F17)," &\r
+ "DDR_DQM : (C11, G15, C8, H11)," &\r
+ "ADVREFP : M6," &\r
+ "CLK_AUDIO : U3," &\r
+ "COMPN : U1," &\r
+ "COMPP : T1," &\r
+ "DDR_CAL : E13," &\r
+ "HHSDMA : R8," &\r
+ "HHSDMB : U9," &\r
+ "HHSDMSTRC : U10," &\r
+ "HHSDPA : T8," &\r
+ "HHSDPB : U8," &\r
+ "HHSDPDATC : T9," &\r
+ "JTAGSEL : T2," &\r
+ "NRST : U2," &\r
+ "RXD : N4," &\r
+ "SDCAL : T10," &\r
+ "SHDN : R1," &\r
+ "TST : P3," &\r
+ "VBG : R6," &\r
+ "WKUP : P4," &\r
+ "XIN : U7," &\r
+ "XIN32 : P1," &\r
+ "XOUT : U6," &\r
+ "XOUT32 : P2," &\r
+ "PIOBU : (R3, N8, R2, R5, R4, P5, P6, M8)";\r
+\r
+-- This section specifies the differential IO port groupings.\r
+\r
+ attribute PORT_GROUPING of top: entity is\r
+ "Differential_Voltage ( " &\r
+ "(DDR_CLK,DDR_CLKN))";\r
+\r
+-- This section specifies the TAP ports. For the TAP TCK port, the parameters in\r
+-- the brackets are:\r
+-- First Field : Maximum TCK frequency.\r
+-- Second Field: Allowable states TCK may be stopped in.\r
+\r
+ attribute TAP_SCAN_CLOCK of PD14: signal is (10.0e6, BOTH);\r
+ attribute TAP_SCAN_IN of PD15: signal is true;\r
+ attribute TAP_SCAN_MODE of PD17: signal is true;\r
+ attribute TAP_SCAN_OUT of PD16: signal is true;\r
+ attribute TAP_SCAN_RESET of PD18: signal is true;\r
+\r
+-- Specifies the compliance enable patterns for the design. It lists a set of\r
+-- design ports and the values that they should be set to, in order to enable\r
+-- compliance to IEEE Std 1149.1\r
+\r
+ attribute COMPLIANCE_PATTERNS of top: entity is\r
+ "(JTAGSEL, TST) (10)";\r
+\r
+-- Specifies the number of bits in the instruction register.\r
+\r
+ attribute INSTRUCTION_LENGTH of top: entity is 4;\r
+\r
+-- Specifies the boundary-scan instructions implemented in the design and their\r
+-- opcodes.\r
+\r
+ attribute INSTRUCTION_OPCODE of top: entity is\r
+ "BYPASS (1111, 0001, 0101, 0110, 1100, 0111, 1101, 1000, 1001, 1011, " &\r
+ "1110)," &\r
+ "EXTEST (0000)," &\r
+ "SAMPLE (0100)," &\r
+ "INTEST (0010)," &\r
+ "IDCODE (0011)," &\r
+ "RUNBIST (1010)";\r
+\r
+-- Specifies the bit pattern that is loaded into the instruction register when\r
+-- the TAP controller passes through the Capture-IR state. The standard mandates\r
+-- that the two LSBs must be "01". The remaining bits are design specific.\r
+\r
+ attribute INSTRUCTION_CAPTURE of top: entity is "0001";\r
+\r
+-- Specifies the bit pattern that is loaded into the DEVICE_ID register during\r
+-- the IDCODE instruction when the TAP controller passes through the Capture-DR\r
+-- state.\r
+\r
+ attribute IDCODE_REGISTER of top: entity is\r
+ "0000" &\r
+ -- 4-bit version number\r
+ "0101101100111111" &\r
+ -- 16-bit part number\r
+ "00000011111" &\r
+ -- 11-bit identity of the manufacturer\r
+ "1";\r
+ -- Required by IEEE Std 1149.1\r
+\r
+-- This section specifies the test data register placed between TDI and TDO for\r
+-- each implemented instruction.\r
+\r
+ attribute REGISTER_ACCESS of top: entity is\r
+ "BYPASS (BYPASS)," &\r
+ "BOUNDARY (EXTEST, SAMPLE, INTEST)," &\r
+ "DEVICE_ID (IDCODE)," &\r
+ "UTDR1[41] (RUNBIST)";\r
+\r
+-- Specifies the length of the boundary scan register.\r
+\r
+ attribute BOUNDARY_LENGTH of top: entity is 374;\r
+\r
+-- The following list specifies the characteristics of each cell in the boundary\r
+-- scan register from TDI to TDO. The following is a description of the label\r
+-- fields:\r
+-- num : Is the cell number.\r
+-- cell : Is the cell type as defined by the standard.\r
+-- port : Is the design port name. Control cells do not have a port\r
+-- name.\r
+-- function: Is the function of the cell as defined by the standard. Is one\r
+-- of input, output2, output3, bidir, control or controlr.\r
+-- safe : Specifies the value that the BSR cell should be loaded with\r
+-- for safe operation when the software might otherwise choose a\r
+-- random value.\r
+-- ccell : The control cell number. Specifies the control cell that\r
+-- drives the output enable for this port.\r
+-- disval : Specifies the value that is loaded into the control cell to\r
+-- disable the output enable for the corresponding port.\r
+-- rslt : Resulting state. Shows the state of the driver when it is\r
+-- disabled.\r
+\r
+ attribute BOUNDARY_REGISTER of top: entity is\r
+--\r
+-- num cell port function safe [ccell disval rslt]\r
+--\r
+ "373 (BC_1, *, control, 1), " &\r
+ "372 (BC_7, PD13, bidir, X, 373, 1, Z), " &\r
+ "371 (BC_1, *, control, 1), " &\r
+ "370 (BC_7, PD12, bidir, X, 371, 1, Z), " &\r
+ "369 (BC_1, *, control, 1), " &\r
+ "368 (BC_7, PD11, bidir, X, 369, 1, Z), " &\r
+ "367 (BC_1, *, control, 1), " &\r
+ "366 (BC_7, PD19, bidir, X, 367, 1, Z), " &\r
+ "365 (BC_1, *, control, 1), " &\r
+ "364 (BC_7, PD20, bidir, X, 365, 1, Z), " &\r
+ "363 (BC_1, *, control, 1), " &\r
+ "362 (BC_7, PD24, bidir, X, 363, 1, Z), " &\r
+ "361 (BC_1, *, control, 1), " &\r
+ "360 (BC_7, PD21, bidir, X, 361, 1, Z), " &\r
+ "359 (BC_1, *, control, 1), " &\r
+ "358 (BC_7, PD25, bidir, X, 359, 1, Z), " &\r
+ "357 (BC_1, *, control, 1), " &\r
+ "356 (BC_7, PD26, bidir, X, 357, 1, Z), " &\r
+ "355 (BC_1, *, control, 1), " &\r
+ "354 (BC_7, PD22, bidir, X, 355, 1, Z), " &\r
+ "353 (BC_1, *, control, 1), " &\r
+ "352 (BC_7, PD27, bidir, X, 353, 1, Z), " &\r
+ "351 (BC_1, *, control, 1), " &\r
+ "350 (BC_7, PD23, bidir, X, 351, 1, Z), " &\r
+ "349 (BC_1, *, control, 1), " &\r
+ "348 (BC_7, PD28, bidir, X, 349, 1, Z), " &\r
+ "347 (BC_1, *, control, 1), " &\r
+ "346 (BC_7, PD30, bidir, X, 347, 1, Z), " &\r
+ "345 (BC_1, *, control, 1), " &\r
+ "344 (BC_7, PD29, bidir, X, 345, 1, Z), " &\r
+ "343 (BC_1, *, control, 1), " &\r
+ "342 (BC_7, PD31, bidir, X, 343, 1, Z), " &\r
+ "341 (BC_1, *, control, 1), " &\r
+ "340 (BC_7, PA0, bidir, X, 341, 1, Z), " &\r
+ "339 (BC_1, *, control, 1), " &\r
+ "338 (BC_7, PA1, bidir, X, 339, 1, Z), " &\r
+ "337 (BC_1, *, control, 1), " &\r
+ "336 (BC_7, PA2, bidir, X, 337, 1, Z), " &\r
+ "335 (BC_1, *, control, 1), " &\r
+ "334 (BC_7, PA3, bidir, X, 335, 1, Z), " &\r
+ "333 (BC_1, *, control, 1), " &\r
+ "332 (BC_7, PA4, bidir, X, 333, 1, Z), " &\r
+ "331 (BC_1, *, control, 1), " &\r
+ "330 (BC_7, PA5, bidir, X, 331, 1, Z), " &\r
+ "329 (BC_1, *, control, 1), " &\r
+ "328 (BC_7, PA6, bidir, X, 329, 1, Z), " &\r
+ "327 (BC_1, *, control, 1), " &\r
+ "326 (BC_7, PA7, bidir, X, 327, 1, Z), " &\r
+ "325 (BC_1, *, control, 1), " &\r
+ "324 (BC_7, PA8, bidir, X, 325, 1, Z), " &\r
+ "323 (BC_1, *, control, 1), " &\r
+ "322 (BC_7, PA9, bidir, X, 323, 1, Z), " &\r
+ "321 (BC_1, *, control, 1), " &\r
+ "320 (BC_7, PA10, bidir, X, 321, 1, Z), " &\r
+ "319 (BC_1, *, control, 1), " &\r
+ "318 (BC_7, PA18, bidir, X, 319, 1, Z), " &\r
+ "317 (BC_1, *, control, 1), " &\r
+ "316 (BC_7, PA20, bidir, X, 317, 1, Z), " &\r
+ "315 (BC_1, *, control, 1), " &\r
+ "314 (BC_7, PA19, bidir, X, 315, 1, Z), " &\r
+ "313 (BC_1, *, control, 1), " &\r
+ "312 (BC_7, PA21, bidir, X, 313, 1, Z), " &\r
+ "311 (BC_1, *, control, 1), " &\r
+ "310 (BC_7, PA22, bidir, X, 311, 1, Z), " &\r
+ "309 (BC_1, *, control, 1), " &\r
+ "308 (BC_7, PA23, bidir, X, 309, 1, Z), " &\r
+ "307 (BC_1, *, control, 1), " &\r
+ "306 (BC_7, PA24, bidir, X, 307, 1, Z), " &\r
+ "305 (BC_1, *, control, 1), " &\r
+ "304 (BC_7, PA25, bidir, X, 305, 1, Z), " &\r
+ "303 (BC_1, *, control, 1), " &\r
+ "302 (BC_7, PA26, bidir, X, 303, 1, Z), " &\r
+ "301 (BC_1, *, control, 1), " &\r
+ "300 (BC_7, PA27, bidir, X, 301, 1, Z), " &\r
+ "299 (BC_1, *, control, 1), " &\r
+ "298 (BC_7, PA28, bidir, X, 299, 1, Z), " &\r
+ "297 (BC_1, *, control, 1), " &\r
+ "296 (BC_7, PA30, bidir, X, 297, 1, Z), " &\r
+ "295 (BC_1, *, control, 1), " &\r
+ "294 (BC_7, PA29, bidir, X, 295, 1, Z), " &\r
+ "293 (BC_1, *, control, 1), " &\r
+ "292 (BC_7, PA31, bidir, X, 293, 1, Z), " &\r
+ "291 (BC_1, *, control, 1), " &\r
+ "290 (BC_7, PC0, bidir, X, 291, 1, Z), " &\r
+ "289 (BC_1, *, control, 1), " &\r
+ "288 (BC_7, PA11, bidir, X, 289, 1, Z), " &\r
+ "287 (BC_1, *, control, 1), " &\r
+ "286 (BC_7, PC1, bidir, X, 287, 1, Z), " &\r
+ "285 (BC_1, *, control, 1), " &\r
+ "284 (BC_7, PA13, bidir, X, 285, 1, Z), " &\r
+ "283 (BC_1, *, control, 1), " &\r
+ "282 (BC_7, PA12, bidir, X, 283, 1, Z), " &\r
+ "281 (BC_1, *, control, 1), " &\r
+ "280 (BC_7, PC2, bidir, X, 281, 1, Z), " &\r
+ "279 (BC_1, *, control, 1), " &\r
+ "278 (BC_7, PA14, bidir, X, 279, 1, Z), " &\r
+ "277 (BC_1, *, control, 1), " &\r
+ "276 (BC_7, PA15, bidir, X, 277, 1, Z), " &\r
+ "275 (BC_1, *, control, 1), " &\r
+ "274 (BC_7, PC3, bidir, X, 275, 1, Z), " &\r
+ "273 (BC_1, *, control, 1), " &\r
+ "272 (BC_7, PC4, bidir, X, 273, 1, Z), " &\r
+ "271 (BC_1, *, control, 1), " &\r
+ "270 (BC_7, PA16, bidir, X, 271, 1, Z), " &\r
+ "269 (BC_1, *, control, 1), " &\r
+ "268 (BC_7, PA17, bidir, X, 269, 1, Z), " &\r
+ "267 (BC_1, *, control, 1), " &\r
+ "266 (BC_7, PC5, bidir, X, 267, 1, Z), " &\r
+ "265 (BC_1, *, control, 1), " &\r
+ "264 (BC_7, PC7, bidir, X, 265, 1, Z), " &\r
+ "263 (BC_1, *, control, 1), " &\r
+ "262 (BC_7, PC6, bidir, X, 263, 1, Z), " &\r
+ "261 (BC_1, *, control, 1), " &\r
+ "260 (BC_7, PC8, bidir, X, 261, 1, Z), " &\r
+ "259 (BC_1, *, control, 1), " &\r
+ "258 (BC_7, DDR_D(31), bidir, X, 259, 1, Z), " &\r
+ "257 (BC_1, *, control, 1), " &\r
+ "256 (BC_7, DDR_D(30), bidir, X, 257, 1, Z), " &\r
+ "255 (BC_1, *, control, 1), " &\r
+ "254 (BC_7, DDR_D(29), bidir, X, 255, 1, Z), " &\r
+ "253 (BC_1, *, control, 1), " &\r
+ "252 (BC_7, DDR_D(28), bidir, X, 253, 1, Z), " &\r
+ "251 (BC_1, *, control, 1), " &\r
+ "250 (BC_7, DDR_DQS(3), bidir, X, 251, 1, Z), " &\r
+ "249 (BC_1, *, control, 1), " &\r
+ "248 (BC_7, DDR_D(27), bidir, X, 249, 1, Z), " &\r
+ "247 (BC_1, *, control, 1), " &\r
+ "246 (BC_7, DDR_D(26), bidir, X, 247, 1, Z), " &\r
+ "245 (BC_1, *, control, 1), " &\r
+ "244 (BC_7, DDR_D(25), bidir, X, 245, 1, Z), " &\r
+ "243 (BC_1, *, control, 1), " &\r
+ "242 (BC_7, DDR_D(24), bidir, X, 243, 1, Z), " &\r
+ "241 (BC_0, *, control, 1), " &\r
+ "240 (BC_0, DDR_DQM(3), output3, X, 241, 1, Z), " &\r
+ "239 (BC_1, *, control, 1), " &\r
+ "238 (BC_7, DDR_D(15), bidir, X, 239, 1, Z), " &\r
+ "237 (BC_1, *, control, 1), " &\r
+ "236 (BC_7, DDR_D(14), bidir, X, 237, 1, Z), " &\r
+ "235 (BC_1, *, control, 1), " &\r
+ "234 (BC_7, DDR_D(13), bidir, X, 235, 1, Z), " &\r
+ "233 (BC_1, *, control, 1), " &\r
+ "232 (BC_7, DDR_D(12), bidir, X, 233, 1, Z), " &\r
+ "231 (BC_1, *, control, 1), " &\r
+ "230 (BC_7, DDR_DQS(1), bidir, X, 231, 1, Z), " &\r
+ "229 (BC_1, *, control, 1), " &\r
+ "228 (BC_7, DDR_D(11), bidir, X, 229, 1, Z), " &\r
+ "227 (BC_1, *, control, 1), " &\r
+ "226 (BC_7, DDR_D(10), bidir, X, 227, 1, Z), " &\r
+ "225 (BC_1, *, control, 1), " &\r
+ "224 (BC_7, DDR_D(9), bidir, X, 225, 1, Z), " &\r
+ "223 (BC_1, *, control, 1), " &\r
+ "222 (BC_7, DDR_D(8), bidir, X, 223, 1, Z), " &\r
+ "221 (BC_0, *, control, 1), " &\r
+ "220 (BC_0, DDR_DQM(1), output3, X, 221, 1, Z), " &\r
+ "219 (BC_0, *, control, 1), " &\r
+ "218 (BC_0, DDR_BA(2), output3, X, 219, 1, Z), " &\r
+ "217 (BC_0, *, control, 1), " &\r
+ "216 (BC_0, DDR_BA(1), output3, X, 217, 1, Z), " &\r
+ "215 (BC_0, *, control, 1), " &\r
+ "214 (BC_0, DDR_BA(0), output3, X, 215, 1, Z), " &\r
+ "213 (BC_0, *, control, 1), " &\r
+ "212 (BC_0, DDR_CKE, output3, X, 213, 1, Z), " &\r
+ "211 (BC_0, *, control, 1), " &\r
+ "210 (BC_0, DDR_CS, output3, X, 211, 1, Z), " &\r
+ "209 (BC_0, *, control, 1), " &\r
+ "208 (BC_0, DDR_A(13), output3, X, 209, 1, Z), " &\r
+ "207 (BC_0, *, control, 1), " &\r
+ "206 (BC_0, DDR_RESETN, output3, X, 207, 1, Z), " &\r
+ "205 (BC_0, *, control, 1), " &\r
+ "204 (BC_0, DDR_A(5), output3, X, 205, 1, Z), " &\r
+ "203 (BC_0, *, control, 1), " &\r
+ "202 (BC_0, DDR_A(6), output3, X, 203, 1, Z), " &\r
+ "201 (BC_0, *, control, 1), " &\r
+ "200 (BC_0, DDR_RAS, output3, X, 201, 1, Z), " &\r
+ "199 (BC_0, *, control, 1), " &\r
+ "198 (BC_0, DDR_CAS, output3, X, 199, 1, Z), " &\r
+ "197 (BC_0, *, control, 1), " &\r
+ "196 (BC_0, DDR_WE, output3, X, 197, 1, Z), " &\r
+ "195 (BC_0, *, control, 1), " &\r
+ "194 (BC_0, DDR_CLK, output3, X, 195, 1, Z), " &\r
+ "193 (BC_0, *, control, 1), " &\r
+ "192 (BC_0, DDR_A(0), output3, X, 193, 1, Z), " &\r
+ "191 (BC_0, *, control, 1), " &\r
+ "190 (BC_0, DDR_A(1), output3, X, 191, 1, Z), " &\r
+ "189 (BC_0, *, control, 1), " &\r
+ "188 (BC_0, DDR_A(2), output3, X, 189, 1, Z), " &\r
+ "187 (BC_0, *, control, 1), " &\r
+ "186 (BC_0, DDR_A(3), output3, X, 187, 1, Z), " &\r
+ "185 (BC_0, *, control, 1), " &\r
+ "184 (BC_0, DDR_A(4), output3, X, 185, 1, Z), " &\r
+ "183 (BC_0, *, control, 1), " &\r
+ "182 (BC_0, DDR_A(12), output3, X, 183, 1, Z), " &\r
+ "181 (BC_0, *, control, 1), " &\r
+ "180 (BC_0, DDR_A(11), output3, X, 181, 1, Z), " &\r
+ "179 (BC_0, *, control, 1), " &\r
+ "178 (BC_0, DDR_A(10), output3, X, 179, 1, Z), " &\r
+ "177 (BC_0, *, control, 1), " &\r
+ "176 (BC_0, DDR_A(9), output3, X, 177, 1, Z), " &\r
+ "175 (BC_0, *, control, 1), " &\r
+ "174 (BC_0, DDR_A(8), output3, X, 175, 1, Z), " &\r
+ "173 (BC_0, *, control, 1), " &\r
+ "172 (BC_0, DDR_A(7), output3, X, 173, 1, Z), " &\r
+ "171 (BC_1, *, control, 1), " &\r
+ "170 (BC_7, DDR_D(7), bidir, X, 171, 1, Z), " &\r
+ "169 (BC_1, *, control, 1), " &\r
+ "168 (BC_7, DDR_D(6), bidir, X, 169, 1, Z), " &\r
+ "167 (BC_1, *, control, 1), " &\r
+ "166 (BC_7, DDR_D(5), bidir, X, 167, 1, Z), " &\r
+ "165 (BC_1, *, control, 1), " &\r
+ "164 (BC_7, DDR_D(4), bidir, X, 165, 1, Z), " &\r
+ "163 (BC_1, *, control, 1), " &\r
+ "162 (BC_7, DDR_DQS(0), bidir, X, 163, 1, Z), " &\r
+ "161 (BC_1, *, control, 1), " &\r
+ "160 (BC_7, DDR_D(3), bidir, X, 161, 1, Z), " &\r
+ "159 (BC_1, *, control, 1), " &\r
+ "158 (BC_7, DDR_D(2), bidir, X, 159, 1, Z), " &\r
+ "157 (BC_1, *, control, 1), " &\r
+ "156 (BC_7, DDR_D(1), bidir, X, 157, 1, Z), " &\r
+ "155 (BC_1, *, control, 1), " &\r
+ "154 (BC_7, DDR_D(0), bidir, X, 155, 1, Z), " &\r
+ "153 (BC_0, *, control, 1), " &\r
+ "152 (BC_0, DDR_DQM(0), output3, X, 153, 1, Z), " &\r
+ "151 (BC_1, *, control, 1), " &\r
+ "150 (BC_7, DDR_D(23), bidir, X, 151, 1, Z), " &\r
+ "149 (BC_1, *, control, 1), " &\r
+ "148 (BC_7, DDR_D(22), bidir, X, 149, 1, Z), " &\r
+ "147 (BC_1, *, control, 1), " &\r
+ "146 (BC_7, DDR_D(21), bidir, X, 147, 1, Z), " &\r
+ "145 (BC_1, *, control, 1), " &\r
+ "144 (BC_7, DDR_D(20), bidir, X, 145, 1, Z), " &\r
+ "143 (BC_1, *, control, 1), " &\r
+ "142 (BC_7, DDR_DQS(2), bidir, X, 143, 1, Z), " &\r
+ "141 (BC_1, *, control, 1), " &\r
+ "140 (BC_7, DDR_D(19), bidir, X, 141, 1, Z), " &\r
+ "139 (BC_1, *, control, 1), " &\r
+ "138 (BC_7, DDR_D(18), bidir, X, 139, 1, Z), " &\r
+ "137 (BC_1, *, control, 1), " &\r
+ "136 (BC_7, DDR_D(17), bidir, X, 137, 1, Z), " &\r
+ "135 (BC_1, *, control, 1), " &\r
+ "134 (BC_7, DDR_D(16), bidir, X, 135, 1, Z), " &\r
+ "133 (BC_0, *, control, 1), " &\r
+ "132 (BC_0, DDR_DQM(2), output3, X, 133, 1, Z), " &\r
+ "131 (BC_1, *, control, 1), " &\r
+ "130 (BC_7, PD0, bidir, X, 131, 1, Z), " &\r
+ "129 (BC_1, *, control, 1), " &\r
+ "128 (BC_7, PD1, bidir, X, 129, 1, Z), " &\r
+ "127 (BC_1, *, control, 1), " &\r
+ "126 (BC_7, PD2, bidir, X, 127, 1, Z), " &\r
+ "125 (BC_1, *, control, 1), " &\r
+ "124 (BC_7, PC26, bidir, X, 125, 1, Z), " &\r
+ "123 (BC_1, *, control, 1), " &\r
+ "122 (BC_7, PC27, bidir, X, 123, 1, Z), " &\r
+ "121 (BC_1, *, control, 1), " &\r
+ "120 (BC_7, PC28, bidir, X, 121, 1, Z), " &\r
+ "119 (BC_1, *, control, 1), " &\r
+ "118 (BC_7, PC29, bidir, X, 119, 1, Z), " &\r
+ "117 (BC_1, *, control, 1), " &\r
+ "116 (BC_7, PC30, bidir, X, 117, 1, Z), " &\r
+ "115 (BC_1, *, control, 1), " &\r
+ "114 (BC_7, PC31, bidir, X, 115, 1, Z), " &\r
+ "113 (BC_1, *, control, 1), " &\r
+ "112 (BC_7, PB0, bidir, X, 113, 1, Z), " &\r
+ "111 (BC_1, *, control, 1), " &\r
+ "110 (BC_7, PB2, bidir, X, 111, 1, Z), " &\r
+ "109 (BC_1, *, control, 1), " &\r
+ "108 (BC_7, PB1, bidir, X, 109, 1, Z), " &\r
+ "107 (BC_1, *, control, 1), " &\r
+ "106 (BC_7, PB3, bidir, X, 107, 1, Z), " &\r
+ "105 (BC_1, *, control, 1), " &\r
+ "104 (BC_7, PB4, bidir, X, 105, 1, Z), " &\r
+ "103 (BC_1, *, control, 1), " &\r
+ "102 (BC_7, PB5, bidir, X, 103, 1, Z), " &\r
+ "101 (BC_1, *, control, 1), " &\r
+ "100 (BC_7, PB6, bidir, X, 101, 1, Z), " &\r
+ "99 (BC_1, *, control, 1), " &\r
+ "98 (BC_7, PB8, bidir, X, 99, 1, Z), " &\r
+ "97 (BC_1, *, control, 1), " &\r
+ "96 (BC_7, PB7, bidir, X, 97, 1, Z), " &\r
+ "95 (BC_1, *, control, 1), " &\r
+ "94 (BC_7, PB10, bidir, X, 95, 1, Z), " &\r
+ "93 (BC_1, *, control, 1), " &\r
+ "92 (BC_7, PB9, bidir, X, 93, 1, Z), " &\r
+ "91 (BC_1, *, control, 1), " &\r
+ "90 (BC_7, PB11, bidir, X, 91, 1, Z), " &\r
+ "89 (BC_1, *, control, 1), " &\r
+ "88 (BC_7, PB12, bidir, X, 89, 1, Z), " &\r
+ "87 (BC_1, *, control, 1), " &\r
+ "86 (BC_7, PB14, bidir, X, 87, 1, Z), " &\r
+ "85 (BC_1, *, control, 1), " &\r
+ "84 (BC_7, PB13, bidir, X, 85, 1, Z), " &\r
+ "83 (BC_1, *, control, 1), " &\r
+ "82 (BC_7, PB15, bidir, X, 83, 1, Z), " &\r
+ "81 (BC_1, *, control, 1), " &\r
+ "80 (BC_7, PB16, bidir, X, 81, 1, Z), " &\r
+ "79 (BC_1, *, control, 1), " &\r
+ "78 (BC_7, PB17, bidir, X, 79, 1, Z), " &\r
+ "77 (BC_1, *, control, 1), " &\r
+ "76 (BC_7, PB19, bidir, X, 77, 1, Z), " &\r
+ "75 (BC_1, *, control, 1), " &\r
+ "74 (BC_7, PB18, bidir, X, 75, 1, Z), " &\r
+ "73 (BC_1, *, control, 1), " &\r
+ "72 (BC_7, PB20, bidir, X, 73, 1, Z), " &\r
+ "71 (BC_1, *, control, 1), " &\r
+ "70 (BC_7, PB21, bidir, X, 71, 1, Z), " &\r
+ "69 (BC_1, *, control, 1), " &\r
+ "68 (BC_7, PB23, bidir, X, 69, 1, Z), " &\r
+ "67 (BC_1, *, control, 1), " &\r
+ "66 (BC_7, PB22, bidir, X, 67, 1, Z), " &\r
+ "65 (BC_1, *, control, 1), " &\r
+ "64 (BC_7, PB25, bidir, X, 65, 1, Z), " &\r
+ "63 (BC_1, *, control, 1), " &\r
+ "62 (BC_7, PB24, bidir, X, 63, 1, Z), " &\r
+ "61 (BC_1, *, control, 1), " &\r
+ "60 (BC_7, PB26, bidir, X, 61, 1, Z), " &\r
+ "59 (BC_1, *, control, 1), " &\r
+ "58 (BC_7, PB28, bidir, X, 59, 1, Z), " &\r
+ "57 (BC_1, *, control, 1), " &\r
+ "56 (BC_7, PB27, bidir, X, 57, 1, Z), " &\r
+ "55 (BC_1, *, control, 1), " &\r
+ "54 (BC_7, PB30, bidir, X, 55, 1, Z), " &\r
+ "53 (BC_1, *, control, 1), " &\r
+ "52 (BC_7, PB29, bidir, X, 53, 1, Z), " &\r
+ "51 (BC_1, *, control, 1), " &\r
+ "50 (BC_7, PB31, bidir, X, 51, 1, Z), " &\r
+ "49 (BC_1, *, control, 1), " &\r
+ "48 (BC_7, PC9, bidir, X, 49, 1, Z), " &\r
+ "47 (BC_1, *, control, 1), " &\r
+ "46 (BC_7, PC11, bidir, X, 47, 1, Z), " &\r
+ "45 (BC_1, *, control, 1), " &\r
+ "44 (BC_7, PC10, bidir, X, 45, 1, Z), " &\r
+ "43 (BC_1, *, control, 1), " &\r
+ "42 (BC_7, PC12, bidir, X, 43, 1, Z), " &\r
+ "41 (BC_1, *, control, 1), " &\r
+ "40 (BC_7, PC13, bidir, X, 41, 1, Z), " &\r
+ "39 (BC_1, *, control, 1), " &\r
+ "38 (BC_7, PC14, bidir, X, 39, 1, Z), " &\r
+ "37 (BC_1, *, control, 1), " &\r
+ "36 (BC_7, PC15, bidir, X, 37, 1, Z), " &\r
+ "35 (BC_1, *, control, 1), " &\r
+ "34 (BC_7, PC17, bidir, X, 35, 1, Z), " &\r
+ "33 (BC_1, *, control, 1), " &\r
+ "32 (BC_7, PC16, bidir, X, 33, 1, Z), " &\r
+ "31 (BC_1, *, control, 1), " &\r
+ "30 (BC_7, PC19, bidir, X, 31, 1, Z), " &\r
+ "29 (BC_1, *, control, 1), " &\r
+ "28 (BC_7, PC18, bidir, X, 29, 1, Z), " &\r
+ "27 (BC_1, *, control, 1), " &\r
+ "26 (BC_7, PC20, bidir, X, 27, 1, Z), " &\r
+ "25 (BC_1, *, control, 1), " &\r
+ "24 (BC_7, PC21, bidir, X, 25, 1, Z), " &\r
+ "23 (BC_1, *, control, 1), " &\r
+ "22 (BC_7, PC22, bidir, X, 23, 1, Z), " &\r
+ "21 (BC_1, *, control, 1), " &\r
+ "20 (BC_7, PC23, bidir, X, 21, 1, Z), " &\r
+ "19 (BC_1, *, control, 1), " &\r
+ "18 (BC_7, PC24, bidir, X, 19, 1, Z), " &\r
+ "17 (BC_1, *, control, 1), " &\r
+ "16 (BC_7, PC25, bidir, X, 17, 1, Z), " &\r
+ "15 (BC_1, *, control, 1), " &\r
+ "14 (BC_7, PD10, bidir, X, 15, 1, Z), " &\r
+ "13 (BC_1, *, control, 1), " &\r
+ "12 (BC_7, PD9, bidir, X, 13, 1, Z), " &\r
+ "11 (BC_1, *, control, 1), " &\r
+ "10 (BC_7, PD8, bidir, X, 11, 1, Z), " &\r
+ "9 (BC_1, *, control, 1), " &\r
+ "8 (BC_7, PD7, bidir, X, 9, 1, Z), " &\r
+ "7 (BC_1, *, control, 1), " &\r
+ "6 (BC_7, PD6, bidir, X, 7, 1, Z), " &\r
+ "5 (BC_1, *, control, 1), " &\r
+ "4 (BC_7, PD5, bidir, X, 5, 1, Z), " &\r
+ "3 (BC_1, *, control, 1), " &\r
+ "2 (BC_7, PD4, bidir, X, 3, 1, Z), " &\r
+ "1 (BC_1, *, control, 1), " &\r
+ "0 (BC_7, PD3, bidir, X, 1, 1, Z) ";\r
+\r
+ end top;\r
--- /dev/null
+# ----------------------------------------------------------------------------\r
+# SAM Software Package License\r
+# ----------------------------------------------------------------------------\r
+# Copyright (c) 2013, Atmel Corporation\r
+#\r
+# All rights reserved.\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# - Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the disclaimer below.\r
+#\r
+# Atmel's name may not be used to endorse or promote products derived from\r
+# this software without specific prior written permission.\r
+#\r
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+# ----------------------------------------------------------------------------\r
+\r
+CFLAGS_INC += -I$(TOP)/drivers\r
+\r
+lib-y += drivers/drivers.a\r
+\r
+drivers-y :=\r
+\r
+include $(TOP)/drivers/cortex-a/Makefile.inc\r
+include $(TOP)/drivers/memories/Makefile.inc\r
+include $(TOP)/drivers/misc/Makefile.inc\r
+include $(TOP)/drivers/network/Makefile.inc\r
+include $(TOP)/drivers/peripherals/Makefile.inc\r
+include $(TOP)/drivers/power/Makefile.inc\r
+include $(TOP)/drivers/video/Makefile.inc\r
+include $(TOP)/drivers/usb/Makefile.inc\r
+\r
+DRIVERS_OBJS := $(addprefix $(BUILDDIR)/,$(drivers-y))\r
+\r
+-include $(DRIVERS_OBJS:.o=.d)\r
+\r
+$(BUILDDIR)/drivers/drivers.a: $(DRIVERS_OBJS)\r
+ @mkdir -p $(BUILDDIR)/drivers\r
+ $(ECHO) AR $@\r
+ $(Q)$(AR) -cr $@ $^\r
--- /dev/null
+# ----------------------------------------------------------------------------\r
+# SAM Software Package License\r
+# ----------------------------------------------------------------------------\r
+# Copyright (c) 2015, Atmel Corporation\r
+#\r
+# All rights reserved.\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# - Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the disclaimer below.\r
+#\r
+# Atmel's name may not be used to endorse or promote products derived from\r
+# this software without specific prior written permission.\r
+#\r
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+# ----------------------------------------------------------------------------\r
+\r
+drivers-y += drivers/cortex-a/cortexa5_interrupts.o\r
+drivers-y += drivers/cortex-a/cp15.o\r
+drivers-y += drivers/cortex-a/cp15_asm_gcc.o\r
+drivers-y += drivers/cortex-a/cp15_pmu.o\r
+drivers-y += drivers/cortex-a/cpsr_gcc.o\r
+drivers-y += drivers/cortex-a/mmu.o\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Provides the low-level initialization function that called on chip startup.\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "compiler.h"\r
+#include "peripherals/aic.h"\r
+#include "cortexa5_interrupts.h"\r
+#include <stdio.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Constants\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* IFSR status */\r
+static const char* _prefetch_abort_status[32] = {\r
+ NULL,\r
+ NULL,\r
+ "debug event",\r
+ "access flag fault, section",\r
+ NULL,\r
+ "translation fault, section",\r
+ "access flag fault, page",\r
+ "translation fault, page",\r
+ "synchronous external abort",\r
+ "domain fault, section",\r
+ NULL,\r
+ "domain fault, page",\r
+ "L1 translation, synchronous external abort",\r
+ "permission fault, section",\r
+ "L2 translation, synchronous external abort",\r
+ "permission fault, page",\r
+};\r
+\r
+/* DFSR status */\r
+static const char* _data_abort_status[32] = {\r
+ NULL,\r
+ "alignment fault",\r
+ "debug event",\r
+ "access flag fault, section",\r
+ "instruction cache maintenance fault",\r
+ "translation fault, section",\r
+ "access flag fault, page",\r
+ "translation fault, page",\r
+ "synchronous external abort, nontranslation",\r
+ "domain fault, section",\r
+ NULL,\r
+ "domain fault, page",\r
+ "1st level translation, synchronous external abort",\r
+ "permission fault, section",\r
+ "2nd level translation, synchronous external abort",\r
+ "permission fault, page",\r
+ NULL,\r
+ NULL,\r
+ NULL,\r
+ NULL,\r
+ NULL,\r
+ NULL,\r
+ "asynchronous external abort"\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Functions Prototypes\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void default_undefined_instruction_irq_handler(void);\r
+void default_software_interrupt_irq_handler(void);\r
+void default_data_abort_irq_handler(void);\r
+void default_prefetch_abort_irq_handler(void);\r
+\r
+#pragma weak undefined_instruction_irq_handler=default_undefined_instruction_irq_handler\r
+#pragma weak software_interrupt_irq_handler=default_software_interrupt_irq_handler\r
+#pragma weak data_abort_irq_handler=default_data_abort_irq_handler\r
+#pragma weak prefetch_abort_irq_handler=default_prefetch_abort_irq_handler\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Default handler for "Undefined Instruction" exception\r
+ */\r
+void default_undefined_instruction_irq_handler(void)\r
+{\r
+ printf("\n\r");\r
+ printf("#####################\n\r");\r
+ printf("Undefined Instruction\n\r");\r
+ printf("#####################\n\r");\r
+\r
+ asm("bkpt #0");\r
+ while(1);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Default handler for "Software Interrupt" exception\r
+ */\r
+void default_software_interrupt_irq_handler(void)\r
+{\r
+ printf("\n\r");\r
+ printf("##################\n\r");\r
+ printf("Software Interrupt\n\r");\r
+ printf("##################\n\r");\r
+\r
+ asm("bkpt #0");\r
+ while(1);\r
+}\r
+\r
+/**\r
+ * \brief Default handler for "Data Abort" exception\r
+ */\r
+void default_data_abort_irq_handler(void)\r
+{\r
+ uint32_t v1, v2, dfsr;\r
+\r
+ asm("mrc p15, 0, %0, c5, c0, 0" : "=r"(v1));\r
+ asm("mrc p15, 0, %0, c6, c0, 0" : "=r"(v2));\r
+\r
+ printf("\n\r");\r
+ printf("####################\n\r");\r
+ dfsr = ((v1 >> 4) & 0x0F);\r
+ printf("Data Fault occured in %x domain\n\r", (unsigned int)dfsr);\r
+ dfsr = (((v1 & 0x400) >> 6) | (v1 & 0x0F));\r
+ if (_data_abort_status[dfsr])\r
+ printf("Data Fault reason is: %s\n\r", _data_abort_status[dfsr]);\r
+ else\r
+ printf("Data Fault reason is unknown\n\r");\r
+ printf("Data Fault occured at address: 0x%08x\n\n\r", (unsigned int)v2);\r
+ printf("Data Fault status register value: 0x%x\n\r", (unsigned int)v1);\r
+ printf("####################\n\r");\r
+\r
+ asm("bkpt #0");\r
+ while(1);\r
+}\r
+\r
+/**\r
+ * \brief Default handler for "Prefetch Abort" exception\r
+ */\r
+void default_prefetch_abort_irq_handler(void)\r
+{\r
+ uint32_t v1, v2, ifsr;\r
+\r
+ asm("mrc p15, 0, %0, c5, c0, 1" : "=r"(v1));\r
+ asm("mrc p15, 0, %0, c6, c0, 2" : "=r"(v2));\r
+\r
+ printf("\n\r");\r
+ printf("####################\n\r");\r
+ ifsr = (((v1 & 0x400) >> 6) | (v1 & 0x0F));\r
+ if (_prefetch_abort_status[ifsr])\r
+ printf("Prefetch Fault reason is: %s\n\r", _prefetch_abort_status[ifsr]);\r
+ else\r
+ printf("Prefetch Fault reason is unknown\n\r");\r
+ printf("prefetch Fault occured at address: 0x%08x\n\n\r", (unsigned int)v2);\r
+ printf("Prefetch Fault status register value: 0x%x\n\r", (unsigned int)v1);\r
+ printf("####################\n\r");\r
+\r
+ asm("bkpt #0");\r
+ while(1);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Cortex-A5 core interrupt handlers\r
+ *\r
+ */\r
+\r
+#ifndef INTERRUPTS_CORTEXA5_H\r
+#define INTERRUPTS_CORTEXA5_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern WEAK void undefined_instruction_irq_handler(void);\r
+extern WEAK void software_interrupt_irq_handler(void);\r
+extern WEAK void prefetch_abort_irq_handler(void);\r
+extern WEAK void data_abort_irq_handler(void);\r
+\r
+#endif /* INTERRUPTS_CORTEXA5_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//-----------------------------------------------------------------------------\r
+// Reg Reads Writes\r
+//----------------------------------------------------------------------------\r
+// 0 ID code Unpredictable\r
+// 0 cache type Unpredictable\r
+// 0 TCM status Unpredictable\r
+// 1 Control Control\r
+// 2 Translation table base Translation table base\r
+// 3 Domain access control Domain access control\r
+// 4 (Reserved)\r
+// 5 Data fault status Data fault status\r
+// 5 Instruction fault status Instruction fault status\r
+// 6 Fault address Fault address\r
+// 7 cache operations cache operations\r
+// 8 Unpredictable TLB operations\r
+// 9 cache lockdown cache lockdown\r
+// 9 TCM region TCM region\r
+// 10 TLB lockdown TLB lockdown\r
+// 11 (Reserved)\r
+// 12 (Reserved)\r
+// 13 FCSE PID FCSE PID\r
+// 13 Context ID Context ID\r
+// 14 (Reserved)\r
+// 15 Test configuration Test configuration\r
+//-----------------------------------------------------------------------------\r
+\r
+/** \page cp15_f CP15 Functions\r
+ *\r
+ * \section CP15 function Usage\r
+ *\r
+ * Methods to manage the Coprocessor 15. Coprocessor 15, or System Control\r
+ * Coprocessor CP15, is used to configure and control all the items in the\r
+ * list below:\r
+ * <ul>\r
+ * <li> ARM core\r
+ * <li> caches (Icache, Dcache and write buffer)\r
+ * <li> TCM\r
+ * <li> MMU\r
+ * <li> Other system options\r
+ * </ul>\r
+ * \section Usage\r
+ *\r
+ * -# Enable or disable D cache with cp15_enable_dcache() and cp15_disable_dcache()\r
+ * -# Enable or disable I cache with cp15_enable_icache() and cp15_disable_icache()\r
+ *\r
+ * Related files:\n\r
+ * \ref cp15.h\n\r
+ * \ref cp15.c\n\r
+ */\r
+\r
+/** \file */\r
+\r
+/**\r
+ * \addtogroup cp15_cache L1 Cache Operations\r
+ * \ingroup cache_module\r
+ *\r
+ * \section Usage\r
+ *\r
+ * They are performed as MCR instructions and only operate on a level 1 cache associated with\r
+ * ATM v7 processor.\r
+ * The supported operations are:\r
+ * <ul>\r
+ * <li> Any of these operations can be applied to\r
+ * -# any data cache\r
+ * -# any unified cache.\r
+ * <li> Invalidate by MVA\r
+ * Performs an invalidate of a data or unified cache line based on the address it contains.\r
+ * <li> Invalidate by set/way\r
+ * Performs an invalidate of a data or unified cache line based on its location in the cache hierarchy.\r
+ * <li> Clean by MVA\r
+ * Performs a clean of a data or unified cache line based on the address it contains.\r
+ * <li> Clean by set/way\r
+ * Performs a clean of a data or unified cache line based on its location in the cache hierarchy.\r
+ * <li> Clean and Invalidate by MVA\r
+ * Performs a clean and invalidate of a data or unified cache line based on the address it contains.\r
+ * <li> Clean and Invalidate by set/way\r
+ * Performs a clean and invalidate of a data or unified cache line based on its location in the cache hierarchy.\r
+ * </ul>\r
+ *\r
+ * Related files:\n\r
+ * \ref cp15.h\n\r
+ * \ref cp15_asm_gcc.S \n\r
+ * \ref cp15_asm_iar.s \n\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#if defined(__ICCARM__)\r
+ #include <intrinsics.h>\r
+#endif\r
+\r
+#include "cortex-a/cp15.h"\r
+#include "trace.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Check Instruction cache\r
+ * \return 0 if I_cache disable, 1 if I_cache enable\r
+ */\r
+unsigned int cp15_is_icached_enabled(void)\r
+{\r
+ unsigned int control;\r
+ control = cp15_read_control();\r
+ return ((control & (1 << CP15_I_BIT)) != 0);\r
+}\r
+\r
+/**\r
+ * \brief Enable Instruction cache\r
+ */\r
+void cp15_enable_icache(void)\r
+{\r
+ unsigned int control;\r
+ control = cp15_read_control();\r
+ // Check if cache is disabled\r
+ if ((control & (1 << CP15_I_BIT)) == 0) {\r
+ cp15_icache_invalidate();\r
+ control |= (1 << CP15_I_BIT);\r
+ cp15_write_control(control);\r
+ trace_info("I cache enabled.\n\r");\r
+ } else {\r
+\r
+ trace_info("I cache is already enabled.\n\r");\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable Instruction cache\r
+ */\r
+void cp15_disable_icache(void)\r
+{\r
+ unsigned int control;\r
+ control = cp15_read_control();\r
+ // Check if cache is enabled\r
+ if ((control & (1 << CP15_I_BIT)) != 0) {\r
+\r
+ control &= ~(1ul << CP15_I_BIT);\r
+ cp15_write_control(control);\r
+ trace_info("I cache disabled.\n\r");\r
+ } else {\r
+\r
+ trace_info("I cache is already disabled.\n\r");\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Check MMU\r
+ * \return 0 if MMU disable, 1 if MMU enable\r
+ */\r
+unsigned int cp15_is_mmu_enabled(void)\r
+{\r
+ unsigned int control;\r
+ control = cp15_read_control();\r
+ return ((control & (1 << CP15_M_BIT)) != 0);\r
+}\r
+\r
+/**\r
+ * \brief Enable MMU\r
+ */\r
+void cp15_enable_mmu(void)\r
+{\r
+ unsigned int control;\r
+ control = cp15_read_control();\r
+ // Check if MMU is disabled\r
+ if ((control & (1 << CP15_M_BIT)) == 0) {\r
+\r
+ control |= (1 << CP15_M_BIT);\r
+ cp15_write_control(control);\r
+ trace_info("MMU enabled.\n\r");\r
+ } else {\r
+ trace_info("MMU is already enabled.\n\r");\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable MMU\r
+ */\r
+void cp15_disable_mmu(void)\r
+{\r
+ unsigned int control;\r
+ control = cp15_read_control();\r
+ // Check if MMU is enabled\r
+ if ((control & (1 << CP15_M_BIT)) != 0) {\r
+\r
+ control &= ~(1ul << CP15_M_BIT);\r
+ control &= ~(1ul << CP15_C_BIT);\r
+ cp15_write_control(control);\r
+ trace_info("MMU disabled.\n\r");\r
+ } else {\r
+ trace_info("MMU is already disabled.\n\r");\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Check D_cache\r
+ * \return 0 if D_cache disable, 1 if D_cache enable (with MMU of course)\r
+ */\r
+unsigned int cp15_is_dcache_enabled(void)\r
+{\r
+ unsigned int control;\r
+ control = cp15_read_control();\r
+ return ((control & ((1 << CP15_C_BIT) || (1 << CP15_M_BIT))) != 0);\r
+}\r
+\r
+/**\r
+ * \brief Enable Data cache\r
+ */\r
+void cp15_enable_dcache(void)\r
+{\r
+ unsigned int control;\r
+ control = cp15_read_control();\r
+ if (!cp15_is_mmu_enabled()) {\r
+ trace_error("Do nothing: MMU not enabled\n\r");\r
+ } else {\r
+ // Check if cache is disabled\r
+ if ((control & (1 << CP15_C_BIT)) == 0) {\r
+ cp15_dcache_invalidate();\r
+ control |= (1 << CP15_C_BIT);\r
+ cp15_write_control(control);\r
+ trace_info("D cache enabled.\n\r");\r
+ } else {\r
+ trace_info("D cache is already enabled.\n\r");\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable Data cache\r
+ */\r
+void cp15_disable_dcache(void)\r
+{\r
+ unsigned int control;\r
+ control = cp15_read_control();\r
+ // Check if cache is enabled\r
+ if ((control & (1 << CP15_C_BIT)) != 0) {\r
+\r
+ control &= ~(1ul << CP15_C_BIT);\r
+ cp15_write_control(control);\r
+ trace_info("D cache disabled.\n\r");\r
+ } else {\r
+\r
+ trace_info("D cache is already disabled.\n\r");\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Clean Data cache\r
+ */\r
+void cp15_dcache_clean(void)\r
+{\r
+ cp15_select_dcache();\r
+ cp15_clean_dcache_by_set_way();\r
+ asm("DSB");\r
+}\r
+\r
+/**\r
+ * \brief Invalidate Icache\r
+ */\r
+void cp15_icache_invalidate(void)\r
+{\r
+ cp15_select_icache();\r
+ cp15_invalid_icache_inner_sharable();\r
+ asm ("ISB");\r
+}\r
+\r
+/**\r
+ * \brief Invalidate Dcache\r
+ */\r
+void cp15_dcache_invalidate(void)\r
+{\r
+ cp15_select_dcache();\r
+ cp15_invalid_dcache_by_set_way();\r
+ asm ("DSB");\r
+}\r
+\r
+/**\r
+ * \brief Flush(Clean and invalidate) Data cache\r
+ */\r
+void cp15_dcache_flush(void)\r
+{\r
+ cp15_select_dcache();\r
+ cp15_clean_invalid_dcache_by_set_way();\r
+ asm("DSB");\r
+\r
+}\r
+\r
+/**\r
+ * \brief Invalidate Data cache by address\r
+ */\r
+void cp15_invalid_dcache_by_va(uint32_t S_Add, uint32_t E_Add)\r
+{\r
+ cp15_select_dcache();\r
+ cp15_invalid_dcache_by_mva(S_Add, E_Add);\r
+}\r
+\r
+/**\r
+ * \brief Clean Data cache by address\r
+ */\r
+void cp15_clean_dcache_by_va(uint32_t S_Add, uint32_t E_Add)\r
+{\r
+ cp15_select_dcache();\r
+ cp15_clean_dcache_by_mva(S_Add, E_Add);\r
+}\r
+\r
+/**\r
+ * \brief Flush Data cache by address\r
+ */\r
+\r
+void cp15_flush_dcache_by_va(uint32_t S_Add, uint32_t E_Add)\r
+{\r
+ cp15_select_dcache();\r
+ cp15_clean_invalid_dcache_by_mva(S_Add, E_Add);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _CP15_H\r
+#define _CP15_H\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definition\r
+ *----------------------------------------------------------------------------*/\r
+#define CP15_L4_BIT 15 // Determines if the T bit is set when load instructions\r
+// change the PC:\r
+// 0 = loads to PC set the T bit\r
+// 1 = loads to PC do not set T bit\r
+\r
+#define CP15_RR_BIT 14 // RR bit Replacement strategy for Icache and Dcache:\r
+// 0 = Random replacement\r
+// 1 = Round-robin replacement.\r
+\r
+#define CP15_V_BIT 13 // V bit Location of exception vectors:\r
+// 0 = Normal exception vectors selected address range = 0x0000 0000 to 0x0000 001C\r
+// 1 = High exception vect selected, address range = 0xFFFF 0000 to 0xFFFF 001C\r
+\r
+#define CP15_I_BIT 12 // I bit Icache enable/disable:\r
+// 0 = Icache disabled\r
+// 1 = Icache enabled\r
+\r
+#define CP15_R_BIT 9 // R bit ROM protection\r
+\r
+#define CP15_S_BIT 8 // S bit System protection\r
+\r
+#define CP15_B_BIT 7 // B bit Endianness:\r
+// 0 = Little-endian operation\r
+// 1 = Big-endian operation.\r
+\r
+#define CP15_C_BIT 2 // C bit Dcache enable/disable:\r
+// 0 = cache disabled\r
+// 1 = cache enabled\r
+\r
+#define CP15_A_BIT 1 // A bit Alignment fault enable/disable:\r
+// 0 = Data address alignment fault checking disabled\r
+// 1 = Data address alignment fault checking enabled\r
+\r
+#define CP15_M_BIT 0 // M bit MMU enable/disable: 0 = disabled 1 = enabled.\r
+// 0 = disabled\r
+// 1 = enabled\r
+\r
+/** No access Any access generates a domain fault. */\r
+#define CP15_DOMAIN_NO_ACCESS 0x00\r
+/** Client Accesses are checked against the access permission bits in the section or page descriptor. */\r
+#define CP15_DOMAIN_CLIENT_ACCESS 0x01\r
+/** Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated. */\r
+#define CP15_DOMAIN_MANAGER_ACCESS 0x03\r
+\r
+#define CP15_ICache 1\r
+#define CP15_DCache 0\r
+\r
+#define CP15_PMCNTENSET_ENABLE 31\r
+#define CP15_PMCR_DIVIDER 3\r
+#define CP15_PMCR_RESET 2\r
+#define CP15_PMCR_ENABLE 0\r
+\r
+/*------------------------------------------------------------------------------ */\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------ */\r
+\r
+/**\r
+ * \brief Read the Main ID Register (MIDR).\r
+ * \return register contents\r
+ */\r
+extern unsigned int cp15_read_id(void);\r
+\r
+/**\r
+ * \brief Read the System Control Register (SCTLR).\r
+ * \return register contents\r
+ */\r
+extern unsigned int cp15_read_control(void);\r
+\r
+/**\r
+ * \brief Indicate CPU that L2 is in exclusive caching mode.\r
+ */\r
+extern void cp15_exclusive_cache(void);\r
+\r
+/**\r
+ * \brief Allow data to reside in the L1 and L2 caches at the same time.\r
+ */\r
+extern void cp15_non_exclusive_cache(void);\r
+\r
+/**\r
+ * \brief Instruction Synchronization Barrier operation.\r
+ */\r
+extern void cp15_isb(void);\r
+\r
+/**\r
+ * \brief Data Synchronization Barrier operation.\r
+ */\r
+extern void cp15_dsb(void);\r
+\r
+/**\r
+ * \brief Data Memory Barrier operation.\r
+ */\r
+extern void cp15_dmb(void);\r
+\r
+/**\r
+ * \brief Invalidate unified Translation Lookaside Buffer.\r
+ */\r
+extern void cp15_invalidate_tlb(void);\r
+\r
+/**\r
+ * \brief Select the data cache as the one to later retrieve architecture\r
+ * information about.\r
+ */\r
+extern void cp15_select_dcache(void);\r
+\r
+/**\r
+ * \brief Select the instruction cache as the one to later retrieve architecture\r
+ * information about.\r
+ */\r
+extern void cp15_select_icache(void);\r
+\r
+/**\r
+ * \brief Modify the System Control Register (SCTLR).\r
+ * This register specifies the configuration used to enable and disable the\r
+ * caches and MMU.\r
+ * It is recommended that you access this register using a read-modify-\r
+ * write sequence.\r
+ * \param value new value for SCTLR\r
+ */\r
+extern void cp15_write_control(unsigned int value);\r
+\r
+/**\r
+ * \brief ARMv7A architecture supports two translation tables.\r
+ * Configure translation table base (TTB) control register 0.\r
+ * \param value address of our page table base\r
+ */\r
+extern void cp15_write_ttb(unsigned int value);\r
+\r
+/**\r
+ * \brief Modify the Domain Access Control Register (DACR).\r
+ * \param value new value for DACR\r
+ */\r
+extern void cp15_write_domain_access_control(unsigned int value);\r
+\r
+/**\r
+ * \brief Invalidate I cache predictor array to point of unification Inner\r
+ * Shareable.\r
+ */\r
+extern void cp15_invalid_icache_inner_sharable(void);\r
+\r
+/**\r
+ * \brief Invalidate entire branch predictor array Inner Shareable\r
+ */\r
+extern void cp15_invalid_btb_inner_sharable(void);\r
+\r
+/**\r
+ * \brief Invalidate all instruction caches to point of unification.\r
+ * Also flush branch target cache.\r
+ */\r
+extern void cp15_invalid_icache(void);\r
+\r
+/**\r
+ * \brief Invalidate instruction caches by virtual address to point of\r
+ * unification.\r
+ */\r
+extern void cp15_invalid_icache_by_mva(void);\r
+\r
+/**\r
+ * \brief Invalidate entire branch predictor array.\r
+ */\r
+extern void cp15_invalid_btb(void);\r
+\r
+/**\r
+ * \brief Invalidate branch predictor array entry by modified virtual address.\r
+ * \param addr virtual address\r
+ */\r
+extern void cp15_invalid_btb_by_mva(uint32_t addr);\r
+\r
+/**\r
+ * \brief Invalidate entire data cache by set/way.\r
+ * Should be called further to cp15_select_dcache(), not\r
+ * cp15_select_icache().\r
+ */\r
+extern void cp15_invalid_dcache_by_set_way(void);\r
+\r
+/**\r
+ * \brief Clean entire data cache by set/way.\r
+ * Should be called further to cp15_select_dcache(), not\r
+ * cp15_select_icache().\r
+ */\r
+extern void cp15_clean_dcache_by_set_way(void);\r
+\r
+/**\r
+ * \brief Clean and invalidate entire data cache by set/way\r
+ * Should be called further to cp15_select_dcache(), not\r
+ * cp15_select_icache().\r
+ */\r
+extern void cp15_clean_invalid_dcache_by_set_way(void);\r
+\r
+/**\r
+ * \brief Invalidate data cache by virtual address to point of coherency.\r
+ * \param start virtual start address of region\r
+ * \param end virtual end address of region\r
+ */\r
+extern void cp15_invalid_dcache_by_mva(uint32_t start, uint32_t end);\r
+\r
+/**\r
+ * \brief Clean data cache by modified virtual address to point of coherency.\r
+ * \param start virtual start address of region\r
+ * \param end virtual end address of region\r
+ */\r
+extern void cp15_clean_dcache_by_mva(uint32_t start, uint32_t end);\r
+\r
+/**\r
+ * \brief Clean and invalidate data cache by virtual address to point of\r
+ * coherency.\r
+ * \param start virtual start address of region\r
+ * \param end virtual end address of region\r
+ */\r
+extern void cp15_clean_invalid_dcache_by_mva(uint32_t start, uint32_t end);\r
+\r
+/**\r
+ * \brief Clean unified cache by modified virtual address to point of\r
+ * unification.\r
+ */\r
+extern void cp15_clean_dcache_umva(void);\r
+\r
+/**\r
+ * \brief Ensure that the I and D caches are coherent within the specified\r
+ * region. This is typically used when code has been written to\r
+ * a memory region, and will be executed.\r
+ * \param start virtual start address of region\r
+ * \param end virtual end address of region\r
+ */\r
+extern void cp15_coherent_dcache_for_dma(uint32_t start, uint32_t end);\r
+\r
+/**\r
+ * \brief Invalidate the data cache within the specified region; we will\r
+ * be performing a DMA operation in this region and we want to purge the\r
+ * cache of old data. Cache data will be discarded, not flushed.\r
+ * The specified region should be aligned on cache lines. Otherwise mind\r
+ * the data loss that may occur in the collateral part of start/end lines,\r
+ * since cache data won't be flushed.\r
+ * \param start virtual start address of region\r
+ * \param end virtual end address of region\r
+ */\r
+extern void cp15_invalidate_dcache_for_dma(uint32_t start, uint32_t end);\r
+\r
+/**\r
+ * \brief Clean the data cache within the specified region.\r
+ * \param start virtual start address of region\r
+ * \param end virtual end address of region\r
+ */\r
+extern void cp15_clean_dcache_for_dma(uint32_t start, uint32_t end);\r
+\r
+/**\r
+ * \brief Flush, i.e. clean and invalidate, the data cache within the specified\r
+ * region.\r
+ * \param start virtual start address of region\r
+ * \param end virtual end address of region\r
+ */\r
+extern void cp15_flush_dcache_for_dma(uint32_t start, uint32_t end);\r
+\r
+/*------------------------------------------------------------------------------ */\r
+/* Exported functions from CP15.c */\r
+/*------------------------------------------------------------------------------ */\r
+\r
+/** MMU (Status/Enable/Disable) */\r
+extern unsigned int cp15_is_mmu_enabled(void);\r
+extern void cp15_enable_mmu(void);\r
+extern void cp15_disable_mmu(void);\r
+\r
+/** I cache (Status/Enable/Disable) */\r
+extern unsigned int cp15_is_icached_enabled(void);\r
+extern void cp15_enable_icache(void);\r
+extern void cp15_disable_icache(void);\r
+\r
+/** D cache (Status/Enable/Disable) */\r
+extern unsigned int cp15_is_dcache_enabled(void);\r
+extern void cp15_enable_dcache(void);\r
+extern void cp15_disable_dcache(void);\r
+\r
+extern void cp15_dcache_clean(void);\r
+extern void cp15_dcache_invalidate(void);\r
+extern void cp15_icache_invalidate(void);\r
+extern void cp15_dcache_flush(void);\r
+extern void cp15_invalid_dcache_by_va(uint32_t S_Add, uint32_t E_Add);\r
+extern void cp15_clean_dcache_by_va(uint32_t S_Add, uint32_t E_Add);\r
+extern void cp15_flush_dcache_by_va(uint32_t S_Add, uint32_t E_Add);\r
+\r
+#endif // #ifndef _CP15_H\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Functions to access CP15 coprocessor register\r
+ *----------------------------------------------------------------------------*/\r
+\r
+ .section .text.cp15_read_id\r
+ .global cp15_read_id\r
+cp15_read_id:\r
+ mov r0, #0\r
+ mrc p15, 0, r0, c0, c0, 0 // read MIDR\r
+ bx lr\r
+\r
+ .section .text.cp15_isb\r
+ .global cp15_isb\r
+cp15_isb:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c5, 4 // CP15ISB()\r
+ nop\r
+ bx lr\r
+\r
+ .section .text.cp15_dsb\r
+ .global cp15_dsb\r
+cp15_dsb:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c10, 4 // CP15DSB()\r
+ nop\r
+ bx lr\r
+\r
+ .section .text.cp15_dmb\r
+ .global cp15_dmb\r
+cp15_dmb:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c10, 5 // CP15DMB\r
+ nop\r
+ bx lr\r
+\r
+ .section .text.cp15_invalidate_tlb\r
+ .global cp15_invalidate_tlb\r
+cp15_invalidate_tlb:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c8, c7, 0 // TLBIALL()\r
+ dsb\r
+ bx lr\r
+\r
+ .section .text.cp15_exclusive_cache\r
+ .global cp15_exclusive_cache\r
+cp15_exclusive_cache:\r
+ mov r0, #0\r
+ mrc p15, 0, r0, c1, c0, 1 // Read ACTLR\r
+ orr r0, r0, #0x00000080 // Set EXCL\r
+ mcr p15, 0, r0, c1, c0, 1 // Write ACTLR\r
+ nop\r
+ bx lr\r
+\r
+ .section .text.cp15_non_exclusive_cache\r
+ .global cp15_non_exclusive_cache\r
+cp15_non_exclusive_cache:\r
+ mov r0, #0\r
+ mrc p15, 0, r0, c1, c0, 1 // Read ACTLR\r
+ bic r0, r0, #0x00000080 // Clear EXCL\r
+ mcr p15, 0, r0, c1, c0, 1 // Write ACTLR\r
+ nop\r
+ bx lr\r
+\r
+ .section .text.cp15_select_icache\r
+ .global cp15_select_icache\r
+cp15_select_icache:\r
+ mrc p15, 2, r0, c0, c0, 0 // Read CSSELR\r
+ orr r0, r0, #0x1 // Set InD: cache type = ICache\r
+ mcr p15, 2, r0, c0, c0, 0 // Write CSSELR\r
+ nop\r
+ bx lr\r
+\r
+ .section .text.cp15_select_dcache\r
+ .global cp15_select_dcache\r
+cp15_select_dcache:\r
+ mrc p15, 2, r0, c0, c0, 0 // Read CSSELR\r
+ and r0, r0, #0xFFFFFFFE // Clear InD: cache type = DCache\r
+ mcr p15, 2, r0, c0, c0, 0 // Write CSSELR\r
+ nop\r
+ bx lr\r
+\r
+ .section .text.cp15_read_control\r
+ .global cp15_read_control\r
+cp15_read_control:\r
+ mov r0, #0\r
+ mrc p15, 0, r0, c1, c0, 0 // read SCTLR\r
+ bx lr\r
+\r
+ .section .text.cp15_write_control\r
+ .global cp15_write_control\r
+cp15_write_control:\r
+ mcr p15, 0, r0, c1, c0, 0 // rewrite SCTLR\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ bx lr\r
+\r
+ .section .text.cp15_write_domain_access_control\r
+ .global cp15_write_domain_access_control\r
+cp15_write_domain_access_control:\r
+ mcr p15, 0, r0, c3, c0, 0 // rewrite DACR\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ bx lr\r
+\r
+ .section .text.cp15_write_ttb\r
+ .global cp15_write_ttb\r
+cp15_write_ttb:\r
+ mcr p15, 0, r0, c2, c0, 0 // rewrite TTBR0\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ bx lr\r
+\r
+ .section .text.cp15_invalid_icache_inner_sharable\r
+ .global cp15_invalid_icache_inner_sharable\r
+cp15_invalid_icache_inner_sharable:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c1, 0 // ICIALLUIS()\r
+ bx lr\r
+\r
+ .section .text.cp15_invalid_btb_inner_sharable\r
+ .global cp15_invalid_btb_inner_sharable\r
+cp15_invalid_btb_inner_sharable:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c1, 6 // BPIALLIS()\r
+ bx lr\r
+\r
+ .section .text.cp15_invalid_icache\r
+ .global cp15_invalid_icache\r
+cp15_invalid_icache:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c5, 0 // ICIALLU()\r
+ bx lr\r
+\r
+ .section .text.cp15_invalid_icache_by_mva\r
+ .global cp15_invalid_icache_by_mva\r
+cp15_invalid_icache_by_mva:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c5, 1 // ICIMVAU()\r
+ bx lr\r
+\r
+ .section .text.cp15_invalid_btb\r
+ .global cp15_invalid_btb\r
+cp15_invalid_btb:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c5, 6 // BPIALL()\r
+ bx lr\r
+\r
+ .section .text.cp15_invalid_btb_by_mva\r
+ .global cp15_invalid_btb_by_mva\r
+cp15_invalid_btb_by_mva:\r
+ mcr p15, 0, r0, c7, c5, 7 // BPIMVA()\r
+ bx lr\r
+\r
+/***********************************************************\r
+ * Data Cache related maintenance functions\r
+ ***********************************************************/\r
+\r
+ .section .text.cp15_invalid_dcache_by_set_way\r
+ .global cp15_invalid_dcache_by_set_way\r
+cp15_invalid_dcache_by_set_way:\r
+ push {r1-r4}\r
+ mrc p15, 1, r0, c0, c0, 0 // Read CCSIDR\r
+ mov r1, r0, lsr #3 // Get Associativity (num of ways)\r
+ and r1, r1, #3 // 3 is specific to CortexA5 with 32 KB\r
+ mov r2, r0, lsr #13 // Get NumSets (num of sets)\r
+ and r2, r2, #0xFF // 8bit is specific to CortexA5 with 32 KB\r
+ mov r0, #0 // 0:SHL:5\r
+1:\r
+ lsl r4, r1, #30\r
+ mov r3, r2\r
+2:\r
+ orr r0, r4, r3, lsl #5\r
+ mcr p15, 0, r0, c7, c6, 2 // DCISW()\r
+ subs r3, r3, #1 // 1:SHL:30\r
+ bpl 2b\r
+ subs r1, r1, #1\r
+ bpl 1b\r
+ dsb\r
+ pop {r1-r4}\r
+ bx lr\r
+\r
+ .section .text.cp15_clean_dcache_by_set_way\r
+ .global cp15_clean_dcache_by_set_way\r
+cp15_clean_dcache_by_set_way:\r
+ push {r1-r4}\r
+ mrc p15, 1, r0, c0, c0, 0 // Read CCSIDR\r
+ mov r1, r0, lsr #3 // Get Associativity (num of ways)\r
+ and r1, r1, #3 // 3 is specific to CortexA5 with 32 KB\r
+ mov r2, r0, lsr #13 // Get NumSets (num of sets)\r
+ and r2, r2, #0xFF // 8bit is specific to CortexA5 with 32 KB\r
+ mov r0, #0 // 0:SHL:5\r
+1:\r
+ lsl r4, r1, #30\r
+ mov r3, r2\r
+2:\r
+ orr r0, r4, r3, lsl #5\r
+ mcr p15, 0, r0, c7, c10, 2 // DCCSW()\r
+ subs r3, r3, #1 // 1:SHL:30\r
+ bpl 2b\r
+ subs r1, r1, #1\r
+ bpl 1b\r
+ dsb\r
+ pop {r1-r4}\r
+ bx lr\r
+\r
+ .section .text.cp15_clean_invalid_dcache_by_set_way\r
+ .global cp15_clean_invalid_dcache_by_set_way\r
+cp15_clean_invalid_dcache_by_set_way:\r
+ push {r1-r4}\r
+ mrc p15, 1, r0, c0, c0, 0 // Read CCSIDR\r
+ mov r1, r0, lsr #3 // Get Associativity (num of ways)\r
+ and r1, r1, #3 // 3 is specific to CortexA5 with 32 KB\r
+ mov r2, r0, lsr #13 // Get NumSets (num of sets)\r
+ and r2, r2, #0xFF // 8bit is specific to CortexA5 with 32 KB\r
+ mov r0, #0 // 0:SHL:5\r
+1:\r
+ lsl r4, r1, #30\r
+ mov r3, r2\r
+2:\r
+ orr r0, r4, r3, lsl #5\r
+ mcr p15, 0, r0, c7, c14, 2 // DCCISW()\r
+ subs r3, r3, #1 // 1:SHL:30\r
+ bpl 2b\r
+ subs r1, r1, #1\r
+ bpl 1b\r
+ dsb\r
+ pop {r1-r4}\r
+ bx lr\r
+\r
+ .section .text.cp15_invalid_dcache_by_mva\r
+ .global cp15_invalid_dcache_by_mva\r
+cp15_invalid_dcache_by_mva:\r
+ mov r2, #0x20 // Eight words per line, Cortex-A5 L1 Line Size 32 Bytes\r
+ mov r3, r0\r
+inv_loop:\r
+ mcr p15, 0, r0, c7, c6, 1 // DCIMVAC()\r
+ add r3, r3, r2\r
+ cmp r3, r1\r
+ bls inv_loop\r
+ bx lr\r
+\r
+ .section .text.cp15_clean_dcache_by_mva\r
+ .global cp15_clean_dcache_by_mva\r
+cp15_clean_dcache_by_mva:\r
+ mov r2, #0x20 // Eight words per line, Cortex-A5 L1 Line Size 32 Bytes\r
+ mov r3, r0\r
+clean_loop:\r
+ mcr p15, 0, r0, c7, c10, 1 // DCCMVAC()\r
+ add r3, r3, r2\r
+ cmp r3, r1\r
+ bls clean_loop\r
+ bx lr\r
+\r
+ .section .text.cp15_clean_dcache_umva\r
+ .global cp15_clean_dcache_umva\r
+cp15_clean_dcache_umva:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c11, 1 // DCCMVAU()\r
+ bx lr\r
+\r
+ .section .text.cp15_clean_invalid_dcache_by_mva\r
+ .global cp15_clean_invalid_dcache_by_mva\r
+cp15_clean_invalid_dcache_by_mva:\r
+ mov r2, #0x20 // Eight words per line, Cortex-A5 L1 Line Size 32 Bytes\r
+ mov r3, r0\r
+clinv_loop:\r
+ mcr p15, 0, r0, c7, c14, 1 // DCCIMVAC()\r
+ add r3, r3, r2\r
+ cmp r3, r1\r
+ bls clinv_loop\r
+ bx lr\r
+\r
+ .section .text.cp15_coherent_dcache_for_dma\r
+ .global cp15_coherent_dcache_for_dma\r
+cp15_coherent_dcache_for_dma:\r
+ push {r2-r4}\r
+ mrc p15, 0, r3, c0, c0, 1 // read Cache Type Register\r
+ lsr r3, r3, #16\r
+ and r3, r3, #0xf // DminLine\r
+ mov r2, #4\r
+ mov r2, r2, lsl r3 // cache line size, in bytes (4*2^DminLine)\r
+\r
+ sub r3, r2, #1 // cache line mask\r
+ bic r4, r0, r3 // address of the first cache line\r
+1:\r
+ mcr p15, 0, r4, c7, c11, 1 // DCCMVAU()\r
+ add r4, r4, r2\r
+ cmp r4, r1\r
+ blo 1b\r
+ dsb\r
+\r
+ bic r4, r0, r3\r
+2:\r
+ mcr p15, 0, r4, c7, c5, 1 // ICIMVAU()\r
+ add r4, r4, r2\r
+ cmp r4, r1\r
+ blo 2b\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c1, 6 // BPIALLIS()\r
+ mcr p15, 0, r0, c7, c5, 6 // BPIALL()\r
+ dsb\r
+ isb\r
+ pop {r2-r4}\r
+ bx lr\r
+\r
+ .section .text.cp15_invalidate_dcache_for_dma\r
+ .global cp15_invalidate_dcache_for_dma\r
+cp15_invalidate_dcache_for_dma:\r
+ push {r2-r3}\r
+ mrc p15, 0, r3, c0, c0, 1 // read CP15 Cache Type Register\r
+ lsr r3, r3, #16\r
+ and r3, r3, #0xf // DminLine\r
+ mov r2, #4\r
+ mov r2, r2, lsl r3 // cache line size, in bytes (4*2^DminLine)\r
+\r
+ sub r3, r2, #1 // cache line mask\r
+ bic r0, r0, r3 // address of the first cache line\r
+3:\r
+ mcr p15, 0, r0, c7, c6, 1 // CP15:DCIMVAC(r0)\r
+ add r0, r0, r2\r
+ cmp r0, r1 // while ('cache line address' < 'end')\r
+ blo 3b\r
+ dsb\r
+ pop {r2-r3}\r
+ bx lr\r
+\r
+ .section .text.cp15_clean_dcache_for_dma\r
+ .global cp15_clean_dcache_for_dma\r
+cp15_clean_dcache_for_dma:\r
+ mrc p15, 0, r3, c0, c0, 1 // read Cache Type Register\r
+ lsr r3, r3, #16\r
+ and r3, r3, #0xf // DminLine\r
+ mov r2, #4\r
+ mov r2, r2, lsl r3 // cache line size, in bytes (4*2^DminLine)\r
+\r
+ sub r3, r2, #1 // cache line mask\r
+ bic r0, r0, r3 // address of the first cache line\r
+4:\r
+ mcr p15, 0, r0, c7, c10, 1 // DCCMVAC()\r
+ add r0, r0, r2\r
+ cmp r0, r1\r
+ blo 4b\r
+ dsb\r
+ bx lr\r
+\r
+ .section .text.cp15_flush_dcache_for_dma\r
+ .global cp15_flush_dcache_for_dma\r
+cp15_flush_dcache_for_dma:\r
+ mrc p15, 0, r3, c0, c0, 1 // read Cache Type Register\r
+ lsr r3, r3, #16\r
+ and r3, r3, #0xf // DminLine\r
+ mov r2, #4\r
+ mov r2, r2, lsl r3 // cache line size, in bytes (4*2^DminLine)\r
+\r
+ sub r3, r2, #1 // cache line mask\r
+ bic r0, r0, r3 // address of the first cache line\r
+5:\r
+ mcr p15, 0, r0, c7, c14, 1 // DCCIMVAC()\r
+ add r0, r0, r2\r
+ cmp r0, r1\r
+ blo 5b\r
+ dsb\r
+ bx lr\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+ MODULE ?cp15\r
+\r
+ /* Forward declaration of sections. */\r
+ SECTION IRQ_STACK:DATA:NOROOT(2)\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Functions to access CP15 coprocessor register\r
+ *----------------------------------------------------------------------------*/\r
+\r
+ SECTION .cp15_read_id:CODE:NOROOT(2)\r
+ PUBLIC cp15_read_id\r
+cp15_read_id:\r
+ mov r0, #0\r
+ mrc p15, 0, r0, c0, c0, 0 ; read MIDR\r
+ bx lr\r
+\r
+ SECTION .cp15_isb:CODE:NOROOT(2)\r
+ PUBLIC cp15_isb\r
+cp15_isb:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c5, 4 ; CP15ISB()\r
+ nop\r
+ bx lr\r
+\r
+ SECTION .cp15_dsb:CODE:NOROOT(2)\r
+ PUBLIC cp15_dsb\r
+cp15_dsb:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c10, 4 ; CP15DSB()\r
+ nop\r
+ bx lr\r
+\r
+ SECTION .cp15_dmb:CODE:NOROOT(2)\r
+ PUBLIC cp15_dmb\r
+cp15_dmb:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c10, 5 ; CP15DMB()\r
+ nop\r
+ bx lr\r
+\r
+ SECTION .cp15_invalidate_tlb:CODE:NOROOT(2)\r
+ PUBLIC cp15_invalidate_tlb\r
+cp15_invalidate_tlb:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c8, c7, 0 ; TLBIALL()\r
+ dsb\r
+ bx lr\r
+\r
+ SECTION .cp15_exclusive_cache:CODE:NOROOT(2)\r
+ PUBLIC cp15_exclusive_cache\r
+cp15_exclusive_cache:\r
+ mov r0, #0\r
+ mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR\r
+ orr r0, r0, #0x00000080 ; Set EXCL\r
+ mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR\r
+ nop\r
+ bx lr\r
+\r
+ SECTION .cp15_non_exclusive_cache:CODE:NOROOT(2)\r
+ PUBLIC cp15_non_exclusive_cache\r
+cp15_non_exclusive_cache:\r
+ mov r0, #0\r
+ mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR\r
+ bic r0, r0, #0x00000080 ; Clear EXCL\r
+ mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR\r
+ nop\r
+ bx lr\r
+\r
+ SECTION .cp15_select_icache:CODE:NOROOT(2)\r
+ PUBLIC cp15_select_icache\r
+cp15_select_icache:\r
+ mrc p15, 2, r0, c0, c0, 0 ; Read CSSELR\r
+ orr r0, r0, #0x1 ; Set InD: cache type = ICache\r
+ mcr p15, 2, r0, c0, c0, 0 ; Write CSSELR\r
+ nop\r
+ bx lr\r
+\r
+ SECTION .cp15_select_dcache:CODE:NOROOT(2)\r
+ PUBLIC cp15_select_dcache\r
+cp15_select_dcache:\r
+ mrc p15, 2, r0, c0, c0, 0 ; Read CSSELR\r
+ and r0, r0, #0xFFFFFFFE ; Clear InD: cache type = DCache\r
+ mcr p15, 2, r0, c0, c0, 0 ; Write CSSELR\r
+ nop\r
+ bx lr\r
+\r
+ SECTION .cp15_read_control:CODE:NOROOT(2)\r
+ PUBLIC cp15_read_control\r
+cp15_read_control:\r
+ mov r0, #0\r
+ mrc p15, 0, r0, c1, c0, 0 ; read SCTLR\r
+ bx lr\r
+\r
+ SECTION .cp15_write_control:CODE:NOROOT(2)\r
+ PUBLIC cp15_write_control\r
+cp15_write_control:\r
+ mcr p15, 0, r0, c1, c0, 0 ; rewrite SCTLR\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ bx lr\r
+\r
+ SECTION .cp15_write_domain_access_control:CODE:NOROOT(2)\r
+ PUBLIC cp15_write_domain_access_control\r
+cp15_write_domain_access_control:\r
+ mcr p15, 0, r0, c3, c0, 0 ; rewrite DACR\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ bx lr\r
+\r
+ SECTION .cp15_write_ttb:CODE:NOROOT(2)\r
+ PUBLIC cp15_write_ttb\r
+cp15_write_ttb:\r
+ mcr p15, 0, r0, c2, c0, 0 ; rewrite TTBR0\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ bx lr\r
+\r
+ SECTION .cp15_invalid_icache_inner_sharable:CODE:NOROOT(2)\r
+ PUBLIC cp15_invalid_icache_inner_sharable\r
+cp15_invalid_icache_inner_sharable:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c1, 0 ; ICIALLUIS()\r
+ bx lr\r
+\r
+ SECTION .cp15_invalid_btb_inner_sharable:CODE:NOROOT(2)\r
+ PUBLIC cp15_invalid_btb_inner_sharable\r
+cp15_invalid_btb_inner_sharable:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c1, 6 ; BPIALLIS()\r
+ bx lr\r
+\r
+ SECTION .cp15_invalid_icache:CODE:NOROOT(2)\r
+ PUBLIC cp15_invalid_icache\r
+cp15_invalid_icache:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c5, 0 ; ICIALLU()\r
+ bx lr\r
+\r
+ SECTION .cp15_invalid_icache_by_mva:CODE:NOROOT(2)\r
+ PUBLIC cp15_invalid_icache_by_mva\r
+cp15_invalid_icache_by_mva:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c5, 1 ; ICIMVAU()\r
+ bx lr\r
+\r
+ SECTION .cp15_invalid_btb:CODE:NOROOT(2)\r
+ PUBLIC cp15_invalid_btb\r
+cp15_invalid_btb:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c5, 6 ; BPIALL()\r
+ bx lr\r
+\r
+ SECTION .cp15_invalid_btb_by_mva:CODE:NOROOT(2)\r
+ PUBLIC cp15_invalid_btb_by_mva\r
+cp15_invalid_btb_by_mva:\r
+ mcr p15, 0, r0, c7, c5, 7 ; BPIMVA()\r
+ bx lr\r
+\r
+/***********************************************************\r
+ * Data Cache related maintenance functions\r
+ ***********************************************************/\r
+\r
+ SECTION .cp15_invalid_dcache_by_set_way:CODE:NOROOT(2)\r
+ PUBLIC cp15_invalid_dcache_by_set_way\r
+cp15_invalid_dcache_by_set_way:\r
+ push {r1-r4}\r
+ mrc p15, 1, r0, c0, c0, 0 ; Read CCSIDR\r
+ mov r1, r0, lsr #3 ; Get Associativity (num of ways)\r
+ and r1, r1, #3 ; 3 is specific to CortexA5 with 32 KB\r
+ mov r2, r0, lsr #13 ; Get NumSets (num of sets)\r
+ and r2, r2, #0xFF ; 8bit is specific to CortexA5 with 32 KB\r
+ mov r0, #0 ; 0:SHL:5\r
+dinv_way_loop:\r
+ lsl r4, r1, #30\r
+ mov r3, r2\r
+dinv_set_loop:\r
+ orr r0, r4, r3, lsl #5\r
+ mcr p15, 0, r0, c7, c6, 2 ; DCISW()\r
+ subs r3, r3, #1 ; 1:SHL:30\r
+ bpl dinv_set_loop\r
+ subs r1, r1, #1\r
+ bpl dinv_way_loop\r
+ dsb\r
+ pop {r1-r4}\r
+ bx lr\r
+\r
+ SECTION .cp15_clean_dcache_by_set_way:CODE:NOROOT(2)\r
+ PUBLIC cp15_clean_dcache_by_set_way\r
+cp15_clean_dcache_by_set_way:\r
+ push {r1-r4}\r
+ mrc p15, 1, r0, c0, c0, 0 ; Read CCSIDR\r
+ mov r1, r0, lsr #3 ; Get Associativity (num of ways)\r
+ and r1, r1, #3 ; 3 is specific to CortexA5 with 32 KB\r
+ mov r2, r0, lsr #13 ; Get NumSets (num of sets)\r
+ and r2, r2, #0xFF ; 8bit is specific to CortexA5 with 32 KB\r
+ mov r0, #0 ; 0:SHL:5\r
+dclean_way_loop:\r
+ lsl r4, r1, #30\r
+ mov r3, r2\r
+dclean_set_loop:\r
+ orr r0, r4, r3, lsl #5\r
+ mcr p15, 0, r0, c7, c10, 2 ; DCCSW()\r
+ subs r3, r3, #1 ; 1:SHL:30\r
+ bpl dclean_set_loop\r
+ subs r1, r1, #1\r
+ bpl dclean_way_loop\r
+ dsb\r
+ pop {r1-r4}\r
+ bx lr\r
+\r
+ SECTION .cp15_clean_invalid_dcache_by_set_way:CODE:NOROOT(2)\r
+ PUBLIC cp15_clean_invalid_dcache_by_set_way\r
+cp15_clean_invalid_dcache_by_set_way:\r
+ push {r1-r4}\r
+ mrc p15, 1, r0, c0, c0, 0 ; Read CCSIDR\r
+ mov r1, r0, lsr #3 ; Get Associativity (num of ways)\r
+ and r1, r1, #3 ; 3 is specific to CortexA5 with 32 KB\r
+ mov r2, r0, lsr #13 ; Get NumSets (num of sets)\r
+ and r2, r2, #0xFF ; 8bit is specific to CortexA5 with 32 KB\r
+ mov r0, #0 ; 0:SHL:5\r
+dclinv_way_loop:\r
+ lsl r4, r1, #30\r
+ mov r3, r2\r
+dclinv_set_loop:\r
+ orr r0, r4, r3, lsl #5\r
+ mcr p15, 0, r0, c7, c14, 2 ; DCCISW()\r
+ subs r3, r3, #1 ; 1:SHL:30\r
+ bpl dclinv_set_loop\r
+ subs r1, r1, #1\r
+ bpl dclinv_way_loop\r
+ dsb\r
+ pop {r1-r4}\r
+ bx lr\r
+\r
+ SECTION .cp15_invalid_dcache_by_mva:CODE:NOROOT(2)\r
+ PUBLIC cp15_invalid_dcache_by_mva\r
+cp15_invalid_dcache_by_mva:\r
+ mov r2, #0x20 ; Eight words per line, Cortex-A5 L1 Line Size 32 Bytes\r
+ mov r3, r0\r
+inv_loop:\r
+ mcr p15, 0, r0, c7, c6, 1 ; DCIMVAC()\r
+ add r3, r3, r2\r
+ cmp r3, r1\r
+ bls inv_loop\r
+ bx lr\r
+\r
+ SECTION .cp15_clean_dcache_by_mva:CODE:NOROOT(2)\r
+ PUBLIC cp15_clean_dcache_by_mva\r
+cp15_clean_dcache_by_mva:\r
+ mov r2, #0x20 ; Eight words per line, Cortex-A5 L1 Line Size 32 Bytes\r
+ mov r3, r0\r
+clean_loop:\r
+ mcr p15, 0, r0, c7, c10, 1 ; DCCMVAC()\r
+ add r3, r3, r2\r
+ cmp r3, r1\r
+ bls clean_loop\r
+ bx lr\r
+\r
+ SECTION .cp15_clean_dcache_umva:CODE:NOROOT(2)\r
+ PUBLIC cp15_clean_dcache_umva\r
+cp15_clean_dcache_umva:\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c11, 1 ; DCCMVAU()\r
+ bx lr\r
+\r
+ SECTION .cp15_clean_invalid_dcache_by_mva:CODE:NOROOT(2)\r
+ PUBLIC cp15_clean_invalid_dcache_by_mva\r
+cp15_clean_invalid_dcache_by_mva:\r
+ mov r2, #0x20 ; Eight words per line, Cortex-A5 L1 Line Size 32 Bytes\r
+ mov r3, r0\r
+clinv_loop:\r
+ mcr p15, 0, r0, c7, c14, 1 ; DCCIMVAC()\r
+ add r3, r3, r2\r
+ cmp r3, r1\r
+ bls clinv_loop\r
+ bx lr\r
+\r
+ SECTION .cp15_coherent_dcache_for_dma:CODE:NOROOT(2)\r
+ PUBLIC cp15_coherent_dcache_for_dma\r
+cp15_coherent_dcache_for_dma:\r
+ push {r2-r4}\r
+ mrc p15, 0, r3, c0, c0, 1 ; read Cache Type Register\r
+ lsr r3, r3, #16\r
+ and r3, r3, #0xf ; DminLine\r
+ mov r2, #4\r
+ mov r2, r2, lsl r3 ; cache line size, in bytes (4*2^DminLine)\r
+\r
+ sub r3, r2, #1 ; cache line mask\r
+ bic r4, r0, r3 ; address of the first cache line\r
+loop1:\r
+ mcr p15, 0, r4, c7, c11, 1 ; DCCMVAU()\r
+ add r4, r4, r2\r
+ cmp r4, r1\r
+ blo loop1\r
+ dsb\r
+\r
+ bic r4, r0, r3\r
+loop2:\r
+ mcr p15, 0, r4, c7, c5, 1 ; ICIMVAU()\r
+ add r4, r4, r2\r
+ cmp r4, r1\r
+ blo loop2\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c1, 6 ; BPIALLIS()\r
+ mcr p15, 0, r0, c7, c5, 6 ; BPIALL()\r
+ dsb\r
+ isb\r
+ pop {r2-r4}\r
+ bx lr\r
+\r
+ SECTION .cp15_invalidate_dcache_for_dma:CODE:NOROOT(2)\r
+ PUBLIC cp15_invalidate_dcache_for_dma\r
+cp15_invalidate_dcache_for_dma:\r
+ push {r2-r3}\r
+ mrc p15, 0, r3, c0, c0, 1 ; read CP15 Cache Type Register\r
+ lsr r3, r3, #16\r
+ and r3, r3, #0xf ; DminLine\r
+ mov r2, #4\r
+ mov r2, r2, lsl r3 ; cache line size, in bytes (4*2^DminLine)\r
+\r
+ sub r3, r2, #1 ; cache line mask\r
+ bic r0, r0, r3 ; address of the first cache line\r
+loop3:\r
+ mcr p15, 0, r0, c7, c6, 1 ; CP15:DCIMVAC(r0)\r
+ add r0, r0, r2\r
+ cmp r0, r1 ; while ('cache line address' < 'end')\r
+ blo loop3\r
+ dsb\r
+ pop {r2-r3}\r
+ bx lr\r
+\r
+ SECTION .cp15_clean_dcache_for_dma:CODE:NOROOT(2)\r
+ PUBLIC cp15_clean_dcache_for_dma\r
+cp15_clean_dcache_for_dma:\r
+ mrc p15, 0, r3, c0, c0, 1 ; read Cache Type Register\r
+ lsr r3, r3, #16\r
+ and r3, r3, #0xf ; DminLine\r
+ mov r2, #4\r
+ mov r2, r2, lsl r3 ; cache line size, in bytes (4*2^DminLine)\r
+\r
+ sub r3, r2, #1 ; cache line mask\r
+ bic r0, r0, r3 ; address of the first cache line\r
+loop4:\r
+ mcr p15, 0, r0, c7, c10, 1 ; DCCMVAC()\r
+ add r0, r0, r2\r
+ cmp r0, r1\r
+ blo loop4\r
+ dsb\r
+ bx lr\r
+\r
+ SECTION .cp15_flush_dcache_for_dma:CODE:NOROOT(2)\r
+ PUBLIC cp15_flush_dcache_for_dma\r
+cp15_flush_dcache_for_dma:\r
+ mrc p15, 0, r3, c0, c0, 1 ; read Cache Type Register\r
+ lsr r3, r3, #16\r
+ and r3, r3, #0xf ; DminLine\r
+ mov r2, #4\r
+ mov r2, r2, lsl r3 ; cache line size, in bytes (4*2^DminLine)\r
+\r
+ sub r3, r2, #1 ; cache line mask\r
+ bic r0, r0, r3 ; address of the first cache line\r
+loop5:\r
+ mcr p15, 0, r0, c7, c14, 1 ; DCCIMVAC()\r
+ add r0, r0, r2\r
+ cmp r0, r1\r
+ blo loop5\r
+ dsb\r
+ bx lr\r
+\r
+ END\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#if defined(__ICCARM__)\r
+#include <intrinsics.h>\r
+#endif\r
+\r
+#include "cortex-a/cp15_pmu.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Resets the counter and enables/disables all counters including PMCCNTR.\r
+ * \param ResetCounterType CounterType: Performance or Cycle counter\r
+ */\r
+static void cp15_pmu_control(uint8_t ResetCounterType, uint8_t EnableCounter)\r
+{\r
+ uint32_t PMU_Value = 0;\r
+\r
+ asm("mrc p15, 0, %0, c9, c12, 0":"=r"(PMU_Value));\r
+ PMU_Value |= ((ResetCounterType << 1) | EnableCounter);\r
+ asm("mcr p15, 0, %0, c9, c12, 0": :"r"(PMU_Value));\r
+}\r
+\r
+/**\r
+ * \brief Select Cycle Count divider\r
+ * \param Divider 0 for increment of counter at every single cycle or 1 for at every 64th cycle\r
+ */\r
+static void cp15_cycle_count_divider(uint8_t Divider)\r
+{\r
+ uint32_t PMU_Value = 0;\r
+ assert((Divider > 1 ? 0 : 1));\r
+ asm("mrc p15, 0, %0, c9, c12, 0":"=r"(PMU_Value));\r
+ PMU_Value |= (Divider << 3);\r
+ asm("mcr p15, 0, %0, c9, c12, 0": :"r"(PMU_Value));\r
+}\r
+\r
+/**\r
+ * \brief Enables PMCCNTR.\r
+ */\r
+static void cp15_enable_PMCNT(void)\r
+{\r
+ uint32_t CNT_Value = 0;\r
+ asm("mrc p15, 0, %0, c9, c12, 1":"=r"(CNT_Value));\r
+ CNT_Value |= (uint32_t) ((1 << CP15_PMCNTENSET));\r
+ asm("mcr p15, 0, %0, c9, c12, 1": :"r"(CNT_Value));\r
+}\r
+\r
+/**\r
+ * \brief Enables PMCCNTR.\r
+ */\r
+static void cp15_enable_counter(uint8_t Counter)\r
+{\r
+ uint32_t CNT_Value = 0;\r
+ asm("mrc p15, 0, %0, c9, c12, 1":"=r"(CNT_Value));\r
+ CNT_Value |= Counter;\r
+ asm("mcr p15, 0, %0, c9, c12, 1": :"r"(CNT_Value));\r
+}\r
+\r
+/**\r
+ * \brief Disables/clear PMCCNTR.\r
+ * \param Counter 0 or 1 to selct counter\r
+ */\r
+\r
+static void cp15_clear_PMCNT(void)\r
+{\r
+ uint32_t CNT_Value = 0;\r
+ asm("mrc p15, 0, %0, c9, c12, 2":"=r"(CNT_Value));\r
+ CNT_Value |= (uint32_t) (1 << CP15_PMCNTENCLEAR);\r
+ asm("mcr p15, 0, %0, c9, c12, 2": :"r"(CNT_Value));\r
+}\r
+\r
+/**\r
+ * \brief Disables/Enables overflow flag.\r
+ * \param Enable Enables or disables the flag option\r
+ * \param ClearCounterFlag selects the counter flag to clear\r
+ */\r
+void cp15_overflow_status(uint8_t Enable, uint8_t ClearCounterFlag)\r
+{\r
+ uint32_t OFW_Value = 0;\r
+ asm("mrc p15, 0, %0, c9, c12, 3":"=r"(OFW_Value));\r
+ OFW_Value |= ((Enable << 31) | ClearCounterFlag);\r
+ asm("mcr p15, 0, %0, c9, c12, 3": :"r"(OFW_Value));\r
+}\r
+\r
+/**\r
+ * \brief Disables/Enables overflow flag.\r
+ * \param EventCounter Counter of the events\r
+ */\r
+uint32_t cp15_read_overflow_status(uint8_t EventCounter)\r
+{\r
+ uint32_t OFW_Value = 0;\r
+ asm("mrc p15, 0, %0, c9, c12, 3":"=r"(OFW_Value));\r
+ OFW_Value = ((OFW_Value & EventCounter) >> (EventCounter - 1));\r
+ return OFW_Value;\r
+}\r
+\r
+/**\r
+ * \brief Increments the count of a performance monitor count register.\r
+ * \param IncrCounter 0 or 1 counters\r
+ */\r
+void cp15_soft_incr(uint8_t IncrCounter)\r
+{\r
+ uint32_t INRC_Value = 0;\r
+ asm("mrc p15, 0, %0, c9, c12, 4":"=r"(INRC_Value));\r
+ INRC_Value |= IncrCounter;\r
+ asm("mcr p15, 0, %0, c9, c12, 4": :"r"(INRC_Value));\r
+}\r
+\r
+/**\r
+ * \brief Increments the count of a performance monitor count register.\r
+ * \param EventType Select Event Type\r
+ * \param Counter 0 or 1 counters\r
+ */\r
+static void cp15_select_event(PerfEventType EventType, uint8_t Counter)\r
+{\r
+ uint32_t CounterSelect = 0;\r
+ assert((Counter == 1) || (Counter == 2));\r
+ CounterSelect = (Counter & 0x1F);\r
+ asm("mcr p15, 0, %0, c9, c12, 5": :"r"(CounterSelect));\r
+ CounterSelect = (EventType & 0xFF);\r
+ asm("mcr p15, 0, %0, c9, c13, 1": :"r"(CounterSelect));\r
+ // PMXEVTYPER\r
+ asm("mrc p15, 0, %0, c9, c13, 1":"=r"(CounterSelect));\r
+ // PMXEVTYPER\r
+}\r
+\r
+/**\r
+ * \brief Enables USER mode\r
+ */\r
+void cp15_enable_user_mode(void)\r
+{\r
+ uint8_t Value = 1;\r
+ asm("mcr p15, 0, %0, c9, c14, 0": :"r"(Value));\r
+}\r
+\r
+/**\r
+ * \brief Enables Oveflows interrupt\r
+ * \param Enable Enables the Interrupt\r
+ * \param Counter 0 or 1 counters\r
+ */\r
+void cp15_enable_interrupt(uint8_t Enable, uint8_t Counter)\r
+{\r
+ uint32_t ITE_Value = 0;\r
+ ITE_Value |= ((Enable << 31) | Counter);\r
+ asm("mcr p15, 0, %0, c9, c14, 1": :"r"(ITE_Value));\r
+}\r
+\r
+/**\r
+ * \brief Disables Oveflows interrupt\r
+ * \param Disable Disables the Interrupt\r
+ * \param Counter 0 or 1 counters\r
+ */\r
+void cp15_disable_interrupt(uint8_t Disable, uint8_t Counter)\r
+{\r
+ uint32_t ITE_Value = 0;\r
+ ITE_Value |= ((Disable << 31) | Counter);\r
+ asm("mcr p15, 0, %0, c9, c14, 2": :"r"(ITE_Value));\r
+}\r
+\r
+/**\r
+ * \brief Initialize Cycle counter with Divider 64\r
+ */\r
+uint32_t cp15_init_cycle_counter(void)\r
+{\r
+ uint32_t value;\r
+ cp15_clear_PMCNT();\r
+ cp15_enable_PMCNT();\r
+ cp15_overflow_status(true, CP15_BothCounter);\r
+ cp15_cycle_count_divider(CP15_CountDivider64);\r
+ cp15_pmu_control(CP15_ResetCycCounter, true);\r
+\r
+ asm("mrc p15, 0, %0, c9, c13, 0":"=r"(value));\r
+ return value;\r
+\r
+}\r
+\r
+/**\r
+ * \brief Initialize Performance monitor counter with Divider 64\r
+ * \param Event Event type\r
+ * \param Counter 0 or 1 counters\r
+ */\r
+\r
+void cp15_init_perf_counter(PerfEventType Event, uint8_t Counter)\r
+{\r
+ cp15_pmu_control(CP15_ResetPerCounter, true);\r
+ cp15_select_event(Event, Counter);\r
+ cp15_overflow_status(false, CP15_BothCounter);\r
+ cp15_enable_counter(Counter);\r
+}\r
+\r
+/**\r
+ * \brief gives total number of event count\r
+ * \param Counter 0 or 1 counters\r
+ */\r
+uint32_t cp15_count_evt(uint8_t Counter)\r
+{\r
+ uint32_t value;\r
+ asm("mcr p15, 0, %0, c9, c12, 5": :"r"(Counter));\r
+ asm("mrc p15, 0, %0, c9, c13, 2":"=r"(value));\r
+ // PMXEVTYPER\r
+ return (value);\r
+}\r
+\r
+/**\r
+ * \brief gives total number of cycle count\r
+\r
+ */\r
+uint32_t cp15_get_cycle_counter(void)\r
+{\r
+ uint32_t value;\r
+ asm("mrc p15, 0, %0, c9, c13, 0":"=r"(value));\r
+ return value;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _CP15_PMU_H\r
+#define _CP15_PMU_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definition\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define CP15_PMCNTENSET 31\r
+#define CP15_PMCNTENCLEAR 31\r
+#define CP15_PMCR_DIVIDER 3\r
+#define CP15_PMCR_RESET 2\r
+#define CP15_PMCR_ENABLE 0\r
+\r
+#define CP15_NoReset 0\r
+#define CP15_ResetPerCounter 1\r
+#define CP15_ResetCycCounter 2\r
+#define CP15_ResetPerCycCounter 3\r
+\r
+#define CP15_CountDividerSingle 0\r
+#define CP15_CountDivider64 1\r
+\r
+#define CP15_CounterNone 0\r
+#define CP15_Counter0 1\r
+#define CP15_Counter1 2\r
+#define CP15_BothCounter 3\r
+\r
+typedef enum {\r
+ L1_IC_FILL, // Level 1 instruction cache refill\r
+ L1_ITLB_FILL, // Level 1 instruction TLB refill\r
+ L1_DC_FILL, // Level 1 data cache refill\r
+ L1_DC_ACC, // Level 1 data cache access\r
+ L1_DTLB_FILL, // Level 1 data TLB refill\r
+ LOAD, // Load\r
+ STORE, // Store\r
+ InstArchExec, // Instruction architecturally executed\r
+ ExcepetionTaken, // Exception taken\r
+ ExcepetionRet, // Exception return\r
+ WrCONTEXTIDR, // Write to CONTEXTIDR\r
+ SoftPCChange, // Software change of the PC\r
+ ImmBr, // Immediate branch\r
+ ProcRet, // Procedure return\r
+ UnalingedLdStr, // Unaligned load or store\r
+ MispredictedBranchExec, // Mispredicted or not predicted branch speculatively executed\r
+ PredictedBranchExec, // Predictable branch speculatively executed\r
+ DataMemAcc, // Data memory access.\r
+ ICAcc, // Instruction Cache access.\r
+ DCEviction, // Data cache eviction.\r
+ IRQException, // IRQ exception taken.\r
+ FIQException, // FIQ exception taken.\r
+ ExtMemReq, // External memory request.\r
+ NCExtMemReq, // Non-cacheable external memory request\r
+ PrefetchLineFill, // Linefill because of prefetch.\r
+ PrefetchLineDrop, // Prefetch linefill dropped.\r
+ EnteringRAmode, // Entering read allocate mode.\r
+ RAmode, // Read allocate mode.\r
+ reserved, // Reserved, do not use\r
+ DWstallSBFfull // Data Write operation that stalls the pipeline because the store buffer is full.\r
+} PerfEventType;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint32_t cp15_init_cycle_counter(void);\r
+extern uint32_t cp15_get_cycle_counter(void);\r
+\r
+extern uint32_t cp15_read_overflow_status(uint8_t EventCounter);\r
+extern void cp15_overflow_status(uint8_t Enable, uint8_t ClearCounterFlag);\r
+extern void cp15_soft_incr(uint8_t IncrCounter);\r
+\r
+extern uint32_t cp15_count_evt(uint8_t Counter);\r
+extern void cp15_enable_user_mode(void);\r
+extern void cp15_enable_interrupt(uint8_t Enable, uint8_t Counter);\r
+extern void cp15_disable_interrupt(uint8_t Disable, uint8_t Counter);\r
+extern void cp15_init_perf_counter(PerfEventType Event, uint8_t Counter);\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+#ifndef CPSR_HEARDER_\r
+#define CPSR_HEARDER_\r
+\r
+#include <stdint.h>\r
+\r
+#define CPSR_MASK_IRQ 0x00000080\r
+#define CPSR_MASK_FIQ 0x00000040\r
+\r
+extern void v_arm_clr_cpsr_bits(uint32_t mask);\r
+\r
+extern void v_arm_set_cpsr_bits(uint32_t mask);\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Functions to access CPSR\r
+ *----------------------------------------------------------------------------*/\r
+\r
+ .section .text.v_arm_clr_cpsr_bits\r
+ .global v_arm_clr_cpsr_bits\r
+v_arm_clr_cpsr_bits:\r
+ push {r1}\r
+ mrs r1, cpsr\r
+ mvn r0, r0\r
+ and r1, r1,r0\r
+ msr CPSR_c, r1\r
+ pop {r1}\r
+ bx lr\r
+\r
+ .section .text.v_arm_set_cpsr_bits\r
+ .global v_arm_set_cpsr_bits\r
+v_arm_set_cpsr_bits:\r
+ push {r1}\r
+ mrs r1, cpsr\r
+ orr r1, r1, r0\r
+ msr cpsr_c, r1\r
+ pop {r1}\r
+ bx lr\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+ MODULE ?cpsr\r
+\r
+ /* Forward declaration of sections. */\r
+ SECTION IRQ_STACK:DATA:NOROOT(2)\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Functions to access CPSR\r
+ *----------------------------------------------------------------------------*/\r
+\r
+ SECTION .v_arm_clr_cpsr_bits:CODE:NOROOT(2)\r
+ PUBLIC v_arm_clr_cpsr_bits\r
+v_arm_clr_cpsr_bits:\r
+ push {r1}\r
+ mrs r1, cpsr\r
+ mvn r0, r0\r
+ and r1, r1,r0\r
+ msr CPSR_c, r1\r
+ pop {r1}\r
+ bx lr\r
+\r
+ SECTION .v_arm_set_cpsr_bits:CODE:NOROOT(2)\r
+ PUBLIC v_arm_set_cpsr_bits\r
+v_arm_set_cpsr_bits:\r
+ push {r1}\r
+ mrs r1, cpsr\r
+ orr r1, r1, r0\r
+ msr cpsr_c, r1\r
+ pop {r1}\r
+ bx lr\r
+\r
+ END\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/**\r
+ * \addtogroup mmu MMU Initialization\r
+ *\r
+ * \section Usage\r
+ *\r
+ * Translation Lookaside Buffers (TLBs) are an implementation technique that caches translations or\r
+ * translation table entries. TLBs avoid the requirement for every memory access to perform a translation table\r
+ * lookup. The ARM architecture does not specify the exact form of the TLB structures for any design. In a\r
+ * similar way to the requirements for caches, the architecture only defines certain principles for TLBs:\r
+ *\r
+ * The MMU supports memory accesses based on memory sections or pages:\r
+ * Supersections Consist of 16MB blocks of memory. Support for Supersections is optional.\r
+ * -# Sections Consist of 1MB blocks of memory.\r
+ * -# Large pages Consist of 64KB blocks of memory.\r
+ * -# Small pages Consist of 4KB blocks of memory.\r
+ *\r
+ * Access to a memory region is controlled by the access permission bits and the domain field in the TLB entry.\r
+ * Memory region attributes\r
+ * Each TLB entry has an associated set of memory region attributes. These control accesses to the caches,\r
+ * how the write buffer is used, and if the memory region is Shareable and therefore must be kept coherent.\r
+ *\r
+ * Related files:\n\r
+ * \ref mmu.c\n\r
+ * \ref mmu.h \n\r
+ */\r
+\r
+/*------------------------------------------------------------------------------ */\r
+/* Headers */\r
+/*------------------------------------------------------------------------------ */\r
+\r
+#include "chip.h"\r
+#include "board.h"\r
+#include "cortex-a/cp15.h"\r
+#include "cortex-a/mmu.h"\r
+\r
+#include "compiler.h"\r
+\r
+/*------------------------------------------------------------------------------ */\r
+/* Local variables */\r
+/*------------------------------------------------------------------------------ */\r
+\r
+ALIGNED(16384) static uint32_t _tlb[4096];\r
+\r
+/*------------------------------------------------------------------------------ */\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------ */\r
+\r
+void mmu_initialize(void)\r
+{\r
+ board_setup_tlb(_tlb);\r
+ cp15_write_ttb((unsigned int)_tlb);\r
+ /* Program the domain access register */\r
+ /* only domain 15: access are not checked */\r
+ cp15_write_domain_access_control(0xC0000000);\r
+ asm volatile("": : :"memory");\r
+ asm("dsb");\r
+ asm("isb");\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _MMU_\r
+#define _MMU_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define TTB_TYPE(x) ((x) << 0)\r
+#define TTB_TYPE_SECT TTB_TYPE(2)\r
+\r
+#define TTB_SECT_B(x) ((x) << 2)\r
+#define TTB_SECT_WRITE_THROUGH TTB_SECT_B(0)\r
+#define TTB_SECT_WRITE_BACK TTB_SECT_B(1)\r
+\r
+#define TTB_SECT_C(x) ((x) << 3)\r
+#define TTB_SECT_NON_CACHEABLE TTB_SECT_C(0)\r
+#define TTB_SECT_CACHEABLE TTB_SECT_C(1)\r
+\r
+#define TTB_SECT_XN(x) ((x) << 4)\r
+#define TTB_SECT_EXEC TTB_SECT_XN(0)\r
+#define TTB_SECT_EXEC_NEVER TTB_SECT_XN(1)\r
+\r
+#define TTB_SECT_DOMAIN(x) ((x) << 5)\r
+\r
+#define TTB_SECT_AP(x) ((x) << 10)\r
+#define TTB_SECT_APX(x) ((x) << 15)\r
+#define TTB_SECT_AP_PRIV_ONLY (TTB_SECT_APX(0) | TTB_SECT_AP(1))\r
+#define TTB_SECT_AP_NO_USER_WRITE (TTB_SECT_APX(0) | TTB_SECT_AP(2))\r
+#define TTB_SECT_AP_FULL_ACCESS (TTB_SECT_APX(0) | TTB_SECT_AP(3))\r
+#define TTB_SECT_AP_PRIV_READ_ONLY (TTB_SECT_APX(1) | TTB_SECT_AP(1))\r
+#define TTB_SECT_AP_READ_ONLY (TTB_SECT_APX(1) | TTB_SECT_AP(2))\r
+\r
+#define TTB_SECT_TEX(x) ((x) << 12)\r
+#define TTB_SECT_STRONGLY_ORDERED (TTB_SECT_TEX(0) | TTB_SECT_NON_CACHEABLE | TTB_SECT_WRITE_THROUGH)\r
+#define TTB_SECT_SHAREABLE_DEVICE (TTB_SECT_TEX(0) | TTB_SECT_NON_CACHEABLE | TTB_SECT_WRITE_BACK)\r
+#define TTB_SECT_CACHEABLE_WT (TTB_SECT_TEX(0) | TTB_SECT_CACHEABLE | TTB_SECT_WRITE_THROUGH)\r
+#define TTB_SECT_CACHEABLE_WB (TTB_SECT_TEX(0) | TTB_SECT_CACHEABLE | TTB_SECT_WRITE_BACK)\r
+\r
+#define TTB_SECT_ADDR(x) ((x) & 0xFFF00000)\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief initializes the MMU\r
+ */\r
+extern void mmu_initialize(void);\r
+\r
+#endif /* #ifndef _MMU_ */\r
--- /dev/null
+# ----------------------------------------------------------------------------\r
+# SAM Software Package License\r
+# ----------------------------------------------------------------------------\r
+# Copyright (c) 2015, Atmel Corporation\r
+#\r
+# All rights reserved.\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# - Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the disclaimer below.\r
+#\r
+# Atmel's name may not be used to endorse or promote products derived from\r
+# this software without specific prior written permission.\r
+#\r
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+# ----------------------------------------------------------------------------\r
+\r
+drivers-y += drivers/misc/console.o\r
+drivers-y += drivers/misc/led.o\r
+\r
+drivers-$(CONFIG_SOC_SAMA5D2) += drivers/misc/bmp280.o
\ No newline at end of file
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation BMP280 driver.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "chip.h"\r
+#include "math.h"\r
+#include "misc/bmp280.h"\r
+#include "peripherals/pio.h"\r
+#include "peripherals/twid.h"\r
+#include "peripherals/twi.h"\r
+#include <stdio.h>\r
+#include <stdint.h>\r
+#include <string.h>\r
+#include <assert.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define EPSILON (1e-10)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static uint8_t _bmp280_read(struct _bmp280* bmp280, uint8_t* buffer, uint32_t len)\r
+{\r
+ struct _buffer in = {\r
+ .data = buffer,\r
+ .size = len\r
+ };\r
+ return (uint8_t)twid_transfert(bmp280->twid, &in, 0, twid_finish_transfert_callback, 0);\r
+}\r
+\r
+static uint8_t _bmp280_write(struct _bmp280* bmp280, const uint8_t* buffer, uint32_t len)\r
+{\r
+ struct _buffer out = {\r
+ .data = (uint8_t*)buffer,\r
+ .size = len\r
+ };\r
+ return (uint8_t)twid_transfert(bmp280->twid, 0, &out, twid_finish_transfert_callback, 0);\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* Write the data to the given register\r
+ *\r
+ * Param addr -> Address of the register\r
+ * data -> The data from the register\r
+ * len -> no of bytes to read\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_write_register(struct _bmp280* bmp280, uint8_t addr, uint8_t* pdata, uint8_t len)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ bmp280->twid->iaddr = addr;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_write(bmp280, pdata, len);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Reads the data from the given register\r
+ *\r
+ * Param addr -> Address of the register\r
+ * data -> The data from the register\r
+ * len -> no of bytes to read\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_read_register(struct _bmp280* bmp280, uint8_t addr, uint8_t* pdata, uint8_t len)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ bmp280->twid->iaddr = addr;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, pdata, len);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/*\r
+ * Read uncompensated temperature in the registers\r
+ * 0xFA, 0xFB and 0xFC\r
+ * 0xFA -> MSB -> bit from 0 to 7\r
+ * 0xFB -> LSB -> bit from 0 to 7\r
+ * 0xFC -> LSB -> bit from 4 to 7\r
+ *\r
+ * Param uncT : The uncompensated temperature.\r
+ *\r
+ * Return results of bus communication function\r
+ * 0 -> Success\r
+ * -1 -> Error\r
+ */\r
+uint8_t bmp280_read_uncompensed_temperature (struct _bmp280* bmp280, int32_t* uncT)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ /* Array holding the MSB and LSb value\r
+ dt[0] - Temperature MSB\r
+ dt[1] - Temperature LSB\r
+ dt[2] - Temperature LSB\r
+ */\r
+ uint8_t dt[3] = {0};\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* read temperature data */\r
+ bmp280->twid->iaddr = BMP280_TEMPERATURE_MSB_REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &dt[0], 3);\r
+ *uncT = (int32_t)((((uint32_t) (dt[0])) << 12) |\r
+ (((uint32_t)(dt[1])) << 4) | ((uint32_t)dt[2] >> 4));\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Reads actual temperature from uncompensated temperature\r
+ * Returns the value in 0.01 degree Centigrade\r
+ * Output value of "5123" equals 51.23 DegC.\r
+ *\r
+ * param uncT : value of uncompensated temperature\r
+ *\r
+ * return Actual temperature output as s32\r
+ */\r
+int32_t bmp280_compensate_temperatureC (struct _bmp280* bmp280, int32_t uncT)\r
+{\r
+ int32_t x1 = 0;\r
+ int32_t x2 = 0;\r
+ int32_t temperature = 0;\r
+\r
+ /* calculate true temperature*/\r
+ x1 = ((((uncT >> 3) - ((int32_t)bmp280->calpar.dig_T1\r
+ << 1))) * ((int32_t)bmp280->calpar.dig_T2)) >> 11;\r
+ x2 = (((((uncT >> 4) - ((int32_t)bmp280->calpar.dig_T1)) *\r
+ ((uncT >> 4) - ((int32_t)bmp280->calpar.dig_T1)))\r
+ >> 12) * ((int32_t)bmp280->calpar.dig_T3)) >> 14;\r
+ bmp280->calpar.t_fine = x1 + x2;\r
+ temperature = (bmp280->calpar.t_fine * BMP280_DEC_TRUE_TEMP_5 +\r
+ BMP280_DEC_TRUE_TEMP_128) >> 8;\r
+ return temperature;\r
+}\r
+\r
+/* Read uncompensated pressure.\r
+ * in the registers 0xF7, 0xF8 and 0xF9\r
+ * 0xF7 -> MSB -> bit from 0 to 7\r
+ * 0xF8 -> LSB -> bit from 0 to 7\r
+ * 0xF9 -> LSB -> bit from 4 to 7\r
+ *\r
+ * param uncP : The value of uncompensated pressure\r
+ *\r
+ * return results of bus communication function\r
+ * 0 -> Success\r
+ * -1 -> Error\r
+ */\r
+uint8_t bmp280_read_uncompensed_pressure (struct _bmp280* bmp280, int32_t* uncP)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ /* Array holding the MSB and LSb value\r
+ dt[0] - Pressure MSB\r
+ dt[1] - Pressure LSB\r
+ dt[2] - Pressure LSB\r
+ */\r
+ uint8_t dt[3] = {0};\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ bmp280->twid->iaddr = BMP280_PRESSURE_MSB_REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &dt[0], 3);\r
+ *uncP = (int32_t)((((uint32_t)(dt[0])) << 12) |\r
+ (((uint32_t)(dt[1])) << 4) | ((uint32_t)dt[2] >> 4));\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/*\r
+ * Reads actual pressure from uncompensated pressure and returns the value in\r
+ * Pascal(Pa)\r
+ *\r
+ * Note: Output value of "96386" equals 96386 Pa = 963.86 hPa = 963.86 millibar\r
+ *\r
+ * Param uncP: value of uncompensated pressure\r
+ *\r
+ * Return Returns the Actual pressure out put as s32\r
+ */\r
+uint32_t bmp280_compensate_pressureP (struct _bmp280* bmp280, int32_t uncP)\r
+{\r
+ int32_t x1 = 0;\r
+ int32_t x2 = 0;\r
+ uint32_t pressure = 0;\r
+\r
+ /* calculate true pressure*/\r
+ x1 = (((int32_t)bmp280->calpar.t_fine) >> 1) - (int32_t)BMP280_DEC_TRUE_PRES_64000;\r
+ x2 = (((x1 >> 2) * (x1 >> 2)) >> 11) * ((int32_t)bmp280->calpar.dig_P6);\r
+ x2 = x2 + ((x1 * ((int32_t)bmp280->calpar.dig_P5)) << 1);\r
+ x2 = (x2 >> 2) + (((int32_t)bmp280->calpar.dig_P4) << 16);\r
+ x1 = (((bmp280->calpar.dig_P3 * (((x1 >> 2) * (x1 >> 2)) >> 13)) >> 3) +\r
+ ((((int32_t)bmp280->calpar.dig_P2) * x1) >> 1)) >> 18;\r
+ x1 = ((((BMP280_DEC_TRUE_PRES_32768 + x1)) * ((int32_t)bmp280->calpar.dig_P1)) >> 15);\r
+ pressure = (((uint32_t)(((int32_t)BMP280_DEC_TRUE_PRES_1048576) - uncP) -\r
+ (x2 >> 12))) * BMP280_DEC_TRUE_PRES_3125;\r
+\r
+ if (pressure < BMP280_HEX_TRUE_PRES_8M)\r
+ /* Avoid exception caused by division by zero */\r
+ if (x1 != 0)\r
+ pressure = (pressure << 1) / ((uint32_t)x1);\r
+ else\r
+ return 0;\r
+ else\r
+ /* Avoid exception caused by division by zero */\r
+ if (x1 != 0)\r
+ pressure = (pressure / (uint32_t)x1) * BMP280_DEC_TRUE_PRES_2;\r
+ else\r
+ return 0;\r
+\r
+ x1 = (((int32_t)bmp280->calpar.dig_P9)* ((int32_t)(((pressure>>3)* (pressure>>3))>>13)))>>12 ;\r
+ x2 = (((int32_t)(pressure >> 2))*((int32_t)bmp280->calpar.dig_P8))>>13;\r
+ pressure = (uint32_t)((int32_t)pressure + ((x1 + x2 + bmp280->calpar.dig_P7)>>4));\r
+\r
+ return pressure;\r
+}\r
+\r
+\r
+/*\r
+ * Reads uncompensated pressure and temperature\r
+ *\r
+ * Param uncP: The value of uncompensated pressure.\r
+ * uncT: The value of uncompensated temperature.\r
+ *\r
+ * Return results of bus communication function\r
+ * 0 -> Success\r
+ * -1 -> Error\r
+ */\r
+uint8_t bmp280_read_uncompensed_pressure_temperature (struct _bmp280* bmp280, int32_t* uncP, int32_t* uncT)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+\r
+ /* Array holding the temperature and pressure data\r
+ dt[0] - Pressure MSB\r
+ dt[1] - Pressure LSB\r
+ dt[2] - Pressure LSB\r
+ dt[3] - Temperature MSB\r
+ dt[4] - Temperature LSB\r
+ dt[5] - Temperature LSB\r
+ */\r
+ uint8_t dt[6] = {0};\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ bmp280->twid->iaddr = BMP280_PRESSURE_MSB_REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &dt[0], 6);\r
+ /*Pressure*/\r
+ *uncP = (int32_t)((((uint32_t)(dt[0]))<<12) | (((uint32_t)(dt[1]))<<4) | ((uint32_t)dt[2]>>4));\r
+ /* Temperature */\r
+ *uncT = (int32_t)((((uint32_t)(dt[3]))<<12) | (((uint32_t)(dt[4]))<<4) | ((uint32_t)dt[5]>>4));\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/*\r
+ * Reads the true pressure and temperature\r
+ *\r
+ * Param pressure : The value of compensated pressure.\r
+ * temperature : The value of compensated temperature.\r
+ *\r
+ * Return results of bus communication function\r
+ * 0 -> Success\r
+ * -1 -> Error\r
+ */\r
+\r
+uint8_t bmp280_read_pressure_temperature (struct _bmp280* bmp280, uint32_t* pressure, int32_t* temperature)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ int32_t uncP = 0;\r
+ int32_t uncT = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* read uncompensated pressure and temperature*/\r
+ com_rslt = bmp280_read_uncompensed_pressure_temperature(bmp280, &uncP, &uncT);\r
+ /* read true pressure and temperature*/\r
+ *temperature = bmp280_compensate_temperatureC(bmp280, uncT);\r
+ *pressure = bmp280_compensate_pressureP(bmp280, uncP);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/*\r
+ * Calibration parameters used for calculation in the registers\r
+ *\r
+ * parameter | Register address | bit\r
+ *------------|------------------|----------------\r
+ * dig_T1 | 0x88 and 0x89 | from 0 : 7 to 8: 15\r
+ * dig_T2 | 0x8A and 0x8B | from 0 : 7 to 8: 15\r
+ * dig_T3 | 0x8C and 0x8D | from 0 : 7 to 8: 15\r
+ * dig_P1 | 0x8E and 0x8F | from 0 : 7 to 8: 15\r
+ * dig_P2 | 0x90 and 0x91 | from 0 : 7 to 8: 15\r
+ * dig_P3 | 0x92 and 0x93 | from 0 : 7 to 8: 15\r
+ * dig_P4 | 0x94 and 0x95 | from 0 : 7 to 8: 15\r
+ * dig_P5 | 0x96 and 0x97 | from 0 : 7 to 8: 15\r
+ * dig_P6 | 0x98 and 0x99 | from 0 : 7 to 8: 15\r
+ * dig_P7 | 0x9A and 0x9B | from 0 : 7 to 8: 15\r
+ * dig_P8 | 0x9C and 0x9D | from 0 : 7 to 8: 15\r
+ * dig_P9 | 0x9E and 0x9F | from 0 : 7 to 8: 15\r
+ *\r
+ * Return results of bus communication function\r
+ * 0 -> Success\r
+ * -1 -> Error\r
+ */\r
+uint8_t bmp280_get_calpar (struct _bmp280* bmp280)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t dt[26] = {0};\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ bmp280->twid->iaddr = BMP280_DIG_T1_LSB_REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &dt[0], 24);\r
+ /* read calibration values*/\r
+ bmp280->calpar.dig_T1 = (uint16_t)((((uint16_t)((uint8_t)dt[1])) << 8) | dt[0]);\r
+ bmp280->calpar.dig_T2 = (int16_t)((((int16_t)((int8_t)dt[3])) << 8) | dt[2]);\r
+ bmp280->calpar.dig_T3 = (int16_t)((((int16_t)((int8_t)dt[5])) << 8) | dt[4]);\r
+ bmp280->calpar.dig_P1 = (uint16_t)((((uint16_t)((uint8_t)dt[7])) << 8) | dt[6]);\r
+ bmp280->calpar.dig_P2 = (int16_t)((((int16_t)((int8_t)dt[9])) << 8) | dt[8]);\r
+ bmp280->calpar.dig_P3 = (int16_t)((((int16_t)((int8_t)dt[11])) << 8) | dt[10]);\r
+ bmp280->calpar.dig_P4 = (int16_t)((((int16_t)((int8_t)dt[13])) << 8) | dt[12]);\r
+ bmp280->calpar.dig_P5 = (int16_t)((((int16_t)((int8_t)dt[15])) << 8) | dt[14]);\r
+ bmp280->calpar.dig_P6 = (int16_t)((((int16_t)((int8_t)dt[17])) << 8) | dt[16]);\r
+ bmp280->calpar.dig_P7 = (int16_t)((((int16_t)((int8_t)dt[19])) << 8) | dt[18]);\r
+ bmp280->calpar.dig_P8 = (int16_t)((((int16_t)((int8_t)dt[21])) << 8) | dt[20]);\r
+ bmp280->calpar.dig_P9 = (int16_t)((((int16_t)((int8_t)dt[23])) << 8) | dt[22]);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Get the temperature oversampling setting in the register 0xF4\r
+ * bits from 5 to 7\r
+ *\r
+ * value | Temperature oversampling\r
+ * ------------------------|------------------------------\r
+ * 0x00 | Skipped\r
+ * 0x01 | BMP280_OVERSAMP_1X\r
+ * 0x02 | BMP280_OVERSAMP_2X\r
+ * 0x03 | BMP280_OVERSAMP_4X\r
+ * 0x04 | BMP280_OVERSAMP_8X\r
+ * 0x05,0x06 and 0x07 | BMP280_OVERSAMP_16X\r
+ *\r
+ * Param: value :The value of temperature over sampling\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_get_overs_temp (struct _bmp280* bmp280, uint8_t* value)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* read temperature over sampling*/\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG_OVRS_TEMP__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ *value = BMP280_GET_BITSLICE(data, BMP280_CTRL_MEAS_REG_OVRS_TEMP);\r
+ /* assign temperature oversampling*/\r
+ bmp280->overs_temp = *value;\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Set the temperature oversampling setting in the register 0xF4\r
+ * bits from 5 to 7\r
+ *\r
+ * value | Temperature oversampling\r
+ * ------------------------|------------------------------\r
+ * 0x00 | Skipped\r
+ * 0x01 | BMP280_OVERSAMP_1X\r
+ * 0x02 | BMP280_OVERSAMP_2X\r
+ * 0x03 | BMP280_OVERSAMP_4X\r
+ * 0x04 | BMP280_OVERSAMP_8X\r
+ * 0x05,0x06 and 0x07 | BMP280_OVERSAMP_16X\r
+ *\r
+ * Param: value :The value of temperature over sampling\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_set_overs_temp (struct _bmp280* bmp280, uint8_t value)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG_OVRS_TEMP__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ if (com_rslt == SUCCESS) {\r
+ /* write over sampling*/\r
+ data = BMP280_SET_BITSLICE(data, BMP280_CTRL_MEAS_REG_OVRS_TEMP, value);\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG_OVRS_TEMP__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_write(bmp280, &data, 1);\r
+ bmp280->overs_temp = value;\r
+ }\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Get the pressure oversampling setting in the register 0xF4\r
+ * bits from 2 to 4\r
+ *\r
+ * value | Pressure oversampling\r
+ * ------------------------|------------------------------\r
+ * 0x00 | Skipped\r
+ * 0x01 | BMP280_OVERSAMP_1X\r
+ * 0x02 | BMP280_OVERSAMP_2X\r
+ * 0x03 | BMP280_OVERSAMP_4X\r
+ * 0x04 | BMP280_OVERSAMP_8X\r
+ * 0x05,0x06 and 0x07 | BMP280_OVERSAMP_16X\r
+ *\r
+ * Param: value : The value of pressure over sampling\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_get_overs_pres (struct _bmp280* bmp280, uint8_t* value)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* read pressure over sampling */\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG_OVRS_PRES__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ *value = BMP280_GET_BITSLICE(data, BMP280_CTRL_MEAS_REG_OVRS_PRES);\r
+ bmp280->overs_pres = *value;\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Set the pressure oversampling setting in the register 0xF4\r
+ * bits from 2 to 4\r
+ *\r
+ * value | Pressure oversampling\r
+ * ------------------------|------------------------------\r
+ * 0x00 | Skipped\r
+ * 0x01 | BMP280_OVERSAMP_1X\r
+ * 0x02 | BMP280_OVERSAMP_2X\r
+ * 0x03 | BMP280_OVERSAMP_4X\r
+ * 0x04 | BMP280_OVERSAMP_8X\r
+ * 0x05,0x06 and 0x07 | BMP280_OVERSAMP_16X\r
+ *\r
+ * Param: value : The value of pressure over sampling\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_set_overs_pres (struct _bmp280* bmp280, uint8_t value)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG_OVRS_PRES__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ if (com_rslt == SUCCESS) {\r
+ /* write pressure over sampling */\r
+ data = BMP280_SET_BITSLICE(data, BMP280_CTRL_MEAS_REG_OVRS_PRES, value);\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG_OVRS_PRES__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_write(bmp280, &data, 1);\r
+ bmp280->overs_pres = value;\r
+ }\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Get the operational Mode from the sensor in the register 0xF4 bit 0 and 1\r
+ *\r
+ * Param: power_mode : The value of power mode value\r
+ * value | Power mode\r
+ * ------------------|------------------\r
+ * 0x00 | BMP280_SLEEP_MODE\r
+ * 0x01 and 0x02 | BMP280_FORCED_MODE\r
+ * 0x03 | BMP280_NORMAL_MODE\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_get_power_mode(struct _bmp280* bmp280, uint8_t* power_mode)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t mode = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* read the power mode*/\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG_POWER_MODE__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &mode, 1);\r
+ *power_mode = BMP280_GET_BITSLICE(mode, BMP280_CTRL_MEAS_REG_POWER_MODE);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Set the operational Mode from the sensor in the register 0xF4 bit 0 and 1\r
+ *\r
+ * Param: power_mode : The value of power mode value\r
+ * value | Power mode\r
+ * ------------------|------------------\r
+ * 0x00 | BMP280_SLEEP_MODE\r
+ * 0x01 and 0x02 | BMP280_FORCED_MODE\r
+ * 0x03 | BMP280_NORMAL_MODE\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_set_power_mode (struct _bmp280* bmp280, uint8_t power_mode)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t mode = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else\r
+ {\r
+ if (power_mode < 4) {\r
+ /* write the power mode*/\r
+ mode = (bmp280->overs_temp << 5) + (bmp280->overs_pres << 2) + power_mode;\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG_POWER_MODE__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_write(bmp280, &mode, 1);\r
+ }\r
+ else {\r
+ com_rslt = E_BMP280_OUT_OF_RANGE;\r
+ }\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Reset the sensor\r
+ * The value 0xB6 is written to the 0xE0 register the device is reset using the\r
+ * complete power-on-reset procedure.\r
+ * Softreset can be easily set using bmp280_set_softreset().\r
+ *\r
+ * Note Usage Hint : bmp280_set_softreset()\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_set_soft_rst (struct _bmp280* bmp280)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = BMP280_SOFT_RESET_CODE;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* write soft reset */\r
+ bmp280->twid->iaddr = BMP280_RST_REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_write(bmp280, &data, 1);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Get the sensor SPI mode(communication type) in the register 0xF5 bit 0\r
+ *\r
+ * Param: enable_disable : The spi3 enable or disable state\r
+ * value | Description\r
+ * -----------|---------------\r
+ * 0 | Disable\r
+ * 1 | Enable\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_get_spi3 (struct _bmp280* bmp280, uint8_t* enable_disable)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ bmp280->twid->iaddr = BMP280_CONFIG_REG_SPI3_ENABLE__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ *enable_disable = BMP280_GET_BITSLICE(data, BMP280_CONFIG_REG_SPI3_ENABLE);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Set the sensor SPI mode(communication type) in the register 0xF5 bit 0\r
+ *\r
+ * Param: enable_disable : The spi3 enable or disable state\r
+ * value | Description\r
+ * -----------|---------------\r
+ * 0 | Disable\r
+ * 1 | Enable\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_set_spi3 (struct _bmp280* bmp280, uint8_t enable_disable)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ bmp280->twid->iaddr = BMP280_CONFIG_REG_SPI3_ENABLE__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ if (com_rslt == SUCCESS) {\r
+ data = BMP280_SET_BITSLICE(data, BMP280_CONFIG_REG_SPI3_ENABLE, enable_disable);\r
+ bmp280->twid->iaddr = BMP280_CONFIG_REG_SPI3_ENABLE__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_write(bmp280, &data, 1);\r
+ }\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Reads filter setting in the register 0xF5 bit 3 and 4\r
+ *\r
+ * Param value : The value of filter coefficient\r
+ * value | Filter coefficient\r
+ * -------------|-------------------------\r
+ * 0x00 | BMP280_FILTER_COEFF_OFF\r
+ * 0x01 | BMP280_FILTER_COEFF_2\r
+ * 0x02 | BMP280_FILTER_COEFF_4\r
+ * 0x03 | BMP280_FILTER_COEFF_8\r
+ * 0x04 | BMP280_FILTER_COEFF_16\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_get_filter (struct _bmp280* bmp280, uint8_t *value)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* read filter*/\r
+ bmp280->twid->iaddr = BMP280_CONFIG_REG_FILTER__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ *value = BMP280_GET_BITSLICE(data, BMP280_CONFIG_REG_FILTER);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Write filter setting in the register 0xF5 bit 3 and 4\r
+ *\r
+ * Param value : The value of filter coefficient\r
+ * value | Filter coefficient\r
+ * -------------|-------------------------\r
+ * 0x00 | BMP280_FILTER_COEFF_OFF\r
+ * 0x01 | BMP280_FILTER_COEFF_2\r
+ * 0x02 | BMP280_FILTER_COEFF_4\r
+ * 0x03 | BMP280_FILTER_COEFF_8\r
+ * 0x04 | BMP280_FILTER_COEFF_16\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_set_filter (struct _bmp280* bmp280, uint8_t value)\r
+{\r
+ uint8_t com_rslt = SUCCESS;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* write filter*/\r
+ bmp280->twid->iaddr = BMP280_CONFIG_REG_FILTER__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ if (com_rslt == SUCCESS) {\r
+ data = BMP280_SET_BITSLICE(data, BMP280_CONFIG_REG_FILTER, value);\r
+ bmp280->twid->iaddr = BMP280_CONFIG_REG_FILTER__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_write(bmp280, &data, 1);\r
+ }\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Read the standby duration time from the sensor in the register 0xF5 bit 5 to 7\r
+ *\r
+ * Param standby_durn : The standby duration time value.\r
+ * value | standby duration\r
+ * -----------|--------------------\r
+ * 0x00 | BMP280_STANDBYTIME_1_MS\r
+ * 0x01 | BMP280_STANDBYTIME_63_MS\r
+ * 0x02 | BMP280_STANDBYTIME_125_MS\r
+ * 0x03 | BMP280_STANDBYTIME_250_MS\r
+ * 0x04 | BMP280_STANDBYTIME_500_MS\r
+ * 0x05 | BMP280_STANDBYTIME_1000_MS\r
+ * 0x06 | BMP280_STANDBYTIME_2000_MS\r
+ * 0x07 | BMP280_STANDBYTIME_4000_MS\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_get_standby_durn(struct _bmp280* bmp280, uint8_t* standby_durn)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* read the standby duration*/\r
+ bmp280->twid->iaddr = BMP280_CONFIG_REG_STANDBY_DURN__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ *standby_durn = BMP280_GET_BITSLICE(data, BMP280_CONFIG_REG_STANDBY_DURN);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Read the standby duration time from the sensor in the register 0xF5 bit 5 to 7\r
+ *\r
+ * Note Normal mode comprises an automated perpetual cycling between an (active)\r
+ * Measurement period and an (inactive) standby period.\r
+ * Note The standby time is determined by the contents of the register t_sb.\r
+ * Standby time can be set using BME280_STANDBYTIME_125_MS.\r
+ * Note bme280_set_standby_durN(BME280_STANDBYTIME_125_MS)\r
+ *\r
+ * Param standby_durn : The standby duration time value.\r
+ * value | standby duration\r
+ * -----------|--------------------\r
+ * 0x00 | BMP280_STANDBYTIME_1_MS\r
+ * 0x01 | BMP280_STANDBYTIME_63_MS\r
+ * 0x02 | BMP280_STANDBYTIME_125_MS\r
+ * 0x03 | BMP280_STANDBYTIME_250_MS\r
+ * 0x04 | BMP280_STANDBYTIME_500_MS\r
+ * 0x05 | BMP280_STANDBYTIME_1000_MS\r
+ * 0x06 | BMP280_STANDBYTIME_2000_MS\r
+ * 0x07 | BMP280_STANDBYTIME_4000_MS\r
+ *\r
+ * @return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_set_standby_durn (struct _bmp280* bmp280, uint8_t standby_durn)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* write the standby duration*/\r
+ bmp280->twid->iaddr = BMP280_CONFIG_REG_STANDBY_DURN__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ if (com_rslt == SUCCESS) {\r
+ data = BMP280_SET_BITSLICE(data, BMP280_CONFIG_REG_STANDBY_DURN, standby_durn);\r
+ bmp280->twid->iaddr = BMP280_CONFIG_REG_STANDBY_DURN__REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_write(bmp280, &data, 1);\r
+ }\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Write the working mode of the sensor\r
+ *\r
+ * Param work_mode : The value of work mode\r
+ * value | mode\r
+ * -------------|-------------\r
+ * 0 | BMP280_ULTRA_LOW_POWER_MODE\r
+ * 1 | BMP280_LOW_POWER_MODE\r
+ * 2 | BMP280_STANDARD_RESOLUTION_MODE\r
+ * 3 | BMP280_HIGH_RESOLUTION_MODE\r
+ * 4 | BMP280_ULTRA_HIGH_RESOLUTION_MODE\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_set_work_mode (struct _bmp280* bmp280, uint8_t work_mode)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ if (work_mode <= 4) {\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ if (com_rslt == SUCCESS)\r
+ {\r
+ switch (work_mode) {\r
+ /* write work mode*/\r
+ case BMP280_ULTRA_LOW_POWER_MODE:\r
+ bmp280->overs_temp = BMP280_ULTRALOWPOWER_OVRS_TEMP;\r
+ bmp280->overs_pres = BMP280_ULTRALOWPOWER_OVRS_PRES;\r
+ break;\r
+ case BMP280_LOW_POWER_MODE:\r
+ bmp280->overs_temp = BMP280_LOWPOWER_OVRS_TEMP;\r
+ bmp280->overs_pres = BMP280_LOWPOWER_OVRS_PRES;\r
+ break;\r
+ case BMP280_STANDARD_RESOLUTION_MODE:\r
+ bmp280->overs_temp = BMP280_STANDARDRESOLUTION_OVRS_TEMP;\r
+ bmp280->overs_pres = BMP280_STANDARDRESOLUTION_OVRS_PRES;\r
+ break;\r
+ case BMP280_HIGH_RESOLUTION_MODE:\r
+ bmp280->overs_temp = BMP280_HIGHRESOLUTION_OVRS_TEMP;\r
+ bmp280->overs_pres = BMP280_HIGHRESOLUTION_OVRS_PRES;\r
+ break;\r
+ case BMP280_ULTRA_HIGH_RESOLUTION_MODE:\r
+ bmp280->overs_temp = BMP280_ULTRAHIGHRESOLUTION_OVRS_TEMP;\r
+ bmp280->overs_pres = BMP280_ULTRAHIGHRESOLUTION_OVRS_PRES;\r
+ break;\r
+ }\r
+ data = BMP280_SET_BITSLICE(data, BMP280_CTRL_MEAS_REG_OVRS_TEMP, bmp280->overs_temp);\r
+ data = BMP280_SET_BITSLICE(data, BMP280_CTRL_MEAS_REG_OVRS_PRES, bmp280->overs_pres);\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_write(bmp280, &data, 1);\r
+ }\r
+ }\r
+ else {\r
+ com_rslt = E_BMP280_OUT_OF_RANGE;\r
+ }\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+/* Read both uncompensated pressure and temperature in forced mode\r
+ *\r
+ * Param uncP: The value of uncompensated pressure.\r
+ * uncT: The value of uncompensated temperature\r
+ *\r
+ * Return results of bus communication function\r
+ * @retval 0 -> Success\r
+ * @retval -1 -> Error\r
+ */\r
+uint8_t bmp280_get_forced_uncP_temperature(struct _bmp280* bmp280, int32_t* uncP, int32_t* uncT)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = ERROR;\r
+ uint8_t data = 0;\r
+ uint8_t waittime = 0;\r
+\r
+ /* check the bmp280 struct pointer as NULL*/\r
+ if (bmp280 == BMP280_NULL)\r
+ return E_BMP280_NULL_PTR;\r
+ else {\r
+ /* read pressure and temperature*/\r
+ data = (bmp280->overs_temp << 5) + (bmp280->overs_pres << 2) + BMP280_FORCED_MODE;\r
+ bmp280->twid->iaddr = BMP280_CTRL_MEAS_REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_write(bmp280, &data, 1);\r
+ bmp280_compute_wait_time(bmp280, &waittime);\r
+ bmp280->delay_msec(waittime);\r
+ com_rslt += bmp280_read_uncompensed_pressure_temperature(bmp280, uncP, uncT);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+\r
+#ifdef BMP280_ENABLE_FLOAT\r
+/* Read actual temperature from uncompensated temperature\r
+ *\r
+ * Note Returns the value in Degree centigrade\r
+ * Output value of "51.23" equals 51.23 DegC.\r
+ *\r
+ * Param uncT : value of uncompensated temperature\r
+ *\r
+ * Return Actual temperature in floating point\r
+ */\r
+double bmp280_compensate_T_double(struct _bmp280* bmp280, int32_t uncT)\r
+{\r
+ double x1 = 0;\r
+ double x2 = 0;\r
+ double temperature = 0;\r
+\r
+ x1 = (((double)uncT) / BMP280_FLOAT_TRUE_TEMP_16384 -\r
+ ((double)bmp280->calpar.dig_T1) / BMP280_FLOAT_TRUE_TEMP_1024) *\r
+ ((double)bmp280->calpar.dig_T2);\r
+ x2 = ((((double)uncT) / BMP280_FLOAT_TRUE_TEMP_131072 -\r
+ ((double)bmp280->calpar.dig_T1) / BMP280_FLOAT_TRUE_TEMP_8192) *\r
+ (((double)uncT) / BMP280_FLOAT_TRUE_TEMP_131072 -\r
+ ((double)bmp280->calpar.dig_T1) / BMP280_FLOAT_TRUE_TEMP_8192)) *\r
+ ((double)bmp280->calpar.dig_T3);\r
+ bmp280->calpar.t_fine = (int32_t)(x1 + x2);\r
+ temperature = (x1 + x2) / BMP280_FLOAT_TRUE_TEMP_5120;\r
+ return temperature;\r
+}\r
+\r
+/* Reads actual pressure from uncompensated pressure and returns pressure in\r
+ * Pa as double.\r
+ *\r
+ * Note Output value of "96386.2" equals 96386.2 Pa = 963.862 hPa.\r
+ *\r
+ * Param uncP : value of uncompensated pressure\r
+ *\r
+ * Return Actual pressure in floating point\r
+ */\r
+double bmp280_compensate_P_double(struct _bmp280* bmp280, int32_t uncP)\r
+{\r
+ double x1 = 0;\r
+ double x2 = 0;\r
+ double pressure = 0;\r
+\r
+ x1 = ((double)bmp280->calpar.t_fine / BMP280_FLOAT_TRUE_PRES_2) -\r
+ BMP280_FLOAT_TRUE_PRES_64000;\r
+ x2 = x1 * x1 * ((double)bmp280->calpar.dig_P6) /\r
+ BMP280_FLOAT_TRUE_PRES_32768;\r
+ x2 = x2 + x1 * ((double)bmp280->calpar.dig_P5)\r
+ * BMP280_FLOAT_TRUE_PRES_2;\r
+ x2 = (x2 / BMP280_FLOAT_TRUE_PRES_4) + ((double)bmp280->calpar.dig_P4)\r
+ * BMP280_FLOAT_TRUE_PRES_65536;\r
+ x1 = (((double)bmp280->calpar.dig_P3) * x1 * x1\r
+ / BMP280_FLOAT_TRUE_PRES_524288 + ((double)bmp280->calpar.dig_P2) * x1)\r
+ / BMP280_FLOAT_TRUE_PRES_524288;\r
+ x1 = (BMP280_FLOAT_TRUE_PRES_1 + x1 / BMP280_FLOAT_TRUE_PRES_32768) *\r
+ ((double)bmp280->calpar.dig_P1);\r
+ pressure = BMP280_FLOAT_TRUE_PRES_1048576 - (double)uncP;\r
+ /* Avoid exception caused by division by zero */\r
+ if (fabs(x1) >= EPSILON)\r
+ pressure = (pressure - (x2 / BMP280_FLOAT_TRUE_PRES_4096)) *\r
+ BMP280_FLOAT_TRUE_PRES_6250 / x1;\r
+ else\r
+ return BMP280_FLOAT_TRUE_PRES_0;\r
+ x1 = ((double)bmp280->calpar.dig_P9) * pressure * pressure /\r
+ BMP280_FLOAT_TRUE_PRES_2147483648;\r
+ x2 = pressure * ((double)bmp280->calpar.dig_P8) / BMP280_FLOAT_TRUE_PRES_32768;\r
+ pressure = pressure + (x1 + x2 + ((double)bmp280->calpar.dig_P7))\r
+ / BMP280_FLOAT_TRUE_PRES_1_6;\r
+\r
+ return pressure;\r
+}\r
+#endif\r
+\r
+\r
+#if defined(BMP280_ENABLE_INT64) && defined(BMP280_64BITSUPPORT_PRESENT)\r
+/* Read actual pressure from uncompensated pressure\r
+ *\r
+ * Note returns the value in Pa as unsigned 32 bit integer in Q24.8 format\r
+ * (24 integer bits and 8 fractional bits). Output value of "24674867"\r
+ * represents 24674867 / 256 = 96386.2 Pa = 963.862 hPa\r
+ *\r
+ * Param uncP : value of uncompensated pressure\r
+ *\r
+ * Return actual pressure as 64bit output\r
+ */\r
+uint32_t bmp280_compensate_P_int64(struct _bmp280* bmp280, int32_t uncP)\r
+{\r
+ int64_t x1_s64r = 0;\r
+ int64_t x2_s64r = 0;\r
+ int64_t pressure = 0;\r
+\r
+ x1_s64r = ((int64_t)bmp280->calpar.t_fine) -\r
+ BMP280_TRUE_PRES_128000;\r
+ x2_s64r = x1_s64r * x1_s64r * (int64_t)bmp280->calpar.dig_P6;\r
+ x2_s64r = x2_s64r + ((x1_s64r * (int64_t)bmp280->calpar.dig_P5) << 17);\r
+ x2_s64r = x2_s64r + (((int64_t)bmp280->calpar.dig_P4) << 35);\r
+ x1_s64r = ((x1_s64r * x1_s64r * (int64_t)bmp280->calpar.dig_P3) >> 8) +\r
+ ((x1_s64r * (int64_t)bmp280->calpar.dig_P2) << 12);\r
+ x1_s64r = (((((int64_t)BMP280_TRUE_PRES_1) << 47) + x1_s64r)) *\r
+ ((int64_t)bmp280->calpar.dig_P1) >> 33;\r
+ pressure = BMP280_TRUE_PRES_1048576 - uncP;\r
+\r
+ if (x1_s64r != 0)\r
+#if defined __KERNEL__\r
+ pressure = div64_s64((((pressure << 31) - x2_s64r)\r
+ * BMP280_TRUE_PRES_3125), x1_s64r);\r
+#else\r
+ pressure = (((pressure << 31) - x2_s64r)\r
+ * BMP280_TRUE_PRES_3125) / x1_s64r;\r
+#endif\r
+ else\r
+ return 0;\r
+\r
+ x1_s64r = (((int64_t)bmp280->calpar.dig_P9) * (pressure >> 13) *\r
+ (pressure >> 13)) >> 25;\r
+ x2_s64r = (((int64_t)bmp280->calpar.dig_P8) * pressure) >> 19;\r
+ pressure = ((pressure + x1_s64r + x2_s64r) >> 8) +\r
+ (((int64_t)bmp280->calpar.dig_P7) << 4);\r
+ return (uint32_t)pressure;\r
+}\r
+#endif\r
+\r
+/* Computing waiting time for sensor data read\r
+ *\r
+ * Param delaytimer: The value of delay time\r
+ *\r
+ * Return 0\r
+ */\r
+uint8_t bmp280_compute_wait_time (struct _bmp280* bmp280, uint8_t* delaytimer)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt = SUCCESS;\r
+\r
+ *delaytimer = (T_INIT_MAX + T_MEASURE_PER_OSRS_MAX *\r
+ (((1 << bmp280->overs_temp) >> 1) +\r
+ ((1 << bmp280->overs_pres) >> 1)) +\r
+ (bmp280->overs_pres ? T_SETUP_PRESSURE_MAX : 0) + 15) / 16;\r
+ return com_rslt;\r
+}\r
+\r
+/*\r
+ * Read ID and Calibration parameters\r
+ * Return results of bus communication function\r
+ * 0 -> Success\r
+ * -1 -> Error\r
+ */\r
+uint8_t bmp280_read_id_get_calib_param (struct _bmp280* bmp280)\r
+{\r
+ /* variable used to return communication result*/\r
+ uint8_t com_rslt;\r
+ uint8_t data = 0;\r
+\r
+ /* read chip id */\r
+ bmp280->twid->iaddr = BMP280_CHIP_ID_REG;\r
+ bmp280->twid->isize = 1;\r
+ com_rslt = _bmp280_read(bmp280, &data, 1);\r
+ bmp280->chip_id = data;\r
+ if ( data != BMP280_CHIP_ID ) {\r
+ printf(" -E- Error Chip ID : 0x%x \n\r", data);\r
+ com_rslt = ERROR;\r
+ }\r
+ else {\r
+ printf(" -I- Chip ID: 0x%x \n\r", data);\r
+ /* readout bmp280 calibration parameter structure */\r
+ com_rslt += bmp280_get_calpar(bmp280);\r
+ }\r
+ return com_rslt;\r
+}\r
+\r
+// End of file\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+/*! \file bmp280.h\r
+ \brief BMP280 Sensor Driver Support Header File */\r
+\r
+#ifndef __BMP280_H__\r
+#define __BMP280_H__\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definition\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define BMP280_64BITSUPPORT_PRESENT\r
+\r
+/********************************************/\r
+/**\name ENABLE FLATING OUTPUT */\r
+/**************************************/\r
+\r
+// If the user wants to support floating point calculations, please set the following define.\r
+#define BMP280_ENABLE_FLOAT\r
+\r
+// If the user wants to support 64 bit integer calculation (needed for optimal pressure accuracy)\r
+// please set the following definition. If int64 calculation is not wanted (e.g. because it would include\r
+// large libraries), please do not set the definition.\r
+#define BMP280_ENABLE_INT64\r
+\r
+/****************************************/\r
+/**\name DELAY */\r
+/****************************************/\r
+\r
+// defines the return parameter type of the BMP280_DELAY_FUNCTION\r
+#define BMP280_DELAY_RETURN_TYPE void\r
+\r
+// defines the calling parameter types of the BMP280_DELAY_FUNCTION\r
+#define BMP280_DELAY_PARAM_TYPES uint16_t\r
+\r
+/***************************************************************/\r
+/**\name GET AND SET BITSLICE FUNCTIONS */\r
+/***************************************************************/\r
+\r
+/* never change this line */\r
+#define BMP280_DELAY_FUNC(delay_in_msec) delay_func(delay_in_msec)\r
+\r
+#define BMP280_GET_BITSLICE(regvar, bitname) ((regvar & bitname##__MSK) >> bitname##__POS)\r
+\r
+#define BMP280_SET_BITSLICE(regvar, bitname, val) ((regvar & ~bitname##__MSK) | ((val<<bitname##__POS)&bitname##__MSK))\r
+\r
+/***************************************************************/\r
+/**\name COMMON USED CONSTANTS */\r
+/***************************************************************/\r
+/* Constants */\r
+#define BMP280_NULL 0\r
+#define BMP280_INIT_VALUE 0\r
+\r
+/************************************************/\r
+/**\name ERROR CODES */\r
+/************************************************/\r
+#define SUCCESS ((uint8_t)0)\r
+#define ERROR ((uint8_t)0xFF)\r
+#define E_BMP280_NULL_PTR ((uint8_t)ERROR-1)\r
+#define E_BMP280_COMM_RES ((uint8_t)ERROR-2)\r
+#define E_BMP280_OUT_OF_RANGE ((uint8_t)ERROR-3)\r
+\r
+/************************************************/\r
+/**\name I2C ADDRESS DEFINITION */\r
+/***********************************************/\r
+#define BMP280_I2C_ADDRESS1 0x76\r
+#define BMP280_I2C_ADDRESS2 0x77\r
+/************************************************/\r
+/**\name POWER MODE DEFINITION */\r
+/***********************************************/\r
+/* Sensor Specific constants */\r
+#define BMP280_SLEEP_MODE 0x00\r
+#define BMP280_FORCED_MODE 0x01\r
+#define BMP280_NORMAL_MODE 0x03\r
+#define BMP280_SOFT_RESET_CODE 0xB6\r
+/************************************************/\r
+/**\name STANDBY TIME DEFINITION */\r
+/***********************************************/\r
+#define BMP280_STANDBY_TIME_1_MS 0x00\r
+#define BMP280_STANDBY_TIME_63_MS 0x01\r
+#define BMP280_STANDBY_TIME_125_MS 0x02\r
+#define BMP280_STANDBY_TIME_250_MS 0x03\r
+#define BMP280_STANDBY_TIME_500_MS 0x04\r
+#define BMP280_STANDBY_TIME_1000_MS 0x05\r
+#define BMP280_STANDBY_TIME_2000_MS 0x06\r
+#define BMP280_STANDBY_TIME_4000_MS 0x07\r
+/************************************************/\r
+/**\name OVERSAMPLING DEFINITION */\r
+/***********************************************/\r
+#define BMP280_OVERSAMPLING_SKIPPED 0x00\r
+#define BMP280_OVERSAMP_1X 0x01\r
+#define BMP280_OVERSAMP_2X 0x02\r
+#define BMP280_OVERSAMP_4X 0x03\r
+#define BMP280_OVERSAMP_8X 0x04\r
+#define BMP280_OVERSAMP_16X 0x05\r
+/************************************************/\r
+/**\name WORKING MODE DEFINITION */\r
+/***********************************************/\r
+#define BMP280_ULTRA_LOW_POWER_MODE 0x00\r
+#define BMP280_LOW_POWER_MODE 0x01\r
+#define BMP280_STANDARD_RESOLUTION_MODE 0x02\r
+#define BMP280_HIGH_RESOLUTION_MODE 0x03\r
+#define BMP280_ULTRA_HIGH_RESOLUTION_MODE 0x04\r
+\r
+#define BMP280_ULTRALOWPOWER_OVRS_PRES BMP280_OVERSAMP_1X\r
+#define BMP280_ULTRALOWPOWER_OVRS_TEMP BMP280_OVERSAMP_1X\r
+\r
+#define BMP280_LOWPOWER_OVRS_PRES BMP280_OVERSAMP_2X\r
+#define BMP280_LOWPOWER_OVRS_TEMP BMP280_OVERSAMP_1X\r
+\r
+#define BMP280_STANDARDRESOLUTION_OVRS_PRES BMP280_OVERSAMP_4X\r
+#define BMP280_STANDARDRESOLUTION_OVRS_TEMP BMP280_OVERSAMP_1X\r
+\r
+#define BMP280_HIGHRESOLUTION_OVRS_PRES BMP280_OVERSAMP_8X\r
+#define BMP280_HIGHRESOLUTION_OVRS_TEMP BMP280_OVERSAMP_1X\r
+\r
+#define BMP280_ULTRAHIGHRESOLUTION_OVRS_PRES BMP280_OVERSAMP_16X\r
+#define BMP280_ULTRAHIGHRESOLUTION_OVRS_TEMP BMP280_OVERSAMP_2X\r
+/************************************************/\r
+/**\name FILTER DEFINITION */\r
+/***********************************************/\r
+#define BMP280_FILTER_COEFF_OFF 0x00\r
+#define BMP280_FILTER_COEFF_2 0x01\r
+#define BMP280_FILTER_COEFF_4 0x02\r
+#define BMP280_FILTER_COEFF_8 0x03\r
+#define BMP280_FILTER_COEFF_16 0x04\r
+/************************************************/\r
+/**\name DELAY TIME DEFINITION */\r
+/***********************************************/\r
+#define T_INIT_MAX 20 /* 20/16 = 1.25 ms */\r
+#define T_MEASURE_PER_OSRS_MAX 37 /* 37/16 = 2.3125 ms*/\r
+#define T_SETUP_PRESSURE_MAX 10 /* 10/16 = 0.625 ms */\r
+/************************************************/\r
+/**\name CALIBRATION PARAMETERS DEFINITION */\r
+/***********************************************/\r
+/*calibration parameters */\r
+#define BMP280_DIG_T1_LSB_REG 0x88\r
+#define BMP280_DIG_T1_MSB_REG 0x89\r
+#define BMP280_DIG_T2_LSB_REG 0x8A\r
+#define BMP280_DIG_T2_MSB_REG 0x8B\r
+#define BMP280_DIG_T3_LSB_REG 0x8C\r
+#define BMP280_DIG_T3_MSB_REG 0x8D\r
+#define BMP280_DIG_P1_LSB_REG 0x8E\r
+#define BMP280_DIG_P1_MSB_REG 0x8F\r
+#define BMP280_DIG_P2_LSB_REG 0x90\r
+#define BMP280_DIG_P2_MSB_REG 0x91\r
+#define BMP280_DIG_P3_LSB_REG 0x92\r
+#define BMP280_DIG_P3_MSB_REG 0x93\r
+#define BMP280_DIG_P4_LSB_REG 0x94\r
+#define BMP280_DIG_P4_MSB_REG 0x95\r
+#define BMP280_DIG_P5_LSB_REG 0x96\r
+#define BMP280_DIG_P5_MSB_REG 0x97\r
+#define BMP280_DIG_P6_LSB_REG 0x98\r
+#define BMP280_DIG_P6_MSB_REG 0x99\r
+#define BMP280_DIG_P7_LSB_REG 0x9A\r
+#define BMP280_DIG_P7_MSB_REG 0x9B\r
+#define BMP280_DIG_P8_LSB_REG 0x9C\r
+#define BMP280_DIG_P8_MSB_REG 0x9D\r
+#define BMP280_DIG_P9_LSB_REG 0x9E\r
+#define BMP280_DIG_P9_MSB_REG 0x9F\r
+/************************************************/\r
+/**\name REGISTER ADDRESS DEFINITION */\r
+/***********************************************/\r
+#define BMP280_CHIP_ID_REG 0xD0 /*Chip ID Register */\r
+#define BMP280_RST_REG 0xE0 /*Softreset Register */\r
+#define BMP280_STAT_REG 0xF3 /*Status Register */\r
+#define BMP280_CTRL_MEAS_REG 0xF4 /*Ctrl Measure Register */\r
+#define BMP280_CONFIG_REG 0xF5 /*Configuration Register */\r
+#define BMP280_PRESSURE_MSB_REG 0xF7 /*Pressure MSB Register */\r
+#define BMP280_PRESSURE_LSB_REG 0xF8 /*Pressure LSB Register */\r
+#define BMP280_PRESSURE_XLSB_REG 0xF9 /*Pressure XLSB Register */\r
+#define BMP280_TEMPERATURE_MSB_REG 0xFA /*Temperature MSB Reg */\r
+#define BMP280_TEMPERATURE_LSB_REG 0xFB /*Temperature LSB Reg */\r
+#define BMP280_TEMPERATURE_XLSB_REG 0xFC /*Temperature XLSB Reg */\r
+/************************************************/\r
+/**\name BIT LENGTH,POSITION AND MASK DEFINITION */\r
+/***********************************************/\r
+/* Status Register */\r
+#define BMP280_STATUS_REG_MEASURING__POS 3\r
+#define BMP280_STATUS_REG_MEASURING__MSK 0x08\r
+#define BMP280_STATUS_REG_MEASURING__LEN 1\r
+#define BMP280_STATUS_REG_MEASURING__REG BMP280_STAT_REG\r
+\r
+#define BMP280_STATUS_REG_IM_UPDATE__POS 0\r
+#define BMP280_STATUS_REG_IM_UPDATE__MSK 0x01\r
+#define BMP280_STATUS_REG_IM_UPDATE__LEN 1\r
+#define BMP280_STATUS_REG_IM_UPDATE__REG BMP280_STAT_REG\r
+/************************************************/\r
+/**\name BIT LENGTH,POSITION AND MASK DEFINITION\r
+FOR TEMPERATURE OVERSAMPLING */\r
+/***********************************************/\r
+/* Control Measurement Register */\r
+#define BMP280_CTRL_MEAS_REG_OVRS_TEMP__POS 5\r
+#define BMP280_CTRL_MEAS_REG_OVRS_TEMP__MSK 0xE0\r
+#define BMP280_CTRL_MEAS_REG_OVRS_TEMP__LEN 3\r
+#define BMP280_CTRL_MEAS_REG_OVRS_TEMP__REG \\r
+BMP280_CTRL_MEAS_REG\r
+/************************************************/\r
+/**\name BIT LENGTH,POSITION AND MASK DEFINITION\r
+FOR PRESSURE OVERSAMPLING */\r
+/***********************************************/\r
+#define BMP280_CTRL_MEAS_REG_OVRS_PRES__POS 2\r
+#define BMP280_CTRL_MEAS_REG_OVRS_PRES__MSK 0x1C\r
+#define BMP280_CTRL_MEAS_REG_OVRS_PRES__LEN 3\r
+#define BMP280_CTRL_MEAS_REG_OVRS_PRES__REG \\r
+BMP280_CTRL_MEAS_REG\r
+/************************************************/\r
+/**\name BIT LENGTH,POSITION AND MASK DEFINITION\r
+FOR POWER MODE */\r
+/***********************************************/\r
+#define BMP280_CTRL_MEAS_REG_POWER_MODE__POS 0\r
+#define BMP280_CTRL_MEAS_REG_POWER_MODE__MSK 0x03\r
+#define BMP280_CTRL_MEAS_REG_POWER_MODE__LEN 2\r
+#define BMP280_CTRL_MEAS_REG_POWER_MODE__REG BMP280_CTRL_MEAS_REG\r
+/************************************************/\r
+/**\name BIT LENGTH,POSITION AND MASK DEFINITION\r
+FOR STANDBY DURATION */\r
+/***********************************************/\r
+/* Configuration Register */\r
+#define BMP280_CONFIG_REG_STANDBY_DURN__POS 5\r
+#define BMP280_CONFIG_REG_STANDBY_DURN__MSK 0xE0\r
+#define BMP280_CONFIG_REG_STANDBY_DURN__LEN 3\r
+#define BMP280_CONFIG_REG_STANDBY_DURN__REG BMP280_CONFIG_REG\r
+/************************************************/\r
+/**\name BIT LENGTH,POSITION AND MASK DEFINITION\r
+FOR IIR FILTER */\r
+/***********************************************/\r
+#define BMP280_CONFIG_REG_FILTER__POS 2\r
+#define BMP280_CONFIG_REG_FILTER__MSK 0x1C\r
+#define BMP280_CONFIG_REG_FILTER__LEN 3\r
+#define BMP280_CONFIG_REG_FILTER__REG BMP280_CONFIG_REG\r
+/************************************************/\r
+/**\name BIT LENGTH,POSITION AND MASK DEFINITION\r
+FOR SPI ENABLE*/\r
+/***********************************************/\r
+#define BMP280_CONFIG_REG_SPI3_ENABLE__POS 0\r
+#define BMP280_CONFIG_REG_SPI3_ENABLE__MSK 0x01\r
+#define BMP280_CONFIG_REG_SPI3_ENABLE__LEN 1\r
+#define BMP280_CONFIG_REG_SPI3_ENABLE__REG BMP280_CONFIG_REG\r
+/************************************************/\r
+/**\name BIT LENGTH,POSITION AND MASK DEFINITION\r
+FOR PRESSURE AND TEMPERATURE DATA REGISTERS */\r
+/***********************************************/\r
+/* Data Register */\r
+#define BMP280_PRESSURE_XLSB_REG__POS 4\r
+#define BMP280_PRESSURE_XLSB_REG__MSK 0xF0\r
+#define BMP280_PRESSURE_XLSB_REG__LEN 4\r
+#define BMP280_PRESSURE_XLSB_REG__REG BMP280_PRESSURE_XLSB_REG\r
+\r
+#define BMP280_TEMPERATURE_XLSB_REG__POS 4\r
+#define BMP280_TEMPERATURE_XLSB_REG__MSK 0xF0\r
+#define BMP280_TEMPERATURE_XLSB_REG__LEN 4\r
+#define BMP280_TEMPERATURE_XLSB_REG__REG BMP280_TEMPERATURE_XLSB_REG\r
+\r
+/****************************************************/\r
+/**\name ARRAY PARAMETERS */\r
+/***************************************************/\r
+#define LSB_ZERO 0\r
+#define MSB_ONE 1\r
+#define LSB_TWO 2\r
+#define MSB_THREE 3\r
+#define LSB_FOUR 4\r
+#define MSB_FIVE 5\r
+#define LSB_SIX 6\r
+#define MSB_SEVEN 7\r
+/****************************************************/\r
+/**\name TRUE TEMPERATURE CALUCULATION PARAMETERS */\r
+/***************************************************/\r
+#define BMP280_DEC_TRUE_TEMP_5 5\r
+#define BMP280_DEC_TRUE_TEMP_128 128\r
+/****************************************************/\r
+/**\name TRUE PRESSURE CALUCULATION PARAMETERS */\r
+/***************************************************/\r
+#define BMP280_DEC_TRUE_PRES_64000 64000\r
+#define BMP280_DEC_TRUE_PRES_2 2\r
+#define BMP280_DEC_TRUE_PRES_32768 32768\r
+#define BMP280_DEC_TRUE_PRES_1048576 1048576\r
+#define BMP280_DEC_TRUE_PRES_3125 3125\r
+#define BMP280_HEX_TRUE_PRES_8M 0x80000000\r
+\r
+/****************************************************/\r
+/**\name TRUE TEMPERATURE CALCULATION FLOAT RETURN */\r
+/***************************************************/\r
+#define BMP280_FLOAT_TRUE_TEMP_16384 16384.0\r
+#define BMP280_FLOAT_TRUE_TEMP_1024 1024.0\r
+#define BMP280_FLOAT_TRUE_TEMP_131072 131072.0\r
+#define BMP280_FLOAT_TRUE_TEMP_8192 8192.0\r
+#define BMP280_FLOAT_TRUE_TEMP_5120 5120.0\r
+\r
+/****************************************************/\r
+/**\name TRUE PRESSURE CALCULATION FLOAT RETURN */\r
+/***************************************************/\r
+#define BMP280_FLOAT_TRUE_PRES_1 1.0\r
+#define BMP280_FLOAT_TRUE_PRES_0 0.0\r
+#define BMP280_FLOAT_TRUE_PRES_2 2.0\r
+#define BMP280_FLOAT_TRUE_PRES_4 4.0\r
+#define BMP280_FLOAT_TRUE_PRES_1_6 16.0\r
+#define BMP280_FLOAT_TRUE_PRES_64000 64000.0\r
+#define BMP280_FLOAT_TRUE_PRES_32768 32768.0\r
+#define BMP280_FLOAT_TRUE_PRES_65536 65536.0\r
+#define BMP280_FLOAT_TRUE_PRES_524288 524288.0\r
+#define BMP280_FLOAT_TRUE_PRES_1048576 1048576.0\r
+#define BMP280_FLOAT_TRUE_PRES_4096 4096.0\r
+#define BMP280_FLOAT_TRUE_PRES_6250 6250.0\r
+#define BMP280_FLOAT_TRUE_PRES_2147483648 2147483648.0\r
+\r
+/****************************************************/\r
+/**\name TRUE PRESSURE CALUCULATION 64BIT RETURN */\r
+/***************************************************/\r
+#define BMP280_TRUE_PRES_128000 128000\r
+#define BMP280_TRUE_PRES_1048576 1048576\r
+#define BMP280_TRUE_PRES_3125 3125\r
+#define BMP280_TRUE_PRES_1 1\r
+\r
+/**************************************************************/\r
+/**\name CHIP ID */\r
+/**************************************************************/\r
+#define BMP280_CHIP_ID 0x58\r
+\r
+/**************************************************************/\r
+/**\name STRUCTURE DEFINITIONS */\r
+/**************************************************************/\r
+// This structure holds all device specific calibration parameters\r
+struct _bmp280_calib_par\r
+{\r
+ uint16_t dig_T1; /**<calibration T1 data*/\r
+ int16_t dig_T2; /**<calibration T2 data*/\r
+ int16_t dig_T3; /**<calibration T3 data*/\r
+ uint16_t dig_P1; /**<calibration P1 data*/\r
+ int16_t dig_P2; /**<calibration P2 data*/\r
+ int16_t dig_P3; /**<calibration P3 data*/\r
+ int16_t dig_P4; /**<calibration P4 data*/\r
+ int16_t dig_P5; /**<calibration P5 data*/\r
+ int16_t dig_P6; /**<calibration P6 data*/\r
+ int16_t dig_P7; /**<calibration P7 data*/\r
+ int16_t dig_P8; /**<calibration P8 data*/\r
+ int16_t dig_P9; /**<calibration P9 data*/\r
+ int32_t t_fine; /**<calibration t_fine data*/\r
+};\r
+\r
+// This structure holds BMP280 initialization parameters\r
+struct _bmp280\r
+{\r
+ struct _twi_desc* twid;\r
+\r
+ struct _bmp280_calib_par calpar; /**<calibration data*/\r
+ uint8_t chip_id; /**< chip id of the sensor*/\r
+ uint8_t dev_addr; /**< device address of the sensor*/\r
+ uint8_t overs_temp; /**< temperature over sampling*/\r
+ uint8_t overs_pres; /**< pressure over sampling*/\r
+ void(*delay_msec)(uint16_t); /**< delay function pointer*/\r
+};\r
+\r
+/**************************************************************/\r
+/**\name FUNCTION DECLARATIONS */\r
+/**************************************************************/\r
+\r
+static uint8_t _bmp280_read(struct _bmp280* bmp280, uint8_t* buffer, uint32_t len);\r
+static uint8_t _bmp280_write(struct _bmp280* bmp280, const uint8_t* buffer, uint32_t len);\r
+\r
+uint8_t bmp280_write_register(struct _bmp280* bmp280, uint8_t addr, uint8_t* pdata, uint8_t len);\r
+uint8_t bmp280_read_register(struct _bmp280* bmp280, uint8_t addr, uint8_t* pdata, uint8_t len);\r
+\r
+uint8_t bmp280_read_uncompensed_temperature (struct _bmp280* bmp280, int32_t* uncT);\r
+int32_t bmp280_compensate_temperatureC (struct _bmp280* bmp280, int32_t uncT);\r
+uint8_t bmp280_read_uncompensed_pressure (struct _bmp280* bmp280, int32_t* uncP);\r
+uint32_t bmp280_compensate_pressureP (struct _bmp280* bmp280, int32_t uncP);\r
+uint8_t bmp280_read_uncompensed_pressure_temperature (struct _bmp280* bmp280, int32_t* uncP, int32_t* uncT);\r
+uint8_t bmp280_read_pressure_temperature (struct _bmp280* bmp280, uint32_t* pressure, int32_t* temperature);\r
+uint8_t bmp280_get_calpar (struct _bmp280* bmp280);\r
+uint8_t bmp280_get_overs_temp (struct _bmp280* bmp280, uint8_t* value);\r
+uint8_t bmp280_set_overs_temp (struct _bmp280* bmp280, uint8_t value);\r
+uint8_t bmp280_get_overs_pres (struct _bmp280* bmp280, uint8_t* value);\r
+uint8_t bmp280_set_overs_pres (struct _bmp280* bmp280, uint8_t value);\r
+uint8_t bmp280_get_power_mode(struct _bmp280* bmp280, uint8_t* power_mode);\r
+uint8_t bmp280_set_power_mode (struct _bmp280* bmp280, uint8_t power_mode);\r
+uint8_t bmp280_set_soft_rst (struct _bmp280* bmp280);\r
+uint8_t bmp280_get_spi3 (struct _bmp280* bmp280, uint8_t* enable_disable);\r
+uint8_t bmp280_set_spi3 (struct _bmp280* bmp280, uint8_t enable_disable);\r
+uint8_t bmp280_get_filter (struct _bmp280* bmp280, uint8_t *value);\r
+uint8_t bmp280_set_filter (struct _bmp280* bmp280, uint8_t value);\r
+uint8_t bmp280_get_standby_durn(struct _bmp280* bmp280, uint8_t* standby_durn);\r
+uint8_t bmp280_set_standby_durn (struct _bmp280* bmp280, uint8_t standby_durn);\r
+uint8_t bmp280_set_work_mode (struct _bmp280* bmp280, uint8_t work_mode);\r
+uint8_t bmp280_get_forced_uncP_temperature(struct _bmp280* bmp280, int32_t* uncP, int32_t* uncT);\r
+\r
+uint8_t bmp280_read_id_get_calib_param (struct _bmp280* bmp280);\r
+\r
+/**************************************************************/\r
+/**\name FUNCTION FOR TRUE TEMPERATURE CALCULATION */\r
+/**************************************************************/\r
+\r
+#ifdef BMP280_ENABLE_FLOAT\r
+ double bmp280_compensate_T_double(struct _bmp280* bmp280, int32_t uncT);\r
+ double bmp280_compensate_P_double(struct _bmp280* bmp280, int32_t uncP);\r
+#endif\r
+\r
+#if defined(BMP280_ENABLE_INT64) && defined(BMP280_64BITSUPPORT_PRESENT)\r
+ uint32_t bmp280_compensate_P_int64(struct _bmp280* bmp280, int32_t uncP);\r
+#endif\r
+\r
+/**************************************************************/\r
+/**\name FUNCTION FOR DELAY CALCULATION DURING FORCEMODE */\r
+/**************************************************************/\r
+\r
+uint8_t bmp280_compute_wait_time (struct _bmp280* bmp280, uint8_t* delaytimer);\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+* \file\r
+*\r
+* Implements CONSOLE.\r
+*\r
+*/\r
+\r
+/*----------------------------------------------------------------------------\r
+* Headers\r
+*----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "chip.h"\r
+#include "misc/console.h"\r
+#include "peripherals/pio.h"\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/uart.h"\r
+#include <stdio.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+* Variables\r
+*----------------------------------------------------------------------------*/\r
+\r
+typedef void (*_init_handler) (void*,uint32_t,uint32_t);\r
+typedef void (*_put_char_handler) (void*, uint8_t);\r
+typedef uint32_t (*_get_char_handler) (void*);\r
+typedef uint32_t (*_rx_ready_handler) (void*);\r
+typedef void (*_enable_it_handler) (void*,uint32_t);\r
+\r
+/* Initialize console structure according to board configuration */\r
+#if CONSOLE_DRIVER == DRV_USART\r
+#include "peripherals/usart.h"\r
+static const struct _console console = {\r
+ CONSOLE_PER_ADD,\r
+ (_init_handler) usart_configure,\r
+ (_put_char_handler) usart_put_char,\r
+ (_get_char_handler) usart_get_char,\r
+ (_rx_ready_handler) usart_is_rx_ready,\r
+ (_enable_it_handler) usart_enable_it\r
+};\r
+#elif CONSOLE_DRIVER == DRV_UART\r
+#include "peripherals/uart.h"\r
+static const struct _console console = {\r
+ CONSOLE_PER_ADD,\r
+ (_init_handler) uart_configure,\r
+ (_put_char_handler) uart_put_char,\r
+ (_get_char_handler) uart_get_char,\r
+ (_rx_ready_handler) uart_is_rx_ready,\r
+ (_enable_it_handler) uart_set_int\r
+};\r
+#elif CONSOLE_DRIVER == DRV_DBGU\r
+#include "peripherals/dbgu.h"\r
+static const struct _console console = {\r
+ CONSOLE_PER_ADD,\r
+ (_init_handler) dbgu_configure,\r
+ (_put_char_handler) dbgu_put_char,\r
+ (_get_char_handler) dbgu_get_char,\r
+ (_rx_ready_handler) dbgu_is_rx_ready,\r
+ (_enable_it_handler) dbgu_enable_it\r
+};\r
+#endif\r
+\r
+/** Pins for CONSOLE */\r
+static const struct _pin pinsConsole[] = PINS_CONSOLE;\r
+\r
+/** Console initialize status */\r
+static uint8_t _bConsoleIsInitialized = 0;\r
+\r
+/*------------------------------------------------------------------------------\r
+* Exported functions\r
+*------------------------------------------------------------------------------*/\r
+\r
+/**\r
+* \brief Configures a CONSOLE peripheral with the specified parameters.\r
+*\r
+* \param baudrate Baudrate at which the CONSOLE should operate (in Hz).\r
+*/\r
+void console_configure(uint32_t baudrate)\r
+{\r
+ /* Configure PIO */\r
+ pio_configure(pinsConsole, ARRAY_SIZE(pinsConsole));\r
+\r
+ pmc_enable_peripheral(CONSOLE_ID);\r
+\r
+ uint32_t mode;\r
+#if CONSOLE_DRIVER != DRV_DBGU\r
+ mode = US_MR_CHMODE_NORMAL | US_MR_PAR_NO | US_MR_CHRL_8_BIT;\r
+#else\r
+ mode = US_MR_CHMODE_NORMAL | US_MR_PAR_NO;\r
+#endif\r
+\r
+#if CONSOLE_DRIVER == DRV_UART\r
+ uint32_t mr;\r
+ mr = mode & US_MR_FILTER ? UART_MR_FILTER_ENABLED\r
+ : UART_MR_FILTER_DISABLED;\r
+ mr |= UART_MR_PAR((mode & US_MR_PAR_Msk) >> US_MR_PAR_Pos);\r
+ if ((mode & US_MR_USCLKS_Msk) == US_MR_USCLKS_PMC_PCK)\r
+ mr |= UART_MR_BRSRCCK_PMC_PCK;\r
+ else\r
+ mr |= UART_MR_BRSRCCK_PERIPH_CLK;\r
+ mr |= UART_MR_CHMODE((mode & US_MR_CHMODE_Msk) >> US_MR_CHMODE_Pos);\r
+ mode = mr;\r
+#endif\r
+\r
+ /* Initialize driver to use */\r
+ console.init(console.addr, mode, baudrate);\r
+\r
+ /* Finally */\r
+ _bConsoleIsInitialized = 1;\r
+}\r
+\r
+/**\r
+* \brief Outputs a character on the CONSOLE line.\r
+*\r
+* \note This function is synchronous (i.e. uses polling).\r
+* \param c Character to send.\r
+*/\r
+void console_put_char(uint8_t c)\r
+{\r
+ if (!_bConsoleIsInitialized)\r
+ console_configure(CONSOLE_BAUDRATE);\r
+\r
+ console.put_char(console.addr, c);\r
+}\r
+\r
+/**\r
+* \brief Input a character from the CONSOLE line.\r
+*\r
+* \note This function is synchronous\r
+* \return character received.\r
+*/\r
+extern uint32_t console_get_char(void)\r
+{\r
+ if (!_bConsoleIsInitialized)\r
+ console_configure(CONSOLE_BAUDRATE);\r
+ return console.get_char(console.addr);\r
+}\r
+\r
+/**\r
+* \brief Check if there is Input from DBGU line.\r
+*\r
+* \return true if there is Input.\r
+*/\r
+extern uint32_t console_is_rx_ready(void)\r
+{\r
+ if (!_bConsoleIsInitialized)\r
+ console_configure(CONSOLE_BAUDRATE);\r
+ return console.is_rx_ready(console.addr);\r
+}\r
+\r
+/**\r
+* Displays the content of the given frame on the DBGU.\r
+*\r
+* \param pucFrame Pointer to the frame to dump.\r
+* \param size Buffer size in bytes.\r
+*/\r
+void console_dump_frame(uint8_t * pframe, uint32_t size)\r
+{\r
+ uint32_t dw;\r
+\r
+ for (dw = 0; dw < size; dw++) {\r
+ printf("%02X ", pframe[dw]);\r
+ }\r
+ printf("\n\r");\r
+}\r
+\r
+/**\r
+* Displays the content of the given buffer on the DBGU.\r
+*\r
+* \param pbuffer Pointer to the buffer to dump.\r
+* \param size Buffer size in bytes.\r
+* \param address Start address to display\r
+*/\r
+void console_dump_memory(uint8_t * pbuffer, uint32_t size,\r
+ uint32_t address)\r
+{\r
+ uint32_t i, j;\r
+ uint32_t last_line_start;\r
+ uint8_t *tmp;\r
+\r
+ for (i = 0; i < (size / 16); i++) {\r
+ printf("0x%08X: ", (unsigned int)(address + (i * 16)));\r
+ tmp = (uint8_t *) & pbuffer[i * 16];\r
+ for (j = 0; j < 4; j++) {\r
+ printf("%02X%02X%02X%02X ", tmp[0], tmp[1], tmp[2],\r
+ tmp[3]);\r
+ tmp += 4;\r
+ }\r
+ tmp = (uint8_t *) & pbuffer[i * 16];\r
+ for (j = 0; j < 16; j++) {\r
+ console_put_char(*tmp++);\r
+ }\r
+ printf("\n\r");\r
+ }\r
+ if ((size % 16) != 0) {\r
+ last_line_start = size - (size % 16);\r
+ printf("0x%08X: ", (unsigned int)(address + last_line_start));\r
+ for (j = last_line_start; j < last_line_start + 16; j++) {\r
+ if ((j != last_line_start) && (j % 4 == 0)) {\r
+ printf(" ");\r
+ }\r
+ if (j < size)\r
+ printf("%02X", pbuffer[j]);\r
+ else\r
+ printf(" ");\r
+ }\r
+ printf(" ");\r
+ for (j = last_line_start; j < size; j++) {\r
+ console_put_char(pbuffer[j]);\r
+ }\r
+ printf("\n\r");\r
+ }\r
+}\r
+\r
+/**\r
+* Reads an integer\r
+*\r
+* \param pvalue Pointer to the uint32_t variable to contain the input value.\r
+*/\r
+extern uint32_t console_get_integer(uint32_t * pvalue)\r
+{\r
+ uint8_t key;\r
+ uint8_t nb = 0;\r
+ uint32_t value = 0;\r
+\r
+ while (1) {\r
+ key = console_get_char();\r
+ console_put_char(key);\r
+\r
+ if (key >= '0' && key <= '9') {\r
+ value = (value * 10) + (key - '0');\r
+ nb++;\r
+ } else {\r
+ if (key == 0x0D || key == ' ') {\r
+ if (nb == 0) {\r
+ printf\r
+ ("\n\rWrite a number and press ENTER or SPACE!\n\r");\r
+ return 0;\r
+ } else {\r
+ printf("\n\r");\r
+ *pvalue = value;\r
+ return 1;\r
+ }\r
+ } else {\r
+ printf("\n\r'%c' not a number!\n\r", key);\r
+ return 0;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+* Reads an integer and check the value\r
+*\r
+* \param pvalue Pointer to the uint32_t variable to contain the input value.\r
+* \param dwMin Minimum value\r
+* \param dwMax Maximum value\r
+*/\r
+extern uint32_t console_get_integer_min_max(uint32_t * pvalue, uint32_t min,\r
+ uint32_t max)\r
+{\r
+ uint32_t value = 0;\r
+\r
+ if (console_get_integer(&value) == 0)\r
+ return 0;\r
+ if (value < min || value > max) {\r
+ printf("\n\rThe number have to be between %u and %u\n\r",\r
+ (unsigned int)min, (unsigned int)max);\r
+ return 0;\r
+ }\r
+ printf("\n\r");\r
+ *pvalue = value;\r
+ return 1;\r
+}\r
+\r
+void console_enable_interrupts(uint32_t mask)\r
+{\r
+ console.enable_interrupts(console.addr, mask);\r
+}\r
+\r
+/**\r
+* Reads an hexadecimal number\r
+*\r
+* \param pvalue Pointer to the uint32_t variable to contain the input value.\r
+*/\r
+extern uint32_t console_get_hexa_32(uint32_t * pvalue)\r
+{\r
+ uint8_t key;\r
+ uint32_t dw = 0;\r
+ uint32_t value = 0;\r
+\r
+ for (dw = 0; dw < 8; dw++) {\r
+ key = console_get_char();\r
+ console_put_char(key);\r
+\r
+ if (key >= '0' && key <= '9') {\r
+ value = (value * 16) + (key - '0');\r
+ } else {\r
+ if (key >= 'A' && key <= 'F') {\r
+ value = (value * 16) + (key - 'A' + 10);\r
+ } else {\r
+ if (key >= 'a' && key <= 'f') {\r
+ value = (value * 16) + (key - 'a' + 10);\r
+ } else {\r
+ printf\r
+ ("\n\rIt is not a hexa character!\n\r");\r
+ return 0;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ printf("\n\r");\r
+ *pvalue = value;\r
+ return 1;\r
+}\r
+\r
+void console_clear_screen(void)\r
+{\r
+ printf("\033[2J\033[0;0f");\r
+}\r
+\r
+void console_reset_cursor(void)\r
+{\r
+ printf("\033[0;0f");\r
+}\r
+\r
+void console_echo(uint8_t c)\r
+{\r
+ switch (c) {\r
+ case '\r':\r
+ case '\n':\r
+ printf("\r\n");\r
+ break;\r
+ case 0x7F:\r
+ printf("\033[1D\033[K");\r
+ break;\r
+ case '\b':\r
+ printf("\033[1D\033[K");\r
+ break;\r
+ default:\r
+ console_put_char(c);\r
+ }\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _CONSOLE_H_\r
+#define _CONSOLE_H_\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+#define DRV_UART (1)\r
+#define DRV_USART (2)\r
+#define DRV_DBGU (3)\r
+//#define DRV_FLEXCOM (4)\r
+\r
+struct _console {\r
+ void* addr;\r
+ void (*init)(void*, uint32_t, uint32_t);\r
+ void (*put_char)(void*, uint8_t);\r
+ uint32_t (*get_char)(void*);\r
+ uint32_t (*is_rx_ready)(void*);\r
+ void (*enable_interrupts)(void*, uint32_t);\r
+};\r
+\r
+/* ----------------------------------------------------------------------------\r
+ * Global function\r
+ * ---------------------------------------------------------------------------*/\r
+\r
+extern void console_configure(uint32_t baudrate);\r
+extern void console_put_char(uint8_t uc);\r
+extern uint32_t console_get_char(void);\r
+extern uint32_t console_is_rx_ready(void);\r
+extern void console_enable_interrupts(uint32_t mask);\r
+extern void console_dump_frame(uint8_t * pframe, uint32_t size);\r
+extern void console_dump_memory(uint8_t * pbuffer, uint32_t size,\r
+ uint32_t address);\r
+extern uint32_t console_get_integer(uint32_t * pvalue);\r
+extern uint32_t console_get_integer_min_max(uint32_t * pvalue, uint32_t min,\r
+ uint32_t max);\r
+extern uint32_t console_get_hexa_32(uint32_t * pvalue);\r
+\r
+extern void console_echo(uint8_t c);\r
+extern void console_clear_screen(void);\r
+extern void console_reset_cursor(void);\r
+\r
+#endif /* _CONSOLE_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "misc/led.h"\r
+#include "peripherals/pio.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local Variables\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#ifdef PINS_LEDS\r
+static const struct _pin pinsLeds[] = PINS_LEDS;\r
+\r
+static const uint32_t numLeds = ARRAY_SIZE(pinsLeds);\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global Functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Configures the pin associated with the given LED number. If the LED does\r
+ * not exist on the board, the function does nothing.\r
+ * \param dwLed Number of the LED to configure.\r
+ * \return 1 if the LED exists and has been configured; otherwise 0.\r
+ */\r
+extern uint32_t led_configure (uint32_t led)\r
+{\r
+#ifdef PINS_LEDS\r
+ // Check that LED exists\r
+ if (led >= numLeds) {\r
+ return 0;\r
+ }\r
+ // Configure LED\r
+ return pio_configure(&pinsLeds[led], 1);\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+/**\r
+ * Turns the given LED on if it exists; otherwise does nothing.\r
+ * \param dwLed Number of the LED to turn on.\r
+ * \return 1 if the LED has been turned on; 0 otherwise.\r
+ */\r
+extern uint32_t led_set(uint32_t led)\r
+{\r
+#ifdef PINS_LEDS\r
+ /* Check if LED exists */\r
+ if (led >= numLeds) {\r
+ return 0;\r
+ }\r
+\r
+ /* Turn LED on */\r
+ if (pinsLeds[led].type == PIO_OUTPUT_0) {\r
+ pio_set(&pinsLeds[led]);\r
+ } else {\r
+ pio_clear(&pinsLeds[led]);\r
+ }\r
+ return 1;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+/**\r
+ * Turns a LED off.\r
+ *\r
+ * \param dwLed Number of the LED to turn off.\r
+ * \return 1 if the LED has been turned off; 0 otherwise.\r
+ */\r
+extern uint32_t led_clear (uint32_t led)\r
+{\r
+#ifdef PINS_LEDS\r
+ /* Check if LED exists */\r
+ if (led >= numLeds) {\r
+ return 0;\r
+ }\r
+ /* Turn LED off */\r
+ if (pinsLeds[led].type == PIO_OUTPUT_0) {\r
+ pio_clear(&pinsLeds[led]);\r
+ } else {\r
+ pio_set(&pinsLeds[led]);\r
+ }\r
+ return 1;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
+/**\r
+ * Toggles the current state of a LED.\r
+ *\r
+ * \param dwLed Number of the LED to toggle.\r
+ * \return 1 if the LED has been toggled; otherwise 0.\r
+ */\r
+extern uint32_t led_toggle(uint32_t led)\r
+{\r
+#ifdef PINS_LEDS\r
+ /* Check if LED exists */\r
+ if (led >= numLeds) {\r
+ return 0;\r
+ }\r
+ /* Toggle LED */\r
+ if (pio_get_output_data_status(&pinsLeds[led])) {\r
+ pio_clear(&pinsLeds[led]);\r
+ } else {\r
+ pio_set(&pinsLeds[led]);\r
+ }\r
+ return 1;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Small set of functions for simple and portable LED usage.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Configure one or more LEDs using led_configure and\r
+ * LED_ConfigureAll.\r
+ * -# Set, clear and toggle LEDs using led_set, led_clear and\r
+ * led_toggle.\r
+ *\r
+ * LEDs are numbered starting from 0; the number of LEDs depend on the\r
+ * board being used. All the functions defined here will compile properly\r
+ * regardless of whether the LED is defined or not; they will simply\r
+ * return 0 when a LED which does not exist is given as an argument.\r
+ * Also, these functions take into account how each LED is connected on to\r
+ * board; thus, \ref led_set might change the level on the corresponding pin\r
+ * to 0 or 1, but it will always light the LED on; same thing for the other\r
+ * methods.\r
+ */\r
+\r
+#ifndef _LED_\r
+#define _LED_\r
+\r
+#include <stdint.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Global Functions\r
+//------------------------------------------------------------------------------\r
+\r
+extern uint32_t led_configure(uint32_t led);\r
+extern uint32_t led_set(uint32_t led);\r
+extern uint32_t led_clear(uint32_t led);\r
+extern uint32_t led_toggle(uint32_t led);\r
+\r
+#endif /* #ifndef LED_H */\r
--- /dev/null
+# ----------------------------------------------------------------------------\r
+# SAM Software Package License\r
+# ----------------------------------------------------------------------------\r
+# Copyright (c) 2015, Atmel Corporation\r
+#\r
+# All rights reserved.\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# - Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the disclaimer below.\r
+#\r
+# Atmel's name may not be used to endorse or promote products derived from\r
+# this software without specific prior written permission.\r
+#\r
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+# ----------------------------------------------------------------------------\r
+\r
+drivers-y += drivers/peripherals/adc.o\r
+drivers-y += drivers/peripherals/aes.o\r
+drivers-y += drivers/peripherals/aic.o\r
+drivers-y += drivers/peripherals/gmacd.o\r
+drivers-y += drivers/peripherals/gmac.o\r
+drivers-y += drivers/peripherals/l2cc.o\r
+drivers-y += drivers/peripherals/matrix.o\r
+drivers-y += drivers/peripherals/mpddrc.o\r
+drivers-y += drivers/peripherals/pit.o\r
+drivers-y += drivers/peripherals/pmc.o\r
+drivers-y += drivers/peripherals/pmecc.o\r
+drivers-y += drivers/peripherals/pmecc_gallois_field_512.o\r
+drivers-y += drivers/peripherals/pmecc_gallois_field_1024.o\r
+drivers-y += drivers/peripherals/pwmc.o\r
+drivers-y += drivers/peripherals/rstc.o\r
+drivers-y += drivers/peripherals/rtc.o\r
+drivers-y += drivers/peripherals/sha.o\r
+drivers-y += drivers/peripherals/hsmc.o\r
+drivers-y += drivers/peripherals/spid.o\r
+drivers-y += drivers/peripherals/spi.o\r
+drivers-y += drivers/peripherals/tc.o\r
+drivers-y += drivers/peripherals/tdes.o\r
+drivers-y += drivers/peripherals/trng.o\r
+drivers-y += drivers/peripherals/twid_legacy.o\r
+drivers-y += drivers/peripherals/twi.o\r
+drivers-y += drivers/peripherals/uart.o\r
+drivers-y += drivers/peripherals/usartd.o\r
+drivers-y += drivers/peripherals/usart_iso7816_4.o\r
+drivers-y += drivers/peripherals/usart.o\r
+drivers-y += drivers/peripherals/wdt.o\r
+drivers-y += drivers/peripherals/xdmac.o\r
+drivers-y += drivers/peripherals/xdmad.o\r
+\r
+drivers-$(CONFIG_HAVE_FLEXCOM) += drivers/peripherals/flexcom.o\r
+drivers-$(CONFIG_HAVE_USART_LIN) += drivers/peripherals/usart_lin.o\r
+drivers-$(CONFIG_HAVE_PIO4) += drivers/peripherals/pio4.o\r
+drivers-$(CONFIG_HAVE_QSPI) += drivers/peripherals/qspi.o\r
+drivers-$(CONFIG_HAVE_MCAN) += drivers/peripherals/mcan.o\r
+drivers-$(CONFIG_HAVE_SDMMC) += drivers/peripherals/sdmmc.o\r
+\r
+drivers-$(CONFIG_SOC_SAMA5D2) += drivers/peripherals/acc.o\r
+drivers-$(CONFIG_SOC_SAMA5D2) += drivers/peripherals/classd.o\r
+drivers-$(CONFIG_SOC_SAMA5D2) += drivers/peripherals/isc.o\r
+drivers-$(CONFIG_SOC_SAMA5D2) += drivers/peripherals/sfrbu.o\r
+drivers-$(CONFIG_SOC_SAMA5D2) += drivers/peripherals/shdwc.o\r
+drivers-$(CONFIG_SOC_SAMA5D2) += drivers/peripherals/twid.o\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/acc.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define ACC_MR_INV_Pos 12 /* ACC invert output (reg offset) */\r
+\r
+#define ACC_ACR_HYST_0mv_max 0x00 /* Hysteresis levels */\r
+#define ACC_ACR_HYST_50mv_max 0x01\r
+#define ACC_ACR_HYST_90mv_max 0x11\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void acc_init(Acc *p_acc, uint32_t select_plus, uint32_t select_minus,\r
+ uint32_t edge_type, uint32_t invert)\r
+{\r
+ /* Reset the controller */\r
+ p_acc->ACC_CR |= ACC_CR_SWRST;\r
+\r
+ /* Write to the MR register */\r
+ p_acc->ACC_MR = (((select_plus << ACC_MR_SELPLUS_Pos) & ACC_MR_SELPLUS_Msk) |\r
+ ((select_minus << ACC_MR_SELMINUS_Pos) & ACC_MR_SELMINUS_Msk) |\r
+ ((edge_type << ACC_MR_EDGETYP_Pos) & ACC_MR_EDGETYP_Msk) |\r
+ ((invert << ACC_MR_INV_Pos) & ACC_MR_INV));\r
+\r
+ /* Set hysteresis and current selection (ISEL) */\r
+ p_acc->ACC_ACR = (ACC_ACR_ISEL_HISP | ACC_ACR_HYST(ACC_ACR_HYST_50mv_max));\r
+\r
+ /* Automatic Output Masking Period */\r
+ while (p_acc->ACC_ISR & (uint32_t)ACC_ISR_MASK) ;\r
+}\r
+\r
+void acc_enable(Acc *p_acc)\r
+{\r
+ p_acc->ACC_MR |= ACC_MR_ACEN_EN;\r
+}\r
+\r
+void acc_disable(Acc *p_acc)\r
+{\r
+ p_acc->ACC_MR &= ~ACC_MR_ACEN_EN;\r
+}\r
+\r
+void acc_reset(Acc *p_acc)\r
+{\r
+ p_acc->ACC_CR = ACC_CR_SWRST;\r
+}\r
+\r
+void acc_set_input(Acc *p_acc, uint32_t select_minus, uint32_t select_plus)\r
+{\r
+ p_acc->ACC_MR &= ~(ACC_MR_SELMINUS_Msk & ACC_MR_SELPLUS_Msk);\r
+ p_acc->ACC_MR |= select_plus | select_minus;\r
+}\r
+\r
+void acc_set_output(Acc *p_acc, uint32_t invert, uint32_t fault_enable,\r
+ uint32_t fault_source)\r
+{\r
+ p_acc->ACC_MR &= ~(ACC_MR_INV_EN & ACC_MR_FE_EN & ACC_MR_SELFS_OUTPUT);\r
+ p_acc->ACC_MR |= invert | fault_source | fault_enable;\r
+}\r
+\r
+uint32_t acc_get_comparison_result(Acc *p_acc)\r
+{\r
+ uint32_t temp = p_acc->ACC_MR;\r
+ uint32_t status = p_acc->ACC_ISR;\r
+\r
+ if ((temp & ACC_MR_INV_EN) == ACC_MR_INV_EN)\r
+ return status & ACC_ISR_SCO ? 0 : 1;\r
+ else\r
+ return status & ACC_ISR_SCO ? 1 : 0;\r
+}\r
+\r
+void acc_enable_interrupt(Acc *p_acc)\r
+{\r
+ p_acc->ACC_IER = ACC_IER_CE;\r
+}\r
+\r
+void acc_disable_interrupt(Acc *p_acc)\r
+{\r
+ p_acc->ACC_IDR = ACC_IDR_CE;\r
+}\r
+\r
+uint32_t acc_get_interrupt_status(Acc *p_acc)\r
+{\r
+ return p_acc->ACC_ISR;\r
+}\r
+\r
+void acc_set_write_protect(Acc *p_acc, uint32_t enable)\r
+{\r
+ if (enable)\r
+ p_acc->ACC_WPMR = ACC_WPMR_WPKEY_PASSWD | ACC_WPMR_WPEN;\r
+ else\r
+ p_acc->ACC_WPMR = ACC_WPMR_WPKEY_PASSWD;\r
+}\r
+\r
+uint32_t acc_get_write_protect_status(Acc *p_acc)\r
+{\r
+ return p_acc->ACC_WPSR & ACC_WPSR_WPVS;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+* \file\r
+*\r
+* Implementation of Analog Comparator Controller (ACC).\r
+*\r
+*/\r
+\r
+#ifndef _ACC_H\r
+#define _ACC_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initialize the Analog Comparator Controller.\r
+ * \param p_acc Pointer to an Acc instance.\r
+ * \param select_plus Input connected to inp, 0~7.\r
+ * \param select_minus Input connected to inm, 0~7.\r
+ * \param edge_type CF flag triggering mode\r
+ * Use pattern defined in the device header file.\r
+ * \param invert Invert comparator output.\r
+ */\r
+extern void acc_init(Acc *p_acc, uint32_t select_plus, uint32_t select_minus,\r
+ uint32_t edge_type, uint32_t invert);\r
+\r
+/**\r
+ * \brief Enable the ACC.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ */\r
+extern void acc_enable(Acc *p_acc);\r
+\r
+/**\r
+ * \brief Disable the ACC.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ */\r
+extern void acc_disable(Acc *p_acc);\r
+\r
+/**\r
+ * \brief Reset the ACC.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ */\r
+extern void acc_reset(Acc *p_acc);\r
+\r
+/**\r
+ * \brief Set the input source.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ * \param select_minus Selection for minus comparator input.\r
+ * \param select_plus Selection for plus comparator input.\r
+ */\r
+extern void acc_set_input(Acc *p_acc, uint32_t select_minus,\r
+ uint32_t select_plus);\r
+\r
+/**\r
+ * \brief Set the output of the ACC.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ * \param invert Invert comparator output, 0 for disable, 1 for enable.\r
+ * \param fault_enable Fault enable, 0 for disable, 1 for enable.\r
+ * \param fault_source Selection of fault source, 0 for CF, 1 for output.\r
+ */\r
+extern void acc_set_output(Acc *p_acc, uint32_t invert, uint32_t fault_enable,\r
+ uint32_t fault_source);\r
+\r
+/**\r
+ * \brief Get the comparison result.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ * \return Result of the comparison, 0 for inn > inp, 1 for inp > inn.\r
+ */\r
+extern uint32_t acc_get_comparison_result(Acc *p_acc);\r
+\r
+/**\r
+ * \brief Enable the interrupt.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ */\r
+extern void acc_enable_interrupt(Acc *p_acc);\r
+\r
+/**\r
+ * \brief Disable the interrupt.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ */\r
+extern void acc_disable_interrupt(Acc *p_acc);\r
+\r
+/**\r
+ * \brief Get the interrupt status.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ * \return Contents of the Interrupt Status Register.\r
+ */\r
+extern uint32_t acc_get_interrupt_status(Acc *p_acc);\r
+\r
+/**\r
+ * \brief Write-protect the Mode Register and the Analog Control Register.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ * \param enable 1 to enable, 0 to disable.\r
+ */\r
+extern void acc_set_write_protect(Acc *p_acc, uint32_t enable);\r
+\r
+/**\r
+ * \brief Return write protect status.\r
+ * \param p_acc Pointer to ACC registers set instance.\r
+ * \retval 0 No write protection violation occurred.\r
+ * \retval 1 At least one write attempt to a write-protected register has been\r
+ * detected, since the previous call to this function.\r
+ */\r
+extern uint32_t acc_get_write_protect_status(Acc *p_acc);\r
+\r
+#endif /* _ACC_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup adc_module Working with ADC\r
+ * \ingroup peripherals_module\r
+ * \section Purpose\r
+ * The ADC driver provides the interface to configure and use the ADC peripheral.\r
+ * \n\r
+ *\r
+ * It converts the analog input to digital format. The converted result could be\r
+ * 12bit.\r
+ *\r
+ * To Enable a ADC conversion,the user has to follow these few steps:\r
+ * <ul>\r
+ * <li> Select an appropriate reference voltage on ADVREF </li>\r
+ * <li> Configure the ADC according to its requirements and special needs,which\r
+ * could be broken down into several parts:\r
+ * -# Select the resolution by setting or clearing ADC_MR_LOWRES bit in\r
+ * ADC_MR (Mode Register)\r
+ * -# Set ADC clock by setting ADC_MR_PRESCAL bits in ADC_MR, the clock is\r
+ * calculated with ADCClock = MCK / ( (PRESCAL+1) * 2 )\r
+ * -# Set Startup Time,Tracking Clock cycles and Transfer Clock respectively\r
+ * in ADC_MR.\r
+ </li>\r
+ * <li> Start conversion by setting ADC_CR_START in ADC_CR. </li>\r
+ * </ul>\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Initialize the ADC controller using adc_initialize().\r
+ * <li> ADC clock and timing configuration using adc_set_clock() and adc_set_timing().\r
+ * <li> For ADC trigger using adc_set_trigger(), adc_set_trigger_mode() and\r
+ * adc_set_trigger_period().\r
+ * <li> For ADC sequence mode using adc_set_sequence_mode(), adc_set_sequence() and\r
+ * adc_set_sequence_by_list().\r
+ * <li> For ADC compare mode using adc_set_compare_channel(), adc_set_compare_mode()\r
+ * and adc_set_comparison_window().\r
+ * <li> ADC works with touchscreen using adc_ts_calibration(), adc_set_ts_mode(),\r
+ * adc_set_ts_debounce(), adc_set_ts_pen_detect(), adc_set_ts_average(),\r
+ * adc_get_ts_xposition(), adc_get_ts_yposition() and adc_get_ts_pressure().\r
+ * </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the ADC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref adc.c\n\r
+ * \ref adc.h\n\r
+ */\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Analog-to-Digital Converter (ADC).\r
+ *\r
+ */\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/adc.h"\r
+#include "peripherals/pmc.h"\r
+\r
+#include "trace.h"\r
+\r
+#include <stdio.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifndef ADC_MR_TRANSFER\r
+/* for compatibility with older peripheral versions */\r
+#define ADC_MR_TRANSFER(x) 0\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Current working clock */\r
+static uint32_t _adc_clock = 0;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+uint32_t adc_num_channels(void)\r
+{\r
+ return ARRAY_SIZE(ADC->ADC_CDR);\r
+}\r
+\r
+/**\r
+ * \brief Initialize the ADC controller\r
+ *\r
+ */\r
+void adc_initialize(void)\r
+{\r
+ /* Enable peripheral clock */\r
+ pmc_enable_peripheral(ID_ADC);\r
+\r
+ /* Reset the controller */\r
+ ADC->ADC_CR = ADC_CR_SWRST;\r
+\r
+ /* Reset Mode Register */\r
+ ADC->ADC_MR = 0;\r
+\r
+}\r
+\r
+/**\r
+ * \brief Set ADC clock.\r
+ *\r
+ * \param clk adc clock frequency\r
+ *\r
+ * \return ADC clock\r
+ */\r
+uint32_t adc_set_clock(uint32_t clk)\r
+{\r
+ uint32_t prescale, mode_reg;\r
+ uint32_t mck = pmc_get_peripheral_clock(ID_ADC);\r
+ /* Formula for PRESCAL is:\r
+ ADCClock = MCK / ( (PRESCAL+1) * 2 )\r
+ PRESCAL = (MCK / (2 * ADCCLK)) + 1\r
+ First, we do the division, multiplied by 10 to get higher precision\r
+ If the last digit is not zero, we round up to avoid generating a higher\r
+ than required frequency. */\r
+ prescale = (mck * 5) / clk;\r
+ if (prescale % 10)\r
+ prescale = prescale / 10;\r
+ else {\r
+ if (prescale == 0)\r
+ return 0;\r
+ prescale = prescale / 10 - 1;\r
+ }\r
+\r
+ mode_reg = ADC_MR_PRESCAL(prescale);\r
+ if (mode_reg == 0)\r
+ return 0;\r
+\r
+ mode_reg |= (ADC->ADC_MR & ~ADC_MR_PRESCAL_Msk);\r
+ ADC->ADC_MR = mode_reg;\r
+\r
+ _adc_clock = mck / (prescale + 1) / 2;\r
+ //_adc_clock = _adc_clock / 1000 * 1000;\r
+ return _adc_clock;\r
+}\r
+\r
+void adc_enable_it(uint32_t mask)\r
+{\r
+ ADC->ADC_IER |= mask;\r
+}\r
+\r
+void adc_disable_it(uint32_t mask)\r
+{\r
+ ADC->ADC_IER &= ~mask;\r
+}\r
+\r
+/**\r
+ * \brief Set ADC timing.\r
+ *\r
+ * \param startup startup value\r
+ * \param tracking tracking value\r
+ * \param settling settling value\r
+ */\r
+void adc_set_timing(uint32_t startup, uint32_t tracking, uint32_t settling)\r
+{\r
+ uint32_t mode_reg;\r
+\r
+#ifndef CONFIG_HAVE_ADC_SETTLING_TIME\r
+ if (settling) {\r
+ settling = 0;\r
+ trace_warning("adc: Analog settling time not supported, IGNORED!\r\n");\r
+ }\r
+#endif\r
+\r
+ mode_reg = ADC->ADC_MR;\r
+ mode_reg &= (~ADC_MR_STARTUP_Msk) & (~ADC_MR_TRACKTIM_Msk);\r
+\r
+ /* Formula:\r
+ * Startup Time = startup value / ADCClock\r
+ * Transfer Time = (TRANSFER * 2 + 3) / ADCClock\r
+ * Tracking Time = (TRACKTIM + 1) / ADCClock\r
+ * Settling Time = settling value / ADCClock\r
+ */\r
+ mode_reg |= ADC_MR_STARTUP(startup);\r
+ mode_reg |= ADC_MR_TRACKTIM(tracking);\r
+ mode_reg |= ADC_MR_TRANSFER(2);\r
+#ifdef CONFIG_HAVE_ADC_SETTLING_TIME\r
+ mode_reg |= ADC_MR_SETTLING(settling);\r
+#endif\r
+ ADC->ADC_MR |= mode_reg;\r
+}\r
+\r
+void adc_set_trigger_mode(uint32_t mode)\r
+{\r
+ uint32_t trg_reg = ADC->ADC_TRGR & ~ADC_TRGR_TRGMOD_Msk;\r
+ ADC->ADC_TRGR = trg_reg | mode;\r
+}\r
+\r
+void adc_set_sleep_mode(uint8_t enable)\r
+{\r
+ if (enable) {\r
+ ADC->ADC_MR |= ADC_MR_SLEEP;\r
+ } else {\r
+ ADC->ADC_MR &= ~ADC_MR_SLEEP;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable seqnence mode.\r
+ *\r
+ * \param enable Enable/Disable seqnence mode.\r
+ */\r
+void adc_set_sequence_mode(uint8_t enable)\r
+{\r
+ if (enable) {\r
+ /* User Sequence Mode: The sequence respects what is defined in\r
+ ADC_SEQR1 and ADC_SEQR2 */\r
+ ADC->ADC_MR |= ADC_MR_USEQ;\r
+ } else {\r
+ /* Normal Mode: The controller converts channels in a simple numeric order. */\r
+ ADC->ADC_MR &= ~ADC_MR_USEQ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set channel sequence.\r
+ *\r
+ * \param seq1 Sequence 1 ~ 8 channel number.\r
+ * \param seq2 Sequence 9 ~ 16 channel number.\r
+ */\r
+\r
+void adc_set_sequence(uint32_t seq1, uint32_t seq2)\r
+{\r
+ ADC->ADC_SEQR1 = seq1;\r
+#ifdef CONFIG_HAVE_ADC_SEQ_REG2\r
+ ADC->ADC_SEQR2 = seq2;\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Set channel sequence by given channel list.\r
+ *\r
+ * \param channel_list Channel list.\r
+ * \param len Number of channels in list.\r
+ */\r
+\r
+void adc_set_sequence_by_list(uint8_t channel_list[], uint8_t len)\r
+{\r
+ uint8_t i;\r
+ uint8_t shift;\r
+\r
+ if (len <= 8) {\r
+ ADC->ADC_SEQR1 = 0;\r
+ for (i = 0, shift = 0; i < len; i++, shift += 4) {\r
+ if (i >= len) return;\r
+ ADC->ADC_SEQR1 |= channel_list[i] << shift;\r
+ }\r
+ }\r
+ else {\r
+ ADC->ADC_SEQR1 = 0;\r
+ for (i = 0, shift = 0; i < 8; i++, shift += 4) {\r
+ if (i >= len) return;\r
+ ADC->ADC_SEQR1 |= channel_list[i] << shift;\r
+ }\r
+#ifdef CONFIG_HAVE_ADC_SEQ_REG2\r
+ ADC->ADC_SEQR2 = 0;\r
+ for (i = 0, shift = 0; i < (len-8); i++, shift += 4) {\r
+ if (i >= len) return;\r
+ ADC->ADC_SEQR2 |= channel_list[8+i] << shift;\r
+ }\r
+#endif\r
+ }\r
+}\r
+\r
+void adc_set_tag_enable(uint8_t enable)\r
+{\r
+ if (enable) {\r
+ ADC->ADC_EMR |= ADC_EMR_TAG;\r
+ } else {\r
+ ADC->ADC_EMR &= ~ADC_EMR_TAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set compare channel.\r
+ *\r
+ * \param channel channel number to be set, xx for all channels\r
+ */\r
+void adc_set_compare_channel(uint32_t channel)\r
+{\r
+ assert(channel <= adc_num_channels());\r
+\r
+ if (channel < adc_num_channels()) {\r
+ ADC->ADC_EMR &= ~(ADC_EMR_CMPALL);\r
+ ADC->ADC_EMR &= ~(ADC_EMR_CMPSEL_Msk);\r
+ ADC->ADC_EMR |= (channel << ADC_EMR_CMPSEL_Pos);\r
+ } else {\r
+ ADC->ADC_EMR |= ADC_EMR_CMPALL;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set compare mode.\r
+ *\r
+ * \param mode compare mode\r
+ */\r
+void adc_set_compare_mode(uint32_t mode)\r
+{\r
+ ADC->ADC_EMR &= ~(ADC_EMR_CMPMODE_Msk);\r
+ ADC->ADC_EMR |= (mode & ADC_EMR_CMPMODE_Msk);\r
+}\r
+\r
+void adc_set_comparison_window(uint32_t window)\r
+{\r
+ ADC->ADC_CWR = window;\r
+}\r
+\r
+uint8_t adc_check_configuration(void)\r
+{\r
+ uint32_t mode_reg;\r
+ uint32_t prescale;\r
+ uint32_t clock;\r
+ uint32_t mck = pmc_get_peripheral_clock(ID_ADC);\r
+\r
+ mode_reg = ADC->ADC_MR;\r
+\r
+ prescale = (mode_reg & ADC_MR_PRESCAL_Msk) >> ADC_MR_PRESCAL_Pos;\r
+ /* Formula: ADCClock = MCK / ( (PRESCAL+1) * 2 ) */\r
+ clock = mck / ((prescale + 1) * 2);\r
+ if (clock > ADC_CLOCK_MAX) {\r
+ printf ("ADC clock is too high (out of specification: %d Hz)\r\n",\r
+ (int) ADC_CLOCK_MAX);\r
+ return 1;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+uint32_t adc_get_converted_data(uint32_t channel)\r
+{\r
+ assert(channel < adc_num_channels());\r
+\r
+ if (channel < adc_num_channels()) {\r
+ return ADC->ADC_CDR[channel];\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+void adc_set_startup_time(uint32_t startup)\r
+{\r
+ uint32_t start;\r
+ uint32_t mode_reg;\r
+\r
+ if (_adc_clock == 0)\r
+ return;\r
+ /* Formula for STARTUP is:\r
+ STARTUP = (time x ADCCLK) / (1000000) - 1\r
+ Division multiplied by 10 for higher precision */\r
+\r
+ start = (startup * _adc_clock) / (100000);\r
+ if (start % 10)\r
+ start /= 10;\r
+ else {\r
+ start /= 10;\r
+ if (start)\r
+ start--;\r
+ }\r
+ if (start > 896)\r
+ mode_reg = ADC_MR_STARTUP_SUT960;\r
+ else if (start > 832)\r
+ mode_reg = ADC_MR_STARTUP_SUT896;\r
+ else if (start > 768)\r
+ mode_reg = ADC_MR_STARTUP_SUT832;\r
+ else if (start > 704)\r
+ mode_reg = ADC_MR_STARTUP_SUT768;\r
+ else if (start > 640)\r
+ mode_reg = ADC_MR_STARTUP_SUT704;\r
+ else if (start > 576)\r
+ mode_reg = ADC_MR_STARTUP_SUT640;\r
+ else if (start > 512)\r
+ mode_reg = ADC_MR_STARTUP_SUT576;\r
+ else if (start > 112)\r
+ mode_reg = ADC_MR_STARTUP_SUT512;\r
+ else if (start > 96)\r
+ mode_reg = ADC_MR_STARTUP_SUT112;\r
+ else if (start > 80)\r
+ mode_reg = ADC_MR_STARTUP_SUT96;\r
+ else if (start > 64)\r
+ mode_reg = ADC_MR_STARTUP_SUT80;\r
+ else if (start > 24)\r
+ mode_reg = ADC_MR_STARTUP_SUT64;\r
+ else if (start > 16)\r
+ mode_reg = ADC_MR_STARTUP_SUT24;\r
+ else if (start > 8)\r
+ mode_reg = ADC_MR_STARTUP_SUT16;\r
+ else if (start > 0)\r
+ mode_reg = ADC_MR_STARTUP_SUT8;\r
+ else\r
+ mode_reg = ADC_MR_STARTUP_SUT0;\r
+\r
+ mode_reg |= ADC->ADC_MR & ~ADC_MR_STARTUP_Msk;\r
+ ADC->ADC_MR = mode_reg;\r
+}\r
+\r
+#ifdef CONFIG_HAVE_ADC_INPUT_OFFSET\r
+/**\r
+ * \brief Enable differential input for the specified channel.\r
+ *\r
+ * \param channel ADC channel number.\r
+ */\r
+void adc_enable_channel_differential_input (uint32_t channel)\r
+{\r
+ /* (ADC_COR) Differential Inputs for Channel n */\r
+ ADC->ADC_COR |= 0x01u << (16 + channel);\r
+}\r
+\r
+/**\r
+ * \brief Disable differential input for the specified channel.\r
+ *\r
+ * \param channel ADC channel number.\r
+ */\r
+void adc_disable_channel_differential_input(uint32_t channel)\r
+{\r
+ uint32_t temp;\r
+ temp = ADC->ADC_COR;\r
+ ADC->ADC_COR &= 0xFFFEFFFFu << channel;\r
+ ADC->ADC_COR |= temp;\r
+}\r
+\r
+/**\r
+ * \brief Enable analog signal offset for the specified channel.\r
+ *\r
+ * \param channel ADC channel number.\r
+ */\r
+void adc_enable_channel_input_offset (uint32_t channel)\r
+{\r
+ ADC->ADC_COR |= 0x01u << channel;\r
+}\r
+\r
+/**\r
+ * \brief Disable analog signal offset for the specified channel.\r
+ *\r
+ * \param channel ADC channel number.\r
+ */\r
+void adc_disable_channel_input_offset (uint32_t channel)\r
+{\r
+ uint32_t temp;\r
+ temp = ADC->ADC_COR;\r
+ ADC->ADC_COR &= (0xFFFFFFFEu << channel);\r
+ ADC->ADC_COR |= temp;\r
+}\r
+#endif /* CONFIG_HAVE_ADC_INPUT_OFFSET */\r
+\r
+#ifdef CONFIG_HAVE_ADC_INPUT_GAIN\r
+/**\r
+ * \brief Configure input gain for the specified channel.\r
+ *\r
+ * \param channel ADC channel number.\r
+ * \param gain Gain value for the input.\r
+ */\r
+void adc_set_channel_input_gain (uint32_t channel, uint32_t gain)\r
+{\r
+ assert(gain < 3);\r
+ uint32_t temp;\r
+ temp = ADC->ADC_CGR;\r
+ temp |= gain << (2 * channel);\r
+ ADC->ADC_CGR = temp;\r
+}\r
+#endif /* CONFIG_HAVE_ADC_INPUT_GAIN */\r
+\r
+void adc_set_tracking_time(uint32_t dwNs)\r
+{\r
+ uint32_t dwShtim;\r
+ uint32_t mode_reg;\r
+\r
+ if (_adc_clock == 0)\r
+ return;\r
+ /* Formula for SHTIM is:\r
+ SHTIM = (time x ADCCLK) / (1000000000) - 1\r
+ Since 1 billion is close to the maximum value for an integer, we first\r
+ divide ADCCLK by 1000 to avoid an overflow */\r
+ dwShtim = (dwNs * (_adc_clock / 1000)) / 100000;\r
+ if (dwShtim % 10)\r
+ dwShtim /= 10;\r
+ else {\r
+ dwShtim /= 10;\r
+ if (dwShtim)\r
+ dwShtim--;\r
+ }\r
+ mode_reg = ADC_MR_TRACKTIM(dwShtim);\r
+ mode_reg |= ADC->ADC_MR & ~ADC_MR_TRACKTIM_Msk;\r
+ ADC->ADC_MR = mode_reg;\r
+}\r
+\r
+void adc_set_trigger_period(uint32_t period)\r
+{\r
+ uint32_t trg_period;\r
+ uint32_t trg_reg;\r
+ if (_adc_clock == 0)\r
+ return;\r
+ trg_period = period * (_adc_clock/1000) - 1;\r
+ trg_reg = ADC->ADC_TRGR & ~ADC_TRGR_TRGPER_Msk;\r
+ trg_reg |= ADC_TRGR_TRGPER(trg_period);\r
+ ADC->ADC_TRGR = trg_reg;\r
+}\r
+\r
+void adc_ts_calibration(void)\r
+{\r
+ ADC->ADC_CR = ADC_CR_TSCALIB;\r
+}\r
+\r
+void adc_set_ts_mode(uint32_t mode)\r
+{\r
+ ADC->ADC_TSMR = (ADC->ADC_TSMR & ~ADC_TSMR_TSMODE_Msk) | mode;\r
+}\r
+\r
+void adc_configure_ext_mode(uint32_t mode)\r
+{\r
+ ADC->ADC_EMR = mode;\r
+}\r
+\r
+void adc_set_ts_debounce(uint32_t time)\r
+{\r
+ uint32_t div = 1000000000;\r
+ uint32_t clk = _adc_clock;\r
+ uint32_t dwPenbc = 0;\r
+ uint32_t target, current;\r
+ uint32_t tsmr;\r
+ if (time == 0 || _adc_clock == 0)\r
+ return;\r
+ /* Divide time & ADCCLK to avoid overflows */\r
+ while ((div > 1) && ((time % 10) == 0)) {\r
+ time /= 10;\r
+ div /= 10;\r
+ }\r
+ while ((div > 1) && ((clk & 10) == 0)) {\r
+ clk /= 10;\r
+ div /= 10;\r
+ }\r
+ /* Compute PENDBC */\r
+ target = time * clk / div;\r
+ current = 1;\r
+ while (current < target) {\r
+ dwPenbc++;\r
+ current *= 2;\r
+ }\r
+ tsmr = ADC_TSMR_PENDBC(dwPenbc);\r
+ if (tsmr == 0)\r
+ return;\r
+ tsmr |= ADC->ADC_TSMR & ~ADC_TSMR_PENDBC_Msk;\r
+ ADC->ADC_TSMR = tsmr;\r
+}\r
+\r
+void adc_set_ts_pen_detect(uint8_t enable)\r
+{\r
+ if (enable)\r
+ ADC->ADC_TSMR |= ADC_TSMR_PENDET;\r
+ else\r
+ ADC->ADC_TSMR &= ~ADC_TSMR_PENDET;\r
+}\r
+\r
+void adc_set_ts_average(uint32_t avg_2_conv)\r
+{\r
+ uint32_t mode_reg = ADC->ADC_TSMR & ~ADC_TSMR_TSAV_Msk;\r
+ uint32_t ts_av = avg_2_conv >> ADC_TSMR_TSAV_Pos;\r
+ uint32_t ts_freq = (mode_reg & ADC_TSMR_TSFREQ_Msk) >> ADC_TSMR_TSFREQ_Pos;\r
+ if (ts_av) {\r
+ if (ts_av > ts_freq) {\r
+ mode_reg &= ~ADC_TSMR_TSFREQ_Msk;\r
+ mode_reg |= ADC_TSMR_TSFREQ(ts_av);\r
+ }\r
+ }\r
+ ADC->ADC_TSMR = mode_reg | avg_2_conv;\r
+}\r
+\r
+uint32_t adc_get_ts_xposition(void)\r
+{\r
+ return ADC->ADC_XPOSR;\r
+}\r
+\r
+uint32_t adc_get_ts_yposition(void)\r
+{\r
+ return ADC->ADC_YPOSR;\r
+}\r
+\r
+uint32_t adc_get_ts_pressure(void)\r
+{\r
+ return ADC->ADC_PRESSR;\r
+}\r
+\r
+void adc_set_trigger(uint32_t trigger)\r
+{\r
+ uint32_t mode_reg;\r
+\r
+ mode_reg = ADC->ADC_MR;\r
+ mode_reg &= ~ADC_MR_TRGSEL_Msk;\r
+ mode_reg |= trigger;\r
+ ADC->ADC_MR |= mode_reg;\r
+}\r
+\r
+#ifdef CONFIG_HAVE_ADC_LOW_RES\r
+void adc_set_low_resolution(uint8_t enable)\r
+{\r
+ if (enable) {\r
+ ADC->ADC_MR |= ADC_MR_LOWRES;\r
+ } else {\r
+ ADC->ADC_MR &= ~ADC_MR_LOWRES;\r
+ }\r
+}\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Interface for configuration the Analog-to-Digital Converter (ADC) peripheral.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Configurate the pins for ADC.\r
+ * -# Initialize the ADC with adc_initialize().\r
+ * -# Set ADC clock and timing with adc_set_clock() and adc_set_timing().\r
+ * -# Select the active channel using adc_enable_channel().\r
+ * -# Start the conversion with adc_start_conversion().\r
+ * -# Wait the end of the conversion by polling status with adc_get_status().\r
+ * -# Finally, get the converted data using adc_get_converted_data() or adc_get_last_converted_data().\r
+ *\r
+*/\r
+#ifndef _ADC_\r
+#define _ADC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <assert.h>\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/* Max. ADC Clock Frequency (Hz) */\r
+#define ADC_CLOCK_MAX 20000000\r
+\r
+/* Max. normal ADC startup time (us) */\r
+#define ADC_STARTUP_NORMAL_MAX 40\r
+/* Max. fast ADC startup time (us) */\r
+#define ADC_STARTUP_FAST_MAX 12\r
+\r
+/* Definitions for ADC channels */\r
+#define ADC_CHANNEL_0 0\r
+#define ADC_CHANNEL_1 1\r
+#define ADC_CHANNEL_2 2\r
+#define ADC_CHANNEL_3 3\r
+#define ADC_CHANNEL_4 4\r
+#define ADC_CHANNEL_5 5\r
+#define ADC_CHANNEL_6 6\r
+#define ADC_CHANNEL_7 7\r
+#define ADC_CHANNEL_8 8\r
+#define ADC_CHANNEL_9 9\r
+#define ADC_CHANNEL_10 10\r
+#define ADC_CHANNEL_11 11\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Macros function of register access\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#define adc_get_mode_reg() (ADC->ADC_MR)\r
+\r
+#define adc_start_conversion() (ADC->ADC_CR = ADC_CR_START)\r
+\r
+#define adc_enable_channel(channel) { \\r
+ ADC->ADC_CHER = (1 << (channel)); \\r
+ }\r
+\r
+#define adc_disable_channel(channel) { \\r
+ ADC->ADC_CHDR = (1 << (channel)); \\r
+ }\r
+\r
+#define adc_enable_interrupt(mode) { \\r
+ ADC->ADC_IER = (mode); \\r
+ }\r
+\r
+#define adc_disable_interrupt(mode) { \\r
+ ADC->ADC_IDR = (mode); \\r
+ }\r
+\r
+#define adc_set_channel_gain(mode) { \\r
+ ADC->ADC_CGR = mode; \\r
+ }\r
+\r
+#define adc_enable_data_ready_it() (ADC->ADC_IER = ADC_IER_DRDY)\r
+\r
+#define adc_get_status() (ADC->ADC_ISR)\r
+\r
+#define adc_get_compare_mode() ((ADC->ADC_EMR)& (ADC_EMR_CMPMODE_Msk))\r
+\r
+#define adc_get_channel_status() (ADC->ADC_CHSR)\r
+\r
+#define adc_interrupt_mask_status() (ADC->ADC_IMR)\r
+\r
+#define adc_get_last_converted_data() (ADC->ADC_LCDR)\r
+\r
+#define adc_get_overrun_status() (ADC->ADC_OVER)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Returns the number of ADC channels\r
+ */\r
+extern uint32_t adc_num_channels(void);\r
+\r
+/**\r
+ * \brief Initialize the ADC controller\r
+ */\r
+extern void adc_initialize(void);\r
+\r
+/**\r
+ * \brief Set ADC clock.\r
+ *\r
+ * \param clk Desired ADC clock frequency.\r
+ *\r
+ * \return ADC clock\r
+ */\r
+extern uint32_t adc_set_clock(uint32_t clk);\r
+\r
+/**\r
+ * \brief Enable ADC interrupt sources\r
+ *\r
+ * \param mask bitmask of the sources to enable\r
+ */\r
+extern void adc_enable_it(uint32_t mask);\r
+\r
+/**\r
+ * \brief Disable ADC interrupt sources\r
+ *\r
+ * \param mask bitmask of the sources to disable\r
+ */\r
+extern void adc_disable_it(uint32_t mask);\r
+\r
+/**\r
+ * \brief Set ADC timing.\r
+ *\r
+ * \param startup startup value\r
+ * \param tracking tracking value\r
+ * \param settling settling value\r
+ */\r
+extern void adc_set_timing(uint32_t startup, uint32_t tracking,\r
+ uint32_t settling);\r
+\r
+/**\r
+ * Sets the trigger mode to following:\r
+ * - \ref ADC_TRGR_TRGMOD_NO_TRIGGER\r
+ * - \ref ADC_TRGR_TRGMOD_EXT_TRIG_RISE\r
+ * - \ref ADC_TRGR_TRGMOD_EXT_TRIG_FALL\r
+ * - \ref ADC_TRGR_TRGMOD_EXT_TRIG_ANY\r
+ * - \ref ADC_TRGR_TRGMOD_PEN_TRIG\r
+ * - \ref ADC_TRGR_TRGMOD_PERIOD_TRIG\r
+ * - \ref ADC_TRGR_TRGMOD_CONTINUOUS\r
+ * \param mode Trigger mode.\r
+ */\r
+extern void adc_set_trigger_mode(uint32_t mode);\r
+\r
+/**\r
+ * \brief Enable/Disable sleep mode.\r
+ *\r
+ * \param enable Enable/Disable sleep mode.\r
+ */\r
+extern void adc_set_sleep_mode(uint8_t enable);\r
+\r
+extern void adc_set_fast_wakeup(uint8_t enable);\r
+\r
+/**\r
+ * \brief Enable/Disable seqnence mode.\r
+ *\r
+ * \param enable Enable/Disable seqnence mode.\r
+ */\r
+extern void adc_set_sequence_mode(uint8_t enable);\r
+\r
+/**\r
+ * \brief Set channel sequence.\r
+ *\r
+ * \param seq1 Sequence 1 ~ 8 channel number.\r
+ * \param seq2 Sequence 9 ~ 16 channel number.\r
+ */\r
+extern void adc_set_sequence(uint32_t seq1, uint32_t seq2);\r
+\r
+/**\r
+ * \brief Set channel sequence by given channel list.\r
+ *\r
+ * \param channel_list Channel list.\r
+ * \param len Number of channels in list.\r
+ */\r
+extern void adc_set_sequence_by_list(uint8_t channel_list[],\r
+ uint8_t len);\r
+\r
+/**\r
+ * \brief Set "TAG" mode, show channel number in last data or not.\r
+ *\r
+ * \param enable Enable/Disable TAG value.\r
+ */\r
+extern void adc_set_tag_enable(uint8_t enable);\r
+\r
+/**\r
+ * Configure extended mode register\r
+ * \param mode ADC extended mode.\r
+ */\r
+extern void adc_configure_ext_mode(uint32_t mode);\r
+\r
+/**\r
+ * \brief Set compare channel.\r
+ *\r
+ * \param channel channel number to be set,16 for all channels\r
+ */\r
+extern void adc_set_compare_channel(uint32_t channel);\r
+\r
+/**\r
+ * \brief Set compare mode.\r
+ *\r
+ * \param mode compare mode\r
+ */\r
+extern void adc_set_compare_mode(uint32_t mode);\r
+\r
+/**\r
+ * \brief Set comparsion window.\r
+ *\r
+ * \param window Comparison Window\r
+ */extern void adc_set_comparison_window(uint32_t window);\r
+\r
+/**\r
+ * \brief Check if ADC configuration is right.\r
+ *\r
+ * \return 0 if check ok, others if not ok.\r
+ */\r
+extern uint8_t adc_check_configuration(void);\r
+\r
+/**\r
+ * \brief Return the Channel Converted Data\r
+ *\r
+ * \param channel channel to get converted value\r
+ */\r
+extern uint32_t adc_get_converted_data(uint32_t channel);\r
+\r
+#ifdef CONFIG_HAVE_ADC_INPUT_OFFSET\r
+/**\r
+ * \brief Enable differential input for the specified channel.\r
+ *\r
+ * \param channel ADC channel number.\r
+ */\r
+extern void adc_enable_channel_differential_input (uint32_t channel);\r
+\r
+/**\r
+ * \brief Disable differential input for the specified channel.\r
+ *\r
+ * \param channel ADC channel number.\r
+ */\r
+extern void adc_disable_channel_differential_input(uint32_t channel);\r
+\r
+/**\r
+ * \brief Enable analog signal offset for the specified channel.\r
+ *\r
+ * \param channel ADC channel number.\r
+ */\r
+extern void adc_enable_channel_input_offset (uint32_t channel);\r
+\r
+/**\r
+ * \brief Disable analog signal offset for the specified channel.\r
+ *\r
+ * \param channel ADC channel number.\r
+ */\r
+extern void adc_disable_channel_input_offset (uint32_t channel);\r
+#endif /* CONFIG_HAVE_ADC_INPUT_OFFSET */\r
+\r
+#ifdef CONFIG_HAVE_ADC_INPUT_GAIN\r
+/**\r
+ * \brief Configure input gain for the specified channel.\r
+ *\r
+ * \param channel ADC channel number.\r
+ * \param gain Gain value for the input.\r
+ */\r
+extern void adc_set_channel_input_gain (uint32_t channel, uint32_t gain);\r
+#endif /* CONFIG_HAVE_ADC_INPUT_GAIN */\r
+\r
+/**\r
+ * Sets the average of the touch screen ADC. The mode can be:\r
+ * - \ref ADC_TSMR_TSAV_NO_FILTER (No filtering)\r
+ * - \ref ADC_TSMR_TSAV_AVG2CONV (Average 2 conversions)\r
+ * - \ref ADC_TSMR_TSAV_AVG4CONV (Average 4 conversions)\r
+ * - \ref ADC_TSMR_TSAV_AVG8CONV (Average 8 conversions)\r
+ * \param avg_2_conv Average mode for touch screen\r
+ */\r
+extern void adc_set_ts_average(uint32_t avg_2_conv);\r
+\r
+/**\r
+ * Return X measurement position value.\r
+ */\r
+extern uint32_t adc_get_ts_xposition(void);\r
+\r
+/**\r
+ * Return Y measurement position value.\r
+ */\r
+extern uint32_t adc_get_ts_yposition(void);\r
+\r
+/**\r
+ * Return Z measurement position value.\r
+ */\r
+extern uint32_t adc_get_ts_pressure(void);\r
+\r
+/**\r
+ * Sets the touchscreen pan debounce time.\r
+ * \param time Debounce time in nS.\r
+ */\r
+extern void adc_set_ts_debounce(uint32_t time);\r
+\r
+/**\r
+ * Enable/Disable touch screen pen detection.\r
+ * \param enable If true, pen detection is enabled;\r
+ * in normal mode otherwise.\r
+ */\r
+extern void adc_set_ts_pen_detect(uint8_t enable);\r
+\r
+/**\r
+ * Sets the ADC startup time.\r
+ * \param startup Startup time in uS.\r
+ */\r
+extern void adc_set_startup_time(uint32_t startup);\r
+\r
+/**\r
+ * Set ADC tracking time\r
+ * \param dwNs Tracking time in nS.\r
+ */\r
+extern void adc_set_tracking_time(uint32_t dwNs);\r
+\r
+/**\r
+ * Sets the trigger period.\r
+ * \param period Trigger period in nS.\r
+ */\r
+extern void adc_set_trigger_period(uint32_t period);\r
+\r
+/**\r
+ * Sets the operation mode of the touch screen ADC. The mode can be:\r
+ * - \ref ADC_TSMR_TSMODE_NONE (TSADC off)\r
+ * - \ref ADC_TSMR_TSMODE_4_WIRE_NO_PM\r
+ * - \ref ADC_TSMR_TSMODE_4_WIRE (CH 0~3 used)\r
+ * - \ref ADC_TSMR_TSMODE_5_WIRE (CH 0~4 used)\r
+ * \param mode Desired mode\r
+ */\r
+extern void adc_set_ts_mode(uint32_t mode);\r
+\r
+/**\r
+ * Start screen calibration (VDD/GND measurement)\r
+ */\r
+extern void adc_ts_calibration(void);\r
+\r
+/**\r
+ * \brief Set ADC trigger.\r
+ *\r
+ * \param trigger Trigger selection\r
+ */\r
+extern void adc_set_trigger(uint32_t trigger);\r
+\r
+#ifdef CONFIG_HAVE_ADC_LOW_RES\r
+/**\r
+ * \brief Enable/Disable low resolution.\r
+ *\r
+ * \param enable Enable/Disable low resolution.\r
+ */\r
+extern void adc_set_low_resolution(uint8_t enable);\r
+#endif /* CONFIG_HAVE_ADC_LOW_RES */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* _ADC_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup aes_module Working with AES\r
+ * \ingroup peripherals_module\r
+ * The AES driver provides the interface to configure and use the AES\r
+ * peripheral.\r
+ * \n\r
+ *\r
+ * The Advanced Encryption Standard (AES) specifies a FIPS-approved\r
+ * cryptographic algorithm that can be used to protect electronic data. The AES\r
+ * algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt\r
+ * (decipher) information.\r
+ * Encryption converts data to an unintelligible form called ciphertext.\r
+ * Decrypting the ciphertext converts the data back into its original form,\r
+ * called plaintext. The CIPHER bit in the AES Mode Register (AES_MR) allows\r
+ * selection between the encryption and the decryption processes. The AES is\r
+ * capable of using cryptographic keys of 128/192/256 bits to encrypt and\r
+ * decrypt data in blocks of 128 bits.\r
+ * This 128-bit/192-bit/256-bit key is defined in the Key Registers (AES_KEYWRx)\r
+ * and set by aes_write_key(). The input to the encryption processes of the CBC,\r
+ * CFB, and OFB modes includes, in addition to the plaintext, a 128-bit data\r
+ * block called the initialization vector (IV), which must be set using\r
+ * aes_set_vector(). The initialization vector is used in an initial step in the\r
+ * encryption of a message and in the corresponding decryption of the message.\r
+ * The Initialization Vector Registers are also used by the CTR mode to set the\r
+ * counter value.\r
+ *\r
+ * To enable AES encryption and decryption, the user has to follow these few\r
+ * steps:\r
+ * <ul>\r
+ * <li> A software triggered hardware reset of the AES interface is performed by\r
+ * aes_soft_reset().</li>\r
+ * <li> Configure AES algorithm mode, key mode, start mode and operation mode\r
+ * with aes_configure().</li>\r
+ * <li> Input AES data for encryption and decryption with function\r
+ * aes_set_input().</li>\r
+ * <li> Set AES key with fucntion aes_write_key().</li>\r
+ * <li> To start the encryption or the decryption process with aes_start().</li>\r
+ * <li> To get the encryption or decryption result by aes_get_output().</li>\r
+ * </ul>\r
+ *\r
+ *\r
+ * For more accurate information, please look at the AES section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref aes.c\n\r
+ * \ref aes.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Advanced Encryption Standard (AES)\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/aes.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void aes_start(void)\r
+{\r
+ AES->AES_CR = AES_CR_START;\r
+}\r
+\r
+void aes_soft_reset(void)\r
+{\r
+ AES->AES_CR = AES_CR_SWRST;\r
+}\r
+\r
+void aes_configure(uint32_t mode)\r
+{\r
+ AES->AES_MR = mode;\r
+}\r
+\r
+void aes_enable_it(uint32_t sources)\r
+{\r
+ AES->AES_IER = sources;\r
+}\r
+\r
+void aes_disable_it(uint32_t sources)\r
+{\r
+ AES->AES_IDR = sources;\r
+}\r
+\r
+uint32_t aes_get_status(void)\r
+{\r
+ return AES->AES_ISR;\r
+}\r
+\r
+void aes_write_key(const uint32_t * key, uint32_t len)\r
+{\r
+ AES->AES_KEYWR[0] = key[0];\r
+ AES->AES_KEYWR[1] = key[1];\r
+ AES->AES_KEYWR[2] = key[2];\r
+ AES->AES_KEYWR[3] = key[3];\r
+\r
+ if (len >= 24) {\r
+ AES->AES_KEYWR[4] = key[4];\r
+ AES->AES_KEYWR[5] = key[5];\r
+ }\r
+ if (len == 32) {\r
+ AES->AES_KEYWR[6] = key[6];\r
+ AES->AES_KEYWR[7] = key[7];\r
+ }\r
+}\r
+\r
+void aes_set_input(uint32_t * data)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i < 4; i++)\r
+ AES->AES_IDATAR[i] = data[i];\r
+}\r
+\r
+void aes_get_output(uint32_t * data)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i < 4; i++)\r
+ data[i] = AES->AES_ODATAR[i];\r
+}\r
+\r
+void aes_set_vector(const uint32_t * vector)\r
+{\r
+ AES->AES_IVR[0] = vector[0];\r
+ AES->AES_IVR[1] = vector[1];\r
+ AES->AES_IVR[2] = vector[2];\r
+ AES->AES_IVR[3] = vector[3];\r
+}\r
+\r
+void aes_set_aad_len(uint32_t len)\r
+{\r
+ AES->AES_AADLENR = len;\r
+}\r
+\r
+void aes_set_data_len(uint32_t len)\r
+{\r
+ AES->AES_CLENR = len;\r
+}\r
+\r
+void aes_set_gcm_hash(uint32_t * hash)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i < 4; i++)\r
+ AES->AES_GHASHR[i] = hash[i];\r
+}\r
+\r
+void aes_get_gcm_tag(uint32_t * tag)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i < 4; i++)\r
+ tag[i] = AES->AES_TAGR[i];\r
+}\r
+\r
+void aes_get_gcm_counter(uint32_t * counter)\r
+{\r
+ *counter = AES->AES_CTRR;\r
+}\r
+\r
+void aes_get_gcm_hash_subkey(uint32_t * h)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i < 4; i++)\r
+ h[i] = AES->AES_GCMHR[i];\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _AES_\r
+#define _AES_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Definition */\r
+/*------------------------------------------------------------------------------*/\r
+#define AES_MR_CIPHER_ENCRYPT 1\r
+#define AES_MR_CIPHER_DECRYPT 0\r
+/*------------------------------------------------------------------------------*/\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Starts Manual encryption/decryption process.\r
+ */\r
+void aes_start(void);\r
+\r
+/**\r
+ * \brief Resets the AES.\r
+ * A software triggered hardware reset of the AES interface is performed.\r
+ */\r
+void aes_soft_reset(void);\r
+\r
+/**\r
+ * \brief Configures an AES peripheral with the specified parameters.\r
+ * \param mode Desired value for the AES mode register (see the datasheet).\r
+ */\r
+void aes_configure(uint32_t mode);\r
+\r
+/**\r
+ * \brief Enables the selected interrupts sources on a AES peripheral.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void aes_enable_it(uint32_t sources);\r
+\r
+/**\r
+ * \brief Disables the selected interrupts sources on a AES peripheral.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void aes_disable_it(uint32_t sources);\r
+\r
+/**\r
+ * \brief Get the current status register of the given AES peripheral.\r
+ * \return AES status register.\r
+ */\r
+extern uint32_t aes_get_status(void);\r
+\r
+/**\r
+ * \brief Set the 128-bit/192-bit/256-bit cryptographic key used for\r
+ * encryption/decryption.\r
+ * \param key Pointer to a 16/24/32 bytes cipher key.\r
+ * \param len Length of the key, in bytes.\r
+ */\r
+void aes_write_key(const uint32_t * key, uint32_t len);\r
+\r
+/**\r
+ * \brief Set the for 32-bit input Data allow to set the 128-bit data block used\r
+ * for encryption/decryption.\r
+ * \param data Pointer to the 16-bytes data to cipher/decipher.\r
+ */\r
+void aes_set_input(uint32_t * data);\r
+\r
+/**\r
+ * \brief Get the four 32-bit data contain the 128-bit data block which has\r
+ * been encrypted/decrypted.\r
+ * \param data Pointer to the word that has been encrypted/decrypted..\r
+ */\r
+void aes_get_output(uint32_t * data);\r
+\r
+/**\r
+ * \brief Set four 64-bit initialization vector data block, which is used by\r
+ * some modes of operation as an additional initial input.\r
+ * \param vector Pointer to the word of the initialization vector.\r
+ */\r
+void aes_set_vector(const uint32_t * vector);\r
+\r
+/**\r
+ * \brief Set Length in bytes of the Additional Authenticated Data that are to\r
+ * be processed.\r
+ * \param len Length.\r
+ */\r
+void aes_set_aad_len(uint32_t len);\r
+\r
+/**\r
+ * \brief Set Length in bytes of the plaintext/ciphertext data (that is, the C\r
+ * portion of the message) that are to be processed.\r
+ * \param len Length.\r
+ */\r
+void aes_set_data_len(uint32_t len);\r
+\r
+/**\r
+ * \brief Set The four 32-bit Hash Word registers expose the intermediate GHASH\r
+ * value. May be read to save the current GHASH value so processing can later be\r
+ * resumed, presumably on a later message fragment.\r
+ * Modes of operation as an additional initial input.\r
+ * \param hash Pointer to the word of the hash.\r
+ */\r
+void aes_set_gcm_hash(uint32_t * hash);\r
+\r
+/**\r
+ * \brief Get The four 32-bit Tag which contain the final 128-bit GCM\r
+ * Authentication tag 'T' when GCM processing is complete.\r
+ * \param tag Pointer to the word of the tag.\r
+ */\r
+void aes_get_gcm_tag(uint32_t * tag);\r
+\r
+/**\r
+ * \brief Reports the current value of the 32-bit GCM counter.\r
+ * \param counter Pointer to value of GCM counter.\r
+ */\r
+void aes_get_gcm_counter(uint32_t * counter);\r
+\r
+/**\r
+ * \brief Get the four 32-bit data containing the 128-bit H value computed from\r
+ * the KEYW value.\r
+ * \param h Pointer to the word that has been encrypted/decrypted.\r
+ */\r
+void aes_get_gcm_hash_subkey(uint32_t * h);\r
+\r
+#endif /* #ifndef _AES_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup aic_module\r
+ *\r
+ * \section Purpose\r
+ * The Advanced Interrupt Controller (AIC) is an 8-level priority, individually\r
+ * maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources.\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Each interrupt source can be enabled or disabled by using the aic_enable() and aic_disable()</li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the AIC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref aic.c\n\r
+ * \ref aic.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+* \file\r
+*\r
+* Implementation of Advanced Interrupt Controller (AIC) controller.\r
+*\r
+*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/aic.h"\r
+#include "peripherals/matrix.h"\r
+#include "cortex-a/cp15.h"\r
+#include "cortex-a/cp15_pmu.h"\r
+#include "cortex-a/cpsr.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Default interrupt handler.\r
+ */\r
+static void _aic_default_irq_handler(void)\r
+{\r
+ while (1);\r
+}\r
+\r
+/**\r
+ * \brief Interrupt Init.\r
+ */\r
+static void _aic_initialize(Aic* aic)\r
+{\r
+ uint32_t i;\r
+\r
+ /* Disable all interrupts */\r
+ for (i = 1; i < ID_PERIPH_COUNT; i++)\r
+ {\r
+ aic->AIC_SSR = i;\r
+ aic->AIC_IDCR = AIC_IDCR_INTD;\r
+ }\r
+\r
+ /* Clear All pending interrupts flags */\r
+ for (i = 0; i < ID_PERIPH_COUNT; i++)\r
+ {\r
+ aic->AIC_SSR = i;\r
+ aic->AIC_ICCR = AIC_ICCR_INTCLR;\r
+ }\r
+\r
+ /* Perform 8 IT acknowledge (write any value in EOICR) (VPy) */\r
+ for (i = 0; i < 8; i++)\r
+ aic->AIC_EOICR = 0;\r
+\r
+ /* Assign default handler */\r
+ for (i = 0; i < ID_PERIPH_COUNT; i++)\r
+ {\r
+ aic->AIC_SSR = i;\r
+ aic->AIC_SVR = (uint32_t)_aic_default_irq_handler;\r
+ }\r
+ aic->AIC_SPU = (uint32_t)_aic_default_irq_handler;\r
+}\r
+\r
+/**\r
+ * \brief Configures an interrupt in the AIC. The interrupt is identified by its\r
+ * source (ID_xxx) and is configured to use the specified mode and\r
+ * interrupt handler function. Mode is the value that will be put in AIC_SMRx\r
+ * and the function address will be set in AIC_SVRx.\r
+ * The interrupt is disabled before configuration, so it is useless\r
+ * to do it before calling this function. When aic_configure returns, the\r
+ * interrupt will always be disabled and cleared; it must be enabled by a\r
+ * call to aic_enable().\r
+ *\r
+ * \param source Interrupt source to configure.\r
+ * \param mode Triggering mode and priority of the interrupt.\r
+ * \param handler Interrupt handler function.\r
+ */\r
+\r
+static void _aic_configure_it(uint32_t source, uint8_t mode)\r
+{\r
+ AIC->AIC_SSR = source;\r
+ /* Disable the interrupt first */\r
+ AIC->AIC_IDCR = AIC_IDCR_INTD;\r
+ /* Configure mode and handler */\r
+ AIC->AIC_SMR = mode;\r
+ /* Clear interrupt */\r
+ AIC->AIC_ICCR = AIC_ICCR_INTCLR;\r
+}\r
+\r
+/**\r
+ * \brief Enables interrupts coming from the given AIC and (unique) source (ID_xxx).\r
+ *\r
+ * \param aic AIC instance.\r
+ * \param source Interrupt source to enable.\r
+ */\r
+static void _aic_enable_it(Aic * aic, uint32_t source)\r
+{\r
+ aic->AIC_SSR = AIC_SSR_INTSEL(source);\r
+ aic->AIC_IECR = AIC_IECR_INTEN;\r
+}\r
+\r
+/**\r
+ * \brief Disables interrupts coming from the given AIC and (unique) source (ID_xxx).\r
+ *\r
+ * \param aic AIC instance.\r
+ * \param source Interrupt source to disable.\r
+ */\r
+static void _aic_disable_it(Aic * aic, uint32_t source)\r
+{\r
+ aic->AIC_SSR = AIC_SSR_INTSEL(source);\r
+ aic->AIC_IDCR = AIC_IDCR_INTD;\r
+}\r
+\r
+/**\r
+ * \brief Configure corresponding handler for the interrupts coming from the given (unique) source (ID_xxx).\r
+ *\r
+ * \param aic AIC instance.\r
+ * \param source Interrupt source to configure.\r
+ * \param handler handler for the interrupt.\r
+ */\r
+static void _aic_set_source_vector(Aic * aic, uint32_t source, void (*handler)(void))\r
+{\r
+ if (aic->AIC_WPMR & AIC_WPMR_WPEN) {\r
+ aic_write_protection(aic, 1);\r
+ }\r
+ aic->AIC_SSR = AIC_SSR_INTSEL(source);\r
+ aic->AIC_SVR = (uint32_t)handler;\r
+}\r
+\r
+/**\r
+ * \brief Configure the spurious interrupt handler\r
+ *\r
+ * \param aic AIC instance.\r
+ * \param handler handler for the interrupt.\r
+ */\r
+static void _aic_set_spurious_vector(Aic * aic, void (*handler)(void))\r
+{\r
+ if (aic->AIC_WPMR & AIC_WPMR_WPEN) {\r
+ aic_write_protection(aic, 1);\r
+ }\r
+ aic->AIC_SPU = (uint32_t)handler;\r
+}\r
+\r
+/**\r
+ * \brief Clears interrupts coming from the given AIC and (unique) source (ID_xxx).\r
+ *\r
+ * \param aic AIC instance.\r
+ * \param source Interrupt source to disable.\r
+ */\r
+static void _aic_clear_it(Aic * aic, uint32_t source)\r
+{\r
+ aic->AIC_SSR = AIC_SSR_INTSEL(source);\r
+ aic->AIC_ICCR = AIC_ICCR_INTCLR;\r
+}\r
+\r
+/**\r
+ * \brief Sets interrupts coming from the given AIC and (unique) source (ID_xxx).\r
+ *\r
+ * \param aic AIC instance.\r
+ * \param source Interrupt source to disable.\r
+ */\r
+static void _aic_set_it(Aic * aic, uint32_t source)\r
+{\r
+ aic->AIC_SSR = AIC_SSR_INTSEL(source);\r
+ aic->AIC_ISCR = AIC_ISCR_INTSET;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Set the default handler for all interrupts\r
+ */\r
+void aic_initialize(void)\r
+{\r
+ /* Disable IRQ and FIQ at core level */\r
+ v_arm_set_cpsr_bits(CPSR_MASK_IRQ | CPSR_MASK_FIQ);\r
+\r
+ /* Set default vectors */\r
+ _aic_initialize(AIC);\r
+ _aic_initialize(SAIC);\r
+\r
+ /* Redirect all interrupts to Non-secure AIC */\r
+ SFR->SFR_AICREDIR = (SFR_AICREDIR_AICREDIRKEY(AICREDIR_KEY) ^ SFR->SFR_SN1) |\r
+ SFR_AICREDIR_NSAIC;\r
+\r
+ /* Enable IRQ and FIQ at core level */\r
+ v_arm_clr_cpsr_bits(CPSR_MASK_IRQ | CPSR_MASK_FIQ);\r
+}\r
+\r
+/**\r
+ * \brief Enables interrupts coming from the given (unique) source (ID_xxx).\r
+ *\r
+ * \param source Interrupt source to enable.\r
+ */\r
+void aic_enable(uint32_t source)\r
+{\r
+ if (SFR->SFR_AICREDIR) {\r
+ _aic_enable_it(AIC, source);\r
+ return;\r
+ }\r
+\r
+ Matrix* matrix = get_peripheral_matrix(source);\r
+ if (!matrix_is_peripheral_secured(matrix, source)) {\r
+ _aic_enable_it(AIC, source);\r
+ } else {\r
+ _aic_enable_it(SAIC, source);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disables interrupts coming from the given (unique) source (ID_xxx).\r
+ *\r
+ * \param source Interrupt source to disable.\r
+ */\r
+void aic_disable(uint32_t source)\r
+{\r
+ if (SFR->SFR_AICREDIR) {\r
+ _aic_disable_it(AIC, source);\r
+ return;\r
+ }\r
+\r
+ Matrix* matrix = get_peripheral_matrix(source);\r
+ if (!matrix_is_peripheral_secured(matrix, source)) {\r
+ _aic_disable_it(AIC, source);\r
+ } else {\r
+ _aic_disable_it(SAIC, source);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure interrupts' source mode.\r
+ *\r
+ * \param source Interrupt source to configure.\r
+ * \param mode mode combined of priority level and interrupt source type.\r
+ */\r
+void aic_configure(uint32_t source, uint8_t mode)\r
+{\r
+ if (SFR->SFR_AICREDIR) {\r
+ _aic_configure_it(source, mode);\r
+ return;\r
+ }\r
+\r
+ Matrix* matrix = get_peripheral_matrix(source);\r
+ if (!matrix_is_peripheral_secured(matrix, source)) {\r
+ _aic_configure_it(source, mode);\r
+ } else {\r
+ // Does not apply for SAIC\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure corresponding handler for the interrupts coming from the given (unique) source (ID_xxx).\r
+ *\r
+ * \param source Interrupt source to configure.\r
+ * \param handler handler for the interrupt.\r
+ */\r
+void aic_set_source_vector(uint32_t source, void (*handler)(void))\r
+{\r
+ Aic *aic = AIC;\r
+\r
+ if (SFR->SFR_AICREDIR == 0) {\r
+ Matrix* matrix = get_peripheral_matrix(source);\r
+ if (matrix_is_peripheral_secured(matrix, source))\r
+ aic = SAIC;\r
+ }\r
+ _aic_set_source_vector(aic, source, handler);\r
+}\r
+\r
+/**\r
+ * \brief Configure the spurious interrupt handler\r
+ *\r
+ * \param handler handler for the interrupt.\r
+ */\r
+void aic_set_spurious_vector(void (*handler)(void))\r
+{\r
+ Aic *aic = AIC;\r
+\r
+ if (SFR->SFR_AICREDIR == 0) {\r
+ aic = SAIC;\r
+ }\r
+\r
+ _aic_set_spurious_vector(aic, handler);\r
+}\r
+\r
+/**\r
+ * \brief Configure interrupts' source mode.\r
+ *\r
+ * \param source Interrupt source to configure.\r
+ * \param mode mode combined of priority level and interrupt source type.\r
+ */\r
+void aic_set_or_clear(uint32_t source, uint8_t set)\r
+{\r
+ Aic *aic = AIC;\r
+\r
+ if (SFR->SFR_AICREDIR == 0) {\r
+ Matrix* matrix = get_peripheral_matrix(source);\r
+ if (matrix_is_peripheral_secured(matrix, source))\r
+ aic = SAIC;\r
+ }\r
+\r
+ if (set) {\r
+ _aic_set_it(aic, source);\r
+ } else {\r
+ _aic_clear_it(aic, source);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Indicate treatment completion for interrupts coming from the given AIC and (unique) source (ID_xxx).\r
+ *\r
+ * \param aic AIC instance.\r
+ */\r
+void aic_end_interrupt(Aic * aic)\r
+{\r
+ aic->AIC_EOICR = AIC_EOICR_ENDIT;\r
+}\r
+\r
+/**\r
+ * \brief Configuration of protection mode and general interrupt mask for debug.\r
+ *\r
+ * \param aic AIC instance.\r
+ * \param protect Enable/Disable protection mode.\r
+ * \param mask Enable/Disable mask IRQ and FIQ.\r
+ *\r
+ * \retval 0 - succeed. 1 - failed.\r
+ */\r
+uint32_t aic_debug_config(Aic * aic, uint8_t protect, uint8_t mask)\r
+{\r
+ uint32_t tmp;\r
+\r
+ /* return in case the "Write Protection Mode" is enabled */\r
+ if (aic->AIC_WPMR & AIC_WPMR_WPEN)\r
+ return 1;\r
+\r
+ tmp = protect ? (1 << 1) : (0 << 1);\r
+ if (mask)\r
+ tmp++;\r
+ aic->AIC_DCR = tmp;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable/Disable AIC write protection mode.\r
+ *\r
+ * \param aic AIC instance.\r
+ * \param enable Enable/Disable AIC write protection mode.\r
+ */\r
+void aic_write_protection(Aic * aic, uint32_t enable)\r
+{\r
+ if (enable) {\r
+ aic->AIC_WPMR = AIC_WPMR_WPKEY_PASSWD | AIC_WPMR_WPEN;\r
+ } else {\r
+ aic->AIC_WPMR = AIC_WPMR_WPKEY_PASSWD;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get AIC Write Protection Status.\r
+ *\r
+ * \param aic AIC instance.\r
+ * \param pViolationSource pointer to address to store the violation source\r
+ *\r
+ * \retval 0 - No violation occured. 1 - violation occured.\r
+ */\r
+uint32_t aic_violation_occured(Aic * aic, uint32_t * pViolationSource)\r
+{\r
+ if (aic->AIC_WPSR & AIC_WPSR_WPVS) {\r
+ *pViolationSource =\r
+ (aic->\r
+ AIC_WPSR & AIC_WPSR_WPVSRC_Msk) >> AIC_WPSR_WPVSRC_Pos;\r
+ }\r
+ return 0;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Methods and definitions for configuring interrupts.\r
+ *\r
+ * \section Usage\r
+ * -# Enable or disable interrupt generation of a particular source with\r
+ * IRQ_EnableIT and IRQ_DisableIT.\r
+ */\r
+\r
+#ifndef AIC_H\r
+#define AIC_H\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+typedef void(*aic_handler_t)(void);\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+extern void aic_initialize(void);\r
+extern void aic_enable(uint32_t source);\r
+extern void aic_disable(uint32_t source);\r
+extern void aic_configure(uint32_t source, uint8_t mode);\r
+extern void aic_set_source_vector(uint32_t source, void (*handler)(void));\r
+extern void aic_set_spurious_vector(void (*handler)(void));\r
+extern void aic_set_or_clear(uint32_t source, uint8_t set);\r
+extern void aic_end_interrupt(Aic * aic);\r
+extern uint32_t aic_debug_config(Aic * aic, uint8_t protect, uint8_t mask);\r
+extern void aic_write_protection(Aic * aic, uint32_t enable);\r
+extern uint32_t aic_violation_occured(Aic * aic, uint32_t * pViolationSource);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif //#ifndef AIC_H\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "board.h"\r
+#include "trace.h"\r
+\r
+#include "peripherals/classd.h"\r
+#include "peripherals/pmc.h"\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local constants\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static const struct {\r
+ uint32_t rate;\r
+ uint32_t sample_rate;\r
+ uint32_t dsp_clk;\r
+} audio_info[] = {\r
+ { 8000, CLASSD_INTPMR_FRAME_FRAME_8K, CLASSD_INTPMR_DSPCLKFREQ_12M288 },\r
+ { 16000, CLASSD_INTPMR_FRAME_FRAME_16K, CLASSD_INTPMR_DSPCLKFREQ_12M288 },\r
+ { 32000, CLASSD_INTPMR_FRAME_FRAME_32K, CLASSD_INTPMR_DSPCLKFREQ_12M288 },\r
+ { 48000, CLASSD_INTPMR_FRAME_FRAME_48K, CLASSD_INTPMR_DSPCLKFREQ_12M288 },\r
+ { 96000, CLASSD_INTPMR_FRAME_FRAME_96K, CLASSD_INTPMR_DSPCLKFREQ_12M288 },\r
+ { 22050, CLASSD_INTPMR_FRAME_FRAME_22K, CLASSD_INTPMR_DSPCLKFREQ_11M2896 },\r
+ { 44100, CLASSD_INTPMR_FRAME_FRAME_44K, CLASSD_INTPMR_DSPCLKFREQ_11M2896 },\r
+ { 88200, CLASSD_INTPMR_FRAME_FRAME_88K, CLASSD_INTPMR_DSPCLKFREQ_11M2896 },\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static bool _dspclk_configure(uint32_t dsp_clk)\r
+{\r
+ struct _pmc_audio_cfg cfg;\r
+\r
+ /* Pad Clock: not used */\r
+ cfg.div = 0;\r
+ cfg.qdaudio = 0;\r
+\r
+ /* PMC Clock: */\r
+ /* 12Mhz * (ND + 1 + FRACR/2^22) / (QDPMC + 1) = 8 * DSPCLK */\r
+ switch (dsp_clk) {\r
+ case CLASSD_INTPMR_DSPCLKFREQ_12M288:\r
+ /* 12Mhz * (56 + 1 + 1442841/2^22) / (6 + 1) = 8 * 12.288Mhz */\r
+ cfg.nd = 56;\r
+ cfg.fracr = 1442841;\r
+ cfg.qdpmc = 6;\r
+ break;\r
+ case CLASSD_INTPMR_DSPCLKFREQ_11M2896:\r
+ /* 12Mhz * (59 + 1 + 885837/2^22) / (7 + 1) = 8 * 11.2896Mhz */\r
+ cfg.nd = 59;\r
+ cfg.fracr = 885837;\r
+ cfg.qdpmc = 7;\r
+ break;\r
+ default:\r
+ return false;\r
+ }\r
+\r
+ pmc_configure_audio(&cfg);\r
+ pmc_enable_audio(true, false);\r
+\r
+#ifndef NDEBUG\r
+ {\r
+ uint32_t clk;\r
+ clk = pmc_get_audio_pmc_clock();\r
+ trace_debug("Configured Audio PLL PMC Clock: %u (= 8 * %u)\r\n",\r
+ (unsigned)clk, (unsigned)(clk >> 3));\r
+ }\r
+#endif\r
+\r
+ return true;\r
+}\r
+\r
+static bool _set_eqcfg_bits(enum _classd_eqcfg eqcfg, volatile uint32_t *intpmr)\r
+{\r
+ uint32_t mask = CLASSD_INTPMR_EQCFG_Msk;\r
+ uint32_t bits = 0;\r
+\r
+ switch (eqcfg) {\r
+ case CLASSD_EQCFG_FLAT:\r
+ bits = CLASSD_INTPMR_EQCFG_FLAT;\r
+ break;\r
+ case CLASSD_EQCFG_BBOOST12:\r
+ bits = CLASSD_INTPMR_EQCFG_BBOOST12;\r
+ break;\r
+ case CLASSD_EQCFG_BBOOST6:\r
+ bits = CLASSD_INTPMR_EQCFG_BBOOST6;\r
+ break;\r
+ case CLASSD_EQCFG_BCUT12:\r
+ bits = CLASSD_INTPMR_EQCFG_BCUT12;\r
+ break;\r
+ case CLASSD_EQCFG_BCUT6:\r
+ bits = CLASSD_INTPMR_EQCFG_BCUT6;\r
+ break;\r
+ case CLASSD_EQCFG_MBOOST3:\r
+ bits = CLASSD_INTPMR_EQCFG_MBOOST3;\r
+ break;\r
+ case CLASSD_EQCFG_MBOOST8:\r
+ bits = CLASSD_INTPMR_EQCFG_MBOOST8;\r
+ break;\r
+ case CLASSD_EQCFG_MCUT3:\r
+ bits = CLASSD_INTPMR_EQCFG_MCUT3;\r
+ break;\r
+ case CLASSD_EQCFG_MCUT8:\r
+ bits = CLASSD_INTPMR_EQCFG_MCUT8;\r
+ break;\r
+ case CLASSD_EQCFG_TBOOST12:\r
+ bits = CLASSD_INTPMR_EQCFG_TBOOST12;\r
+ break;\r
+ case CLASSD_EQCFG_TBOOST6:\r
+ bits = CLASSD_INTPMR_EQCFG_TBOOST6;\r
+ break;\r
+ case CLASSD_EQCFG_TCUT12:\r
+ bits = CLASSD_INTPMR_EQCFG_TCUT12;\r
+ break;\r
+ case CLASSD_EQCFG_TCUT6:\r
+ bits = CLASSD_INTPMR_EQCFG_TCUT6;\r
+ break;\r
+ default:\r
+ trace_warning("classd: invalid equalizer config %u\r\n",\r
+ (unsigned)eqcfg);\r
+ return false;\r
+ };\r
+\r
+ *intpmr = (*intpmr & ~mask) | bits;\r
+ return true;\r
+}\r
+\r
+static bool _set_mono_bits(bool mono, enum _classd_mono mono_mode, volatile uint32_t *intpmr)\r
+{\r
+ uint32_t mask = CLASSD_INTPMR_MONO_ENABLED | CLASSD_INTPMR_MONOMODE_Msk;\r
+ uint32_t bits = 0;\r
+\r
+ if (mono) {\r
+ bits = CLASSD_INTPMR_MONO_ENABLED;\r
+ switch (mono_mode) {\r
+ case CLASSD_MONO_MIXED:\r
+ bits |= CLASSD_INTPMR_MONOMODE_MONOMIX;\r
+ break;\r
+ case CLASSD_MONO_SAT:\r
+ bits |= CLASSD_INTPMR_MONOMODE_MONOSAT;\r
+ break;\r
+ case CLASSD_MONO_LEFT:\r
+ bits |= CLASSD_INTPMR_MONOMODE_MONOLEFT;\r
+ break;\r
+ case CLASSD_MONO_RIGHT:\r
+ bits |= CLASSD_INTPMR_MONOMODE_MONORIGHT;\r
+ break;\r
+ default:\r
+ trace_warning("classd: invalid mono mode %u\r\n",\r
+ (unsigned)mono_mode);\r
+ return false;\r
+ }\r
+ }\r
+\r
+ *intpmr = (*intpmr & ~mask) | bits;\r
+ return true;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+bool classd_configure(struct _classd_desc *desc)\r
+{\r
+ uint8_t i;\r
+ uint32_t mr, intpmr, dsp_clk_set, frame_set;\r
+\r
+ for (i = 0; i < ARRAY_SIZE(audio_info); i++) {\r
+ if (audio_info[i].rate == desc->sample_rate) {\r
+ dsp_clk_set = audio_info[i].dsp_clk;\r
+ frame_set = audio_info[i].sample_rate;\r
+ break;\r
+ }\r
+ }\r
+ if(i == ARRAY_SIZE(audio_info))\r
+ return false;\r
+\r
+ if (!_dspclk_configure(dsp_clk_set))\r
+ return false;\r
+\r
+ /* enable peripheral clock, disable audio clock for now */\r
+ pmc_enable_peripheral(ID_CLASSD);\r
+ pmc_disable_gck(ID_CLASSD);\r
+ pmc_configure_gck(ID_CLASSD, PMC_PCR_GCKCSS_AUDIO_CLK, 0);\r
+\r
+ /* perform soft reset */\r
+ CLASSD->CLASSD_CR = CLASSD_CR_SWRST;\r
+ CLASSD->CLASSD_IDR = CLASSD_IDR_DATRDY;\r
+\r
+ /* initial MR/INTPMR values */\r
+ mr = 0;\r
+ intpmr = dsp_clk_set | frame_set;\r
+\r
+ /* configure output mode */\r
+ switch (desc->mode) {\r
+ case CLASSD_OUTPUT_SINGLE_ENDED:\r
+ break;\r
+ case CLASSD_OUTPUT_DIFFERENTIAL:\r
+ mr |= CLASSD_MR_PWMTYP;\r
+ break;\r
+ case CLASSD_OUTPUT_HALF_BRIDGE:\r
+ mr |= CLASSD_MR_NON_OVERLAP;\r
+ break;\r
+ case CLASSD_OUTPUT_FULL_BRIDGE:\r
+ mr |= CLASSD_MR_PWMTYP | CLASSD_MR_NON_OVERLAP;\r
+ break;\r
+ default:\r
+ trace_warning("classd: invalid mode %u\n", (unsigned)desc->mode);\r
+ return false;\r
+ }\r
+\r
+ /* configure non-overlapping time */\r
+ if (mr & CLASSD_MR_NON_OVERLAP) {\r
+ switch (desc->non_ovr) {\r
+ case CLASSD_NONOVR_5NS:\r
+ mr |= CLASSD_MR_NOVRVAL_5NS;\r
+ break;\r
+ case CLASSD_NONOVR_10NS:\r
+ mr |= CLASSD_MR_NOVRVAL_10NS;\r
+ break;\r
+ case CLASSD_NONOVR_15NS:\r
+ mr |= CLASSD_MR_NOVRVAL_15NS;\r
+ break;\r
+ case CLASSD_NONOVR_20NS:\r
+ mr |= CLASSD_MR_NOVRVAL_20NS;\r
+ break;\r
+ default:\r
+ trace_warning("classd: invalid non overlap value %u\r\n",\r
+ (unsigned)desc->non_ovr);\r
+ return false;\r
+ }\r
+ }\r
+\r
+ /* configure mono/stereo */\r
+ if (desc->swap_channels)\r
+ intpmr |= CLASSD_INTPMR_SWAP;\r
+ if (!_set_mono_bits(desc->mono, desc->mono_mode, &intpmr))\r
+ return false;\r
+\r
+ /* configure left channel (muted, max attn) */\r
+ if (desc->left_enable)\r
+ mr |= CLASSD_MR_LEN;\r
+ mr |= CLASSD_MR_LMUTE;\r
+ intpmr |= CLASSD_INTPMR_ATTL(CLASSD_INTPMR_ATTL_Msk);\r
+\r
+ /* configure right channel (muted, max attn) */\r
+ if (desc->right_enable)\r
+ mr |= CLASSD_MR_REN;\r
+ mr |= CLASSD_MR_RMUTE;\r
+ intpmr |= CLASSD_INTPMR_ATTR(CLASSD_INTPMR_ATTL_Msk);\r
+\r
+ /* write configuration */\r
+ CLASSD->CLASSD_MR = mr;\r
+ CLASSD->CLASSD_INTPMR = intpmr;\r
+\r
+ /* enable audio clock */\r
+ pmc_enable_gck(ID_CLASSD);\r
+\r
+ return (CLASSD->CLASSD_INTSR & CLASSD_INTSR_CFGERR) == 0;\r
+}\r
+\r
+void classd_disable(void)\r
+{\r
+ pmc_disable_audio();\r
+ pmc_disable_gck(ID_CLASSD);\r
+ pmc_disable_peripheral(ID_CLASSD);\r
+}\r
+\r
+void classd_swap_channels(bool swap)\r
+{\r
+ if (swap) {\r
+ CLASSD->CLASSD_INTPMR |= CLASSD_INTPMR_SWAP;\r
+ } else {\r
+ CLASSD->CLASSD_INTPMR &= ~CLASSD_INTPMR_SWAP;\r
+ }\r
+}\r
+\r
+void classd_enable_mono(enum _classd_mono mono_mode)\r
+{\r
+ _set_mono_bits(true, mono_mode, &CLASSD->CLASSD_INTPMR);\r
+}\r
+\r
+void classd_disable_mono(void)\r
+{\r
+ _set_mono_bits(false, CLASSD_MONO_MIXED, &CLASSD->CLASSD_INTPMR);\r
+}\r
+\r
+void classd_set_equalizer(enum _classd_eqcfg eqcfg)\r
+{\r
+ _set_eqcfg_bits(eqcfg, &CLASSD->CLASSD_INTPMR);\r
+}\r
+\r
+void classd_enable_channels(bool left, bool right)\r
+{\r
+ uint32_t bits = 0;\r
+ if (left)\r
+ bits |= CLASSD_MR_LEN;\r
+ if (right)\r
+ bits |= CLASSD_MR_REN;\r
+ CLASSD->CLASSD_MR |= bits;\r
+}\r
+\r
+void classd_disable_channels(bool left, bool right)\r
+{\r
+ uint32_t bits = 0;\r
+ if (left)\r
+ bits |= CLASSD_MR_LEN;\r
+ if (right)\r
+ bits |= CLASSD_MR_REN;\r
+ CLASSD->CLASSD_MR &= ~bits;\r
+}\r
+\r
+void classd_set_left_attenuation(uint8_t attn)\r
+{\r
+ if (attn < 1 || attn > 0x3f)\r
+ return;\r
+\r
+ uint32_t intpmr = CLASSD->CLASSD_INTPMR & ~CLASSD_INTPMR_ATTL_Msk;\r
+ CLASSD->CLASSD_INTPMR = intpmr | CLASSD_INTPMR_ATTL(attn);\r
+}\r
+\r
+void classd_set_right_attenuation(uint8_t attn)\r
+{\r
+ if (attn < 1 || attn > 0x3f)\r
+ return;\r
+\r
+ uint32_t intpmr = CLASSD->CLASSD_INTPMR & ~CLASSD_INTPMR_ATTR_Msk;\r
+ CLASSD->CLASSD_INTPMR = intpmr | CLASSD_INTPMR_ATTR(attn);\r
+}\r
+\r
+void classd_volume_mute(bool left, bool right)\r
+{\r
+ uint32_t bits = 0;\r
+ if (left)\r
+ bits |= CLASSD_MR_LMUTE;\r
+ if (right)\r
+ bits |= CLASSD_MR_RMUTE;\r
+ CLASSD->CLASSD_MR |= bits;\r
+}\r
+\r
+void classd_volume_unmute(bool left, bool right)\r
+{\r
+ uint32_t bits = 0;\r
+ if (left)\r
+ bits |= CLASSD_MR_LMUTE;\r
+ if (right)\r
+ bits |= CLASSD_MR_RMUTE;\r
+ CLASSD->CLASSD_MR &= ~bits;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _CLASSD_H\r
+#define _CLASSD_H\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Includes\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Types\r
+ *---------------------------------------------------------------------------*/\r
+\r
+enum _classd_mode\r
+{\r
+ CLASSD_OUTPUT_SINGLE_ENDED,\r
+ CLASSD_OUTPUT_DIFFERENTIAL,\r
+ CLASSD_OUTPUT_HALF_BRIDGE,\r
+ CLASSD_OUTPUT_FULL_BRIDGE,\r
+};\r
+\r
+enum _classd_non_ovr\r
+{\r
+ CLASSD_NONOVR_5NS,\r
+ CLASSD_NONOVR_10NS,\r
+ CLASSD_NONOVR_15NS,\r
+ CLASSD_NONOVR_20NS,\r
+};\r
+\r
+enum _classd_eqcfg\r
+{\r
+ CLASSD_EQCFG_FLAT,\r
+ CLASSD_EQCFG_BBOOST12,\r
+ CLASSD_EQCFG_BBOOST6,\r
+ CLASSD_EQCFG_BCUT12,\r
+ CLASSD_EQCFG_BCUT6,\r
+ CLASSD_EQCFG_MBOOST3,\r
+ CLASSD_EQCFG_MBOOST8,\r
+ CLASSD_EQCFG_MCUT3,\r
+ CLASSD_EQCFG_MCUT8,\r
+ CLASSD_EQCFG_TBOOST12,\r
+ CLASSD_EQCFG_TBOOST6,\r
+ CLASSD_EQCFG_TCUT12,\r
+ CLASSD_EQCFG_TCUT6,\r
+};\r
+\r
+enum _classd_mono\r
+{\r
+ CLASSD_MONO_MIXED,\r
+ CLASSD_MONO_SAT,\r
+ CLASSD_MONO_LEFT,\r
+ CLASSD_MONO_RIGHT,\r
+};\r
+\r
+struct _classd_desc\r
+{\r
+ uint32_t sample_rate;\r
+ enum _classd_mode mode;\r
+ enum _classd_non_ovr non_ovr;\r
+ bool swap_channels;\r
+ bool mono;\r
+ enum _classd_mono mono_mode;\r
+ bool left_enable;\r
+ bool right_enable;\r
+};\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+extern bool classd_configure(struct _classd_desc *desc);\r
+\r
+extern void classd_disable(void);\r
+\r
+extern void classd_swap_channels(bool swap);\r
+\r
+extern void classd_enable_mono(enum _classd_mono mono_mode);\r
+\r
+extern void classd_disable_mono(void);\r
+\r
+extern void classd_set_equalizer(enum _classd_eqcfg eqcfg);\r
+\r
+extern void classd_enable_channels(bool left, bool right);\r
+\r
+extern void classd_disable_channels(bool left, bool right);\r
+\r
+extern void classd_set_left_attenuation(uint8_t attn);\r
+\r
+extern void classd_set_right_attenuation(uint8_t attn);\r
+\r
+extern void classd_volume_mute(bool left, bool right);\r
+\r
+extern void classd_volume_unmute(bool left, bool right);\r
+\r
+#endif /* _CLASSD_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/flexcom.h"\r
+\r
+#include "peripherals/usart.h"\r
+#include "peripherals/spi.h"\r
+#include "peripherals/twi.h"\r
+\r
+#include <assert.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Select a protocol for a FLEXCOM device\r
+ *\r
+ *\r
+ * \param flexcom Pointer to FLEXCOM peripheral to configure.\r
+ * \param protocol Protocol to use.\r
+ */\r
+void flexcom_select(Flexcom * flexcom, uint32_t protocol)\r
+{\r
+ assert(flexcom);\r
+ uint32_t current_protocol = flexcom->FLEX_MR;\r
+\r
+ usart_set_receiver_enabled(&flexcom->usart, 0u);\r
+\r
+ /* Shutdown previous protocol */\r
+ switch (current_protocol) {\r
+ case FLEX_MR_OPMODE_USART:\r
+ usart_set_receiver_enabled(&flexcom->usart, 0u);\r
+ usart_set_transmitter_enabled(&flexcom->usart, 0u);\r
+ break;\r
+ case FLEX_MR_OPMODE_SPI:\r
+ spi_disable(&flexcom->spi);\r
+ break;\r
+ case FLEX_MR_OPMODE_TWI:\r
+ twi_stop(&flexcom->twi);\r
+ default:\r
+ break;\r
+ }\r
+\r
+ assert(protocol & FLEX_MR_OPMODE_NO_COM ||\r
+ protocol & FLEX_MR_OPMODE_USART ||\r
+ FLEX_MR_OPMODE_SPI || FLEX_MR_OPMODE_TWI);\r
+\r
+ /* Activate the new mode () */\r
+ flexcom->FLEX_MR = protocol;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License \r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * This module provides several definitions and methods for using an USART\r
+ * peripheral.\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Enable the USART peripheral clock in the PMC.\r
+ * -# Enable the required USART PIOs (see pio.h).\r
+ * -# Configure the UART by calling usart_configure.\r
+ * -# Enable the transmitter and/or the receiver of the USART using\r
+ * usart_set_transmitter_enabled and usart_set_receiver_enabled.\r
+ * -# Send data through the USART using the usart_write methods.\r
+ * -# Receive data from the USART using the usart_read functions; the availability of data can be polled\r
+ * with usart_is_data_available.\r
+ * -# Disable the transmitter and/or the receiver of the USART with\r
+ * usart_set_transmitter_enabled and usart_set_receiver_enabled.\r
+ */\r
+\r
+#ifndef _FLEXCOM_\r
+#define _FLEXCOM_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+extern void flexcom_select(Flexcom * flexcom, uint32_t protocol);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* #ifndef _FLEXCOM_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "trace.h"\r
+#include "peripherals/gmac.h"\r
+#include "peripherals/pmc.h"\r
+#include <stdio.h>\r
+#include <string.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* some IP versions don't have this configuration flag and instead expect 0 */\r
+#ifndef GMAC_NCFGR_DBW_DBW32\r
+#define GMAC_NCFGR_DBW_DBW32 0\r
+#endif\r
+\r
+/* some IP versions don't have this error flag, set it to 0 to ignore it */\r
+#ifndef GMAC_TSR_UND\r
+#define GMAC_TSR_UND 0\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static bool _gmac_configure_mdc_clock(Gmac *gmac)\r
+{\r
+ uint32_t mck, clk;\r
+\r
+ mck = pmc_get_peripheral_clock(get_gmac_id_from_addr(gmac));\r
+\r
+ /* Disable RX/TX */\r
+ gmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+\r
+ /* Find divider */\r
+ if (mck <= 20000000) {\r
+ clk = GMAC_NCFGR_CLK_MCK_8; // MCK/8\r
+ } else if (mck <= 40000000) {\r
+ clk = GMAC_NCFGR_CLK_MCK_16; // MCK/16\r
+ } else if (mck <= 80000000) {\r
+ clk = GMAC_NCFGR_CLK_MCK_32; // MCK/32\r
+ } else if (mck <= 120000000) {\r
+ clk = GMAC_NCFGR_CLK_MCK_48; // MCK/48\r
+ } else if (mck <= 160000000) {\r
+ clk = GMAC_NCFGR_CLK_MCK_64; // MCK/64\r
+ } else if (mck <= 240000000) {\r
+ clk = GMAC_NCFGR_CLK_MCK_96; // MCK/96\r
+ } else {\r
+ trace_error("MCK too high, cannot configure MDC clock.\r\n");\r
+ return false;\r
+ }\r
+\r
+ /* configure MDC clock divider and enable RX/TX */\r
+ gmac->GMAC_NCFGR = (gmac->GMAC_NCFGR & ~GMAC_NCFGR_CLK_Msk) | clk;\r
+ gmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+\r
+ return true;\r
+}\r
+\r
+static bool _gmac_phy_wait_idle(Gmac* gmac, uint32_t retries)\r
+{\r
+ uint32_t count = 0;\r
+ while ((gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0) {\r
+ if (retries > 0 && count > retries) {\r
+ trace_debug("Timeout reached while waiting for PHY management logic to become idle");\r
+ return false;\r
+ }\r
+ count++;\r
+ }\r
+ return true;\r
+}\r
+\r
+static void _gmac_set_link_speed(Gmac* gmac, enum _gmac_speed speed, enum _gmac_duplex duplex)\r
+{\r
+ /* Configure duplex */\r
+ switch (duplex) {\r
+ case GMAC_DUPLEX_HALF:\r
+ gmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD;\r
+ break;\r
+ case GMAC_DUPLEX_FULL:\r
+ gmac->GMAC_NCFGR |= GMAC_NCFGR_FD;\r
+ break;\r
+ default:\r
+ trace_error("Invalid duplex value %d\r\n", duplex);\r
+ return;\r
+ }\r
+\r
+ /* Configure speed */\r
+ switch (speed) {\r
+ case GMAC_SPEED_10M:\r
+ gmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD;\r
+ break;\r
+ case GMAC_SPEED_100M:\r
+ gmac->GMAC_NCFGR |= GMAC_NCFGR_SPD;\r
+ break;\r
+ default:\r
+ trace_error("Invalid speed value %d\r\n", speed);\r
+ return;\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+bool gmac_configure(Gmac* gmac)\r
+{\r
+ pmc_enable_peripheral(get_gmac_id_from_addr(gmac));\r
+\r
+ /* Disable TX & RX and more */\r
+ gmac_set_network_control_register(gmac, 0);\r
+ gmac_set_network_config_register(gmac, GMAC_NCFGR_DBW_DBW32);\r
+\r
+ /* Disable interrupts */\r
+ gmac_disable_it(gmac, 0, ~0u);\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ gmac_disable_it(gmac, 1, ~0u);\r
+ gmac_disable_it(gmac, 2, ~0u);\r
+#endif\r
+\r
+ /* Clear statistics */\r
+ gmac_clear_statistics(gmac);\r
+\r
+ /* Clear all status bits in the receive status register. */\r
+ gmac_clear_rx_status(gmac, GMAC_RSR_RXOVR | GMAC_RSR_REC |\r
+ GMAC_RSR_BNA | GMAC_RSR_HNO);\r
+\r
+ /* Clear all status bits in the transmit status register */\r
+ gmac_clear_tx_status(gmac, GMAC_TSR_UBR | GMAC_TSR_COL |\r
+ GMAC_TSR_RLE | GMAC_TSR_TXGO | GMAC_TSR_TFC |\r
+ GMAC_TSR_TXCOMP | GMAC_TSR_UND | GMAC_TSR_HRESP);\r
+\r
+ /* Clear interrupts */\r
+ gmac_get_it_status(gmac, 0);\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ gmac_get_it_status(gmac, 1);\r
+ gmac_get_it_status(gmac, 2);\r
+#endif\r
+\r
+ return _gmac_configure_mdc_clock(gmac);\r
+}\r
+\r
+void gmac_set_network_control_register(Gmac* gmac, uint32_t ncr)\r
+{\r
+ gmac->GMAC_NCR = ncr;\r
+}\r
+\r
+uint32_t gmac_get_network_control_register(Gmac* gmac)\r
+{\r
+ return gmac->GMAC_NCR;\r
+}\r
+\r
+void gmac_set_network_config_register(Gmac* gmac, uint32_t ncfgr)\r
+{\r
+ gmac->GMAC_NCFGR = ncfgr;\r
+}\r
+\r
+uint32_t gmac_get_network_config_register(Gmac* gmac)\r
+{\r
+ return gmac->GMAC_NCFGR;\r
+}\r
+\r
+void gmac_enable_mdio(Gmac* gmac)\r
+{\r
+ /* Disable RX/TX */\r
+ gmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+\r
+ /* Enable MDIO */\r
+ gmac->GMAC_NCR |= GMAC_NCR_MPE;\r
+\r
+ /* Enable RX/TX */\r
+ gmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+}\r
+\r
+void gmac_disable_mdio(Gmac* gmac)\r
+{\r
+ /* Disable RX/TX */\r
+ gmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+\r
+ /* Disable MDIO */\r
+ gmac->GMAC_NCR &= ~GMAC_NCR_MPE;\r
+\r
+ /* Enable RX/TX */\r
+ gmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+}\r
+\r
+bool gmac_phy_read(Gmac* gmac, uint8_t phy_addr, uint8_t reg_addr, uint16_t* data,\r
+ uint32_t retries)\r
+{\r
+ /* Wait until idle */\r
+ if (!_gmac_phy_wait_idle(gmac, retries))\r
+ return false;\r
+\r
+ /* Write maintenance register */\r
+ gmac->GMAC_MAN = GMAC_MAN_CLTTO |\r
+ GMAC_MAN_OP(2) |\r
+ GMAC_MAN_WTN(2) |\r
+ GMAC_MAN_PHYA(phy_addr) |\r
+ GMAC_MAN_REGA(reg_addr);\r
+\r
+ /* Wait until idle */\r
+ if (!_gmac_phy_wait_idle(gmac, retries))\r
+ return false;\r
+\r
+ *data = (gmac->GMAC_MAN & GMAC_MAN_DATA_Msk) >> GMAC_MAN_DATA_Pos;\r
+ return true;\r
+}\r
+\r
+bool gmac_phy_write(Gmac* gmac, uint8_t phy_addr, uint8_t reg_addr, uint16_t data,\r
+ uint32_t retries)\r
+{\r
+ /* Wait until idle */\r
+ if (!_gmac_phy_wait_idle(gmac, retries))\r
+ return false;\r
+\r
+ /* Write maintenance register */\r
+ gmac->GMAC_MAN = GMAC_MAN_CLTTO |\r
+ GMAC_MAN_OP(1) |\r
+ GMAC_MAN_WTN(2) |\r
+ GMAC_MAN_PHYA(phy_addr) |\r
+ GMAC_MAN_REGA(reg_addr) |\r
+ GMAC_MAN_DATA(data);\r
+\r
+ /* Wait until idle */\r
+ return _gmac_phy_wait_idle(gmac, retries);\r
+}\r
+\r
+void gmac_enable_mii(Gmac* gmac)\r
+{\r
+ /* Disable RX/TX */\r
+ gmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+\r
+ /* Disable RMII */\r
+ gmac->GMAC_UR &= ~GMAC_UR_RMII;\r
+\r
+ /* Enable RX/TX */\r
+ gmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+}\r
+\r
+void gmac_enable_rmii(Gmac* gmac, enum _gmac_speed speed, enum _gmac_duplex duplex)\r
+{\r
+ /* Disable RX/TX */\r
+ gmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+\r
+ /* Configure speed/duplex */\r
+ _gmac_set_link_speed(gmac, speed, duplex);\r
+\r
+ /* Enable RMII */\r
+ gmac->GMAC_UR |= GMAC_UR_RMII;\r
+\r
+ /* Enable RX/TX */\r
+ gmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+}\r
+\r
+void gmac_set_link_speed(Gmac* gmac, enum _gmac_speed speed, enum _gmac_duplex duplex)\r
+{\r
+ /* Disable RX/TX */\r
+ gmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+\r
+ /* Configure speed/duplex */\r
+ _gmac_set_link_speed(gmac, speed, duplex);\r
+\r
+ /* Enable RX/TX */\r
+ gmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);\r
+}\r
+\r
+void gmac_enable_local_loopback(Gmac* gmac)\r
+{\r
+ gmac->GMAC_NCR |= GMAC_NCR_LBL;\r
+}\r
+\r
+void gmac_disable_local_loopback(Gmac* gmac)\r
+{\r
+ gmac->GMAC_NCR &= ~GMAC_NCR_LBL;\r
+}\r
+\r
+uint32_t gmac_get_tx_status(Gmac* gmac)\r
+{\r
+ return gmac->GMAC_TSR;\r
+}\r
+\r
+void gmac_clear_tx_status(Gmac* gmac, uint32_t mask)\r
+{\r
+ gmac->GMAC_TSR = mask;\r
+}\r
+\r
+uint32_t gmac_get_rx_status(Gmac* gmac)\r
+{\r
+ return gmac->GMAC_RSR;\r
+}\r
+\r
+void gmac_clear_rx_status(Gmac* gmac, uint32_t mask)\r
+{\r
+ gmac->GMAC_RSR = mask;\r
+}\r
+\r
+void gmac_receive_enable(Gmac* gmac, bool enable)\r
+{\r
+ if (enable)\r
+ gmac->GMAC_NCR |= GMAC_NCR_RXEN;\r
+ else\r
+ gmac->GMAC_NCR &= ~GMAC_NCR_RXEN;\r
+}\r
+\r
+void gmac_transmit_enable(Gmac* gmac, bool enable)\r
+{\r
+ if (enable)\r
+ gmac->GMAC_NCR |= GMAC_NCR_TXEN;\r
+ else\r
+ gmac->GMAC_NCR &= ~GMAC_NCR_TXEN;\r
+}\r
+\r
+void gmac_set_rx_desc(Gmac* gmac, uint8_t queue, struct _gmac_desc* desc)\r
+{\r
+ if (queue == 0) {\r
+ gmac->GMAC_RBQB = ((uint32_t)desc) & GMAC_RBQB_ADDR_Msk;\r
+ }\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ else if (queue <= GMAC_NUM_QUEUES) {\r
+ gmac->GMAC_RBQBAPQ[queue - 1] = ((uint32_t)desc) & GMAC_RBQBAPQ_RXBQBA_Msk;\r
+ }\r
+#endif\r
+ else {\r
+ trace_debug("Invalid queue number %d\r\n", queue);\r
+ }\r
+}\r
+\r
+struct _gmac_desc* gmac_get_rx_desc(Gmac* gmac, uint8_t queue)\r
+{\r
+ if (queue == 0) {\r
+ return (struct _gmac_desc*)(gmac->GMAC_RBQB & GMAC_RBQB_ADDR_Msk);\r
+ }\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ else if (queue <= GMAC_NUM_QUEUES) {\r
+ return (struct _gmac_desc*)(gmac->GMAC_RBQBAPQ[queue - 1] & GMAC_RBQBAPQ_RXBQBA_Msk);\r
+ }\r
+#endif\r
+ else {\r
+ trace_debug("Invalid queue number %d\r\n", queue);\r
+ return NULL;\r
+ }\r
+}\r
+\r
+void gmac_set_tx_desc(Gmac* gmac, uint8_t queue, struct _gmac_desc* desc)\r
+{\r
+ if (queue == 0) {\r
+ gmac->GMAC_TBQB = ((uint32_t)desc) & GMAC_TBQB_ADDR_Msk;\r
+ }\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ else if (queue <= GMAC_NUM_QUEUES) {\r
+ gmac->GMAC_TBQBAPQ[queue - 1] = ((uint32_t)desc) & GMAC_TBQBAPQ_TXBQBA_Msk;\r
+ }\r
+#endif\r
+ else {\r
+ trace_debug("Invalid queue number %d\r\n", queue);\r
+ }\r
+}\r
+\r
+struct _gmac_desc* gmac_get_tx_desc(Gmac* gmac, uint8_t queue)\r
+{\r
+ if (queue == 0) {\r
+ return (struct _gmac_desc*)(gmac->GMAC_TBQB & GMAC_TBQB_ADDR_Msk);\r
+ }\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ else if (queue <= GMAC_NUM_QUEUES) {\r
+ return (struct _gmac_desc*)(gmac->GMAC_TBQBAPQ[queue - 1] & GMAC_TBQBAPQ_TXBQBA_Msk);\r
+ }\r
+#endif\r
+ else {\r
+ trace_debug("Invalid queue number %d\r\n", queue);\r
+ return NULL;\r
+ }\r
+}\r
+\r
+uint32_t gmac_get_it_mask(Gmac* gmac, uint8_t queue)\r
+{\r
+ if (queue == 0) {\r
+ return gmac->GMAC_IMR;\r
+ }\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ else if (queue <= GMAC_NUM_QUEUES) {\r
+ return gmac->GMAC_IMRPQ[queue - 1];\r
+ }\r
+#endif\r
+ else {\r
+ trace_debug("Invalid queue number %d\r\n", queue);\r
+ return 0;\r
+ }\r
+}\r
+\r
+void gmac_enable_it(Gmac* gmac, uint8_t queue, uint32_t mask)\r
+{\r
+ if (queue == 0) {\r
+ gmac->GMAC_IER = mask;\r
+ }\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ else if (queue <= GMAC_NUM_QUEUES) {\r
+ gmac->GMAC_IERPQ[queue - 1] = mask;\r
+ }\r
+#endif\r
+ else {\r
+ trace_debug("Invalid queue number %d\r\n", queue);\r
+ }\r
+}\r
+\r
+void gmac_disable_it(Gmac * gmac, uint8_t queue, uint32_t mask)\r
+{\r
+ if (queue == 0) {\r
+ gmac->GMAC_IDR = mask;\r
+ }\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ else if (queue <= GMAC_NUM_QUEUES) {\r
+ gmac->GMAC_IDRPQ[queue - 1] = mask;\r
+ }\r
+#endif\r
+ else {\r
+ trace_debug("Invalid queue number %d\r\n", queue);\r
+ }\r
+}\r
+\r
+uint32_t gmac_get_it_status(Gmac* gmac, uint8_t queue)\r
+{\r
+ if (queue == 0) {\r
+ return gmac->GMAC_ISR;\r
+ }\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ else if (queue <= GMAC_NUM_QUEUES) {\r
+ return gmac->GMAC_ISRPQ[queue - 1];\r
+ }\r
+#endif\r
+ else {\r
+ trace_debug("Invalid queue number %d\r\n", queue);\r
+ return 0;\r
+ }\r
+}\r
+\r
+void gmac_set_mac_addr(Gmac* gmac, uint8_t sa_idx, uint8_t* mac)\r
+{\r
+ gmac->GMAC_SA[sa_idx].GMAC_SAB = (mac[3] << 24) |\r
+ (mac[2] << 16) | (mac[1] << 8) | mac[0];\r
+ gmac->GMAC_SA[sa_idx].GMAC_SAT = (mac[5] << 8) |\r
+ mac[4];\r
+}\r
+\r
+void gmac_set_mac_addr32(Gmac* gmac, uint8_t sa_idx,\r
+ uint32_t mac_top, uint32_t mac_bottom)\r
+{\r
+ gmac->GMAC_SA[sa_idx].GMAC_SAB = mac_bottom;\r
+ gmac->GMAC_SA[sa_idx].GMAC_SAT = mac_top;\r
+}\r
+\r
+void gmac_set_mac_addr64(Gmac* gmac, uint8_t sa_idx, uint64_t mac)\r
+{\r
+ gmac->GMAC_SA[sa_idx].GMAC_SAB = (uint32_t)(mac & 0xffffffff);\r
+ gmac->GMAC_SA[sa_idx].GMAC_SAT = (uint32_t)(mac >> 32);\r
+}\r
+\r
+void gmac_clear_statistics(Gmac* gmac)\r
+{\r
+ gmac->GMAC_NCR |= GMAC_NCR_CLRSTAT;\r
+}\r
+\r
+void gmac_increase_statistics(Gmac* gmac)\r
+{\r
+ gmac->GMAC_NCR |= GMAC_NCR_INCSTAT;\r
+}\r
+\r
+void gmac_enable_statistics_write(Gmac* gmac, bool enable)\r
+{\r
+ if (enable)\r
+ gmac->GMAC_NCR |= GMAC_NCR_WESTAT;\r
+ else\r
+ gmac->GMAC_NCR &= ~GMAC_NCR_WESTAT;\r
+}\r
+\r
+void gmac_start_transmission(Gmac * gmac)\r
+{\r
+ gmac->GMAC_NCR |= GMAC_NCR_TSTART;\r
+}\r
+\r
+void gmac_halt_transmission(Gmac * gmac)\r
+{\r
+ gmac->GMAC_NCR |= GMAC_NCR_THALT;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup gmac_module\r
+ * @{\r
+ * Provides the interface to configure and use the GMAC peripheral.\r
+ *\r
+ * \section gmac_usage Usage\r
+ * - Configure Gmac::GMAC_NCFG with gmac_configure(), some of related controls\r
+ * are also available, such as:\r
+ * - gmac_set_link_speed(): Setup GMAC working clock.\r
+ * - gmac_full_duplex_enable(): Working in full duplex or not.\r
+ * - gmac_cpy_all_enable(): Copying all valid frames (\ref GMAC_NCFG_CAF).\r
+ * - ...\r
+ * - Setup Gmac::GMAC_NCR with gmac_network_control(), more related controls\r
+ * can modify with:\r
+ * - gmac_receive_enable(): Enable/Disable Rx.\r
+ * - gmac_transmit_enable(): Enable/Disable Tx.\r
+ * - gmac_broadcast_disable(): Enable/Disable broadcast receiving.\r
+ * - ...\r
+ * - Manage GMAC interrupts with GMAC_EnableIt(), gmac_disable_it(),\r
+ * gmac_get_it_mask() and gmac_get_it_status().\r
+ * - Manage GMAC Tx/Rx status with gmac_get_tx_status(), gmac_get_rx_status()\r
+ * gmac_clear_tx_status() and gmac_clear_rx_status().\r
+ * - Manage GMAC Queue with gmac_set_tx_queue(), GMAC_GetTxQueue(),\r
+ * gmac_set_rx_queue() and GMAC_GetRxQueue(), the queue descriptor can define\r
+ * by \ref _gmac_rx_descriptor and \ref _gmac_tx_descriptor.\r
+ * - Manage PHY through GMAC is performed by\r
+ * - gmac_management_enable(): Enable/Disable PHY management.\r
+ * - gmac_phy_maintain(): Execute PHY management commands.\r
+ * - gmac_phy_data(): Return PHY management data.\r
+ * - gmac_is_idle(): Check if PHY is idle.\r
+ * - Setup GMAC parameters with following functions:\r
+ * - gmac_set_hash(): Set Hash value.\r
+ * - gmac_set_address(): Set MAC address.\r
+ * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable()\r
+ * - Switch GMAC MII/RMII mode through gmac_enable_rgmii()\r
+ *\r
+ * For more accurate information, please look at the GMAC section of the\r
+ * Datasheet.\r
+ *\r
+ * \sa \ref gmacd_module\r
+ *\r
+ * Related files:\n\r
+ * gmac.c\n\r
+ * gmac.h.\n\r
+ *\r
+ * \defgroup gmac_defines GMAC Defines\r
+ * \defgroup gmac_structs GMAC Data Structs\r
+ * \defgroup gmac_functions GMAC Functions\r
+ */\r
+/**@}*/\r
+\r
+#ifndef _GMAC_H_\r
+#define _GMAC_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Defines\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup gmac_defines\r
+ @{*/\r
+\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+#define GMAC_NUM_QUEUES 3\r
+#else\r
+#define GMAC_NUM_QUEUES 1\r
+#endif\r
+\r
+#define GMAC_MAX_FRAME_LENGTH 1536\r
+#define GMAC_MAX_JUMBO_FRAME_LENGTH 10240\r
+\r
+enum _gmac_duplex {\r
+ GMAC_DUPLEX_HALF = 0,\r
+ GMAC_DUPLEX_FULL = 1,\r
+};\r
+\r
+enum _gmac_speed {\r
+ GMAC_SPEED_10M = 0,\r
+ GMAC_SPEED_100M = 1,\r
+};\r
+\r
+/* Bits contained in struct _gmac_desc addr when used for RX*/\r
+#define GMAC_RX_ADDR_OWN (1u << 0)\r
+#define GMAC_RX_ADDR_WRAP (1u << 1)\r
+#define GMAC_RX_ADDR_MASK 0xfffffffcu\r
+\r
+/* Bits contained in struct _gmac_desc status when used for RX */\r
+#define GMAC_RX_STATUS_LENGTH_MASK 0x3fffu\r
+#define GMAC_RX_STATUS_SOF (1u << 14)\r
+#define GMAC_RX_STATUS_EOF (1u << 15)\r
+\r
+/* Bits contained in struct _gmac_desc status when used for TX */\r
+#define GMAC_TX_STATUS_LASTBUF (1u << 15)\r
+#define GMAC_TX_STATUS_WRAP (1u << 30)\r
+#define GMAC_TX_STATUS_USED (1u << 31)\r
+\r
+/**@}*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup gmac_structs\r
+ @{*/\r
+\r
+/** Transmit/Receive buffer descriptor struct */\r
+struct _gmac_desc {\r
+ uint32_t addr;\r
+ uint32_t status;\r
+};\r
+\r
+/** @}*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * TODO\r
+ */\r
+extern bool gmac_configure(Gmac *gmac);\r
+\r
+/**\r
+ * \brief Write NCR register value\r
+ */\r
+extern void gmac_set_network_control_register(Gmac * gmac, uint32_t ncr);\r
+\r
+/**\r
+ * \brief Get NCR register value\r
+ */\r
+extern uint32_t gmac_get_network_control_register(Gmac * gmac);\r
+\r
+/**\r
+ * \brief Set network configuration register\r
+ */\r
+extern void gmac_set_network_config_register(Gmac* gmac, uint32_t ncfgr);\r
+\r
+/**\r
+ * \brief Get network configuration register\r
+ */\r
+\r
+extern uint32_t gmac_get_network_config_register(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Enable MDI with PHY\r
+ * \param gmac Pointer to an Gmac instance.\r
+ */\r
+extern void gmac_enable_mdio(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Disable MDI with PHY\r
+ * \param gmac Pointer to an Gmac instance.\r
+ */\r
+extern void gmac_disable_mdio(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Execute PHY read command\r
+ */\r
+extern bool gmac_phy_read(Gmac* gmac, uint8_t phy_addr, uint8_t reg_addr,\r
+ uint16_t* data, uint32_t retries);\r
+\r
+/**\r
+ * \brief Execute PHY write command\r
+ */\r
+extern bool gmac_phy_write(Gmac* gmac, uint8_t phy_addr, uint8_t reg_addr,\r
+ uint16_t data, uint32_t retries);\r
+\r
+/**\r
+ * \brief Enable MII mode for GMAC, called once after autonegotiate\r
+ * \param gmac Pointer to an Gmac instance.\r
+ */\r
+extern void gmac_enable_mii(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Enable RMII mode for GMAC, called once after autonegotiate\r
+ * \param gmac Pointer to an Gmac instance.\r
+ * \param duplex: 1 full duplex 0 half duplex\r
+ * \param speed: 0 10M 1 100M\r
+ */\r
+extern void gmac_enable_rmii(Gmac* gmac, enum _gmac_speed speed,\r
+ enum _gmac_duplex duplex);\r
+\r
+/**\r
+ * \brief Setup the GMAC for the link : speed 100M/10M and Full/Half duplex\r
+ * \param gmac Pointer to an Gmac instance.\r
+ * \param speed Link speed, 0 for 10M, 1 for 100M\r
+ * \param fullduplex 1 for Full Duplex mode\r
+ */\r
+extern void gmac_set_link_speed(Gmac* gmac, enum _gmac_speed speed,\r
+ enum _gmac_duplex duplex);\r
+\r
+/**\r
+ * \brief Enable local loop back\r
+ * \param gmac Pointer to an Gmac instance.\r
+ */\r
+extern void gmac_enable_local_loopback(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Disable local loop back\r
+ * \param gmac Pointer to an Gmac instance.\r
+ */\r
+extern void gmac_disable_local_loopback(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Return transmit status\r
+ */\r
+extern uint32_t gmac_get_tx_status(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Clear transmit status\r
+ */\r
+extern void gmac_clear_tx_status(Gmac* gmac, uint32_t mask);\r
+\r
+/**\r
+ * \brief Return receive status\r
+ */\r
+extern uint32_t gmac_get_rx_status(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Clear receive status\r
+ */\r
+extern void gmac_clear_rx_status(Gmac* gmac, uint32_t mask);\r
+\r
+/**\r
+ * \brief Enable/Disable GMAC receive.\r
+ */\r
+extern void gmac_receive_enable(Gmac* gmac, bool enable);\r
+\r
+/**\r
+ * \brief Enable/Disable GMAC transmit.\r
+ */\r
+extern void gmac_transmit_enable(Gmac* gmac, bool enable);\r
+\r
+/**\r
+ * \brief Set RX descriptor address\r
+ */\r
+void gmac_set_rx_desc(Gmac* gmac, uint8_t queue, struct _gmac_desc* desc);\r
+\r
+/**\r
+ * \brief Get RX descriptor address\r
+ */\r
+struct _gmac_desc* gmac_get_rx_desc(Gmac* gmac, uint8_t queue);\r
+\r
+/**\r
+ * \brief Set TX descriptor address\r
+ */\r
+void gmac_set_tx_desc(Gmac* gmac, uint8_t queue, struct _gmac_desc* desc);\r
+\r
+/**\r
+ * \brief Get TX descriptor address\r
+ */\r
+struct _gmac_desc* gmac_get_tx_desc(Gmac* gmac, uint8_t queue);\r
+\r
+/**\r
+ * \brief Return interrupt mask.\r
+ */\r
+extern uint32_t gmac_get_it_mask(Gmac* gmac, uint8_t queue);\r
+\r
+/**\r
+ * \brief Enable interrupt(s).\r
+ */\r
+extern void gmac_enable_it(Gmac* gmac, uint8_t queue, uint32_t mask);\r
+\r
+/**\r
+ * \brief Disable interrupt(s).\r
+ */\r
+extern void gmac_disable_it(Gmac * gmac, uint8_t queue, uint32_t mask);\r
+\r
+/**\r
+ * \brief Return interrupt status mask.\r
+ */\r
+extern uint32_t gmac_get_it_status(Gmac* gmac, uint8_t queue);\r
+\r
+/**\r
+ * \brief Set MAC Address\r
+ */\r
+extern void gmac_set_mac_addr(Gmac* gmac, uint8_t sa_idx, uint8_t* mac);\r
+\r
+/**\r
+ * \brief Set MAC Address using two 32-bit integers\r
+ */\r
+extern void gmac_set_mac_addr32(Gmac* gmac, uint8_t sa_idx,\r
+ uint32_t mac_top, uint32_t mac_bottom);\r
+\r
+/**\r
+ * \brief Set MAC Address using a 64-bit integer\r
+ */\r
+extern void gmac_set_mac_addr64(Gmac* gmac, uint8_t sa_idx, uint64_t mac);\r
+\r
+/**\r
+ * \brief Clear all statistics registers\r
+ */\r
+extern void gmac_clear_statistics(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Increase all statistics registers\r
+ */\r
+extern void gmac_increase_statistics(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Enable/Disable statistics registers writing.\r
+ */\r
+extern void gmac_enable_statistics_write(Gmac* gmac, bool enable);\r
+\r
+/**\r
+ * \brief Start transmission\r
+ */\r
+extern void gmac_start_transmission(Gmac* gmac);\r
+\r
+/**\r
+ * \brief Halt transmission\r
+ */\r
+extern void gmac_halt_transmission(Gmac* gmac);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _GMAC_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "trace.h"\r
+#include "ring.h"\r
+\r
+#include "peripherals/aic.h"\r
+#include "peripherals/gmacd.h"\r
+#include "peripherals/gmac.h"\r
+#include "peripherals/l2cc.h"\r
+#include "peripherals/pmc.h"\r
+\r
+#include <string.h>\r
+#include <assert.h>\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+// Interrupt bits\r
+#define GMAC_INT_RX_BITS (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR)\r
+#define GMAC_INT_TX_ERR_BITS (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC)\r
+#define GMAC_INT_TX_BITS (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP)\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Types\r
+ *---------------------------------------------------------------------------*/\r
+\r
+struct _gmacd_irq_handler {\r
+ Gmac* addr;\r
+ struct _gmacd** gmacd;\r
+ uint32_t irq;\r
+ aic_handler_t handler;\r
+};\r
+\r
+/*---------------------------------------------------------------------------\r
+ * IRQ Handlers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+#if GMAC_NUM_QUEUES != 3\r
+#error This driver assumes that GMAC_NUM_QUEUES is 3\r
+#endif\r
+#endif\r
+\r
+static struct _gmacd* _gmacd0;\r
+#ifdef GMAC1\r
+static struct _gmacd* _gmacd1;\r
+#endif\r
+\r
+static void _gmacd_handler(struct _gmacd* gmacd, uint8_t queue);\r
+\r
+static void _gmacd_gmac0_irq_handler(void)\r
+{\r
+ _gmacd_handler(_gmacd0, 0);\r
+}\r
+\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+static void _gmacd_gmac0q1_irq_handler(void)\r
+{\r
+ _gmacd_handler(_gmacd0, 1);\r
+}\r
+\r
+static void _gmacd_gmac0q2_irq_handler(void)\r
+{\r
+ _gmacd_handler(_gmacd0, 2);\r
+}\r
+#endif\r
+\r
+#ifdef GMAC1\r
+static void _gmacd_gmac1_irq_handler(void)\r
+{\r
+ _gmacd_handler(_gmacd1, 0);\r
+}\r
+\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+static void _gmacd_gmac1q1_irq_handler(void)\r
+{\r
+ _gmacd_handler(_gmacd1, 1);\r
+}\r
+\r
+static void _gmacd_gmac1q2_irq_handler(void)\r
+{\r
+ _gmacd_handler(_gmacd1, 2);\r
+}\r
+#endif\r
+#endif\r
+\r
+static const struct _gmacd_irq_handler _gmacd_irq_handlers[] = {\r
+ { GMAC0, &_gmacd0, ID_GMAC0, _gmacd_gmac0_irq_handler },\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ { GMAC0, &_gmacd0, ID_GMAC0_Q1, _gmacd_gmac0q1_irq_handler },\r
+ { GMAC0, &_gmacd0, ID_GMAC0_Q2, _gmacd_gmac0q2_irq_handler },\r
+#endif\r
+#ifdef GMAC1\r
+ { GMAC1, &_gmacd1, ID_GMAC1, _gmacd_gmac1_irq_handler },\r
+#ifdef CONFIG_HAVE_GMAC_QUEUES\r
+ { GMAC1, &_gmacd1, ID_GMAC1_Q1, _gmacd_gmac1q1_irq_handler },\r
+ { GMAC1, &_gmacd1, ID_GMAC1_Q2, _gmacd_gmac1q2_irq_handler },\r
+#endif\r
+#endif\r
+};\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Dummy Buffers for unconfigured queues\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#define DUMMY_BUFFERS 2\r
+#define DUMMY_UNITSIZE 128\r
+\r
+/** TX descriptors list */\r
+ALIGNED(8) SECTION(".region_ddr_nocache")\r
+static struct _gmac_desc dummy_tx_desc[DUMMY_BUFFERS];\r
+\r
+/** RX descriptors list */\r
+ALIGNED(8) SECTION(".region_ddr_nocache")\r
+static struct _gmac_desc dummy_rx_desc[DUMMY_BUFFERS];\r
+\r
+/** Send Buffer */\r
+ALIGNED(32)\r
+static uint8_t dummy_buffer[DUMMY_BUFFERS * DUMMY_UNITSIZE];\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Local functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Disable TX & reset registers and descriptor list\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ */\r
+static void _gmacd_reset_tx(struct _gmacd* gmacd, uint8_t queue)\r
+{\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+ uint32_t addr = (uint32_t)q->tx_buffer;\r
+ uint32_t i;\r
+\r
+ /* Disable TX */\r
+ gmac_transmit_enable(gmacd->gmac, false);\r
+\r
+ /* Setup the TX descriptors */\r
+ RING_CLEAR(q->tx_head, q->tx_tail);\r
+ for (i = 0; i < q->tx_size; i++) {\r
+ q->tx_desc[i].addr = addr;\r
+ DSB();\r
+ q->tx_desc[i].status = GMAC_TX_STATUS_USED;\r
+ addr += GMAC_TX_UNITSIZE;\r
+ }\r
+ q->tx_desc[q->tx_size - 1].status |= GMAC_TX_STATUS_WRAP;\r
+\r
+ /* Transmit Buffer Queue Pointer Register */\r
+ gmac_set_tx_desc(gmacd->gmac, queue, q->tx_desc);\r
+}\r
+\r
+/**\r
+ * \brief Disable RX & reset registers and descriptor list\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ */\r
+static void _gmacd_reset_rx(struct _gmacd* gmacd, uint8_t queue)\r
+{\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+ uint32_t addr = (uint32_t)q->rx_buffer;\r
+ uint32_t i;\r
+\r
+ /* Disable RX */\r
+ gmac_receive_enable(gmacd->gmac, false);\r
+\r
+ /* Setup the RX descriptors */\r
+ q->rx_head = 0;\r
+ for (i = 0; i < q->rx_size; i++) {\r
+ q->rx_desc[i].addr = addr & GMAC_RX_ADDR_MASK;\r
+ DSB();\r
+ q->rx_desc[i].status = 0;\r
+ addr += GMAC_RX_UNITSIZE;\r
+ }\r
+ q->rx_desc[q->rx_size - 1].addr |= GMAC_RX_ADDR_WRAP;\r
+\r
+ /* Receive Buffer Queue Pointer Register */\r
+ gmac_set_rx_desc(gmacd->gmac, queue, q->rx_desc);\r
+}\r
+\r
+/**\r
+ * \brief Process successfully sent packets\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ */\r
+static void _gmacd_tx_complete_handler(struct _gmacd* gmacd, uint8_t queue)\r
+{\r
+ Gmac* gmac = gmacd->gmac;\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+ struct _gmac_desc *desc;\r
+ gmacd_callback_t callback;\r
+ uint32_t tsr;\r
+\r
+ //printf("<TX>\r\n");\r
+\r
+ /* Clear status */\r
+ tsr = gmac_get_tx_status(gmac);\r
+ gmac_clear_tx_status(gmac, tsr);\r
+\r
+ while (!RING_EMPTY(q->tx_head, q->tx_tail)) {\r
+ desc = &q->tx_desc[q->tx_tail];\r
+\r
+ /* Exit if frame has not been sent yet:\r
+ * On TX completion, the GMAC set the USED bit only into the\r
+ * very first buffer descriptor of the sent frame.\r
+ * Otherwise it updates this descriptor with status error bits.\r
+ * This is the descriptor writeback.\r
+ */\r
+ if ((desc->status & GMAC_TX_STATUS_USED) == 0)\r
+ break;\r
+\r
+ /* Process all buffers of the current transmitted frame */\r
+ while ((desc->status & GMAC_TX_STATUS_LASTBUF) == 0) {\r
+ RING_INC(q->tx_tail, q->tx_size);\r
+ desc = &q->tx_desc[q->tx_tail];\r
+ }\r
+\r
+ /* Notify upper layer that a frame has been sent */\r
+ if (q->tx_callbacks) {\r
+ callback = q->tx_callbacks[q->tx_tail];\r
+ if (callback)\r
+ callback(queue, tsr);\r
+ }\r
+\r
+ /* Go to next frame */\r
+ RING_INC(q->tx_tail, q->tx_size);\r
+ }\r
+\r
+ /* If a wakeup callback has been set, notify upper layer that it can\r
+ send more packets now */\r
+ if (q->tx_wakeup_callback) {\r
+ if (RING_SPACE(q->tx_head, q->tx_tail, q->tx_size) >=\r
+ q->tx_wakeup_threshold) {\r
+ q->tx_wakeup_callback(queue);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Reset TX queue when errors are detected\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ */\r
+static void _gmacd_tx_error_handler(struct _gmacd* gmacd, uint8_t queue)\r
+{\r
+ Gmac *gmac = gmacd->gmac;\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+ struct _gmac_desc* desc;\r
+ gmacd_callback_t callback;\r
+ uint32_t tsr;\r
+\r
+ printf("<TXERR>\r\n");\r
+\r
+ /* Clear TXEN bit into the Network Configuration Register:\r
+ * this is a workaround to recover from TX lockups that\r
+ * occur on sama5d4 gmac (r1p24f2) when using scatter-gather.\r
+ * This issue has never been seen on sama5d4 gmac (r1p31).\r
+ */\r
+ gmac_transmit_enable(gmac, false);\r
+\r
+ /* The following step should be optional since this function is called\r
+ * directly by the IRQ handler. Indeed, according to Cadence\r
+ * documentation, the transmission is halted on errors such as\r
+ * too many retries or transmit under run.\r
+ * However it would become mandatory if the call of this function\r
+ * were scheduled as a task by the IRQ handler (this is how Linux\r
+ * driver works). Then this function might compete with GMACD_Send().\r
+ *\r
+ * Setting bit 10, tx_halt, of the Network Control Register is not enough:\r
+ * We should wait for bit 3, tx_go, of the Transmit Status Register to\r
+ * be cleared at transmit completion if a frame is being transmitted.\r
+ */\r
+ gmac_halt_transmission(gmac);\r
+ while (gmac_get_tx_status(gmac) & GMAC_TSR_TXGO);\r
+\r
+ /* Treat frames in TX queue including the ones that caused the error. */\r
+ while (!RING_EMPTY(q->tx_head, q->tx_tail)) {\r
+ int tx_completed = 0;\r
+ desc = &q->tx_desc[q->tx_tail];\r
+\r
+ /* Check USED bit on the very first buffer descriptor to validate\r
+ * TX completion.\r
+ */\r
+ if (desc->status & GMAC_TX_STATUS_USED)\r
+ tx_completed = 1;\r
+\r
+ /* Go to the last buffer descriptor of the frame */\r
+ while ((desc->status & GMAC_TX_STATUS_LASTBUF) == 0) {\r
+ RING_INC(q->tx_tail, q->tx_size);\r
+ desc = &q->tx_desc[q->tx_tail];\r
+ }\r
+\r
+ /* Notify upper layer that a frame status */\r
+ // TODO: which error to notify?\r
+ if (q->tx_callbacks) {\r
+ callback = q->tx_callbacks[q->tx_tail];\r
+ if (callback)\r
+ callback(queue, tx_completed ? GMAC_TSR_TXCOMP : 0);\r
+ }\r
+\r
+ /* Go to next frame */\r
+ RING_INC(q->tx_tail, q->tx_size);\r
+ }\r
+\r
+ /* Reset TX queue */\r
+ _gmacd_reset_tx(gmacd, queue);\r
+\r
+ /* Clear status */\r
+ tsr = gmac_get_tx_status(gmac);\r
+ gmac_clear_tx_status(gmac, tsr);\r
+\r
+ /* Now we are ready to start transmission again */\r
+ gmac_transmit_enable(gmac, true);\r
+ if (q->tx_wakeup_callback)\r
+ q->tx_wakeup_callback(queue);\r
+}\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief GMAC Interrupt handler\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ */\r
+static void _gmacd_handler(struct _gmacd * gmacd, uint8_t queue)\r
+{\r
+ Gmac *gmac = gmacd->gmac;\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+ uint32_t isr;\r
+ uint32_t rsr;\r
+\r
+ /* Interrupt Status Register is cleared on read */\r
+ while ((isr = gmac_get_it_status(gmac, queue)) != 0) {\r
+ /* RX packet */\r
+ if (isr & GMAC_INT_RX_BITS) {\r
+ /* Clear status */\r
+ rsr = gmac_get_rx_status(gmac);\r
+ gmac_clear_rx_status(gmac, rsr);\r
+\r
+ /* Invoke callback */\r
+ if (q->rx_callback)\r
+ q->rx_callback(queue, rsr);\r
+ }\r
+\r
+ /* TX error */\r
+ if (isr & GMAC_INT_TX_ERR_BITS) {\r
+ _gmacd_tx_error_handler(gmacd, queue);\r
+ break;\r
+ }\r
+\r
+ /* TX packet */\r
+ if (isr & GMAC_IER_TCOMP) {\r
+ _gmacd_tx_complete_handler(gmacd, queue);\r
+ }\r
+\r
+ /* HRESP not OK */\r
+ if (isr & GMAC_IER_HRESP) {\r
+ trace_error("HRESP not OK\n\r");\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Initialize the GMAC with the Gmac controller address\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ * \param gmac Pointer to HW address for registers.\r
+ * \param enableCAF Enable/Disable CopyAllFrame.\r
+ * \param enableNBC Enable/Disable NoBroadCast.\r
+ */\r
+void gmacd_configure(struct _gmacd * gmacd,\r
+ Gmac * gmac, uint8_t enableCAF, uint8_t enableNBC)\r
+{\r
+ uint32_t ncfgr;\r
+ int i;\r
+\r
+ /* Initialize struct */\r
+ gmacd->gmac = gmac;\r
+\r
+ gmac_configure(gmac);\r
+\r
+ uint32_t id = get_gmac_id_from_addr(gmac);\r
+ for (i = 0; i < ARRAY_SIZE(_gmacd_irq_handlers); i++) {\r
+ if (_gmacd_irq_handlers[i].addr == gmac) {\r
+ *_gmacd_irq_handlers[i].gmacd = gmacd;\r
+ aic_set_source_vector(_gmacd_irq_handlers[i].irq,\r
+ _gmacd_irq_handlers[i].handler);\r
+ }\r
+ }\r
+ aic_enable(id);\r
+\r
+ /* Enable the copy of data into the buffers\r
+ ignore broadcasts, and don't copy FCS. */\r
+ ncfgr = gmac_get_network_config_register(gmac);\r
+ ncfgr |= GMAC_NCFGR_FD;\r
+ if (enableCAF) {\r
+ ncfgr |= GMAC_NCFGR_CAF;\r
+ }\r
+ if (enableNBC) {\r
+ ncfgr |= GMAC_NCFGR_NBC;\r
+ }\r
+ gmac_set_network_config_register(gmac, ncfgr);\r
+\r
+ for (i = 0; i < GMAC_NUM_QUEUES; i++) {\r
+ gmacd_setup_queue(gmacd, i,\r
+ DUMMY_BUFFERS, dummy_buffer, dummy_rx_desc,\r
+ DUMMY_BUFFERS, dummy_buffer, dummy_tx_desc,\r
+ NULL);\r
+ }\r
+}\r
+\r
+/**\r
+ * Initialize necessary allocated buffer lists for GMAC Driver to transfer data.\r
+ * Must be invoked after GMACD_Init() but before RX/TX start.\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ * \param rx_buffer Pointer to allocated buffer for RX. The address should\r
+ * be 8-byte aligned and the size should be\r
+ * GMAC_RX_UNITSIZE * wRxSize.\r
+ * \param rx_desc Pointer to allocated RX descriptor list.\r
+ * \param wRxSize RX size, in number of registered units (RX descriptors).\r
+ * \param tx_buffer Pointer to allocated buffer for TX. The address should\r
+ * be 8-byte aligned and the size should be\r
+ * GMAC_TX_UNITSIZE * wTxSize.\r
+ * \param tx_desc Pointer to allocated TX descriptor list.\r
+ * \param pTxCb Pointer to allocated TX callback list.\r
+ * \param wTxSize TX size, in number of registered units (TX descriptors).\r
+ * \return GMACD_OK or GMACD_PARAM.\r
+ * \note If input address is not 8-byte aligned the address is automatically\r
+ * adjusted and the list size is reduced by one.\r
+ */\r
+\r
+\r
+uint8_t gmacd_setup_queue(struct _gmacd* gmacd, uint8_t queue,\r
+ uint16_t rx_size, uint8_t* rx_buffer, struct _gmac_desc* rx_desc,\r
+ uint16_t tx_size, uint8_t* tx_buffer, struct _gmac_desc* tx_desc,\r
+ gmacd_callback_t *tx_callbacks)\r
+{\r
+ Gmac *gmac = gmacd->gmac;\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+\r
+ if (rx_size <= 1 || tx_size <= 1)\r
+ return GMACD_PARAM;\r
+\r
+ /* Assign RX buffers */\r
+ if (((uint32_t)rx_buffer & 0x7)\r
+ || ((uint32_t)rx_desc & 0x7)) {\r
+ rx_size--;\r
+ trace_debug("RX list address adjusted\n\r");\r
+ }\r
+ q->rx_buffer = (uint8_t*)((uint32_t)rx_buffer & 0xFFFFFFF8);\r
+ q->rx_desc = (struct _gmac_desc *)((uint32_t)rx_desc & 0xFFFFFFF8);\r
+ q->rx_size = rx_size;\r
+ q->rx_callback = NULL;\r
+\r
+ /* Assign TX buffers */\r
+ if (((uint32_t)tx_buffer & 0x7)\r
+ || ((uint32_t)tx_desc & 0x7)) {\r
+ tx_size--;\r
+ trace_debug("TX list address adjusted\n\r");\r
+ }\r
+ q->tx_buffer = (uint8_t*)((uint32_t)tx_buffer & 0xFFFFFFF8);\r
+ q->tx_desc = (struct _gmac_desc*)((uint32_t)tx_desc & 0xFFFFFFF8);\r
+ q->tx_size = tx_size;\r
+ q->tx_callbacks = tx_callbacks;\r
+ q->tx_wakeup_callback = NULL;\r
+\r
+ /* Reset TX & RX */\r
+ _gmacd_reset_rx(gmacd, queue);\r
+ _gmacd_reset_tx(gmacd, queue);\r
+\r
+ /* Setup the interrupts for RX/TX completion (and errors) */\r
+ gmac_enable_it(gmac, queue, GMAC_INT_RX_BITS | GMAC_INT_TX_BITS | GMAC_IER_HRESP);\r
+\r
+ return GMACD_OK;\r
+}\r
+\r
+void gmacd_start(struct _gmacd * gmacd)\r
+{\r
+ /* Enable Rx and Tx, plus the stats register. */\r
+ gmac_transmit_enable(gmacd->gmac, true);\r
+ gmac_receive_enable(gmacd->gmac, true);\r
+ gmac_enable_statistics_write(gmacd->gmac, true);\r
+}\r
+\r
+/**\r
+ * Reset TX & RX queue & statistics\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ */\r
+void gmacd_reset(struct _gmacd* gmacd)\r
+{\r
+ int i;\r
+ for (i = 0; i < GMAC_NUM_QUEUES; i++) {\r
+ _gmacd_reset_rx(gmacd, i);\r
+ _gmacd_reset_tx(gmacd, i);\r
+ }\r
+\r
+ gmac_set_network_control_register(gmacd->gmac, GMAC_NCR_TXEN | GMAC_NCR_RXEN |\r
+ GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT);\r
+}\r
+\r
+/**\r
+ * \brief Send a frame splitted into buffers. If the frame size is larger than transfer buffer size\r
+ * error returned. If frame transfer status is monitored, specify callback for each frame.\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ * \param sgl Pointer to a scatter-gather list describing the buffers of the ethernet frame.\r
+ * \param fTxCb Pointer to callback function.\r
+ */\r
+uint8_t gmacd_send_sg(struct _gmacd* gmacd, uint8_t queue,\r
+ const struct _gmac_sg_list* sgl, gmacd_callback_t callback)\r
+{\r
+ Gmac* gmac = gmacd->gmac;\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+ struct _gmac_desc* desc;\r
+ uint16_t idx, tx_head;\r
+ int i;\r
+\r
+ if (callback && !q->tx_callbacks) {\r
+ trace_error("Cannot set send callback, no tx_callbacks "\\r
+ "buffer configured for queue %u", queue);\r
+ }\r
+\r
+ /* Check parameter */\r
+ if (!sgl->size) {\r
+ trace_error("gmacd_send_sg: ethernet frame is empty.\r\n");\r
+ return GMACD_PARAM;\r
+ }\r
+ if (sgl->size >= q->tx_size) {\r
+ trace_error("gmacd_send_sg: ethernet frame has too many buffers.\r\n");\r
+ return GMACD_PARAM;\r
+ }\r
+\r
+ /* Check available space */\r
+ if (RING_SPACE(q->tx_head, q->tx_tail, q->tx_size) < sgl->size) {\r
+ trace_error("gmacd_send_sg: not enough free buffers in TX queue.\r\n");\r
+ return GMACD_TX_BUSY;\r
+ }\r
+\r
+ /* Tag end of TX queue */\r
+ tx_head = fixed_mod(q->tx_head + sgl->size, q->tx_size);\r
+ idx = tx_head;\r
+ if (q->tx_callbacks)\r
+ q->tx_callbacks[idx] = NULL;\r
+ desc = &q->tx_desc[idx];\r
+ desc->status |= GMAC_TX_STATUS_USED;\r
+\r
+ /* Update buffer descriptors in reverse order to avoid a race\r
+ * condition with hardware.\r
+ */\r
+ for (i = sgl->size - 1; i >= 0; i--) {\r
+ const struct _gmac_sg *sg = &sgl->entries[i];\r
+ uint32_t status;\r
+\r
+ if (sg->size > GMAC_TX_UNITSIZE) {\r
+ trace_error("gmacd_send_sg: buffer size is too big.\r\n");\r
+ return GMACD_PARAM;\r
+ }\r
+\r
+ RING_DEC(idx, q->tx_size);\r
+\r
+ /* Reset TX callback */\r
+ if (q->tx_callbacks)\r
+ q->tx_callbacks[idx] = NULL;\r
+\r
+ desc = &q->tx_desc[idx];\r
+\r
+ /* Copy data into transmittion buffer */\r
+ if (sg->buffer && sg->size) {\r
+ memcpy((void*)desc->addr, sg->buffer, sg->size);\r
+ l2cc_clean_region(desc->addr, desc->addr + sg->size);\r
+ }\r
+\r
+ /* Compute buffer descriptor status word */\r
+ status = sg->size & GMAC_RX_STATUS_LENGTH_MASK;\r
+ if (i == (sgl->size - 1)) {\r
+ status |= GMAC_TX_STATUS_LASTBUF;\r
+ if (q->tx_callbacks)\r
+ q->tx_callbacks[idx] = callback;\r
+ }\r
+ if (idx == (q->tx_size - 1)) {\r
+ status |= GMAC_TX_STATUS_WRAP;\r
+ }\r
+\r
+ /* Update buffer descriptor status word: clear USED bit */\r
+ desc->status = status;\r
+ DSB();\r
+ }\r
+\r
+ /* Update TX ring buffer pointers */\r
+ q->tx_head = tx_head;\r
+\r
+ /* Now start to transmit if it is not already done */\r
+ gmac_start_transmission(gmac);\r
+\r
+ return GMACD_OK;\r
+}\r
+\r
+/**\r
+ * \brief Send a packet with GMAC. If the packet size is larger than transfer buffer size\r
+ * error returned. If packet transfer status is monitored, specify callback for each packet.\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ * \param pBuffer The buffer to be send\r
+ * \param size The size of buffer to be send\r
+ * \param fTxCb Threshold Wakeup callback\r
+ * \return OK, Busy or invalid packet\r
+ */\r
+uint8_t gmacd_send(struct _gmacd* gmacd, uint8_t queue, void *buffer,\r
+ uint32_t size, gmacd_callback_t callback)\r
+{\r
+ struct _gmac_sg sg;\r
+ struct _gmac_sg_list sgl;\r
+\r
+ /* Init single entry scatter-gather list */\r
+ sg.size = size;\r
+ sg.buffer = buffer;\r
+ sgl.size = 1;\r
+ sgl.entries = &sg;\r
+\r
+ return gmacd_send_sg(gmacd, queue, &sgl, callback);\r
+}\r
+\r
+/**\r
+ * Return current load of TX.\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ */\r
+uint32_t gmacd_get_tx_load(struct _gmacd* gmacd, uint8_t queue)\r
+{\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+ return RING_CNT(q->tx_head, q->tx_tail, q->tx_size);\r
+}\r
+\r
+/**\r
+ * \brief Receive a packet with GMAC.\r
+ * If not enough buffer for the packet, the remaining data is lost but right\r
+ * frame length is returned.\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ * \param pFrame Buffer to store the frame\r
+ * \param frameSize Size of the frame\r
+ * \param pRcvSize Received size\r
+ * \return OK, no data, or frame too small\r
+ */\r
+uint8_t gmacd_poll(struct _gmacd* gmacd, uint8_t queue,\r
+ uint8_t* buffer, uint32_t buffer_size, uint32_t* recv_size)\r
+{\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+ struct _gmac_desc *desc;\r
+ uint32_t idx;\r
+ uint32_t cur_frame_size = 0;\r
+ uint8_t *cur_frame = 0;\r
+\r
+ if (!buffer)\r
+ return GMACD_PARAM;\r
+\r
+ /* Set the default return value */\r
+ *recv_size = 0;\r
+\r
+ /* Process RX descriptors */\r
+ idx = q->rx_head;\r
+ desc = &q->rx_desc[idx];\r
+ while (desc->addr & GMAC_RX_ADDR_OWN) {\r
+ /* A start of frame has been received, discard previous fragments */\r
+ if (desc->status & GMAC_RX_STATUS_SOF) {\r
+ /* Skip previous fragment */\r
+ while (idx != q->rx_head) {\r
+ desc = &q->rx_desc[q->rx_head];\r
+ desc->addr &= ~GMAC_RX_ADDR_OWN;\r
+ RING_INC(q->rx_head, q->rx_size);\r
+ }\r
+ cur_frame = buffer;\r
+ cur_frame_size = 0;\r
+ }\r
+\r
+ /* Increment the index */\r
+ RING_INC(idx, q->rx_size);\r
+\r
+ /* Copy data in the frame buffer */\r
+ if (cur_frame) {\r
+ if (idx == q->rx_head) {\r
+ trace_info("no EOF (buffers probably too small)\r\n");\r
+\r
+ do {\r
+ desc = &q->rx_desc[q->rx_head];\r
+ desc->addr &= ~GMAC_RX_ADDR_OWN;\r
+ RING_INC(q->rx_head, q->rx_size);\r
+ } while (idx != q->rx_head);\r
+ return GMACD_RX_NULL;\r
+ }\r
+\r
+ /* Copy the buffer into the application frame */\r
+ uint32_t length = GMAC_RX_UNITSIZE;\r
+ if ((cur_frame_size + length) > buffer_size) {\r
+ length = buffer_size - cur_frame_size;\r
+ }\r
+\r
+ uint32_t addr = desc->addr & GMAC_RX_ADDR_MASK;\r
+ l2cc_invalidate_region(addr, addr + length);\r
+ memcpy(cur_frame, (void*)addr, length);\r
+ cur_frame += length;\r
+ cur_frame_size += length;\r
+\r
+ /* An end of frame has been received, return the data */\r
+ if (desc->status & GMAC_RX_STATUS_EOF) {\r
+ /* Frame size from the GMAC */\r
+ *recv_size = desc->status & GMAC_RX_STATUS_LENGTH_MASK;\r
+\r
+ /* Application frame buffer is too small all\r
+ * data have not been copied */\r
+ if (cur_frame_size < *recv_size) {\r
+ return GMACD_SIZE_TOO_SMALL;\r
+ }\r
+\r
+ /* All data have been copied in the application\r
+ * frame buffer => release descriptors */\r
+ while (q->rx_head != idx) {\r
+ desc = &q->rx_desc[q->rx_head];\r
+ desc->addr &= ~GMAC_RX_ADDR_OWN;\r
+ RING_INC(q->rx_head, q->rx_size);\r
+ }\r
+\r
+ return GMACD_OK;\r
+ }\r
+ }\r
+\r
+ /* SOF has not been detected, skip the fragment */\r
+ else {\r
+ desc->addr &= ~GMAC_RX_ADDR_OWN;\r
+ q->rx_head = idx;\r
+ }\r
+\r
+ /* Process the next buffer */\r
+ desc = &q->rx_desc[idx];\r
+ }\r
+ return GMACD_RX_NULL;\r
+}\r
+\r
+/**\r
+ * \brief Registers pRxCb callback. Callback will be invoked after the next received\r
+ * frame. When GMAC_Poll() returns GMAC_RX_NO_DATA the application task call GMAC_Set_RxCb()\r
+ * to register pRxCb() callback and enters suspend state. The callback is in charge\r
+ * to resume the task once a new frame has been received. The next time GMAC_Poll()\r
+ * is called, it will be successful.\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ * \param fRxCb Pointer to callback function\r
+ * \return OK, no data, or frame too small\r
+ */\r
+\r
+void gmacd_set_rx_callback(struct _gmacd* gmacd, uint8_t queue, gmacd_callback_t callback)\r
+{\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+ if (!callback) {\r
+ gmac_disable_it(gmacd->gmac, queue, GMAC_IDR_RCOMP);\r
+ q->rx_callback = NULL;\r
+ } else {\r
+ q->rx_callback = callback;\r
+ gmac_enable_it(gmacd->gmac, queue, GMAC_IER_RCOMP);\r
+ }\r
+}\r
+\r
+/**\r
+ * Register/Clear TX wakeup callback.\r
+ *\r
+ * When GMACD_Send() returns GMACD_TX_BUSY (all TD busy) the application\r
+ * task calls GMACD_SetTxWakeupCallback() to register fWakeup() callback and\r
+ * enters suspend state. The callback is in charge to resume the task once\r
+ * several TD have been released. The next time GMACD_Send() will be called,\r
+ * it shall be successful.\r
+ *\r
+ * This function is usually invoked with NULL callback from the TX wakeup\r
+ * callback itself, to unregister. Once the callback has resumed the\r
+ * application task, there is no need to invoke the callback again.\r
+ *\r
+ * \param gmacd Pointer to GMAC Driver instance.\r
+ * \param fWakeup Wakeup callback.\r
+ * \param bThreshold Number of free TD before wakeup callback invoked.\r
+ * \return GMACD_OK, GMACD_PARAM on parameter error.\r
+ */\r
+uint8_t gmacd_set_tx_wakeup_callback(struct _gmacd* gmacd, uint8_t queue,\r
+ gmacd_wakeup_cb_t callback, uint16_t threshold)\r
+{\r
+ struct _gmacd_queue* q = &gmacd->queues[queue];\r
+ if (!callback) {\r
+ q->tx_wakeup_callback = NULL;\r
+ } else {\r
+ if (threshold <= q->tx_size) {\r
+ q->tx_wakeup_callback = callback;\r
+ q->tx_wakeup_threshold = threshold;\r
+ } else {\r
+ return GMACD_PARAM;\r
+ }\r
+ }\r
+\r
+ return GMACD_OK;\r
+}\r
+\r
+/**@}*/\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup gmacd_module\r
+ * @{\r
+ * Implement GMAC data transfer and PHY management functions.\r
+ *\r
+ * \section Usage\r
+ * -# Implement GMAC interrupt handler, which must invoke GMACD_Handler()\r
+ * to handle GMAC interrupt events.\r
+ * -# Implement struct _gmacd instance in application.\r
+ * -# Initialize the instance with GMACD_Init() and GMACD_InitTransfer(),\r
+ * so that GMAC data can be transmitted/received.\r
+ * -# Some management callbacks can be set by GMACD_SetRxCallback()\r
+ * and GMACD_SetTxWakeupCallback().\r
+ * -# Send ethernet packets using GMACD_Send(), GMACD_TxLoad() is used\r
+ * to check the free space in TX queue.\r
+ * -# Check and obtain received ethernet packets via GMACD_Poll().\r
+ *\r
+ * \sa \ref gmacb_module, \ref gmac_module\r
+ *\r
+ * Related files:\n\r
+ * \ref gmacd.c\n\r
+ * \ref gmacd.h.\n\r
+ *\r
+ * \defgroup gmacd_defines GMAC Driver Defines\r
+ * \defgroup gmacd_types GMAC Driver Types\r
+ * \defgroup gmacd_functions GMAC Driver Functions\r
+ */\r
+/**@}*/\r
+\r
+#ifndef _GMACD_H_\r
+#define _GMACD_H_\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "peripherals/gmac.h"\r
+#include <stdint.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Definitions\r
+ *---------------------------------------------------------------------------*/\r
+/** \addtogroup gmacd_defines\r
+ @{*/\r
+\r
+/** \addtogroup gmacd_buf_size GMACD Default Buffer Size\r
+ @{*/\r
+#define GMAC_RX_UNITSIZE 128 /**< RX buffer size, must be 128 */\r
+#define GMAC_TX_UNITSIZE 1536 /**< TX buffer size, must be multiple\r
+ of 32 (cache line) */\r
+/** @}*/\r
+\r
+/** \addtogroup gmacd_rc GMACD Return Codes\r
+ @{*/\r
+#define GMACD_OK 0 /**< Operation OK */\r
+#define GMACD_TX_BUSY 1 /**< TX in progress */\r
+#define GMACD_RX_NULL 1 /**< No data received */\r
+/** Buffer size not enough */\r
+#define GMACD_SIZE_TOO_SMALL 2\r
+/** Parameter error, TX packet invalid or RX size too small */\r
+#define GMACD_PARAM 3\r
+/** Transter is not initialized */\r
+#define GMACD_NOT_INITIALIZED 4\r
+/** @}*/\r
+\r
+/** @}*/\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Types\r
+ *---------------------------------------------------------------------------*/\r
+/** \addtogroup gmacd_types\r
+ @{*/\r
+\r
+/** RX/TX callback */\r
+typedef void (*gmacd_callback_t)(uint8_t queue, uint32_t status);\r
+\r
+/** TX Wakeup callback */\r
+typedef void (*gmacd_wakeup_cb_t)(uint8_t queue);\r
+\r
+/** GMAC scatter-gather entry */\r
+struct _gmac_sg {\r
+ uint32_t size;\r
+ void *buffer;\r
+ struct _gmac_sg *next;\r
+};\r
+\r
+/** GMAC scatter-gather list */\r
+struct _gmac_sg_list {\r
+ uint32_t size;\r
+ struct _gmac_sg *entries;\r
+};\r
+\r
+struct _gmacd_queue {\r
+ uint8_t *rx_buffer;\r
+ struct _gmac_desc *rx_desc;\r
+ uint16_t rx_size;\r
+ uint16_t rx_head;\r
+ gmacd_callback_t rx_callback;\r
+\r
+ uint8_t *tx_buffer;\r
+ struct _gmac_desc *tx_desc;\r
+ uint16_t tx_size;\r
+ uint16_t tx_head;\r
+ uint16_t tx_tail;\r
+ gmacd_callback_t *tx_callbacks;\r
+\r
+ gmacd_wakeup_cb_t tx_wakeup_callback;\r
+ uint16_t tx_wakeup_threshold;\r
+};\r
+\r
+/**\r
+ * GMAC driver struct.\r
+ */\r
+struct _gmacd {\r
+ Gmac* gmac; /**< GMAC instance */\r
+ struct _gmacd_queue queues[GMAC_NUM_QUEUES];\r
+};\r
+\r
+/** @}*/\r
+\r
+/** \addtogroup gmacd_functions\r
+ @{*/\r
+\r
+/*---------------------------------------------------------------------------\r
+ * GMAC Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+extern void gmacd_configure(struct _gmacd* gmacd, Gmac *pHw, uint8_t enableCAF, uint8_t enableNBC);\r
+\r
+extern uint8_t gmacd_setup_queue(struct _gmacd* gmacd, uint8_t queue,\r
+ uint16_t rx_size, uint8_t* rx_buffer, struct _gmac_desc* rx_desc,\r
+ uint16_t tx_size, uint8_t* tx_buffer, struct _gmac_desc* tx_desc,\r
+ gmacd_callback_t *tx_callbacks);\r
+\r
+extern void gmacd_start(struct _gmacd* gmacd);\r
+\r
+extern void gmacd_reset(struct _gmacd* gmacd);\r
+\r
+extern uint8_t gmacd_send_sg(struct _gmacd* gmacd, uint8_t queue,\r
+ const struct _gmac_sg_list* sgl, gmacd_callback_t callback);\r
+\r
+extern uint8_t gmacd_send(struct _gmacd* gmacd, uint8_t queue, void *buffer,\r
+ uint32_t size, gmacd_callback_t callback);\r
+\r
+extern uint32_t gmacd_get_tx_load(struct _gmacd* gmacd, uint8_t queue);\r
+\r
+extern uint8_t gmacd_poll(struct _gmacd* gmacd, uint8_t queue,\r
+ uint8_t* buffer, uint32_t buffer_size, uint32_t* recv_size);\r
+\r
+extern void gmacd_set_rx_callback(struct _gmacd *gmacd, uint8_t queue,\r
+ gmacd_callback_t callback);\r
+\r
+extern uint8_t gmacd_set_tx_wakeup_callback(struct _gmacd *gmacd,\r
+ uint8_t queue, gmacd_wakeup_cb_t wakeup_callback,\r
+ uint16_t threshold);\r
+\r
+/** @}*/\r
+\r
+#endif /* _GMACD_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of HSMC functions.\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/hsmc.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static uint32_t _nfc_read_cmd(uint32_t cmd)\r
+{\r
+ return *(volatile uint32_t*)(NFC_ADDR + cmd);\r
+}\r
+\r
+static void _nfc_write_cmd(uint32_t cmd, uint32_t value)\r
+{\r
+ *(volatile uint32_t*)(NFC_ADDR + cmd) = value;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Sets SMC timing for NAND FLASH.\r
+ * \param cs chip select.\r
+ * \param bus_width bus width 8/16.\r
+ */\r
+void hsmc_nand_configure(uint8_t cs, uint8_t bus_width)\r
+{\r
+ pmc_enable_peripheral(ID_HSMC);\r
+\r
+ HSMC->SMC_CS_NUMBER[cs].HSMC_SETUP =\r
+ HSMC_SETUP_NWE_SETUP(2) |\r
+ HSMC_SETUP_NCS_WR_SETUP(2) |\r
+ HSMC_SETUP_NRD_SETUP(2) |\r
+ HSMC_SETUP_NCS_RD_SETUP(2);\r
+\r
+ HSMC->SMC_CS_NUMBER[cs].HSMC_PULSE =\r
+ HSMC_PULSE_NWE_PULSE(7) |\r
+ HSMC_PULSE_NCS_WR_PULSE(7) |\r
+ HSMC_PULSE_NRD_PULSE(7) |\r
+ HSMC_PULSE_NCS_RD_PULSE(7);\r
+\r
+ HSMC->SMC_CS_NUMBER[cs].HSMC_CYCLE =\r
+ HSMC_CYCLE_NWE_CYCLE(13) |\r
+ HSMC_CYCLE_NRD_CYCLE(13);\r
+\r
+ HSMC->SMC_CS_NUMBER[cs].HSMC_TIMINGS =\r
+ HSMC_TIMINGS_TCLR(3) |\r
+ HSMC_TIMINGS_TADL(27) |\r
+ HSMC_TIMINGS_TAR(3) |\r
+ HSMC_TIMINGS_TRR(6) |\r
+ HSMC_TIMINGS_TWB(5) |\r
+ HSMC_TIMINGS_RBNSEL(3) |\r
+ HSMC_TIMINGS_NFSEL;\r
+\r
+ HSMC->SMC_CS_NUMBER[cs].HSMC_MODE =\r
+ HSMC_MODE_READ_MODE |\r
+ HSMC_MODE_WRITE_MODE |\r
+ ((bus_width == 8 ) ? HSMC_MODE_DBW_BIT_8 : HSMC_MODE_DBW_BIT_16) |\r
+ HSMC_MODE_TDF_CYCLES(1);\r
+}\r
+\r
+/**\r
+ * \brief Sets SMC timing for NOR FLASH.\r
+ * \param cs chip select.\r
+ * \param bus_width bus width 8/16.\r
+ */\r
+void hsmc_nor_configure(uint8_t cs, uint8_t bus_width)\r
+{\r
+ pmc_enable_peripheral(ID_HSMC);\r
+\r
+ HSMC->SMC_CS_NUMBER[cs].HSMC_SETUP =\r
+ HSMC_SETUP_NWE_SETUP(1) |\r
+ HSMC_SETUP_NCS_WR_SETUP(0) |\r
+ HSMC_SETUP_NRD_SETUP(2) |\r
+ HSMC_SETUP_NCS_RD_SETUP(0);\r
+\r
+ HSMC->SMC_CS_NUMBER[cs].HSMC_PULSE =\r
+ HSMC_PULSE_NWE_PULSE(10) |\r
+ HSMC_PULSE_NCS_WR_PULSE(10) |\r
+ HSMC_PULSE_NRD_PULSE(11) |\r
+ HSMC_PULSE_NCS_RD_PULSE(11);\r
+\r
+ HSMC->SMC_CS_NUMBER[cs].HSMC_CYCLE =\r
+ HSMC_CYCLE_NWE_CYCLE(11) |\r
+ HSMC_CYCLE_NRD_CYCLE(14);\r
+\r
+ HSMC->SMC_CS_NUMBER[cs].HSMC_TIMINGS = 0;\r
+\r
+ HSMC->SMC_CS_NUMBER[cs].HSMC_MODE =\r
+ HSMC_MODE_READ_MODE |\r
+ HSMC_MODE_WRITE_MODE |\r
+ (bus_width == 8 ? HSMC_MODE_DBW_BIT_8 : HSMC_MODE_DBW_BIT_16) |\r
+ HSMC_MODE_EXNW_MODE_DISABLED |\r
+ HSMC_MODE_TDF_CYCLES(1);\r
+}\r
+\r
+/**\r
+ * \brief Reset NFC controller.\r
+ */\r
+void hsmc_nfc_reset(void)\r
+{\r
+ /* Disable all the SMC NFC interrupts */\r
+ HSMC->HSMC_IDR = 0xFFFFFFFF;\r
+ HSMC->HSMC_CTRL = 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if spare area be read in read mode.\r
+ *\r
+ * \return Returns true if NFC controller reads both main and spare area in\r
+ * read mode, otherwise returns false.\r
+ */\r
+bool hsmc_nfc_is_spare_read_enabled(void)\r
+{\r
+ return (((HSMC->HSMC_CFG) >> 9) & 0x1) != 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if spare area be written in write mode.\r
+ *\r
+ * \return Returns true if NFC controller writes both main and spare area in\r
+ * write mode, otherwise returns false.\r
+ */\r
+bool hsmc_nfc_is_spare_write_enabled(void)\r
+{\r
+ return (((HSMC->HSMC_CFG) >> 8) & 0x1) != 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if NFC Controller is busy.\r
+ *\r
+ * \return Returns 1 if NFC Controller is activated and accesses the memory device,\r
+ * otherwise returns 0.\r
+ */\r
+bool hsmc_nfc_is_nfc_busy(void)\r
+{\r
+ return ((HSMC->HSMC_SR & HSMC_SR_NFCBUSY) == HSMC_SR_NFCBUSY);\r
+}\r
+\r
+/**\r
+ * \brief Check if the host controller is busy.\r
+ * \return Returns 1 if the host controller is busy, otherwise returns 0.\r
+ */\r
+static bool smc_nfc_is_host_busy(void)\r
+{\r
+ return (_nfc_read_cmd(NFCADDR_CMD_NFCCMD) & 0x8000000) == 0x8000000;\r
+}\r
+\r
+/**\r
+ * \brief Wait for Ready-busy pin falling and then rising.\r
+ */\r
+void hsmc_wait_rb(void)\r
+{\r
+ /* Wait for RB pin falling */\r
+ while ((HSMC->HSMC_SR & HSMC_SR_RB_FALL) != HSMC_SR_RB_FALL);\r
+\r
+ /* Wait for RB pin rising */\r
+ while ((HSMC->HSMC_SR & HSMC_SR_RB_RISE) != HSMC_SR_RB_RISE);\r
+}\r
+\r
+/**\r
+ * \brief Wait for NFC command has done.\r
+ */\r
+void hsmc_nfc_wait_cmd_done(void)\r
+{\r
+ while ((HSMC->HSMC_SR & HSMC_SR_CMDDONE) != HSMC_SR_CMDDONE);\r
+}\r
+\r
+/**\r
+ * \brief Wait for NFC Data Transfer Terminated.\r
+ */\r
+void hsmc_nfc_wait_xfr_done(void)\r
+{\r
+ while ((HSMC->HSMC_SR & HSMC_SR_XFRDONE) != HSMC_SR_XFRDONE);\r
+}\r
+\r
+/**\r
+ * \brief Wait for NFC Ready/Busy Line 3 Edge Detected.\r
+ */\r
+void hsmc_nfc_wait_rb_busy(void)\r
+{\r
+ while ((HSMC->HSMC_SR & HSMC_SR_RB_EDGE0) != HSMC_SR_RB_EDGE0);\r
+}\r
+\r
+/**\r
+ * \brief Wait for PMECC ready.\r
+ */\r
+void hsmc_pmecc_wait_ready(void)\r
+{\r
+ while((HSMC->HSMC_PMECCSR) & HSMC_PMECCSR_BUSY);\r
+}\r
+\r
+/**\r
+ * \brief Uses the HOST NANDFLASH controller to send a command to the NFC.\r
+ * \param cmd command to send.\r
+ * \param address_cycle address cycle when command access id decoded.\r
+ * \param cycle0 address at first cycle.\r
+ */\r
+void hsmc_nfc_send_cmd(uint32_t cmd, uint32_t address_cycle, uint32_t cycle0)\r
+{\r
+ /* Wait until host controller is not busy. */\r
+ while (smc_nfc_is_host_busy());\r
+\r
+ /* Send the command plus the ADDR_CYCLE */\r
+ HSMC->HSMC_ADDR = cycle0;\r
+ _nfc_write_cmd(cmd, address_cycle);\r
+ hsmc_nfc_wait_cmd_done();\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+* \file\r
+*\r
+* Definitions and function prototype for smc module\r
+*/\r
+\r
+#ifndef _HSMC_\r
+#define _HSMC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define hsmc_nfc_configure(mode) {HSMC->HSMC_CFG = mode ;}\r
+#define hsmc_nfc_enable() {HSMC->HSMC_CTRL |= HSMC_CTRL_NFCEN;}\r
+#define hsmc_nfc_disable() {HSMC->HSMC_CTRL |= HSMC_CTRL_NFCDIS;}\r
+#define hsmc_nfc_get_status() {HSMC->HSMC_SR;}\r
+\r
+#define hsmc_nfc_enable_spare_read() {HSMC->HSMC_CFG |= HSMC_CFG_RSPARE;}\r
+#define hsmc_nfc_disable_spare_read() {HSMC->HSMC_CFG &= (~HSMC_CFG_RSPARE);}\r
+#define hsmc_nfc_enable_spare_write() {HSMC->HSMC_CFG |= HSMC_CFG_WSPARE;}\r
+#define hsmc_nfc_disable_spare_write() {HSMC->HSMC_CFG &= (~HSMC_CFG_WSPARE);}\r
+\r
+#define hsmc_pmecc_reset() {HSMC->HSMC_PMECCTRL = HSMC_PMECCTRL_RST; }\r
+#define hsmc_pmecc_or_reset() {HSMC->HSMC_PMECCTRL |= HSMC_PMECCTRL_RST; }\r
+#define hsmc_pmecc_data_phase() {HSMC->HSMC_PMECCTRL |= HSMC_PMECCTRL_DATA; }\r
+#define hsmc_pmecc_enable_write() {HSMC->HSMC_PMECCFG |= HSMC_PMECCFG_NANDWR;}\r
+#define hsmc_pmecc_enable_read() {HSMC->HSMC_PMECCFG &= (~HSMC_PMECCFG_NANDWR);}\r
+ \r
+#define hsmc_pmecc_error_status() (HSMC->HSMC_PMECCISR )\r
+#define hsmc_pmecc_enable() {HSMC->HSMC_PMECCTRL = HSMC_PMECCTRL_ENABLE;}\r
+#define hsmc_pmecc_disable() {HSMC->HSMC_PMECCTRL = HSMC_PMECCTRL_DISABLE;}\r
+#define hsmc_pmecc_auto_enable() {HSMC->HSMC_PMECCFG |= HSMC_PMECCFG_AUTO;}\r
+#define hsmc_pmecc_auto_disable() {HSMC->HSMC_PMECCFG &= (~HSMC_PMECCFG_AUTO);}\r
+#define hsmc_pmecc_auto_apare_en() ((HSMC->HSMC_PMECCFG & HSMC_PMECCFG_SPAREEN) == HSMC_PMECCFG_SPAREEN) \r
+#define hsmc_pmecc(i) (HSMC->SMC_PMECC[i])\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define HSMC_SR_RB_EDGE0 (0x1u << 24)\r
+\r
+/* -------- NFCADDR_CMD : NFC Address Command -------- */\r
+\r
+#define NFCADDR_CMD_CMD1 (0xFFu << 2) /* Command Register Value for Cycle 1 */\r
+#define NFCADDR_CMD_CMD2 (0xFFu << 10) /* Command Register Value for Cycle 2 */\r
+#define NFCADDR_CMD_VCMD2 (0x1u << 18) /* Valid Cycle 2 Command */\r
+#define NFCADDR_CMD_ACYCLE (0x7u << 19) /* Number of Address required for the current command */\r
+#define NFCADDR_CMD_ACYCLE_NONE (0x0u << 19) /* No address cycle */\r
+#define NFCADDR_CMD_ACYCLE_ONE (0x1u << 19) /* One address cycle */\r
+#define NFCADDR_CMD_ACYCLE_TWO (0x2u << 19) /* Two address cycles */\r
+#define NFCADDR_CMD_ACYCLE_THREE (0x3u << 19) /* Three address cycles */\r
+#define NFCADDR_CMD_ACYCLE_FOUR (0x4u << 19) /* Four address cycles */\r
+#define NFCADDR_CMD_ACYCLE_FIVE (0x5u << 19) /* Five address cycles */\r
+#define NFCADDR_CMD_CSID (0x7u << 22) /* Chip Select Identifier */\r
+#define NFCADDR_CMD_CSID_0 (0x0u << 22) /* CS0 */\r
+#define NFCADDR_CMD_CSID_1 (0x1u << 22) /* CS1 */\r
+#define NFCADDR_CMD_CSID_2 (0x2u << 22) /* CS2 */\r
+#define NFCADDR_CMD_CSID_3 (0x3u << 22) /* CS3 */\r
+#define NFCADDR_CMD_CSID_4 (0x4u << 22) /* CS4 */\r
+#define NFCADDR_CMD_CSID_5 (0x5u << 22) /* CS5 */\r
+#define NFCADDR_CMD_CSID_6 (0x6u << 22) /* CS6 */\r
+#define NFCADDR_CMD_CSID_7 (0x7u << 22) /* CS7 */\r
+#define NFCADDR_CMD_DATAEN (0x1u << 25) /* NFC Data Enable */\r
+#define NFCADDR_CMD_DATADIS (0x0u << 25) /* NFC Data disable */\r
+#define NFCADDR_CMD_NFCRD (0x0u << 26) /* NFC Read Enable */\r
+#define NFCADDR_CMD_NFCWR (0x1u << 26) /* NFC Write Enable */\r
+#define NFCADDR_CMD_NFCCMD (0x1u << 27) /* NFC Command Enable */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void hsmc_nand_configure(uint8_t cs, uint8_t bus_width);\r
+\r
+extern void hsmc_nor_configure(uint8_t cs, uint8_t bus_width);\r
+\r
+extern void hsmc_nfc_reset(void);\r
+\r
+extern bool hsmc_nfc_is_spare_read_enabled(void);\r
+\r
+extern bool hsmc_nfc_is_spare_write_enabled(void);\r
+\r
+extern bool hsmc_nfc_is_nfc_busy(void);\r
+\r
+extern void hsmc_wait_rb(void);\r
+\r
+extern void hsmc_nfc_send_cmd(uint32_t cmd, uint32_t address_cycle, uint32_t cycle0);\r
+\r
+extern void hsmc_nfc_wait_cmd_done(void);\r
+\r
+extern void hsmc_nfc_wait_xfr_done(void);\r
+\r
+extern void hsmc_nfc_wait_rb_busy(void);\r
+\r
+extern void hsmc_nfc_wait_hamming_ready(void);\r
+\r
+extern void hsmc_pmecc_wait_ready(void);\r
+\r
+#endif /* _HSMC_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/isc.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Export functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*------------------------------------------\r
+ * ISC Control functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Send Capture Input Stream Command to start a single shot capture or a\r
+ * multiple frame.\r
+ */\r
+void isc_start_capture(void)\r
+{\r
+ ISC->ISC_CTRLEN = ISC_CTRLEN_CAPTURE;\r
+}\r
+\r
+/**\r
+ * \brief end the capture at the next Vertical Synchronization Detection.\r
+ */\r
+void isc_stop_capture(void)\r
+{\r
+ ISC->ISC_CTRLDIS = ISC_CTRLDIS_DISABLE;\r
+}\r
+\r
+/**\r
+ * \brief Returns ISC Control Status.\r
+ */\r
+uint32_t isc_get_ctrl_status(void)\r
+{\r
+ return (ISC->ISC_CTRLSR);\r
+}\r
+\r
+/**\r
+ * \brief update the color profile.\r
+ */\r
+void isc_update_profile(void)\r
+{\r
+ ISC->ISC_CTRLEN = ISC_CTRLEN_UPPRO;\r
+ while((ISC->ISC_CTRLSR & ISC_CTRLSR_UPPRO) == ISC_CTRLSR_UPPRO);\r
+}\r
+\r
+/**\r
+ * \brief Perform software reset of the interface.\r
+ */\r
+void isc_software_reset(void)\r
+{\r
+ ISC->ISC_CTRLDIS = ISC_CTRLDIS_SWRST;\r
+}\r
+\r
+/*------------------------------------------\r
+ * PFE(Parallel Front End) functions\r
+ *----------------------------------------*/\r
+\r
+/**\r
+ * \brief configure PFE(Parallel Front End) video mode.\r
+ * \param vmode: Parallel Front End Mode\r
+ */\r
+void isc_pfe_set_video_mode(uint32_t vmode)\r
+{\r
+ ISC->ISC_PFE_CFG0 &= ~ISC_PFE_CFG0_MODE_Msk;\r
+ ISC->ISC_PFE_CFG0 |= vmode;\r
+}\r
+\r
+/**\r
+ * \brief set PFE(Parallel Front End) H/V synchronization polarity.\r
+ * \param hpol: Horizontal Synchronization Polarity\r
+ * \param vpol: Vertical Synchronization Polarity\r
+ */\r
+void isc_pfe_set_sync_polarity(uint32_t hpol, uint32_t vpol)\r
+{\r
+ ISC->ISC_PFE_CFG0 &= ~ISC_PFE_CFG0_HPOL;\r
+ ISC->ISC_PFE_CFG0 &= ~ISC_PFE_CFG0_VPOL;\r
+ ISC->ISC_PFE_CFG0 |= hpol | vpol;\r
+}\r
+\r
+/**\r
+ * \brief set PFE(Parallel Front End) pixel clock polarity.\r
+ * \param ppol: pixel clock Polarity, The pixel stream is sampled on the\r
+ * rising or falling edge of the pixel clock\r
+ */\r
+void isc_pfe_set_pixel_polarity(uint32_t ppol)\r
+{\r
+ ISC->ISC_PFE_CFG0 &= ~ISC_PFE_CFG0_PPOL;\r
+ ISC->ISC_PFE_CFG0 |= ppol ;\r
+}\r
+\r
+/**\r
+ * \brief set PFE(Parallel Front End) field polarity.\r
+ * \param fpol: Top/bottom field polarity configuration.\r
+ */\r
+void isc_pfe_set_field_polarity(uint32_t fpol)\r
+{\r
+ ISC->ISC_PFE_CFG0 &= ~ISC_PFE_CFG0_FPOL;\r
+ ISC->ISC_PFE_CFG0 |= fpol ;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Enables/disable PFE(Parallel Front End) cropping\r
+ * \param enCol: Column Cropping enable/disable(1/0)\r
+ * \param enRow: Row Cropping enable/disable(1/0)\r
+ */\r
+void isc_pfe_set_cropping_enabled(uint8_t enCol, uint8_t enRow)\r
+{\r
+ ISC->ISC_PFE_CFG0 &= ~ISC_PFE_CFG0_COLEN;\r
+ ISC->ISC_PFE_CFG0 &= ~ISC_PFE_CFG0_ROWEN;\r
+ if (enCol) ISC->ISC_PFE_CFG0 |=ISC_PFE_CFG0_COLEN;\r
+ if (enRow) ISC->ISC_PFE_CFG0 |=ISC_PFE_CFG0_ROWEN;\r
+}\r
+\r
+/**\r
+ * \brief set PFE(Parallel Front End) Bits Per Sample.\r
+ * \param bps: Bits Per Sample.\r
+ */\r
+void isc_pfe_set_bps(uint32_t bps)\r
+{\r
+ ISC->ISC_PFE_CFG0 &= ~ISC_PFE_CFG0_BPS_Msk;\r
+ ISC->ISC_PFE_CFG0 |= bps ;\r
+}\r
+\r
+/**\r
+ * \brief set PFE(Parallel Front End)in single shot mode\r
+ */\r
+void isc_pfe_set_single_shot(void)\r
+{\r
+ ISC->ISC_PFE_CFG0 &= ~ISC_PFE_CFG0_CONT;\r
+}\r
+\r
+/**\r
+ * \brief set PFE(Parallel Front End)in continuous mode\r
+ */\r
+void isc_pfe_set_continuous_shot(void)\r
+{\r
+ ISC->ISC_PFE_CFG0 |= ISC_PFE_CFG0_CONT;\r
+}\r
+\r
+\r
+/**\r
+ * \brief set PFE(Parallel Front End) gated clock.\r
+ * \param en: enable/disable gated clock.\r
+ */\r
+void isc_pfe_set_gated_clock(uint8_t en)\r
+{\r
+ ISC->ISC_PFE_CFG0 &= ~ISC_PFE_CFG0_GATED;\r
+ if (en) ISC->ISC_PFE_CFG0 |= ISC_PFE_CFG0_GATED ;\r
+}\r
+/**\r
+ * \brief configure PFE(Parallel Front End) cropping area.\r
+ * \param Hstart: Horizontal starting position of the cropping area\r
+ * \param Hend: Horizontal ending position of the cropping area\r
+ * \param Vstart: Vertical starting position of the cropping area\r
+ * \param Hend: Vertical ending position of the cropping area\r
+ */\r
+void isc_pfe_set_cropping_area(\r
+ uint32_t Hstart, uint32_t Hend, uint32_t Vstart, uint32_t Vend)\r
+{\r
+ ISC->ISC_PFE_CFG1 = ISC_PFE_CFG1_COLMIN(Hstart) | ISC_PFE_CFG1_COLMAX(Hend);\r
+ ISC->ISC_PFE_CFG2 = ISC_PFE_CFG2_ROWMIN(Vstart) | ISC_PFE_CFG2_ROWMAX(Vend);\r
+}\r
+\r
+/*------------------------------------------\r
+ * Clock configuration functions\r
+ *----------------------------------------*/\r
+\r
+/**\r
+ * \brief Configure the ISP clock.\r
+ * \param ispClockDiv ISP Clock Divider.\r
+ * \param ispClockSelection ISP Clock Selection.\r
+ 0: HCLOCK is selected.\r
+ 1: GCK is selected.\r
+ */\r
+void isc_configure_isp_clock(uint32_t ispClockDiv, uint32_t ispClockSelection)\r
+{\r
+ ISC->ISC_CLKCFG |= ISC_CLKCFG_ICDIV(ispClockDiv) | (ispClockSelection << 8);\r
+}\r
+\r
+/**\r
+ * \brief Enables the ISP clock.\r
+ */\r
+void isc_enable_isp_clock(void)\r
+{\r
+ ISC->ISC_CLKEN = ISC_CLKEN_ICEN;\r
+}\r
+\r
+/**\r
+ * \brief Disables the ISP clock.\r
+ */\r
+void isc_disable_isp_clock(void)\r
+{\r
+ ISC->ISC_CLKDIS = ISC_CLKDIS_ICDIS;\r
+}\r
+\r
+/**\r
+ * \brief Software reset the ISP clock.\r
+ */\r
+void isc_reset_isp_clock(void)\r
+{\r
+ ISC->ISC_CLKDIS = ISC_CLKDIS_ICSWRST;\r
+}\r
+\r
+/**\r
+ * \brief Configure the Master clock.\r
+ * \param masterClockDiv Master Clock Divider.\r
+ * \param masterClockSelection Master Clock Selection.\r
+ 0: HCLOCK is selected.\r
+ 1: GCK is selected.\r
+ 2: 480-MHz system clock is selected.\r
+ */\r
+void isc_configure_master_clock(uint32_t masterClockDiv, uint32_t masterClockSelection)\r
+{\r
+ ISC->ISC_CLKCFG |= ISC_CLKCFG_MCDIV(masterClockDiv)\r
+ | ISC_CLKCFG_MCSEL(masterClockSelection);\r
+}\r
+\r
+/**\r
+ * \brief Enables the master clock.\r
+ */\r
+void isc_enable_master_clock(void)\r
+{\r
+ ISC->ISC_CLKEN = ISC_CLKEN_MCEN;\r
+}\r
+\r
+/**\r
+ * \brief Disables the master clock.\r
+ */\r
+void isc_disable_master_clock(void)\r
+{\r
+ ISC->ISC_CLKDIS = ISC_CLKDIS_MCDIS;\r
+}\r
+\r
+/**\r
+ * \brief Software reset the master clock.\r
+ */\r
+void isc_reset_master_clock(void)\r
+{\r
+ ISC->ISC_CLKDIS = ISC_CLKDIS_MCSWRST;\r
+}\r
+\r
+/**\r
+ * \brief Returns ISC clock Status.\r
+ */\r
+uint32_t isc_get_clock_status(void)\r
+{\r
+ return (ISC->ISC_CLKSR);\r
+}\r
+\r
+/*------------------------------------------\r
+ * Interrupt functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Enable ISC interrupt\r
+ * \param flag of interrupt to enable\r
+ */\r
+void isc_enable_interrupt(uint32_t flag)\r
+{\r
+ ISC->ISC_INTEN = flag;\r
+}\r
+\r
+/**\r
+ * \brief Disable ISC interrupt\r
+ * \param flag of interrupt to disable\r
+ */\r
+void isc_disable_interrupt(uint32_t flag)\r
+{\r
+ ISC->ISC_INTDIS = flag;\r
+}\r
+\r
+/**\r
+ * \brief Return ISC status register\r
+ * \return Status of ISC register\r
+ */\r
+uint32_t isc_interrupt_status(void)\r
+{\r
+ return(ISC->ISC_INTSR);\r
+}\r
+\r
+\r
+/*------------------------------------------\r
+ * White Balance functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Enables/disable White Balance.\r
+ */\r
+void isc_wb_enabled(uint8_t enabled)\r
+{\r
+ if (enabled)\r
+ ISC->ISC_WB_CTRL = ISC_WB_CTRL_ENABLE;\r
+ else\r
+ ISC->ISC_WB_CTRL = 0;\r
+}\r
+\r
+/**\r
+ * \brief White Balance Bayer Configuration (Pixel Color Pattern).\r
+ */\r
+void isc_wb_set_bayer_pattern(uint8_t pattern)\r
+{\r
+ ISC->ISC_WB_CFG = pattern;\r
+}\r
+\r
+/**\r
+ * \brief adjust White Balance with color component.\r
+ * \param rOffset Offset Red Component (signed 13 bits 1:12:0)\r
+ * \param grOffset Offset Green Component for Red Row (signed 13 bits 1:12:0)\r
+ * \param bOffset Offset Blue Component (signed 13 bits, 1:12:0)\r
+ * \param gbOffset Offset Green Component for Blue Row (signed 13 bits, 1:12:0)\r
+ * \param rGain Red Component Gain (unsigned 13 bits, 0:4:9)\r
+ * \param grGain Green Component (Red row) Gain (unsigned 13 bits, 0:4:9)\r
+ * \param bGain Blue Component Gain (unsigned 13 bits, 0:4:9)\r
+ * \param gbGain Green Component (Blue row) Gain (unsigned 13 bits, 0:4:9)\r
+ */\r
+void isc_wb_adjust_bayer_color(uint32_t rOffset, uint32_t grOffset,\r
+ uint32_t bOffset, uint32_t gbOffset,\r
+ uint32_t rGain, uint32_t grGain,\r
+ uint32_t bGain, uint32_t gbGain)\r
+{\r
+ ISC->ISC_WB_O_RGR =\r
+ ISC_WB_O_RGR_ROFST(rOffset) | ISC_WB_O_RGR_GROFST(grOffset);\r
+ ISC->ISC_WB_O_BGB =\r
+ ISC_WB_O_BGB_BOFST(bOffset) | ISC_WB_O_BGB_GBOFST(gbOffset);\r
+ ISC->ISC_WB_G_RGR =\r
+ ISC_WB_G_RGR_RGAIN(rGain) | ISC_WB_G_RGR_GRGAIN(grGain);\r
+ ISC->ISC_WB_G_BGB =\r
+ ISC_WB_G_BGB_BGAIN(bGain) | ISC_WB_G_BGB_GBGAIN(gbGain);\r
+}\r
+\r
+/*------------------------------------------\r
+ * Color Filter Array functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Enables/disable Color Filter Array Interpolation.\r
+ */\r
+void isc_cfa_enabled(uint8_t enabled)\r
+{\r
+ if (enabled)\r
+ ISC->ISC_CFA_CTRL = ISC_CFA_CTRL_ENABLE;\r
+ else\r
+ ISC->ISC_CFA_CTRL = 0;\r
+}\r
+\r
+/**\r
+ * \brief configure color filter array interpolation.\r
+ * \param pattern Color Filter Array Pattern\r
+ * \param edge Edge Interpolation\r
+ 0: Edges are not interpolated.\r
+ 1: Edge interpolation is performed.\r
+ */\r
+void isc_cfa_configure(uint8_t pattern, uint8_t edge)\r
+{\r
+ ISC->ISC_CFA_CFG = pattern | (edge << 4);\r
+}\r
+\r
+/*------------------------------------------\r
+ * Color Correction functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Enables/disable Color Correction.\r
+ */\r
+void isc_cc_enabled(uint8_t enabled)\r
+{\r
+ if (enabled)\r
+ ISC->ISC_CC_CTRL = ISC_CC_CTRL_ENABLE;\r
+ else\r
+ ISC->ISC_CFA_CTRL = 0;\r
+}\r
+\r
+/**\r
+ * \brief Color correction with color component.\r
+ * \param cc Pointer to structure _color_correct\r
+ */\r
+void isc_cc_configure(struct _color_correct* cc)\r
+{\r
+ ISC->ISC_CC_RR_RG =\r
+ ISC_CC_RR_RG_RRGAIN(cc->rrGain) | ISC_CC_RR_RG_RGGAIN(cc->rgGain);\r
+ ISC->ISC_CC_RB_OR =\r
+ ISC_CC_RB_OR_RBGAIN(cc->rbGain) | ISC_CC_RB_OR_ROFST(cc->rOffset);\r
+ ISC->ISC_CC_GR_GG =\r
+ ISC_CC_GR_GG_GRGAIN(cc->grGain) | ISC_CC_GR_GG_GGGAIN(cc->ggGain);\r
+ ISC->ISC_CC_GB_OG =\r
+ ISC_CC_GB_OG_GBGAIN(cc->gbGain) | ISC_CC_GB_OG_ROFST(cc->gOffset);\r
+ ISC->ISC_CC_BR_BG =\r
+ ISC_CC_BR_BG_BRGAIN(cc->brGain) | ISC_CC_BR_BG_BGGAIN(cc->bgGain);\r
+ ISC->ISC_CC_BB_OB =\r
+ ISC_CC_BB_OB_BBGAIN(cc->bbGain) | ISC_CC_BB_OB_BOFST(cc->bOffset);\r
+}\r
+\r
+/*------------------------------------------\r
+ * Gamma Correction functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Enables/disable Gamma Correction with giving channels.\r
+ * \param enabled 1: enable, 0: disable\r
+ * \param channels ISC_GAM_CTRL_BENABLE/ISC_GAM_CTRL_GENABLE/ISC_GAM_CTRL_RENABLE\r
+ */\r
+void isc_gamma_enabled(uint8_t enabled, uint8_t channels)\r
+{\r
+ if (enabled)\r
+ ISC->ISC_GAM_CTRL |= ISC_GAM_CTRL_ENABLE | channels;\r
+ else\r
+ ISC->ISC_GAM_CTRL = 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure gamma correction with give table.\r
+ * \param rGamConstant Pointer to red Color Constant instance (64 half-word).\r
+ * \param rGamSlope Pointer to red Color Slope instance (64 half-word).\r
+ * \param gGamConstant Pointer to green Color Constant instance (64 half-word).\r
+ * \param gGamSlope Pointer to green Color Slope instance (64 half-word).\r
+ * \param bGamConstant Pointer to blue Color Constant instance (64 half-word).\r
+ * \param bGamSlope Pointer to blue Color Slope instance (64 half-word).\r
+ */\r
+void isc_gamma_configure(uint16_t* rGamConstant, uint16_t* rGamSlope,\r
+ uint16_t* gGamConstant, uint16_t* gGamSlope,\r
+ uint16_t* bGamConstant, uint16_t* bGamSlope)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i < 64 ; i++) {\r
+ ISC->ISC_GAM_BENTRY[i] =\r
+ ISC_GAM_BENTRY_BCONSTANT(bGamConstant[i])\r
+ | ISC_GAM_BENTRY_BSLOPE(bGamSlope[i]);\r
+ ISC->ISC_GAM_GENTRY[i] =\r
+ ISC_GAM_GENTRY_GCONSTANT(bGamConstant[i])\r
+ | ISC_GAM_GENTRY_GSLOPE(bGamSlope[i]);\r
+ ISC->ISC_GAM_RENTRY[i] =\r
+ ISC_GAM_RENTRY_RCONSTANT(bGamConstant[i])\r
+ | ISC_GAM_RENTRY_RSLOPE(bGamSlope[i]);\r
+ }\r
+}\r
+\r
+/*------------------------------------------\r
+ * Color Space Conversion functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Enables/disable Color Space Conversion.\r
+ */\r
+void isc_csc_enabled(uint8_t enabled)\r
+{\r
+ if (enabled)\r
+ ISC->ISC_CSC_CTRL = ISC_CSC_CTRL_ENABLE;\r
+ else\r
+ ISC->ISC_CSC_CTRL = 0;\r
+}\r
+\r
+/**\r
+ * \brief Color space convert with color space component.\r
+ * \param cs Pointer to structure _color_space\r
+ */\r
+void isc_csc_configure(struct _color_space* cs)\r
+{\r
+ ISC->ISC_CSC_YR_YG = ISC_CSC_YR_YG_YRGAIN(cs->YrGain)\r
+ | ISC_CSC_YR_YG_YGGAIN(cs->YgGain);\r
+ ISC->ISC_CSC_YB_OY = ISC_CSC_YB_OY_YBGAIN(cs->YbGain)\r
+ | ISC_CSC_YB_OY_YOFST(cs->Yoffset);\r
+ ISC->ISC_CSC_CBR_CBG = ISC_CSC_CBR_CBG_CBRGAIN(cs->cbrGain)\r
+ | ISC_CSC_CBR_CBG_CBGGAIN(cs->cbgGain);\r
+ ISC->ISC_CSC_CBB_OCB = ISC_CSC_CBB_OCB_CBBGAIN(cs->cbbGain)\r
+ | ISC_CSC_CBB_OCB_CBOFST(cs->cbOffset);\r
+ ISC->ISC_CSC_CRR_CRG = ISC_CSC_CRR_CRG_CRRGAIN(cs->crrGain)\r
+ | ISC_CSC_CRR_CRG_CRGGAIN(cs->crgGain);\r
+ ISC->ISC_CSC_CRB_OCR = ISC_CSC_CRB_OCR_CRBGAIN(cs->crbGain)\r
+ | ISC_CSC_CRB_OCR_CROFST(cs->crOffset);\r
+}\r
+\r
+/*------------------------------------------\r
+ * Contrast And Brightness functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Enables/disable contrast and brightness control.\r
+ */\r
+void isc_cbc_enabled(uint8_t enabled)\r
+{\r
+ if (enabled)\r
+ ISC->ISC_CBC_CTRL = ISC_CBC_CTRL_ENABLE;\r
+ else\r
+ ISC->ISC_CBC_CTRL = 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure Contrast and brightness with give parameter.\r
+ * \param ccir656 CCIR656 Stream Enable.\r
+ 0: Raw mode\r
+ 1: CCIR mode\r
+ * \param byteOrder CCIR656 Byte Ordering.\r
+ * \param brightness Brightness Control (signed 11 bits 1:10:0).\r
+ * \param Contrast Contrast (signed 12 bits 1:3:8).\r
+ */\r
+void isc_cbc_configure(uint8_t ccir656, uint8_t byteOrder,\r
+ uint16_t brightness, uint16_t contrast)\r
+{\r
+ if (ccir656)\r
+ ISC->ISC_CBC_CFG = ISC_CBC_CFG_CCIR | byteOrder ;\r
+ else\r
+ ISC->ISC_CBC_CFG = 0;\r
+ ISC->ISC_CBC_BRIGHT = ISC_CBC_BRIGHT_BRIGHT(brightness);\r
+ ISC->ISC_CBC_CONTRAST = ISC_CBC_CONTRAST_CONTRAST(contrast);\r
+}\r
+\r
+/*------------------------------------------\r
+ * Sub-sampling functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Enables/disable 4:4:4 to 4:2:2 Chrominance Horizontal Subsampling Filter Enable.\r
+ */\r
+void isc_sub422_enabled(uint8_t enabled)\r
+{\r
+ if (enabled)\r
+ ISC->ISC_SUB422_CTRL = ISC_SUB422_CTRL_ENABLE;\r
+ else\r
+ ISC->ISC_SUB422_CTRL = 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure Subsampling 4:4:4 to 4:2:2 with giving value.\r
+ * \param ccir656 CCIR656 Stream Enable.\r
+ 0: Raw mode\r
+ 1: CCIR mode\r
+ * \param byteOrder CCIR656 Byte Ordering.\r
+ * \param lpf Low Pass Filter Selection.\r
+ */\r
+void isc_sub422_configure(uint8_t ccir656, uint8_t byteOrder, uint8_t lpf)\r
+{\r
+ if (ccir656)\r
+ ISC->ISC_SUB422_CFG = ISC_SUB422_CFG_CCIR | byteOrder ;\r
+ else\r
+ ISC->ISC_SUB422_CFG = 0;\r
+ ISC->ISC_SUB422_CFG |= lpf;\r
+}\r
+\r
+/**\r
+ * \brief Configure 4:2:2 to 4:2:0 Vertical Subsampling Filter Enable\r
+ (Center Aligned) with giving value.\r
+ * \param enabled Subsampler enabled.\r
+ 0: disabled\r
+ 1: enabled\r
+ * \param filter Interlaced or Progressive Chrominance Filter.\r
+ 0: Progressive filter {0.5, 0.5}\r
+ 1: Field-dependent filter, top field filter is {0.75, 0.25},\r
+ bottom field filter is {0.25, 0.75}\r
+ */\r
+void isc_sub420_configure(uint8_t enabled, uint8_t filter)\r
+{\r
+ if (enabled){\r
+ ISC->ISC_SUB420_CTRL = ISC_SUB420_CTRL_ENABLE;\r
+ if (filter){\r
+ ISC->ISC_SUB420_CTRL |= ISC_SUB420_CTRL_FILTER;\r
+ }\r
+ } else {\r
+ ISC->ISC_SUB420_CTRL = 0;\r
+ }\r
+}\r
+\r
+/*------------------------------------------\r
+ * Rounding, Limiting and Packing functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Configure Rounding, Limiting and Packing Mode.\r
+ * \param rlpMode Rounding, Limiting and Packing Mode.\r
+ * \param alpha Alpha Value for Alpha-enabled RGB Mode.\r
+ */\r
+void isc_rlp_configure(uint8_t rlpMode, uint8_t alpha)\r
+{\r
+ ISC->ISC_RLP_CFG = rlpMode;\r
+ if (alpha)\r
+ ISC->ISC_RLP_CFG |= ISC_RLP_CFG_ALPHA(alpha);\r
+}\r
+\r
+/*------------------------------------------\r
+ * Histogram functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Enables/disable Histogram\r
+ */\r
+void isc_histogram_enabled(uint8_t enabled)\r
+{\r
+ if (enabled)\r
+ ISC->ISC_HIS_CTRL = ISC_HIS_CTRL_ENABLE;\r
+ else\r
+ ISC->ISC_HIS_CTRL = 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure Histogram.\r
+ * \param mode Histogram Operating Mode.\r
+ * \param baySel Bayer Color Component Selection.\r
+ * \param reset Histogram Reset After Read\r
+ 0: Reset after read mode is disabled\r
+ 1: Reset after read mode is enabled.\r
+ */\r
+void isc_histogram_configure(uint8_t mode, uint8_t baySel, uint8_t reset)\r
+{\r
+ ISC->ISC_HIS_CFG = mode | baySel;\r
+ if (reset)\r
+ ISC->ISC_HIS_CFG |= ISC_HIS_CFG_RAR;\r
+}\r
+\r
+ /**\r
+ * \brief update the histogram table.\r
+ */\r
+void isc_update_histogram_table(void)\r
+{\r
+ while((ISC->ISC_CTRLSR & ISC_CTRLSR_HISREQ) == ISC_CTRLSR_HISREQ);\r
+ ISC->ISC_CTRLEN = ISC_CTRLEN_HISREQ;\r
+}\r
+\r
+/**\r
+ * \brief clear the histogram table.\r
+ */\r
+void isc_clear_histogram_table(void)\r
+{\r
+ ISC->ISC_CTRLEN = ISC_CTRLEN_HISCLR;\r
+}\r
+\r
+/*------------------------------------------\r
+ * DMA functions\r
+ *----------------------------------------*/\r
+/**\r
+ * \brief Configure ISC DMA input mode.\r
+ * \param mode Operating Mode.\r
+ */\r
+void isc_dma_configure_input_mode(uint32_t mode)\r
+{\r
+ ISC->ISC_DCFG = mode;\r
+}\r
+\r
+/**\r
+ * \brief Configure ISC DMA with giving entry.\r
+ * \param descEntry entry of DMA descriptor VIEW.\r
+ */\r
+void isc_dma_configure_desc_entry(uint32_t desc_entry)\r
+{\r
+ ISC->ISC_DNDA = desc_entry;\r
+}\r
+\r
+/**\r
+ * \brief Enable ISC DMA with giving view.\r
+ * \param ctrl setting for DMA descriptor VIEW.\r
+ */\r
+void isc_dma_enable(uint32_t ctrl)\r
+{\r
+ ISC->ISC_DCTRL = ctrl;\r
+}\r
+\r
+/**\r
+ * \brief Configure ISC DMA start address.\r
+ * \param channel channel number.\r
+ * \param address address for giving channel.\r
+ * \param stride stride for giving channel.\r
+ */\r
+void isc_dma_adderss(uint8_t channel, uint32_t address, uint32_t stride)\r
+{\r
+ ISC->ISC_SUB0[channel].ISC_DAD = address;\r
+ ISC->ISC_SUB0[channel].ISC_DST = stride;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup isc_module\r
+ * @{\r
+ * \section isc_usage Usage\r
+ * - isc_start_capture: Send Capture Input Stream Command to start a single\r
+ * shot capture or a multiple frame\r
+ */\r
+/**@}*/\r
+\r
+#ifndef ISC_H\r
+#define ISC_H\r
+\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Type\r
+ *----------------------------------------------------------------------------*/\r
+/** color correction components structure */\r
+struct _color_correct {\r
+ /** Red Component Offset (signed 13 bits, 1:12:0) */\r
+ uint16_t rOffset;\r
+ /** Green Component Offset (signed 13 bits, 1:12:0)*/\r
+ uint16_t gOffset;\r
+ /** Green Component Offset (signed 13 bits, 1:12:0)*/\r
+ uint16_t bOffset;\r
+ /** Red Gain for Red Component (signed 12 bits, 1:3:8)*/\r
+ uint16_t rrGain;\r
+ /** Green Component (Red row) Gain (unsigned 13 bits, 0:4:9)*/\r
+ uint16_t rgGain;\r
+ /** Blue Gain for Red Component (signed 12 bits, 1:3:8)*/\r
+ uint16_t rbGain;\r
+ /** Green Gain for Green Component (signed 12 bits, 1:3:8)*/\r
+ uint16_t ggGain;\r
+ /** Red Gain for Green Component (signed 12 bits, 1:3:8)*/\r
+ uint16_t grGain;\r
+ /** Blue Gain for Green Component (signed 12 bits, 1:3:8)*/\r
+ uint16_t gbGain;\r
+ /** Green Gain for Blue Component (signed 12 bits, 1:3:8) */\r
+ uint16_t bgGain;\r
+ /** Red Gain for Blue Component (signed 12 bits, 1:3:8) */\r
+ uint16_t brGain;\r
+ /** Blue Gain for Blue Component (signed 12 bits, 1:3:8)*/\r
+ uint16_t bbGain;\r
+};\r
+\r
+/** color space convertion components structure */\r
+struct _color_space {\r
+ /** Red Gain for Luminance (signed 12 bits 1:3:8) */\r
+ uint16_t YrGain;\r
+ /** Green Gain for Luminance (signed 12 bits 1:3:8)*/\r
+ uint16_t YgGain;\r
+ /** Blue Gain for Luminance Component (12 bits signed 1:3:8)*/\r
+ uint16_t YbGain;\r
+ /** Luminance Offset (11 bits signed 1:10:0)*/\r
+ uint16_t Yoffset;\r
+ /** Green Gain for Blue Chrominance (signed 12 bits 1:3:8)*/\r
+ uint16_t cbrGain;\r
+ /** Red Gain for Blue Chrominance (signed 12 bits, 1:3:8)*/\r
+ uint16_t cbgGain;\r
+ /** Blue Gain for Blue Chrominance (signed 12 bits 1:3:8)*/\r
+ uint16_t cbbGain;\r
+ /** Blue Chrominance Offset (signed 11 bits 1:10:0)*/\r
+ uint16_t cbOffset;\r
+ /** Red Gain for Red Chrominance (signed 12 bits 1:3:8)*/\r
+ uint16_t crrGain;\r
+ /** Green Gain for Red Chrominance (signed 12 bits 1:3:8)*/\r
+ uint16_t crgGain;\r
+ /** Blue Gain for Red Chrominance (signed 12 bits 1:3:8)*/\r
+ uint16_t crbGain;\r
+ /** Red Chrominance Offset (signed 11 bits 1:10:0)*/\r
+ uint16_t crOffset;\r
+};\r
+\r
+/** \brief Structure for ISC DMA descriptor view0 that can be\r
+ * performed when the pixel or data stream is packed.*/\r
+struct _isc_dma_view0\r
+{\r
+ /** ISC DMA Control. */\r
+ uint32_t ctrl;\r
+ /** Next ISC DMA Descriptor Address number. */\r
+ uint32_t next_desc;\r
+ /** Transfer Address. */\r
+ uint32_t addr;\r
+ /** stride . */\r
+ uint32_t stride;\r
+};\r
+\r
+/** \brief Structure for ISC DMA descriptor view1 that can be\r
+ * performed for YCbCr semi-planar pixel stream.*/\r
+struct _isc_dma_view1\r
+{\r
+ /** ISC DMA Control. */\r
+ uint32_t ctrl;\r
+ /** Next ISC DMA Descriptor Address number. */\r
+ uint32_t next_desc;\r
+ /** Transfer Address 0. */\r
+ uint32_t addr0;\r
+ /** stride 0 . */\r
+ uint32_t stride0;\r
+ /** Transfer Address 1. */\r
+ uint32_t addr1;\r
+ /** stride 1 . */\r
+ uint32_t stride1;\r
+\r
+};\r
+\r
+/** \brief Structure for ISC DMA descriptor view2 that can be\r
+ * performed for used for YCbCr planar pixel stream.*/\r
+struct _isc_dma_view2\r
+{\r
+ /** ISC DMA Control. */\r
+ uint32_t ctrl;\r
+ /** Next ISC DMA Descriptor Address number. */\r
+ uint32_t next_desc;\r
+ /** Transfer Address 0. */\r
+ uint32_t addr0;\r
+ /** stride 0. */\r
+ uint32_t stride0;\r
+ /** Transfer Address 1. */\r
+ uint32_t addr1;\r
+ /** stride 1 . */\r
+ uint32_t stride1;\r
+ /** Transfer Address 2. */\r
+ uint32_t addr2;\r
+ /** stride 2. */\r
+ uint32_t stride2;\r
+};\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/*------------------------------------------\r
+ * ISC Control functions\r
+ *----------------------------------------*/\r
+extern void isc_start_capture(void);\r
+extern void isc_stop_capture(void);\r
+extern uint32_t isc_get_ctrl_status(void);\r
+extern void isc_update_profile(void);\r
+extern void isc_software_reset(void);\r
+\r
+/*------------------------------------------\r
+ * PFE(Parallel Front End) functions\r
+ *----------------------------------------*/\r
+extern void isc_pfe_set_video_mode(uint32_t vmode);\r
+extern void isc_pfe_set_sync_polarity(uint32_t hpol, uint32_t vpol);\r
+extern void isc_pfe_set_pixel_polarity(uint32_t ppol);\r
+extern void isc_pfe_set_field_polarity(uint32_t fpol);\r
+extern void isc_pfe_set_gated_clock(uint8_t en);\r
+extern void isc_pfe_set_cropping_enabled(uint8_t enCol, uint8_t enRow);\r
+extern void isc_pfe_set_bps(uint32_t bps);\r
+extern void isc_pfe_set_single_shot(void);\r
+extern void isc_pfe_set_continuous_shot(void);\r
+extern void isc_pfe_set_cropping_area(uint32_t Hstart, uint32_t Hend,\r
+ uint32_t Vstart, uint32_t Vend);\r
+\r
+/*------------------------------------------\r
+ * Clock configuration functions\r
+ *----------------------------------------*/\r
+ extern void isc_configure_isp_clock(uint32_t isp_clk_div,\r
+ uint32_t isp_clk_sel);\r
+extern void isc_enable_isp_clock(void);\r
+extern void isc_disable_isp_clock(void);\r
+extern void isc_reset_isp_clock(void);\r
+extern void isc_configure_master_clock(uint32_t master_clk_div,\r
+ uint32_t master_clk_sel);\r
+extern void isc_enable_master_clock(void);\r
+extern void isc_disable_master_clock(void);\r
+extern void isc_reset_master_clock(void);\r
+extern uint32_t isc_get_clock_status(void);\r
+\r
+/*------------------------------------------\r
+ * Interrupt functions\r
+ *----------------------------------------*/\r
+extern void isc_enable_interrupt(uint32_t flag);\r
+extern void isc_disable_interrupt(uint32_t flag);\r
+extern uint32_t isc_interrupt_status(void);\r
+\r
+/*------------------------------------------\r
+ * White Balance functions\r
+ *----------------------------------------*/\r
+extern void isc_wb_enabled(uint8_t enabled);\r
+extern void isc_wb_set_bayer_pattern(uint8_t pattern);\r
+extern void isc_wb_adjust_bayer_color(uint32_t rOffset, uint32_t grOffset,\r
+ uint32_t bOffset, uint32_t gbOffset,\r
+ uint32_t rGain, uint32_t grGain,\r
+ uint32_t bGain, uint32_t gbGain);\r
+\r
+/*------------------------------------------\r
+ * Color Filter Array functions\r
+ *----------------------------------------*/\r
+extern void isc_cfa_enabled(uint8_t enabled);\r
+extern void isc_cfa_configure(uint8_t pattern, uint8_t edge);\r
+\r
+/*------------------------------------------\r
+ * Color Correction functions\r
+ *----------------------------------------*/\r
+extern void isc_cc_enabled(uint8_t enabled);\r
+extern void isc_cc_configure(struct _color_correct* cc);\r
+\r
+/*------------------------------------------\r
+ * Gamma Correction functions\r
+ *----------------------------------------*/\r
+extern void isc_gamma_enabled(uint8_t enabled, uint8_t channels);\r
+extern void isc_gamma_configure(uint16_t* rGamConstant, uint16_t* rGamSlope,\r
+ uint16_t* gGamConstant, uint16_t* gGamSlope,\r
+ uint16_t* bGamConstant, uint16_t* bGamSlope);\r
+\r
+/*------------------------------------------\r
+ * Color Space Conversion functions\r
+ *----------------------------------------*/\r
+extern void isc_csc_enabled(uint8_t enabled);\r
+extern void isc_csc_configure(struct _color_space* cs);\r
+\r
+/*------------------------------------------\r
+ * Contrast And Brightness functions\r
+ *----------------------------------------*/\r
+extern void isc_cbc_enabled(uint8_t enabled);\r
+extern void isc_cbc_configure(uint8_t ccir656, uint8_t byteOrder,\r
+ uint16_t brightness, uint16_t contrast);\r
+\r
+/*------------------------------------------\r
+ * Sub-sampling functions\r
+ *----------------------------------------*/\r
+extern void isc_sub422_enabled(uint8_t enabled);\r
+extern void isc_sub422_configure(uint8_t ccir656, uint8_t byte_order,\r
+ uint8_t lpf);\r
+extern void isc_sub420_configure(uint8_t enabled, uint8_t filter);\r
+\r
+/*------------------------------------------\r
+ * Rounding, Limiting and Packing functions\r
+ *----------------------------------------*/\r
+extern void isc_rlp_configure(uint8_t rlpMode, uint8_t alpha);\r
+\r
+/*------------------------------------------\r
+ * Histogram functions\r
+ *----------------------------------------*/\r
+extern void isc_histogram_enabled(uint8_t enabled);\r
+extern void isc_histogram_configure(uint8_t mode, uint8_t bay_sel,\r
+ uint8_t reset);\r
+extern void isc_update_histogram_table(void);\r
+extern void isc_clear_histogram_table(void);\r
+\r
+/*------------------------------------------\r
+ * DMA functions\r
+ *----------------------------------------*/\r
+extern void isc_dma_configure_input_mode(uint32_t mode);\r
+extern void isc_dma_configure_desc_entry(uint32_t desc_entry);\r
+extern void isc_dma_enable(uint32_t ctrl);\r
+extern void isc_dma_adderss(uint8_t channel, uint32_t address, uint32_t stride);\r
+\r
+#endif //#ifndef ISC_H\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/l2cc.h"\r
+#include "cortex-a/cp15.h"\r
+#include "trace.h"\r
+\r
+#include <assert.h>\r
+#include <stdbool.h>\r
+#include <string.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+uint32_t l2cc_is_enabled(void)\r
+{\r
+ return ((L2CC->L2CC_CR) & L2CC_CR_L2CEN);\r
+}\r
+\r
+void l2cc_enable(void)\r
+{\r
+ L2CC->L2CC_CR |= L2CC_CR_L2CEN;\r
+ asm volatile("": : :"memory");\r
+ asm("dsb");\r
+ asm("isb");\r
+ trace_info("L2 cache is enabled\r\n");\r
+}\r
+\r
+void l2cc_disable(void)\r
+{\r
+ L2CC->L2CC_CR &= ~L2CC_CR_L2CEN;\r
+ asm volatile("": : :"memory");\r
+ asm("dsb");\r
+ asm("isb");\r
+ trace_info("L2 cache is disabled\r\n");\r
+}\r
+\r
+void l2cc_exclusive_cache(uint8_t enable)\r
+{\r
+ uint32_t cfg;\r
+ if (l2cc_is_enabled()) {\r
+ l2cc_disable();\r
+ }\r
+ cfg = L2CC->L2CC_ACR;\r
+ if (enable) {\r
+ cp15_exclusive_cache();\r
+ cfg |= L2CC_ACR_EXCC;\r
+ trace_info("L2 Exclusive mode enabled\n\r");\r
+ } else {\r
+ cp15_non_exclusive_cache();\r
+ cfg &= ~L2CC_ACR_EXCC;\r
+ trace_info("L2 Exclusive mode disabled\n\r");\r
+ }\r
+ L2CC->L2CC_ACR |= cfg;\r
+}\r
+\r
+void l2cc_config_lat_ram(struct _ram_latency_control * latencies)\r
+{\r
+ if (l2cc_is_enabled()) {\r
+ l2cc_disable();\r
+ }\r
+\r
+ L2CC->L2CC_TRCR =\r
+ (L2CC_TRCR_TSETLAT(latencies->tag.setup) |\r
+ L2CC_TRCR_TRDLAT(latencies->tag.read) |\r
+ L2CC_TRCR_TWRLAT(latencies->tag.write));\r
+ L2CC->L2CC_DRCR =\r
+ (L2CC_DRCR_DSETLAT(latencies->data.setup) |\r
+ L2CC_DRCR_DRDLAT(latencies->data.read) |\r
+ L2CC_DRCR_DWRLAT(latencies->data.write));\r
+}\r
+\r
+void l2cc_set_config(const struct _l2cc_control* cfg)\r
+{\r
+ uint32_t aux_control, debug_control, prefetch_control, power_control;\r
+\r
+ if (cfg->offset > 31) {\r
+ assert(0);\r
+ }\r
+ if ((cfg->offset > 7) && (cfg->offset < 15)) {\r
+ assert(0);\r
+ }\r
+ if ((cfg->offset > 15) && (cfg->offset < 23)) {\r
+ assert(0);\r
+ }\r
+ if ((cfg->offset > 23) && (cfg->offset < 31)) {\r
+ assert(0);\r
+ }\r
+\r
+ if (l2cc_is_enabled()) {\r
+ l2cc_disable();\r
+ }\r
+\r
+ aux_control = ((cfg->high_prior_so << 10) |\r
+ (cfg->store_buff_dev_limit << 11) |\r
+ (cfg->shared_attr_invalidate << 13) |\r
+ (cfg->evt_mon_bus << 20) |\r
+ (cfg->parity << 21) |\r
+ (cfg->shared_attr_override << 22) |\r
+ (L2CC_ACR_FWA(cfg->force_write_alloc)) |\r
+ (cfg->cache_replacement << 25) |\r
+ (cfg->non_sec_lockdown << 26) |\r
+ (cfg->it_acces_non_sec << 27) |\r
+ (cfg->data_prefetch << 28) |\r
+ (cfg->instruct_prefetch << 29));\r
+\r
+ debug_control = ((cfg->no_cache_linefill << 0) |\r
+ (cfg->no_write_back << 1));\r
+\r
+ prefetch_control = ((L2CC_PCR_OFFSET(cfg->offset << 0)) |\r
+ (cfg->exclusive_seq_same_id << 21) |\r
+ (cfg->incr_double_linefill << 23) |\r
+ (cfg->prefetch_drop << 24) |\r
+ (cfg->DLFWRDIS << 27) |\r
+ (cfg->data_prefetch << 28) |\r
+ (cfg->instruct_prefetch << 29) |\r
+ (cfg->double_linefill << 30));\r
+\r
+ power_control = ((cfg->standby_mode << 0) |\r
+ (cfg->dyn_clock_gating << 1));\r
+\r
+ L2CC->L2CC_ACR = aux_control;\r
+ L2CC->L2CC_DCR = debug_control;\r
+ L2CC->L2CC_PCR = prefetch_control;\r
+ L2CC->L2CC_POWCR = power_control;\r
+}\r
+\r
+void l2cc_data_prefetch_enable(void)\r
+{\r
+ L2CC->L2CC_PCR |= L2CC_PCR_DATPEN;\r
+}\r
+\r
+void l2cc_inst_prefetch_enable(void)\r
+{\r
+ L2CC->L2CC_PCR |= L2CC_PCR_INSPEN;\r
+}\r
+\r
+void l2cc_enable_reset_counter(uint8_t event_counter)\r
+{\r
+ assert((event_counter > 3) ? 0 : 1);\r
+ L2CC->L2CC_ECR = (L2CC_ECR_EVCEN | (event_counter << 1));\r
+}\r
+\r
+void l2cc_event_config(uint8_t event_counter, uint8_t source, uint8_t it)\r
+{\r
+ if (l2cc_is_enabled()) {\r
+ L2CC->L2CC_CR = false;\r
+ }\r
+ assert((event_counter > 1) ? 0 : 1);\r
+ if (!event_counter) {\r
+ L2CC->L2CC_ECFGR0 = (source | it);\r
+ } else {\r
+ L2CC->L2CC_ECFGR1 = (source | it);\r
+ }\r
+\r
+}\r
+\r
+uint32_t l2cc_event_counter_value(uint8_t event_counter)\r
+{\r
+ assert((event_counter > 1) ? 0 : 1);\r
+ if (!event_counter) {\r
+ return L2CC->L2CC_EVR0;\r
+ } else {\r
+ return L2CC->L2CC_EVR1;\r
+ }\r
+}\r
+\r
+void l2cc_enable_it(uint16_t sources)\r
+{\r
+ L2CC->L2CC_IMR |= sources;\r
+}\r
+\r
+void l2cc_disable_it(uint16_t sources)\r
+{\r
+ L2CC->L2CC_IMR &= (!sources);\r
+}\r
+\r
+unsigned short l2cc_it_status_raw(uint16_t sources)\r
+{\r
+ return ((L2CC->L2CC_RISR) & sources) ? 1 : 0;\r
+}\r
+\r
+uint16_t l2cc_it_status_mask(uint16_t sources)\r
+{\r
+ return ((L2CC->L2CC_MISR) & sources) ? 1 : 0;\r
+}\r
+\r
+void l2cc_it_clear(uint16_t sources)\r
+{\r
+ L2CC->L2CC_ICR |= sources;\r
+}\r
+\r
+uint8_t l2cc_poll_spniden()\r
+{\r
+ return ((L2CC->L2CC_DCR & L2CC_DCR_SPNIDEN) >> 2);\r
+}\r
+\r
+void l2cc_cache_sync()\r
+{\r
+ while ((L2CC->L2CC_CSR) & L2CC_CSR_C) ;\r
+ L2CC->L2CC_CSR = L2CC_CSR_C;\r
+ while ((L2CC->L2CC_CSR) & L2CC_CSR_C) ;\r
+}\r
+\r
+void l2cc_invalidate_pal(uint32_t phys_addr)\r
+{\r
+ static uint32_t Tag;\r
+ static uint16_t Index;\r
+ Tag = (phys_addr >> (OFFSET_BIT + INDEX_BIT));\r
+ Index = (phys_addr >> OFFSET_BIT) & ((1 << INDEX_BIT) - 1);\r
+ L2CC->L2CC_IPALR = (L2CC_IPALR_TAG(Tag) | L2CC_IPALR_IDX(Index) | L2CC_IPALR_C);\r
+ while ((L2CC->L2CC_IPALR) & L2CC_IPALR_C) ;\r
+}\r
+\r
+void l2cc_clean_pal(uint32_t phys_addr)\r
+{\r
+ static uint32_t Tag;\r
+ static uint16_t Index;\r
+\r
+ Tag = (phys_addr >> (OFFSET_BIT + INDEX_BIT));\r
+ Index = (phys_addr >> OFFSET_BIT) & ((1 << INDEX_BIT) - 1);\r
+ L2CC->L2CC_CPALR =\r
+ (L2CC_CPALR_TAG(Tag) | L2CC_CPALR_IDX(Index) | L2CC_CPALR_C);\r
+ while ((L2CC->L2CC_CPALR) & L2CC_CPALR_C) ;\r
+}\r
+\r
+void l2cc_clean_ix(uint32_t phys_addr)\r
+{\r
+ static uint32_t Tag;\r
+ static uint16_t Index;\r
+\r
+ Tag = (phys_addr >> (OFFSET_BIT + INDEX_BIT));\r
+ Index = (phys_addr >> OFFSET_BIT) & ((1 << INDEX_BIT) - 1);\r
+ L2CC->L2CC_CIPALR =\r
+ (L2CC_CIPALR_TAG(Tag) | L2CC_CIPALR_IDX(Index) | L2CC_CIPALR_C);\r
+ while ((L2CC->L2CC_CIPALR) & L2CC_CIPALR_C) ;\r
+}\r
+\r
+void l2cc_invalidate_way(uint8_t way)\r
+{\r
+ L2CC->L2CC_IWR = way;\r
+ while (L2CC->L2CC_IWR) ;\r
+ while (L2CC->L2CC_CSR) ;\r
+}\r
+\r
+void l2cc_clean_way(uint8_t way)\r
+{\r
+ L2CC->L2CC_CWR = way;\r
+ while (L2CC->L2CC_CWR) ;\r
+ while (L2CC->L2CC_CSR) ;\r
+}\r
+\r
+/**\r
+ * \brief Clean Invalidate cache by way\r
+ * \param way way number\r
+ */\r
+static void l2cc_clean_invalidate_way(uint8_t way)\r
+{\r
+ L2CC->L2CC_CIWR = way;\r
+ while (L2CC->L2CC_CSR) ;\r
+}\r
+\r
+void l2cc_clean_index(uint32_t phys_addr, uint8_t way)\r
+{\r
+ static uint16_t Index;\r
+\r
+ Index = (phys_addr >> OFFSET_BIT) & ((1 << INDEX_BIT) - 1);\r
+ L2CC->L2CC_CIR =\r
+ (L2CC_CIR_IDX(Index) | L2CC_CIR_WAY(way) | L2CC_CIR_C);\r
+ while ((L2CC->L2CC_CIR) & L2CC_CIR_C) ;\r
+}\r
+\r
+void l2cc_clean_invalidate_index(uint32_t phys_addr, uint8_t way)\r
+{\r
+ static uint16_t Index;\r
+\r
+ (void) way;\r
+ Index = (phys_addr >> OFFSET_BIT) & ((1 << INDEX_BIT) - 1);\r
+ L2CC->L2CC_CIIR =\r
+ (L2CC_CIIR_IDX(Index) | L2CC_CIIR_WAY(Index) | L2CC_CIIR_C);\r
+ while ((L2CC->L2CC_CIIR) & L2CC_CIIR_C) ;\r
+}\r
+\r
+void l2cc_data_lockdown(uint8_t way)\r
+{\r
+ L2CC->L2CC_DLKR = way;\r
+ while (L2CC->L2CC_CSR) ;\r
+}\r
+\r
+void l2cc_instruction_lockdown(uint8_t way)\r
+{\r
+ L2CC->L2CC_ILKR = way;\r
+ while (L2CC->L2CC_CSR) ;\r
+}\r
+\r
+static void l2cc_clean(void)\r
+{\r
+ // Clean of L1; This is broadcast within the cluster\r
+ cp15_dcache_clean();\r
+ if (l2cc_is_enabled()) {\r
+ // forces the address out past level 2\r
+ l2cc_clean_way(0xFF);\r
+ // Ensures completion of the L2 clean\r
+ l2cc_cache_sync();\r
+ }\r
+}\r
+\r
+static void l2cc_invalidate(void)\r
+{\r
+ if (l2cc_is_enabled()) {\r
+ // forces the address out past level 2\r
+ l2cc_invalidate_way(0xFF);\r
+ // Ensures completion of the L2 inval\r
+ l2cc_cache_sync();\r
+ }\r
+ // Inval of L1; This is broadcast within the cluster\r
+ cp15_dcache_invalidate();\r
+}\r
+\r
+static void l2cc_clean_invalidate(void)\r
+{\r
+ /* Clean of L1; This is broadcast within the cluster */\r
+ cp15_dcache_clean();\r
+\r
+ if (l2cc_is_enabled()) {\r
+ /* forces the address out past level 2 */\r
+ l2cc_clean_invalidate_way(0xFF);\r
+ /* Ensures completion of the L2 inval */\r
+ l2cc_cache_sync();\r
+ }\r
+\r
+ /* Inval of L1; This is broadcast within the cluster */\r
+ cp15_dcache_invalidate();\r
+}\r
+\r
+void l2cc_cache_maintenance(enum _maint_op maintenance)\r
+{\r
+ switch (maintenance) {\r
+ case L2CC_DCACHE_CLEAN:\r
+ l2cc_clean();\r
+ break;\r
+ case L2CC_DCACHE_INVAL:\r
+ l2cc_invalidate();\r
+ break;\r
+ case L2CC_DCACHE_FLUSH:\r
+ l2cc_clean_invalidate();\r
+ break;\r
+ }\r
+}\r
+\r
+void l2cc_invalidate_region(uint32_t start, uint32_t end)\r
+{\r
+ assert(start < end);\r
+ uint32_t current = start & ~0x1fUL;\r
+ if (l2cc_is_enabled()) {\r
+ while (current <= end) {\r
+ l2cc_invalidate_pal(current);\r
+ current += 32;\r
+ }\r
+ l2cc_invalidate_pal(end);\r
+ }\r
+ cp15_invalidate_dcache_for_dma(start, end);\r
+}\r
+\r
+void l2cc_clean_region(uint32_t start, uint32_t end)\r
+{\r
+ assert(start < end);\r
+ uint32_t current = start & ~0x1fUL;\r
+ if (l2cc_is_enabled()) {\r
+ while (current <= end) {\r
+ l2cc_clean_pal(current);\r
+ current += 32;\r
+ }\r
+ l2cc_clean_pal(end);\r
+ }\r
+ cp15_clean_dcache_for_dma(start, end);\r
+}\r
+\r
+void l2cc_configure(const struct _l2cc_control* cfg)\r
+{\r
+ l2cc_event_config(0, L2CC_ECFGR0_ESRC_SRC_DRHIT,\r
+ L2CC_ECFGR0_EIGEN_INT_DIS);\r
+ l2cc_event_config(1, L2CC_ECFGR0_ESRC_SRC_DWHIT,\r
+ L2CC_ECFGR0_EIGEN_INT_DIS);\r
+\r
+ l2cc_enable_reset_counter(L2CC_RESET_BOTH_COUNTER);\r
+ l2cc_set_config(cfg);\r
+ /* Enable Prefetch */\r
+ l2cc_inst_prefetch_enable();\r
+ l2cc_data_prefetch_enable();\r
+ /* Invalidate whole L2CC */\r
+ l2cc_invalidate_way(0xFF);\r
+ /* Disable all L2CC Interrupt */\r
+ l2cc_disable_it(0x1FF);\r
+ /* Clear all L2CC Interrupt */\r
+ l2cc_it_clear(0xFF);\r
+ l2cc_exclusive_cache(true);\r
+ l2cc_enable();\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for Level 2 cache (L2CC) controller.\r
+ *\r
+ */\r
+\r
+/** \addtogroup l2cc_module L2 Cache Operations\r
+ * \ingroup cache_module\r
+ * \section Usage\r
+ * - Enable or disable L2CC with L2CC_Enable() or L2CC_Disable().\r
+ * - Check if L2CC is enabled with L2CC_IsEnabled().\r
+ * - Enable or disable L2CC interrupt with L2CC_EnableIT() or L2CC_DisableIT().\r
+ * - Enable data or instruction prefetch with L2CC_DataPrefetchEnable() or L2CC_InstPrefetchEnable().\r
+ *\r
+ * Related files:\n\r
+ * \ref l2cc.h\n\r
+ * \ref l2cc.c\n\r
+ */\r
+\r
+#ifndef _L2CC_H\r
+#define _L2CC_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Define\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#define OFFSET_BIT 5\r
+#define INDEX_BIT 9\r
+#define TAG_BIT 18\r
+\r
+#define L2CC_RESET_EVCOUNTER0 0\r
+#define L2CC_RESET_EVCOUNTER1 1\r
+#define L2CC_RESET_BOTH_COUNTER 3\r
+\r
+#define FWA_DEFAULT 0u\r
+#define FWA_NO_ALLOCATE 1u\r
+#define FWA_FORCE_ALLOCATE 2u\r
+#define FWA_INTERNALLY_MAPPED 3u\r
+\r
+/*----------------------------------------------------------------------------\r
+* Types\r
+*----------------------------------------------------------------------------*/\r
+\r
+enum _maint_op {\r
+ L2CC_DCACHE_CLEAN,\r
+ L2CC_DCACHE_INVAL,\r
+ L2CC_DCACHE_FLUSH\r
+};\r
+\r
+struct _latency {\r
+ uint8_t setup;\r
+ uint8_t read;\r
+ uint8_t write;\r
+};\r
+\r
+struct _ram_latency_control {\r
+ struct _latency tag;\r
+ struct _latency data;\r
+};\r
+\r
+/** L2CC structure */\r
+struct _l2cc_control {\r
+ /** High Priority for SO and Dev Reads Enable */\r
+ uint32_t high_prior_so: 1,\r
+ /** Store Buffer Device Limitation Enable */\r
+ store_buff_dev_limit: 1,\r
+ /** Shared Attribute Invalidate Enable */\r
+ shared_attr_invalidate: 1,\r
+ /** Event Monitor Bus Enable */\r
+ evt_mon_bus: 1,\r
+ /** Parity Enable */\r
+ parity: 1,\r
+ /** Shared Attribute Override Enable */\r
+ shared_attr_override: 1,\r
+ /** Force Write Allocate */\r
+ force_write_alloc: 2,\r
+ /** Cache Replacement Policy */\r
+ cache_replacement: 1,\r
+ /** Non-Secure Lockdown Enable*/\r
+ non_sec_lockdown: 1,\r
+ /** Non-Secure Interrupt Access Control */\r
+ it_acces_non_sec: 1,\r
+ /** Data Prefetch Enable*/\r
+ data_prefetch: 1,\r
+ /** Instruction Prefetch Enable */\r
+ instruct_prefetch: 1,\r
+ /** Prefetch Offset */\r
+ offset: 5,\r
+ /** Not Same ID on Exclusive Sequence Enable */\r
+ exclusive_seq_same_id: 1,\r
+ /** INCR Double Linefill Enable */\r
+ incr_double_linefill: 1,\r
+ /** Prefetch Drop Enable*/\r
+ prefetch_drop: 1,\r
+ /** Double Linefill on WRAP Read Disable */\r
+ DLFWRDIS: 1,\r
+ /** Double linefill Enable */\r
+ double_linefill: 1,\r
+ /** Standby Mode Enable */\r
+ standby_mode: 1,\r
+ /** Dynamic Clock Gating Enable */\r
+ dyn_clock_gating: 1,\r
+ /** Disable Cache Linefill*/\r
+ no_cache_linefill: 1,\r
+ /** Disable Write-back, Force Write-through */\r
+ no_write_back: 1;\r
+};\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Check if Level 2 cache is enable.\r
+ */\r
+extern uint32_t l2cc_is_enabled(void);\r
+\r
+/**\r
+ * \brief Enable Level 2 cache.\r
+ */\r
+extern void l2cc_enable(void);\r
+\r
+/**\r
+ * \brief Disable Level 2 cache.\r
+ */\r
+extern void l2cc_disable(void);\r
+\r
+/**\r
+ * \brief Configures Level 2 cache as exclusive cache.\r
+ * \param Enable Enable/disable exclusive cache.\r
+ */\r
+extern void l2cc_exclusive_cache(uint8_t enable);\r
+\r
+/**\r
+ * \brief Configures Level 2 cache RAM Latency (Tag and Data).\r
+ * \param latencies Structure containing RAM Tag and Data latencies\r
+ */\r
+extern void l2cc_config_lat_ram(struct _ram_latency_control * latencies);\r
+\r
+/**\r
+ * \brief Configures Level 2 cache.\r
+ * \param cfg Configuration values to put in Auxiliary, prefetch,\r
+ * debug and powercontrol registers.\r
+ */\r
+extern void l2cc_set_config(const struct _l2cc_control* cfg);\r
+\r
+/**\r
+ * \brief Enables Data prefetch on L2\r
+ */\r
+extern void l2cc_data_prefetch_enable(void);\r
+\r
+/**\r
+ * \brief Enables instruction prefetch on L2\r
+ */\r
+extern void l2cc_inst_prefetch_enable(void);\r
+\r
+/**\r
+ * \brief Enables instruction prefetch on L2\r
+ * \param event_counter Counter of the events.\r
+ */\r
+extern void l2cc_enable_reset_counter(uint8_t event_counter);\r
+\r
+/**\r
+ * \brief Configures Event of Level 2 cache.\r
+ * \param event_counter Eventcounter 1 or 0\r
+ * \param source Event Genration source\r
+ * \param it Event Counter Interrupt Generation condition\r
+ */\r
+extern void l2cc_event_config(uint8_t event_counter, uint8_t source,\r
+ uint8_t it);\r
+\r
+/**\r
+ * \brief Reads Event Counter value.\r
+ * \param event_counter choose Eventcounter 1 or 0\r
+ */\r
+extern uint32_t l2cc_event_counter_value(uint8_t event_counter);\r
+\r
+/**\r
+ * \brief Enable interrupts\r
+ * \param sources Interrupt source\r
+ */\r
+extern void l2cc_enable_it(uint16_t sources);\r
+\r
+/**\r
+ * \brief Disable interrupts\r
+ * \param sources Interrupt source\r
+ */\r
+extern void l2cc_disable_it(uint16_t sources);\r
+\r
+/**\r
+ * \brief Enabled interrupt's raw status\r
+ * \param sources Interrupt source\r
+ */\r
+extern uint16_t l2cc_it_status_raw(uint16_t sources);\r
+\r
+/**\r
+ * \brief Status of masked interrupts\r
+ * \param sources Interrupt source\r
+ */\r
+extern uint16_t l2cc_it_status_mask(uint16_t sources);\r
+\r
+/**\r
+ * \brief Clear interrupts\r
+ * \param sources Interrupt source\r
+ */\r
+extern void l2cc_it_clear(uint16_t sources);\r
+\r
+/**\r
+ * \brief Poll SPNIDEN signal\r
+ */\r
+extern uint8_t l2cc_poll_spniden(void);\r
+\r
+/**\r
+ * \brief Synchronizes the L2 cache\r
+ */\r
+extern void l2cc_cache_sync(void);\r
+\r
+/**\r
+ * \brief Invalidate cache by way\r
+ * \param way way number\r
+ */\r
+extern void l2cc_invalidate_way(uint8_t way);\r
+\r
+/**\r
+ * \brief Clean cache by way\r
+ * \param way way number\r
+ */\r
+extern void l2cc_clean_way(uint8_t way);\r
+\r
+/**\r
+ * \brief Invalidate cache by Physical addersse\r
+ * \param phys_addr Physical addresse\r
+ */\r
+extern void l2cc_invalidate_pal(uint32_t phys_addr);\r
+\r
+/**\r
+ * \brief Clean cache by Physical addersse\r
+ * \param phys_addr Physical addresse\r
+ */\r
+extern void l2cc_clean_pal(uint32_t phys_addr);\r
+\r
+/**\r
+ * \brief Clean index cache by Physical addersse\r
+ * \param phys_addr Physical addresse\r
+ */\r
+extern void l2cc_clean_ix(uint32_t phys_addr);\r
+\r
+/**\r
+ * \brief Clean cache by Index\r
+ * \param phys_addr Physical addresse\r
+ * \param way way number\r
+ */\r
+extern void l2cc_clean_index(uint32_t phys_addr, uint8_t way);\r
+\r
+/**\r
+ * \brief Clean Invalidate cache by index\r
+ * \param phys_addr Physical address\r
+ * \param way way number\r
+ */\r
+extern void l2cc_clean_invalidate_index(uint32_t phys_addr, uint8_t way);\r
+\r
+/**\r
+ * \brief cache Data lockdown\r
+ * \param way way number\r
+ */\r
+extern void l2cc_data_lockdown(uint8_t way);\r
+\r
+/**\r
+ * \brief cache instruction lockdown\r
+ * \param way way number\r
+ */\r
+extern void l2cc_instruction_lockdown(uint8_t way);\r
+\r
+/**\r
+ * \brief L2 DCache maintenance (clean/invalidate/flush)\r
+ *\r
+ * \param maintenance Maintenance operation to apply: \sa #_maint_op\r
+ */\r
+extern void l2cc_cache_maintenance(enum _maint_op maintenance);\r
+\r
+/**\r
+ * \brief Invalidate cache lines corresponding to a memory region\r
+ *\r
+ * \param start Beginning of the memory region\r
+ * \param end End of the memory region\r
+ */\r
+extern void l2cc_invalidate_region(uint32_t start, uint32_t end);\r
+\r
+/**\r
+ * \brief Clean cache lines corresponding to a memory region\r
+ *\r
+ * \param start Beginning of the memory region\r
+ * \param end End of the memory region\r
+ */\r
+extern void l2cc_clean_region(uint32_t start, uint32_t end);\r
+\r
+/**\r
+ * \brief Enable level two cache controller (L2CC)\r
+ *\r
+ * \param cfg configuration to apply: \sa #_l2cc_control\r
+ */\r
+extern void l2cc_configure(const struct _l2cc_control* cfg);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* #ifndef _L2CC_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#include "peripherals/matrix.h"\r
+\r
+#include <assert.h>\r
+\r
+void matrix_configure_slave_sec(Matrix* mtx, uint8_t slave_id,\r
+ uint8_t sel_mask, uint8_t read_mask,\r
+ uint8_t write_mask)\r
+{\r
+ mtx->MATRIX_SSR[slave_id] = sel_mask | (read_mask << 8) |\r
+ (write_mask << 16);\r
+}\r
+\r
+void matrix_set_slave_split_addr(Matrix* mtx, uint8_t slave_id,\r
+ uint8_t area_size, uint8_t mask)\r
+{\r
+ uint8_t i = mask, j = 0;\r
+ uint32_t value = 0;\r
+ for (i = 1; (i <= mask) && (j < 32); i <<= 1, j += 4) {\r
+ if (i & mask)\r
+ value |= area_size << j;\r
+ }\r
+ mtx->MATRIX_SASSR[slave_id] = value;\r
+}\r
+\r
+void matrix_set_slave_region_size(Matrix* mtx, uint8_t slave_id,\r
+ uint8_t area_size, uint8_t mask)\r
+{\r
+ assert(slave_id != 0);\r
+ uint8_t i = mask, j = 0;\r
+ uint32_t value = 0;\r
+ for (i = 1; (i <= mask) && (j < 32 ); i <<= 1, j += 4) {\r
+ if (i & mask)\r
+ value |= area_size << j;\r
+ }\r
+ mtx->MATRIX_SRTSR[slave_id] = value;\r
+}\r
+\r
+uint8_t matrix_is_peripheral_secured(Matrix* mtx, uint32_t periph_id)\r
+{\r
+ if (mtx->MATRIX_SPSELR[periph_id / 32] & (1 << (periph_id % 32))) {\r
+ return 0;\r
+ } else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+void matrix_remove_write_protection(Matrix* mtx)\r
+{\r
+ mtx->MATRIX_WPMR = MATRIX_WPMR_WPKEY_PASSWD;\r
+}\r
+\r
+/**\r
+ * \brief Changes the mapping of the chip so that the remap area mirrors the\r
+ * internal ROM or the EBI CS0.\r
+ */\r
+void matrix_remap_rom(void)\r
+{\r
+ AXIMX->AXIMX_REMAP = 0;\r
+}\r
+\r
+/**\r
+ * \brief Changes the mapping of the chip so that the remap area mirrors the\r
+ * internal RAM.\r
+ */\r
+\r
+void matrix_remap_ram(void)\r
+{\r
+ volatile uint32_t i;\r
+ AXIMX->AXIMX_REMAP = AXIMX_REMAP_REMAP0;\r
+ for(i=1000;--i;);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef MATRIX_HEADER_\r
+#define MATRIX_HEADER_\r
+\r
+#include "chip.h"\r
+#include <stdint.h>\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define MATRIX_AREA_4K (0x0u) /* 0x1000 */\r
+#define MATRIX_AREA_8K (0x1u) /* 0x2000 */\r
+#define MATRIX_AREA_16K (0x2u) /* 0x4000 */\r
+#define MATRIX_AREA_32K (0x3u) /* 0x8000 */\r
+#define MATRIX_AREA_64K (0x4u) /* 0x10000 */\r
+#define MATRIX_AREA_128K (0x5u) /* 0x20000 */\r
+#define MATRIX_AREA_256K (0x6u) /* 0x40000 */\r
+#define MATRIX_AREA_512K (0x7u) /* 0x80000 */\r
+#define MATRIX_AREA_1M (0x8u) /* 0x100000 */\r
+#define MATRIX_AREA_2M (0x9u) /* 0x200000 */\r
+#define MATRIX_AREA_4M (0xAu) /* 0x400000 */\r
+#define MATRIX_AREA_8M (0xBu) /* 0x800000 */\r
+#define MATRIX_AREA_16M (0xCu) /* 0x1000000 */\r
+#define MATRIX_AREA_32M (0xDu) /* 0x2000000 */\r
+#define MATRIX_AREA_64M (0xEu) /* 0x4000000 */\r
+#define MATRIX_AREA_128M (0xFu) /* 0x8000000 */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+extern void matrix_configure_slave_sec(Matrix* mtx, uint8_t slave_id,\r
+ uint8_t sel_mask, uint8_t read_mask,\r
+ uint8_t write_mask);\r
+\r
+extern void matrix_set_slave_split_addr(Matrix* mtx, uint8_t slave_id,\r
+ uint8_t area, uint8_t mask);\r
+\r
+extern void matrix_set_slave_region_size(Matrix* mtx, uint8_t slave_id,\r
+ uint8_t area, uint8_t mask);\r
+\r
+extern uint8_t matrix_is_peripheral_secured(Matrix* mtx, uint32_t periph_id);\r
+\r
+extern void matrix_remove_write_protection(Matrix* mtx);\r
+\r
+extern void matrix_remap_rom(void);\r
+\r
+extern void matrix_remap_ram(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* MATRIX_HEADER_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file\r
+ * Implements functions for Controller Area Network with Flexible Data-rate,\r
+ * relying on the MCAN peripheral.\r
+ */\r
+/** \addtogroup can_module\r
+ *@{*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "chip.h"\r
+#include "mcan.h"\r
+#include "pmc.h"\r
+\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Local definitions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+enum mcan_dlc\r
+{\r
+ CAN_DLC_0 = 0,\r
+ CAN_DLC_1 = 1,\r
+ CAN_DLC_2 = 2,\r
+ CAN_DLC_3 = 3,\r
+ CAN_DLC_4 = 4,\r
+ CAN_DLC_5 = 5,\r
+ CAN_DLC_6 = 6,\r
+ CAN_DLC_7 = 7,\r
+ CAN_DLC_8 = 8,\r
+ CAN_DLC_12 = 9,\r
+ CAN_DLC_16 = 10,\r
+ CAN_DLC_20 = 11,\r
+ CAN_DLC_24 = 12,\r
+ CAN_DLC_32 = 13,\r
+ CAN_DLC_48 = 14,\r
+ CAN_DLC_64 = 15\r
+};\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Local functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Convert data length to Data Length Code.\r
+ * \param len length, in bytes\r
+ * \param dlc address where the matching Data Length Code will be written\r
+ * \return true if a code matched the provided length, false if this exact\r
+ * length is not supported.\r
+ */\r
+static bool get_length_code(uint8_t len, enum mcan_dlc *dlc)\r
+{\r
+ assert(dlc);\r
+\r
+ if (len <= 8) {\r
+ *dlc = (enum mcan_dlc)len;\r
+ return true;\r
+ }\r
+ if (len % 4)\r
+ return false;\r
+ len /= 4;\r
+ if (len <= 6) {\r
+ *dlc = (enum mcan_dlc)(len + 6);\r
+ return true;\r
+ }\r
+ if (len % 4)\r
+ return false;\r
+ len /= 4;\r
+ if (len > 4)\r
+ return false;\r
+ *dlc = (enum mcan_dlc)(len + 11);\r
+ return true;\r
+}\r
+\r
+/**\r
+ * \brief Convert Data Length Code to actual data length.\r
+ * \param dlc CAN_DLC_xx enum value\r
+ * \return Data length, expressed in bytes.\r
+ */\r
+static uint8_t get_data_length(enum mcan_dlc dlc)\r
+{\r
+ assert((dlc == CAN_DLC_0 || dlc > CAN_DLC_0) && dlc <= CAN_DLC_64);\r
+\r
+ if (dlc <= CAN_DLC_8)\r
+ return (uint8_t)dlc;\r
+ if (dlc <= CAN_DLC_24)\r
+ return ((uint8_t)dlc - 6) * 4;\r
+ return ((uint8_t)dlc - 11) * 16;\r
+}\r
+\r
+/**\r
+ * \brief Compute the size of the Message RAM, depending on the application.\r
+ * \param set Pointer to a MCAN instance that will be setup accordingly.\r
+ * \param cfg MCAN configuration to be considered. Only integer size parameters\r
+ * need to be configured. The other parameters can be left blank at this stage.\r
+ * \param size address where the required size of the Message RAM will be\r
+ * written, expressed in (32-bit) words.\r
+ * \return true if successful, false if a parameter is set to an unsupported\r
+ * value.\r
+ */\r
+static bool configure_ram(struct mcan_set *set,\r
+ const struct mcan_config *cfg, uint32_t *size)\r
+{\r
+ if (cfg->array_size_filt_std > 128 || cfg->array_size_filt_ext > 64\r
+ || cfg->fifo_size_rx0 > 64 || cfg->fifo_size_rx1 > 64\r
+ || cfg->array_size_rx > 64 || cfg->fifo_size_tx_evt > 32\r
+ || cfg->array_size_tx > 32 || cfg->fifo_size_tx > 32\r
+ || cfg->array_size_tx + cfg->fifo_size_tx > 32\r
+ || cfg->buf_size_rx_fifo0 > 64 || cfg->buf_size_rx_fifo1 > 64\r
+ || cfg->buf_size_rx > 64 || cfg->buf_size_tx > 64)\r
+ return false;\r
+\r
+ set->ram_filt_std = cfg->msg_ram;\r
+ *size = (uint32_t)cfg->array_size_filt_std * MCAN_RAM_FILT_STD_SIZE;\r
+ set->ram_filt_ext = cfg->msg_ram + *size;\r
+ *size += (uint32_t)cfg->array_size_filt_ext * MCAN_RAM_FILT_EXT_SIZE;\r
+ set->ram_fifo_rx0 = cfg->msg_ram + *size;\r
+ *size += (uint32_t)cfg->fifo_size_rx0 * (MCAN_RAM_BUF_HDR_SIZE\r
+ + cfg->buf_size_rx_fifo0 / 4);\r
+ set->ram_fifo_rx1 = cfg->msg_ram + *size;\r
+ *size += (uint32_t)cfg->fifo_size_rx1 * (MCAN_RAM_BUF_HDR_SIZE\r
+ + cfg->buf_size_rx_fifo1 / 4);\r
+ set->ram_array_rx = cfg->msg_ram + *size;\r
+ *size += (uint32_t)cfg->array_size_rx * (MCAN_RAM_BUF_HDR_SIZE\r
+ + cfg->buf_size_rx / 4);\r
+ set->ram_fifo_tx_evt = cfg->msg_ram + *size;\r
+ *size += (uint32_t)cfg->fifo_size_tx_evt * MCAN_RAM_TX_EVT_SIZE;\r
+ set->ram_array_tx = cfg->msg_ram + *size;\r
+ *size += (uint32_t)cfg->array_size_tx * (MCAN_RAM_BUF_HDR_SIZE\r
+ + cfg->buf_size_tx / 4);\r
+ *size += (uint32_t)cfg->fifo_size_tx * (MCAN_RAM_BUF_HDR_SIZE\r
+ + cfg->buf_size_tx / 4);\r
+ return true;\r
+}\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported Functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+bool mcan_configure_msg_ram(const struct mcan_config *cfg, uint32_t *size)\r
+{\r
+ assert(cfg);\r
+ assert(size);\r
+\r
+ struct mcan_set tmp_set = { .cfg = { 0 } };\r
+\r
+ return configure_ram(&tmp_set, cfg, size);\r
+}\r
+\r
+bool mcan_initialize(struct mcan_set *set, const struct mcan_config *cfg)\r
+{\r
+ assert(set);\r
+ assert(cfg);\r
+ assert(cfg->regs);\r
+ assert(cfg->msg_ram);\r
+\r
+ Mcan *mcan = cfg->regs;\r
+ uint32_t *element = NULL, *elem_end = NULL;\r
+ uint32_t freq, regVal32;\r
+ enum mcan_dlc dlc;\r
+\r
+ memset(set, 0, sizeof(*set));\r
+ if (!configure_ram(set, cfg, ®Val32))\r
+ return false;\r
+ set->cfg = *cfg;\r
+\r
+ /* Configure the MSB of the Message RAM Base Address */\r
+ regVal32 = (uint32_t)cfg->msg_ram >> 16;\r
+ if (cfg->id == ID_CAN0_INT0 || cfg->id == ID_CAN0_INT1)\r
+ regVal32 = (SFR->SFR_CAN & ~SFR_CAN_EXT_MEM_CAN0_ADDR_Msk)\r
+ | SFR_CAN_EXT_MEM_CAN0_ADDR(regVal32);\r
+ else\r
+ regVal32 = (SFR->SFR_CAN & ~SFR_CAN_EXT_MEM_CAN1_ADDR_Msk)\r
+ | SFR_CAN_EXT_MEM_CAN1_ADDR(regVal32);\r
+ SFR->SFR_CAN = regVal32;\r
+\r
+ /* Reset the CC Control Register */\r
+ mcan->MCAN_CCCR = 0 | MCAN_CCCR_INIT_ENABLED;\r
+\r
+ mcan_disable(set);\r
+ mcan_reconfigure(set);\r
+\r
+ /* Global Filter Configuration: Reject remote frames, reject non-matching frames */\r
+ mcan->MCAN_GFC = MCAN_GFC_RRFE_REJECT | MCAN_GFC_RRFS_REJECT\r
+ | MCAN_GFC_ANFE(2) | MCAN_GFC_ANFS(2);\r
+\r
+ /* Extended ID Filter AND mask */\r
+ mcan->MCAN_XIDAM = 0x1FFFFFFF;\r
+\r
+ /* Interrupt configuration - leave initialization with all interrupts off\r
+ * Disable all interrupts */\r
+ mcan->MCAN_IE = 0;\r
+ mcan->MCAN_TXBTIE = 0x00000000;\r
+ /* All interrupts directed to Line 0 */\r
+ mcan->MCAN_ILS = 0x00000000;\r
+ /* Disable both interrupt LINE 0 & LINE 1 */\r
+ mcan->MCAN_ILE = 0x00;\r
+ /* Clear all interrupt flags */\r
+ mcan->MCAN_IR = 0xFFCFFFFF;\r
+\r
+ /* Configure CAN bit timing */\r
+ if (cfg->bit_rate == 0\r
+ || cfg->quanta_before_sp < 3 || cfg->quanta_before_sp > 257\r
+ || cfg->quanta_after_sp < 1 || cfg->quanta_after_sp > 128\r
+ || cfg->quanta_sync_jump < 1 || cfg->quanta_sync_jump > 128)\r
+ return false;\r
+ /* Retrieve the frequency of the CAN core clock i.e. the Generated Clock */\r
+ freq = pmc_get_gck_clock(cfg->id);\r
+ /* Compute the Nominal Baud Rate Prescaler */\r
+ regVal32 = ROUND_INT_DIV(freq, cfg->bit_rate\r
+ * (cfg->quanta_before_sp + cfg->quanta_after_sp));\r
+ if (regVal32 < 1 || regVal32 > 512)\r
+ return false;\r
+ /* Apply bit timing configuration */\r
+ mcan->MCAN_NBTP = MCAN_NBTP_NBRP(regVal32 - 1)\r
+ | MCAN_NBTP_NTSEG1(cfg->quanta_before_sp - 1 - 1)\r
+ | MCAN_NBTP_NTSEG2(cfg->quanta_after_sp - 1)\r
+ | MCAN_NBTP_NSJW(cfg->quanta_sync_jump - 1);\r
+\r
+ /* Configure fast CAN FD bit timing */\r
+ if (cfg->bit_rate_fd < cfg->bit_rate\r
+ || cfg->quanta_before_sp_fd < 3 || cfg->quanta_before_sp_fd > 33\r
+ || cfg->quanta_after_sp_fd < 1 || cfg->quanta_after_sp_fd > 16\r
+ || cfg->quanta_sync_jump_fd < 1 || cfg->quanta_sync_jump_fd > 8)\r
+ return false;\r
+ /* Compute the Fast Baud Rate Prescaler */\r
+ regVal32 = ROUND_INT_DIV(freq, cfg->bit_rate_fd\r
+ * (cfg->quanta_before_sp_fd + cfg->quanta_after_sp_fd));\r
+ if (regVal32 < 1 || regVal32 > 32)\r
+ return false;\r
+ /* Apply bit timing configuration */\r
+ mcan->MCAN_DBTP = MCAN_DBTP_FBRP(regVal32 - 1)\r
+ | MCAN_DBTP_DTSEG1(cfg->quanta_before_sp_fd - 1 - 1)\r
+ | MCAN_DBTP_DTSEG2(cfg->quanta_after_sp_fd - 1)\r
+ | MCAN_DBTP_DSJW(cfg->quanta_sync_jump_fd - 1);\r
+\r
+ /* Configure Message RAM starting addresses and element count */\r
+ /* 11-bit Message ID Rx Filters */\r
+ mcan->MCAN_SIDFC =\r
+ MCAN_SIDFC_FLSSA((uint32_t)set->ram_filt_std >> 2)\r
+ | MCAN_SIDFC_LSS(cfg->array_size_filt_std);\r
+ /* 29-bit Message ID Rx Filters */\r
+ mcan->MCAN_XIDFC =\r
+ MCAN_XIDFC_FLESA((uint32_t)set->ram_filt_ext >> 2)\r
+ | MCAN_XIDFC_LSE(cfg->array_size_filt_ext);\r
+ /* Rx FIFO 0 */\r
+ mcan->MCAN_RXF0C =\r
+ MCAN_RXF0C_F0SA((uint32_t)set->ram_fifo_rx0 >> 2)\r
+ | MCAN_RXF0C_F0S(cfg->fifo_size_rx0)\r
+ | MCAN_RXF0C_F0WM(0)\r
+ | 0; /* clear MCAN_RXF0C_F0OM */\r
+ /* Rx FIFO 1 */\r
+ mcan->MCAN_RXF1C =\r
+ MCAN_RXF1C_F1SA((uint32_t)set->ram_fifo_rx1 >> 2)\r
+ | MCAN_RXF1C_F1S(cfg->fifo_size_rx1)\r
+ | MCAN_RXF1C_F1WM(0)\r
+ | 0; /* clear MCAN_RXF1C_F1OM */\r
+ /* Dedicated Rx Buffers\r
+ * Note: the HW does not know (and does not care about) how many\r
+ * dedicated Rx Buffers are used by the application. */\r
+ mcan->MCAN_RXBC =\r
+ MCAN_RXBC_RBSA((uint32_t)set->ram_array_rx >> 2);\r
+ /* Tx Event FIFO */\r
+ mcan->MCAN_TXEFC =\r
+ MCAN_TXEFC_EFSA((uint32_t)set->ram_fifo_tx_evt >> 2)\r
+ | MCAN_TXEFC_EFS(cfg->fifo_size_tx_evt)\r
+ | MCAN_TXEFC_EFWM(0);\r
+ /* Tx Buffers */\r
+ mcan->MCAN_TXBC =\r
+ MCAN_TXBC_TBSA((uint32_t)set->ram_array_tx >> 2)\r
+ | MCAN_TXBC_NDTB(cfg->array_size_tx)\r
+ | MCAN_TXBC_TFQS(cfg->fifo_size_tx)\r
+ | 0; /* clear MCAN_TXBC_TFQM */\r
+\r
+ /* Configure the size of data fields in Rx and Tx Buffer Elements */\r
+ if (!get_length_code(cfg->buf_size_rx_fifo0, &dlc))\r
+ return false;\r
+ regVal32 = MCAN_RXESC_F0DS(dlc < CAN_DLC_8 ? 0 : dlc - CAN_DLC_8);\r
+ if (!get_length_code(cfg->buf_size_rx_fifo1, &dlc))\r
+ return false;\r
+ regVal32 |= MCAN_RXESC_F1DS(dlc < CAN_DLC_8 ? 0 : dlc - CAN_DLC_8);\r
+ if (!get_length_code(cfg->buf_size_rx, &dlc))\r
+ return false;\r
+ regVal32 |= MCAN_RXESC_RBDS(dlc < CAN_DLC_8 ? 0 : dlc - CAN_DLC_8);\r
+ mcan->MCAN_RXESC = regVal32;\r
+ if (!get_length_code(cfg->buf_size_tx, &dlc))\r
+ return false;\r
+ mcan->MCAN_TXESC =\r
+ MCAN_TXESC_TBDS(dlc < CAN_DLC_8 ? 0 : dlc - CAN_DLC_8);\r
+\r
+ /* Configure Message ID Filters\r
+ * ...Disable all standard filters */\r
+ for (element = set->ram_filt_std, elem_end = set->ram_filt_std\r
+ + (uint32_t)cfg->array_size_filt_std * MCAN_RAM_FILT_STD_SIZE;\r
+ element < elem_end;\r
+ element += MCAN_RAM_FILT_STD_SIZE)\r
+ element[0] = MCAN_RAM_FILT_SFEC_DIS;\r
+ /* ...Disable all extended filters */\r
+ for (element = set->ram_filt_ext, elem_end = set->ram_filt_ext\r
+ + (uint32_t)cfg->array_size_filt_ext * MCAN_RAM_FILT_EXT_SIZE;\r
+ element < elem_end;\r
+ element += MCAN_RAM_FILT_EXT_SIZE)\r
+ element[0] = MCAN_RAM_FILT_EFEC_DIS;\r
+\r
+ mcan->MCAN_NDAT1 = 0xFFFFFFFF; /* clear new (rx) data flags */\r
+ mcan->MCAN_NDAT2 = 0xFFFFFFFF; /* clear new (rx) data flags */\r
+\r
+ regVal32 = mcan->MCAN_CCCR & ~(MCAN_CCCR_BRSE | MCAN_CCCR_FDOE);\r
+ mcan->MCAN_CCCR = regVal32 | MCAN_CCCR_PXHD | MCAN_CCCR_BRSE_DISABLED\r
+ | MCAN_CCCR_FDOE_DISABLED;\r
+\r
+ DSB();\r
+ ISB();\r
+ return true;\r
+}\r
+\r
+void mcan_reconfigure(struct mcan_set *set)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ uint32_t regVal32;\r
+\r
+ regVal32 = mcan->MCAN_CCCR & ~MCAN_CCCR_CCE;\r
+ assert((regVal32 & MCAN_CCCR_INIT) == MCAN_CCCR_INIT_ENABLED);\r
+ /* Enable writing to configuration registers */\r
+ mcan->MCAN_CCCR = regVal32 | MCAN_CCCR_CCE_CONFIGURABLE;\r
+}\r
+\r
+void mcan_set_mode(struct mcan_set *set, enum mcan_can_mode mode)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ uint32_t regVal32;\r
+\r
+ regVal32 = mcan->MCAN_CCCR & ~(MCAN_CCCR_BRSE | MCAN_CCCR_FDOE);\r
+ switch (mode) {\r
+ case MCAN_MODE_CAN:\r
+ regVal32 |= MCAN_CCCR_BRSE_DISABLED | MCAN_CCCR_FDOE_DISABLED;\r
+ break;\r
+ case MCAN_MODE_EXT_LEN_CONST_RATE:\r
+ regVal32 |= MCAN_CCCR_BRSE_DISABLED | MCAN_CCCR_FDOE_ENABLED;\r
+ break;\r
+ case MCAN_MODE_EXT_LEN_DUAL_RATE:\r
+ regVal32 |= MCAN_CCCR_BRSE_ENABLED | MCAN_CCCR_FDOE_ENABLED;\r
+ break;\r
+ default:\r
+ return;\r
+ }\r
+ mcan->MCAN_CCCR = regVal32;\r
+}\r
+\r
+enum mcan_can_mode mcan_get_mode(const struct mcan_set *set)\r
+{\r
+ const uint32_t cccr = set->cfg.regs->MCAN_CCCR;\r
+\r
+ if ((cccr & MCAN_CCCR_FDOE) == MCAN_CCCR_FDOE_DISABLED)\r
+ return MCAN_MODE_CAN;\r
+ if ((cccr & MCAN_CCCR_BRSE) == MCAN_CCCR_BRSE_DISABLED)\r
+ return MCAN_MODE_EXT_LEN_CONST_RATE;\r
+ return MCAN_MODE_EXT_LEN_DUAL_RATE;\r
+}\r
+\r
+void mcan_init_loopback(struct mcan_set *set)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+\r
+ mcan->MCAN_CCCR |= MCAN_CCCR_TEST_ENABLED;\r
+#if 0\r
+ mcan->MCAN_CCCR |= MCAN_CCCR_MON_ENABLED; /* for internal loop back */\r
+#endif\r
+ mcan->MCAN_TEST |= MCAN_TEST_LBCK_ENABLED;\r
+}\r
+\r
+void mcan_set_tx_queue_mode(struct mcan_set *set)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ mcan->MCAN_TXBC |= MCAN_TXBC_TFQM;\r
+}\r
+\r
+void mcan_enable(struct mcan_set *set)\r
+{\r
+ uint32_t index, val;\r
+\r
+ /* Depending on bus condition, the HW may switch back to the\r
+ * Initialization state, by itself. Therefore, upon timeout, return.\r
+ * [Using an arbitrary timeout criterion.] */\r
+ for (index = 0; index < 1024; index++) {\r
+ val = set->cfg.regs->MCAN_CCCR;\r
+ if ((val & MCAN_CCCR_INIT) == MCAN_CCCR_INIT_DISABLED)\r
+ break;\r
+ if (index == 0)\r
+ set->cfg.regs->MCAN_CCCR = (val & ~MCAN_CCCR_INIT)\r
+ | MCAN_CCCR_INIT_DISABLED;\r
+ }\r
+}\r
+\r
+void mcan_disable(struct mcan_set *set)\r
+{\r
+ uint32_t val;\r
+ bool initial;\r
+\r
+ for (initial = true; true; initial = false) {\r
+ val = set->cfg.regs->MCAN_CCCR;\r
+ if ((val & MCAN_CCCR_INIT) == MCAN_CCCR_INIT_ENABLED)\r
+ break;\r
+ if (initial)\r
+ set->cfg.regs->MCAN_CCCR = (val & ~MCAN_CCCR_INIT)\r
+ | MCAN_CCCR_INIT_ENABLED;\r
+ }\r
+}\r
+\r
+void mcan_loopback_on(struct mcan_set *set)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ mcan->MCAN_TEST |= MCAN_TEST_LBCK_ENABLED;\r
+}\r
+\r
+void mcan_loopback_off(struct mcan_set *set)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ mcan->MCAN_TEST &= ~MCAN_TEST_LBCK_ENABLED;\r
+}\r
+\r
+void mcan_enable_rx_array_flag(struct mcan_set *set, uint8_t line)\r
+{\r
+ assert(line == 0 || line == 1);\r
+\r
+ Mcan *mcan = set->cfg.regs;\r
+ if (line) {\r
+ mcan->MCAN_ILS |= MCAN_ILS_DRXL;\r
+ mcan->MCAN_ILE |= MCAN_ILE_EINT1;\r
+ } else {\r
+ mcan->MCAN_ILS &= ~MCAN_ILS_DRXL;\r
+ mcan->MCAN_ILE |= MCAN_ILE_EINT0;\r
+ }\r
+ mcan->MCAN_IR = MCAN_IR_DRX; /* clear previous flag */\r
+ mcan->MCAN_IE |= MCAN_IE_DRXE; /* enable it */\r
+}\r
+\r
+uint8_t * mcan_prepare_tx_buffer(struct mcan_set *set, uint8_t buf_idx,\r
+ uint32_t id, uint8_t len)\r
+{\r
+ assert(buf_idx < set->cfg.array_size_tx);\r
+ assert(len <= set->cfg.buf_size_tx);\r
+\r
+ Mcan *mcan = set->cfg.regs;\r
+ uint32_t *pThisTxBuf = 0;\r
+ uint32_t val;\r
+ const enum mcan_can_mode mode = mcan_get_mode(set);\r
+ enum mcan_dlc dlc;\r
+\r
+ if (buf_idx >= set->cfg.array_size_tx)\r
+ return NULL;\r
+ if (!get_length_code(len, &dlc))\r
+ dlc = CAN_DLC_0;\r
+ pThisTxBuf = set->ram_array_tx + buf_idx\r
+ * (MCAN_RAM_BUF_HDR_SIZE + set->cfg.buf_size_tx / 4);\r
+ if (mcan_is_extended_id(id))\r
+ *pThisTxBuf++ = MCAN_RAM_BUF_XTD | MCAN_RAM_BUF_ID_XTD(id);\r
+ else\r
+ *pThisTxBuf++ = MCAN_RAM_BUF_ID_STD(id);\r
+ val = MCAN_RAM_BUF_MM(0) | MCAN_RAM_BUF_DLC((uint32_t)dlc);\r
+ if (mode == MCAN_MODE_EXT_LEN_CONST_RATE)\r
+ val |= MCAN_RAM_BUF_FDF;\r
+ else if (mode == MCAN_MODE_EXT_LEN_DUAL_RATE)\r
+ val |= MCAN_RAM_BUF_FDF | MCAN_RAM_BUF_BRS;\r
+ *pThisTxBuf++ = val;\r
+ /* enable transmit from buffer to set TC interrupt bit in IR,\r
+ * but interrupt will not happen unless TC interrupt is enabled */\r
+ mcan->MCAN_TXBTIE = (1 << buf_idx);\r
+ return (uint8_t *)pThisTxBuf; /* now it points to the data field */\r
+}\r
+\r
+void mcan_send_tx_buffer(struct mcan_set *set, uint8_t buf_idx)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+\r
+ if (buf_idx < set->cfg.array_size_tx)\r
+ mcan->MCAN_TXBAR = (1 << buf_idx);\r
+}\r
+\r
+uint8_t mcan_enqueue_outgoing_msg(struct mcan_set *set, uint32_t id,\r
+ uint8_t len, const uint8_t *data)\r
+{\r
+ assert(len <= set->cfg.buf_size_tx);\r
+\r
+ Mcan *mcan = set->cfg.regs;\r
+ uint32_t val;\r
+ uint32_t *pThisTxBuf = 0;\r
+ const enum mcan_can_mode mode = mcan_get_mode(set);\r
+ enum mcan_dlc dlc;\r
+ uint8_t putIdx = 255;\r
+\r
+ if (!get_length_code(len, &dlc))\r
+ dlc = CAN_DLC_0;\r
+ /* Configured for FifoQ and FifoQ not full? */\r
+ if (set->cfg.fifo_size_tx == 0 || (mcan->MCAN_TXFQS & MCAN_TXFQS_TFQF))\r
+ return putIdx;\r
+ putIdx = (uint8_t)((mcan->MCAN_TXFQS & MCAN_TXFQS_TFQPI_Msk)\r
+ >> MCAN_TXFQS_TFQPI_Pos);\r
+ pThisTxBuf = set->ram_array_tx + (uint32_t)\r
+ putIdx * (MCAN_RAM_BUF_HDR_SIZE + set->cfg.buf_size_tx / 4);\r
+ if (mcan_is_extended_id(id))\r
+ *pThisTxBuf++ = MCAN_RAM_BUF_XTD | MCAN_RAM_BUF_ID_XTD(id);\r
+ else\r
+ *pThisTxBuf++ = MCAN_RAM_BUF_ID_STD(id);\r
+ val = MCAN_RAM_BUF_MM(0) | MCAN_RAM_BUF_DLC((uint32_t)dlc);\r
+ if (mode == MCAN_MODE_EXT_LEN_CONST_RATE)\r
+ val |= MCAN_RAM_BUF_FDF;\r
+ else if (mode == MCAN_MODE_EXT_LEN_DUAL_RATE)\r
+ val |= MCAN_RAM_BUF_FDF | MCAN_RAM_BUF_BRS;\r
+ *pThisTxBuf++ = val;\r
+ memcpy(pThisTxBuf, data, len);\r
+ /* enable transmit from buffer to set TC interrupt bit in IR,\r
+ * but interrupt will not happen unless TC interrupt is enabled\r
+ */\r
+ mcan->MCAN_TXBTIE = (1 << putIdx);\r
+ /* request to send */\r
+ mcan->MCAN_TXBAR = (1 << putIdx);\r
+ return putIdx;\r
+}\r
+\r
+bool mcan_is_buffer_sent(const struct mcan_set *set, uint8_t buf_idx)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ return mcan->MCAN_TXBTO & (1 << buf_idx) ? true : false;\r
+}\r
+\r
+void mcan_filter_single_id(struct mcan_set *set,\r
+ uint8_t buf_idx, uint8_t filter, uint32_t id)\r
+{\r
+ assert(buf_idx < set->cfg.array_size_rx);\r
+ assert(id & CAN_EXT_MSG_ID ? filter < set->cfg.array_size_filt_ext\r
+ : filter < set->cfg.array_size_filt_std);\r
+ assert(id & CAN_EXT_MSG_ID ? (id & ~CAN_EXT_MSG_ID) <= 0x1fffffff :\r
+ id <= 0x7ff);\r
+\r
+ uint32_t *pThisRxFilt = 0;\r
+\r
+ if (buf_idx >= set->cfg.array_size_rx)\r
+ return;\r
+ if (mcan_is_extended_id(id)) {\r
+ pThisRxFilt = set->ram_filt_ext + filter\r
+ * MCAN_RAM_FILT_EXT_SIZE;\r
+ *pThisRxFilt++ = MCAN_RAM_FILT_EFEC_BUF\r
+ | MCAN_RAM_FILT_EFID1(id);\r
+ *pThisRxFilt = MCAN_RAM_FILT_EFID2_BUF\r
+ | MCAN_RAM_FILT_EFID2_BUF_IDX(buf_idx);\r
+ } else {\r
+ pThisRxFilt = set->ram_filt_std + filter\r
+ * MCAN_RAM_FILT_STD_SIZE;\r
+ *pThisRxFilt = MCAN_RAM_FILT_SFEC_BUF\r
+ | MCAN_RAM_FILT_SFID1(id)\r
+ | MCAN_RAM_FILT_SFID2_BUF\r
+ | MCAN_RAM_FILT_SFID2_BUF_IDX(buf_idx);\r
+ }\r
+}\r
+\r
+void mcan_filter_id_mask(struct mcan_set *set, uint8_t fifo, uint8_t filter,\r
+ uint32_t id, uint32_t mask)\r
+{\r
+ assert(fifo == 0 || fifo == 1);\r
+ assert(id & CAN_EXT_MSG_ID ? filter < set->cfg.array_size_filt_ext\r
+ : filter < set->cfg.array_size_filt_std);\r
+ assert(id & CAN_EXT_MSG_ID ? (id & ~CAN_EXT_MSG_ID) <= 0x1fffffff :\r
+ id <= 0x7ff);\r
+ assert(id & CAN_EXT_MSG_ID ? mask <= 0x1fffffff : mask <= 0x7ff);\r
+\r
+ uint32_t *pThisRxFilt = 0;\r
+ uint32_t val;\r
+\r
+ if (mcan_is_extended_id(id)) {\r
+ pThisRxFilt = set->ram_filt_ext + filter\r
+ * MCAN_RAM_FILT_EXT_SIZE;\r
+ *pThisRxFilt++ = (fifo ? MCAN_RAM_FILT_EFEC_FIFO1\r
+ : MCAN_RAM_FILT_EFEC_FIFO0) | MCAN_RAM_FILT_EFID1(id);\r
+ *pThisRxFilt = MCAN_RAM_FILT_EFT_CLASSIC\r
+ | MCAN_RAM_FILT_EFID2(mask);\r
+ } else {\r
+ pThisRxFilt = set->ram_filt_std + filter\r
+ * MCAN_RAM_FILT_STD_SIZE;\r
+ val = MCAN_RAM_FILT_SFT_CLASSIC\r
+ | MCAN_RAM_FILT_SFID1(id)\r
+ | MCAN_RAM_FILT_SFID2(mask);\r
+ *pThisRxFilt = (fifo ? MCAN_RAM_FILT_SFEC_FIFO1\r
+ : MCAN_RAM_FILT_SFEC_FIFO0) | val;\r
+ }\r
+}\r
+\r
+bool mcan_rx_buffer_data(const struct mcan_set *set, uint8_t buf_idx)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+\r
+ if (buf_idx < 32)\r
+ return mcan->MCAN_NDAT1 & (1 << buf_idx) ? true : false;\r
+ else if (buf_idx < 64)\r
+ return mcan->MCAN_NDAT2 & (1 << (buf_idx - 32)) ? true : false;\r
+ else\r
+ return false;\r
+}\r
+\r
+void mcan_read_rx_buffer(struct mcan_set *set, uint8_t buf_idx,\r
+ struct mcan_msg_info *msg)\r
+{\r
+ assert(buf_idx < set->cfg.array_size_rx);\r
+\r
+ Mcan *mcan = set->cfg.regs;\r
+ const uint32_t *pThisRxBuf = 0;\r
+ uint32_t tempRy; /* temp copy of RX buffer word */\r
+ uint8_t len;\r
+\r
+ if (buf_idx >= set->cfg.array_size_rx) {\r
+ msg->id = 0;\r
+ msg->timestamp = 0;\r
+ msg->full_len = 0;\r
+ msg->data_len = 0;\r
+ return;\r
+ }\r
+ pThisRxBuf = set->ram_array_rx + (buf_idx\r
+ * (MCAN_RAM_BUF_HDR_SIZE + set->cfg.buf_size_rx / 4));\r
+ tempRy = *pThisRxBuf++; /* word R0 contains ID */\r
+ if (tempRy & MCAN_RAM_BUF_XTD)\r
+ msg->id = CAN_EXT_MSG_ID | (tempRy & MCAN_RAM_BUF_ID_XTD_Msk)\r
+ >> MCAN_RAM_BUF_ID_XTD_Pos;\r
+ else\r
+ msg->id = (tempRy & MCAN_RAM_BUF_ID_STD_Msk)\r
+ >> MCAN_RAM_BUF_ID_STD_Pos;\r
+ tempRy = *pThisRxBuf++; /* word R1 contains DLC & time stamp */\r
+ msg->full_len = len = get_data_length((enum mcan_dlc)\r
+ ((tempRy & MCAN_RAM_BUF_DLC_Msk) >> MCAN_RAM_BUF_DLC_Pos));\r
+ msg->timestamp = (tempRy & MCAN_RAM_BUF_RXTS_Msk)\r
+ >> MCAN_RAM_BUF_RXTS_Pos;\r
+ if (msg->data) {\r
+ /* copy the data from the Rx Buffer Element to the\r
+ * application-owned buffer */\r
+ if (len > set->cfg.buf_size_rx)\r
+ len = set->cfg.buf_size_rx;\r
+ if (len > msg->data_len)\r
+ len = msg->data_len;\r
+ memcpy(msg->data, pThisRxBuf, len);\r
+ msg->data_len = len;\r
+ }\r
+ else\r
+ msg->data_len = 0;\r
+ /* clear the new data flag for the buffer */\r
+ if (buf_idx < 32)\r
+ mcan->MCAN_NDAT1 = (1 << buf_idx);\r
+ else\r
+ mcan->MCAN_NDAT2 = (1 << (buf_idx - 32));\r
+}\r
+\r
+uint8_t mcan_dequeue_received_msg(struct mcan_set *set, uint8_t fifo,\r
+ struct mcan_msg_info *msg)\r
+{\r
+ assert(fifo == 0 || fifo == 1);\r
+\r
+ Mcan *mcan = set->cfg.regs;\r
+ uint32_t *pThisRxBuf = 0;\r
+ uint32_t tempRy; /* temp copy of RX buffer word */\r
+ uint8_t buf_elem_data_size, len;\r
+ uint32_t *fifo_ack_reg;\r
+ uint32_t get_index;\r
+ uint8_t fill_level = 0; /* default: fifo empty */\r
+\r
+ if (fifo) {\r
+ get_index = (mcan->MCAN_RXF1S & MCAN_RXF1S_F1GI_Msk) >>\r
+ MCAN_RXF1S_F1GI_Pos;\r
+ fill_level = (uint8_t)((mcan->MCAN_RXF1S & MCAN_RXF1S_F1FL_Msk)\r
+ >> MCAN_RXF1S_F1FL_Pos);\r
+ pThisRxBuf = set->ram_fifo_rx1;\r
+ buf_elem_data_size = set->cfg.buf_size_rx_fifo1;\r
+ fifo_ack_reg = (uint32_t *) & mcan->MCAN_RXF1A;\r
+ } else {\r
+ get_index = (mcan->MCAN_RXF0S & MCAN_RXF0S_F0GI_Msk)\r
+ >> MCAN_RXF0S_F0GI_Pos;\r
+ fill_level = (uint8_t)((mcan->MCAN_RXF0S & MCAN_RXF0S_F0FL_Msk)\r
+ >> MCAN_RXF0S_F0FL_Pos);\r
+ pThisRxBuf = set->ram_fifo_rx0;\r
+ buf_elem_data_size = set->cfg.buf_size_rx_fifo0;\r
+ fifo_ack_reg = (uint32_t *) & mcan->MCAN_RXF0A;\r
+ }\r
+\r
+ if (fill_level == 0)\r
+ return 0;\r
+\r
+ pThisRxBuf += get_index * (MCAN_RAM_BUF_HDR_SIZE + buf_elem_data_size\r
+ / 4);\r
+ tempRy = *pThisRxBuf++; /* word R0 contains ID */\r
+ if (tempRy & MCAN_RAM_BUF_XTD)\r
+ msg->id = CAN_EXT_MSG_ID | (tempRy & MCAN_RAM_BUF_ID_XTD_Msk)\r
+ >> MCAN_RAM_BUF_ID_XTD_Pos;\r
+ else\r
+ msg->id = (tempRy & MCAN_RAM_BUF_ID_STD_Msk)\r
+ >> MCAN_RAM_BUF_ID_STD_Pos;\r
+ tempRy = *pThisRxBuf++; /* word R1 contains DLC & timestamps */\r
+ msg->full_len = len = get_data_length((enum mcan_dlc)\r
+ ((tempRy & MCAN_RAM_BUF_DLC_Msk) >> MCAN_RAM_BUF_DLC_Pos));\r
+ msg->timestamp = (tempRy & MCAN_RAM_BUF_RXTS_Msk)\r
+ >> MCAN_RAM_BUF_RXTS_Pos;\r
+ if (msg->data) {\r
+ /* copy the data from the Rx Buffer Element to the\r
+ * application-owned buffer */\r
+ if (len > buf_elem_data_size)\r
+ len = buf_elem_data_size;\r
+ if (len > msg->data_len)\r
+ len = msg->data_len;\r
+ memcpy(msg->data, pThisRxBuf, len);\r
+ msg->data_len = len;\r
+ }\r
+ else\r
+ msg->data_len = 0;\r
+ /* acknowledge reading the fifo entry */\r
+ *fifo_ack_reg = get_index;\r
+ /* return entries remaining in FIFO */\r
+ return (fill_level);\r
+}\r
+\r
+/**@}*/\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Controller Area Network with Flexible Data-rate.\r
+ * Interface for configuring and using the MCAN peripheral.\r
+ */\r
+\r
+#ifndef _MCAN_H_\r
+#define _MCAN_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <assert.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+enum mcan_can_mode\r
+{\r
+ /* ISO 11898-1 CAN mode */\r
+ MCAN_MODE_CAN,\r
+\r
+ /* Long CAN FD frame.\r
+ * - TX and RX payloads up to 64 bytes.\r
+ * - Slow transmitter: TX frames are sent at constant bit rate.\r
+ * - Fast receiver: both constant-rate (slow) and dual-rate (fast)\r
+ * RX frames are supported and received. */\r
+ MCAN_MODE_EXT_LEN_CONST_RATE,\r
+\r
+ /* Long and fast CAN FD frame.\r
+ * - TX and RX payloads up to 64 bytes.\r
+ * - Fast transmitter: control, data and CRC fields are transmitted at a\r
+ * higher bit rate.\r
+ * - Fast receiver. */\r
+ MCAN_MODE_EXT_LEN_DUAL_RATE,\r
+};\r
+\r
+/* Flag signalling a standard (11-bit) message identifiers */\r
+#define CAN_STD_MSG_ID (0x0u << 30)\r
+/* Flag to be bitwise or'ed to extended (29-bit) message identifiers */\r
+#define CAN_EXT_MSG_ID (0x1u << 30)\r
+\r
+struct mcan_msg_info\r
+{\r
+ uint32_t id;\r
+ uint32_t timestamp;\r
+ uint8_t *data;\r
+ uint8_t full_len;\r
+ uint8_t data_len;\r
+};\r
+\r
+struct mcan_config\r
+{\r
+ uint32_t id; /* peripheral ID (ID_xxx) */\r
+ Mcan *regs; /* set of MCAN hardware registers */\r
+ uint32_t *msg_ram; /* base address of the Message RAM to be\r
+ * assigned to this MCAN instance */\r
+\r
+ uint8_t array_size_filt_std; /* # of 11-bit Message ID Rx Filters */\r
+ uint8_t array_size_filt_ext; /* # of 29-bit Message ID Rx Filters */\r
+ uint8_t fifo_size_rx0; /* # of Rx Buffers in Rx FIFO 0 */\r
+ uint8_t fifo_size_rx1; /* # of Rx Buffers in Rx FIFO 1 */\r
+ uint8_t array_size_rx; /* # of dedicated Rx Buffers */\r
+ uint8_t fifo_size_tx_evt; /* # of Tx Event Elements in the Tx Event\r
+ * FIFO */\r
+ uint8_t array_size_tx; /* # of dedicated Tx Buffers */\r
+ uint8_t fifo_size_tx; /* # of Tx Buffers in the Tx FIFO or Tx\r
+ * Queue */\r
+\r
+ uint8_t buf_size_rx_fifo0; /* size of the data field in each Rx\r
+ * Buffer of Rx FIFO 0, in bytes */\r
+ uint8_t buf_size_rx_fifo1; /* size of the data field in each Rx\r
+ * Buffer of Rx FIFO 1, in bytes */\r
+ uint8_t buf_size_rx; /* size of the data field in each\r
+ * dedicated Rx Buffer, in bytes */\r
+ uint8_t buf_size_tx; /* size of the data field in each Tx\r
+ * Buffer, in bytes. Applies to all Tx\r
+ * Buffers, dedicated and in Tx FIFO /\r
+ * Queue. */\r
+\r
+ uint32_t bit_rate; /* requested CAN bit rate in CAN mode,\r
+ * in bps */\r
+ uint16_t quanta_before_sp; /* duration of the time segment before the\r
+ * sample point (Sync_Seg + Prop_Seg +\r
+ * Phase_Seg1), while in CAN mode,\r
+ * expressed in CAN time quanta */\r
+ uint8_t quanta_after_sp; /* duration of the time segment after the\r
+ * sample point (Phase_Seg2), while in CAN\r
+ * mode, expressed in CAN time quanta */\r
+\r
+ uint32_t bit_rate_fd; /* requested CAN bit rate in fast CAN FD\r
+ * mode, in bps */\r
+ uint8_t quanta_before_sp_fd; /* duration of the time segment before the\r
+ * sample point (Sync_Seg + Prop_Seg +\r
+ * Phase_Seg1), while in fast CAN FD mode,\r
+ * expressed in CAN time quanta */\r
+ uint8_t quanta_after_sp_fd; /* duration of the time segment after the\r
+ * sample point (Phase_Seg2), while in\r
+ * fast CAN FD mode, expressed in CAN time\r
+ * quanta */\r
+\r
+ uint8_t quanta_sync_jump; /* duration of a (re)synchronization jump,\r
+ * while in CAN mode, expressed in CAN\r
+ * time quanta */\r
+ uint8_t quanta_sync_jump_fd; /* duration of a (re)synchronization jump,\r
+ * while in fast CAN FD mode, expressed in\r
+ * CAN time quanta */\r
+};\r
+\r
+/* This structure is private to the MCAN Driver.\r
+ * Allocate it but ignore its members. */\r
+struct mcan_set\r
+{\r
+ struct mcan_config cfg;\r
+ uint32_t *ram_filt_std;\r
+ uint32_t *ram_filt_ext;\r
+ uint32_t *ram_fifo_rx0;\r
+ uint32_t *ram_fifo_rx1;\r
+ uint32_t *ram_array_rx;\r
+ uint32_t *ram_fifo_tx_evt;\r
+ uint32_t *ram_array_tx;\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported symbols\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static inline bool mcan_is_enabled(const struct mcan_set *set)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ return ((mcan->MCAN_CCCR & MCAN_CCCR_INIT) == MCAN_CCCR_INIT_DISABLED);\r
+}\r
+\r
+static inline bool mcan_is_extended_id(uint32_t msg_id)\r
+{\r
+ return msg_id & CAN_EXT_MSG_ID ? true : false;\r
+}\r
+\r
+static inline uint32_t mcan_get_id(uint32_t msg_id)\r
+{\r
+ return msg_id & CAN_EXT_MSG_ID ? msg_id & 0x1fffffff : msg_id & 0x7ff;\r
+}\r
+\r
+static inline bool mcan_is_tx_complete(const struct mcan_set *set)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ return mcan->MCAN_IR & MCAN_IR_TC ? true : false;\r
+}\r
+\r
+static inline void mcan_clear_tx_flag(const struct mcan_set *set)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ mcan->MCAN_IR = MCAN_IR_TC;\r
+}\r
+\r
+static inline bool mcan_rx_array_data(const struct mcan_set *set)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ return mcan->MCAN_IR & MCAN_IR_DRX ? true : false;\r
+}\r
+\r
+static inline void mcan_clear_rx_array_flag(const struct mcan_set *set)\r
+{\r
+ Mcan *mcan = set->cfg.regs;\r
+ mcan->MCAN_IR = MCAN_IR_DRX;\r
+}\r
+\r
+static inline bool mcan_rx_fifo_data(const struct mcan_set *set, uint8_t fifo)\r
+{\r
+ assert(fifo == 0 || fifo == 1);\r
+\r
+ Mcan *mcan = set->cfg.regs;\r
+\r
+ return mcan->MCAN_IR & (fifo ? MCAN_IR_RF1N : MCAN_IR_RF0N) ? true\r
+ : false;\r
+}\r
+\r
+static inline void mcan_clear_rx_fifo_flag(const struct mcan_set *set,\r
+ uint8_t fifo)\r
+{\r
+ assert(fifo == 0 || fifo == 1);\r
+\r
+ Mcan *mcan = set->cfg.regs;\r
+\r
+ mcan->MCAN_IR = fifo ? MCAN_IR_RF1N : MCAN_IR_RF0N;\r
+}\r
+\r
+/**\r
+ * \brief Compute the size of the Message RAM to be assigned to the MCAN.\r
+ * \param cfg MCAN configuration to be considered. Only integer size parameters\r
+ * need to be configured. The other parameters can be left blank at this stage.\r
+ * \param size address where the required size of the Message RAM will be\r
+ * written, expressed in (32-bit) words.\r
+ * \return true if successful, false if a parameter is set to an unsupported\r
+ * value.\r
+ */\r
+bool mcan_configure_msg_ram(const struct mcan_config *cfg, uint32_t *size);\r
+\r
+/**\r
+ * \brief Initialize the MCAN hardware for the given peripheral.\r
+ * Default: Non-FD, ISO 11898-1 CAN mode; mixed mode TX Buffer + FIFO.\r
+ * \param set Pointer to uninitialized driver instance data.\r
+ * \param cfg MCAN configuration to be used.\r
+ * \return true if successful, false if a parameter is set to an unsupported\r
+ * value.\r
+ */\r
+bool mcan_initialize(struct mcan_set *set, const struct mcan_config *cfg);\r
+\r
+/**\r
+ * \brief Unlock the peripheral configuration so it can be altered.\r
+ * Prerequisite: the peripheral shall be disabled. In case the device has been\r
+ * enabled, call mcan_disable.\r
+ * \param set Pointer to driver instance data.\r
+ */\r
+void mcan_reconfigure(struct mcan_set *set);\r
+\r
+/**\r
+ * \brief Select either the legacy ISO 11898-1 CAN mode or the CAN-FD mode,\r
+ * along with the FD variant in the latter case.\r
+ * Should be called further to mcan_initialize() or mcan_reconfigure(), before\r
+ * mcan_enable().\r
+ * \param set Pointer to driver instance data.\r
+ * \param mode CAN mode, and FD variant in case of FD mode.\r
+ */\r
+void mcan_set_mode(struct mcan_set *set, enum mcan_can_mode mode);\r
+\r
+/**\r
+ * \brief Query the current CAN mode.\r
+ * \param set Pointer to driver instance data.\r
+ * \return Currently selected CAN mode, and FD variant in case of CAN FD mode.\r
+ */\r
+enum mcan_can_mode mcan_get_mode(const struct mcan_set *set);\r
+\r
+/**\r
+ * \brief Select the TX Queue mode, disable TX FIFO mode.\r
+ * INIT must be set - so this should be called between mcan_initialize() and\r
+ * mcan_enable().\r
+ * \param set Pointer to driver instance data.\r
+ */\r
+void mcan_set_tx_queue_mode(struct mcan_set *set);\r
+\r
+/**\r
+ * \brief Initialize the MCAN in loop back mode.\r
+ * INIT must be set - so this should be called between mcan_initialize() and\r
+ * mcan_enable().\r
+ * \param set Pointer to driver instance data.\r
+ */\r
+void mcan_init_loopback(struct mcan_set *set);\r
+\r
+/**\r
+ * \brief Enable the peripheral I/O stage. Synchronize with the bus.\r
+ * INIT must be set - so this should be called after mcan_initialize().\r
+ * \param set Pointer to driver instance data.\r
+ */\r
+void mcan_enable(struct mcan_set *set);\r
+\r
+/**\r
+ * \brief Disable the peripheral I/O stage. Go Bus_Off.\r
+ * \note Subsequent operations may include reconfiguring the peripheral\r
+ * (mcan_reconfigure) and/or re-enabling it (mcan_enable).\r
+ * \param set Pointer to driver instance data.\r
+ */\r
+void mcan_disable(struct mcan_set *set);\r
+\r
+/**\r
+ * \brief Turn the loop-back mode ON.\r
+ * \note TEST must be set in MCAN_CCCR. This mode should have been enabled upon\r
+ * initialization.\r
+ * \param set Pointer to driver instance data.\r
+ */\r
+void mcan_loopback_on(struct mcan_set *set);\r
+\r
+/**\r
+ * \brief Turn the loop-back mode OFF.\r
+ * \param set Pointer to driver instance data.\r
+ */\r
+void mcan_loopback_off(struct mcan_set *set);\r
+\r
+/**\r
+ * \brief Select either the m_can_int0 or the m_can_int1 interrupt line.\r
+ * Also, enable the 'Message stored to Dedicated Receive Buffer' specific\r
+ * interrupt.\r
+ * \param set Pointer to driver instance data.\r
+ * \param int_line The interrupt line to be enabled:\r
+ * 0 -> m_can_int0\r
+ * 1 -> m_can_int1.\r
+ */\r
+void mcan_enable_rx_array_flag(struct mcan_set *set, uint8_t int_line);\r
+\r
+/**\r
+ * \brief Configure a Dedicated TX Buffer.\r
+ * \param set Pointer to driver instance data.\r
+ * \param buf_idx Index of the dedicated transmit buffer to be used.\r
+ * \param id Message ID.\r
+ * \param len Data length, in bytes.\r
+ * \return Address of data byte 0, part of the transmit buffer.\r
+ */\r
+uint8_t * mcan_prepare_tx_buffer(struct mcan_set *set, uint8_t buf_idx,\r
+ uint32_t id, uint8_t len);\r
+\r
+/**\r
+ * \brief Start the transmission of a Dedicated TX Buffer.\r
+ * \param set Pointer to driver instance data.\r
+ * \param buf_idx Index of the dedicated transmit buffer to be used.\r
+ */\r
+void mcan_send_tx_buffer(struct mcan_set *set, uint8_t buf_idx);\r
+\r
+/**\r
+ * \brief Append the provided message to the TX FIFO, or to the TX Queue,\r
+ * depending on whether mcan_set_tx_queue_mode() has been invoked or not.\r
+ * \param set Pointer to driver instance data.\r
+ * \param id Message ID.\r
+ * \param len Data length, in bytes.\r
+ * \param data Pointer to data.\r
+ * \return Index of the assigned transmit buffer, part of the FIFO / queue.\r
+ * Or 0xff if the TX FIFO / queue was full, or an error occurred.\r
+ */\r
+uint8_t mcan_enqueue_outgoing_msg(struct mcan_set *set, uint32_t id,\r
+ uint8_t len, const uint8_t *data);\r
+\r
+/**\r
+ * \brief Check if message transmitted from the specified TX Buffer, either\r
+ * dedicated or part of the TX FIFO or TX Queue.\r
+ * \param set Pointer to driver instance data.\r
+ * \param buf_idx Index of the transmit buffer to be queried.\r
+ * \return true if the message has been successfully transmitted, false\r
+ * otherwise.\r
+ */\r
+bool mcan_is_buffer_sent(const struct mcan_set *set, uint8_t buf_idx);\r
+\r
+/**\r
+ * \brief Configure RX buffer filter.\r
+ * \param set Pointer to driver instance data.\r
+ * \param buf_idx Index of the receive buffer to be used as the recipient.\r
+ * \param filter Index of the filter to be configured.\r
+ * \param id Single message identifier. Incoming message need to match exactly\r
+ * to be accepted.\r
+ */\r
+void mcan_filter_single_id(struct mcan_set *set, uint8_t buf_idx,\r
+ uint8_t filter, uint32_t id);\r
+\r
+/**\r
+ * \brief Configure classic RX filter.\r
+ * The classic filters direct the accepted messages to a FIFO, and include both\r
+ * an ID and an ID mask.\r
+ * \param set Pointer to driver instance data.\r
+ * \param fifo Index of the RX FIFO to be used as the recipient.\r
+ * \param filter Index of the filter to be configured.\r
+ * \param id Message identifier.\r
+ * \param mask Message identifier mask to be matched.\r
+ */\r
+void mcan_filter_id_mask(struct mcan_set *set, uint8_t fifo, uint8_t filter,\r
+ uint32_t id, uint32_t mask);\r
+\r
+/**\r
+ * \brief Check whether some data has been received into the specified RX\r
+ * Buffer.\r
+ * \param set Pointer to driver instance data.\r
+ * \param buf_idx Index of the receive buffer to be queried.\r
+ * \return true if the receive buffer is flagged as containing an unfetched\r
+ * frame, and false otherwise.\r
+ */\r
+bool mcan_rx_buffer_data(const struct mcan_set *set, uint8_t buf_idx);\r
+\r
+/**\r
+ * \brief Get RX buffer.\r
+ * \param set Pointer to driver instance data.\r
+ * \param buf_idx Index of the receive buffer to be read.\r
+ * \param msg Address where the CAN message properties will be written.\r
+ * The msg->data and msg->data_len parameters shall be initialized prior to\r
+ * calling this function. Message contents will be copied to msg->data if\r
+ * msg->data is not null and if msg->data_len is large enough.\r
+ */\r
+void mcan_read_rx_buffer(struct mcan_set *set, uint8_t buf_idx,\r
+ struct mcan_msg_info *msg);\r
+\r
+/**\r
+ * \brief Detach one received message from the specified RX FIFO, and copy it to\r
+ * a buffer owned by the application.\r
+ * \param set Pointer to driver instance data.\r
+ * \param fifo Index of the RX FIFO to dequeue from.\r
+ * \param msg Address where the CAN message properties will be written.\r
+ * The msg->data and msg->data_len parameters shall be initialized prior to\r
+ * calling this function. Message contents will be copied to msg->data if\r
+ * msg->data is not null and if msg->data_len is large enough.\r
+ * \return: # of FIFO entries at the time the function was entered:\r
+ * 0 -> The FIFO was initially empty.\r
+ * 1 -> The FIFO had 1 entry upon entry, but is empty upon exit.\r
+ * 2 to 64 -> The FIFO had several entries upon entry, and still holds one\r
+ * or more entries upon exit.\r
+ */\r
+uint8_t mcan_dequeue_received_msg(struct mcan_set *set, uint8_t fifo,\r
+ struct mcan_msg_info *msg);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _MCAN_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#include "chip.h"\r
+#include "peripherals/mpddrc.h"\r
+#include "peripherals/sfrbu.h"\r
+#include "peripherals/pmc.h"\r
+#include "trace.h"\r
+#include "timer.h"\r
+#include "compiler.h"\r
+#include <stdlib.h>\r
+\r
+static void _set_ddr_timings(struct _mpddrc_desc* desc)\r
+{\r
+ MPDDRC->MPDDRC_TPR0 = desc->tpr0;\r
+ MPDDRC->MPDDRC_TPR1 = desc->tpr1;\r
+ MPDDRC->MPDDRC_TPR2 = desc->tpr2;\r
+}\r
+\r
+static uint32_t _compute_ba_offset(void)\r
+{\r
+ /* Compute BA[] offset according to CR configuration */\r
+ uint32_t offset = (MPDDRC->MPDDRC_CR & MPDDRC_CR_NC_Msk) + 9;\r
+ if (!(MPDDRC->MPDDRC_CR & MPDDRC_CR_DECOD_INTERLEAVED))\r
+ offset += ((MPDDRC->MPDDRC_CR & MPDDRC_CR_NR_Msk) >> 2) + 11;\r
+\r
+ offset += (MPDDRC->MPDDRC_MD & MPDDRC_MD_DBW) ? 1 : 2;\r
+\r
+ return offset;\r
+}\r
+\r
+/**\r
+ * \brief Send a NOP command\r
+ */\r
+static void _send_nop_cmd(void)\r
+{\r
+ MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD;\r
+ /* Perform a write to a DDR memory access to acknoledge the command */\r
+ *((uint32_t *)DDR_CS_ADDR) = 0;\r
+}\r
+\r
+static void _send_lmr_cmd(void)\r
+{\r
+ MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;\r
+ /* Perform a write to a DDR memory access to acknoledge the command */\r
+ *((uint32_t *)DDR_CS_ADDR) = 0u;\r
+}\r
+\r
+static void _send_ext_lmr_cmd(uint32_t opcode, uint32_t ba_offset)\r
+{\r
+ MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD;\r
+ /* Perform a write to a DDR memory access to acknoledge the command */\r
+ *((uint32_t *)(DDR_CS_ADDR + (opcode << ba_offset))) = 0u;\r
+}\r
+\r
+static void _send_normal_cmd(void)\r
+{\r
+ MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NORMAL_CMD;\r
+ /* Perform a write to a DDR memory access to acknoledge the command */\r
+ *((uint32_t *)DDR_CS_ADDR) = 0;\r
+}\r
+\r
+static void _send_precharge_cmd(void)\r
+{\r
+ MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD;\r
+ /* Perform a write to a DDR memory access to acknoledge the command */\r
+ *((uint32_t *)DDR_CS_ADDR) = 0;\r
+}\r
+\r
+static void _send_refresh_cmd(void)\r
+{\r
+ MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD;\r
+ /* Perform a write to a DDR memory access to acknoledge the command */\r
+ *((uint32_t *)DDR_CS_ADDR) = 0;\r
+}\r
+\r
+#ifdef CONFIG_HAVE_DDR3\r
+\r
+static void _send_calib_cmd(void)\r
+{\r
+ MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_DEEP_CALIB_MD;\r
+ /* Perform a write to a DDR memory access to acknoledge the command */\r
+ *((uint32_t *)DDR_CS_ADDR) = 0;\r
+}\r
+\r
+static void _configure_ddr3(struct _mpddrc_desc* desc)\r
+{\r
+ /* Timings */\r
+ _set_ddr_timings(desc);\r
+ uint32_t ba_offset = _compute_ba_offset();\r
+\r
+ /*\r
+ * Step 3: Issue a NOP command to the memory controller using\r
+ * its mode register (MPDDRC_MR).\r
+ */\r
+ _send_nop_cmd();\r
+\r
+ /*\r
+ * Step 4: A pause of at least 500us must be observed before a\r
+ * single toggle.\r
+ */\r
+ timer_sleep(50);\r
+ /*\r
+ * Step 5: Issue a NOP command to the memory controller using\r
+ * its mode register (MPDDRC_MR). CKE is now driven high.\r
+ */\r
+ _send_nop_cmd();\r
+ timer_sleep(1);\r
+ /*\r
+ * Step 6: Issue Extended Mode Register Set 2 (EMRS2) cycle to\r
+ * choose between commercial or high temperature\r
+ * operations.\r
+ */\r
+ _send_ext_lmr_cmd(0x2, ba_offset);\r
+ timer_sleep(1);\r
+ /*\r
+ * Step 7: Issue Extended Mode Register Set 3 (EMRS3) cycle to set\r
+ * the Extended Mode Register to 0.\r
+ */\r
+ _send_ext_lmr_cmd(0x3, ba_offset);\r
+ timer_sleep(1);\r
+ /*\r
+ * Step 8: Issue Extended Mode Register Set 1 (EMRS1) cycle to\r
+ * disable and to program O.D.S. (Output Driver Strength).\r
+ */\r
+ _send_ext_lmr_cmd(0x1, ba_offset);\r
+ timer_sleep(1);\r
+ /*\r
+ * Step 9: Write a one to the DLL bit (enable DLL reset) in the MPDDRC\r
+ * Configuration Register (MPDDRC_CR)\r
+ */\r
+ /* Not done for DDR3 */\r
+\r
+ /*\r
+ * Step 10: Issue a Mode Register Set (MRS) cycle to reset DLL.\r
+ */\r
+ _send_lmr_cmd();\r
+ timer_sleep(5);\r
+ /*\r
+ * Step 11: Issue a Calibration command (MRS) cycle to calibrate RTT and\r
+ * RON values for the Process Voltage Temperature (PVT).\r
+ */\r
+ _send_calib_cmd();\r
+ timer_sleep(1);\r
+\r
+ /*\r
+ * Step 12: A Normal Mode command is provided.\r
+ * Program the Normal mode in the MPDDRC_MR and perform a write access\r
+ * to any DDR3-SDRAM address to acknowledge this command.\r
+ */\r
+ _send_normal_cmd();\r
+ /*\r
+ * Step 13: Perform a write access to any DDR3-SDRAM address.\r
+ */\r
+ *((uint32_t *)(DDR_CS_ADDR)) = 0;\r
+}\r
+\r
+#endif\r
+\r
+static void _configure_ddr2(struct _mpddrc_desc* desc)\r
+{\r
+ /* Timings */\r
+ _set_ddr_timings(desc);\r
+ uint32_t ba_offset = _compute_ba_offset();\r
+\r
+ /* Step 3: An NOP command is issued to the DDR2-SDRAM. Program\r
+ * the NOP command into the Mode Register and wait minimum 200\r
+ * us */\r
+ _send_nop_cmd();\r
+ timer_sleep(20);\r
+\r
+ /* Step 4: Issue a NOP command. */\r
+ _send_nop_cmd();\r
+ timer_sleep(1);\r
+\r
+ /* Step 5: Issue all banks precharge command. */\r
+ _send_precharge_cmd();\r
+ timer_sleep(1);\r
+\r
+ /* Step 6: Issue an Extended Mode Register set (EMRS2) cycle\r
+ * to chose between commercialor high temperature\r
+ * operations. */\r
+ _send_ext_lmr_cmd(0x2, ba_offset);\r
+ timer_sleep(1);\r
+\r
+ /* Step 7: Issue an Extended Mode Register set (EMRS3) cycle\r
+ * to set all registers to 0. */\r
+ _send_ext_lmr_cmd(0x3, ba_offset);\r
+ timer_sleep(1);\r
+\r
+ /* Step 8: Issue an Extended Mode Register set (EMRS1) cycle\r
+ * to enable DLL. */\r
+ _send_ext_lmr_cmd(0x1, ba_offset);\r
+ timer_sleep(1);\r
+\r
+ /* Step 9: Program DLL field into the Configuration Register. */\r
+ MPDDRC->MPDDRC_CR |= MPDDRC_CR_DLL_RESET_ENABLED;\r
+\r
+ /* Step 10: A Mode Register set (MRS) cycle is issued to reset DLL. */\r
+ MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD;\r
+ /* Perform a write to a DDR memory access to acknoledge the command */\r
+ *((uint32_t *)DDR_CS_ADDR) = 0;\r
+\r
+ timer_sleep(1);\r
+\r
+ /* Step 11: Issue all banks precharge command to the DDR2-SDRAM. */\r
+ _send_precharge_cmd();\r
+ timer_sleep(1);\r
+\r
+ /* Step 12: Two auto-refresh (CBR) cycles are\r
+ * provided. Program the auto refresh command (CBR) into the\r
+ * Mode Register. */\r
+ _send_refresh_cmd();\r
+ timer_sleep(1);\r
+ _send_refresh_cmd();\r
+ timer_sleep(1);\r
+\r
+ /* Step 13: Program DLL field into the Configuration Register\r
+ * to low(Disable DLL reset). */\r
+ MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_DLL_RESET_ENABLED;\r
+\r
+ /* Step 14: Issue a Mode Register set (MRS) cycle to program\r
+ * the parameters of the DDR2-SDRAM devices. */\r
+ _send_lmr_cmd();\r
+ timer_sleep(1);\r
+\r
+ /* Step 15: Program OCD field into the Configuration Register\r
+ * to high (OCD calibration default). */\r
+ MPDDRC->MPDDRC_CR |= MPDDRC_CR_OCD_DDR2_DEFAULT_CALIB;\r
+\r
+ /* Step 16: An Extended Mode Register set (EMRS1) cycle is\r
+ * issued to OCD default value. */\r
+ _send_ext_lmr_cmd(0x1, ba_offset);\r
+ timer_sleep(1);\r
+\r
+ /* Step 19,20: A mode Normal command is provided. Program the\r
+ * Normal mode into Mode Register. */\r
+ _send_normal_cmd();\r
+ timer_sleep(1);\r
+}\r
+\r
+extern void mpddrc_configure(struct _mpddrc_desc* desc)\r
+{\r
+ /* Retrieve the current resolution to put it back later */\r
+ uint32_t resolution = timer_get_resolution();\r
+ /* Configure time to have 10 microseconds resolution */\r
+ timer_configure(10);\r
+\r
+ /* controller and DDR clock */\r
+ pmc_enable_peripheral(ID_MPDDRC);\r
+ pmc_enable_system_clock(PMC_SYSTEM_CLOCK_DDR);\r
+\r
+ /* Step1: Program memory device type */\r
+ MPDDRC->MPDDRC_MD = desc->mode;\r
+\r
+ /* set driver impedance */\r
+ uint32_t value = MPDDRC->MPDDRC_IO_CALIBR;\r
+ value &= ~MPDDRC_IO_CALIBR_RDIV_Msk;\r
+ value &= ~MPDDRC_IO_CALIBR_TZQIO_Msk;\r
+ value &= ~MPDDRC_IO_CALIBR_CALCODEP_Msk;\r
+ value &= ~MPDDRC_IO_CALIBR_CALCODEN_Msk;\r
+ value |= desc->io_calibr;\r
+ MPDDRC->MPDDRC_IO_CALIBR = value;\r
+\r
+ MPDDRC->MPDDRC_RD_DATA_PATH = desc->data_path;\r
+\r
+ /* Step 2: Program features of the DDR3-SDRAM device in the\r
+ * configuration register and timing parameter registers (TPR0\r
+ * ans TPR1) */\r
+\r
+ /* Configurations */\r
+ MPDDRC->MPDDRC_CR = desc->control;\r
+\r
+#ifdef CONFIG_HAVE_DDR3_SELFREFRESH\r
+ if (sfrbu_is_ddr_backup_enabled())\r
+ /* DDR memory had been initilized and in backup mode */\r
+ MPDDRC->MPDDRC_LPR =\r
+ MPDDRC_LPR_LPCB_SELFREFRESH |\r
+ MPDDRC_LPR_CLK_FR_ENABLED |\r
+ MPDDRC_LPR_PASR(0) |\r
+ MPDDRC_LPR_DS(2) |\r
+ MPDDRC_LPR_TIMEOUT_NONE |\r
+ MPDDRC_LPR_APDE_DDR2_FAST_EXIT |\r
+ MPDDRC_LPR_UPD_MR(0);\r
+ else\r
+ /* DDR memory is not in backup mode */\r
+ MPDDRC->MPDDRC_LPR =\r
+ MPDDRC_LPR_LPCB_SELFREFRESH |\r
+ MPDDRC_LPR_CLK_FR_ENABLED |\r
+ MPDDRC_LPR_PASR(0) |\r
+ MPDDRC_LPR_DS(2) |\r
+ MPDDRC_LPR_TIMEOUT_DELAY_128_CLK |\r
+ MPDDRC_LPR_APDE_DDR2_SLOW_EXIT |\r
+ MPDDRC_LPR_UPD_MR(0);\r
+#endif\r
+\r
+ switch(desc->type) {\r
+#ifdef CONFIG_HAVE_DDR3\r
+ case MPDDRC_TYPE_DDR3:\r
+#ifdef CONFIG_HAVE_DDR3_SELFREFRESH\r
+ _set_ddr_timings(desc);\r
+ /* Initialize DDR chip when needed */\r
+ if (!sfrbu_is_ddr_backup_enabled())\r
+#endif\r
+ _configure_ddr3(desc);\r
+ break;\r
+#endif\r
+ case MPDDRC_TYPE_DDR2:\r
+ _configure_ddr2(desc);\r
+ break;\r
+ default:\r
+ trace_error("Device not handled\r\n");\r
+ abort();\r
+ }\r
+\r
+ /* Last step: Write the refresh rate */\r
+ /* Refresh Timer is (64ms / (bank_size)) * master_clock */\r
+ uint32_t master_clock = pmc_get_master_clock()/1000000;\r
+ MPDDRC->MPDDRC_RTR = MPDDRC_RTR_COUNT(64000*master_clock/desc->bank);\r
+\r
+ /* wait for end of calibration */\r
+ timer_sleep(1);\r
+\r
+ /* Restore resolution or put the default one if not already set */\r
+ timer_configure(resolution);\r
+\r
+#ifdef CONFIG_HAVE_DDR3_SELFREFRESH\r
+ if (sfrbu_is_ddr_backup_enabled()) {\r
+ MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NORMAL_CMD;\r
+ sfrbu_disable_ddr_backup();\r
+ }\r
+#endif\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef MPDDRC_HEADER_\r
+#define MPDDRC_HEADER_\r
+\r
+#include <stdint.h>\r
+\r
+enum _ram_type {\r
+ MPDDRC_TYPE_DDR3,\r
+ MPDDRC_TYPE_LPDDR3,\r
+ MPDDRC_TYPE_DDR2,\r
+ MPDDRC_TYPE_LPDDR2,\r
+ MPDDRC_TYPE_DDR\r
+};\r
+\r
+struct _mpddrc_desc {\r
+ enum _ram_type type;\r
+ uint32_t io_calibr;\r
+ uint32_t data_path;\r
+ uint32_t mode;\r
+ uint32_t control;\r
+ uint32_t bank;\r
+ uint32_t tpr0;\r
+ uint32_t tpr1;\r
+ uint32_t tpr2;\r
+};\r
+\r
+extern void mpddrc_configure(struct _mpddrc_desc* desc);\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _PIO_H\r
+#define _PIO_H\r
+\r
+#define IRQ_PIO_HANDLERS_SIZE 16\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global Types\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+struct _pin\r
+{\r
+ uint8_t group; /*< The IO group containing the pins you want to use. */\r
+ uint32_t mask; /*< Bitmask indicating which pin(s) to configure. */\r
+ uint8_t type; /*< Pin type */\r
+ uint32_t attribute; /*< Pin config attribute. */\r
+};\r
+\r
+typedef void(*pio_handler_t)(uint32_t, uint32_t, void*);\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#if defined(CONFIG_HAVE_PIO4)\r
+#include "peripherals/pio4.h"\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures a list of Pin instances.\r
+ *\r
+ * \details Each of them can either hold a single pin or a group of\r
+ * pins, depending on the mask value; all pins are configured by this\r
+ * function. The size of the array must also be provided and is easily\r
+ * computed using ARRAY_SIZE whenever its length is not known in\r
+ * advance.\r
+ *\r
+ * \param list Pointer to a list of Pin instances.\r
+ * \param size Size of the Pin list (calculated using ARRAY_SIZE).\r
+ *\r
+ * \return 1 if the pins have been configured properly; otherwise 0.\r
+ */\r
+extern uint8_t pio_configure(const struct _pin *list, uint32_t size);\r
+\r
+/**\r
+ * \brief Sets a high output level on all the PIOs defined in the\r
+ * given Pin instance.\r
+ *\r
+ * \details This has no immediate effects on PIOs that are not output,\r
+ * but the PIO controller will memorize the value they are changed to\r
+ * outputs.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+extern void pio_set(const struct _pin *pin);\r
+\r
+/**\r
+ * \brief Sets a low output level on all the PIOs defined in the given\r
+ * Pin instance.\r
+ *\r
+ * \details This has no immediate effects on PIOs that are not output,\r
+ * but the PIO controller will memorize the value they are changed to\r
+ * outputs.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+extern void pio_clear(const struct _pin *pin);\r
+\r
+/**\r
+ * \brief Returns 1 if one or more PIO of the given Pin instance currently have\r
+ * a high level; otherwise returns 0. This method returns the actual value that\r
+ * is being read on the pin. To return the supposed output value of a pin, use\r
+ * \ref pio_get_output_date_status() instead.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ *\r
+ * \return 1 if the Pin instance contains at least one PIO that currently has\r
+ * a high level; otherwise 0.\r
+ */\r
+extern uint8_t pio_get(const struct _pin *pin);\r
+\r
+/**\r
+ * \brief Returns 1 if one or more PIO of the given Pin are configured to output a\r
+ * high level (even if they are not output).\r
+ * To get the actual value of the pin, use pio_get() instead.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ *\r
+ * \return 1 if the Pin instance contains at least one PIO that is configured\r
+ * to output a high level; otherwise 0.\r
+ */\r
+extern uint8_t pio_get_output_data_status(const struct _pin *pin);\r
+\r
+/**\r
+ * \brief Configures Glitch or Debouncing filter for input.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ * \param cuttoff Cutt off frequency for debounce filter.\r
+ */\r
+extern void pio_set_debounce_filter(const struct _pin *pin, uint32_t cuttoff);\r
+\r
+/**\r
+ * \brief Enable write protect.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+extern void pio_enable_write_protect(const struct _pin *pin);\r
+\r
+/**\r
+ * \brief Disable write protect.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+extern void pio_disable_write_protect(const struct _pin *pin);\r
+\r
+/**\r
+ * \brief Get write protect violation information.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+extern uint32_t pio_get_write_protect_violation_info(const struct _pin * pin);\r
+\r
+/**\r
+ * \brief Configure all pio outputs low\r
+ *\r
+ * \param group PIO group number\r
+ * \param mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+extern void pio_output_low(uint32_t group, uint32_t mask);\r
+\r
+extern void pio_add_handler_to_group(uint32_t group, uint32_t mask,\r
+ pio_handler_t handler, void* user_arg);\r
+\r
+extern void pio_reset_all_it(void);\r
+\r
+/**\r
+ * \brief Generate an interrupt on status change for a PIO or a group\r
+ * of PIO.\r
+\r
+ * \details The provided interrupt handler will be called with the\r
+ * triggering pin as its parameter (enabling different pin instances\r
+ * to share the same handler).\r
+ *\r
+ * \param pin Pointer to a _pin instance.\r
+ */\r
+extern void pio_configure_it(const struct _pin * pin);\r
+\r
+\r
+/**\r
+ * Enables the given interrupt source if it has been configured. The status\r
+ * register of the corresponding PIO controller is cleared prior to enabling\r
+ * the interrupt.\r
+ * \param pin Interrupt source to enable.\r
+ */\r
+extern void pio_enable_it(const struct _pin * pin);\r
+\r
+/**\r
+ * Disables a given interrupt source, with no added side effects.\r
+ *\r
+ * \param pin Interrupt source to disable.\r
+ */\r
+extern void pio_disable_it(const struct _pin * pin);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* _PIO_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup pio_module Working with PIO\r
+ * \section Purpose\r
+ * The PIO driver provides the Interface for configuration the Parallel Input/Output\r
+ * Controller (PIO).\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Initialize the PIO with the desired period using pio_configure().\r
+ * <li> Set a high or low output level on the given PIO using pio_set() or pio_clear().\r
+ * <li> Get the level of the given PIOs using pio_get() or pio_get_output_date_status().\r
+ * <li> Configures Glitch or Debouncing filter for given input PIO using pio_set_debounce_filter().\r
+ * <li> Enable & disable write protect of the given PIOs using pio_enable_write_protect() or pio_disable_write_protect().\r
+ * <li> Get write protect violation information of given PIO using pio_get_write_protect_violation_info().\r
+ * </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the PIT section of the Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref pio.c\n\r
+ * \ref pio3.h\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of PIO V3 (Parallel Input/Output) controller.\r
+ *\r
+ */\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/pio.h"\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/aic.h"\r
+#include "peripherals/matrix.h"\r
+\r
+#include "trace.h"\r
+#include "compiler.h"\r
+\r
+#include <stdint.h>\r
+#include <string.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+struct _bitfield_pio_cfgr_func {\r
+ uint32_t\r
+ func : 3,\r
+ rfu3_7 : 5,\r
+ dir : 1,\r
+ puen : 1,\r
+ pden : 1,\r
+ rfu11 : 1,\r
+ ifen : 1,\r
+ ifscen : 1,\r
+ opd : 1,\r
+ schmitt : 1,\r
+ drvstr : 2,\r
+ rfu18_23 : 6,\r
+ evtsel : 3,\r
+ rfu27_28 : 2,\r
+ pcfs : 1,\r
+ icfs : 1,\r
+ tampen : 1;\r
+};\r
+\r
+union _pio_cfg {\r
+ struct _bitfield_pio_cfgr_func bitfield;\r
+ uint32_t uint32_value;\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions declarations\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef ID_PIOA\r
+static void _pioa_handler(void);\r
+#endif\r
+#ifdef ID_PIOB\r
+static void _piob_handler(void);\r
+#endif\r
+#ifdef ID_PIOC\r
+static void _pioc_handler(void);\r
+#endif\r
+#ifdef ID_PIOD\r
+static void _piod_handler(void);\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+struct _handler {\r
+ uint32_t mask;\r
+ pio_handler_t handler;\r
+ void *user_arg;\r
+};\r
+static struct _handler _handlers[IRQ_PIO_HANDLERS_SIZE];\r
+\r
+static const aic_handler_t _generic_handlers[PIO_GROUP_LENGTH] = {\r
+#ifdef ID_PIOA\r
+ _pioa_handler,\r
+#endif\r
+#ifdef ID_PIOB\r
+ _piob_handler,\r
+#endif\r
+#ifdef ID_PIOC\r
+ _pioc_handler,\r
+#endif\r
+#ifdef ID_PIOD\r
+ _piod_handler,\r
+#endif\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static void _handler_push(void (*handler)(uint32_t, uint32_t, void*),\r
+ uint32_t mask, void* user_arg)\r
+{\r
+ static int i = 0;\r
+ _handlers[i].mask = mask;\r
+ _handlers[i].handler = handler;\r
+ _handlers[i].user_arg = user_arg;\r
+ ++i;\r
+ assert(i < ARRAY_SIZE(_handlers));\r
+}\r
+\r
+#ifdef ID_PIOA\r
+static void _pioa_handler(void)\r
+{\r
+ uint32_t status = 0;\r
+ unsigned int i = 0;\r
+ if (matrix_is_peripheral_secured(MATRIX1, ID_PIOA))\r
+ status = PIOA->PIO_PIO_[PIO_GROUP_A].S_PIO_ISR;\r
+ else\r
+ status = PIOA->PIO_IO_GROUP[PIO_GROUP_A].PIO_ISR;\r
+\r
+ for (i = 0; i < ARRAY_SIZE(_handlers); ++i) {\r
+ if (_handlers[i].mask & status) {\r
+ _handlers[i].handler(PIO_GROUP_A, status,\r
+ _handlers[i].user_arg);\r
+ }\r
+ }\r
+}\r
+#endif\r
+#ifdef ID_PIOB\r
+static void _piob_handler(void)\r
+{\r
+ uint32_t status = 0;\r
+ unsigned int i = 0;\r
+ if (matrix_is_peripheral_secured(MATRIX1, ID_PIOB))\r
+ status = PIOA->PIO_PIO_[PIO_GROUP_B].S_PIO_ISR;\r
+ else\r
+ status = PIOA->PIO_IO_GROUP[PIO_GROUP_B].PIO_ISR;\r
+\r
+ for (i = 0; i < ARRAY_SIZE(_handlers); ++i) {\r
+ if (_handlers[i].mask & status) {\r
+ _handlers[i].handler(PIO_GROUP_B, status,\r
+ _handlers[i].user_arg);\r
+ }\r
+ }\r
+\r
+}\r
+#endif\r
+#ifdef ID_PIOC\r
+static void _pioc_handler(void)\r
+{\r
+ uint32_t status = 0;\r
+ unsigned int i = 0;\r
+ if (matrix_is_peripheral_secured(MATRIX1, ID_PIOC))\r
+ status = PIOA->PIO_PIO_[PIO_GROUP_C].S_PIO_ISR;\r
+ else\r
+ status = PIOA->PIO_IO_GROUP[PIO_GROUP_C].PIO_ISR;\r
+\r
+ for (i = 0; i < ARRAY_SIZE(_handlers); ++i) {\r
+ if (_handlers[i].mask & status) {\r
+ _handlers[i].handler(PIO_GROUP_C, status,\r
+ _handlers[i].user_arg);\r
+ }\r
+ }\r
+}\r
+#endif\r
+#ifdef ID_PIOD\r
+static void _piod_handler(void)\r
+{\r
+ uint32_t status = 0;\r
+ unsigned int i = 0;\r
+ if (matrix_is_peripheral_secured(MATRIX1, ID_PIOD))\r
+ status = PIOA->PIO_PIO_[PIO_GROUP_D].S_PIO_ISR;\r
+ else\r
+ status = PIOA->PIO_IO_GROUP[PIO_GROUP_D].PIO_ISR;\r
+\r
+ for (i = 0; i < ARRAY_SIZE(_handlers); ++i) {\r
+ if (_handlers[i].mask & status) {\r
+ _handlers[i].handler(PIO_GROUP_D, status,\r
+ _handlers[i].user_arg);\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+static inline uint32_t _pio_group_to_id(int group)\r
+{\r
+ switch(group) {\r
+ case PIO_GROUP_A:\r
+ return ID_PIOA;\r
+ case PIO_GROUP_B:\r
+ return ID_PIOB;\r
+ case PIO_GROUP_C:\r
+ return ID_PIOC;\r
+ case PIO_GROUP_D:\r
+ return ID_PIOD;\r
+ default:\r
+ return (unsigned int)-1;\r
+ };\r
+}\r
+\r
+static void* _pio_configure_pins(const struct _pin *pin, uint32_t periph_id)\r
+{\r
+ PioPio_* piogroup = &PIOA->PIO_PIO_[pin->group];\r
+ if (!matrix_is_peripheral_secured(MATRIX1, periph_id)) {\r
+ piogroup->S_PIO_SIONR = pin->mask;\r
+ return (void*) &PIOA->PIO_IO_GROUP[pin->group];\r
+ } else {\r
+ piogroup->S_PIO_SIOSR = pin->mask;\r
+ return (void*) piogroup;\r
+ }\r
+}\r
+\r
+static void* _pio_retrive_group(const struct _pin *pin, uint32_t periph_id)\r
+{\r
+ if (!matrix_is_peripheral_secured(MATRIX1, periph_id)) {\r
+ return (void*) &PIOA->PIO_IO_GROUP[pin->group];\r
+ } else {\r
+ return (void*) &PIOA->PIO_PIO_[pin->group];\r
+ }\r
+}\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures a list of Pin instances, each of which can either\r
+ * hold a single pin or a group of pins, depending on the mask value;\r
+ * all pins are configured by this function. The size of the array\r
+ * must also be provided and is easily computed using ARRAY_SIZE\r
+ * whenever its length is not known in advance.\r
+ *\r
+ * \param list Pointer to a list of _pin instances.\r
+ * \param size Size of the _pin list (calculated using PIN_LISTSIZE).\r
+ *\r
+ * \return 1 if the pins have been configured properly; otherwise 0.\r
+ */\r
+uint8_t pio_configure(const struct _pin *pin_list, uint32_t size)\r
+{\r
+ union _pio_cfg cfg;\r
+ PioIo_group* pioiog;\r
+\r
+ /* Configure pins */\r
+ while (size--)\r
+ {\r
+ /* Enable the PIO group if needed */\r
+ uint32_t periph_id = _pio_group_to_id(pin_list->group);\r
+\r
+ assert(pin_list->group < PIO_GROUP_LENGTH);\r
+ cfg.uint32_value = 0;\r
+ pioiog = (PioIo_group*) _pio_configure_pins(pin_list, periph_id);\r
+\r
+ if ( pin_list->attribute != PIO_DEFAULT) {\r
+ cfg.bitfield.puen = (pin_list->attribute & PIO_PULLUP)? 1:0;\r
+ cfg.bitfield.pden = (pin_list->attribute & PIO_PULLDOWN)? 1:0;\r
+ cfg.bitfield.ifen = (pin_list->attribute & PIO_DEGLITCH)? 1:0;\r
+ cfg.bitfield.ifscen = (pin_list->attribute & PIO_DEBOUNCE)? 1:0;\r
+ cfg.bitfield.opd = (pin_list->attribute & PIO_OPENDRAIN)? 1:0;\r
+ cfg.bitfield.schmitt =(pin_list->attribute & PIO_TRIGGER_DIS)? 1:0;\r
+\r
+ switch (pin_list->attribute & PIO_DRVSTR_Msk) {\r
+ case PIO_DRVSTR_HI:\r
+ cfg.bitfield.drvstr = PIO_CFGR_DRVSTR_HI >> PIO_CFGR_DRVSTR_Pos;\r
+ break;\r
+ case PIO_DRVSTR_ME:\r
+ cfg.bitfield.drvstr = PIO_CFGR_DRVSTR_ME >> PIO_CFGR_DRVSTR_Pos;\r
+ break;\r
+ case PIO_DRVSTR_LO:\r
+ default:\r
+ cfg.bitfield.drvstr = PIO_CFGR_DRVSTR_LO >> PIO_CFGR_DRVSTR_Pos;\r
+ break;\r
+ }\r
+\r
+ switch (pin_list->attribute & PIO_EVTSEL_Msk) {\r
+ case PIO_IT_HIGH_LEVEL:\r
+ cfg.bitfield.evtsel = PIO_CFGR_EVTSEL_HIGH >> PIO_CFGR_EVTSEL_Pos;\r
+ break;\r
+ case PIO_IT_LOW_LEVEL:\r
+ cfg.bitfield.evtsel = PIO_CFGR_EVTSEL_LOW >> PIO_CFGR_EVTSEL_Pos;\r
+ break;\r
+ case PIO_IT_BOTH_EDGE:\r
+ cfg.bitfield.evtsel = PIO_CFGR_EVTSEL_BOTH >> PIO_CFGR_EVTSEL_Pos;\r
+ break;\r
+ case PIO_IT_RISE_EDGE:\r
+ cfg.bitfield.evtsel = PIO_CFGR_EVTSEL_RISING >> PIO_CFGR_EVTSEL_Pos;\r
+ break;\r
+ case PIO_IT_FALL_EDGE:\r
+ default:\r
+ cfg.bitfield.evtsel = PIO_CFGR_EVTSEL_FALLING >> PIO_CFGR_EVTSEL_Pos;\r
+ break;\r
+ }\r
+ }\r
+\r
+ switch (pin_list->type){\r
+\r
+ case PIO_PERIPH_A:\r
+ cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_A >> PIO_CFGR_FUNC_Pos;\r
+ break;\r
+ case PIO_PERIPH_B:\r
+ cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_B >> PIO_CFGR_FUNC_Pos;\r
+ break;\r
+ case PIO_PERIPH_C:\r
+ cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_C >> PIO_CFGR_FUNC_Pos;\r
+ break;\r
+ case PIO_PERIPH_D:\r
+ cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_D >> PIO_CFGR_FUNC_Pos;\r
+ break;\r
+ case PIO_PERIPH_E:\r
+ cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_E >> PIO_CFGR_FUNC_Pos;\r
+ break;\r
+ case PIO_PERIPH_F:\r
+ cfg.bitfield.func = PIO_CFGR_FUNC_PERIPH_F >> PIO_CFGR_FUNC_Pos;\r
+ break;\r
+ case PIO_GENERIC:\r
+ case PIO_INPUT:\r
+ cfg.bitfield.dir = 0;\r
+ break;\r
+\r
+ case PIO_OUTPUT_0:\r
+ cfg.bitfield.dir = 1;\r
+ pio_clear(pin_list);\r
+ break;\r
+\r
+ case PIO_OUTPUT_1:\r
+ cfg.bitfield.dir = 1;\r
+ pio_set(pin_list);\r
+ break;\r
+\r
+ default:\r
+ case PIO_PERIPH_G:\r
+ return 0;\r
+ }\r
+\r
+ pioiog->PIO_MSKR = pin_list->mask;\r
+ pioiog->PIO_CFGR = cfg.uint32_value;\r
+ pmc_enable_peripheral(periph_id);\r
+\r
+ ++pin_list;\r
+ }\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Sets a high output level on all the PIOs defined in the\r
+ * given Pin instance. This has no immediate effects on PIOs that are\r
+ * not output, but the PIO controller will memorize the value they are\r
+ * changed to outputs.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+void pio_set(const struct _pin *pin)\r
+{\r
+ assert(pin->group < PIO_GROUP_LENGTH);\r
+ uint32_t periph_id = _pio_group_to_id(pin->group);\r
+ PioIo_group* pioiog = (PioIo_group*) _pio_retrive_group(pin, periph_id);\r
+ pioiog->PIO_SODR = pin->mask;\r
+}\r
+\r
+/**\r
+ * \brief Sets a low output level on all the PIOs defined in the given\r
+ * Pin instance. This has no immediate effects on PIOs that are not\r
+ * output, but the PIO controller will memorize the value they are\r
+ * changed to outputs.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+void pio_clear(const struct _pin *pin)\r
+{\r
+ assert(pin->group < PIO_GROUP_LENGTH);\r
+ uint32_t periph_id = _pio_group_to_id(pin->group);\r
+ PioIo_group* pioiog = (PioIo_group*) _pio_retrive_group(pin, periph_id);\r
+ pioiog->PIO_CODR = pin->mask;\r
+}\r
+\r
+/**\r
+ * \brief Returns 1 if one or more PIO of the given Pin instance currently have\r
+ * a high level; otherwise returns 0. This method returns the actual value that\r
+ * is being read on the pin. To return the supposed output value of a pin, use\r
+ * pio_get_output_date_status() instead.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ *\r
+ * \return 1 if the Pin instance contains at least one PIO that currently has\r
+ * a high level; otherwise 0.\r
+ */\r
+uint8_t pio_get(const struct _pin *pin)\r
+{\r
+ assert(pin->group < PIO_GROUP_LENGTH);\r
+ uint32_t reg ;\r
+ uint32_t periph_id = _pio_group_to_id(pin->group);\r
+ PioIo_group* pioiog = (PioIo_group*) _pio_retrive_group(pin, periph_id);\r
+\r
+ if ((pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1)) {\r
+ reg = pioiog->PIO_ODSR ;\r
+ }\r
+ else {\r
+ reg = pioiog->PIO_PDSR ;\r
+ }\r
+ if ( (reg & pin->mask) == 0 ) {\r
+ return 0 ;\r
+ }\r
+ else {\r
+ return 1 ;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Returns 1 if one or more PIO of the given Pin are configured\r
+ * to output a high level (even if they are not output). To get the\r
+ * actual value of the pin, use pio_get() instead.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ *\r
+ * \return 1 if the Pin instance contains at least one PIO that is configured\r
+ * to output a high level; otherwise 0.\r
+ */\r
+uint8_t pio_get_output_data_status(const struct _pin *pin)\r
+{\r
+ assert(pin->group < PIO_GROUP_LENGTH);\r
+ uint32_t periph_id = _pio_group_to_id(pin->group);\r
+ PioIo_group* pioiog = (PioIo_group*) _pio_retrive_group(pin, periph_id);\r
+\r
+ if ((pioiog->PIO_ODSR & pin->mask) == 0) {\r
+ return 0;\r
+ }\r
+ else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configures Glitch or Debouncing filter for input.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ * \param cuttoff Cutt off frequency for debounce filter.\r
+ */\r
+void pio_set_debounce_filter(const struct _pin *pin, uint32_t cuttoff)\r
+{\r
+ assert(pin->group < PIO_GROUP_LENGTH);\r
+ if (cuttoff == 0) {\r
+ PIOA->S_PIO_SCDR = 0;\r
+ }\r
+ else {\r
+ /* the lowest 14 bits work */\r
+ PIOA->S_PIO_SCDR =\r
+ ((pmc_get_slow_clock()/(2*(cuttoff))) - 1) & 0x3FFF;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable write protect.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+void pio_enable_write_protect(const struct _pin *pin)\r
+{\r
+ assert(pin->group < PIO_GROUP_LENGTH);\r
+ PIOA->PIO_WPMR = (PIO_WPMR_WPKEY_VALID | PIO_WPMR_WPEN_EN );\r
+}\r
+\r
+/**\r
+ * \brief Disable write protect.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+void pio_disable_write_protect(const struct _pin *pin)\r
+{\r
+ assert(pin->group < PIO_GROUP_LENGTH);\r
+ PIOA->PIO_WPMR = (PIO_WPMR_WPKEY_VALID | PIO_WPMR_WPEN_DIS );\r
+}\r
+\r
+/**\r
+ * \brief Get write protect violation information.\r
+ *\r
+ * \param pin Pointer to a Pin instance describing one or more pins.\r
+ */\r
+uint32_t pio_get_write_protect_violation_info(const struct _pin * pin)\r
+{\r
+ assert(pin->group < PIO_GROUP_LENGTH);\r
+ return PIOA->PIO_WPSR;\r
+}\r
+\r
+void pio_add_handler_to_group(uint32_t group, uint32_t mask,\r
+ pio_handler_t handler, void* user_arg)\r
+{\r
+ trace_debug("Enter in pio_add_handler_to_group()\n\r");\r
+ assert(group <\r
+ (sizeof(_generic_handlers)/sizeof(_generic_handlers[0])));\r
+ _handler_push(handler, mask, user_arg);\r
+ uint32_t id = _pio_group_to_id(group);\r
+ aic_set_source_vector(id,\r
+ (aic_handler_t)_generic_handlers[group]);\r
+ aic_enable(id);\r
+}\r
+\r
+void pio_reset_all_it(void)\r
+{\r
+ int i = 0;\r
+ for (i = 0; i < PIO_GROUP_LENGTH; ++i) {\r
+ PIOA->PIO_IO_GROUP[i].PIO_ISR;\r
+ PIOA->PIO_IO_GROUP[i].PIO_IDR = ~0UL;\r
+ }\r
+}\r
+\r
+/**\r
+ * Configures a PIO or a group of PIO to generate an interrupt on status\r
+ * change. The provided interrupt handler will be called with the triggering\r
+ * pin as its parameter (enabling different pin instances to share the same\r
+ * handler).\r
+ * \param pin Pointer to a _pin instance.\r
+ */\r
+void pio_configure_it(const struct _pin *pin)\r
+{\r
+ trace_debug("Enter in pio_configure_it()\n\r");\r
+ assert(pin != NULL);\r
+}\r
+\r
+/**\r
+ * Enables the given interrupt source if it has been configured. The status\r
+ * register of the corresponding PIO controller is cleared prior to enabling\r
+ * the interrupt.\r
+ * \param pin Interrupt source to enable.\r
+ */\r
+void pio_enable_it(const struct _pin *pin)\r
+{\r
+ trace_debug("pio_enable_it() \n\r");\r
+ assert(pin != NULL);\r
+ uint32_t periph_id = _pio_group_to_id(pin->group);\r
+ PioIo_group* pioiog = (PioIo_group*) _pio_retrive_group(pin, periph_id);\r
+\r
+ pioiog->PIO_ISR;\r
+ /* Configure interrupt enable register */\r
+ pioiog->PIO_IER = pin->mask; /* enable interrupt register */\r
+}\r
+\r
+/**\r
+ * Disables a given interrupt source, with no added side effects.\r
+ *\r
+ * \param pin Interrupt source to disable.\r
+ */\r
+void pio_disable_it(const struct _pin *pin)\r
+{\r
+ trace_debug("pio_enable_it()\n\r");\r
+ assert(pin != NULL);\r
+ uint32_t periph_id = _pio_group_to_id(pin->group);\r
+ PioIo_group* pioiog = (PioIo_group*) _pio_retrive_group(pin, periph_id);\r
+ pioiog->PIO_IDR = pin->mask;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * This file provides a basic API for PIO configuration and usage of\r
+ * user-controlled pins. Please refer to the board.h file for a list of\r
+ * available pin definitions.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Define a constant pin description array such as the following one, using\r
+ * the existing definitions provided by the board.h file if possible:\r
+ * \code\r
+ * const struct _pin pins[] = {PIN_USART0_TXD, PIN_USART0_RXD};\r
+ * \endcode\r
+ * Alternatively, it is possible to add new pins by provided the full Pin\r
+ * structure:\r
+ * \code\r
+ * // Pin instance to configure PA10 & PA11 as inputs with the internal\r
+ * // pull-up enabled.\r
+ * const Pin pins = {\r
+ * (1 << 10) | (1 << 11),\r
+ * REG_PIOA,\r
+ * ID_PIOA,\r
+ * PIO_INPUT,\r
+ * PIO_PULLUP\r
+ * };\r
+ * \endcode\r
+ * -# Configure a pin array by calling pio_configure() with a pointer to the\r
+ * array and its size (which is computed using the ARRAY_SIZE macro).\r
+ * -# Change and get the value of a user-controlled pin using the pio_set,\r
+ * pio_clear and pio_get methods.\r
+ * -# Get the level being currently output by a user-controlled pin configured\r
+ * as an output using pio_get_output_date_status().\r
+ */\r
+\r
+#ifndef _PIO_H\r
+#error "pio3.h cannot be included. pio.h should be used instead"\r
+#endif\r
+\r
+#ifndef _PIO4_H\r
+#define _PIO4_H\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/* The IO group is A (or 0) */\r
+#define PIO_GROUP_A 0\r
+/* The IO group is B (or 1) */\r
+#define PIO_GROUP_B 1\r
+/* The IO group is C (or 2) */\r
+#define PIO_GROUP_C 2\r
+/* The IO group is D (or 3) */\r
+#define PIO_GROUP_D 3\r
+\r
+#define PIO_GROUP_LENGTH PIOIO_GROUP_NUMBER\r
+\r
+/* The pin is controlled by the generic PIO. */\r
+#define PIO_GENERIC 0\r
+/* The pin is controlled by the associated signal of peripheral A. */\r
+#define PIO_PERIPH_A 1\r
+/* The pin is controlled by the associated signal of peripheral B. */\r
+#define PIO_PERIPH_B 2\r
+/* The pin is controlled by the associated signal of peripheral C. */\r
+#define PIO_PERIPH_C 3\r
+/* The pin is controlled by the associated signal of peripheral D. */\r
+#define PIO_PERIPH_D 4\r
+/* The pin is controlled by the associated signal of peripheral E. */\r
+#define PIO_PERIPH_E 5\r
+/* The pin is controlled by the associated signal of peripheral F. */\r
+#define PIO_PERIPH_F 6\r
+/* The pin is controlled by the associated signal of peripheral G. */\r
+#define PIO_PERIPH_G 7\r
+\r
+/* The pin is an input. */\r
+#define PIO_INPUT 10\r
+/* The pin is an output. */\r
+#define PIO_OUTPUT 11\r
+/* The pin is an output and has a default level of 0. */\r
+#define PIO_OUTPUT_0 11\r
+/* The pin is an output and has a default level of 1. */\r
+#define PIO_OUTPUT_1 12\r
+\r
+\r
+/* Default pin configuration (no attribute). */\r
+#define PIO_DEFAULT (0x0u << 0)\r
+/* The internal pin pull-up is active. */\r
+#define PIO_PULLUP (0x1u << 0)\r
+/* The internal pin pull-down is active. */\r
+#define PIO_PULLDOWN (0x1u << 1)\r
+/* The pin is open-drain. */\r
+#define PIO_OPENDRAIN (0x1u << 2)\r
+/* The internal glitch filter is active. */\r
+#define PIO_DEGLITCH (0x1u << 3)\r
+/* The internal Debounce filter is active. */\r
+#define PIO_DEBOUNCE (0x1u << 4)\r
+/* The internal Schmitt trigger is disable. */\r
+#define PIO_TRIGGER_DIS (0x1u << 5)\r
+\r
+/* Drive Strength. */\r
+#define PIO_DRVSTR_Pos 10\r
+#define PIO_DRVSTR_Msk (0x3u << 10)\r
+#define PIO_DRVSTR_HI (0x2u << 10) /* High drive */\r
+#define PIO_DRVSTR_ME (0x1u << 10) /* Medium drive */\r
+#define PIO_DRVSTR_LO (0x0u << 10) /* Low drive */\r
+\r
+#define PIO_EVTSEL_Pos 12\r
+#define PIO_EVTSEL_Msk (0x7u << 12)\r
+/* Event detection on input falling edge. */\r
+#define PIO_IT_FALL_EDGE (0x0u << 12)\r
+/* Event detection on input rising edge. */\r
+#define PIO_IT_RISE_EDGE (0x1u << 12)\r
+/* Event detection on input both edge. */\r
+#define PIO_IT_BOTH_EDGE (0x2u << 12)\r
+/* Event detection on low level input. */\r
+#define PIO_IT_LOW_LEVEL (0x3u << 12)\r
+/*Event detection on high level input. */\r
+#define PIO_IT_HIGH_LEVEL (0x4u << 12)\r
+\r
+#define PIO_WPMR_WPEN_EN ( 0x01 << 0 )\r
+\r
+#define PIO_WPMR_WPEN_DIS ( 0x00 << 0 )\r
+\r
+#define PIO_WPMR_WPKEY_VALID ( 0x50494F << 8 )\r
+\r
+#endif /* #ifndef _PIO4_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup pit_module Working with PIT\r
+ * \section Purpose\r
+ * The PIT driver provides the Interface for configuration the Periodic\r
+ * Interval Timer (PIT) peripheral.\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Initialize the PIT with the desired period using pit_init().\r
+ * Alternatively, the Periodic Interval Value (PIV) can be configured\r
+ * manually using pit_set_piv(). </li>\r
+ * <li> Start the PIT counting using pit_enable().\r
+ * <li> Enable & disable the PIT interrupt using pit_enable_it() and\r
+ * pit_disable_it(). </li>\r
+ * <li> Retrieve the current status of the PIT using pit_get_status(). </li>\r
+ * <li> To get the current value of the internal counter and the number of ticks\r
+ * that have occurred, use either pit_get_pivr() or pit_get_piir() depending\r
+ * on whether you want the values to be cleared or not. </li>\r
+ *\r
+ * </ul>\r
+ * For more accurate information, please look at the PIT section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref pit.c\n\r
+ * \ref pit.h.\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of PIT (Periodic Interval Timer) controller.\r
+ *\r
+ */\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/pit.h"\r
+#include "peripherals/pmc.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+void pit_init(uint32_t period)\r
+{\r
+ uint32_t pit_frequency = pmc_get_peripheral_clock(ID_PIT) / 1000000;\r
+ PIT->PIT_MR = period ? (period * pit_frequency + 8) >> 4 : 0;\r
+ PIT->PIT_MR |= PIT_MR_PITEN;\r
+}\r
+\r
+void pit_set_piv(uint32_t piv)\r
+{\r
+ uint32_t dwMr = PIT->PIT_MR & (~PIT_MR_PIV_Msk);\r
+ PIT->PIT_MR = dwMr | PIT_MR_PIV(piv);\r
+}\r
+\r
+void pit_enable(void)\r
+{\r
+ PIT->PIT_MR |= PIT_MR_PITEN;\r
+}\r
+\r
+void pit_disable(void)\r
+{\r
+ PIT->PIT_MR &= ~PIT_MR_PITEN;\r
+}\r
+\r
+void pit_enable_it(void)\r
+{\r
+ PIT->PIT_MR |= PIT_MR_PITIEN;\r
+}\r
+\r
+void pit_disable_it(void)\r
+{\r
+ PIT->PIT_MR &= ~PIT_MR_PITIEN;\r
+}\r
+\r
+uint32_t pit_get_mode(void)\r
+{\r
+ return PIT->PIT_MR;\r
+}\r
+\r
+uint32_t pit_get_status(void)\r
+{\r
+ return PIT->PIT_SR;\r
+}\r
+\r
+uint32_t pit_get_piir(void)\r
+{\r
+ return PIT->PIT_PIIR;\r
+}\r
+\r
+uint32_t pit_get_pivr(void)\r
+{\r
+ return PIT->PIT_PIVR;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _PIT_H_\r
+#define _PIT_H_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+* \brief Initialize the Periodic Interval Timer to generate a tick at the\r
+* specified period, given the current master clock frequency.\r
+*\r
+* \param period Period in micro seconds.\r
+*/\r
+extern void pit_init(uint32_t period);\r
+\r
+/**\r
+ * \brief Set the Periodic Interval Value of the PIT.\r
+ *\r
+ * \param piv PIV value to set.\r
+ */\r
+extern void pit_set_piv(uint32_t piv);\r
+\r
+/**\r
+ * \brief Enables the PIT if this is not already the case.\r
+ *\r
+ */\r
+extern void pit_enable(void);\r
+\r
+/**\r
+ * \brief Disnables the PIT when PIV value is reached.\r
+ *\r
+ */\r
+extern void pit_disable(void);\r
+\r
+/**\r
+ * \brief Enable the PIT periodic interrupt.\r
+ *\r
+ */\r
+extern void pit_enable_it(void);\r
+\r
+/**\r
+ * \brief Disables the PIT periodic interrupt.\r
+ *\r
+ */\r
+extern void pit_disable_it(void);\r
+\r
+/**\r
+ * \brief Returns the value of the PIT mode register.\r
+ *\r
+ * \return PIT_MR value.\r
+ */\r
+extern uint32_t pit_get_mode(void);\r
+\r
+/**\r
+ * \brief Returns the value of the PIT status register, clearing it as\r
+ * a side effect.\r
+ *\r
+ * \return PIT_SR value.\r
+ */\r
+extern uint32_t pit_get_status(void);\r
+\r
+/**\r
+ * \brief Returns the value of the PIT Image Register, to read PICNT\r
+ * and CPIV without clearing the current values.\r
+ *\r
+ * \return PIT_PIIR value.\r
+ */\r
+extern uint32_t pit_get_piir(void);\r
+\r
+/**\r
+ * \brief Returns the value of the PIT Value Register, clearing it as\r
+ * a side effect.\r
+ *\r
+ * \return PITC_PIVR value.\r
+ */\r
+extern uint32_t pit_get_pivr(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _PIT_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup pmc_module Working with PMC\r
+ * \section Purpose\r
+ * The PMC driver provides the Interface for configuration the Power Management\r
+ * Controller (PMC).\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Enable & disable peripherals using pmc_enable_peripheral() and\r
+ * pmc_enable_all_peripherals() or pmc_disable_peripheral() and\r
+ * pmc_disable_all_peripherals().\r
+ * <li> Get & set maximum frequency clock for giving peripheral using\r
+ * pmc_get_peri_max_freq() and pmc_set_peri_max_clock().\r
+ * <li> Get Peripheral Status for the given peripheral using pmc_is_periph_enabled()\r
+ * <li> Select clocks's source using pmc_select_external_crystal(),\r
+ * pmc_select_internal_crystal(), pmc_select_external_osc() and pmc_select_internal_osc().\r
+ * <li> Switch MCK using pmc_switch_mck_to_pll(), pmc_switch_mck_to_main() and\r
+ * pmc_switch_mck_to_slck().\r
+ * <li> Config PLL using pmc_set_pll_a() and pmc_disable_pll_a().\r
+ * </li>\r
+ * </ul>\r
+ * For more accurate information, please look at the PMC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref pmc.c\n\r
+ * \ref pmc.h\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of PIO (Parallel Input/Output) controller.\r
+ *\r
+ */\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "board.h"\r
+#include "peripherals/pmc.h"\r
+#include "trace.h"\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static uint32_t _pmc_mck = 0;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Private functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static void _pmc_compute_mck(void)\r
+{\r
+ uint32_t clk = 0;\r
+ uint32_t mckr = PMC->PMC_MCKR;\r
+\r
+ uint32_t css = mckr & PMC_MCKR_CSS_Msk;\r
+ switch (css) {\r
+ case PMC_MCKR_CSS_SLOW_CLK:\r
+ clk = pmc_get_slow_clock();\r
+ break;\r
+ case PMC_MCKR_CSS_MAIN_CLK:\r
+ clk = pmc_get_main_clock();\r
+ break;\r
+ case PMC_MCKR_CSS_PLLA_CLK:\r
+ clk = pmc_get_plla_clock();\r
+ break;\r
+ case PMC_MCKR_CSS_UPLL_CLK:\r
+ clk = pmc_get_upll_clock();\r
+ break;\r
+ default:\r
+ /* should never get here... */\r
+ break;\r
+ }\r
+\r
+ uint32_t pres = mckr & PMC_MCKR_PRES_Msk;\r
+ switch (pres) {\r
+ case PMC_MCKR_PRES_CLOCK:\r
+ break;\r
+ case PMC_MCKR_PRES_CLOCK_DIV2:\r
+ clk >>= 1;\r
+ break;\r
+ case PMC_MCKR_PRES_CLOCK_DIV4:\r
+ clk >>= 2;\r
+ break;\r
+ case PMC_MCKR_PRES_CLOCK_DIV8:\r
+ clk >>= 3;\r
+ break;\r
+ case PMC_MCKR_PRES_CLOCK_DIV16:\r
+ clk >>= 4;\r
+ break;\r
+ case PMC_MCKR_PRES_CLOCK_DIV32:\r
+ clk >>= 5;\r
+ break;\r
+ case PMC_MCKR_PRES_CLOCK_DIV64:\r
+ clk >>= 6;\r
+ break;\r
+ default:\r
+ /* should never get here... */\r
+ break;\r
+ }\r
+\r
+ uint32_t mdiv = mckr & PMC_MCKR_MDIV_Msk;\r
+ switch (mdiv) {\r
+ case PMC_MCKR_MDIV_EQ_PCK:\r
+ break;\r
+ case PMC_MCKR_MDIV_PCK_DIV2:\r
+ clk >>= 1; // divide by 2\r
+ break;\r
+ case PMC_MCKR_MDIV_PCK_DIV4:\r
+ clk >>= 2; // divide by 4\r
+ break;\r
+ case PMC_MCKR_MDIV_PCK_DIV3:\r
+ clk /= 3; // divide by 3\r
+ break;\r
+ default:\r
+ /* should never get here... */\r
+ break;\r
+ }\r
+\r
+ _pmc_mck = clk;\r
+}\r
+\r
+static uint32_t _pmc_get_pck_clock(uint32_t index)\r
+{\r
+ uint32_t clk = 0;\r
+ uint32_t pck = PMC->PMC_PCK[index];\r
+\r
+ switch (pck & PMC_PCK_CSS_Msk) {\r
+ case PMC_PCK_CSS_SLOW_CLK:\r
+ clk = pmc_get_slow_clock();\r
+ break;\r
+ case PMC_PCK_CSS_MAIN_CLK:\r
+ clk = pmc_get_main_clock();\r
+ break;\r
+ case PMC_PCK_CSS_PLLA_CLK:\r
+ clk = pmc_get_plla_clock();\r
+ break;\r
+ case PMC_PCK_CSS_UPLL_CLK:\r
+ clk = pmc_get_upll_clock();\r
+ break;\r
+ case PMC_PCK_CSS_MCK_CLK:\r
+ clk = pmc_get_master_clock();\r
+ break;\r
+#ifdef CONFIG_HAVE_PMC_AUDIO_CLOCK\r
+ case PMC_PCK_CSS_AUDIO_CLK:\r
+ clk = pmc_get_audio_pmc_clock();\r
+ break;\r
+#endif\r
+ }\r
+\r
+ uint32_t prescaler = (pck & PMC_PCK_PRES_Msk) >> PMC_PCK_PRES_Pos;\r
+ return clk / (prescaler + 1);\r
+}\r
+\r
+static bool _pmc_get_system_clock_bits(enum _pmc_system_clock clock,\r
+ uint32_t *scer, uint32_t* scdr, uint32_t *scsr)\r
+{\r
+ uint32_t e, d, s;\r
+\r
+ switch (clock)\r
+ {\r
+#ifdef PMC_SCDR_PCK\r
+ case PMC_SYSTEM_CLOCK_PCK:\r
+ e = 0;\r
+ d = PMC_SCDR_PCK;\r
+ s = PMC_SCSR_PCK;\r
+ break;\r
+#endif\r
+ case PMC_SYSTEM_CLOCK_DDR:\r
+ e = PMC_SCER_DDRCK;\r
+ d = PMC_SCDR_DDRCK;\r
+ s = PMC_SCSR_DDRCK;\r
+ break;\r
+ case PMC_SYSTEM_CLOCK_LCD:\r
+ e = PMC_SCER_LCDCK;\r
+ d = PMC_SCDR_LCDCK;\r
+ s = PMC_SCSR_LCDCK;\r
+ break;\r
+#ifdef PMC_SCER_SMDCK\r
+ case PMC_SYSTEM_CLOCK_SMD:\r
+ e = PMC_SCER_SMDCK;\r
+ d = PMC_SCDR_SMDCK;\r
+ s = PMC_SCSR_SMDCK;\r
+ break;\r
+#endif\r
+ case PMC_SYSTEM_CLOCK_UHP:\r
+ e = PMC_SCER_UHP;\r
+ d = PMC_SCDR_UHP;\r
+ s = PMC_SCSR_UHP;\r
+ break;\r
+ case PMC_SYSTEM_CLOCK_UDP:\r
+ e = PMC_SCER_UDP;\r
+ d = PMC_SCDR_UDP;\r
+ s = PMC_SCSR_UDP;\r
+ break;\r
+ case PMC_SYSTEM_CLOCK_PCK0:\r
+ e = PMC_SCER_PCK0;\r
+ d = PMC_SCDR_PCK0;\r
+ s = PMC_SCSR_PCK0;\r
+ break;\r
+ case PMC_SYSTEM_CLOCK_PCK1:\r
+ e = PMC_SCER_PCK1;\r
+ d = PMC_SCDR_PCK1;\r
+ s = PMC_SCSR_PCK1;\r
+ break;\r
+ case PMC_SYSTEM_CLOCK_PCK2:\r
+ e = PMC_SCER_PCK2;\r
+ d = PMC_SCDR_PCK2;\r
+ s = PMC_SCSR_PCK2;\r
+ break;\r
+#ifdef PMC_SCER_ISCCK\r
+ case PMC_SYSTEM_CLOCK_ISC:\r
+ e = PMC_SCER_ISCCK;\r
+ d = PMC_SCDR_ISCCK;\r
+ s = PMC_SCSR_ISCCK;\r
+ break;\r
+#endif\r
+ default:\r
+ return false;\r
+ }\r
+\r
+ if (scer) {\r
+ if (e)\r
+ *scer = e;\r
+ else\r
+ return false;\r
+ }\r
+\r
+ if (scdr) {\r
+ if (d)\r
+ *scdr = d;\r
+ else\r
+ return false;\r
+ }\r
+\r
+ if (scsr) {\r
+ if (s)\r
+ *scsr = s;\r
+ else\r
+ return false;\r
+ }\r
+\r
+ return true;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions (General)\r
+ *----------------------------------------------------------------------------*/\r
+\r
+uint32_t pmc_get_master_clock(void)\r
+{\r
+ if (!_pmc_mck) {\r
+ _pmc_compute_mck();\r
+ }\r
+ return _pmc_mck;\r
+}\r
+\r
+uint32_t pmc_get_slow_clock(void)\r
+{\r
+ if (SCKC->SCKC_CR & SCKC_CR_OSCSEL)\r
+ return SLOW_CLOCK_INT_OSC; /* on-chip slow clock RC */\r
+ else\r
+ return BOARD_SLOW_CLOCK_EXT_OSC; /* external crystal */\r
+}\r
+\r
+uint32_t pmc_get_main_clock(void)\r
+{\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)\r
+ return MAIN_CLOCK_INT_OSC; /* on-chip main clock RC */\r
+ else\r
+ return BOARD_MAIN_CLOCK_EXT_OSC; /* external crystal */\r
+}\r
+\r
+uint32_t pmc_get_plla_clock(void)\r
+{\r
+ uint32_t pllaclk, pllar, pllmula, plldiva;\r
+\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)\r
+ pllaclk = MAIN_CLOCK_INT_OSC; /* on-chip main clock RC */\r
+ else\r
+ pllaclk = BOARD_MAIN_CLOCK_EXT_OSC; /* external crystal */\r
+\r
+ pllar = PMC->CKGR_PLLAR;\r
+ pllmula = (pllar & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos;\r
+ plldiva = (pllar & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos;\r
+ if (plldiva == 0 || pllmula == 0) {\r
+ pllaclk = 0;\r
+ } else {\r
+ pllaclk = pllaclk * (pllmula + 1) / plldiva;\r
+ if (PMC->PMC_MCKR & PMC_MCKR_PLLADIV2)\r
+ pllaclk >>= 1;\r
+ }\r
+\r
+ return pllaclk;\r
+}\r
+\r
+uint32_t pmc_get_processor_clock(void)\r
+{\r
+ uint32_t procclk, mdiv;\r
+\r
+ procclk = pmc_get_master_clock();\r
+\r
+ mdiv = PMC->PMC_MCKR & PMC_MCKR_MDIV_Msk;\r
+ switch (mdiv) {\r
+ case PMC_MCKR_MDIV_EQ_PCK:\r
+ break;\r
+ case PMC_MCKR_MDIV_PCK_DIV2:\r
+ procclk <<= 1; // multiply by 2\r
+ break;\r
+ case PMC_MCKR_MDIV_PCK_DIV3:\r
+ procclk *= 3; // multiply by 3\r
+ break;\r
+ case PMC_MCKR_MDIV_PCK_DIV4:\r
+ procclk <<= 2; // multiply by 4\r
+ break;\r
+ default:\r
+ /* should never get here... */\r
+ break;\r
+ }\r
+\r
+ return procclk;\r
+}\r
+\r
+void pmc_select_external_crystal(void)\r
+{\r
+ int return_to_sclock = 0;\r
+\r
+ if (PMC->PMC_MCKR == PMC_MCKR_CSS(PMC_MCKR_CSS_SLOW_CLK)) {\r
+ pmc_switch_mck_to_main();\r
+ return_to_sclock = 1;\r
+ }\r
+\r
+ /* switch from internal RC 32kHz to external OSC 32 kHz */\r
+ SCKC->SCKC_CR = (SCKC->SCKC_CR & ~SCKC_CR_OSCSEL) | SCKC_CR_OSCSEL_XTAL;\r
+\r
+ /* Wait 5 slow clock cycles for internal resynchronization */\r
+ volatile int count;\r
+ for (count = 0; count < 0x1000; count++);\r
+\r
+ /* Switch to slow clock again if needed */\r
+ if (return_to_sclock)\r
+ pmc_switch_mck_to_slck();\r
+}\r
+\r
+void pmc_select_internal_crystal(void)\r
+{\r
+ int return_to_sclock = 0;\r
+\r
+ if (PMC->PMC_MCKR == PMC_MCKR_CSS(PMC_MCKR_CSS_SLOW_CLK)) {\r
+ pmc_switch_mck_to_main();\r
+ return_to_sclock = 1;\r
+ }\r
+\r
+ /* switch from extenal OSC 32kHz to internal RC 32 kHz */\r
+ /* switch slow clock source to internal OSC 32 kHz */\r
+ SCKC->SCKC_CR = (SCKC->SCKC_CR & ~SCKC_CR_OSCSEL) | SCKC_CR_OSCSEL_RC;\r
+\r
+ /* Wait 5 slow clock cycles for internal resynchronization */\r
+ volatile int count;\r
+ for (count = 0; count < 0x1000; count++);\r
+\r
+ /* Switch to slow clock again if needed */\r
+ if (return_to_sclock)\r
+ pmc_switch_mck_to_slck();\r
+}\r
+\r
+void pmc_select_external_osc(void)\r
+{\r
+ /* Enable external osc 12 MHz when needed */\r
+ if ((PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN) != CKGR_MOR_MOSCXTEN) {\r
+ PMC->CKGR_MOR |= CKGR_MOR_MOSCXTST(18) | CKGR_MOR_MOSCXTEN | CKGR_MOR_KEY_PASSWD;\r
+ /* Wait Main Oscillator ready */\r
+ while(!(PMC->PMC_SR & PMC_SR_MOSCXTS));\r
+ }\r
+\r
+ /* Return if external osc had been selected */\r
+ if ((PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) == CKGR_MOR_MOSCSEL)\r
+ return;\r
+\r
+ /* switch MAIN clock to external OSC 12 MHz */\r
+ PMC->CKGR_MOR |= CKGR_MOR_MOSCSEL | CKGR_MOR_KEY_PASSWD;\r
+\r
+ /* wait for the command to be taken into account */\r
+ while ((PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) != CKGR_MOR_MOSCSEL);\r
+\r
+ /* wait MAIN clock status change for external OSC 12 MHz selection */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));\r
+\r
+ /* disable internal RC 12 MHz to save power */\r
+ pmc_disable_internal_osc();\r
+}\r
+\r
+void pmc_disable_external_osc(void)\r
+{\r
+ /* disable external OSC 12 MHz */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | CKGR_MOR_KEY_PASSWD;\r
+}\r
+\r
+void pmc_select_internal_osc(void)\r
+{\r
+#ifdef CKGR_MOR_MOSCRCEN\r
+ /* Enable internal RC 12 MHz when needed */\r
+ if ((PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN) != CKGR_MOR_MOSCRCEN) {\r
+ PMC->CKGR_MOR |= CKGR_MOR_MOSCRCEN | CKGR_MOR_KEY_PASSWD;\r
+ /* Wait internal 12 MHz RC Startup Time for clock stabilization */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+ }\r
+#endif\r
+\r
+ /* switch MAIN clock to internal RC 12 MHz */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_KEY_PASSWD;\r
+\r
+ /* in case where MCK is running on MAIN CLK */\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+\r
+ /* disable external OSC 12 MHz to save power*/\r
+ pmc_disable_external_osc();\r
+}\r
+\r
+void pmc_disable_internal_osc(void)\r
+{\r
+#ifdef CKGR_MOR_MOSCRCEN\r
+ /* disable internal RC 12 MHz */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN) | CKGR_MOR_KEY_PASSWD;\r
+#endif\r
+}\r
+\r
+void pmc_switch_mck_to_pll(void)\r
+{\r
+ /* Select PLL as input clock for PCK and MCK */\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_PLLA_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+\r
+ _pmc_mck = 0;\r
+}\r
+\r
+void pmc_switch_mck_to_upll(void)\r
+{\r
+ /* Select UPLL as input clock for PCK and MCK */\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_UPLL_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+\r
+ _pmc_mck = 0;\r
+}\r
+\r
+void pmc_switch_mck_to_main(void)\r
+{\r
+ /* Select Main Oscillator as input clock for PCK and MCK */\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_PCK_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+\r
+ _pmc_mck = 0;\r
+}\r
+\r
+void pmc_switch_mck_to_slck(void)\r
+{\r
+ /* Select Slow Clock as input clock for PCK and MCK */\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_PCK_CSS_SLOW_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+\r
+ _pmc_mck = 0;\r
+}\r
+\r
+void pmc_set_mck_prescaler(uint32_t prescaler)\r
+{\r
+ /* Change MCK Prescaler divider in PMC_MCKR register */\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk) | prescaler;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+void pmc_set_mck_plla_div(uint32_t divider)\r
+{\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_PLLADIV2) == PMC_MCKR_PLLADIV2) {\r
+ if (divider == 0) {\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_PLLADIV2);\r
+ }\r
+ } else {\r
+ if (divider == PMC_MCKR_PLLADIV2) {\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR | PMC_MCKR_PLLADIV2);\r
+ }\r
+ }\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+void pmc_set_mck_h32mxdiv(uint32_t divider)\r
+{\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_H32MXDIV) == PMC_MCKR_H32MXDIV_H32MXDIV2) {\r
+ if (divider == PMC_MCKR_H32MXDIV_H32MXDIV1) {\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_H32MXDIV);\r
+ }\r
+ } else {\r
+ if (divider == PMC_MCKR_H32MXDIV_H32MXDIV2) {\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR | PMC_MCKR_H32MXDIV_H32MXDIV2);\r
+ }\r
+ }\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+void pmc_set_mck_divider(uint32_t divider)\r
+{\r
+ /* change MCK Prescaler divider in PMC_MCKR register */\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk) | divider;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+void pmc_set_plla(uint32_t pll, uint32_t cpcr)\r
+{\r
+ PMC->CKGR_PLLAR = pll;\r
+ PMC->PMC_PLLICPR = cpcr;\r
+\r
+ if ((pll & CKGR_PLLAR_DIVA_Msk) != CKGR_PLLAR_DIVA_0) {\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA));\r
+ }\r
+}\r
+\r
+void pmc_disable_plla(void)\r
+{\r
+ PMC->CKGR_PLLAR = (PMC->CKGR_PLLAR & ~CKGR_PLLAR_MULA_Msk) | CKGR_PLLAR_MULA(0);\r
+}\r
+\r
+void pmc_enable_system_clock(enum _pmc_system_clock clock)\r
+{\r
+ uint32_t scer, scsr;\r
+ if (!_pmc_get_system_clock_bits(clock, &scer, NULL, &scsr))\r
+ return;\r
+\r
+ PMC->PMC_SCER |= scer;\r
+ while (!(PMC->PMC_SCSR & scsr));\r
+}\r
+\r
+void pmc_disable_system_clock(enum _pmc_system_clock clock)\r
+{\r
+ uint32_t scdr, scsr;\r
+ if (!_pmc_get_system_clock_bits(clock, NULL, &scdr, &scsr))\r
+ return;\r
+\r
+ PMC->PMC_SCDR |= scdr;\r
+ while (PMC->PMC_SCSR & scsr);\r
+}\r
+\r
+#ifdef CONFIG_HAVE_PMC_FAST_STARTUP\r
+void pmc_set_fast_startup_mode(uint32_t startup_mode)\r
+{\r
+ PMC->PMC_FSMR = startup_mode;\r
+}\r
+\r
+void pmc_set_fast_startup_polarity(uint32_t high_level, uint32_t low_level)\r
+{\r
+ PMC->PMC_FSPR &= ~low_level;\r
+ PMC->PMC_FSPR |= high_level;\r
+}\r
+#endif /* CONFIG_HAVE_PMC_FAST_STARTUP */\r
+\r
+void pmc_set_custom_pck_mck(struct pck_mck_cfg *cfg)\r
+{\r
+ pmc_switch_mck_to_slck();\r
+\r
+ if (cfg->ext12m)\r
+ pmc_select_external_osc();\r
+ else\r
+ pmc_select_internal_osc();\r
+\r
+ pmc_switch_mck_to_main();\r
+\r
+ if (cfg->ext32k)\r
+ pmc_select_external_crystal();\r
+ else\r
+ pmc_select_internal_crystal();\r
+\r
+ pmc_set_mck_prescaler(cfg->pck_pres);\r
+ pmc_set_mck_divider(cfg->mck_div);\r
+\r
+ pmc_set_mck_plla_div(cfg->plla_div2 ? PMC_MCKR_PLLADIV2 : 0);\r
+ if (cfg->plla_mul > 0) {\r
+ pmc_disable_plla();\r
+ uint32_t tmp = CKGR_PLLAR_ONE |\r
+ CKGR_PLLAR_PLLACOUNT(0x3F) |\r
+ CKGR_PLLAR_OUTA(0x0) |\r
+ CKGR_PLLAR_MULA(cfg->plla_mul) |\r
+ CKGR_PLLAR_DIVA(cfg->plla_div);\r
+ pmc_set_plla(tmp, PMC_PLLICPR_IPLL_PLLA(0x3));\r
+ } else {\r
+ pmc_disable_plla();\r
+ }\r
+\r
+ if (cfg->h32mxdiv2)\r
+ pmc_set_mck_h32mxdiv(PMC_MCKR_H32MXDIV_H32MXDIV2);\r
+ else\r
+ pmc_set_mck_h32mxdiv(PMC_MCKR_H32MXDIV_H32MXDIV1);\r
+\r
+ switch (cfg->pck_input) {\r
+ case PMC_MCKR_CSS_PLLA_CLK:\r
+ pmc_switch_mck_to_pll();\r
+ break;\r
+\r
+ case PMC_MCKR_CSS_UPLL_CLK:\r
+ pmc_switch_mck_to_upll();\r
+ break;\r
+\r
+ case PMC_MCKR_CSS_SLOW_CLK:\r
+ pmc_switch_mck_to_slck();\r
+ pmc_disable_internal_osc();\r
+ pmc_disable_external_osc();\r
+ break;\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions (Peripherals)\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void pmc_enable_peripheral(uint32_t id)\r
+{\r
+ assert(id > 1 && id < ID_PERIPH_COUNT);\r
+\r
+ PMC->PMC_PCR = PMC_PCR_PID(id);\r
+ volatile uint32_t pcr = PMC->PMC_PCR;\r
+\r
+ PMC->PMC_PCR = pcr | PMC_PCR_CMD | PMC_PCR_EN;\r
+}\r
+\r
+void pmc_disable_peripheral(uint32_t id)\r
+{\r
+ assert(id > 1 && id < ID_PERIPH_COUNT);\r
+\r
+ PMC->PMC_PCR = PMC_PCR_PID(id);\r
+ volatile uint32_t pcr = PMC->PMC_PCR;\r
+\r
+ PMC->PMC_PCR = PMC_PCR_CMD | (pcr & ~PMC_PCR_EN);\r
+}\r
+\r
+uint32_t pmc_is_peripheral_enabled(uint32_t id)\r
+{\r
+ assert(id > 1 && id < ID_PERIPH_COUNT);\r
+\r
+ PMC->PMC_PCR = PMC_PCR_PID(id);\r
+ volatile uint32_t pcr = PMC->PMC_PCR;\r
+\r
+ return !!(pcr & PMC_PCR_EN);\r
+}\r
+\r
+uint32_t pmc_get_peripheral_clock(uint32_t id)\r
+{\r
+ assert(id > 1 && id < ID_PERIPH_COUNT);\r
+\r
+ uint32_t div = get_peripheral_clock_divider(id);\r
+ if (div)\r
+ return pmc_get_master_clock() / div;\r
+\r
+ return 0;\r
+}\r
+\r
+void pmc_disable_all_peripherals(void)\r
+{\r
+ int i;\r
+ for (i = 2; i < ID_PERIPH_COUNT; i++)\r
+ pmc_disable_peripheral(i);\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions (PCK0-2)\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void pmc_configure_pck0(uint32_t clock_source, uint32_t prescaler)\r
+{\r
+ pmc_disable_pck0();\r
+ PMC->PMC_PCK[0] = (clock_source & PMC_PCK_CSS_Msk) | PMC_PCK_PRES(prescaler);\r
+}\r
+\r
+void pmc_enable_pck0(void)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK0;\r
+ while (!(PMC->PMC_SR & PMC_SR_PCKRDY0));\r
+}\r
+\r
+void pmc_disable_pck0(void)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCDR_PCK0;\r
+ while (PMC->PMC_SCSR & PMC_SCSR_PCK0);\r
+}\r
+\r
+uint32_t pmc_get_pck0_clock(void)\r
+{\r
+ return _pmc_get_pck_clock(0);\r
+}\r
+\r
+void pmc_configure_pck1(uint32_t clock_source, uint32_t prescaler)\r
+{\r
+ pmc_disable_pck1();\r
+ PMC->PMC_PCK[1] = (clock_source & PMC_PCK_CSS_Msk) | PMC_PCK_PRES(prescaler);\r
+}\r
+\r
+void pmc_enable_pck1(void)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK1;\r
+ while (!(PMC->PMC_SR & PMC_SR_PCKRDY1));\r
+}\r
+\r
+void pmc_disable_pck1(void)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCDR_PCK1;\r
+ while (PMC->PMC_SCSR & PMC_SCSR_PCK1);\r
+}\r
+\r
+uint32_t pmc_get_pck1_clock(void)\r
+{\r
+ return _pmc_get_pck_clock(1);\r
+}\r
+\r
+void pmc_configure_pck2(uint32_t clock_source, uint32_t prescaler)\r
+{\r
+ pmc_disable_pck2();\r
+ PMC->PMC_PCK[2] = (clock_source & PMC_PCK_CSS_Msk) | PMC_PCK_PRES(prescaler);\r
+}\r
+\r
+void pmc_enable_pck2(void)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK2;\r
+ while (!(PMC->PMC_SR & PMC_SR_PCKRDY2));\r
+}\r
+\r
+void pmc_disable_pck2(void)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCDR_PCK2;\r
+ while (PMC->PMC_SCSR & PMC_SCSR_PCK2);\r
+}\r
+\r
+uint32_t pmc_get_pck2_clock(void)\r
+{\r
+ return _pmc_get_pck_clock(2);\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions (UPLL)\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void pmc_enable_upll_clock(void)\r
+{\r
+ /* enable 480Mhz UPLL */\r
+ PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3)\r
+ | CKGR_UCKR_BIASCOUNT(0x1);\r
+\r
+ /* wait until UPLL is locked */\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));\r
+}\r
+\r
+void pmc_disable_upll_clock(void)\r
+{\r
+ PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;\r
+}\r
+\r
+uint32_t pmc_get_upll_clock(void)\r
+{\r
+#ifdef SFR_UTMICKTRIM_FREQ_Msk\r
+ uint32_t clktrim = SFR->SFR_UTMICKTRIM & SFR_UTMICKTRIM_FREQ_Msk;\r
+ switch (clktrim) {\r
+ case SFR_UTMICKTRIM_FREQ_16:\r
+ return 30 * BOARD_MAIN_CLOCK_EXT_OSC;\r
+ case SFR_UTMICKTRIM_FREQ_24:\r
+ return 20 * BOARD_MAIN_CLOCK_EXT_OSC;\r
+ default:\r
+ return 40 * BOARD_MAIN_CLOCK_EXT_OSC;\r
+ }\r
+#else\r
+ return 40 * BOARD_MAIN_CLOCK_EXT_OSC;\r
+#endif\r
+}\r
+\r
+void pmc_enable_upll_bias(void)\r
+{\r
+ PMC->CKGR_UCKR |= CKGR_UCKR_BIASEN;\r
+}\r
+\r
+void pmc_disable_upll_bias(void)\r
+{\r
+ PMC->CKGR_UCKR &= ~CKGR_UCKR_BIASEN;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions (Generated clocks)\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef CONFIG_HAVE_PMC_GENERATED_CLOCKS\r
+void pmc_configure_gck(uint32_t id, uint32_t clock_source, uint32_t div)\r
+{\r
+ assert(id > 1 && id < ID_PERIPH_COUNT);\r
+ assert(!(clock_source & ~PMC_PCR_GCKCSS_Msk));\r
+ assert(!(div << PMC_PCR_GCKDIV_Pos & ~PMC_PCR_GCKDIV_Msk));\r
+\r
+ pmc_disable_gck(id);\r
+ PMC->PMC_PCR = PMC_PCR_PID(id);\r
+ volatile uint32_t pcr = PMC->PMC_PCR;\r
+ PMC->PMC_PCR = pcr | (clock_source & PMC_PCR_GCKCSS_Msk) | PMC_PCR_CMD\r
+ | PMC_PCR_GCKDIV(div);\r
+}\r
+\r
+void pmc_enable_gck(uint32_t id)\r
+{\r
+ assert(id > 1 && id < ID_PERIPH_COUNT);\r
+\r
+ PMC->PMC_PCR = PMC_PCR_PID(id);\r
+ volatile uint32_t pcr = PMC->PMC_PCR;\r
+ PMC->PMC_PCR = pcr | PMC_PCR_CMD | PMC_PCR_GCKEN;\r
+ while (!(PMC->PMC_SR & PMC_SR_GCKRDY));\r
+}\r
+\r
+void pmc_disable_gck(uint32_t id)\r
+{\r
+ assert(id > 1 && id < ID_PERIPH_COUNT);\r
+\r
+ PMC->PMC_PCR = PMC_PCR_PID(id);\r
+ volatile uint32_t pcr = PMC->PMC_PCR;\r
+ PMC->PMC_PCR = PMC_PCR_CMD | (pcr & ~PMC_PCR_GCKEN);\r
+}\r
+\r
+uint32_t pmc_get_gck_clock(uint32_t id)\r
+{\r
+ uint32_t clk = 0;\r
+ assert(id > 1 && id < ID_PERIPH_COUNT);\r
+\r
+ PMC->PMC_PCR = PMC_PCR_PID(id);\r
+ volatile uint32_t pcr = PMC->PMC_PCR;\r
+\r
+ switch (pcr & PMC_PCR_GCKCSS_Msk) {\r
+ case PMC_PCR_GCKCSS_SLOW_CLK:\r
+ clk = pmc_get_slow_clock();\r
+ break;\r
+ case PMC_PCR_GCKCSS_MAIN_CLK:\r
+ clk = pmc_get_main_clock();\r
+ break;\r
+ case PMC_PCR_GCKCSS_PLLA_CLK:\r
+ clk = pmc_get_plla_clock();\r
+ break;\r
+ case PMC_PCR_GCKCSS_UPLL_CLK:\r
+ clk = pmc_get_upll_clock();\r
+ break;\r
+ case PMC_PCR_GCKCSS_MCK_CLK:\r
+ clk = pmc_get_master_clock();\r
+ break;\r
+#ifdef CONFIG_HAVE_PMC_AUDIO_CLOCK\r
+ case PMC_PCR_GCKCSS_AUDIO_CLK:\r
+ clk = pmc_get_audio_pmc_clock();\r
+ break;\r
+#endif\r
+ }\r
+\r
+ uint32_t div = (pcr & PMC_PCR_GCKDIV_Msk) >> PMC_PCR_GCKDIV_Pos;\r
+ return ROUND_INT_DIV(clk, div + 1);\r
+}\r
+#endif /* CONFIG_HAVE_PMC_GENERATED_CLOCKS */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions (Audio PLL)\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef CONFIG_HAVE_PMC_AUDIO_CLOCK\r
+void pmc_configure_audio(struct _pmc_audio_cfg *cfg)\r
+{\r
+ /* reset audio clock */\r
+ PMC->PMC_AUDIO_PLL0 &= ~PMC_AUDIO_PLL0_RESETN;\r
+ PMC->PMC_AUDIO_PLL0 |= PMC_AUDIO_PLL0_RESETN;\r
+\r
+ /* configure values */\r
+ uint32_t pll0 = PMC->PMC_AUDIO_PLL0;\r
+ pll0 &= ~PMC_AUDIO_PLL0_ND_Msk;\r
+ pll0 |= cfg->nd << PMC_AUDIO_PLL0_ND_Pos;\r
+ pll0 &= ~PMC_AUDIO_PLL0_QDPMC_Msk;\r
+ pll0 |= cfg->qdpmc << PMC_AUDIO_PLL0_QDPMC_Pos;\r
+ PMC->PMC_AUDIO_PLL0 = pll0;\r
+ uint32_t pll1 = PMC->PMC_AUDIO_PLL1;\r
+ pll1 &= ~PMC_AUDIO_PLL1_DIV_Msk;\r
+ pll1 |= cfg->div << PMC_AUDIO_PLL1_DIV_Pos;\r
+ pll1 &= ~PMC_AUDIO_PLL1_FRACR_Msk;\r
+ pll1 |= cfg->fracr << PMC_AUDIO_PLL1_FRACR_Pos;\r
+ pll1 &= ~PMC_AUDIO_PLL1_QDAUDIO_Msk;\r
+ pll1 |= cfg->qdaudio << PMC_AUDIO_PLL1_QDAUDIO_Pos;\r
+ PMC->PMC_AUDIO_PLL1 = pll1;\r
+}\r
+\r
+void pmc_enable_audio(bool pmc_clock, bool pad_clock)\r
+{\r
+ uint32_t bits = PMC_AUDIO_PLL0_PLLEN | PMC_AUDIO_PLL0_RESETN;\r
+ uint32_t nbits = 0;\r
+\r
+ if (pad_clock)\r
+ bits |= PMC_AUDIO_PLL0_PADEN;\r
+ else\r
+ nbits |= PMC_AUDIO_PLL0_PADEN;\r
+\r
+ if (pmc_clock)\r
+ bits |= PMC_AUDIO_PLL0_PMCEN;\r
+ else\r
+ nbits |= PMC_AUDIO_PLL0_PMCEN;\r
+\r
+ PMC->PMC_AUDIO_PLL0 = (PMC->PMC_AUDIO_PLL0 & ~nbits) | bits;\r
+}\r
+\r
+void pmc_disable_audio()\r
+{\r
+ uint32_t nbits = PMC_AUDIO_PLL0_PLLEN | PMC_AUDIO_PLL0_RESETN |\r
+ PMC_AUDIO_PLL0_PADEN | PMC_AUDIO_PLL0_PMCEN;\r
+ PMC->PMC_AUDIO_PLL0 &= ~nbits;\r
+}\r
+\r
+uint32_t pmc_get_audio_pmc_clock(void)\r
+{\r
+ uint32_t pll0 = PMC->PMC_AUDIO_PLL0;\r
+ uint32_t pll1 = PMC->PMC_AUDIO_PLL1;\r
+\r
+ uint32_t nd = (pll0 & PMC_AUDIO_PLL0_ND_Msk) >> PMC_AUDIO_PLL0_ND_Pos;\r
+ uint32_t fracr = (pll1 & PMC_AUDIO_PLL1_FRACR_Msk) >> PMC_AUDIO_PLL1_FRACR_Pos;\r
+ uint32_t qdpmc = (pll0 & PMC_AUDIO_PLL0_QDPMC_Msk) >> PMC_AUDIO_PLL0_QDPMC_Pos;\r
+\r
+ uint64_t clk = BOARD_MAIN_CLOCK_EXT_OSC;\r
+ clk *= ((nd + 1) << 22) + fracr;\r
+ clk /= 1 << 22;\r
+ clk /= qdpmc + 1;\r
+ return (uint32_t)clk;\r
+}\r
+\r
+uint32_t pmc_get_audio_pad_clock(void)\r
+{\r
+ uint32_t pll0 = PMC->PMC_AUDIO_PLL0;\r
+ uint32_t pll1 = PMC->PMC_AUDIO_PLL1;\r
+\r
+ uint32_t nd = (pll0 & PMC_AUDIO_PLL0_ND_Msk) >> PMC_AUDIO_PLL0_ND_Pos;\r
+ uint32_t fracr = (pll1 & PMC_AUDIO_PLL1_FRACR_Msk) >> PMC_AUDIO_PLL1_FRACR_Pos;\r
+ uint32_t qdaudio = (pll1 & PMC_AUDIO_PLL1_QDAUDIO_Msk) >> PMC_AUDIO_PLL1_QDAUDIO_Pos;\r
+ if (qdaudio == 0)\r
+ return 0;\r
+\r
+ uint32_t div = (pll1 & PMC_AUDIO_PLL1_DIV_Msk) >> PMC_AUDIO_PLL1_DIV_Pos;\r
+ if (div != 2 && div != 3)\r
+ return 0;\r
+\r
+ uint64_t clk = BOARD_MAIN_CLOCK_EXT_OSC;\r
+ clk *= ((nd + 1) << 22) + fracr;\r
+ clk /= 1 << 22;\r
+ clk /= div * qdaudio;\r
+ return (uint32_t)clk;\r
+}\r
+#endif /* CONFIG_HAVE_PMC_AUDIO_CLOCK */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _PMC_H_\r
+#define _PMC_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+struct pck_mck_cfg {\r
+ /** PLL A, SLCK, MAIN, UPLL */\r
+ uint32_t pck_input;\r
+\r
+ /** RC12M (false) or EXT12M (true) */\r
+ bool ext12m;\r
+\r
+ /** RC32K (false) or EXT32K (true) */\r
+ bool ext32k;\r
+\r
+ /** PLLA MUL value in PMC PLL register */\r
+ uint32_t plla_mul;\r
+\r
+ /** PLLA DIV value in PMC PLL register */\r
+ uint32_t plla_div;\r
+\r
+ /** PLLA DIV value by 2 */\r
+ bool plla_div2;\r
+\r
+ /** Master/Processor Clock Prescaler */\r
+ uint32_t pck_pres;\r
+\r
+ /** Master Clock Division after Prescaler divider */\r
+ uint32_t mck_div;\r
+\r
+ /** true if the AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency divided by 2 */\r
+ bool h32mxdiv2;\r
+};\r
+\r
+/**\r
+ * \brief System clock identifiers, used for pmc_{enable,disable}_system_clock\r
+ */\r
+enum _pmc_system_clock {\r
+ PMC_SYSTEM_CLOCK_PCK,\r
+ PMC_SYSTEM_CLOCK_DDR,\r
+ PMC_SYSTEM_CLOCK_LCD,\r
+ PMC_SYSTEM_CLOCK_SMD,\r
+ PMC_SYSTEM_CLOCK_UHP,\r
+ PMC_SYSTEM_CLOCK_UDP,\r
+ PMC_SYSTEM_CLOCK_PCK0,\r
+ PMC_SYSTEM_CLOCK_PCK1,\r
+ PMC_SYSTEM_CLOCK_PCK2,\r
+ PMC_SYSTEM_CLOCK_ISC,\r
+};\r
+\r
+#ifdef CONFIG_HAVE_PMC_AUDIO_CLOCK\r
+/**\r
+ * \brief Configuration data for Audio clock\r
+ *\r
+ * AUDIOPLLCK = BOARD_EXT_OSC * (nd + 1 + (fracr / 2^22)) / (qdpmc + 1)\r
+ * AUDIOPINCLK = BOARD_EXT_OSC * (nc + 1 + (fracr / 2^22)) / (div * qdaudio)\r
+ */\r
+struct _pmc_audio_cfg {\r
+ uint32_t nd;\r
+ uint32_t fracr;\r
+ uint32_t qdpmc;\r
+ uint32_t div;\r
+ uint32_t qdaudio;\r
+};\r
+#endif /* CONFIG_HAVE_PMC_AUDIO_CLOCK */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \brief Configure PCK and MCK with custom setting\r
+ */\r
+extern void pmc_set_custom_pck_mck(struct pck_mck_cfg *cfg);\r
+\r
+/**\r
+ * \brief Get the configured frequency of the master clock\r
+ * \return master clock frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_master_clock(void);\r
+\r
+/**\r
+ * \brief Get the configured frequency of the slow clock\r
+ * \return slow clock frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_slow_clock(void);\r
+\r
+/**\r
+ * \brief Get the configured frequency of the main clock\r
+ * \return main clock frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_main_clock(void);\r
+\r
+/**\r
+ * \brief Get the configured frequency of the PLLA clock\r
+ * \return PLLA clock frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_plla_clock(void);\r
+\r
+/**\r
+ * \brief Get the configured frequency of the processor clock\r
+ * \return processor clock frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_processor_clock(void);\r
+\r
+/**\r
+ * \brief Select external 32K crystal.\r
+ */\r
+extern void pmc_select_external_crystal(void);\r
+\r
+/**\r
+ * \brief Select internal 32K crystal.\r
+ */\r
+extern void pmc_select_internal_crystal(void);\r
+\r
+/**\r
+ * \brief Select external 12M OSC.\r
+ */\r
+extern void pmc_select_external_osc(void);\r
+\r
+/**\r
+ * \brief Disable external 12M OSC.\r
+ */\r
+extern void pmc_disable_external_osc(void);\r
+\r
+/**\r
+ * \brief Select internal 12M OSC.\r
+ */\r
+extern void pmc_select_internal_osc(void);\r
+\r
+/**\r
+ * \brief Disable internal 12M OSC.\r
+ */\r
+extern void pmc_disable_internal_osc(void);\r
+\r
+/**\r
+ * \brief Switch PMC from MCK to PLL clock.\r
+ */\r
+extern void pmc_switch_mck_to_pll(void);\r
+\r
+/**\r
+ * \brief Switch PMC from MCK to UPLL clock.\r
+ */\r
+extern void pmc_switch_mck_to_upll(void);\r
+\r
+/**\r
+ * \brief Switch PMC from MCK to main clock.\r
+ */\r
+extern void pmc_switch_mck_to_main(void);\r
+\r
+/**\r
+ * \brief Switch PMC from MCK to slow clock.\r
+ */\r
+extern void pmc_switch_mck_to_slck(void);\r
+\r
+/**\r
+ * \brief Configure PLL Register.\r
+ * \param pll pll value.\r
+ * \param cpcr cpcr value.\r
+ */\r
+extern void pmc_set_plla(uint32_t pll, uint32_t cpcr);\r
+\r
+/**\r
+ * \brief Configure MCK Prescaler.\r
+ * \param prescaler prescaler value.\r
+ */\r
+extern void pmc_set_mck_prescaler(uint32_t prescaler);\r
+\r
+/**\r
+ * \brief Configure MCK Divider.\r
+ * \param divider divider value.\r
+ */\r
+extern void pmc_set_mck_divider(uint32_t divider);\r
+\r
+/**\r
+ * \brief Configure MCK H32MXDIV.\r
+ * \param divider divider value.\r
+ */\r
+extern void pmc_set_mck_h32mxdiv(uint32_t divider);\r
+\r
+/**\r
+ * \brief Configure MCK PLLA divider.\r
+ * \param divider PLL divider value.\r
+ */\r
+extern void pmc_set_mck_plla_div(uint32_t divider);\r
+\r
+/**\r
+ * \brief Disable PLLA Register.\r
+ */\r
+extern void pmc_disable_plla(void);\r
+\r
+/**\r
+ * \brief Enables a system clock\r
+ * \param clock system clock to enable\r
+ */\r
+extern void pmc_enable_system_clock(enum _pmc_system_clock clock);\r
+\r
+/**\r
+ * \brief Disables a system clock\r
+ * \param clock system clock to disable\r
+ */\r
+extern void pmc_disable_system_clock(enum _pmc_system_clock clock);\r
+\r
+#ifdef CONFIG_HAVE_PMC_FAST_STARTUP\r
+/**\r
+ * \brief Set up fast startup mode\r
+ * \param source and low power mode\r
+ */\r
+extern void pmc_set_fast_startup_mode(uint32_t startup_mode);\r
+\r
+/**\r
+ * \brief Set up fast startup polarity\r
+ * \param level\r
+ */\r
+extern void pmc_set_fast_startup_polarity(uint32_t high_level,\r
+ uint32_t low_level);\r
+#endif /* CONFIG_HAVE_PMC_FAST_STARTUP */\r
+\r
+/**\r
+ * \brief Enables the clock of a peripheral. The peripheral ID is used\r
+ * to identify which peripheral is targeted.\r
+ *\r
+ * \param id Peripheral ID (ID_xxx).\r
+ */\r
+extern void pmc_enable_peripheral(uint32_t id);\r
+\r
+/**\r
+ * \brief Disables the clock of a peripheral. The peripheral ID is used\r
+ * to identify which peripheral is targeted.\r
+ *\r
+ * \param id Peripheral ID (ID_xxx).\r
+ */\r
+extern void pmc_disable_peripheral(uint32_t id);\r
+\r
+/**\r
+ * \brief Get Peripheral Status for the given peripheral ID.\r
+ *\r
+ * \param id Peripheral ID (ID_xxx).\r
+ */\r
+extern uint32_t pmc_is_peripheral_enabled(uint32_t id);\r
+\r
+/**\r
+ * \brief Get current frequency clock for the given peripheral ID.\r
+ *\r
+ * \param id Peripheral ID (ID_xxx).\r
+ */\r
+extern uint32_t pmc_get_peripheral_clock(uint32_t id);\r
+\r
+/**\r
+ * \brief Disable clocks for all peripherals\r
+ */\r
+extern void pmc_disable_all_peripherals(void);\r
+\r
+/**\r
+ * \brief Configure programmable clock 0 (PCK0) with the given master clock\r
+ * source and clock prescaler\r
+ * \param clock_source clock source selection (one of the PMC_PCK_CSS_xxx_CLK\r
+ * constants)\r
+ * \param prescaler prescaler\r
+ */\r
+extern void pmc_configure_pck0(uint32_t clock_source, uint32_t prescaler);\r
+\r
+/**\r
+ * \brief Enable programmable clock 0 (PCK0)\r
+ */\r
+extern void pmc_enable_pck0(void);\r
+\r
+/**\r
+ * \brief Disable programmable clock 0 (PCK0)\r
+ */\r
+extern void pmc_disable_pck0(void);\r
+\r
+/**\r
+ * \brief Get the frequency of the programmable clock 0 (PCK0)\r
+ * \return PCK0 frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_pck0_clock(void);\r
+\r
+/**\r
+ * \brief Configure programmable clock 1 (PCK1) with the given master clock\r
+ * source and clock prescaler\r
+ * \param clock_source Clock source selection (one of the PMC_PCK_CSS_xxx_CLK\r
+ * constants)\r
+ * \param prescaler Prescaler value\r
+ */\r
+extern void pmc_configure_pck1(uint32_t clock_source, uint32_t prescaler);\r
+\r
+/**\r
+ * \brief Enable programmable clock 1 (PCK1)\r
+ */\r
+extern void pmc_enable_pck1(void);\r
+\r
+/**\r
+ * \brief Disable programmable clock 1 (PCK1)\r
+ */\r
+extern void pmc_disable_pck1(void);\r
+\r
+/**\r
+ * \brief Get the frequency of the programmable clock 1 (PCK1)\r
+ * \return PCK1 Frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_pck1_clock(void);\r
+\r
+/**\r
+ * \brief Configure programmable clock 2 (PCK2) with the given master clock\r
+ * source and clock prescaler\r
+ * \param clock_source Clock source selection (one of the PMC_PCK_CSS_xxx_CLK\r
+ * constants)\r
+ * \param prescaler Prescaler value\r
+ */\r
+extern void pmc_configure_pck2(uint32_t clock_source, uint32_t prescaler);\r
+\r
+/**\r
+ * \brief Enable programmable clock 2 (PCK2)\r
+ */\r
+extern void pmc_enable_pck2(void);\r
+\r
+/**\r
+ * \brief Disable programmable clock 2 (PCK2)\r
+ */\r
+extern void pmc_disable_pck2(void);\r
+\r
+/**\r
+ * \brief Get the frequency of the programmable clock 2 (PCK2)\r
+ * \return PCK2 Frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_pck2_clock(void);\r
+\r
+/**\r
+ * \brief Enable the UPLL clock\r
+ */\r
+extern void pmc_enable_upll_clock(void);\r
+\r
+/**\r
+ * \brief Disable the UPLL clock\r
+ */\r
+extern void pmc_disable_upll_clock(void);\r
+\r
+/**\r
+ * \brief Get the frequency of the UPLL clock\r
+ * \return UPLL clock frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_upll_clock(void);\r
+\r
+/**\r
+ * \brief Enable the UPLL clock bias\r
+ */\r
+extern void pmc_enable_upll_bias(void);\r
+\r
+/**\r
+ * \brief Disable the UPLL clock bias\r
+ */\r
+extern void pmc_disable_upll_bias(void);\r
+\r
+#ifdef CONFIG_HAVE_PMC_GENERATED_CLOCKS\r
+/**\r
+ * \brief Configure the generated clock (GCK) for the given peripheral with the\r
+ * given master clock source and clock prescaler\r
+ * \param id Peripheral ID (ID_xxx)\r
+ * \param clock_source Clock source selection (one of the\r
+ * PMC_PCR_GCKCSS_xxx_CLK constants)\r
+ * \param div Generated Clock Division Ratio (selected clock is divided by\r
+ * div + 1)\r
+ */\r
+extern void pmc_configure_gck(uint32_t id, uint32_t clock_source, uint32_t div);\r
+\r
+/**\r
+ * \brief Enable generated clock for the given peripheral\r
+ * \param id Peripheral ID (ID_xxx)\r
+ */\r
+extern void pmc_enable_gck(uint32_t id);\r
+\r
+/**\r
+ * \brief Disable generated clock for the given peripheral\r
+ * \param id Peripheral ID (ID_xxx)\r
+ */\r
+extern void pmc_disable_gck(uint32_t id);\r
+\r
+/**\r
+ * \brief Get the frequency of the generated clock (GCK) for the given\r
+ * peripheral\r
+ * \param id Peripheral ID (ID_xxx)\r
+ * \return GCK Frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_gck_clock(uint32_t id);\r
+#endif /* CONFIG_HAVE_PMC_GENERATED_CLOCKS */\r
+\r
+#ifdef CONFIG_HAVE_PMC_AUDIO_CLOCK\r
+/**\r
+ * \brief Configure the audio clock\r
+ */\r
+extern void pmc_configure_audio(struct _pmc_audio_cfg *cfg);\r
+\r
+/**\r
+ * \brief Enable audio clocks\r
+ * \param pmc_clock if true AUDIOPLLCK is sent to the PMC\r
+ * \param pad_clock if true the external audio pin is driven by AUDIOPINCLK, if\r
+ * false the audio pin is driven low\r
+ */\r
+extern void pmc_enable_audio(bool pmc_clock, bool pad_clock);\r
+\r
+/**\r
+ * \brief Disable audio clocks\r
+ */\r
+extern void pmc_disable_audio(void);\r
+\r
+/**\r
+ * \brief Get the frequency of the audio PMC clock\r
+ * \return Audio PMC Frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_audio_pmc_clock(void);\r
+\r
+/**\r
+ * \brief Get the frequency of the audio pad clock\r
+ * \return Audio pad Frequency in Hz\r
+ */\r
+extern uint32_t pmc_get_audio_pad_clock(void);\r
+#endif /* CONFIG_HAVE_PMC_AUDIO_CLOCK */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* #ifndef _PMC_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2012, Atmel Corporation\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "trace.h"\r
+\r
+#include "peripherals/pmecc.h"\r
+#include "peripherals/pmecc_gallois_field_512.h"\r
+#include "peripherals/pmecc_gallois_field_1024.h"\r
+\r
+/*--------------------------------------------------------------------------- */\r
+/* Local types */\r
+/*--------------------------------------------------------------------------- */\r
+\r
+/** PMECC configuration descriptor */\r
+struct _pmecc_descriptor {\r
+ /** Number of Sectors in one Page */\r
+ uint32_t page_size;\r
+\r
+ /** The spare area size is equal to (SPARESIZE+1) bytes */\r
+ uint32_t spare_size;\r
+\r
+ /** 0 for 512, 1 for 1024 bytes, like in PMECCFG register */\r
+ uint32_t sector_size;\r
+\r
+ /** Coded value of ECC bit number correction\r
+ * 0 (2 bits), 1 (4 bits), 2 (8 bits), 3 (12 bits), 4 (24 bits), 5 (NU)) */\r
+ uint32_t err_bit_nbr_capability;\r
+\r
+ /** Real size in bytes of ECC in spare */\r
+ uint32_t ecc_size_byte;\r
+\r
+ /** The first byte address of the ECC area */\r
+ uint32_t ecc_start_address;\r
+\r
+ /** The last byte address of the ECC area */\r
+ uint32_t ecc_end_address;\r
+\r
+ /** NAND Write Access*/\r
+ uint32_t nand_wr;\r
+\r
+ /** Spare Enable */\r
+ uint32_t spare_ena;\r
+\r
+ /** Automatic Mode */\r
+ uint32_t mode_auto;\r
+\r
+ /** The PMECC Module data path Setup Time is set to CLKCTRL+1. */\r
+ uint32_t clk_ctrl;\r
+\r
+ /** */\r
+ uint32_t interrupt;\r
+\r
+ /** defines the error correcting capability selected at encoding/decoding time */\r
+ int32_t tt;\r
+\r
+ /** degree of the remainders, GF(2**mm) */\r
+ int32_t mm;\r
+\r
+ /** length of codeword = nn=2**mm -1 */\r
+ int32_t nn;\r
+\r
+ /** Gallois field table */\r
+ const int16_t *alpha_to;\r
+\r
+ /** Index of Gallois field table */\r
+ const int16_t *index_of;\r
+\r
+ /** */\r
+ int16_t partial_syn[100];\r
+\r
+ /** Holds the current syndrome value, an element of that table belongs to the field.*/\r
+ int16_t si[100];\r
+\r
+ /** sigma table */\r
+ int16_t smu[PMECC_NB_ERROR_MAX + 2][2 * PMECC_NB_ERROR_MAX + 1];\r
+\r
+ /** polynom order */\r
+ int16_t lmu[PMECC_NB_ERROR_MAX + 1];\r
+};\r
+\r
+/*--------------------------------------------------------------------------- */\r
+/* Local variables */\r
+/*--------------------------------------------------------------------------- */\r
+\r
+/** Pmecc decriptor instance */\r
+struct _pmecc_descriptor pmecc_desc;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+ /**\r
+ * \brief Build the pseudo syndromes table\r
+ * \param sector Targetted sector.\r
+ */\r
+static void gen_syn(uint32_t sector)\r
+{\r
+ int16_t *remainer;\r
+ uint32_t index;\r
+\r
+ remainer = (int16_t*)&HSMC->SMC_REM[sector];\r
+ for (index = 0; index < (uint32_t)pmecc_desc.tt; index++) {\r
+ /* Fill odd syndromes */\r
+ pmecc_desc.partial_syn[1 + (2 * index)] = remainer[index];\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief The substitute function evaluates the polynomial remainder,\r
+ * with different values of the field primitive elements.\r
+ */\r
+static uint32_t substitute(void)\r
+{\r
+ int32_t i, j;\r
+ int16_t *si;\r
+ int16_t *p_partial_syn = pmecc_desc.partial_syn;\r
+ const int16_t *alpha_to = pmecc_desc.alpha_to;\r
+ const int16_t *index_of = pmecc_desc.index_of;\r
+\r
+ /* si[] is a table that holds the current syndrome value, an element of that table belongs to the field.*/\r
+ si = pmecc_desc.si;\r
+\r
+ for (i = 1; i < 2 * PMECC_NB_ERROR_MAX; i++)\r
+ si[i] = 0;\r
+\r
+ /* Computation 2t syndromes based on S(x) */\r
+ /* Odd syndromes */\r
+ for (i = 1; i <= 2 * pmecc_desc.tt - 1; i = i + 2) {\r
+ si[i] = 0;\r
+ for (j = 0; j < pmecc_desc.mm; j++) {\r
+ if (p_partial_syn[i] & ((uint16_t)0x1 << j))\r
+ si[i] = alpha_to[(i * j)] ^ si[i];\r
+ }\r
+ }\r
+ /* Even syndrome = (Odd syndrome) ** 2 */\r
+ for (i = 2; i <= 2 * pmecc_desc.tt; i = i + 2) {\r
+ j = i / 2;\r
+ if (si[j] == 0) {\r
+ si[i] = 0;\r
+ } else {\r
+ si[i] = alpha_to[(2 * index_of[si[j]]) % pmecc_desc.nn];\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief The substitute function finding the value of the error\r
+ * location polynomial.\r
+ */\r
+static uint32_t get_sigma(void)\r
+{\r
+ uint32_t dmu_0_count;\r
+ int32_t i, j, k;\r
+ int16_t *lmu = pmecc_desc.lmu;\r
+ int16_t *si = pmecc_desc.si;\r
+ int16_t tt = pmecc_desc.tt;\r
+\r
+ int32_t mu[PMECC_NB_ERROR_MAX+1]; /* mu */\r
+ int32_t dmu[PMECC_NB_ERROR_MAX+1]; /* discrepancy */\r
+ int32_t delta[PMECC_NB_ERROR_MAX+1]; /* delta order */\r
+ int32_t ro; /* index of largest delta */\r
+ int32_t largest;\r
+ int32_t diff;\r
+\r
+ dmu_0_count = 0;\r
+\r
+ /* -- First Row -- */\r
+\r
+ /* Mu */\r
+ mu[0] = -1;\r
+ /* Actually -1/2 */\r
+ /* Sigma(x) set to 1 */\r
+\r
+ for (i = 0; i < (2 * PMECC_NB_ERROR_MAX + 1); i++)\r
+ pmecc_desc.smu[0][i] = 0;\r
+ pmecc_desc.smu[0][0] = 1;\r
+\r
+ /* discrepancy set to 1 */\r
+ dmu[0] = 1;\r
+\r
+ /* polynom order set to 0 */\r
+ lmu[0] = 0;\r
+\r
+ /* delta set to -1 */\r
+ delta[0] = (mu[0] * 2 - lmu[0]) >> 1;\r
+\r
+ /* -- Second Row -- */\r
+\r
+ /* Mu */\r
+ mu[1] = 0;\r
+\r
+ /* Sigma(x) set to 1 */\r
+ for (i = 0; i < (2 * PMECC_NB_ERROR_MAX + 1); i++)\r
+ pmecc_desc.smu[1][i] = 0;\r
+ pmecc_desc.smu[1][0] = 1;\r
+\r
+ /* discrepancy set to S1 */\r
+ dmu[1] = si[1];\r
+\r
+ /* polynom order set to 0 */\r
+ lmu[1] = 0;\r
+\r
+ /* delta set to 0 */\r
+ delta[1] = (mu[1] * 2 - lmu[1]) >> 1;\r
+\r
+ /* Init the Sigma(x) last row */\r
+ for (i = 0; i < (2 * PMECC_NB_ERROR_MAX + 1); i++)\r
+ pmecc_desc.smu[tt + 1][i] = 0;\r
+\r
+ for (i = 1; i <= tt; i++) {\r
+ mu[i+1] = i << 1;\r
+\r
+ /* Compute Sigma (Mu+1) */\r
+ /* And L(mu) */\r
+ /* check if discrepancy is set to 0 */\r
+ if ( dmu[i] == 0) {\r
+ dmu_0_count++;\r
+ if (( tt - (lmu[i] >> 1) - 1) & 0x1) {\r
+ if (dmu_0_count == (uint32_t)((tt - (lmu[i] >> 1) - 1) / 2) + 2) {\r
+ for (j = 0; j <= (lmu[i] >> 1) + 1; j++)\r
+ pmecc_desc.smu[tt+1][j] = pmecc_desc.smu[i][j];\r
+ lmu[tt + 1] = lmu[i];\r
+ return 0;\r
+ }\r
+ } else {\r
+ if (dmu_0_count == (uint32_t)((tt - (lmu[i] >> 1) - 1) / 2) + 1) {\r
+ for (j = 0; j <= (lmu[i] >> 1) + 1; j++)\r
+ pmecc_desc.smu[tt + 1][j] = pmecc_desc.smu[i][j];\r
+ lmu[tt + 1] = lmu[i];\r
+ return 0;\r
+ }\r
+ }\r
+\r
+ /* copy polynom */\r
+ for (j = 0; j <= (lmu[i] >> 1); j++)\r
+ pmecc_desc.smu[i + 1][j] = pmecc_desc.smu[i][j];\r
+\r
+ /* copy previous polynom order to the next */\r
+ lmu[i + 1] = lmu[i];\r
+ } else {\r
+ /* find largest delta with dmu != 0 */\r
+ ro = 0;\r
+ largest = -1;\r
+ for (j = 0; j < i; j++) {\r
+ if (dmu[j]) {\r
+ if (delta[j] > largest) {\r
+ largest = delta[j];\r
+ ro = j;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* compute difference */\r
+ diff = (mu[i] - mu[ro]);\r
+\r
+ /* Compute degree of the new smu polynomial */\r
+ if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))\r
+ lmu[i + 1] = lmu[i];\r
+ else\r
+ lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;\r
+\r
+ /* Init smu[i+1] with 0 */\r
+ for (k = 0; k < (2 * PMECC_NB_ERROR_MAX + 1); k++)\r
+ pmecc_desc.smu[i+1][k] = 0;\r
+\r
+ /* Compute smu[i+1] */\r
+ for (k = 0; k <= (lmu[ro] >> 1); k++) {\r
+ if (pmecc_desc.smu[ro][k] && dmu[i])\r
+ pmecc_desc.smu[i + 1][k + diff] = pmecc_desc.alpha_to[(pmecc_desc.index_of[dmu[i]] +\r
+ (pmecc_desc.nn - pmecc_desc.index_of[dmu[ro]]) +\r
+ pmecc_desc.index_of[pmecc_desc.smu[ro][k]]) % pmecc_desc.nn];\r
+ }\r
+ for (k = 0; k <= (lmu[i] >> 1); k++)\r
+ pmecc_desc.smu[i+1][k] ^= pmecc_desc.smu[i][k];\r
+ }\r
+\r
+ /*************************************************/\r
+ /* End Compute Sigma (Mu+1) */\r
+ /* And L(mu) */\r
+ /*************************************************/\r
+ /* In either case compute delta */\r
+ delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;\r
+\r
+ /* Do not compute discrepancy for the last iteration */\r
+ if (i < tt) {\r
+ for (k = 0 ; k <= (lmu[i + 1] >> 1); k++) {\r
+ if (k == 0)\r
+ dmu[i + 1] = si[2 * (i - 1) + 3];\r
+ /* check if one operand of the multiplier is null, its index is -1 */\r
+ else if (pmecc_desc.smu[i+1][k] && si[2 * (i - 1) + 3 - k])\r
+ dmu[i + 1] = pmecc_desc.alpha_to[(pmecc_desc.index_of[pmecc_desc.smu[i + 1][k]] +\r
+ pmecc_desc.index_of[si[2 * (i - 1) + 3 - k]]) % pmecc_desc.nn] ^ dmu[i + 1];\r
+ }\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Init the PMECC Error Location peripheral and start the error\r
+ * location processing\r
+ * \param sector_size_in_bits Size of the sector in bits.\r
+ * \return Number of errors\r
+ */\r
+static int32_t error_location (uint32_t sector_size_in_bits)\r
+{\r
+ uint32_t alphax;\r
+ uint32_t *sigma;\r
+ uint32_t error_number;\r
+ uint32_t nbr_of_roots;\r
+\r
+ /* Disable PMECC Error Location IP */\r
+ HSMC->HSMC_ELDIS |= 0xFFFFFFFF;\r
+ error_number = 0;\r
+ alphax = 0;\r
+\r
+ sigma = (uint32_t*)&HSMC->HSMC_SIGMA0;\r
+\r
+ for (alphax = 0; alphax <= (uint32_t)(pmecc_desc.lmu[pmecc_desc.tt + 1] >> 1); alphax++) {\r
+ *sigma++ = pmecc_desc.smu[pmecc_desc.tt + 1][alphax];\r
+ error_number++;\r
+ }\r
+\r
+ /* Enable error location process */\r
+ HSMC->HSMC_ELCFG |= ((error_number - 1) << 16);\r
+ HSMC->HSMC_ELEN = sector_size_in_bits;\r
+\r
+ while ((HSMC->HSMC_ELISR & HSMC_ELISR_DONE) == 0);\r
+\r
+ nbr_of_roots = (HSMC->HSMC_ELISR & HSMC_ELISR_ERR_CNT_Msk) >> 8;\r
+ /* Number of roots == degree of smu hence <= tt */\r
+ if (nbr_of_roots == (uint32_t)(pmecc_desc.lmu[pmecc_desc.tt + 1] >> 1))\r
+ return (error_number - 1);\r
+\r
+ /* Number of roots not match the degree of smu ==> unable to correct error */\r
+ return -1;\r
+}\r
+\r
+/**\r
+ * \brief Correct errors indicated in the PMECCEL error location registers.\r
+ * \param sector_base_address Base address of the sector.\r
+ * \param extra_bytes Number of extra bytes of the sector.(encoded Spare Area, only for the last sector)\r
+ * \param error_nbr Number of error to correct\r
+ * \return Number of errors\r
+ */\r
+static uint32_t error_correction(uint32_t sector_base_address, uint32_t extra_bytes, uint32_t error_nbr)\r
+{\r
+ uint32_t *error_pos;\r
+ uint32_t byte_pos;\r
+ uint32_t bit_pos;\r
+ uint32_t sector_size;\r
+ uint32_t ecc_size;\r
+ uint32_t ecc_end_addr;\r
+\r
+ error_pos = (uint32_t*)&HSMC->HSMC_ERRLOC0;\r
+\r
+ sector_size = 512 * (((HSMC->HSMC_PMECCFG & HSMC_PMECCFG_SECTORSZ) >> 4) + 1);\r
+\r
+ /* Get number of ECC bytes */\r
+ ecc_end_addr = HSMC->HSMC_PMECCEADDR;\r
+ ecc_size = (ecc_end_addr - HSMC->HSMC_PMECCSADDR) + 1;\r
+\r
+ while (error_nbr) {\r
+ byte_pos = (*error_pos - 1) / 8;\r
+ bit_pos = (*error_pos - 1) % 8;\r
+\r
+ /* If error is located in the data area(not in ECC) */\r
+ if ( byte_pos < (sector_size + extra_bytes)) {\r
+ uint8_t *data_ptr = NULL;\r
+\r
+ /* If the error position is before ECC area */\r
+ if ( byte_pos < sector_size + HSMC->HSMC_PMECCSADDR) {\r
+ data_ptr = (uint8_t*)(sector_base_address + byte_pos);\r
+ } else {\r
+ data_ptr = (uint8_t*)(sector_base_address + byte_pos + ecc_size);\r
+ }\r
+\r
+ trace_info("Correct error bit @[#Byte %u,Bit# %u]\n\r",\r
+ (unsigned)byte_pos, (unsigned)bit_pos);\r
+\r
+ if (*data_ptr & (1 << bit_pos))\r
+ *data_ptr &= (0xFF ^ (1 << bit_pos));\r
+ else\r
+ *data_ptr |= (1 << bit_pos);\r
+ }\r
+ error_pos++;\r
+ error_nbr--;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure the PMECC peripheral\r
+ * \param pPmeccDescriptor Pointer to a PmeccDescriptor instance.\r
+ */\r
+static void _pmecc_configure(void)\r
+{\r
+ /* Disable ECC module */\r
+ HSMC->HSMC_PMECCTRL |= HSMC_PMECCTRL_DISABLE;\r
+\r
+ /* Reset the ECC module */\r
+ HSMC->HSMC_PMECCTRL = HSMC_PMECCTRL_RST;\r
+ HSMC->HSMC_PMECCFG = pmecc_desc.err_bit_nbr_capability |\r
+ pmecc_desc.sector_size |\r
+ pmecc_desc.page_size |\r
+ pmecc_desc.nand_wr |\r
+ pmecc_desc.spare_ena |\r
+ pmecc_desc.mode_auto;\r
+ HSMC->HSMC_PMECCSAREA = pmecc_desc.spare_size - 1;\r
+ HSMC->HSMC_PMECCSADDR = pmecc_desc.ecc_start_address;\r
+ HSMC->HSMC_PMECCEADDR = pmecc_desc.ecc_end_address - 1;\r
+\r
+ /* Disable all interrupts */\r
+ HSMC->HSMC_PMECCIDR = 0xFF;\r
+\r
+ /* Enable ECC module */\r
+ HSMC->HSMC_PMECCTRL |= HSMC_PMECCTRL_ENABLE;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Export functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief This function is able to build Galois Field.\r
+ * \param mm degree of the remainders.\r
+ * \param index_of Pointer to a buffer for index_of table.\r
+ * \param alpha_to Pointer to a buffer for alpha_to table.\r
+ */\r
+void build_gf(uint32_t mm, int32_t* index_of, int32_t* alpha_to)\r
+{\r
+ uint32_t i;\r
+ uint32_t mask;\r
+ uint32_t nn;\r
+ uint32_t p[15];\r
+\r
+ nn = (1 << mm) - 1;\r
+ /* set default value */\r
+ for (i = 1; i < mm; i++)\r
+ p[i] = 0;\r
+\r
+ /* 1 + X^mm */\r
+ p[0] = 1;\r
+ p[mm] = 1;\r
+\r
+ /* others */\r
+ if (mm == 3)\r
+ p[1] = 1;\r
+ else if (mm == 4)\r
+ p[1] = 1;\r
+ else if (mm == 5)\r
+ p[2] = 1;\r
+ else if (mm == 6)\r
+ p[1] = 1;\r
+ else if (mm == 7)\r
+ p[3] = 1;\r
+ else if (mm == 8)\r
+ p[2] = p[3] = p[4] = 1;\r
+ else if (mm == 9)\r
+ p[4] = 1;\r
+ else if (mm == 10)\r
+ p[3] = 1;\r
+ else if (mm == 11)\r
+ p[2] = 1;\r
+ else if (mm == 12)\r
+ p[1] = p[4] = p[6] = 1;\r
+ else if (mm == 13)\r
+ p[1] = p[3] = p[4] = 1;\r
+ else if (mm == 14)\r
+ p[1] = p[6] = p[10] = 1;\r
+ else if (mm == 15)\r
+ p[1] = 1;\r
+\r
+ /*-- First of All */\r
+ /*-- build alpha ^ mm it will help to generate the field (primitiv) */\r
+ alpha_to[mm] = 0;\r
+ for (i = 0; i < mm; i++)\r
+ if (p[i])\r
+ alpha_to[mm] |= 1 << i;\r
+\r
+ /* Secondly */\r
+ /* Build elements from 0 to mm - 1 */\r
+ /* very easy because degree is less than mm so it is */\r
+ /* just a logical shift ! (only the remainder) */\r
+ mask = 1;\r
+ for (i = 0; i < mm; i++) {\r
+ alpha_to[i] = mask;\r
+ index_of[alpha_to[i]] = i;\r
+ mask <<= 1;\r
+ }\r
+\r
+ index_of[alpha_to[mm]] = mm;\r
+\r
+ /* use a mask to select the MSB bit of the */\r
+ /* LFSR ! */\r
+ mask >>= 1; /* previous value moust be decremented */\r
+\r
+ /* then finish the building */\r
+ for (i = mm + 1; i <= nn; i++) {\r
+ /* check if the msb bit of the lfsr is set */\r
+ if (alpha_to[i-1] & mask)\r
+ /* feedback loop is set */\r
+ alpha_to[i] = alpha_to[mm] ^ ((alpha_to[i-1] ^ mask) << 1);\r
+ else\r
+ /* only shift is enabled */\r
+ alpha_to[i] = alpha_to[i-1] << 1;\r
+ /* lookup table */\r
+ //index_of[alpha_to[i]] = i ;\r
+ index_of[alpha_to[i]] = i%nn ;\r
+ }\r
+ /* of course index of 0 is undefined in a multiplicative field */\r
+ index_of[0] = -1;\r
+}\r
+\r
+/**\r
+ * \brief Initialize the PMECC peripheral\r
+ * \param sector_size 0 for 512, 1 for 1024.\r
+ * \param ecc_errors_per_sector Coded value of ECC bit number correction(2,4,8,12,24).\r
+ * \param page_data_size Data area size in byte.\r
+ * \param page_spare_size Spare area size in byte.\r
+ * \param ecc_offset_in_spare offset of the first ecc byte in spare zone.\r
+ * \param spare_protected 1: The spare area is protected with the last sector of data.\r
+ * 0: The spare area is skipped in read or write mode.\r
+ * \return 0 if successful; otherwise returns 1.\r
+ */\r
+uint8_t pmecc_initialize(uint8_t sector_size , uint8_t ecc_errors_per_sector,\r
+ uint32_t page_data_size, uint32_t page_spare_size,\r
+ uint16_t ecc_offset_in_spare, uint8_t spare_protected)\r
+{\r
+ uint8_t nb_sectors_per_page = 0;\r
+\r
+ if (ecc_errors_per_sector == 0xFF) {\r
+ /* ONFI 2.2 : a value of 0xff indaicate we must apply a correction on sector > 512 bytes,\r
+ so we set at the maximum allowed by PMECC 24 bits on 1024 sectors. */\r
+ ecc_errors_per_sector = 24;\r
+ sector_size = 1; /* 1 for 1024 bytes per sector */\r
+ }\r
+\r
+ /* Number of Sectors in one Page */\r
+ switch (sector_size) {\r
+ /* 512 bytes per sector */\r
+ case 0:\r
+ pmecc_desc.sector_size = 0;\r
+ nb_sectors_per_page = page_data_size / 512;\r
+ pmecc_desc.mm = 13;\r
+ pmecc_get_gf_512_tables(&pmecc_desc.alpha_to, &pmecc_desc.index_of);\r
+ break;\r
+\r
+ /* 1024 bytes per sector */\r
+ case 1:\r
+ pmecc_desc.sector_size = HSMC_PMECCFG_SECTORSZ;\r
+ nb_sectors_per_page = page_data_size / 1024;\r
+ pmecc_desc.mm = 14;\r
+ pmecc_get_gf_1024_tables(&pmecc_desc.alpha_to, &pmecc_desc.index_of);\r
+ break;\r
+ }\r
+\r
+ switch (nb_sectors_per_page) {\r
+ case 1:\r
+ pmecc_desc.page_size = HSMC_PMECCFG_PAGESIZE_PAGESIZE_1SEC;\r
+ break;\r
+ case 2:\r
+ pmecc_desc.page_size = HSMC_PMECCFG_PAGESIZE_PAGESIZE_2SEC;\r
+ break;\r
+ case 4:\r
+ pmecc_desc.page_size = HSMC_PMECCFG_PAGESIZE_PAGESIZE_4SEC;\r
+ break;\r
+ case 8:\r
+ pmecc_desc.page_size = HSMC_PMECCFG_PAGESIZE_PAGESIZE_8SEC;\r
+ break;\r
+ default :\r
+ pmecc_desc.page_size = HSMC_PMECCFG_PAGESIZE_PAGESIZE_1SEC;\r
+ break;\r
+ }\r
+\r
+ pmecc_desc.nn = (1 << pmecc_desc.mm) - 1;\r
+\r
+ /* Coded value of ECC bit number correction (0 (2 bits), 1 (4 bits), 2 (8 bits), 3 (12 bits), 4 (24 bits), 5 (NU)) */\r
+ switch (ecc_errors_per_sector) {\r
+ case 2:\r
+ pmecc_desc.err_bit_nbr_capability = HSMC_PMECCFG_BCH_ERR_BCH_ERR2;\r
+ break;\r
+ case 4:\r
+ pmecc_desc.err_bit_nbr_capability = HSMC_PMECCFG_BCH_ERR_BCH_ERR4;\r
+ break;\r
+ case 8:\r
+ pmecc_desc.err_bit_nbr_capability = HSMC_PMECCFG_BCH_ERR_BCH_ERR8;\r
+ break;\r
+ case 12:\r
+ pmecc_desc.err_bit_nbr_capability = HSMC_PMECCFG_BCH_ERR_BCH_ERR12;\r
+ break;\r
+ case 24:\r
+ pmecc_desc.err_bit_nbr_capability = HSMC_PMECCFG_BCH_ERR_BCH_ERR24;\r
+ break;\r
+ default:\r
+ pmecc_desc.err_bit_nbr_capability = HSMC_PMECCFG_BCH_ERR_BCH_ERR2;\r
+ ecc_errors_per_sector = 2;\r
+ break;\r
+ }\r
+\r
+ /* Real value of ECC bit number correction (2, 4, 8, 12, 24) */\r
+ pmecc_desc.tt = ecc_errors_per_sector;\r
+ if (((pmecc_desc.mm * ecc_errors_per_sector ) % 8 ) == 0) {\r
+ pmecc_desc.ecc_size_byte = ((pmecc_desc.mm * ecc_errors_per_sector ) / 8) * nb_sectors_per_page;\r
+ } else {\r
+ pmecc_desc.ecc_size_byte = (((pmecc_desc.mm * ecc_errors_per_sector ) / 8 ) + 1 ) * nb_sectors_per_page;\r
+ }\r
+ if (ecc_offset_in_spare <= 2) {\r
+ pmecc_desc.ecc_start_address = PMECC_ECC_DEFAULT_START_ADDR;\r
+ } else {\r
+ pmecc_desc.ecc_start_address = ecc_offset_in_spare;\r
+ }\r
+ pmecc_desc.ecc_end_address = pmecc_desc.ecc_start_address + pmecc_desc.ecc_size_byte;\r
+ if (pmecc_desc.ecc_end_address > page_spare_size) {\r
+ return 1;\r
+ }\r
+ pmecc_desc.spare_size = pmecc_desc.ecc_end_address;\r
+\r
+ //pmecc_desc.nand_wr = PMECC_CFG_NANDWR; /* NAND write access */\r
+ pmecc_desc.nand_wr = 0; /* NAND Read access */\r
+ if (spare_protected) {\r
+ pmecc_desc.spare_ena = HSMC_PMECCFG_SPAREEN;\r
+ } else {\r
+ pmecc_desc.spare_ena = 0;\r
+ }\r
+ /* PMECC_CFG_AUTO indicates that the spare is error protected. In this case, the ECC computation takes into account the whole spare area\r
+ minus the ECC area in the ECC computation operation */\r
+ pmecc_desc.mode_auto = 0;\r
+ /* At 133 Mhz, this field must be programmed with 2,\r
+ indicating that the setup time is 3 clock cycles.*/\r
+ pmecc_desc.clk_ctrl = 2;\r
+ pmecc_desc.interrupt = 0;\r
+ _pmecc_configure();\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Return PMECC page size.\r
+ */\r
+uint32_t pmecc_get_page_size(void)\r
+{\r
+ return pmecc_desc.page_size;\r
+}\r
+\r
+/**\r
+ * \brief Return PMECC ecc size.\r
+ */\r
+uint32_t pmecc_get_ecc_bytes(void)\r
+{\r
+ return pmecc_desc.ecc_size_byte;\r
+}\r
+\r
+/**\r
+ * \brief Return PMECC ecc start address.\r
+ */\r
+uint32_t pmecc_get_ecc_start_address(void)\r
+{\r
+ return pmecc_desc.ecc_start_address;\r
+}\r
+\r
+/**\r
+ * \brief Return PMECC ecc end address.\r
+ */\r
+uint32_t pmecc_get_ecc_end_address(void)\r
+{\r
+ return pmecc_desc.ecc_end_address;\r
+}\r
+\r
+\r
+typedef uint32_t (*pmecc_correction_algo_t)(Smc *, struct _pmecc_descriptor *, uint32_t, uint32_t);\r
+\r
+/**\r
+ * \brief Launch error detection functions and correct corrupted bits.\r
+ * \param pmecc_status Value of the PMECC status register.\r
+ * \param page_buffer Base address of the buffer containing the page to be corrected.\r
+ * \return 0 if all errors have been corrected, 1 if too many errors detected\r
+ */\r
+uint32_t pmecc_correction(uint32_t pmecc_status, uint32_t page_buffer)\r
+{\r
+ uint32_t sector_number = 0;\r
+ uint32_t sector_base_address;\r
+ volatile int32_t error_nbr;\r
+\r
+ /* Set the sector size (512 or 1024 bytes) */\r
+ HSMC->HSMC_ELCFG = pmecc_desc.sector_size >> 4;\r
+\r
+ while (sector_number < (uint32_t)((1 << ((HSMC->HSMC_PMECCFG & HSMC_PMECCFG_PAGESIZE_Msk) >> 8)))) {\r
+ error_nbr = 0;\r
+ if (pmecc_status & 0x1) {\r
+ sector_base_address = page_buffer + (sector_number * ((pmecc_desc.sector_size >> 4) + 1) * 512);\r
+ gen_syn(sector_number);\r
+ substitute();\r
+ get_sigma();\r
+ error_nbr = error_location((((pmecc_desc.sector_size >> 4) + 1) * 512 * 8) +\r
+ (pmecc_desc.tt * (13 + (pmecc_desc.sector_size >> 4)))); /* number of bits of the sector + ecc */\r
+\r
+ if (error_nbr == -1)\r
+ return 1;\r
+ else\r
+ error_correction(sector_base_address, 0, error_nbr); /* Extra byte is 0 */\r
+ }\r
+ sector_number++;\r
+ pmecc_status = pmecc_status >> 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Disable pmecc.\r
+ */\r
+void pmecc_disable(void)\r
+{\r
+ /* Disable ECC module */\r
+ HSMC->HSMC_PMECCTRL |= HSMC_PMECCTRL_DISABLE;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef PMECC_H\r
+#define PMECC_H\r
+\r
+/*----------------------------------------------------------------------- */\r
+/* Definition */\r
+/*----------------------------------------------------------------------- */\r
+\r
+/** Start address of ECC cvalue in spare zone, this must not be 0 since Bad block tag are at 0. */\r
+#define PMECC_ECC_DEFAULT_START_ADDR 0x02\r
+\r
+/*------------------------------------------------------------------------------ */\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------ */\r
+\r
+extern uint8_t pmecc_initialize(uint8_t sector_size,\r
+ uint8_t ecc_errors_per_sector,\r
+ uint32_t page_data_size,\r
+ uint32_t page_spare_size,\r
+ uint16_t ecc_offset_in_spare,\r
+ uint8_t spare_protected);\r
+\r
+extern uint32_t pmecc_get_page_size(void);\r
+\r
+extern uint32_t pmecc_get_ecc_bytes(void);\r
+\r
+extern uint32_t pmecc_get_ecc_start_address(void);\r
+\r
+extern uint32_t pmecc_get_ecc_end_address(void);\r
+\r
+extern uint32_t pmecc_correction(uint32_t pmecc_status, uint32_t page_buffer);\r
+\r
+extern void build_gf(uint32_t mm, int32_t *index_of, int32_t *alpha_to);\r
+\r
+extern void pmecc_disable(void);\r
+\r
+#endif\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+#ifndef PMECC_TABLES_1024_H\r
+#define PMECC_TABLES_1024_H\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define PMECC_GF_1024_SIZE (0x4000)\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \brief Get the addresses of Gallois Field tables for 1024 bytes sectors */\r
+void pmecc_get_gf_1024_tables(const int16_t **alpha_to, const int16_t **index_of);\r
+\r
+#endif /* PMECC_TABLES_1024_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+#ifndef PMECC_TABLES_512_H\r
+#define PMECC_TABLES_512_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define PMECC_GF_512_SIZE (0x2000)\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \brief Get the addresses of Gallois Field tables for 512 bytes sectors */\r
+void pmecc_get_gf_512_tables(const int16_t **alpha_to, const int16_t **index_of);\r
+\r
+#endif /* PMECC_TABLES_512_H */\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup pwm_module Working with PWM\r
+ * \section Purpose\r
+ * The PWM driver provides the interface to configure and use the PWM\r
+ * peripheral.\r
+ *\r
+ * The PWM macrocell controls square output waveforms of 4 channels.\r
+ * Characteristics of output waveforms such as period, duty-cycle can be configured.\n\r
+ *\r
+ * Before enabling the channels, they must have been configured first.\r
+ * The main settings include:\r
+ * <ul>\r
+ * <li>Configuration of the clock generator.</li>\r
+ * <li>Selection of the clock for each channel.</li>\r
+ * <li>Configuration of output waveform characteristics, such as period, duty-cycle etc.</li>\r
+ * </ul>\r
+ *\r
+ * After the channels is enabled, the user must use respective update registers\r
+ * to change the wave characteristics to prevent unexpected output waveform.\r
+ * i.e. PWM_CUPDx register should be used if user want to change duty-cycle\r
+ * when the channel is enabled.\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Configure PWM clock using pwmc_configure_clocks().\r
+ * <li> Enable & disable given PWM channel using pwmc_enable_channel() and pwmc_disable_channel().\r
+ * <li> Enable & disable interrupt of given PWM channel using pwmc_enable_channel_it()\r
+ * and pwmc_disable_channel_it().\r
+ * <li> Set feature of the given PWM channel's output signal using pwmc_set_period()\r
+ * and pwmc_set_duty_cycle().\r
+ * </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the PWM section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref pwmc.c\n\r
+ * \ref pwmc.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of the Pulse Width Modulation Controller (PWM) peripheral.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/pwmc.h"\r
+\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void pwmc_configure_clocks(Pwm * p_pwm, uint32_t mode)\r
+{\r
+ p_pwm->PWM_CLK = mode;\r
+}\r
+\r
+void pwmc_enable_channel(Pwm * p_pwm, uint8_t channel)\r
+{\r
+ p_pwm->PWM_ENA = 0x1ul << channel;\r
+}\r
+\r
+void pwmc_disable_channel(Pwm * p_pwm, uint8_t channel)\r
+{\r
+ p_pwm->PWM_DIS = 0x1ul << channel;\r
+}\r
+\r
+void pwmc_enable_channel_it(Pwm * p_pwm, uint8_t channel)\r
+{\r
+ p_pwm->PWM_IER1 = 0x1ul << channel;\r
+}\r
+\r
+void pwmc_disable_channel_it(Pwm * p_pwm, uint8_t channel)\r
+{\r
+ p_pwm->PWM_IDR1 = 0x1ul << channel;\r
+}\r
+\r
+void pwmc_configure_channel(Pwm * p_pwm, uint8_t channel, uint32_t mode)\r
+{\r
+ p_pwm->PWM_CH_NUM[channel].PWM_CMR = mode;\r
+}\r
+\r
+void pwmc_set_period(Pwm * p_pwm, uint8_t channel, uint16_t period)\r
+{\r
+ /* If channel is disabled, write to CPRD */\r
+ if ((p_pwm->PWM_SR & (1 << channel)) == 0) {\r
+ p_pwm->PWM_CH_NUM[channel].PWM_CPRD = period;\r
+ }\r
+ /* Otherwise use update register */\r
+ else {\r
+ p_pwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period;\r
+ }\r
+}\r
+\r
+void pwmc_set_duty_cycle(Pwm * p_pwm, uint8_t channel, uint16_t duty)\r
+{\r
+ assert(duty <= p_pwm->PWM_CH_NUM[channel].PWM_CPRD);\r
+\r
+ /* If channel is disabled, write to CDTY */\r
+ if ((p_pwm->PWM_SR & (1 << channel)) == 0) {\r
+ p_pwm->PWM_CH_NUM[channel].PWM_CDTY = duty;\r
+ }\r
+ /* Otherwise use update register */\r
+ else {\r
+ p_pwm->PWM_CH_NUM[channel].PWM_CDTYUPD = duty;\r
+ }\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * Interface for configuration the Pulse Width Modulation Controller (PWM) peripheral.\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Configures PWM clocks A & B to run at the given frequencies using\r
+ * pwmc_configure_clocks().\r
+ * -# Configure PWMC channel using pwmc_configure_channel(), pwmc_set_period()\r
+ * and pwmc_set_duty_cycle().\r
+ * -# Enable & disable channel using pwmc_enable_channel() and pwmc_disable_channel().\r
+ * -# Enable & disable the period interrupt for the given PWM channel using\r
+ * pwmc_enable_channel_it() and pwmc_disable_channel_it().\r
+ *\r
+ */\r
+\r
+#ifndef _PWMC_\r
+#define _PWMC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures PWM clocks\r
+ * \param p_pwm Pointer to a Pwm instance\r
+ * \param mode PWM clock source selection and divide factor.\r
+ */\r
+extern void pwmc_configure_clocks(Pwm * p_pwm, uint32_t mode);\r
+\r
+/**\r
+ * \brief Enables the given PWM channel.\r
+ *\r
+ * This does NOT enable the corresponding pin; this must be done in the user\r
+ * code.\r
+ *\r
+ * \param p_pwm Pointer to a Pwm instance\r
+ * \param channel Channel number.\r
+ */\r
+extern void pwmc_enable_channel(Pwm * p_pwm, uint8_t channel);\r
+\r
+/**\r
+ * \brief Disables the given PWM channel.\r
+ *\r
+ * Beware, the channel will be effectively disabled at the end of the current\r
+ * period.\r
+ * Applications may check whether the channel is disabled using the following\r
+ * wait loop:\r
+ * while ((PWM->PWM_SR & (1 << channel)) != 0) {};\r
+ *\r
+ * \param p_pwm Pointer to a Pwm instance\r
+ * \param channel Channel number.\r
+ */\r
+extern void pwmc_disable_channel(Pwm * p_pwm, uint8_t channel);\r
+\r
+/**\r
+ * \brief Enables the selected interrupts sources on a PWMC peripheral.\r
+ * \param p_pwm Pointer to a Pwm instance\r
+ * \param channel Channel number.\r
+ */\r
+extern void pwmc_enable_channel_it(Pwm * p_pwm, uint8_t channel);\r
+\r
+/**\r
+ * \brief Disables the selected interrupts sources on a PWMC peripheral.\r
+ * \param p_pwm Pointer to a Pwm instance\r
+ * \param channel Channel number.\r
+ */\r
+extern void pwmc_disable_channel_it(Pwm * p_pwm, uint8_t channel);\r
+\r
+/**\r
+ * \brief Configures a PWM channel with the given parameters, basic configure\r
+ * function.\r
+ *\r
+ * The PWM controller must have been clocked in the PMC prior to calling this\r
+ * function.\r
+ * Beware: this function disables the channel. It will wait until the channel is\r
+ * effectively disabled.\r
+ *\r
+ * \param p_pwm Pointer to a Pwm instance\r
+ * \param channel Channel number.\r
+ * \param mode Channel mode.\r
+ */\r
+extern void pwmc_configure_channel(Pwm * p_pwm, uint8_t channel, uint32_t mode);\r
+\r
+/**\r
+ * \brief Sets the period value used by a PWM channel.\r
+ *\r
+ * This function writes directly to the CPRD register if the channel is\r
+ * disabled. Otherwise it sets the update register CPRDUPD.\r
+ *\r
+ * \param p_pwm Pointer to a Pwm instance\r
+ * \param channel Channel number.\r
+ * \param period Period value.\r
+ */\r
+extern void pwmc_set_period(Pwm * p_pwm, uint8_t channel, uint16_t period);\r
+\r
+/**\r
+ * \brief Sets the duty cycle used by a PWM channel.\r
+ * This function writes directly to the CDTY register if the channel is\r
+ * disabled. Otherwise it sets the update register CDTYUPD.\r
+ * Note that the duty cycle must always be inferior or equal to the channel\r
+ * period.\r
+ *\r
+ * \param p_pwm Pointer to a Pwm instance\r
+ * \param channel Channel number.\r
+ * \param duty Duty cycle value.\r
+ */\r
+extern void pwmc_set_duty_cycle(Pwm * p_pwm, uint8_t channel, uint16_t duty);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* #ifndef _PWMC_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+#include "chip.h"\r
+#include "timer.h"\r
+#include "trace.h"\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/qspi.h"\r
+#include <stdint.h>\r
+#include <string.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static void qspi_memcpy(uint8_t *dst, const uint8_t *src, int count)\r
+{\r
+ while (count--)\r
+ *dst++ = *src++;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Public functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void qspi_initialize(Qspi *qspi)\r
+{\r
+ pmc_enable_peripheral(get_qspi_id_from_addr(qspi));\r
+\r
+ /* Disable write protection */\r
+ qspi->QSPI_WPMR = QSPI_WPMR_WPKEY_PASSWD;\r
+\r
+ /* Reset */\r
+ qspi->QSPI_CR = QSPI_CR_SWRST;\r
+\r
+ /* Configure */\r
+ qspi->QSPI_MR = QSPI_MR_SMM_MEMORY;\r
+ qspi->QSPI_SCR = 0;\r
+\r
+ /* Enable */\r
+ qspi->QSPI_CR = QSPI_CR_QSPIEN;\r
+}\r
+\r
+uint32_t qspi_set_baudrate(Qspi *qspi, uint32_t baudrate)\r
+{\r
+ uint32_t mck, scr, scbr;\r
+\r
+ if (!baudrate)\r
+ return 0;\r
+\r
+ /* Serial Clock Baudrate */\r
+ mck = pmc_get_peripheral_clock(get_qspi_id_from_addr(qspi));\r
+ scbr = (mck + baudrate - 1) / baudrate;\r
+ if (scbr > 0)\r
+ scbr--;\r
+\r
+ /* Update the Serial Clock Register */\r
+ scr = qspi->QSPI_SCR;\r
+ scr &= ~QSPI_SCR_SCBR_Msk;\r
+ scr |= QSPI_SCR_SCBR(scbr);\r
+ qspi->QSPI_SCR = scr;\r
+\r
+ return mck / (scbr + 1);\r
+}\r
+\r
+bool qspi_perform_command(Qspi *qspi, const struct _qspi_cmd *cmd)\r
+{\r
+ uint32_t iar, icr, ifr;\r
+ uint32_t offset;\r
+\r
+ iar = 0;\r
+ icr = 0;\r
+ ifr = (cmd->ifr_width & QSPI_IFR_WIDTH_Msk) | (cmd->ifr_type & QSPI_IFR_TFRTYP_Msk);\r
+\r
+ /* Compute address parameters */\r
+ switch (cmd->enable.address) {\r
+ case 4:\r
+ ifr |= QSPI_IFR_ADDRL_32_BIT;\r
+ /* fallback to the 24-bit address case */\r
+ case 3:\r
+ iar = (cmd->enable.data) ? 0 : QSPI_IAR_ADDR(cmd->address);\r
+ ifr |= QSPI_IFR_ADDREN;\r
+ offset = cmd->address;\r
+ break;\r
+ case 0:\r
+ offset = 0;\r
+ break;\r
+ default:\r
+ return false;\r
+ }\r
+\r
+ /* Compute instruction parameters */\r
+ if (cmd->enable.instruction) {\r
+ icr |= QSPI_ICR_INST(cmd->instruction);\r
+ ifr |= QSPI_IFR_INSTEN;\r
+ }\r
+\r
+ /* Compute option parameters */\r
+ if (cmd->enable.mode && cmd->num_mode_cycles) {\r
+ uint32_t mode_cycle_bits, mode_bits;\r
+\r
+ icr |= QSPI_ICR_OPT(cmd->mode);\r
+ ifr |= QSPI_IFR_OPTEN;\r
+\r
+ switch (ifr & QSPI_IFR_WIDTH_Msk) {\r
+ case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:\r
+ case QSPI_IFR_WIDTH_DUAL_OUTPUT:\r
+ case QSPI_IFR_WIDTH_QUAD_OUTPUT:\r
+ mode_cycle_bits = 1;\r
+ break;\r
+ case QSPI_IFR_WIDTH_DUAL_IO:\r
+ case QSPI_IFR_WIDTH_DUAL_CMD:\r
+ mode_cycle_bits = 2;\r
+ break;\r
+ case QSPI_IFR_WIDTH_QUAD_IO:\r
+ case QSPI_IFR_WIDTH_QUAD_CMD:\r
+ mode_cycle_bits = 4;\r
+ break;\r
+ default:\r
+ return false;\r
+ }\r
+\r
+ mode_bits = cmd->num_mode_cycles * mode_cycle_bits;\r
+ switch (mode_bits) {\r
+ case 1:\r
+ ifr |= QSPI_IFR_OPTL_OPTION_1BIT;\r
+ break;\r
+\r
+ case 2:\r
+ ifr |= QSPI_IFR_OPTL_OPTION_2BIT;\r
+ break;\r
+\r
+ case 4:\r
+ ifr |= QSPI_IFR_OPTL_OPTION_4BIT;\r
+ break;\r
+\r
+ case 8:\r
+ ifr |= QSPI_IFR_OPTL_OPTION_8BIT;\r
+ break;\r
+\r
+ default:\r
+ return false;\r
+ }\r
+ }\r
+\r
+ /* Set number of dummy cycles */\r
+ if (cmd->enable.dummy)\r
+ ifr |= QSPI_IFR_NBDUM(cmd->num_dummy_cycles);\r
+ else\r
+ ifr |= QSPI_IFR_NBDUM(0);\r
+\r
+ /* Set data enable */\r
+ if (cmd->enable.data) {\r
+ ifr |= QSPI_IFR_DATAEN;\r
+\r
+ /* Special case for Continous Read Mode */\r
+ if (!cmd->tx_buffer && !cmd->rx_buffer)\r
+ ifr |= QSPI_IFR_CRM_ENABLED;\r
+ }\r
+\r
+ /* Set QSPI Instruction Frame registers */\r
+ qspi->QSPI_IAR = iar;\r
+ qspi->QSPI_ICR = icr;\r
+ qspi->QSPI_IFR = ifr;\r
+\r
+ /* Skip to the final steps if there is no data */\r
+ if (!cmd->enable.data)\r
+ goto no_data;\r
+\r
+ /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */\r
+ (void)qspi->QSPI_IFR;\r
+\r
+ /* Send/Receive data */\r
+ if (cmd->tx_buffer) {\r
+ /* Write data */\r
+ uint8_t *ptr = (uint8_t*)get_qspi_mem_from_addr(qspi);\r
+ qspi_memcpy(ptr + offset, cmd->tx_buffer, cmd->buffer_len);\r
+ } else if (cmd->rx_buffer) {\r
+ /* Read data */\r
+ const uint8_t *ptr = (const uint8_t*)get_qspi_mem_from_addr(qspi);\r
+ qspi_memcpy(cmd->rx_buffer, ptr + offset, cmd->buffer_len);\r
+ } else {\r
+ /* Stop here for continuous read */\r
+ return true;\r
+ }\r
+\r
+no_data:\r
+ /* Release the chip-select */\r
+ qspi->QSPI_CR = QSPI_CR_LASTXFER;\r
+\r
+ /* Wait for INSTRuction End */\r
+ struct _timeout timeout;\r
+ timer_start_timeout(&timeout, cmd->timeout);\r
+ while (!(qspi->QSPI_SR & QSPI_SR_INSTRE)) {\r
+ if (timer_timeout_reached(&timeout)) {\r
+ trace_debug("qspi_perform_command timeout reached\r\n");\r
+ return false;\r
+ }\r
+ }\r
+\r
+ return true;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for Quad Serial Peripheral Interface (QSPI) controller.\r
+ *\r
+ */\r
+\r
+#ifndef _QSPI_H_\r
+#define _QSPI_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** QSPI Command structure */\r
+struct _qspi_cmd {\r
+ /** Data Transfer Type (QSPI_IFR_TFRTYP_TRSFR_xxx) */\r
+ uint32_t ifr_type;\r
+\r
+ /** Width of Instruction Code, Address, Option Code and Data\r
+ * (QSPI_IFR_WIDTH_xxx) */\r
+ uint32_t ifr_width;\r
+\r
+ /** Flags to select which information is included in the command */\r
+ struct {\r
+ /** 0: don't send instruction code, 1: send instuction code */\r
+ uint32_t instruction:1;\r
+ /** 0: don't send address, 3: send 3-byte address, 4: send\r
+ * 4-byte address */\r
+ uint32_t address:3;\r
+ /** 0: don't send mode bits, 1: send mode bits */\r
+ uint32_t mode:1;\r
+ /** 0: don't send dummy bits, 1: send dummy bits */\r
+ uint32_t dummy:1;\r
+ /** 0: don't send/recieve data, 1: send/recieve data */\r
+ uint32_t data:1;\r
+ /** reserved, not used */\r
+ uint32_t reserved:25;\r
+ } enable;\r
+\r
+ /** Instruction code */\r
+ uint8_t instruction;\r
+\r
+ /** Mode bits */\r
+ uint8_t mode;\r
+\r
+ /** Number of mode cycles */\r
+ uint8_t num_mode_cycles;\r
+\r
+ /** Number of dummy cycles */\r
+ uint8_t num_dummy_cycles;\r
+\r
+ /** QSPI address */\r
+ uint32_t address;\r
+\r
+ /** Address of the TX buffer */\r
+ const void *tx_buffer;\r
+\r
+ /** Address of the RX buffer */\r
+ void *rx_buffer;\r
+\r
+ /** Size of the RX/TX buffer */\r
+ uint32_t buffer_len;\r
+\r
+ /** Timeout for the command execution, in timer ticks */\r
+ uint32_t timeout;\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \brief Reset and initialize a QSPI instance.\r
+ *\r
+ * \param qspi the QSPI instance\r
+ */\r
+void qspi_initialize(Qspi *qspi);\r
+\r
+/**\r
+ * \brief Configure the baudrate for a QSPI instance.\r
+ *\r
+ * \param qspi the QSPI instance\r
+ * \param baudrate the requested baudrate\r
+ * \return the actual baudrate configured (can be lower than requested)\r
+ */\r
+uint32_t qspi_set_baudrate(Qspi *qspi, uint32_t baudrate);\r
+\r
+/**\r
+ * \brief Perform a QSPI command.\r
+ *\r
+ * Note that if enable.data is set in the command, data will be sent/recieved:\r
+ * - if tx_buffer is not NULL, data will be sent\r
+ * - if rx_buffer is not NULL, data will be recieved\r
+ * - if both tx_buffer and rx_buffer are NULL, QSPI will be configured in\r
+ * "Continuous Read" mode and random read access can be done at the address\r
+ * returned by get_qspi_mem_from_addr\r
+ *\r
+ * \param qspi the QSPI instance\r
+ * \param cmd the QSPI command to perform\r
+ * \return true if the command was succesfully issued, false otherwise\r
+ */\r
+bool qspi_perform_command(Qspi *qspi, const struct _qspi_cmd *cmd);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _QSPI_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/rstc.h"\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Configure the mode of the RSTC peripheral.\r
+ * The configuration is computed by the lib (RSTC_RMR_*).\r
+ * \param mr Desired mode configuration.\r
+ */\r
+void rstc_configure_mode(uint32_t mr)\r
+{\r
+ RSTC->RSTC_MR = (mr & ~RSTC_MR_KEY_Msk) | RSTC_MR_KEY_PASSWD;\r
+}\r
+\r
+/**\r
+ * Enable/Disable the detection of a low level on the pin NRST as User Reset\r
+ * \param enable 1 to enable & 0 to disable.\r
+ */\r
+void rstc_set_user_reset_enable(uint8_t enable)\r
+{\r
+ uint32_t mr = RSTC->RSTC_MR;\r
+ if (enable) {\r
+ mr |= RSTC_MR_URSTEN;\r
+ } else {\r
+ mr &= ~RSTC_MR_URSTEN;\r
+ }\r
+ RSTC->RSTC_MR = mr | RSTC_MR_KEY_PASSWD;\r
+}\r
+\r
+/**\r
+ * Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST).\r
+ * \param enable 1 to enable & 0 to disable.\r
+ */\r
+void rstc_set_user_reset_interrupt_enable(uint8_t enable)\r
+{\r
+ uint32_t mr = RSTC->RSTC_MR;\r
+ if (enable) {\r
+ mr |= RSTC_MR_URSTIEN;\r
+ } else {\r
+\r
+ mr &= ~RSTC_MR_URSTIEN;\r
+ }\r
+ RSTC->RSTC_MR = mr | RSTC_MR_KEY_PASSWD;\r
+}\r
+\r
+/**\r
+ * Resets the processor.\r
+ */\r
+void rstc_processor_reset(void)\r
+{\r
+ RSTC->RSTC_CR = RSTC_CR_PROCRST | RSTC_MR_KEY_PASSWD;\r
+}\r
+\r
+/**\r
+ * Resets the peripherals.\r
+ */\r
+void rstc_peripheral_reset(void)\r
+{\r
+ RSTC->RSTC_CR = RSTC_CR_PERRST | RSTC_MR_KEY_PASSWD;\r
+}\r
+\r
+/**\r
+ * Return NRST pin level ( 1 or 0 ).\r
+ */\r
+uint8_t rstc_get_nrst_level(void)\r
+{\r
+ return (RSTC->RSTC_SR & RSTC_SR_NRSTL) != 0;\r
+}\r
+\r
+/**\r
+ * Returns 1 if at least one high-to-low transition of NRST (User Reset) has\r
+ * been detected since the last read of RSTC_RSR.\r
+ */\r
+uint8_t rstc_is_user_reset_detected(void)\r
+{\r
+ return (RSTC->RSTC_SR & RSTC_SR_URSTS) != 0;\r
+}\r
+\r
+/**\r
+ * Return 1 if a software reset command is being performed by the reset\r
+ * controller. The reset controller is busy.\r
+ */\r
+uint8_t rstc_is_busy(void)\r
+{\r
+ return (RSTC->RSTC_SR & RSTC_SR_SRCMP) != 0;\r
+}\r
+\r
+/**\r
+ * Get the status\r
+ */\r
+uint32_t rstc_get_status(void)\r
+{\r
+ return RSTC->RSTC_SR;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _RSTC_H\r
+#define _RSTC_H\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Includes\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Exported functions\r
+ *---------------------------------------------------------------------------*/\r
+\r
+extern void rstc_configure_mode(uint32_t rmr);\r
+extern void rstc_set_user_reset_enable(uint8_t enable);\r
+extern void rstc_set_user_reset_interrupt_enable(uint8_t enable);\r
+extern void rstc_processor_reset(void);\r
+extern void rstc_peripheral_reset(void);\r
+extern uint8_t rstc_get_nrst_level(void);\r
+extern uint8_t rstc_is_user_reset_detected(void);\r
+extern uint8_t rstc_is_busy(void);\r
+extern uint32_t rstc_get_status(void);\r
+\r
+#endif /* #ifndef _RSTC_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup rtc_module Working with RTC\r
+ * \section Purpose\r
+ * The RTC driver provides the interface to configure and use the RTC\r
+ * peripheral.\r
+ *\r
+ * It manages date, time, and alarms.\n\r
+ * This timer is clocked by the 32kHz system clock, and is not impacted by\r
+ * power management settings (PMC). To be accurate, it is better to use an\r
+ * external 32kHz crystal instead of the internal 32kHz RC.\n\r
+ *\r
+ * It uses BCD format, and time can be set in AM/PM or 24h mode through a\r
+ * configuration bit in the mode register.\n\r
+ *\r
+ * To update date or time, the user has to follow these few steps :\r
+ * <ul>\r
+ * <li>Set UPDTIM and/or UPDCAL bit(s) in RTC_CR,</li>\r
+ * <li>Polling or IRQ on the ACKUPD bit of RTC_CR,</li>\r
+ * <li>Clear ACKUPD bit in RTC_SCCR,</li>\r
+ * <li>Update Time and/or Calendar values in RTC_TIMR/RTC_CALR (BCD format),</li>\r
+ * <li>Clear UPDTIM and/or UPDCAL bit in RTC_CR.</li>\r
+ * </ul>\r
+ * An alarm can be set to happen on month, date, hours, minutes or seconds,\r
+ * by setting the proper "Enable" bit of each of these fields in the Time and\r
+ * Calendar registers.\r
+ * This allows a large number of configurations to be available for the user.\r
+ * Alarm occurence can be detected even by polling or interrupt.\r
+ *\r
+ * A check of the validity of the date and time format and values written by the user is automatically done.\r
+ * Errors are reported through the Valid Entry Register.\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Enable & disable RTC interrupt using rtc_enable_it() and rtc_disable_it().\r
+ * <li> Set RTC data, time, alarm using rtc_set_date(), rtc_set_time(),\r
+ * rtc_set_time_alarm() and rtc_set_date_alarm().\r
+ * <li> Get RTC data, time using rtc_get_date() and rtc_get_time().\r
+ * </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the RTC section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref rtc.c\n\r
+ * \ref rtc.h.\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Real Time Clock (RTC) controller.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/rtc.h"\r
+#include "trace.h"\r
+#include <stdint.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local Defines\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* The BCD code shift value */\r
+#define BCD_SHIFT 4\r
+\r
+/* The BCD code mask value */\r
+#define BCD_MASK 0xfu\r
+\r
+/* The BCD mul/div factor value */\r
+#define BCD_FACTOR 10\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+struct rtc_ppm_lookup {\r
+ int8_t tempr;\r
+ int16_t ppm;\r
+ uint8_t negppm;\r
+ uint8_t highppm;\r
+ uint16_t correction;\r
+};\r
+\r
+//------------------------------------------------------------------------------\r
+// Local constants\r
+//------------------------------------------------------------------------------\r
+\r
+static const struct rtc_ppm_lookup ppm_lookup[] = {\r
+ {-40, -168, 0, 1, 22},\r
+ {-39, -163, 0, 1, 23},\r
+ {-38, -158, 0, 1, 24},\r
+ {-37, -153, 0, 1, 25},\r
+ {-36, -148, 0, 1, 25},\r
+ {-35, -143, 0, 1, 26},\r
+ {-34, -138, 0, 1, 27},\r
+ {-33, -134, 0, 1, 28},\r
+ {-32, -129, 0, 1, 29},\r
+ {-31, -124, 0, 1, 31},\r
+ {-30, -120, 0, 1, 32},\r
+ {-29, -116, 0, 1, 33},\r
+ {-28, -111, 0, 1, 34},\r
+ {-27, -107, 0, 1, 36},\r
+ {-26, -103, 0, 1, 37},\r
+ {-25, -99, 0, 1, 38},\r
+ {-24, -95, 0, 1, 40},\r
+ {-23, -91, 0, 1, 42},\r
+ {-22, -87, 0, 1, 44},\r
+ {-21, -84, 0, 1, 45},\r
+ {-20, -80, 0, 1, 48},\r
+ {-19, -76, 0, 1, 50},\r
+ {-18, -73, 0, 1, 53},\r
+ {-17, -70, 0, 1, 55},\r
+ {-16, -66, 0, 1, 58},\r
+ {-15, -63, 0, 1, 61},\r
+ {-14, -60, 0, 1, 64},\r
+ {-13, -57, 0, 1, 68},\r
+ {-12, -54, 0, 1, 71},\r
+ {-11, -51, 0, 1, 76},\r
+ {-10, -48, 0, 1, 80},\r
+ {-9, -45, 0, 1, 86},\r
+ {-8, -43, 0, 1, 90},\r
+ {-7, -40, 0, 1, 97},\r
+ {-6, -37, 0, 1, 105},\r
+ {-5, -35, 0, 1, 111},\r
+ {-4, -33, 0, 1, 117},\r
+ {-3, -30, 0, 0, 6},\r
+ {-2, -28, 0, 0, 6},\r
+ {-1, -26, 0, 0, 7},\r
+ {0, -24, 0, 0, 7},\r
+ {1, -22, 0, 0, 8},\r
+ {2, -20, 0, 0, 9},\r
+ {3, -18, 0, 0, 10},\r
+ {4, -17, 0, 0, 10},\r
+ {5, -15, 0, 0, 12},\r
+ {6, -13, 0, 0, 14},\r
+ {7, -12, 0, 0, 15},\r
+ {8, -11, 0, 0, 17},\r
+ {9, -9, 0, 0, 21},\r
+ {10, -8, 0, 0, 23},\r
+ {11, -7, 0, 0, 27},\r
+ {12, -6, 0, 0, 32},\r
+ {13, -5, 0, 0, 38},\r
+ {14, -4, 0, 0, 48},\r
+ {15, -3, 0, 0, 64},\r
+ {16, -2, 0, 0, 97},\r
+ {17, -2, 0, 0, 97},\r
+ {18, -1, 0, 0, 127},\r
+ {19, 0, 1, 0, 0},\r
+ {20, 0, 1, 0, 0},\r
+ {21, 0, 1, 0, 0},\r
+ {22, 1, 1, 0, 127},\r
+ {23, 1, 1, 0, 127},\r
+ {24, 1, 1, 0, 127},\r
+ {25, 1, 1, 0, 127},\r
+ {26, 1, 1, 0, 127},\r
+ {27, 1, 1, 0, 127},\r
+ {28, 1, 1, 0, 127},\r
+ {29, 0, 1, 0, 0},\r
+ {30, 0, 1, 0, 0},\r
+ {31, 0, 1, 0, 0},\r
+ {32, -1, 0, 0, 127},\r
+ {33, -2, 0, 0, 97},\r
+ {34, -2, 0, 0, 97},\r
+ {35, -3, 0, 0, 64},\r
+ {36, -4, 0, 0, 48},\r
+ {37, -5, 0, 0, 38},\r
+ {38, -6, 0, 0, 32},\r
+ {39, -7, 0, 0, 27},\r
+ {40, -8, 0, 0, 23},\r
+ {41, -9, 0, 0, 21},\r
+ {42, -11, 0, 0, 17},\r
+ {43, -12, 0, 0, 15},\r
+ {44, -13, 0, 0, 14},\r
+ {45, -15, 0, 0, 12},\r
+ {46, -17, 0, 0, 10},\r
+ {47, -18, 0, 0, 10},\r
+ {48, -20, 0, 0, 9},\r
+ {49, -22, 0, 0, 8},\r
+ {50, -24, 0, 0, 7},\r
+ {51, -26, 0, 0, 7},\r
+ {52, -28, 0, 0, 6},\r
+ {53, -30, 0, 0, 6},\r
+ {54, -33, 0, 1, 117},\r
+ {55, -35, 0, 1, 111},\r
+ {56, -37, 0, 1, 105},\r
+ {57, -40, 0, 1, 97},\r
+ {58, -43, 0, 1, 90},\r
+ {59, -45, 0, 1, 86},\r
+ {60, -48, 0, 1, 80},\r
+ {61, -51, 0, 1, 76},\r
+ {62, -54, 0, 1, 71},\r
+ {63, -57, 0, 1, 68},\r
+ {64, -60, 0, 1, 64},\r
+ {65, -63, 0, 1, 61},\r
+ {66, -66, 0, 1, 58},\r
+ {67, -70, 0, 1, 55},\r
+ {68, -73, 0, 1, 53},\r
+ {69, -76, 0, 1, 50},\r
+ {70, -80, 0, 1, 48},\r
+ {71, -84, 0, 1, 45},\r
+ {72, -87, 0, 1, 44},\r
+ {73, -91, 0, 1, 42},\r
+ {74, -95, 0, 1, 40},\r
+ {75, -99, 0, 1, 38},\r
+ {76, -103, 0, 1, 37},\r
+ {77, -107, 0, 1, 36},\r
+ {78, -111, 0, 1, 34},\r
+ {79, -116, 0, 1, 33},\r
+ {80, -120, 0, 1, 32},\r
+ {81, -124, 0, 1, 31},\r
+ {82, -129, 0, 1, 29},\r
+ {83, -134, 0, 1, 28},\r
+ {84, -138, 0, 1, 27},\r
+ {85, -143, 0, 1, 26}\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Sets the RTC in either 12 or 24 hour mode.\r
+ *\r
+ * \param dwMode Hour mode.\r
+ */\r
+void rtc_set_hour_mode(uint32_t mode)\r
+{\r
+ assert((mode & 0xFFFFFFFE) == 0);\r
+ RTC->RTC_MR = mode;\r
+}\r
+\r
+extern uint32_t rtc_get_hour_mode(void)\r
+{\r
+ uint32_t mode;\r
+ mode = RTC->RTC_MR;\r
+ mode &= 0xFFFFFFFE;\r
+ return mode;\r
+}\r
+\r
+void rtc_enable_it(uint32_t sources)\r
+{\r
+ assert((sources & (uint32_t) (~0x1F)) == 0);\r
+ RTC->RTC_IER = sources;\r
+}\r
+\r
+void rtc_disable_it(uint32_t sources)\r
+{\r
+ assert((sources & (uint32_t) (~0x1F)) == 0);\r
+ RTC->RTC_IDR = sources;\r
+}\r
+\r
+uint32_t rtc_set_time(struct _time *time)\r
+{\r
+ uint32_t ltime = 0;\r
+ uint8_t hour_bcd , min_bcd, sec_bcd;\r
+\r
+ /* if 12-hour mode, set AMPM bit */\r
+ if ((RTC->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD) {\r
+ if (time->hour > 12) {\r
+ time->hour -= 12;\r
+ ltime |= RTC_TIMR_AMPM;\r
+ }\r
+ }\r
+ hour_bcd = (time->hour % 10) | ((time->hour / 10) << 4);\r
+ min_bcd = (time->min % 10) | ((time->min / 10) << 4);\r
+ sec_bcd = (time->sec % 10) | ((time->sec / 10) << 4);\r
+ /* value overflow */\r
+ if ((hour_bcd & (uint8_t) (~RTC_HOUR_BIT_LEN_MASK)) |\r
+ (min_bcd & (uint8_t) (~RTC_MIN_BIT_LEN_MASK)) |\r
+ (sec_bcd & (uint8_t) (~RTC_SEC_BIT_LEN_MASK))) {\r
+ return 1;\r
+ }\r
+ ltime = sec_bcd | (min_bcd << 8) | (hour_bcd << 16);\r
+ RTC->RTC_CR |= RTC_CR_UPDTIM;\r
+ while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;\r
+ RTC->RTC_SCCR = RTC_SCCR_ACKCLR;\r
+ RTC->RTC_TIMR = ltime;\r
+ RTC->RTC_CR &= (uint32_t) (~RTC_CR_UPDTIM);\r
+ RTC->RTC_SCCR |= RTC_SCCR_SECCLR;\r
+ return (uint32_t) (RTC->RTC_VER & RTC_VER_NVTIM);\r
+}\r
+\r
+void rtc_get_time(struct _time *time)\r
+{\r
+ uint32_t ltime;\r
+\r
+ /* Get current RTC time */\r
+ ltime = RTC->RTC_TIMR;\r
+ while (ltime != RTC->RTC_TIMR) {\r
+ ltime = RTC->RTC_TIMR;\r
+ }\r
+ /* Hour */\r
+ time->hour = ((ltime & 0x00300000) >> 20) * 10 + ((ltime & 0x000F0000) >> 16);\r
+ if ((ltime & RTC_TIMR_AMPM) == RTC_TIMR_AMPM) {\r
+ time->hour += 12;\r
+ }\r
+ /* Minute */\r
+ time->min = ((ltime & 0x00007000) >> 12) * 10 + ((ltime & 0x00000F00) >> 8);\r
+ /* Second */\r
+ time->sec = ((ltime & 0x00000070) >> 4) * 10 + (ltime & 0x0000000F);\r
+}\r
+\r
+uint32_t rtc_set_time_alarm(struct _time *time)\r
+{\r
+ uint32_t alarm = 0;\r
+\r
+ /* Hour */\r
+ if (time->hour) {\r
+ alarm |= RTC_TIMALR_HOUREN | ((time->hour / 10) << 20) | ((time->hour % 10) << 16);\r
+ }\r
+ /* Minute */\r
+ if (time->min) {\r
+ alarm |= RTC_TIMALR_MINEN | ((time->min / 10) << 12) | ((time->min % 10) << 8);\r
+ }\r
+ /* Second */\r
+ if (time->sec) {\r
+ alarm |= RTC_TIMALR_SECEN | ((time->sec / 10) << 4) | (time->sec % 10);\r
+ }\r
+ RTC->RTC_TIMALR = alarm;\r
+ return (uint32_t) (RTC->RTC_VER & RTC_VER_NVTIMALR);\r
+}\r
+\r
+void rtc_get_date(struct _date *date)\r
+{\r
+ uint32_t ldate;\r
+\r
+ /* Get current date (multiple reads are necessary to insure a stable value) */\r
+ do {\r
+ ldate = RTC->RTC_CALR;\r
+ } while (ldate != RTC->RTC_CALR);\r
+\r
+ /* Retrieve values */\r
+ date->year = (((ldate >> 4) & 0x7) * 1000) + ((ldate & 0xF) * 100)\r
+ + (((ldate >> 12) & 0xF) * 10) + ((ldate >> 8) & 0xF);\r
+ date->month = (((ldate >> 20) & 1) * 10) + ((ldate >> 16) & 0xF);\r
+ date->day = (((ldate >> 28) & 0x3) * 10) + ((ldate >> 24) & 0xF);\r
+ date->week = ((ldate >> 21) & 0x7);\r
+}\r
+\r
+uint32_t rtc_set_date(struct _date *date)\r
+{\r
+ uint32_t ldate;\r
+ uint8_t cent_bcd, year_bcd, month_bcd, day_bcd, week_bcd;\r
+\r
+ cent_bcd = ((date->year / 100) % 10) | ((date->year / 1000) << 4);\r
+ year_bcd = (date->year % 10) | (((date->year / 10) % 10) << 4);\r
+ month_bcd = ((date->month % 10) | (date->month / 10) << 4);\r
+ day_bcd = ((date->day % 10) | (date->day / 10) << 4);\r
+ week_bcd = ((date->week % 10) | (date->week / 10) << 4);\r
+ /* value over flow */\r
+ if ((cent_bcd & (uint8_t) (~RTC_CENT_BIT_LEN_MASK)) |\r
+ (year_bcd & (uint8_t) (~RTC_YEAR_BIT_LEN_MASK)) |\r
+ (month_bcd & (uint8_t) (~RTC_MONTH_BIT_LEN_MASK)) |\r
+ (week_bcd & (uint8_t) (~RTC_WEEK_BIT_LEN_MASK)) |\r
+ (day_bcd & (uint8_t) (~RTC_DATE_BIT_LEN_MASK))\r
+ ) {\r
+ return 1;\r
+ }\r
+ /* Convert values to date register value */\r
+ ldate = cent_bcd | (year_bcd << 8) | (month_bcd << 16) | (week_bcd << 21) | (day_bcd << 24);\r
+ /* Update calendar register */\r
+ RTC->RTC_CR |= RTC_CR_UPDCAL;\r
+ while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;\r
+ RTC->RTC_SCCR = RTC_SCCR_ACKCLR;\r
+ RTC->RTC_CALR = ldate;\r
+ RTC->RTC_CR &= (uint32_t) (~RTC_CR_UPDCAL);\r
+ RTC->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */\r
+ return (uint32_t) (RTC->RTC_VER & RTC_VER_NVCAL);\r
+}\r
+\r
+uint32_t rtc_set_date_alarm(struct _date *date)\r
+{\r
+ uint32_t alarm;\r
+\r
+ alarm = ((date->month) || (date->day)) ? (0) : (0x01010000);\r
+ /* Compute alarm field value */\r
+ if (date->month) {\r
+ alarm |= RTC_CALALR_MTHEN | ((date->month / 10) << 20) | ((date->month % 10) << 16);\r
+ }\r
+ if (date->day) {\r
+ alarm |= RTC_CALALR_DATEEN | ((date->day / 10) << 28) | ((date->day % 10) << 24);\r
+ }\r
+ /* Set alarm */\r
+ RTC->RTC_CALALR = alarm;\r
+ return (uint32_t) (RTC->RTC_VER & RTC_VER_NVCALALR);\r
+}\r
+\r
+void rtc_clear_sccr(uint32_t mask)\r
+{\r
+ /* Clear all flag bits in status clear command register */\r
+ mask &= RTC_SCCR_ACKCLR | RTC_SCCR_ALRCLR | RTC_SCCR_SECCLR |\r
+ RTC_SCCR_TIMCLR | RTC_SCCR_CALCLR;\r
+ RTC->RTC_SCCR = mask;\r
+}\r
+\r
+uint32_t rtc_get_sr(uint32_t mask)\r
+{\r
+ return (RTC->RTC_SR) & mask;\r
+}\r
+\r
+void rtc_get_tamper_time(struct _time *time, uint8_t reg_num)\r
+{\r
+ uint32_t ltime, temp;\r
+\r
+ /* Get current RTC time */\r
+ ltime = RTC->RTC_TS[reg_num].RTC_TSTR;\r
+ while (ltime != RTC->RTC_TS[reg_num].RTC_TSTR) {\r
+ ltime = RTC->RTC_TS[reg_num].RTC_TSTR;\r
+ }\r
+ /* Hour */\r
+ if (time->hour) {\r
+ temp = (ltime & RTC_TSTR_HOUR_Msk) >> RTC_TSTR_HOUR_Pos;\r
+ time->hour = (temp >> BCD_SHIFT) * BCD_FACTOR + (temp & BCD_MASK);\r
+ if ((ltime & RTC_TSTR_AMPM) == RTC_TSTR_AMPM) {\r
+ time->hour += 12;\r
+ }\r
+ }\r
+ /* Minute */\r
+ if (time->min) {\r
+ temp = (ltime & RTC_TSTR_MIN_Msk) >> RTC_TSTR_MIN_Pos;\r
+ time->min = (temp >> BCD_SHIFT) * BCD_FACTOR + (temp & BCD_MASK);\r
+ }\r
+ /* Second */\r
+ if (time->sec) {\r
+ temp = (ltime & RTC_TSTR_SEC_Msk) >> RTC_TSTR_SEC_Pos;\r
+ time->sec = (temp >> BCD_SHIFT) * BCD_FACTOR + (temp & BCD_MASK);\r
+ }\r
+}\r
+\r
+void rtc_get_tamper_date(struct _date *date, uint8_t reg_num)\r
+{\r
+ uint32_t ldate, cent, temp;\r
+\r
+ /* Get the current date (multiple reads are to insure a stable value). */\r
+ ldate = RTC->RTC_TS[reg_num].RTC_TSDR;\r
+ while (ldate != RTC->RTC_TS[reg_num].RTC_TSDR) {\r
+ ldate = RTC->RTC_TS[reg_num].RTC_TSDR;\r
+ }\r
+ /* Retrieve year */\r
+ temp = (ldate & RTC_TSDR_CENT_Msk) >> RTC_TSDR_CENT_Pos;\r
+ cent = (temp >> BCD_SHIFT) * BCD_FACTOR + (temp & BCD_MASK);\r
+ temp = (ldate & RTC_TSDR_YEAR_Msk) >> RTC_TSDR_YEAR_Pos;\r
+ date->year = (cent * BCD_FACTOR * BCD_FACTOR) + (temp >> BCD_SHIFT) * BCD_FACTOR + (temp & BCD_MASK);\r
+\r
+ /* Retrieve month */\r
+ temp = (ldate & RTC_TSDR_MONTH_Msk) >> RTC_TSDR_MONTH_Pos;\r
+ date->month = (temp >> BCD_SHIFT) * BCD_FACTOR + (temp & BCD_MASK);\r
+\r
+ /* Retrieve day */\r
+ temp = (ldate & RTC_TSDR_DATE_Msk) >> RTC_TSDR_DATE_Pos;\r
+ date->day = (temp >> BCD_SHIFT) * BCD_FACTOR + (temp & BCD_MASK);\r
+\r
+ /* Retrieve week */\r
+ date->week= ((ldate & RTC_TSDR_DAY_Msk) >> RTC_TSDR_DAY_Pos);\r
+}\r
+\r
+uint32_t rtc_get_tamper_source(uint8_t reg_num)\r
+{\r
+ return RTC->RTC_TS[reg_num].RTC_TSSR;\r
+}\r
+\r
+uint32_t rtc_get_tamper_event_counter(void)\r
+{\r
+ return (RTC->RTC_TS[0].RTC_TSTR & RTC_TSTR_TEVCNT_Msk) >> RTC_TSTR_TEVCNT_Pos;\r
+}\r
+\r
+uint8_t rtc_is_tamper_occur_in_backup_mode(uint8_t reg_num)\r
+{\r
+ if (RTC->RTC_TS[reg_num].RTC_TSTR & RTC_TSTR_BACKUP) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+void rtc_convert_time_to_hms(struct _time *time, uint32_t count)\r
+{\r
+ count = count % 86400;\r
+ time->hour = count / 3600;\r
+ count -= time->hour * 3600;\r
+ time->min = count / 60;\r
+ time->sec = count % 60;\r
+}\r
+\r
+void rtc_calibration(int32_t current_tempr)\r
+{\r
+ uint32_t i, mr;\r
+ for (i = 0; i < ARRAY_SIZE(ppm_lookup); i++) {\r
+ if (ppm_lookup[i].tempr == current_tempr) {\r
+ mr = RTC_MR_CORRECTION(ppm_lookup[i].correction);\r
+ mr |= (ppm_lookup[i].highppm << 15);\r
+ mr |= (ppm_lookup[i].negppm << 4);\r
+ RTC->RTC_MR = mr; // update the calibration value\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+uint32_t rtc_set_time_event (uint32_t mask)\r
+{\r
+ uint32_t reg;\r
+ reg = RTC->RTC_CR;\r
+ reg &= ~RTC_CR_TIMEVSEL_Msk;\r
+ reg |= mask;\r
+ RTC->RTC_CR = reg;\r
+ return RTC->RTC_CR;\r
+}\r
+\r
+uint32_t rtc_set_calendar_event (uint32_t mask)\r
+{\r
+ uint32_t reg;\r
+ reg = RTC->RTC_CR;\r
+ reg &= ~RTC_CR_CALEVSEL_Msk;\r
+ reg |= mask;\r
+ RTC->RTC_CR = reg;\r
+ return RTC->RTC_CR;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for Real Time Clock (RTC) controller.\r
+ *\r
+ */\r
+\r
+#ifndef _RTC_H_\r
+#define _RTC_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define RTC_HOUR_BIT_LEN_MASK 0x3F\r
+#define RTC_MIN_BIT_LEN_MASK 0x7F\r
+#define RTC_SEC_BIT_LEN_MASK 0x7F\r
+#define RTC_CENT_BIT_LEN_MASK 0x7F\r
+#define RTC_YEAR_BIT_LEN_MASK 0xFF\r
+#define RTC_MONTH_BIT_LEN_MASK 0x1F\r
+#define RTC_DATE_BIT_LEN_MASK 0x3F\r
+#define RTC_WEEK_BIT_LEN_MASK 0x07\r
+\r
+struct _time\r
+{\r
+ uint8_t hour;\r
+ uint8_t min;\r
+ uint8_t sec;\r
+} ;\r
+\r
+struct _date\r
+{\r
+ uint16_t year;\r
+ uint8_t month;\r
+ uint8_t day;\r
+ uint8_t week;\r
+} ;\r
+\r
+#ifdef CONFIG_SOC_SAMA5D2\r
+ /* -------- RTC_TSTR : (RTC Offset: N/A) TimeStamp Time Register 0 -------- */\r
+ #define RTC_TSTR_SEC_Pos 0\r
+ #define RTC_TSTR_SEC_Msk (0x7fu << RTC_TSTR_SEC_Pos) /**< \brief (RTC_TSTR) SEConds of the tamper */\r
+ #define RTC_TSTR_MIN_Pos 8\r
+ #define RTC_TSTR_MIN_Msk (0x7fu << RTC_TSTR_MIN_Pos) /**< \brief (RTC_TSTR) MINutes of the tamper */\r
+ #define RTC_TSTR_HOUR_Pos 16\r
+ #define RTC_TSTR_HOUR_Msk (0x3fu << RTC_TSTR_HOUR_Pos) /**< \brief (RTC_TSTR) HOURs of the tamper */\r
+ #define RTC_TSTR_AMPM (0x1u << 22) /**< \brief (RTC_TSTR) AMPM indicator of the tamper */\r
+ #define RTC_TSTR_TEVCNT_Pos 24\r
+ #define RTC_TSTR_TEVCNT_Msk (0xfu << RTC_TSTR_TEVCNT_Pos) /**< \brief (RTC_TSTR) Tamper events counter */\r
+ #define RTC_TSTR_BACKUP (0x1u << 31) /**< \brief (RTC_TSTR) system mode of the tamper */\r
+ /* -------- RTC_TSDR : (RTC Offset: N/A) TimeStamp Date Register 0 -------- */\r
+ #define RTC_TSDR_CENT_Pos 0\r
+ #define RTC_TSDR_CENT_Msk (0x7fu << RTC_TSDR_CENT_Pos) /**< \brief (RTC_TSDR) Century of the tamper */\r
+ #define RTC_TSDR_YEAR_Pos 8\r
+ #define RTC_TSDR_YEAR_Msk (0xffu << RTC_TSDR_YEAR_Pos) /**< \brief (RTC_TSDR) Year of the tamper */\r
+ #define RTC_TSDR_MONTH_Pos 16\r
+ #define RTC_TSDR_MONTH_Msk (0x1fu << RTC_TSDR_MONTH_Pos) /**< \brief (RTC_TSDR) Month of the tamper */\r
+ #define RTC_TSDR_DAY_Pos 21\r
+ #define RTC_TSDR_DAY_Msk (0x7u << RTC_TSDR_DAY_Pos) /**< \brief (RTC_TSDR) Day of the tamper */\r
+ #define RTC_TSDR_DATE_Pos 24\r
+ #define RTC_TSDR_DATE_Msk (0x3fu << RTC_TSDR_DATE_Pos) /**< \brief (RTC_TSDR) Date of the tamper */\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \brief Sets the RTC in either 12 or 24 hour mode.\r
+ *\r
+ * \param mode Hour mode.\r
+ */\r
+extern void rtc_set_hour_mode(uint32_t mode);\r
+\r
+/**\r
+ * \brief Gets the RTC mode.\r
+ *\r
+ * \return Hour mode.\r
+ */\r
+extern uint32_t rtc_get_hour_mode(void);\r
+\r
+/**\r
+ * \brief Enables the selected interrupt sources of the RTC.\r
+ *\r
+ * \param sources Interrupt sources to enable.\r
+ */\r
+extern void rtc_enable_it(uint32_t sources);\r
+\r
+/**\r
+* \brief Disables the selected interrupt sources of the RTC.\r
+*\r
+* \param sources Interrupt sources to disable.\r
+*/\r
+extern void rtc_disable_it(uint32_t sources);\r
+\r
+/**\r
+ * \brief Sets the current time in the RTC.\r
+ *\r
+ * \note In successive update operations, the user must wait at least one second\r
+ * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these\r
+ * bits again. Please look at the RTC section of the datasheet for detail.\r
+ *\r
+ * \param time Pointer to structure time\r
+ *\r
+ * \return 0 sucess, 1 fail to set\r
+ */\r
+extern uint32_t rtc_set_time(struct _time *time);\r
+\r
+/**\r
+ * \brief Retrieves the current time as stored in the RTC in several variables.\r
+ *\r
+ * \param time Pointer to structure time\r
+ */\r
+extern void rtc_get_time(struct _time *time);\r
+\r
+/**\r
+ * \brief Sets a time alarm on the RTC.\r
+ * The match is performed only on the provided variables;\r
+ * Setting all pointers to 0 disables the time alarm.\r
+ *\r
+ * \note In AM/PM mode, the hour value must have bit #7 set for PM, cleared for\r
+ * AM (as expected in the time registers).\r
+ *\r
+ * \param time Pointer to structure time.\r
+ *\r
+ * \return 0 success, 1 fail to set\r
+ */\r
+extern uint32_t rtc_set_time_alarm(struct _time *time);\r
+\r
+/**\r
+ * \brief Retrieves the current year, month and day from the RTC.\r
+ * Month, day and week values are numbered starting at 1.\r
+ *\r
+ * \param date Pointer to structure Date.\r
+ */\r
+extern void rtc_get_date(struct _date *date);\r
+\r
+/**\r
+ * \brief Sets the current year, month and day in the RTC.\r
+ * Month, day and week values must be numbered starting from 1.\r
+ *\r
+ * \note In successive update operations, the user must wait at least one second\r
+ * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these\r
+ * bits again. Please look at the RTC section of the datasheet for detail.\r
+ *\r
+ * \param date Pointer to structure Date\r
+ *\r
+ * \return 0 success, 1 fail to set\r
+ */\r
+extern uint32_t rtc_set_date(struct _date *date);\r
+\r
+/**\r
+ * \brief Sets a date alarm in the RTC.\r
+ * The alarm will match only the provided values;\r
+ * Passing a null-pointer disables the corresponding field match.\r
+ *\r
+ * \param pucMonth If not null, the RTC alarm will month-match this value.\r
+ * \param pucDay If not null, the RTC alarm will day-match this value.\r
+ *\r
+ * \return 0 success, 1 fail to set\r
+ */\r
+extern uint32_t rtc_set_date_alarm(struct _date *date);\r
+\r
+/**\r
+ * \brief Clear flag bits of status clear command register in the RTC.\r
+ *\r
+ * \param mask Bits mask of cleared events\r
+ */\r
+extern void rtc_clear_sccr(uint32_t mask);\r
+\r
+/**\r
+ * \brief Get flag bits of status register in the RTC.\r
+ *\r
+ * \param mask Bits mask of Status Register\r
+ *\r
+ * \return Status register & mask\r
+ */\r
+extern uint32_t rtc_get_sr(uint32_t mask);\r
+\r
+/**\r
+ * \brief Get the RTC tamper time value.\r
+ *\r
+ * \note This function should be called before rtc_get_tamper_source()\r
+ * function call, Otherwise the tamper time will be cleared.\r
+ *\r
+ * \param time Pointer to structure Time.\r
+ * \param reg_num Tamper register set number.\r
+ */\r
+extern void rtc_get_tamper_time(struct _time *time, uint8_t reg_num);\r
+\r
+/**\r
+ * \brief Get the RTC tamper date.\r
+ *\r
+ * \note This function should be called before rtc_get_tamper_source()\r
+ * function call, Otherwise the tamper date will be cleared.\r
+ *\r
+ * \param date Pointer to structure Date\r
+ * \param reg_num Tamper register set number.\r
+ */\r
+extern void rtc_get_tamper_date(struct _date *date, uint8_t reg_num);\r
+\r
+/**\r
+ * \brief Get the RTC tamper source.\r
+ *\r
+ * \param reg_num Current tamper register set number.\r
+ *\r
+ * \return Tamper source.\r
+ */\r
+extern uint32_t rtc_get_tamper_source(uint8_t reg_num);\r
+\r
+/**\r
+ * \brief Get the RTC tamper event counter.\r
+ *\r
+ * \note This function should be called before rtc_get_tamper_source()\r
+ * function call, Otherwise the tamper event counter will be cleared.\r
+ *\r
+ * \return Tamper event counter\r
+ */\r
+extern uint32_t rtc_get_tamper_event_counter(void);\r
+\r
+/**\r
+ * \brief Check the system is in backup mode when RTC tamper event happen.\r
+ *\r
+ * \note This function should be called before rtc_get_tamper_source()\r
+ * function call, Otherwise the flag indicates tamper occur in backup\r
+ * mode will be cleared.\r
+ *\r
+ * \param reg_num Current tamper register set number.\r
+ *\r
+ * \return 1 - The system is in backup mode when the tamper event occurs.\r
+ * 0 - The system is different from backup mode.\r
+ */\r
+extern uint8_t rtc_is_tamper_occur_in_backup_mode(uint8_t reg_num);\r
+\r
+/**\r
+ * \brief Convert number of second (count) to HMS format.\r
+ *\r
+ */\r
+extern void rtc_convert_time_to_hms (struct _time *time, uint32_t count);\r
+\r
+/**\r
+ * \brief RTC calibration for Temperature or PPM drift\r
+ */\r
+extern void rtc_calibration(int32_t current_tempr);\r
+\r
+/**\r
+ * \brief Set calendar event selection.\r
+ *\r
+ * \param mask Bits CALEVSEL of Control Register\r
+ * \return Status register & mask\r
+ */\r
+extern uint32_t rtc_set_calendar_event (uint32_t mask);\r
+\r
+/**\r
+ * \brief Set time event selection.\r
+ *\r
+ * \param mask Bits TIMEVSEL of Control Register\r
+ * \return Status register & mask\r
+ */\r
+extern uint32_t rtc_set_time_event (uint32_t maskask);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* _RTC_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup sdmmc_module Working with Multi Media Cards and\r
+ * Secure Digital Memory Cards\r
+ * \ingroup peripherals_module\r
+ * The SDMMC driver provides the interface to configure and use\r
+ * the SDMMC peripheral.\r
+ * \n\r
+ *\r
+ * For more accurate information, please look at the SDMMC\r
+ * section of the Datasheet.\r
+ *\r
+ * Related files:\n\r
+ * \ref sdmmc.c\n\r
+ * \ref sdmmc.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+/**\r
+ * \file\r
+ *\r
+ * Driver for MMC and SD Cards using the SDMMC IP.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "trace.h"\r
+#include "intmath.h"\r
+#include "timer.h"\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/tc.h"\r
+#include "peripherals/l2cc.h"\r
+#include "peripherals/sdmmc.h"\r
+#include "libsdmmc/sdmmc_hal.h"\r
+#include "libsdmmc/sdmmc_api.h" /* Included for debug functions only */\r
+\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Device status */\r
+#define STAT_ADDRESS_OUT_OF_RANGE (1UL << 31)\r
+#define STAT_ADDRESS_MISALIGN (1UL << 30)\r
+#define STAT_BLOCK_LEN_ERROR (1UL << 29)\r
+#define STAT_ERASE_SEQ_ERROR (1UL << 28)\r
+#define STAT_ERASE_PARAM (1UL << 27)\r
+#define STAT_WP_VIOLATION (1UL << 26)\r
+#define STAT_DEVICE_IS_LOCKED (1UL << 25)\r
+#define STAT_LOCK_UNLOCK_FAILED (1UL << 24)\r
+#define STAT_COM_CRC_ERROR (1UL << 23)\r
+#define STAT_ILLEGAL_COMMAND (1UL << 22)\r
+#define STAT_DEVICE_ECC_FAILED (1UL << 21)\r
+#define STAT_CC_ERROR (1UL << 20)\r
+#define STAT_ERROR (1UL << 19)\r
+#define STAT_CID_OVERWRITE (1UL << 16)\r
+#define STAT_ERASE_SKIP (1UL << 15)\r
+#define STAT_CARD_ECC_DISABLED (1UL << 14)\r
+#define STAT_ERASE_RESET (1UL << 13)\r
+#define STAT_CURRENT_STATE (0xfUL << 9)\r
+#define STAT_READY_FOR_DATA (1UL << 8)\r
+#define STAT_SWITCH_ERROR (1UL << 7)\r
+#define STAT_EXCEPTION_EVENT (1UL << 6)\r
+#define STAT_APP_CMD (1UL << 5)\r
+\r
+/** Device state */\r
+#define STATE_TRANSFER 0x4\r
+#define STATE_SENDING_DATA 0x5\r
+#define STATE_RECEIVE_DATA 0x6\r
+#define STATE_PROGRAMMING 0x7\r
+\r
+/** Driver state */\r
+#define MCID_OFF 0 /**< Device not powered */\r
+#define MCID_IDLE 1 /**< Idle */\r
+#define MCID_LOCKED 2 /**< Locked for specific slot */\r
+#define MCID_CMD 3 /**< Processing the command */\r
+#define MCID_ERROR 4 /**< Command error */\r
+\r
+/** A software event, never raised by the hardware, specific to this driver */\r
+#define SDMMC_NISTR_CUSTOM_EVT (0x1u << 13)\r
+\r
+union uint32_u {\r
+ uint32_t word;\r
+ uint8_t bytes[4];\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static uint32_t sdmmc_send_command(void *set, sSdmmcCommand *cmd);\r
+static uint8_t sdmmc_cancel_command(struct sdmmc_set *set);\r
+\r
+static void sdmmc_reset_peripheral(struct sdmmc_set *set)\r
+{\r
+ assert(set);\r
+\r
+ Sdmmc *regs = set->regs;\r
+ uint8_t mc1r, tcr;\r
+\r
+ /* First, save the few settings we'll want to restore. */\r
+ mc1r = regs->SDMMC_MC1R;\r
+ tcr = regs->SDMMC_TCR;\r
+\r
+ /* Reset the peripheral. This will reset almost all registers. */\r
+ regs->SDMMC_SRR |= SDMMC_SRR_SWRSTALL;\r
+ while (regs->SDMMC_SRR & SDMMC_SRR_SWRSTALL) ;\r
+\r
+ /* Restore specific register fields */\r
+ if (mc1r & SDMMC_MC1R_FCD)\r
+ regs->SDMMC_MC1R |= SDMMC_MC1R_FCD;\r
+ regs->SDMMC_TCR = (regs->SDMMC_TCR & ~SDMMC_TCR_DTCVAL_Msk)\r
+ | (tcr & SDMMC_TCR_DTCVAL_Msk);\r
+\r
+ /* Apply our unconditional custom settings */\r
+ /* When using DMA, use the 32-bit Advanced DMA 2 mode */\r
+ regs->SDMMC_HC1R = (regs->SDMMC_HC1R & ~SDMMC_HC1R_DMASEL_Msk)\r
+ | SDMMC_HC1R_DMASEL_ADMA32;\r
+ /* Configure maximum AHB burst size */\r
+ regs->SDMMC_ACR = (regs->SDMMC_ACR & ~SDMMC_ACR_BMAX_Msk)\r
+ | SDMMC_ACR_BMAX_INCR16;\r
+}\r
+\r
+static void sdmmc_power_device(struct sdmmc_set *set, bool on)\r
+{\r
+ assert(set);\r
+\r
+ Sdmmc *regs = set->regs;\r
+ uint32_t timer_res_prv, usec = 0;\r
+ uint8_t mc1r;\r
+\r
+ if ((on && set->state != MCID_OFF) || (!on && set->state == MCID_OFF))\r
+ return;\r
+ if (on) {\r
+ trace_debug("Power the device on\n\r");\r
+ /* Power the signals to/from the device */\r
+ regs->SDMMC_PCR |= SDMMC_PCR_SDBPWR;\r
+ set->state = MCID_IDLE;\r
+ return;\r
+ }\r
+ trace_debug("Release and power the device off\n\r");\r
+ if (set->state == MCID_CMD)\r
+ sdmmc_cancel_command(set);\r
+\r
+ /* Hardware-reset the e.MMC, move it to the pre-idle state.\r
+ * Note that this will only be effective on systems where\r
+ * 1) the RST_n e.MMC input is wired to the SDMMCx_RSTN PIO, and\r
+ * 2) the hardware reset functionality of the device has been\r
+ * enabled by software (!) Refer to ECSD register byte 162. */\r
+ timer_res_prv = timer_get_resolution();\r
+ /* Generate a pulse on SDMMCx_RSTN. Satisfy tRSTW >= 1 usec.\r
+ * The timer driver can't cope with periodic interrupts triggered as\r
+ * frequently as one interrupt per microsecond. Extend to 10 usec. */\r
+ timer_configure(10);\r
+ mc1r = regs->SDMMC_MC1R;\r
+ regs->SDMMC_MC1R = mc1r | SDMMC_MC1R_RSTN;\r
+ timer_sleep(1);\r
+ regs->SDMMC_MC1R = mc1r;\r
+ /* Wait for either tRSCA = 200 usec or 74 device clock cycles, as per\r
+ * the e.MMC Electrical Standard. */\r
+ if (set->dev_freq != 0)\r
+ usec = ROUND_INT_DIV(74 * 1000000UL / 10UL, set->dev_freq);\r
+ usec = usec < 20 ? 20 : usec;\r
+ timer_sleep(usec);\r
+ timer_configure(timer_res_prv);\r
+\r
+ /* Stop both the output clock and the SDMMC internal clock */\r
+ regs->SDMMC_CCR &= ~(SDMMC_CCR_SDCLKEN | SDMMC_CCR_INTCLKEN);\r
+ set->dev_freq = 0;\r
+ /* Cut the power rail supplying signals to/from the device */\r
+ regs->SDMMC_PCR &= ~SDMMC_PCR_SDBPWR;\r
+ /* Reset the peripheral. This will reset almost all registers. */\r
+ sdmmc_reset_peripheral(set);\r
+\r
+ set->state = MCID_OFF;\r
+}\r
+\r
+static uint8_t sdmmc_get_bus_width(struct sdmmc_set *set)\r
+{\r
+ assert(set);\r
+\r
+ const uint8_t hc1r = set->regs->SDMMC_HC1R;\r
+\r
+ if (hc1r & SDMMC_HC1R_EXTDW)\r
+ return 8;\r
+ else if (hc1r & SDMMC_HC1R_DW)\r
+ return 4;\r
+ else\r
+ return 1;\r
+}\r
+\r
+static uint8_t sdmmc_set_bus_width(struct sdmmc_set *set, uint8_t bits)\r
+{\r
+ assert(set);\r
+\r
+ Sdmmc *regs = set->regs;\r
+ uint8_t hc1r_prv, hc1r;\r
+\r
+ if (bits != 1 && bits != 4 && bits != 8)\r
+ return SDMMC_PARAM;\r
+ if (bits == 8 && !(regs->SDMMC_CA0R & SDMMC_CA0R_ED8SUP)) {\r
+ trace_error("This slot doesn't support an 8-bit data bus\n\r");\r
+ return SDMMC_PARAM;\r
+ }\r
+\r
+ hc1r = hc1r_prv = regs->SDMMC_HC1R;\r
+ if (bits == 8 && hc1r & SDMMC_HC1R_EXTDW)\r
+ return SDMMC_OK;\r
+ else if (bits == 8)\r
+ hc1r |= SDMMC_HC1R_EXTDW;\r
+ else {\r
+ hc1r &= ~SDMMC_HC1R_EXTDW;\r
+ if (bits == 4)\r
+ hc1r |= SDMMC_HC1R_DW;\r
+ else\r
+ hc1r &= ~SDMMC_HC1R_DW;\r
+ if (hc1r == hc1r_prv)\r
+ return SDMMC_OK;\r
+ }\r
+ regs->SDMMC_HC1R = hc1r;\r
+ return SDMMC_OK;\r
+}\r
+\r
+static bool sdmmc_get_speed_mode(struct sdmmc_set *set)\r
+{\r
+ assert(set);\r
+\r
+ if (set->regs->SDMMC_MC1R & SDMMC_MC1R_DDR)\r
+ return true;\r
+ if (set->regs->SDMMC_HC1R & SDMMC_HC1R_HSEN)\r
+ return true;\r
+ return false;\r
+}\r
+\r
+static uint8_t sdmmc_set_speed_mode(struct sdmmc_set *set, bool high_speed)\r
+{\r
+ assert(set);\r
+\r
+ Sdmmc *regs = set->regs;\r
+ uint8_t hc1r, mc1r;\r
+ bool enable_dev_clock;\r
+\r
+ if (high_speed && !(regs->SDMMC_CA0R & SDMMC_CA0R_HSSUP)) {\r
+ trace_error("This slot doesn't support High Speed Mode\n\r");\r
+ return SDMMC_PARAM;\r
+ }\r
+#ifndef NDEBUG\r
+ if (high_speed && !(regs->SDMMC_CCR & (SDMMC_CCR_USDCLKFSEL_Msk\r
+ | SDMMC_CCR_SDCLKFSEL_Msk))) {\r
+ trace_error("Incompatible with the current clock config\n\r");\r
+ return SDMMC_STATE;\r
+ }\r
+#endif\r
+ mc1r = regs->SDMMC_MC1R;\r
+ if (high_speed && mc1r & SDMMC_MC1R_DDR)\r
+ return SDMMC_OK;\r
+ if (!high_speed && mc1r & SDMMC_MC1R_DDR)\r
+ regs->SDMMC_MC1R = mc1r & ~SDMMC_MC1R_DDR;\r
+\r
+ hc1r = regs->SDMMC_HC1R;\r
+ if ((hc1r & SDMMC_HC1R_HSEN) == (high_speed ? SDMMC_HC1R_HSEN : 0))\r
+ return SDMMC_OK;\r
+ hc1r ^= SDMMC_HC1R_HSEN;\r
+ /* Avoid generating glitches on the device clock */\r
+ enable_dev_clock = regs->SDMMC_HC2R & SDMMC_HC2R_PVALEN\r
+ && regs->SDMMC_CCR & SDMMC_CCR_SDCLKEN;\r
+ if (enable_dev_clock)\r
+ regs->SDMMC_CCR &= ~SDMMC_CCR_SDCLKEN;\r
+ /* Now change the Speed Mode */\r
+ regs->SDMMC_HC1R = hc1r;\r
+ if (enable_dev_clock)\r
+ regs->SDMMC_CCR |= SDMMC_CCR_SDCLKEN;\r
+ return SDMMC_OK;\r
+}\r
+\r
+static void sdmmc_set_device_clock(struct sdmmc_set *set, uint32_t freq)\r
+{\r
+ assert(set);\r
+ assert(freq);\r
+\r
+ Sdmmc *regs = set->regs;\r
+ uint32_t base_freq, div, low_freq, up_freq, new_freq;\r
+ uint32_t mult_freq, p_div, p_mode_freq;\r
+ uint16_t shval;\r
+ bool use_prog_mode = false;\r
+\r
+#ifndef NDEBUG\r
+ if (regs->SDMMC_HC2R & SDMMC_HC2R_PVALEN)\r
+ trace_error("Preset values enabled though not implemented\n\r");\r
+#endif\r
+ /* In the Divided Clock Mode scenario, compute the divider */\r
+ base_freq = (regs->SDMMC_CA0R & SDMMC_CA0R_BASECLKF_Msk) >> SDMMC_CA0R_BASECLKF_Pos;\r
+ base_freq *= 1000000UL;\r
+ /* DIV = FBASECLK / (2 * FSDCLK) */\r
+ div = base_freq / (2 * freq);\r
+ if (div >= 0x3ff)\r
+ div = 0x3ff;\r
+ else {\r
+ up_freq = base_freq / (div == 0 ? 1UL : 2 * div);\r
+ low_freq = base_freq / (2 * (div + 1UL));\r
+ if (up_freq > freq && (up_freq - freq) > (freq - low_freq))\r
+ div += 1;\r
+ }\r
+ new_freq = base_freq / (div == 0 ? 1UL : 2 * div);\r
+\r
+ /* Now, in the Programmable Clock Mode scenario, compute the divider.\r
+ * First, retrieve the frequency of the Generated Clock feeding this\r
+ * peripheral. */\r
+ /* TODO fix CLKMULT value in CA1R capability register: the default value\r
+ * is 32 whereas the real value is 40.5 */\r
+ mult_freq = (regs->SDMMC_CA1R & SDMMC_CA1R_CLKMULT_Msk) >> SDMMC_CA1R_CLKMULT_Pos;\r
+ if (mult_freq != 0)\r
+#if 0\r
+ mult_freq = base_freq * (mult_freq + 1);\r
+#else\r
+ mult_freq = pmc_get_gck_clock(set->id);\r
+#endif\r
+ if (mult_freq != 0) {\r
+ /* DIV = FMULTCLK / FSDCLK - 1 */\r
+ p_div = ROUND_INT_DIV(mult_freq, freq);\r
+ if (p_div > 0x3ff)\r
+ p_div = 0x3ff;\r
+ else if (p_div != 0)\r
+ p_div = p_div - 1;\r
+ p_mode_freq = mult_freq / (p_div + 1);\r
+ if (ABS_DIFF(freq, p_mode_freq) < ABS_DIFF(freq, new_freq)) {\r
+ use_prog_mode = true;\r
+ div = p_div;\r
+ new_freq = p_mode_freq;\r
+ }\r
+ }\r
+\r
+ /* Stop both the output clock and the SDMMC internal clock */\r
+ shval = regs->SDMMC_CCR & ~SDMMC_CCR_SDCLKEN & ~SDMMC_CCR_INTCLKEN;\r
+ regs->SDMMC_CCR = shval;\r
+ set->dev_freq = new_freq;\r
+ /* Select the clock mode */\r
+ if (use_prog_mode)\r
+ shval |= SDMMC_CCR_CLKGSEL;\r
+ else\r
+ shval &= ~SDMMC_CCR_CLKGSEL;\r
+ /* Set the clock divider, and start the SDMMC internal clock */\r
+ shval = (shval & ~SDMMC_CCR_USDCLKFSEL_Msk & ~SDMMC_CCR_SDCLKFSEL_Msk)\r
+ | SDMMC_CCR_USDCLKFSEL(div >> 8) | SDMMC_CCR_SDCLKFSEL(div & 0xff)\r
+ | SDMMC_CCR_INTCLKEN;\r
+ regs->SDMMC_CCR = shval;\r
+ while (!(regs->SDMMC_CCR & SDMMC_CCR_INTCLKS)) ;\r
+ /* Now start the output clock */\r
+ regs->SDMMC_CCR |= SDMMC_CCR_SDCLKEN;\r
+}\r
+\r
+static uint8_t sdmmc_build_dma_table(struct sdmmc_set *set, sSdmmcCommand *cmd)\r
+{\r
+ assert(set);\r
+ assert(set->table);\r
+ assert(set->table_size);\r
+ assert(cmd->pData);\r
+ assert(cmd->wBlockSize);\r
+ assert(cmd->wNbBlocks);\r
+\r
+ uint32_t *line = NULL;\r
+ uint32_t data_len = (uint32_t)cmd->wNbBlocks\r
+ * (uint32_t)cmd->wBlockSize;\r
+ uint32_t ram_addr = (uint32_t)cmd->pData;\r
+ uint32_t ram_bound = ram_addr + data_len;\r
+ uint32_t line_ix, line_cnt;\r
+ uint8_t rc = SDMMC_OK;\r
+\r
+#if 0 && !defined(NDEBUG)\r
+ trace_debug("Configuring DMA for a %luB transfer %s %p\n\r",\r
+ data_len, cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX ? "from" : "to",\r
+ cmd->pData);\r
+#endif\r
+ /* Verify that cmd->pData is word-aligned */\r
+ if ((uint32_t)cmd->pData & 0x3)\r
+ return SDMMC_PARAM;\r
+ /* Compute the size of the descriptor table for this transfer */\r
+ line_cnt = (data_len - 1 + SDMMC_DMADL_TRAN_LEN_MAX)\r
+ / SDMMC_DMADL_TRAN_LEN_MAX;\r
+ /* If it won't fit into the allocated buffer, resize the transfer */\r
+ if (line_cnt > set->table_size) {\r
+ line_cnt = set->table_size;\r
+ data_len = line_cnt * SDMMC_DMADL_TRAN_LEN_MAX;\r
+ data_len /= cmd->wBlockSize;\r
+ if (data_len == 0)\r
+ return SDMMC_NOT_SUPPORTED;\r
+ cmd->wNbBlocks = (uint16_t)data_len;\r
+ data_len *= cmd->wBlockSize;\r
+ ram_bound = ram_addr + data_len;\r
+ rc = SDMMC_CHANGED;\r
+ }\r
+ /* Fill the table */\r
+ for (line_ix = 0, line = set->table; line_ix < line_cnt;\r
+ line_ix++, line += SDMMC_DMADL_SIZE) {\r
+ if (line_ix + 1 < line_cnt) {\r
+ line[0] = SDMMC_DMA0DL_LEN_MAX\r
+ | SDMMC_DMA0DL_ATTR_ACT_TRAN\r
+ | SDMMC_DMA0DL_ATTR_VALID;\r
+ line[1] = SDMMC_DMA1DL_ADDR(ram_addr);\r
+ ram_addr += SDMMC_DMADL_TRAN_LEN_MAX;\r
+ }\r
+ else {\r
+ line[0] = ram_bound - ram_addr\r
+ < SDMMC_DMADL_TRAN_LEN_MAX\r
+ ? SDMMC_DMA0DL_LEN(ram_bound - ram_addr)\r
+ : SDMMC_DMA0DL_LEN_MAX;\r
+ line[0] |= SDMMC_DMA0DL_ATTR_ACT_TRAN\r
+ | SDMMC_DMA0DL_ATTR_END | SDMMC_DMA0DL_ATTR_VALID;\r
+ line[1] = SDMMC_DMA1DL_ADDR(ram_addr);\r
+ }\r
+#if 0 && !defined(NDEBUG)\r
+ trace_debug("DMA descriptor: %luB @ 0x%lx%c\n\r",\r
+ (line[0] & SDMMC_DMA0DL_LEN_Msk) >> SDMMC_DMA0DL_LEN_Pos,\r
+ line[1], line[0] & SDMMC_DMA0DL_ATTR_END ? '.' : ' ');\r
+#endif\r
+ }\r
+ /* Clean the underlying cache lines, to ensure the DMA gets our table\r
+ * when it reads from RAM.\r
+ * CPU access to the table is write-only, peripheral/DMA access is read-\r
+ * only, hence there is no need to invalidate. */\r
+ l2cc_clean_region((uint32_t)set->table, (uint32_t)line);\r
+\r
+ return rc;\r
+}\r
+\r
+/**\r
+ * \brief Retrieve command response from the SDMMC peripheral.\r
+ * The response may be retrieved once per command.\r
+ */\r
+static void sdmmc_get_response(struct sdmmc_set *set, sSdmmcCommand *cmd,\r
+ bool complete, uint32_t *out)\r
+{\r
+ assert(set);\r
+ assert(cmd);\r
+ assert(cmd->cmdOp.bmBits.respType <= 7);\r
+ assert(out);\r
+\r
+ const bool first_call = set->resp_len == 0;\r
+ const bool has_data = cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX\r
+ || cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_RX;\r
+ uint32_t resp;\r
+ uint8_t ix;\r
+\r
+ if (first_call) {\r
+ switch (cmd->cmdOp.bmBits.respType) {\r
+ case 2:\r
+ /* R2 response is 120-bit long, split in\r
+ * 32+32+32+24 bits this way:\r
+ * RR[0] = R[ 39: 8]\r
+ * RR[1] = R[ 71: 40]\r
+ * RR[2] = R[103: 72]\r
+ * RR[3] = R[127:104]\r
+ * Shift data the way libsdmmc expects it,\r
+ * that is:\r
+ * pResp[0] = R[127: 96]\r
+ * pResp[1] = R[ 95: 64]\r
+ * pResp[2] = R[ 63: 32]\r
+ * pResp[3] = R[ 31: 0]\r
+ * The CRC7 and the end bit aren't provided,\r
+ * just hard-code their default values. */\r
+ out[3] = 0x000000ff;\r
+ for (ix = 0; ix < 4; ix++) {\r
+ resp = set->regs->SDMMC_RR[ix];\r
+ if (ix < 3)\r
+ out[2 - ix] = resp >> 24 & 0xff;\r
+ out[3 - ix] |= resp << 8 & 0xffffff00;\r
+ }\r
+ set->resp_len = 4;\r
+ break;\r
+ case 1: case 3: case 4: case 5: case 6: case 7:\r
+ /* The nominal response is 32-bit long */\r
+ out[0] = set->regs->SDMMC_RR[0];\r
+ set->resp_len = 1;\r
+ break;\r
+ case 0:\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (has_data && (cmd->bCmd == 18 || cmd->bCmd == 25) && ((first_call\r
+ && set->use_set_blk_cnt) || (complete && !set->use_set_blk_cnt))) {\r
+ resp = set->regs->SDMMC_RR[3];\r
+#if 0 && !defined(NDEBUG)\r
+ trace_debug("Auto CMD%d returned status 0x%lx\n\r",\r
+ set->use_set_blk_cnt ? 23 : 12, resp);\r
+#endif\r
+ if (!set->use_set_blk_cnt)\r
+ /* We return a single response to the application: the\r
+ * device status returned by CMD18 or CMD25, combined\r
+ * with the device status just returned by Auto CMD12.\r
+ * Retain the status bits from only CMD18 or CMD25, and\r
+ * combine the exception bits from both. */\r
+ out[0] |= resp & ~STAT_DEVICE_IS_LOCKED\r
+ & ~STAT_CARD_ECC_DISABLED & ~STAT_CURRENT_STATE\r
+ & ~STAT_READY_FOR_DATA & ~STAT_EXCEPTION_EVENT\r
+ & ~STAT_APP_CMD;\r
+#ifndef NDEBUG\r
+ resp = (resp & STAT_CURRENT_STATE) >> 9;\r
+ if (set->use_set_blk_cnt && resp != STATE_TRANSFER)\r
+ trace_warning("Auto CMD23 returned state %lx\n\r", resp)\r
+ else if (!set->use_set_blk_cnt && cmd->bCmd == 18\r
+ && resp != STATE_SENDING_DATA)\r
+ trace_warning("CMD18 switched to state %lx\n\r", resp)\r
+ else if (!set->use_set_blk_cnt && cmd->bCmd == 25\r
+ && resp != STATE_RECEIVE_DATA && resp != STATE_PROGRAMMING)\r
+ trace_warning("CMD25 switched to state %lx\n\r", resp)\r
+#endif\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Fetch events from the SDMMC peripheral, handle them, and proceed to\r
+ * the subsequent step, w.r.t. the SD/MMC command being processed.\r
+ * \warning This implementation suits LITTLE ENDIAN hosts only.\r
+ */\r
+static void sdmmc_poll(struct sdmmc_set *set)\r
+{\r
+ assert(set);\r
+ assert(set->state != MCID_OFF);\r
+\r
+ Sdmmc *regs = set->regs;\r
+ sSdmmcCommand *cmd = set->cmd;\r
+ uint16_t events, errors, acesr;\r
+ bool has_data;\r
+\r
+ if (set->state != MCID_CMD)\r
+ return;\r
+ assert(cmd);\r
+ has_data = cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX\r
+ || cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_RX;\r
+\r
+Fetch:\r
+ /* Fetch normal events */\r
+ events = regs->SDMMC_NISTR;\r
+ if (set->expect_auto_end && !(set->timer->TC_SR & TC_SR_CLKSTA))\r
+ events |= SDMMC_NISTR_CUSTOM_EVT;\r
+ if (!events)\r
+ return;\r
+\r
+ errors = 0;\r
+ /* Check the global error flag */\r
+ if (events & SDMMC_NISTR_ERRINT) {\r
+ errors = regs->SDMMC_EISTR;\r
+ events &= ~SDMMC_NISTR_ERRINT;\r
+ /* Clear error interrupts */\r
+ regs->SDMMC_EISTR = errors;\r
+ if (errors & SDMMC_EISTR_CURLIM)\r
+ cmd->bStatus = SDMMC_NOT_INITIALIZED;\r
+ else if (errors & SDMMC_EISTR_CMDCRC)\r
+ cmd->bStatus = SDMMC_ERR_IO;\r
+ else if (errors & SDMMC_EISTR_CMDTEO)\r
+ cmd->bStatus = SDMMC_NO_RESPONSE;\r
+ else if (errors & (SDMMC_EISTR_CMDEND | SDMMC_EISTR_CMDIDX))\r
+ cmd->bStatus = SDMMC_ERR_IO;\r
+ /* TODO if SDMMC_NISTR_TRFC and only SDMMC_EISTR_DATTEO then\r
+ * ignore SDMMC_EISTR_DATTEO */\r
+ else if (errors & SDMMC_EISTR_DATTEO)\r
+ cmd->bStatus = SDMMC_ERR_IO;\r
+ else if (errors & (SDMMC_EISTR_DATCRC | SDMMC_EISTR_DATEND))\r
+ cmd->bStatus = SDMMC_ERR_IO;\r
+ else if (errors & SDMMC_EISTR_ACMD) {\r
+ acesr = regs->SDMMC_ACESR;\r
+ if (acesr & SDMMC_ACESR_ACMD12NE)\r
+ cmd->bStatus = SDMMC_ERR;\r
+ else if (acesr & SDMMC_ACESR_ACMDCRC)\r
+ cmd->bStatus = SDMMC_ERR_IO;\r
+ else if (acesr & SDMMC_ACESR_ACMDTEO)\r
+ cmd->bStatus = SDMMC_NO_RESPONSE;\r
+ else if (acesr & (SDMMC_ACESR_ACMDEND | SDMMC_ACESR_ACMDIDX))\r
+ cmd->bStatus = SDMMC_ERR_IO;\r
+ else\r
+ cmd->bStatus = SDMMC_ERR;\r
+ }\r
+ else if (errors & SDMMC_EISTR_ADMA) {\r
+ cmd->bStatus = SDMMC_PARAM;\r
+ trace_error("ADMA error 0x%x at desc. line[%lu]\n\r",\r
+ regs->SDMMC_AESR, (regs->SDMMC_ASA0R -\r
+ (uint32_t)set->table) / (SDMMC_DMADL_SIZE * 4UL));\r
+ }\r
+ else if (errors & SDMMC_EISTR_BOOTAE)\r
+ cmd->bStatus = SDMMC_STATE;\r
+ else\r
+ cmd->bStatus = SDMMC_ERR;\r
+ set->state = cmd->bCmd == 12 ? MCID_LOCKED : MCID_ERROR;\r
+ /* Reset CMD and DAT lines.\r
+ * Resetting DAT lines also aborts the DMA transfer - if any -\r
+ * and resets the DMA circuit. */\r
+ regs->SDMMC_SRR |= SDMMC_SRR_SWRSTDAT | SDMMC_SRR_SWRSTCMD;\r
+ while (regs->SDMMC_SRR & (SDMMC_SRR_SWRSTDAT\r
+ | SDMMC_SRR_SWRSTCMD)) ;\r
+ trace_warning("CMD%u ended with error flags %04x, cmd status "\r
+ "%s\n\r", cmd->bCmd, errors, SD_StringifyRetCode(cmd->bStatus));\r
+ goto End;\r
+ }\r
+\r
+ /* No error. Give priority to the low-latency event that signals the\r
+ * completion of the Auto CMD12 command, hence of the whole multiple-\r
+ * block data transfer. */\r
+ if (events & SDMMC_NISTR_CUSTOM_EVT) {\r
+#ifndef NDEBUG\r
+ if (!(set->regs->SDMMC_PSR & SDMMC_PSR_CMDLL))\r
+ trace_warning("Command still ongoing\n\r");\r
+#endif\r
+ if (cmd->pResp)\r
+ sdmmc_get_response(set, cmd, true, cmd->pResp);\r
+ goto Succeed;\r
+ }\r
+\r
+ /* First, expect completion of the command */\r
+ if (events & SDMMC_NISTR_CMDC) {\r
+ /* Clear this normal interrupt */\r
+ regs->SDMMC_NISTR = SDMMC_NISTR_CMDC;\r
+ events &= ~SDMMC_NISTR_CMDC;\r
+#ifndef NDEBUG\r
+ if (cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX\r
+ && !set->table && set->blk_index != cmd->wNbBlocks\r
+ && !(regs->SDMMC_PSR & SDMMC_PSR_WTACT))\r
+ trace_warning("Write transfer not started\n\r")\r
+ else if (cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_RX\r
+ && !set->table && set->blk_index != cmd->wNbBlocks\r
+ && !(regs->SDMMC_PSR & SDMMC_PSR_RTACT))\r
+ trace_warning("Read transfer not started\n\r")\r
+#endif\r
+ /* Retrieve command response */\r
+ if (cmd->pResp)\r
+ sdmmc_get_response(set, cmd, false, cmd->pResp);\r
+ if (!has_data && !cmd->cmdOp.bmBits.checkBsy)\r
+ goto Succeed;\r
+ }\r
+\r
+ /* Expect the next incoming block of data */\r
+ if (events & SDMMC_NISTR_BRDRDY\r
+ && cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_RX && !set->table) {\r
+ /* FIXME may be optimized by looping while PSR.BUFRDEN == 1 */\r
+ uint8_t *in, *out, *bound;\r
+ union uint32_u val;\r
+ uint16_t count;\r
+\r
+ /* Clear this normal interrupt */\r
+ regs->SDMMC_NISTR = SDMMC_NISTR_BRDRDY;\r
+ events &= ~SDMMC_NISTR_BRDRDY;\r
+\r
+ if (set->blk_index >= cmd->wNbBlocks) {\r
+ trace_error("Excess of incoming data\n\r");\r
+ cmd->bStatus = SDMMC_ERR_IO;\r
+ set->state = MCID_ERROR;\r
+ goto End;\r
+ }\r
+ out = cmd->pData + set->blk_index * (uint32_t)cmd->wBlockSize;\r
+ count = cmd->wBlockSize & ~0x3;\r
+ for (bound = out + count; out < bound; out += 4) {\r
+#ifndef NDEBUG\r
+ if (!(regs->SDMMC_PSR & SDMMC_PSR_BUFRDEN))\r
+ trace_error("Unexpected Buffer Read Disable status\n\r");\r
+#endif\r
+ val.word = regs->SDMMC_BDPR;\r
+ out[0] = val.bytes[0];\r
+ out[1] = val.bytes[1];\r
+ out[2] = val.bytes[2];\r
+ out[3] = val.bytes[3];\r
+ }\r
+ if (count < cmd->wBlockSize) {\r
+#ifndef NDEBUG\r
+ if (!(regs->SDMMC_PSR & SDMMC_PSR_BUFRDEN))\r
+ trace_error("Unexpected Buffer Read Disable status\n\r");\r
+#endif\r
+ val.word = regs->SDMMC_BDPR;\r
+ count = cmd->wBlockSize - count;\r
+ for (in = val.bytes, bound = out + count;\r
+ out < bound; in++, out++)\r
+ *out = *in;\r
+ }\r
+#if 0 && !defined(NDEBUG)\r
+ if (regs->SDMMC_PSR & SDMMC_PSR_BUFRDEN)\r
+ trace_warning("Renewed Buffer Read Enable status\n\r");\r
+#endif\r
+ set->blk_index++;\r
+ }\r
+\r
+ /* Expect the Buffer Data Port to be ready to accept the next\r
+ * outgoing block of data */\r
+ if (events & SDMMC_NISTR_BWRRDY\r
+ && cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX && !set->table\r
+ && set->blk_index < cmd->wNbBlocks) {\r
+ /* FIXME may be optimized by looping while PSR.BUFWREN == 1 */\r
+ uint8_t *in, *out, *bound;\r
+ union uint32_u val;\r
+ uint16_t count;\r
+\r
+ /* Clear this normal interrupt */\r
+ regs->SDMMC_NISTR = SDMMC_NISTR_BWRRDY;\r
+ events &= ~SDMMC_NISTR_BWRRDY;\r
+\r
+ in = cmd->pData + set->blk_index * (uint32_t)cmd->wBlockSize;\r
+ count = cmd->wBlockSize & ~0x3;\r
+ for (bound = in + count; in < bound; in += 4) {\r
+ val.bytes[0] = in[0];\r
+ val.bytes[1] = in[1];\r
+ val.bytes[2] = in[2];\r
+ val.bytes[3] = in[3];\r
+#ifndef NDEBUG\r
+ if (!(regs->SDMMC_PSR & SDMMC_PSR_BUFWREN))\r
+ trace_error("Unexpected Buffer Write Disable status\n\r");\r
+#endif\r
+ regs->SDMMC_BDPR = val.word;\r
+ }\r
+ if (count < cmd->wBlockSize) {\r
+ count = cmd->wBlockSize - count;\r
+ for (val.word = 0, out = val.bytes, bound = in + count;\r
+ in < bound; in++, out++)\r
+ *out = *in;\r
+#ifndef NDEBUG\r
+ if (!(regs->SDMMC_PSR & SDMMC_PSR_BUFWREN))\r
+ trace_error("Unexpected Buffer Write Disable status\n\r");\r
+#endif\r
+ regs->SDMMC_BDPR = val.word;\r
+ }\r
+#if 0 && !defined(NDEBUG)\r
+ if (regs->SDMMC_PSR & SDMMC_PSR_BUFWREN)\r
+ trace_warning("Renewed Buffer Write Enable status\n\r");\r
+#endif\r
+ set->blk_index++;\r
+ }\r
+#ifndef NDEBUG\r
+ else if (events & SDMMC_NISTR_BWRRDY\r
+ && cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX && !set->table\r
+ && set->blk_index >= cmd->wNbBlocks)\r
+ trace_warning("Excess Buffer Write Ready status\n\r");\r
+#endif\r
+\r
+ /* Expect completion of either the data transfer or the busy state. */\r
+ if (events & SDMMC_NISTR_TRFC) {\r
+ /* Deviation from the SD Host Controller Specification:\r
+ * the Auto CMD12 command/response (when enabled) is still in\r
+ * progress. We are on our own to figure out when CMD12 will\r
+ * have completed.\r
+ * In the meantime:\r
+ * 1. errors affecting the CMD12 command - essentially\r
+ * SDMMC_EISTR_ACMD - have not been detected yet.\r
+ * 2. SDMMC_RR[3] is not yet valid.\r
+ * Our workaround here consists in generating a third event\r
+ * further to Transfer Complete, after a predefined amount of\r
+ * time, sufficient for CMD12 to complete.\r
+ * Refer to sdmmc_send_command(), which has prepared our Timer/\r
+ * Counter for this purpose. */\r
+ if (has_data && (cmd->bCmd == 18 || cmd->bCmd == 25)\r
+ && !set->use_set_blk_cnt) {\r
+ set->timer->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;\r
+ set->expect_auto_end = true;\r
+ }\r
+ /* Clear this normal interrupt */\r
+ regs->SDMMC_NISTR = SDMMC_NISTR_TRFC;\r
+ events &= ~SDMMC_NISTR_TRFC;\r
+ /* Deviation from the SD Host Controller Specification:\r
+ * there are cases, notably CMD7 with address and R1b, where the\r
+ * Command Complete interrupt does not occur. In such cases,\r
+ * the command response has not been retrieved yet. */\r
+ if (!set->expect_auto_end && cmd->pResp)\r
+ sdmmc_get_response(set, cmd, true, cmd->pResp);\r
+#ifndef NDEBUG\r
+ if (regs->SDMMC_PSR & SDMMC_PSR_WTACT)\r
+ trace_error("Write transfer still active\n\r");\r
+ if (regs->SDMMC_PSR & SDMMC_PSR_RTACT)\r
+ trace_error("Read transfer still active\n\r");\r
+#endif\r
+ if (has_data && !set->table\r
+ && set->blk_index != cmd->wNbBlocks) {\r
+ trace_error("Incomplete data transfer\n\r");\r
+ cmd->bStatus = SDMMC_ERR_IO;\r
+ set->state = MCID_ERROR;\r
+ goto End;\r
+ }\r
+ else if (has_data && set->table\r
+ && cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_RX)\r
+ l2cc_invalidate_region((uint32_t)cmd->pData,\r
+ (uint32_t)cmd->pData + (uint32_t)cmd->wNbBlocks\r
+ * (uint32_t)cmd->wBlockSize);\r
+ if (!set->expect_auto_end)\r
+ goto Succeed;\r
+ }\r
+\r
+#ifndef NDEBUG\r
+ if (events)\r
+ trace_warning("Unhandled NISTR events: 0x%04x\n\r", events);\r
+#endif\r
+ if (events)\r
+ regs->SDMMC_NISTR = events;\r
+ goto Fetch;\r
+\r
+Succeed:\r
+ set->state = MCID_LOCKED;\r
+End:\r
+ /* Clear residual normal interrupts, if any */\r
+ if (events)\r
+ regs->SDMMC_NISTR = events;\r
+#if 0 && !defined(NDEBUG)\r
+ if (set->resp_len == 1)\r
+ trace_debug("CMD%u got response %08lx\n\r", cmd->bCmd,\r
+ cmd->pResp[0])\r
+ else if (set->resp_len == 4)\r
+ trace_debug("CMD%u got response %08lx %08lx %08lx %08lx\n\r",\r
+ cmd->bCmd, cmd->pResp[0], cmd->pResp[1], cmd->pResp[2],\r
+ cmd->pResp[3])\r
+#endif\r
+ /* Release command */\r
+ set->cmd = NULL;\r
+ set->resp_len = 0;\r
+ set->blk_index = 0;\r
+ set->expect_auto_end = false;\r
+ /* Invoke the end-of-command fSdmmcCallback function, if provided */\r
+ if (cmd->fCallback)\r
+ (cmd->fCallback)(cmd->bStatus, cmd->pArg);\r
+}\r
+\r
+/**\r
+ * \brief Check if the command is finished.\r
+ */\r
+static bool sdmmc_is_busy(struct sdmmc_set *set)\r
+{\r
+ assert(set->state != MCID_OFF);\r
+\r
+ if (set->use_polling)\r
+ sdmmc_poll(set);\r
+ if (set->state == MCID_CMD)\r
+ return true;\r
+ return false;\r
+}\r
+\r
+static uint8_t sdmmc_cancel_command(struct sdmmc_set *set)\r
+{\r
+ assert(set);\r
+ assert(set->state != MCID_OFF);\r
+\r
+ Sdmmc *regs = set->regs;\r
+ sSdmmcCommand *cmd = set->cmd;\r
+ uint32_t response; /* The R1 response is 32-bit long */\r
+ uint32_t timer_res_prv, usec, rc;\r
+ sSdmmcCommand stop_cmd = {\r
+ .pResp = &response,\r
+ .cmdOp.wVal = SDMMC_CMD_CSTOP | SDMMC_CMD_bmBUSY,\r
+ .bCmd = 12,\r
+ };\r
+\r
+ if (set->state != MCID_CMD && set->state != MCID_ERROR)\r
+ return SDMMC_STATE;\r
+ trace_debug("Requested to cancel CMD%u\n\r", set->cmd ? set->cmd->bCmd : 99);\r
+ if (set->state == MCID_ERROR) {\r
+ set->state = MCID_LOCKED;\r
+ return SDMMC_OK;\r
+ }\r
+ assert(cmd);\r
+ /* Asynchronous Abort, if a data transfer has been started */\r
+ if (cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX\r
+ || cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_RX) {\r
+ /* May the CMD line still be busy, reset it */\r
+ if (regs->SDMMC_PSR & SDMMC_PSR_CMDINHC) {\r
+ regs->SDMMC_SRR |= SDMMC_SRR_SWRSTCMD;\r
+ while (regs->SDMMC_SRR & SDMMC_SRR_SWRSTCMD) ;\r
+ }\r
+ /* Issue the STOP_TRANSMISSION command. */\r
+ set->state = MCID_LOCKED;\r
+ set->cmd = NULL;\r
+ set->resp_len = 0;\r
+ set->blk_index = 0;\r
+ set->expect_auto_end = false;\r
+ rc = sdmmc_send_command(set, &stop_cmd);\r
+ if (rc == SDMMC_OK) {\r
+ timer_res_prv = timer_get_resolution();\r
+ timer_configure(10);\r
+ for (usec = 0; set->state == MCID_CMD && usec < 500000; usec+= 10) {\r
+ timer_sleep(1);\r
+ sdmmc_poll(set);\r
+ }\r
+ timer_configure(timer_res_prv);\r
+ }\r
+ }\r
+ /* Reset CMD and DATn lines */\r
+ regs->SDMMC_SRR |= SDMMC_SRR_SWRSTDAT | SDMMC_SRR_SWRSTCMD;\r
+ while (regs->SDMMC_SRR & (SDMMC_SRR_SWRSTDAT | SDMMC_SRR_SWRSTCMD)) ;\r
+ /* Release command */\r
+ cmd->bStatus = SDMMC_ERROR_USER_CANCEL;\r
+ set->state = MCID_LOCKED;\r
+ set->cmd = NULL;\r
+ set->resp_len = 0;\r
+ set->blk_index = 0;\r
+ set->expect_auto_end = false;\r
+ /* Invoke the end-of-command fSdmmcCallback function, if provided */\r
+ if (cmd->fCallback)\r
+ (cmd->fCallback)(cmd->bStatus, cmd->pArg);\r
+ return SDMMC_OK;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * HAL for the SD/MMC library\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Here is the fSdmmcLock-type callback.\r
+ * Lock the driver for slot N access.\r
+ * TODO implement, once used by the library.\r
+ */\r
+static uint32_t sdmmc_lock(void *_set, uint8_t slot)\r
+{\r
+ assert(_set);\r
+\r
+ if (slot > 0) {\r
+ return SDMMC_ERROR_PARAM;\r
+ }\r
+ return SDMMC_OK;\r
+}\r
+\r
+/**\r
+ * Here is the fSdmmcRelease-type callback.\r
+ * Release the driver.\r
+ * TODO implement, once used by the library.\r
+ */\r
+static uint32_t sdmmc_release(void *_set)\r
+{\r
+ assert(_set);\r
+\r
+ return SDMMC_OK;\r
+}\r
+\r
+/** \r
+ * Here is the fSdmmcIOCtrl-type callback.\r
+ * IO control functions.\r
+ * \param _set Pointer to driver instance data (struct sdmmc_set).\r
+ * \param bCtl IO control code.\r
+ * \param param IO control parameter. Optional, depends on the IO control code.\r
+ * \return Return code, from the eSDMMC_RC enumeration.\r
+ */\r
+static uint32_t sdmmc_control(void *_set, uint32_t bCtl, uint32_t param)\r
+{\r
+ assert(_set);\r
+\r
+ struct sdmmc_set *set = (struct sdmmc_set *)_set;\r
+ uint32_t rc = SDMMC_OK, *param_u32 = (uint32_t *)param;\r
+ uint8_t byte;\r
+\r
+#ifndef NDEBUG\r
+ if (bCtl != SDMMC_IOCTL_BUSY_CHECK && bCtl != SDMMC_IOCTL_GET_DEVICE)\r
+ trace_debug("%s(%lu)\n\r", SD_StringifyIOCtrl(bCtl),\r
+ param ? *param_u32 : 0);\r
+#endif\r
+\r
+ switch (bCtl) {\r
+ case SDMMC_IOCTL_GET_DEVICE:\r
+ if (!param)\r
+ return SDMMC_ERROR_PARAM;\r
+ *param_u32 = set->regs->SDMMC_PSR & SDMMC_PSR_CARDINS ? 1 : 0;\r
+ break;\r
+\r
+ case SDMMC_IOCTL_POWER:\r
+ if (!param)\r
+ return SDMMC_ERROR_PARAM;\r
+ sdmmc_power_device(set, *param_u32 ? true : false);\r
+ break;\r
+\r
+ case SDMMC_IOCTL_RESET:\r
+ /* Release the device. The device may have been removed. */\r
+ sdmmc_power_device(set, false);\r
+ break;\r
+\r
+ case SDMMC_IOCTL_GET_BUSMODE:\r
+ if (!param)\r
+ return SDMMC_ERROR_PARAM;\r
+ byte = sdmmc_get_bus_width(set);\r
+ *param_u32 = byte;\r
+ break;\r
+\r
+ case SDMMC_IOCTL_SET_BUSMODE:\r
+ if (!param)\r
+ return SDMMC_ERROR_PARAM;\r
+ if (*param_u32 > 0xff)\r
+ return SDMMC_ERROR_PARAM;\r
+ rc = sdmmc_set_bus_width(set, (uint8_t)*param_u32);\r
+ byte = sdmmc_get_bus_width(set);\r
+ trace_debug("Using a %u-bit data bus\n\r", byte);\r
+ break;\r
+\r
+ case SDMMC_IOCTL_GET_HSMODE:\r
+ if (!param)\r
+ return SDMMC_ERROR_PARAM;\r
+ *param_u32 = set->regs->SDMMC_CA0R & SDMMC_CA0R_HSSUP ? 1 : 0;\r
+ break;\r
+\r
+ case SDMMC_IOCTL_SET_HSMODE:\r
+ if (!param)\r
+ return SDMMC_ERROR_PARAM;\r
+ rc = sdmmc_set_speed_mode(set, *param_u32 ? true : false);\r
+ *param_u32 = sdmmc_get_speed_mode(set) ? 1 : 0;\r
+ trace_debug("Using %s mode\n\r", *param_u32 ? "High Speed" : "Default Speed");\r
+ break;\r
+\r
+ case SDMMC_IOCTL_SET_CLOCK:\r
+ if (!param)\r
+ return SDMMC_ERROR_PARAM;\r
+ if (*param_u32 == 0)\r
+ return SDMMC_ERROR_PARAM;\r
+ sdmmc_set_device_clock(set, *param_u32);\r
+ trace_debug("Clocking the device at %lu Hz\n\r", set->dev_freq);\r
+ if (set->dev_freq != *param_u32) {\r
+ rc = SDMMC_CHANGED;\r
+ *param_u32 = set->dev_freq;\r
+ }\r
+ break;\r
+\r
+ case SDMMC_IOCTL_SET_LENPREFIX:\r
+ if (!param)\r
+ return SDMMC_ERROR_PARAM;\r
+ set->use_set_blk_cnt = *param_u32 ? true : false;\r
+ *param_u32 = set->use_set_blk_cnt ? 1 : 0;\r
+ break;\r
+\r
+ case SDMMC_IOCTL_GET_XFERCOMPL:\r
+ if (!param)\r
+ return SDMMC_ERROR_PARAM;\r
+ *param_u32 = 1;\r
+ break;\r
+\r
+ case SDMMC_IOCTL_BUSY_CHECK:\r
+ if (!param)\r
+ return SDMMC_ERROR_PARAM;\r
+ if (set->state == MCID_OFF)\r
+ *param_u32 = 0;\r
+ else\r
+ *param_u32 = sdmmc_is_busy(set) ? 1 : 0;\r
+ break;\r
+\r
+ case SDMMC_IOCTL_CANCEL_CMD:\r
+ if (set->state == MCID_OFF)\r
+ rc = SDMMC_STATE;\r
+ else\r
+ rc = sdmmc_cancel_command(set);\r
+ break;\r
+\r
+ case SDMMC_IOCTL_GET_CLOCK:\r
+ case SDMMC_IOCTL_SET_BOOTMODE:\r
+ case SDMMC_IOCTL_GET_BOOTMODE:\r
+ default:\r
+ rc = SDMMC_ERROR_NOT_SUPPORT;\r
+ break;\r
+ }\r
+#ifndef NDEBUG\r
+ if (rc != SDMMC_OK && rc != SDMMC_CHANGED && bCtl != SDMMC_IOCTL_BUSY_CHECK)\r
+ trace_error("%s ended with %s\n\r", SD_StringifyIOCtrl(bCtl), SD_StringifyRetCode(rc));\r
+#endif\r
+ return rc;\r
+}\r
+\r
+/**\r
+ * Here is the fSdmmcSendCommand-type callback.\r
+ * SD/MMC command.\r
+ * \param _set Pointer to driver instance data (struct sdmmc_set).\r
+ * \param cmd Pointer to the command to be sent. Owned by the caller. Shall\r
+ * remain valid until the command is completed or stopped. For commands which\r
+ * transfer data, mind the peripheral and DMA alignment requirements that the\r
+ * external data buffer shall meet. Especially when DMA is used to read from the\r
+ * device, in which case the buffer shall be aligned on entire cache lines.\r
+ * \return Return code, from the eSDMMC_RC enumeration. If SDMMC_OK, the command\r
+ * has been issued and the caller should:\r
+ * 1. poll on sdmmc_is_busy(),\r
+ * 2. once finished, check the result of the command in cmd->bStatus.\r
+ * TODO in future when libsdmmc will set it: call sSdmmcCommand::fCallback.\r
+ */\r
+static uint32_t sdmmc_send_command(void *_set, sSdmmcCommand *cmd)\r
+{\r
+ assert(_set);\r
+ assert(cmd);\r
+ assert(cmd->bCmd <= 63);\r
+\r
+ struct sdmmc_set *set = (struct sdmmc_set *)_set;\r
+ Sdmmc *regs = set->regs;\r
+ const bool stop_xfer = cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_STOPXFR;\r
+ const bool has_data = cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX\r
+ || cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_RX;\r
+ const bool multiple_xfer = cmd->bCmd == 18 || cmd->bCmd == 25;\r
+ const bool blk_count_prefix = (cmd->bCmd == 18 || cmd->bCmd == 25)\r
+ && set->use_set_blk_cnt;\r
+ const bool stop_xfer_suffix = (cmd->bCmd == 18 || cmd->bCmd == 25)\r
+ && !set->use_set_blk_cnt;\r
+ uint32_t timer_res_prv, usec, eister, mask, cycles;\r
+ uint16_t cr, tmr;\r
+ uint8_t rc = SDMMC_OK, mc1r;\r
+\r
+ if (set->state == MCID_OFF)\r
+ return SDMMC_STATE;\r
+ if (cmd->cmdOp.bmBits.powerON == cmd->cmdOp.bmBits.sendCmd) {\r
+ trace_error("Invalid command\n\r");\r
+ return SDMMC_ERROR_PARAM;\r
+ }\r
+ if (stop_xfer && cmd->bCmd != 12 && cmd->bCmd != 52) {\r
+ trace_error("Inconsistent abort command\n\r");\r
+ return SDMMC_ERROR_PARAM;\r
+ }\r
+ if (cmd->cmdOp.bmBits.powerON) {\r
+ /* Special call, no command to send this time */\r
+ /* Wait for 74 SD Clock cycles, as per SD Card specification.\r
+ * The e.MMC Electrical Standard specifies tRSCA >= 200 usec. */\r
+ if (set->dev_freq == 0) {\r
+ trace_error("Shall enable the device clock first\n\r");\r
+ return SDMMC_ERROR_STATE;\r
+ }\r
+ timer_res_prv = timer_get_resolution();\r
+ usec = ROUND_INT_DIV(74 * 1000000UL, set->dev_freq);\r
+ timer_configure(usec < 200 ? 200 : usec);\r
+ timer_sleep(1);\r
+ timer_configure(timer_res_prv);\r
+ return SDMMC_OK;\r
+ }\r
+\r
+ if (has_data && (cmd->wNbBlocks == 0 || cmd->wBlockSize == 0\r
+ || cmd->pData == NULL)) {\r
+ trace_error("Invalid data\n\r");\r
+ return SDMMC_ERROR_PARAM;\r
+ }\r
+ if (has_data && cmd->wBlockSize > set->blk_size) {\r
+ trace_error("%u-byte data block size not supported\n\r", cmd->wBlockSize);\r
+ return SDMMC_ERROR_PARAM;\r
+ }\r
+ if (has_data && set->table) {\r
+ /* Using DMA. Prepare the descriptor table. */\r
+ rc = sdmmc_build_dma_table(set, cmd);\r
+ if (rc != SDMMC_OK && rc != SDMMC_CHANGED)\r
+ return rc;\r
+ if (cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX)\r
+ /* Ensure the outgoing data can be fetched directly from\r
+ * RAM */\r
+ l2cc_clean_region((uint32_t)cmd->pData,\r
+ (uint32_t)cmd->pData + (uint32_t)cmd->wNbBlocks\r
+ * (uint32_t)cmd->wBlockSize);\r
+ }\r
+ if (multiple_xfer && !has_data)\r
+ trace_warning("Inconsistent data\n\r");\r
+ if (sdmmc_is_busy(set)) {\r
+ trace_error("Concurrent command\n\r");\r
+ return SDMMC_ERROR_BUSY;\r
+ }\r
+ set->state = MCID_CMD;\r
+ set->cmd = cmd;\r
+ set->resp_len = 0;\r
+ set->blk_index = 0;\r
+ set->expect_auto_end = false;\r
+ cmd->bStatus = rc;\r
+\r
+ tmr = (regs->SDMMC_TMR & ~SDMMC_TMR_MSBSEL & ~SDMMC_TMR_DTDSEL\r
+ & ~SDMMC_TMR_ACMDEN_Msk & ~SDMMC_TMR_BCEN & ~SDMMC_TMR_DMAEN)\r
+ | SDMMC_TMR_ACMDEN_DIS;\r
+ mc1r = (regs->SDMMC_MC1R & ~SDMMC_MC1R_OPD & ~SDMMC_MC1R_CMDTYP_Msk)\r
+ | SDMMC_MC1R_CMDTYP_NORMAL;\r
+ cr = (regs->SDMMC_CR & ~SDMMC_CR_CMDIDX_Msk & ~SDMMC_CR_CMDTYP_Msk\r
+ & ~SDMMC_CR_DPSEL & ~SDMMC_CR_RESPTYP_Msk)\r
+ | SDMMC_CR_CMDIDX(cmd->bCmd) | SDMMC_CR_CMDTYP_NORMAL\r
+ | SDMMC_CR_CMDICEN | SDMMC_CR_CMDCCEN;\r
+ eister = SDMMC_EISTER_BOOTAE | SDMMC_EISTER_ADMA\r
+ | SDMMC_EISTER_ACMD | SDMMC_EISTER_CURLIM | SDMMC_EISTER_DATEND\r
+ | SDMMC_EISTER_DATCRC | SDMMC_EISTER_DATTEO | SDMMC_EISTER_CMDIDX\r
+ | SDMMC_EISTER_CMDEND | SDMMC_EISTER_CMDCRC | SDMMC_EISTER_CMDTEO;\r
+\r
+ if (cmd->cmdOp.bmBits.odON)\r
+ mc1r |= SDMMC_MC1R_OPD;\r
+ switch (cmd->cmdOp.bmBits.respType) {\r
+ case 2:\r
+ cr |= SDMMC_CR_RESPTYP_RL136;\r
+ /* R2 response doesn't include the command index */\r
+ eister &= ~SDMMC_EISTER_CMDIDX;\r
+ break;\r
+ case 3:\r
+ /* R3 response includes neither the command index nor the CRC */\r
+ eister &= ~(SDMMC_EISTER_CMDIDX | SDMMC_EISTER_CMDCRC);\r
+ case 1:\r
+ case 4:\r
+ if (cmd->cmdOp.bmBits.respType == 4 && cmd->cmdOp.bmBits.ioCmd)\r
+ /* SDIO R4 response includes neither the command index nor the CRC */\r
+ eister &= ~(SDMMC_EISTER_CMDIDX | SDMMC_EISTER_CMDCRC);\r
+ case 5:\r
+ case 6:\r
+ case 7:\r
+ cr |= cmd->cmdOp.bmBits.checkBsy ? SDMMC_CR_RESPTYP_RL48BUSY\r
+ : SDMMC_CR_RESPTYP_RL48;\r
+ break;\r
+ default:\r
+ /* No response, ignore response time-out error */\r
+ cr |= SDMMC_CR_RESPTYP_NORESP;\r
+ eister &= ~SDMMC_EISTER_CMDTEO;\r
+ break;\r
+ }\r
+ if (stop_xfer) {\r
+ tmr |= SDMMC_TMR_MSBSEL | SDMMC_TMR_BCEN;\r
+ /* TODO consider BGCR:STPBGR (pause) */\r
+ /* TODO in case of SDIO consider CR:CMDTYP = ABORT */\r
+ /* Ignore data errors */\r
+ eister = eister & ~SDMMC_EISTER_ADMA & ~SDMMC_EISTER_DATEND\r
+ & ~SDMMC_EISTER_DATCRC & ~SDMMC_EISTER_DATTEO;\r
+ }\r
+ else if (has_data) {\r
+ cr |= SDMMC_CR_DPSEL;\r
+ tmr |= cmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX\r
+ ? SDMMC_TMR_DTDSEL_WR : SDMMC_TMR_DTDSEL_RD;\r
+ if (blk_count_prefix)\r
+ tmr = (tmr & ~SDMMC_TMR_ACMDEN_Msk)\r
+ | SDMMC_TMR_ACMDEN_ACMD23;\r
+ else if (stop_xfer_suffix)\r
+ tmr = (tmr & ~SDMMC_TMR_ACMDEN_Msk)\r
+ | SDMMC_TMR_ACMDEN_ACMD12;\r
+ /* TODO check if this is fine for SDIO too (byte or block transfer) (cmd->cmdOp.bmBits.ioCmd, cmd->wBlockSize) */\r
+ if (multiple_xfer || cmd->wNbBlocks > 1)\r
+ tmr |= SDMMC_TMR_MSBSEL | SDMMC_TMR_BCEN;\r
+ if (set->table)\r
+ tmr |= SDMMC_TMR_DMAEN;\r
+ }\r
+\r
+ /* Enable normal interrupts */\r
+ regs->SDMMC_NISTER |= SDMMC_NISTER_BRDRDY | SDMMC_NISTER_BWRRDY\r
+ | SDMMC_NISTER_TRFC | SDMMC_NISTER_CMDC;\r
+ assert(!(regs->SDMMC_NISTER & SDMMC_NISTR_CUSTOM_EVT));\r
+ /* Enable error interrupts */\r
+ regs->SDMMC_EISTER = eister;\r
+ /* Clear all interrupt status flags */\r
+ regs->SDMMC_NISTR = SDMMC_NISTR_ERRINT | SDMMC_NISTR_BOOTAR\r
+ | SDMMC_NISTR_CINT | SDMMC_NISTR_CREM | SDMMC_NISTR_CINS\r
+ | SDMMC_NISTR_BRDRDY | SDMMC_NISTR_BWRRDY | SDMMC_NISTR_DMAINT\r
+ | SDMMC_NISTR_BLKGE | SDMMC_NISTR_TRFC | SDMMC_NISTR_CMDC;\r
+ regs->SDMMC_EISTR = SDMMC_EISTR_BOOTAE | SDMMC_EISTR_ADMA\r
+ | SDMMC_EISTR_ACMD | SDMMC_EISTR_CURLIM | SDMMC_EISTR_DATEND\r
+ | SDMMC_EISTR_DATCRC | SDMMC_EISTR_DATTEO | SDMMC_EISTR_CMDIDX\r
+ | SDMMC_EISTR_CMDEND | SDMMC_EISTR_CMDCRC | SDMMC_EISTR_CMDTEO;\r
+\r
+ /* Wait for the CMD and DATn lines to be ready */\r
+ mask = SDMMC_PSR_CMDINHC;\r
+ if (has_data || (cmd->cmdOp.bmBits.checkBsy && !stop_xfer))\r
+ mask |= SDMMC_PSR_CMDINHD;\r
+ while (regs->SDMMC_PSR & mask) ;\r
+\r
+ /* Issue the command */\r
+ if (has_data) {\r
+ if (blk_count_prefix)\r
+ regs->SDMMC_SSAR = SDMMC_SSAR_ARG2(cmd->wNbBlocks);\r
+ if (set->table)\r
+ regs->SDMMC_ASA0R =\r
+ SDMMC_ASA0R_ADMASA((uint32_t)set->table);\r
+ regs->SDMMC_BSR = (regs->SDMMC_BSR & ~SDMMC_BSR_BLKSIZE_Msk)\r
+ | SDMMC_BSR_BLKSIZE(cmd->wBlockSize);\r
+ }\r
+ if (stop_xfer)\r
+ regs->SDMMC_BCR = SDMMC_BCR_BLKCNT(0);\r
+ else if (has_data && (multiple_xfer || cmd->wNbBlocks > 1))\r
+ regs->SDMMC_BCR = SDMMC_BCR_BLKCNT(cmd->wNbBlocks);\r
+ regs->SDMMC_ARG1R = cmd->dwArg;\r
+ if (has_data || stop_xfer)\r
+ regs->SDMMC_TMR = tmr;\r
+ regs->SDMMC_MC1R = mc1r;\r
+ regs->SDMMC_CR = cr;\r
+\r
+ /* In the case of Auto CMD12, we'll need to generate an extra event.\r
+ * Have our Timer/Counter ready for this. */\r
+ if (has_data && stop_xfer_suffix) {\r
+ /* Considering the multiple block read mode,\r
+ * 1. Assuming Transfer Complete is raised upon successful\r
+ * reception of the End bit of the last data packet,\r
+ * 2. A SD/eMMC protocol analyzer shows that the CMD12 command\r
+ * token is fully transmitted 1 or 2 device clock cycles\r
+ * later,\r
+ * 3. The device may take up to 64 clock cycles (NCR) before\r
+ * initiating the CMD12 response token,\r
+ * 4. The code length of the CMD12 response token (R1) is 48\r
+ * bits, hence 48 device clock cycles.\r
+ * The sum of the above timings is the maximum time CMD12 will\r
+ * take to complete. */\r
+ cycles = pmc_get_peripheral_clock(set->tc_id)\r
+ / (set->dev_freq / (2ul + 64ul + 48ul));\r
+ /* The Timer operates with RC >= 1 */\r
+ set->timer->TC_RC = cycles ? cycles : 1;\r
+ }\r
+\r
+ return SDMMC_OK;\r
+}\r
+\r
+static sSdHalFunctions sdHal = {\r
+ .fLock = sdmmc_lock,\r
+ .fRelease = sdmmc_release,\r
+ .fCommand = sdmmc_send_command,\r
+ .fIOCtrl = sdmmc_control,\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+bool sdmmc_initialize(struct sdmmc_set *set, Sdmmc *regs, uint32_t periph_id,\r
+ uint32_t tc_id, uint32_t tc_ch, uint32_t *dma_buf, uint32_t dma_buf_size)\r
+{\r
+ assert(set);\r
+ assert(regs);\r
+ assert(periph_id <= 0xff);\r
+ assert(tc_ch < TCCHANNEL_NUMBER);\r
+\r
+ Tc * const tc_module = get_tc_addr_from_id(tc_id);\r
+ uint32_t base_freq, power, val;\r
+ const uint8_t max_exp = (SDMMC_TCR_DTCVAL_Msk >> SDMMC_TCR_DTCVAL_Pos) - 1;\r
+ uint8_t exp;\r
+\r
+ assert(tc_module);\r
+ memset(set, 0, sizeof(*set));\r
+ set->id = periph_id;\r
+ set->regs = regs;\r
+ set->tc_id = tc_id;\r
+ set->timer = &tc_module->TC_CHANNEL[tc_ch];\r
+ set->table_size = dma_buf ? dma_buf_size / SDMMC_DMADL_SIZE : 0;\r
+ set->table = set->table_size ? dma_buf : NULL;\r
+ set->use_polling = true;\r
+ set->use_set_blk_cnt = false;\r
+ set->state = MCID_OFF;\r
+\r
+ val = (regs->SDMMC_CA0R & SDMMC_CA0R_MAXBLKL_Msk) >> SDMMC_CA0R_MAXBLKL_Pos;\r
+ set->blk_size = val <= 0x2 ? 512 << val : 512;\r
+\r
+ /* Prepare our Timer/Counter */\r
+ tc_configure(tc_module, tc_ch, TC_CMR_WAVE | TC_CMR_WAVSEL_UP\r
+ | TC_CMR_CPCDIS | TC_CMR_BURST_NONE | TC_CMR_TCCLKS_TIMER_CLOCK2);\r
+ set->timer->TC_EMR |= TC_EMR_NODIVCLK;\r
+\r
+ /* Perform the initial I/O calibration sequence, manually.\r
+ * Allow tSTARTUP = 2 usec for the analog circuitry to start up.\r
+ * CNTVAL = fHCLOCK / (4 * (1 / tSTARTUP)) */\r
+ val = pmc_get_peripheral_clock(periph_id);\r
+ val = ROUND_INT_DIV(val, 4 * 500000UL);\r
+ assert(!(val << SDMMC_CALCR_CNTVAL_Pos & ~SDMMC_CALCR_CNTVAL_Msk));\r
+ regs->SDMMC_CALCR = (regs->SDMMC_CALCR & ~SDMMC_CALCR_CNTVAL_Msk) | SDMMC_CALCR_CNTVAL(val);\r
+ regs->SDMMC_CALCR |= SDMMC_CALCR_EN;\r
+ while (regs->SDMMC_CALCR & SDMMC_CALCR_EN) ;\r
+ val = regs->SDMMC_CALCR;\r
+ trace_info("Result of output impedance calibration: CALN=%lu, CALP=%lu.\n\r",\r
+ (val & SDMMC_CALCR_CALN_Msk) >> SDMMC_CALCR_CALN_Pos,\r
+ (val & SDMMC_CALCR_CALP_Msk) >> SDMMC_CALCR_CALP_Pos);\r
+\r
+ /* Set DAT line timeout error to occur after 500 ms waiting delay.\r
+ * 500 ms is the timeout value to implement when writing to SDXC cards.\r
+ */\r
+ base_freq = (regs->SDMMC_CA0R & SDMMC_CA0R_TEOCLKF_Msk) >> SDMMC_CA0R_TEOCLKF_Pos;\r
+ base_freq *= regs->SDMMC_CA0R & SDMMC_CA0R_TEOCLKU ? 1000000UL : 1000UL;\r
+ /* 2 ^ (DTCVAL + 13) = TIMEOUT * FTEOCLK = FTEOCLK / 2 */\r
+ val = base_freq / 2;\r
+ for (exp = 31, power = 1UL << 31; !(val & power) && power != 0;\r
+ exp--, power >>= 1) ;\r
+ if (power == 0) {\r
+ trace_warning("FTEOCLK is unknown\n\r");\r
+ exp = max_exp;\r
+ }\r
+ else {\r
+ exp = exp + 1 - 13;\r
+ exp = exp <= max_exp ? exp : max_exp;\r
+ }\r
+ regs->SDMMC_TCR = (regs->SDMMC_TCR & ~SDMMC_TCR_DTCVAL_Msk)\r
+ | SDMMC_TCR_DTCVAL(exp);\r
+ trace_debug("Set DAT line timeout to %lu ms\n\r", (10UL << (exp + 13UL))\r
+ / (base_freq / 100UL));\r
+\r
+ /* Reset the peripheral. This will reset almost all registers.\r
+ * It doesn't affect I/O calibration however. */\r
+ sdmmc_reset_peripheral(set);\r
+ /* As sdmmc_reset_peripheral deliberately preserves MC1R.FCD, this field\r
+ * has yet to be initialized. */\r
+ regs->SDMMC_MC1R &= ~SDMMC_MC1R_FCD;\r
+\r
+ return true;\r
+}\r
+\r
+/**\r
+ * \brief Initialize the SD/MMC library instance for SD/MMC bus mode (versus\r
+ * SPI mode, not supported by this driver). Provide it with the HAL callback\r
+ * functions implemented here.\r
+ * \param pSd Pointer to SD/MMC library instance data.\r
+ * \param pDrv Pointer to driver instance data (struct sdmmc_set).\r
+ * \param bSlot Slot number.\r
+ */\r
+void SDD_InitializeSdmmcMode(sSdCard *pSd, void *pDrv, uint8_t bSlot)\r
+{\r
+ SDD_Initialize(pSd, pDrv, bSlot, &sdHal);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _SDMMC_PERIPH_H_\r
+#define _SDMMC_PERIPH_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+struct _SdmmcCommand;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* This structure is private to the SDMMC Driver.\r
+ * Allocate it but ignore its members. */\r
+struct sdmmc_set\r
+{\r
+ uint32_t id; /* SDMMC peripheral ID (ID_SDMMCx) */\r
+ Sdmmc *regs; /* set of SDMMC hardware registers */\r
+ uint32_t tc_id; /* Timer/Counter peripheral ID (ID_TCx) */\r
+ TcChannel *timer; /* set of TC channel hardware registers */\r
+ uint32_t *table; /* ADMA descriptor table, or NULL when DMA\r
+ * is not used */\r
+ uint32_t table_size; /* Max size of the ADMA descriptor table,\r
+ * in lines */\r
+ bool use_polling; /* polling mode */\r
+ bool use_set_blk_cnt; /* implicit SET_BLOCK_COUNT command */\r
+\r
+ uint16_t blk_size; /* max data block size, in bytes */\r
+ uint32_t dev_freq; /* frequency of clock provided to memory\r
+ * device, in Hz */\r
+ volatile uint8_t state;\r
+ struct _SdmmcCommand *cmd; /* pointer to the command being processed */\r
+ uint16_t blk_index; /* count of data blocks tranferred already,\r
+ * in the context of the command and data\r
+ * transfer being executed */\r
+ uint8_t resp_len; /* size of the response, once retrieved,\r
+ * in the context of the command being\r
+ * executed, expressed in 32-bit words */\r
+ bool expect_auto_end; /* waiting for completion of Auto CMD12 */\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initialize the specified driver instance and the associated SDMMC \r
+ * peripheral.\r
+ * \param set Pointer to uninitialized driver instance data.\r
+ * \param regs Base address of registers of the SDMMC peripheral.\r
+ * \param sdmmc_id SDMMC peripheral ID (ID_SDMMCx).\r
+ * \param tc_id TC peripheral ID (ID_TCx).\r
+ * \note The application shall have enabled the clock assigned to this\r
+ * Timer/Counter peripheral.\r
+ * \param tc_ch TC channel number, within the Timer/Counter module designated\r
+ * by tc_id. Every instance of the SDMMC Driver requires a Timer/Counter channel\r
+ * for its exclusive usage.\r
+ * \param dma_buf Buffer allocated by the application, required when DMA is\r
+ * used. This is where the DMA descriptor table will be set up. The larger\r
+ * the buffer is, the greater throughput we achieve. Up to 4 KiB. Shall be\r
+ * word-aligned. NULL to have the CPU read/write data, word by word.\r
+ * \param dma_buf_size Size of the dma_buf buffer, in words.\r
+ * \return true if successful, false if a parameter is assigned an unsupported\r
+ * value.\r
+ */\r
+bool sdmmc_initialize(struct sdmmc_set *set, Sdmmc *regs, uint32_t sdmmc_id,\r
+ uint32_t tc_id, uint32_t tc_ch, uint32_t *dma_buf, uint32_t dma_buf_size);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _SDMMC_PERIPH_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "peripherals/sfrbu.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void sfrbu_enable_ddr_backup(void)\r
+{\r
+ /* Enable DDR backup mode. Isolate the DDR Pads from the CPU domain,\r
+ VCCCORE */\r
+ SFRBU->SFRBU_DDRBUMCR = SFRBU_DDRBUMCR_BUMEN;\r
+}\r
+\r
+void sfrbu_disable_ddr_backup(void)\r
+{\r
+ /* Connect the DDR Pads to the CPU domain, VCCCORE */\r
+ SFRBU->SFRBU_DDRBUMCR &= ~SFRBU_DDRBUMCR_BUMEN;\r
+}\r
+\r
+bool sfrbu_is_ddr_backup_enabled(void)\r
+{\r
+ return (SFRBU->SFRBU_DDRBUMCR & SFRBU_DDRBUMCR_BUMEN) != 0;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _SFRBU_H\r
+#define _SFRBU_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Enable DDR backup\r
+ */\r
+extern void sfrbu_enable_ddr_backup(void);\r
+\r
+/**\r
+ * \brief Disable DDR backup\r
+ */\r
+extern void sfrbu_disable_ddr_backup(void);\r
+\r
+/**\r
+ * \brief Get DDR backup status\r
+ * \return true if DDR BU Mode is enabled, false otherwise\r
+ */\r
+extern bool sfrbu_is_ddr_backup_enabled(void);\r
+\r
+#endif //#ifndef _SFRBU_H\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup sha_module Working with SHA\r
+ * \ingroup peripherals_module\r
+ * The SHA driver provides the interface to configure and use the SHA\r
+ * peripheral.\r
+ * \n\r
+ *\r
+ * The Secure Hash Algorithm (SHA) module requires a padded message\r
+ * according to FIPS180-2 specification. The first block of the\r
+ * message must be indicated to the module by a specific command. The\r
+ * SHA module produces a N-bit message digest each time a block is\r
+ * written and processing period ends. N is 160 for SHA1, 224 for\r
+ * SHA224, 256 for SHA256, 384 for SHA384, 512 for SHA512.\r
+ *\r
+ * To Enable a SHA encryption and decrypt,the user has to follow these\r
+ * few steps:\r
+ * <ul>\r
+ * <li> Configure SHA algorithm mode, key mode, start mode and\r
+ * operation mode by sha_configure(). </li>\r
+ * <li> Set sha_first_block() to indicates that the next block to\r
+ * process is the first one of a message.</li>\r
+ * <li> Input data for encryption by sha_set_input(). </li>\r
+ * <li> To start the encryption process with sha_start()</li>\r
+ * <li> To get the encryption reslut by sha_get_output() </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the SHA section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref sha.c\n\r
+ * \ref sha.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Secure Hash Algorithm (SHA)\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/sha.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void sha_start(void)\r
+{\r
+ SHA->SHA_CR = SHA_CR_START;\r
+}\r
+\r
+void sha_soft_reset(void)\r
+{\r
+ SHA->SHA_CR = SHA_CR_SWRST;\r
+}\r
+\r
+void sha_first_block(void)\r
+{\r
+ SHA->SHA_CR = SHA_CR_FIRST;\r
+}\r
+\r
+void sha_configure(uint32_t mode)\r
+{\r
+ SHA->SHA_MR = mode;\r
+}\r
+\r
+void sha_enable_it(uint32_t sources)\r
+{\r
+ SHA->SHA_IER = sources;\r
+}\r
+\r
+void sha_disable_it(uint32_t sources)\r
+{\r
+ SHA->SHA_IDR = sources;\r
+}\r
+\r
+uint32_t sha_get_status(void)\r
+{\r
+ return SHA->SHA_ISR;\r
+}\r
+\r
+void sha_set_input(uint32_t * data, uint8_t len)\r
+{\r
+ uint8_t i;\r
+ uint8_t num;\r
+ num = len <= 16 ? len : 16;\r
+ for (i = 0; i < num; i++)\r
+ SHA->SHA_IDATAR[i] = (data[i]);\r
+ num = len > 16 ? len - 16 : 0;\r
+ for (i = 0; i < num; i++)\r
+ SHA->SHA_IODATAR[i] = (data[i + 16]);\r
+}\r
+\r
+void sha_get_output(uint32_t * data)\r
+{\r
+ uint8_t i;\r
+ for (i = 0; i < 16; i++)\r
+ data[i] = SHA->SHA_IODATAR[i];\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _SHA_\r
+#define _SHA_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Exported functions */\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Starts Manual hash algorithm process.\r
+ */\r
+extern void sha_start(void);\r
+\r
+/**\r
+ * \brief Resets the SHA. A software triggered hardware reset of the\r
+ * SHA interface is performed.\r
+ */\r
+extern void sha_soft_reset(void);\r
+\r
+/**\r
+ * \brief Indicates that the next block to process is the first one of\r
+ * a message.\r
+ */\r
+extern void sha_first_block(void);\r
+\r
+/**\r
+ * \brief Configures an SHA peripheral with the specified parameters.\r
+ * \param mode Desired value for the SHA mode register (see the datasheet).\r
+ */\r
+extern void sha_configure(uint32_t mode);\r
+\r
+/**\r
+ * \brief Enables the selected interrupts sources on a SHA peripheral.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+extern void sha_enable_it(uint32_t sources);\r
+\r
+/**\r
+ * \brief Disables the selected interrupts sources on a SHA peripheral.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+extern void sha_disable_it(uint32_t sources);\r
+\r
+/**\r
+ * \brief Get the current status register of the given SHA peripheral.\r
+ * \return SHA status register.\r
+ */\r
+extern uint32_t sha_get_status(void);\r
+\r
+/**\r
+ * \brief Set the 32-bit Input Data registers allow to load the data block used for hash processing.\r
+ * \param data Pointer data block.\r
+ * \param len 512/1024-bits block size\r
+ */\r
+extern void sha_set_input(uint32_t * data, uint8_t len);\r
+\r
+/**\r
+ * \brief Getread the resulting message digest and to write the second part of the message block when the\r
+* SHA algorithm is SHA-384 or SHA-512.\r
+ * \param data pointer to the word that has been encrypted/decrypted..\r
+ */\r
+extern void sha_get_output(uint32_t * data);\r
+\r
+#endif /* #ifndef _SHA_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/shdwc.h"\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local Defines\r
+ *----------------------------------------------------------------------------*/\r
+\r
+struct _bitfield_shdwc_cfgr {\r
+ uint32_t\r
+ lpdbcen0: 1,\r
+ lpdbcen1: 1,\r
+ rfu2_7: 6,\r
+ lpdbc: 3,\r
+ rfu10_15: 5,\r
+ rttwken: 1,\r
+ rtcwken: 1,\r
+ accwken: 1,\r
+ rxlpwken: 1,\r
+ rfu20_23: 4,\r
+ wkupdbc: 3,\r
+ rfu26_31: 5;\r
+};\r
+\r
+union _shdwc_cfg {\r
+ struct _bitfield_shdwc_cfgr bfield;\r
+ uint32_t uint32_value;\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void shdwc_configure_wakeup_mode(uint32_t config)\r
+{\r
+ union _shdwc_cfg cfg;\r
+\r
+ cfg.uint32_value = SHDWC->SHDW_MR;\r
+\r
+ cfg.bfield.lpdbcen0 = (config & SHDW_MR_LPDBCEN0_ENABLE) ? 1 : 0;\r
+ cfg.bfield.lpdbcen1 = (config & SHDW_MR_LPDBCEN1_ENABLE) ? 1 : 0;\r
+ cfg.bfield.lpdbc = (config & SHDW_MR_LPDBC_Msk) >> SHDW_MR_LPDBC_Pos;\r
+ cfg.bfield.rttwken = (config & SHDW_MR_RTTWKEN) ? 1 : 0;\r
+ cfg.bfield.rtcwken = (config & SHDW_MR_RTCWKEN) ? 1 : 0;\r
+ cfg.bfield.accwken = (config & SHDW_MR_ACCWKEN) ? 1 : 0;\r
+ cfg.bfield.rxlpwken = (config & SHDW_MR_RXLPWKEN) ? 1 : 0;\r
+ cfg.bfield.wkupdbc = (config & SHDW_MR_WKUPDBC_Msk) >> SHDW_MR_WKUPDBC_Pos;\r
+\r
+ SHDWC->SHDW_MR = cfg.uint32_value;\r
+}\r
+\r
+void shdwc_set_wakeup_input(uint32_t input_enable, uint32_t input_type)\r
+{\r
+ uint32_t wuir = (input_enable & 0x0000FFFF) | (input_type & 0xFFFF0000);\r
+\r
+ SHDWC->SHDW_WUIR |= wuir;\r
+}\r
+\r
+void shdwc_do_shutdown(void)\r
+{\r
+ SHDWC->SHDW_CR = SHDW_CR_KEY_PASSWD | SHDW_CR_SHDW;\r
+}\r
+\r
+uint32_t shdwc_get_status(void)\r
+{\r
+ return SHDWC->SHDW_SR;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _SHDWC_H\r
+#define _SHDWC_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configure the Shutdown Mode Register\r
+ */\r
+extern void shdwc_configure_wakeup_mode(uint32_t config);\r
+\r
+/**\r
+ * \brief Configure the Shutdown Wake-up Input Register\r
+ *\r
+ * \param input_enable, WKUPEN0-WKUPEN15: define the corresponding\r
+ * wake-up input.\r
+ * \param input_type, WKUPT0-WKUPT15: define falling or rising edge\r
+ * on wake-up input.\r
+ */\r
+extern void shdwc_set_wakeup_input(uint32_t input_enable,\r
+ uint32_t input_type);\r
+\r
+/**\r
+ * \brief Launch the ShutDown\r
+ */\r
+extern void shdwc_do_shutdown(void);\r
+\r
+/**\r
+ * \brief Get Status\r
+ * \return Contents of the Shutdown Status Register\r
+ */\r
+extern uint32_t shdwc_get_status(void);\r
+\r
+#endif //#ifndef _SHDWC_H\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup spi_module Working with SPI\r
+ * \section Purpose\r
+ * The SPI driver provides the interface to configure and use the SPI\r
+ * peripheral.\r
+ *\r
+ * The Serial Peripheral Interface (SPI) circuit is a synchronous serial\r
+ * data link that provides communication with external devices in Master\r
+ * or Slave Mode.\r
+ *\r
+ * \section Usage\r
+ * To use the SPI, the user has to follow these few steps:\r
+ * -# Enable the SPI pins required by the application (see pio.h).\r
+ * -# Configure the SPI using the \ref spi_configure(). This enables the\r
+ * peripheral clock. The mode register is loaded with the given value.\r
+ * -# Configure all the necessary chip selects with \ref spi_configure_npcs().\r
+ * -# Enable the SPI by calling \ref spi_enable().\r
+ * -# Send/receive data using \ref spi_write() and \ref\r
+ * spi_read(). Note that \ref spi_read()\r
+ * must be called after \ref spi_write() to retrieve the last value read.\r
+ * -# Disable the SPI by calling \ref spi_disable().\r
+ *\r
+ * For more accurate information, please look at the SPI section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref spi.c\n\r
+ * \ref spi.h\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Serial Peripheral Interface (SPI) controller.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include "peripherals/spi.h"\r
+#include "peripherals/pmc.h"\r
+\r
+#include "io.h"\r
+#include "trace.h"\r
+\r
+#include <stdint.h>\r
+\r
+#include <assert.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+* Macros\r
+*----------------------------------------------------------------------------*/\r
+\r
+#define SPI_PCS(npcs) SPI_MR_PCS((~(1 << npcs) & 0xF))\r
+\r
+/*----------------------------------------------------------------------------\r
+ * local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static inline uint32_t _spi_compute_scbr(uint32_t bitrate, uint32_t periph_id)\r
+{\r
+ assert(bitrate>0);\r
+ return SPI_CSR_SCBR(\r
+ pmc_get_peripheral_clock(periph_id) / (bitrate*1000));\r
+}\r
+\r
+static inline uint32_t _spi_compute_dlybs(uint32_t delay, uint32_t periph_id)\r
+{\r
+ uint32_t dlybs =\r
+ ((pmc_get_peripheral_clock(periph_id)/1000000u) * delay) / 100;\r
+ return SPI_CSR_DLYBS(dlybs);\r
+}\r
+\r
+static inline uint32_t _spi_compute_dlybct(uint32_t delay, uint32_t periph_id)\r
+{\r
+ uint32_t dlybct =\r
+ ((pmc_get_peripheral_clock(periph_id)/31250u) * delay) / 100;\r
+ return SPI_CSR_DLYBCT(dlybct);\r
+}\r
+\r
+static inline uint32_t _spi_is_master(Spi* spi)\r
+{\r
+ return (spi->SPI_MR & SPI_MR_MSTR);\r
+}\r
+\r
+static inline uint32_t _spi_is_variable_ps(Spi* spi)\r
+{\r
+ return (spi->SPI_MR & SPI_MR_PS);\r
+}\r
+\r
+static void _spi_write_dummy(Spi* spi)\r
+{\r
+ if (_spi_is_master(spi)) {\r
+ writehw(&spi->SPI_TDR, 0xFF);\r
+ }\r
+}\r
+\r
+static void _spi_consume_read(Spi* spi, uint32_t cs)\r
+{\r
+ if (_spi_is_master(spi)) {\r
+ while(!(spi->SPI_SR & SPI_SR_RDRF));\r
+ uint16_t value;\r
+ if ((spi->SPI_CSR[cs] & SPI_CSR_BITS_Msk) < SPI_CSR_BITS_9_BIT) {\r
+ readb(&spi->SPI_RDR, (uint8_t*)&value);\r
+ } else {\r
+ readhw(&spi->SPI_RDR, &value);\r
+ }\r
+ (void)value;\r
+ }\r
+}\r
+\r
+#ifdef CONFIG_HAVE_SPI_FIFO\r
+\r
+static void _spi_fifo_clear(Spi* spi, uint32_t fifos)\r
+{\r
+ trace_debug("Spi: Clearing FIFOs\r\n");\r
+ while (!(spi->SPI_SR & SPI_SR_TXFEF));\r
+ spi->SPI_CR = fifos & (SPI_CR_RXFCLR | SPI_CR_TXFCLR);\r
+}\r
+\r
+static inline void _clear_fifo_control_flags(uint32_t* control_reg)\r
+{\r
+ *control_reg |= SPI_CR_TXFCLR | SPI_CR_RXFCLR | SPI_CR_FIFODIS;\r
+}\r
+#else\r
+#define _clear_fifo_control_flags(dummy) do {} while(0)\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void spi_enable(Spi * spi)\r
+{\r
+ spi->SPI_CR = SPI_CR_SPIEN;\r
+}\r
+\r
+void spi_disable(Spi * spi)\r
+{\r
+ spi->SPI_CR = SPI_CR_SPIDIS;\r
+}\r
+\r
+void spi_enable_it(Spi * spi, uint32_t dwSources)\r
+{\r
+ spi->SPI_IER = dwSources;\r
+}\r
+\r
+void spi_disable_it(Spi * spi, uint32_t dwSources)\r
+{\r
+ spi->SPI_IDR = dwSources;\r
+}\r
+\r
+void spi_configure(Spi * spi, uint32_t configuration)\r
+{\r
+ /* Execute a software reset of the SPI twice */\r
+ spi->SPI_CR = SPI_CR_SWRST;\r
+ spi->SPI_CR = SPI_CR_SWRST;\r
+\r
+ uint32_t control_reg = SPI_CR_SPIDIS;\r
+ /* Add clear FIFO flags if present */\r
+ _clear_fifo_control_flags(&control_reg);\r
+ /* Apply */\r
+ spi->SPI_CR = control_reg;\r
+\r
+ spi->SPI_MR = configuration;\r
+}\r
+\r
+void spi_chip_select(Spi * spi, uint8_t cS)\r
+{\r
+ spi->SPI_MR &= ~SPI_MR_PCS_Msk;\r
+ spi->SPI_MR |= SPI_PCS(cS);\r
+}\r
+\r
+void spi_set_mode(Spi * spi, uint32_t dwConfiguration)\r
+{\r
+ spi->SPI_MR = dwConfiguration;\r
+}\r
+\r
+void spi_release_cs(Spi * spi)\r
+{\r
+ spi->SPI_CR = SPI_CR_LASTXFER;\r
+}\r
+\r
+void spi_configure_cs(Spi * spi, uint32_t cs, uint32_t bitrate,\r
+ uint32_t delay_dlybs, uint32_t delay_dlybct,\r
+ uint32_t spi_mode, uint32_t release_on_last)\r
+{\r
+ trace_debug("Spi: configuring chip select %u\r\n", (unsigned int)cs);\r
+ uint32_t id = get_spi_id_from_addr(spi);\r
+ assert(id < ID_PERIPH_COUNT);\r
+\r
+ bitrate = _spi_compute_scbr(bitrate, id);\r
+ delay_dlybs = _spi_compute_dlybs(delay_dlybs, id);\r
+ delay_dlybct = _spi_compute_dlybct(delay_dlybct, id);\r
+ release_on_last = release_on_last ? SPI_CSR_CSAAT : 0;\r
+\r
+ spi->SPI_CSR[cs] = bitrate | delay_dlybs | delay_dlybct\r
+ | release_on_last | spi_mode;\r
+}\r
+\r
+void spi_configure_cs_mode(Spi * spi, uint32_t cs, uint32_t release_on_last)\r
+{\r
+ if (!release_on_last) {\r
+ spi->SPI_CSR[cs] |= SPI_CSR_CSAAT;\r
+ } else {\r
+ spi->SPI_CSR[cs] &= ~SPI_CSR_CSAAT;\r
+ }\r
+}\r
+\r
+uint32_t spi_get_status(Spi * spi)\r
+{\r
+ return spi->SPI_SR;\r
+}\r
+\r
+uint16_t spi_read(Spi * spi, uint8_t cs)\r
+{\r
+ _spi_write_dummy(spi);\r
+ while ((spi->SPI_SR & SPI_SR_RDRF) == 0) ;\r
+ uint16_t value;\r
+ if ((spi->SPI_CSR[cs] & SPI_CSR_BITS_Msk) < SPI_CSR_BITS_9_BIT) {\r
+ readb(&spi->SPI_RDR, (uint8_t*)&value);\r
+ } else {\r
+ readhw(&spi->SPI_RDR, &value);\r
+ }\r
+ return value;\r
+}\r
+\r
+/**\r
+ * \details If the SPI is configured to use a fixed peripheral select,\r
+ * the npcs value is meaningless. Otherwise, it identifies the\r
+ * component which shall be addressed.\r
+ */\r
+void spi_write(Spi * spi, uint32_t cs, uint16_t data)\r
+{\r
+ /* Send data */\r
+ while ((spi->SPI_SR & SPI_SR_TXEMPTY) == 0);\r
+ if (_spi_is_variable_ps(spi)) {\r
+ spi->SPI_TDR = data | SPI_PCS(cs);\r
+ } else {\r
+ writehw(&spi->SPI_TDR, data);\r
+ }\r
+ /* Consume write */\r
+ _spi_consume_read(spi, cs);\r
+}\r
+\r
+/**\r
+ * \brief Sends last data through a SPI peripheral.\r
+ *\r
+ * \details If the SPI is configured to use a fixed peripheral select,\r
+ * the npcs value is meaningless. Otherwise, it identifies the\r
+ * component which shall be addressed.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param dwNpcs Chip select of the component to address (0, 1, 2 or 3).\r
+ * \param wData Word of data to send.\r
+ */\r
+void spi_write_last(Spi * spi, uint32_t cs, uint16_t data)\r
+{\r
+ /* Send data */\r
+ while ((spi->SPI_SR & SPI_SR_TXEMPTY) == 0) ;\r
+ spi->SPI_TDR = data | SPI_PCS(cs) | SPI_TDR_LASTXFER;\r
+ /* Consume write to not corrupt FIFO if present (dummy\r
+ * function if CONFIG_HAV_SPI_FIFO not defined) */\r
+ _spi_consume_read(spi, cs);\r
+}\r
+\r
+uint32_t spi_is_finished(Spi * spi)\r
+{\r
+ return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0);\r
+}\r
+\r
+#ifdef CONFIG_HAVE_SPI_FIFO\r
+\r
+static void _spi_fifo_set_rx_threshold(Spi* spi, uint8_t rx_thres)\r
+{\r
+ spi->SPI_FMR &= ~SPI_FMR_RXFTHRES_Msk;\r
+ spi->SPI_FMR |= SPI_FMR_RXFTHRES(rx_thres);\r
+}\r
+\r
+static uint32_t _spi_write_stream(Spi *spi, uint32_t chip_select,\r
+ const void *stream, uint32_t len)\r
+{\r
+ const uint8_t* buffer = stream;\r
+ uint32_t left = len;\r
+\r
+ uint8_t is_ps = _spi_is_variable_ps(spi);\r
+ uint32_t max_size = is_ps ? sizeof(uint8_t) : sizeof(uint16_t);\r
+ int32_t fifo_size = get_peripheral_fifo_depth(spi);\r
+ if (fifo_size < 0)\r
+ return 0;\r
+\r
+ while (left > 0) {\r
+ if ((spi->SPI_SR & SPI_SR_TDRE) == 0) continue;\r
+\r
+ /* Get FIFO free size (int octet) and clamp it */\r
+ uint32_t buf_size = fifo_size - spi_fifo_tx_size(spi);\r
+ buf_size = (buf_size > left) ? left : buf_size;\r
+\r
+ /* Fill the FIFO as must as possible */\r
+ while (buf_size >= max_size) {\r
+ if (is_ps) {\r
+ spi->SPI_TDR = *(uint8_t*)buffer |\r
+ SPI_PCS(chip_select);\r
+ } else {\r
+ spi->SPI_TDR = *buffer |\r
+ (*(buffer+1) << 16);\r
+ }\r
+ buffer += max_size;\r
+ left -= max_size;\r
+ buf_size -= max_size;\r
+ }\r
+ if (buf_size >= sizeof(uint8_t)) {\r
+ writehw(&spi->SPI_TDR, *(uint8_t*)buffer);\r
+ buffer += sizeof(uint8_t);\r
+ left -= sizeof(uint8_t);\r
+ }\r
+ }\r
+ trace_debug("Spi (fifo): %u data writen\r\n",\r
+ (unsigned int)(len-left));\r
+ return len - left;\r
+}\r
+\r
+void spi_fifo_configure(Spi* spi, uint8_t tx_thres,\r
+ uint8_t rx_thres,\r
+ uint32_t ready_modes)\r
+{\r
+ /* Disable SPI and activate FIFO */\r
+ spi->SPI_CR = SPI_CR_SPIDIS | SPI_CR_FIFOEN;\r
+\r
+ /* Configure FIFO */\r
+ spi->SPI_FMR = SPI_FMR_TXFTHRES(tx_thres) | SPI_FMR_RXFTHRES(rx_thres)\r
+ | ready_modes;\r
+\r
+ /* Reenable SPI */\r
+ spi->SPI_CR = SPI_CR_SPIEN;\r
+}\r
+\r
+void spi_fifo_disable(Spi* spi)\r
+{\r
+ uint32_t reg = 0;\r
+ _clear_fifo_control_flags(®);\r
+ spi->SPI_CR = reg;\r
+}\r
+\r
+uint32_t spi_fifo_rx_size(Spi *spi)\r
+{\r
+ return (spi->SPI_FLR & SPI_FLR_RXFL_Msk) >> SPI_FLR_RXFL_Pos;\r
+}\r
+\r
+uint32_t spi_fifo_tx_size(Spi *spi)\r
+{\r
+ return (spi->SPI_FLR & SPI_FLR_TXFL_Msk) >> SPI_FLR_TXFL_Pos;\r
+}\r
+\r
+uint32_t spi_read_stream(Spi *spi, uint32_t chip_select,\r
+ void *stream, uint32_t len)\r
+{\r
+ uint8_t* buffer = stream;\r
+ uint32_t left = len;\r
+\r
+ uint8_t is_master = _spi_is_master(spi);\r
+ uint32_t max_size = is_master ? sizeof(uint8_t) : sizeof(uint32_t);\r
+\r
+ while (left > 0) {\r
+ uint32_t lenwrite = (left > SPI_FIFO_DEPTH) ?\r
+ SPI_FIFO_DEPTH : left;\r
+\r
+ _spi_fifo_set_rx_threshold(spi, lenwrite);\r
+ _spi_write_stream(spi, chip_select,\r
+ stream, lenwrite);\r
+\r
+ while (!(spi->SPI_SR & SPI_SR_RXFTHF));\r
+\r
+ /* Get FIFO size (in octets) and clamp it */\r
+ uint32_t buf_size = spi_fifo_rx_size(spi);\r
+ buf_size = buf_size > left ? left : buf_size;\r
+\r
+ /* Fill the buffer as must as possible with four data reads */\r
+ while (buf_size >= max_size) {\r
+ if (is_master) {\r
+ readb(&spi->SPI_RDR, (uint8_t*)buffer);\r
+ } else {\r
+ *(uint32_t*)buffer = spi->SPI_RDR;\r
+ }\r
+ buffer += max_size;\r
+ left -= max_size;\r
+ buf_size -= max_size;\r
+ }\r
+ /* Add tail data if stream is not 4 octet aligned */\r
+ if (buf_size >= sizeof(uint16_t)) {\r
+ /* two data read */\r
+ readhw(&spi->SPI_RDR, (uint16_t*)buffer);\r
+ left -= sizeof(uint16_t);\r
+ buffer += sizeof(uint16_t);\r
+ buf_size -= sizeof(uint16_t);\r
+ }\r
+ if (buf_size >= sizeof(uint8_t)) {\r
+ /* two data read */\r
+ readb(&spi->SPI_RDR, (uint8_t*)buffer);\r
+ left -= sizeof(uint8_t);\r
+ buffer += sizeof(uint8_t);\r
+ }\r
+ }\r
+ trace_debug("Spi (fifo): %u data read\r\n",\r
+ (unsigned int)(len-left));\r
+ return len - left;\r
+}\r
+\r
+uint32_t spi_write_stream(Spi *spi, uint32_t chip_select,\r
+ const void *stream, uint32_t len)\r
+{\r
+ uint32_t consumed = _spi_write_stream(spi, chip_select, stream, len);\r
+ _spi_fifo_clear(spi, SPI_CR_RXFCLR);\r
+ return consumed;\r
+}\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for Serial Peripheral Interface (SPI) controller.\r
+ *\r
+ */\r
+\r
+#ifndef _SPI_\r
+#define _SPI_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define SPI_KEEP_CS_OW (0)\r
+#define SPI_RELEASE_CS_OW (1)\r
+\r
+/*------------------------------------------------------------------------------ */\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Enables a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ */\r
+extern void spi_enable(Spi * spi);\r
+\r
+/**\r
+ * \brief Disables a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ */\r
+extern void spi_disable(Spi * spi);\r
+\r
+/**\r
+ * \brief Enables one or more interrupt sources of a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param dwSources Bitwise OR of selected interrupt sources.\r
+ */\r
+extern void spi_enable_it(Spi * spi, uint32_t dwSources);\r
+\r
+/**\r
+ * \brief Disables one or more interrupt sources of a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param dwSources Bitwise OR of selected interrupt sources.\r
+ */\r
+extern void spi_disable_it(Spi * spi, uint32_t dwSources);\r
+\r
+/**\r
+ * \brief Configures a SPI peripheral as specified. The configuration\r
+ * can be computed\r
+ * using several macros (see \ref spi_configuration_macros).\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param dwConfiguration Value of the SPI configuration register.\r
+ */\r
+extern void spi_configure(Spi * spi, uint32_t configuration);\r
+\r
+/**\r
+ * \brief Configures SPI Mode Register.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param dwConfiguration Value of the SPI mode register.\r
+ */\r
+extern void spi_set_mode(Spi * spi, uint32_t dwConfiguration);\r
+\r
+/**\r
+ * \brief Configures SPI chip select.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param cS Chip select of NPSCx.\r
+ */\r
+extern void spi_chip_select(Spi * spi, uint8_t cS);\r
+\r
+/**\r
+ * \brief Configures SPI to release last used CS line.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ */\r
+extern void spi_release_cs(Spi * spi);\r
+\r
+/**\r
+ * \brief Configures a chip select of a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param cs Chip select to configure (0, 1, 2 or 3).\r
+ * \param bitrate\r
+ * \param delay_dlybs\r
+ * \param delay_dlybct\r
+ * \param spi_mode\r
+ * \param release_on_last\r
+ */\r
+extern void spi_configure_cs(Spi * spi, uint32_t cs,uint32_t bitrate,\r
+ uint32_t delay_dlybs, uint32_t delay_dlybct,\r
+ uint32_t spi_mode, uint32_t release_on_last);\r
+\r
+/**\r
+ * \brief Configures a chip select active mode of a SPI peripheral.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param cs Chip select to configure (0, 1, 2 or 3).\r
+ * \param release_on_last CS controlled by last transfer.\r
+ * spi_release_cs() is used to deactive CS.\r
+ */\r
+extern void spi_configure_cs_mode(Spi * spi, uint32_t cs,\r
+ uint32_t release_on_last);\r
+\r
+/**\r
+ * \brief Reads one data from SPI peripheral with a dummy write.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ *\r
+ * \return readed data.\r
+ */\r
+\r
+extern uint16_t spi_read(Spi * spi, uint8_t cs);\r
+\r
+/**\r
+ * \brief Sends data through a SPI peripheral consuming reads.\r
+ *\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ * \param cs Chip select of the component to address (0, 1, 2 or 3).\r
+ * \param data Word of data to send.\r
+ */\r
+extern void spi_write(Spi * spi, uint32_t cs, uint16_t data);\r
+extern void spi_write_last(Spi * spi, uint32_t cs, uint16_t data);\r
+\r
+/**\r
+ * \brief Get the current status register of the given SPI peripheral.\r
+ *\r
+ * \note This resets the internal value of the status register, so further\r
+ * read may yield different values.\r
+ *\r
+ * \param spi Pointer to a Spi instance.\r
+ * \return SPI status register.\r
+ */\r
+extern uint32_t spi_get_status(Spi * spi);\r
+\r
+\r
+/**\r
+ * \brief Check if SPI transfer finish.\r
+ *\r
+ * \param spi Pointer to an Spi instance.\r
+ *\r
+ * \return Returns 1 if there is no pending write operation on the SPI;\r
+ * otherwise returns 0.\r
+ */\r
+\r
+extern uint32_t spi_is_finished(Spi * spi);\r
+\r
+#ifdef CONFIG_HAVE_SPI_FIFO\r
+extern void spi_fifo_configure(Spi* spi, uint8_t tx_thres,\r
+ uint8_t rx_thres,\r
+ uint32_t ready_modes);\r
+extern void spi_fifo_disable(Spi* spi);\r
+\r
+extern uint32_t spi_fifo_rx_size(Spi *spi);\r
+extern uint32_t spi_fifo_tx_size(Spi *spi);\r
+\r
+extern uint32_t spi_read_stream(Spi *spi, uint32_t chip_select,\r
+ void *stream, uint32_t len);\r
+extern uint32_t spi_write_stream(Spi *spi, uint32_t chip_select,\r
+ const void *stream, uint32_t len);\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* #ifndef _SPI_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+#include "peripherals/aic.h"\r
+#ifdef CONFIG_HAVE_FLEXCOM\r
+#include "peripherals/flexcom.h"\r
+#endif\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/spid.h"\r
+#include "peripherals/spi.h"\r
+#include "peripherals/xdmac.h"\r
+#include "peripherals/xdmad.h"\r
+#include "peripherals/l2cc.h"\r
+\r
+#include "cortex-a/cp15.h"\r
+\r
+#include "trace.h"\r
+\r
+#include <stddef.h>\r
+#include <stdint.h>\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+#define SPID_ATTRIBUTE_MASK (SPI_MR_PS | SPI_MR_MODFDIS | SPI_MR_MSTR | SPI_MR_WDRBT)\r
+#define SPID_DMA_THRESHOLD 16\r
+\r
+static uint32_t _garbage = 0;\r
+\r
+static void _spid_xdmad_callback_wrapper(struct _xdmad_channel *channel,\r
+ void *arg)\r
+{\r
+ trace_debug("SPID DMA Transfert Finished\r\n");\r
+ struct _spi_desc* spid = (struct _spi_desc*) arg;\r
+\r
+ xdmad_free_channel(channel);\r
+\r
+ if (spid->region_start && spid->region_end) {\r
+ l2cc_invalidate_region(spid->region_start, spid->region_end);\r
+ }\r
+\r
+ if (spid && spid->callback)\r
+ spid->callback(spid, spid->cb_args);\r
+}\r
+\r
+static void _spid_xdmad_cleanup_callback(struct _xdmad_channel *channel,\r
+ void *arg)\r
+{\r
+ xdmad_free_channel(channel);\r
+}\r
+\r
+#ifdef CONFIG_HAVE_SPI_FIFO\r
+static void spid_fifo_error(void)\r
+{\r
+ trace_error("Fifo pointer error encountered !!\r\n");\r
+}\r
+#endif\r
+\r
+void spid_configure(struct _spi_desc* desc)\r
+{\r
+ uint32_t id = get_spi_id_from_addr(desc->addr);\r
+\r
+#ifdef CONFIG_HAVE_FLEXCOM\r
+ Flexcom* flexcom = get_flexcom_addr_from_id(id);\r
+ if (flexcom) {\r
+ flexcom_select(flexcom, FLEX_MR_OPMODE_SPI);\r
+ }\r
+#endif\r
+ /* Enable SPI early otherwise FIFO configuration won't be applied */\r
+ pmc_enable_peripheral(id);\r
+ if (desc->transfert_mode == SPID_MODE_FIFO) {\r
+ desc->attributes &= ~SPI_MR_WDRBT;\r
+ }\r
+ spi_configure(desc->addr, (desc->attributes & SPID_ATTRIBUTE_MASK) | SPI_MR_MSTR);\r
+ spi_chip_select(desc->addr, desc->chip_select);\r
+ spi_configure_cs(desc->addr, desc->chip_select, desc->bitrate,\r
+ desc->dlybs, desc->dlybct, desc->spi_mode, 0);\r
+#ifdef CONFIG_HAVE_SPI_FIFO\r
+ if (desc->transfert_mode == SPID_MODE_FIFO) {\r
+ spi_fifo_configure(desc->addr, SPI_FIFO_DEPTH, SPI_FIFO_DEPTH,\r
+ SPI_FMR_TXRDYM_ONE_DATA | SPI_FMR_RXRDYM_ONE_DATA);\r
+ spi_enable_it(desc->addr, SPI_IER_TXFPTEF | SPI_IER_RXFPTEF);\r
+ aic_set_source_vector(id, spid_fifo_error);\r
+ aic_enable(id);\r
+ }\r
+#endif\r
+ (void)spi_get_status(desc->addr);\r
+\r
+ spi_enable(desc->addr);\r
+}\r
+\r
+void spid_begin_transfert(struct _spi_desc* desc)\r
+{\r
+ spi_chip_select(desc->addr, desc->chip_select);\r
+ spi_configure_cs_mode(desc->addr, desc->chip_select, SPI_KEEP_CS_OW);\r
+}\r
+\r
+static void _spid_init_dma_write_channel(const struct _spi_desc* desc,\r
+ struct _xdmad_channel** channel,\r
+ struct _xdmad_cfg* cfg)\r
+{\r
+ assert(cfg);\r
+ assert(channel);\r
+\r
+ uint32_t id = get_spi_id_from_addr(desc->addr);\r
+\r
+ memset(cfg, 0x0, sizeof(*cfg));\r
+\r
+ *channel =\r
+ xdmad_allocate_channel(XDMAD_PERIPH_MEMORY, id);\r
+ assert(*channel);\r
+\r
+ xdmad_prepare_channel(*channel);\r
+ cfg->cfg.uint32_value = XDMAC_CC_TYPE_PER_TRAN\r
+ | XDMAC_CC_DSYNC_MEM2PER\r
+ | XDMAC_CC_MEMSET_NORMAL_MODE\r
+ | XDMAC_CC_CSIZE_CHK_1\r
+ | XDMAC_CC_DWIDTH_BYTE\r
+ | XDMAC_CC_DIF_AHB_IF1\r
+ | XDMAC_CC_SIF_AHB_IF0\r
+ | XDMAC_CC_DAM_FIXED_AM;\r
+\r
+ cfg->dest_addr = (void*)&desc->addr->SPI_TDR;\r
+}\r
+\r
+static void _spid_init_dma_read_channel(const struct _spi_desc* desc,\r
+ struct _xdmad_channel** channel,\r
+ struct _xdmad_cfg* cfg)\r
+{\r
+ assert(cfg);\r
+ assert(channel);\r
+\r
+ uint32_t id = get_spi_id_from_addr(desc->addr);\r
+\r
+ memset(cfg, 0x0, sizeof(*cfg));\r
+\r
+ *channel =\r
+ xdmad_allocate_channel(id, XDMAD_PERIPH_MEMORY);\r
+ assert(*channel);\r
+\r
+ xdmad_prepare_channel(*channel);\r
+ cfg->cfg.uint32_value = XDMAC_CC_TYPE_PER_TRAN\r
+ | XDMAC_CC_DSYNC_PER2MEM\r
+ | XDMAC_CC_MEMSET_NORMAL_MODE\r
+ | XDMAC_CC_CSIZE_CHK_1\r
+ | XDMAC_CC_DWIDTH_BYTE\r
+ | XDMAC_CC_DIF_AHB_IF0\r
+ | XDMAC_CC_SIF_AHB_IF1\r
+ | XDMAC_CC_SAM_FIXED_AM;\r
+\r
+ cfg->src_addr = (void*)&desc->addr->SPI_RDR;\r
+}\r
+\r
+static void _spid_dma_write(const struct _spi_desc* desc,\r
+ const struct _buffer* buffer)\r
+{\r
+ struct _xdmad_channel* w_channel = NULL;\r
+ struct _xdmad_channel* r_channel = NULL;\r
+ struct _xdmad_cfg w_cfg;\r
+ struct _xdmad_cfg r_cfg;\r
+\r
+ _spid_init_dma_write_channel(desc, &w_channel, &w_cfg);\r
+ _spid_init_dma_read_channel(desc, &r_channel, &r_cfg);\r
+\r
+ w_cfg.cfg.bitfield.sam = XDMAC_CC_SAM_INCREMENTED_AM\r
+ >> XDMAC_CC_SAM_Pos;\r
+ w_cfg.src_addr = buffer->data;\r
+ w_cfg.ublock_size = buffer->size;\r
+ xdmad_configure_transfer(w_channel, &w_cfg, 0, 0);\r
+ xdmad_set_callback(w_channel, _spid_xdmad_cleanup_callback,\r
+ NULL);\r
+\r
+ r_cfg.cfg.bitfield.dam = XDMAC_CC_DAM_FIXED_AM\r
+ >> XDMAC_CC_DAM_Pos;\r
+ r_cfg.dest_addr = &_garbage;\r
+ r_cfg.ublock_size = buffer->size;\r
+ xdmad_configure_transfer(r_channel, &r_cfg, 0, 0);\r
+ xdmad_set_callback(r_channel, _spid_xdmad_callback_wrapper,\r
+ (void*)desc);\r
+\r
+ l2cc_clean_region(desc->region_start, desc->region_end);\r
+\r
+ xdmad_start_transfer(w_channel);\r
+ xdmad_start_transfer(r_channel);\r
+}\r
+\r
+static void _spid_dma_read(const struct _spi_desc* desc,\r
+ struct _buffer* buffer)\r
+{\r
+ struct _xdmad_channel* w_channel = NULL;\r
+ struct _xdmad_channel* r_channel = NULL;\r
+ struct _xdmad_cfg w_cfg;\r
+ struct _xdmad_cfg r_cfg;\r
+\r
+ _spid_init_dma_write_channel(desc, &w_channel, &w_cfg);\r
+ _spid_init_dma_read_channel(desc, &r_channel, &r_cfg);\r
+\r
+ w_cfg.cfg.bitfield.sam = XDMAC_CC_SAM_FIXED_AM\r
+ >> XDMAC_CC_SAM_Pos;\r
+ w_cfg.src_addr = buffer->data;\r
+ w_cfg.ublock_size = buffer->size;\r
+ w_cfg.block_size = 0;\r
+ xdmad_configure_transfer(w_channel, &w_cfg, 0, 0);\r
+ xdmad_set_callback(w_channel, _spid_xdmad_cleanup_callback, NULL);\r
+\r
+ r_cfg.cfg.bitfield.dam = XDMAC_CC_DAM_INCREMENTED_AM\r
+ >> XDMAC_CC_DAM_Pos;\r
+ r_cfg.dest_addr = buffer->data;\r
+ r_cfg.ublock_size = buffer->size;\r
+ xdmad_configure_transfer(r_channel, &r_cfg, 0, 0);\r
+ xdmad_set_callback(r_channel, _spid_xdmad_callback_wrapper,\r
+ (void*)desc);\r
+\r
+ l2cc_clean_region(desc->region_start, desc->region_end);\r
+\r
+ xdmad_start_transfer(w_channel);\r
+ xdmad_start_transfer(r_channel);\r
+}\r
+\r
+uint32_t spid_transfert(struct _spi_desc* desc, struct _buffer* rx,\r
+ struct _buffer* tx, spid_callback_t cb,\r
+ void* user_args)\r
+{\r
+ Spi* spi = desc->addr;\r
+ uint32_t i = 0;\r
+\r
+ desc->callback = cb;\r
+ desc->cb_args = user_args;\r
+\r
+ if (mutex_try_lock(&desc->mutex)) {\r
+ return SPID_ERROR_LOCK;\r
+ }\r
+\r
+ switch (desc->transfert_mode) {\r
+ case SPID_MODE_POLLING:\r
+ if (tx) {\r
+ for (i = 0; i < tx->size; ++i) {\r
+ spi_write(spi, desc->chip_select, tx->data[i]);\r
+ }\r
+ }\r
+ if (rx) {\r
+ for (i = 0; i < rx->size; ++i) {\r
+ rx->data[i] = spi_read(spi, desc->chip_select);\r
+ }\r
+ }\r
+ mutex_free(&desc->mutex);\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ break;\r
+ case SPID_MODE_DMA:\r
+ if (tx) {\r
+ if (tx->size < SPID_DMA_THRESHOLD) {\r
+ for (i = 0; i < tx->size; ++i) {\r
+ spi_write(spi, desc->chip_select, tx->data[i]);\r
+ }\r
+ if (!rx) {\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ mutex_free(&desc->mutex);\r
+ }\r
+ } else {\r
+ desc->region_start = (uint32_t)tx->data;\r
+ desc->region_end = desc->region_start\r
+ + tx->size;\r
+ _spid_dma_write(desc, tx);\r
+ if (rx) {\r
+ spid_wait_transfert(desc);\r
+ mutex_lock(&desc->mutex);\r
+ }\r
+ }\r
+ }\r
+ if (rx) {\r
+ if (rx->size < SPID_DMA_THRESHOLD) {\r
+ for (i = 0; i < rx->size; ++i) {\r
+ rx->data[i] = spi_read(spi, desc->chip_select);\r
+ }\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ mutex_free(&desc->mutex);\r
+ } else {\r
+ desc->region_start = (uint32_t)rx->data;\r
+ desc->region_end = desc->region_start\r
+ + rx->size;\r
+ _spid_dma_read(desc, rx);\r
+ }\r
+ }\r
+ break;\r
+#ifdef CONFIG_HAVE_SPI_FIFO\r
+ case SPID_MODE_FIFO:\r
+ if (tx) {\r
+ spi_write_stream(spi, desc->chip_select,\r
+ tx->data, tx->size);\r
+ }\r
+ if (rx) {\r
+ spi_read_stream(spi, desc->chip_select,\r
+ rx->data, rx->size);\r
+ }\r
+ mutex_free(&desc->mutex);\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ break;\r
+#endif\r
+ default:\r
+ trace_debug("Unkown mode");\r
+ }\r
+\r
+ return SPID_SUCCESS;\r
+}\r
+\r
+void spid_finish_transfert_callback(struct _spi_desc* desc, void* user_args)\r
+{\r
+ (void)user_args;\r
+ spid_finish_transfert(desc);\r
+}\r
+\r
+void spid_finish_transfert(struct _spi_desc* desc)\r
+{\r
+ spi_release_cs(desc->addr);\r
+ mutex_free(&desc->mutex);\r
+}\r
+\r
+void spid_close(const struct _spi_desc* desc)\r
+{\r
+ uint32_t id = get_spi_id_from_addr(desc->addr);\r
+#ifdef CONFIG_HAVE_SPI_FIFO\r
+ spi_fifo_disable(desc->addr);\r
+ spi_disable_it(desc->addr, SPI_IER_TXFPTEF | SPI_IER_RXFPTEF);\r
+ aic_disable(id);\r
+#endif\r
+ spi_disable(desc->addr);\r
+ pmc_disable_peripheral(id);\r
+}\r
+\r
+uint32_t spid_is_busy(const struct _spi_desc* desc)\r
+{\r
+ return mutex_is_locked(&desc->mutex);\r
+}\r
+\r
+void spid_wait_transfert(const struct _spi_desc* desc)\r
+{\r
+ while (mutex_is_locked(&desc->mutex));\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+#ifndef SPID_HEADER__\r
+#define SPID_HEADER__\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Header\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+#include "mutex.h"\r
+#include "io.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define SPID_SUCCESS (0)\r
+#define SPID_INVALID_ID (1)\r
+#define SPID_INVALID_BITRATE (2)\r
+#define SPID_ERROR_LOCK (3)\r
+\r
+#define SPID_NO_CALLBACK ((spid_callback_t)0)\r
+\r
+struct _spi_desc;\r
+\r
+typedef void (*spid_callback_t)(struct _spi_desc* spid, void* args);\r
+\r
+enum _spid_trans_mode\r
+{\r
+ SPID_MODE_POLLING,\r
+ SPID_MODE_FIFO,\r
+ SPID_MODE_DMA\r
+};\r
+\r
+struct _spi_desc\r
+{\r
+ Spi* addr;\r
+ uint32_t bitrate;\r
+ uint32_t attributes;\r
+ uint8_t dlybs;\r
+ uint8_t dlybct;\r
+ uint8_t chip_select;\r
+ uint8_t spi_mode;\r
+ uint8_t transfert_mode;\r
+ /* implicit internal padding is mandatory here */\r
+ spid_callback_t callback;\r
+ void* cb_args;\r
+ mutex_t mutex;\r
+ uint32_t region_start;\r
+ uint32_t region_end;\r
+};\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void spid_configure(struct _spi_desc* desc);\r
+\r
+extern void spid_begin_transfert(struct _spi_desc* desc);\r
+\r
+extern uint32_t spid_transfert(struct _spi_desc* desc, struct _buffer* rx,\r
+ struct _buffer* tx, spid_callback_t cb,\r
+ void* user_args);\r
+extern void spid_finish_transfert(struct _spi_desc* desc);\r
+extern void spid_finish_transfert_callback(struct _spi_desc* desc,\r
+ void* user_arg);\r
+extern void spid_close(const struct _spi_desc* desc);\r
+\r
+extern uint32_t spid_is_busy(const struct _spi_desc* desc);\r
+extern void spid_wait_transfert(const struct _spi_desc* desc);\r
+\r
+#endif /* SPID_HEADER__ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup tc_module\r
+ * \section Purpose\r
+ * The TC driver provides the Interface to configure the Timer Counter (TC).\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Optionally, use tc_find_mck_divisor() to let the program find the best\r
+ * TCCLKS field value automatically.</li>\r
+ * <li> Configure a Timer Counter in the desired mode using tc_configure().</li>\r
+ * <li> Start or stop the timer clock using tc_start() and tc_stop().</li>\r
+ * </li>\r
+ * </ul>\r
+ * For more accurate information, please look at the TC section of the Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref tc.c\n\r
+ * \ref tc.h.\n\r
+*/\r
+\r
+/**\r
+* \file\r
+*\r
+* \section Purpose\r
+*\r
+* Interface for configuring and using Timer Counter (TC) peripherals.\r
+*\r
+* \section Usage\r
+* -# Optionally, use tc_find_mck_divisor() to let the program find the best\r
+* TCCLKS field value automatically.\r
+* -# Configure a Timer Counter in the desired mode using tc_configure().\r
+* -# Start or stop the timer clock using tc_start() and tc_stop().\r
+*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Timer Counter (TC).\r
+ *\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/tc.h"\r
+#include "peripherals/pmc.h"\r
+\r
+#include <assert.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures a Timer Counter Channel\r
+ *\r
+ * Configures a Timer Counter to operate in the given mode. Timer is stopped\r
+ * after configuration and must be restarted with tc_start(). All the\r
+ * interrupts of the timer are also disabled.\r
+ *\r
+ * \param pTc Pointer to a Tc instance.\r
+ * \param channel Channel number.\r
+ * \param mode Operating mode (TC_CMR value).\r
+ */\r
+void tc_configure(Tc * pTc, uint32_t channel, uint32_t mode)\r
+{\r
+ volatile TcChannel *pTcCh;\r
+\r
+ assert(channel <\r
+ (sizeof (pTc->TC_CHANNEL) / sizeof (pTc->TC_CHANNEL[0])));\r
+ pTcCh = pTc->TC_CHANNEL + channel;\r
+\r
+ /* Disable TC clock */\r
+ pTcCh->TC_CCR = TC_CCR_CLKDIS;\r
+\r
+ /* Disable interrupts */\r
+ pTcCh->TC_IDR = 0xFFFFFFFF;\r
+\r
+ /* Clear status register */\r
+ pTcCh->TC_SR;\r
+\r
+ /* Set mode */\r
+ pTcCh->TC_CMR = mode;\r
+}\r
+\r
+/**\r
+ * \brief Reset and Start the TC Channel\r
+ *\r
+ * Enables the timer clock and performs a software reset to start the counting.\r
+ *\r
+ * \param pTc Pointer to a Tc instance.\r
+ * \param channel Channel number.\r
+ */\r
+void tc_start(Tc * pTc, uint32_t channel)\r
+{\r
+ volatile TcChannel *pTcCh;\r
+\r
+ assert(channel <\r
+ (sizeof (pTc->TC_CHANNEL) / sizeof (pTc->TC_CHANNEL[0])));\r
+\r
+ pTcCh = pTc->TC_CHANNEL + channel;\r
+ pTcCh->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;\r
+ pTcCh->TC_IER = TC_IER_COVFS;\r
+}\r
+\r
+/**\r
+ * \brief Stop TC Channel\r
+ *\r
+ * Disables the timer clock, stopping the counting.\r
+ *\r
+ * \param pTc Pointer to a Tc instance.\r
+ * \param channel Channel number.\r
+ */\r
+void tc_stop(Tc * pTc, uint32_t channel)\r
+{\r
+ volatile TcChannel *pTcCh;\r
+\r
+ assert(channel <\r
+ (sizeof (pTc->TC_CHANNEL) / sizeof (pTc->TC_CHANNEL[0])));\r
+\r
+ pTcCh = pTc->TC_CHANNEL + channel;\r
+ pTcCh->TC_CCR = TC_CCR_CLKDIS;\r
+ pTcCh->TC_IDR = TC_IER_COVFS;\r
+}\r
+\r
+/**\r
+ * \brief Enables TC channel interrupts\r
+ *\r
+ * \param tc Pointer to Tc instance\r
+ * \param channel Channel number\r
+ * \param mask mask of interrupts to enable\r
+ */\r
+void tc_enable_it(Tc* tc, uint32_t channel, uint32_t mask)\r
+{\r
+ assert(channel < (sizeof (tc->TC_CHANNEL) / sizeof (tc->TC_CHANNEL[0])));\r
+ tc->TC_CHANNEL[channel].TC_IER = mask;\r
+}\r
+\r
+/**\r
+ * \brief Find best MCK divisor\r
+ *\r
+ * Finds the best MCK divisor given the timer frequency and MCK. The result\r
+ * is guaranteed to satisfy the following equation:\r
+ * \code\r
+ * (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)\r
+ * \endcode\r
+ * with DIV being the highest possible value.\r
+ *\r
+ * \param freq Desired timer freq.\r
+ * \param div Divisor value.\r
+ * \param tc_clks TCCLKS field value for divisor.\r
+ *\r
+ * \return 1 if a proper divisor has been found, otherwise 0.\r
+ */\r
+uint32_t tc_find_mck_divisor (uint32_t freq, uint32_t * div,\r
+ uint32_t * tc_clks)\r
+{\r
+ const uint32_t periph_clock = pmc_get_peripheral_clock(ID_TC0);\r
+ const uint32_t available_freqs[5] = {periph_clock >> 1, periph_clock >> 3, periph_clock >> 5, periph_clock >> 7, 32768};\r
+\r
+ int i = 0;\r
+ for (i = 0; i < 5; ++i)\r
+ {\r
+ uint32_t tmp = freq << 1;\r
+ if (tmp > available_freqs[i])\r
+ break;\r
+ }\r
+\r
+ i = (i == 5 ? i-1 : i);\r
+\r
+ /* Store results */\r
+ if (div) {\r
+ *div = periph_clock / available_freqs[i];\r
+ }\r
+ if (tc_clks) {\r
+ *tc_clks = i;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+uint32_t tc_get_status(Tc* tc, uint32_t channel_num)\r
+{\r
+ return tc->TC_CHANNEL[channel_num].TC_SR;\r
+}\r
+\r
+\r
+void tc_trigger_on_freq(Tc* tc, uint32_t channel_num, uint32_t freq)\r
+{\r
+ uint32_t div = 0;\r
+ uint32_t tcclks = 0;\r
+ uint32_t tc_id = get_tc_id_from_addr(tc);\r
+ TcChannel* channel = &tc->TC_CHANNEL[channel_num];\r
+\r
+ tc_find_mck_divisor(freq, &div, &tcclks);\r
+ tc_configure(tc, channel_num, tcclks | TC_CMR_CPCTRG);\r
+ channel->TC_RC = (pmc_get_peripheral_clock(tc_id) / div) / freq;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Interface for configuring and using Timer Counter (TC) peripherals.\r
+ *\r
+ * \section Usage\r
+ * -# Optionally, use tc_find_mck_divisor() to let the program find the best\r
+ * TCCLKS field value automatically.\r
+ * -# Configure a Timer Counter in the desired mode using tc_configure().\r
+ * -# Start or stop the timer clock using tc_start() and tc_stop().\r
+ */\r
+\r
+#ifndef _TC_\r
+#define _TC_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+extern void tc_configure (Tc* pTc, uint32_t channel, uint32_t mode);\r
+extern void tc_start (Tc * pTc, uint32_t channel);\r
+extern void tc_stop (Tc * pTc, uint32_t channel);\r
+extern void tc_enable_it(Tc* tc, uint32_t channel, uint32_t mask);\r
+extern uint32_t tc_find_mck_divisor (uint32_t freq, uint32_t* div, uint32_t * tc_clks);\r
+extern uint32_t tc_get_status(Tc* tc, uint32_t channel_num);\r
+extern void tc_trigger_on_freq(Tc* tc, uint32_t channel_num, uint32_t freq);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* #ifndef _TC_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup tdes_module Working with TDES\r
+ * \ingroup peripherals_module\r
+ * The TDES driver provides the interface to configure and use the TDES\r
+ * peripheral.\r
+ * \n\r
+ *\r
+ * The Data Encryption Standard (DES) and the Triple Data Encryption Algorithm\r
+ * (TDES) specify FIPS-approved cryptographic algorithms that can be used to\r
+ * protect electronic data.\r
+ * The TDES bit in the TDES Mode Register (TDES_MR) is used to select either the\r
+ * single DES or the Triple DES mode (make use of the tdes_configure()\r
+ * function).\r
+ *\r
+ * The DES uses 64-bit cryptographic keys to encrypt and decrypt 64-bit data\r
+ * blocks. Input data can be fed calling tdes_set_input().\r
+ * The 64-bit key is defined in the Key 1 Word Registers (TDES_KEY1WRx) and set\r
+ * by tdes_write_key1().\r
+ *\r
+ * The Triple DES key consists in three DES keys, which set is also referred to\r
+ * as a key bundle. These three 64-bit keys are defined, respectively, in the\r
+ * Key 1, 2 and 3 Word Registers (TDES_KEY1WRx, TDES_KEY2WRx and TDES_KEY3WRx).\r
+ * In Triple DES mode (TDES_MR:TDESMOD set to 1), the TDES_MR:KEYMOD bit is used\r
+ * to select either the two- or three-key algorithm.\r
+ *\r
+ * In order to perform TDES encryption/decryption, the user has to follow these\r
+ * few steps:\r
+ * <ul>\r
+ * <li> A software-triggered hardware reset of the TDES interface is performed\r
+ * by tdes_soft_reset().</li>\r
+ * <li> Configure TDES algorithm mode, key mode, start mode and operation mode\r
+ * by means of tdes_configure().</li>\r
+ * <li> Set DES keys with function tdes_write_key1(), tdes_write_key2(), and\r
+ * tdes_write_key3().</li>\r
+ * <li> To start encrypting or decrypting call tdes_start().</li>\r
+ * <li> Retrieve the encryption or decryption result by means of\r
+ * tdes_get_output().</li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the TDES section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files:\n\r
+ * \ref tdes.c\n\r
+ * \ref tdes.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of the Triple Data Encryption Algorithm (TDES).\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/tdes.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void tdes_start(void)\r
+{\r
+ TDES->TDES_CR = TDES_CR_START;\r
+}\r
+\r
+void tdes_soft_reset(void)\r
+{\r
+ TDES->TDES_CR = TDES_CR_SWRST;\r
+}\r
+\r
+void tdes_configure(uint32_t mode)\r
+{\r
+ TDES->TDES_MR = mode;\r
+}\r
+\r
+void tdes_enable_it(uint32_t sources)\r
+{\r
+ TDES->TDES_IER = sources;\r
+}\r
+\r
+void tdes_disable_it(uint32_t sources)\r
+{\r
+ TDES->TDES_IDR = sources;\r
+}\r
+\r
+uint32_t tdes_get_status(void)\r
+{\r
+ return TDES->TDES_ISR;\r
+}\r
+\r
+void tdes_write_key1(uint32_t key_word0, uint32_t key_word1)\r
+{\r
+ TDES->TDES_KEY1WR[0] = key_word0;\r
+ TDES->TDES_KEY1WR[1] = key_word1;\r
+}\r
+\r
+void tdes_write_key2(uint32_t key_word0, uint32_t key_word1)\r
+{\r
+ TDES->TDES_KEY2WR[0] = key_word0;\r
+ TDES->TDES_KEY2WR[1] = key_word1;\r
+}\r
+\r
+void tdes_write_key3(uint32_t key_word0, uint32_t key_word1)\r
+{\r
+ TDES->TDES_KEY3WR[0] = key_word0;\r
+ TDES->TDES_KEY3WR[1] = key_word1;\r
+}\r
+\r
+void tdes_set_input(uint32_t data0, uint32_t data1)\r
+{\r
+ TDES->TDES_IDATAR[0] = data0;\r
+ TDES->TDES_IDATAR[1] = data1;\r
+}\r
+\r
+void tdes_get_output(uint32_t *data0, uint32_t *data1)\r
+{\r
+ *data0 = TDES->TDES_ODATAR[0];\r
+ *data1 = TDES->TDES_ODATAR[1];\r
+}\r
+\r
+void tdes_set_vector(uint32_t v0, uint32_t v1)\r
+{\r
+ TDES->TDES_IVR[0] = v0;\r
+ TDES->TDES_IVR[1] = v1;\r
+}\r
+\r
+void tdes_set_xtea_rounds(uint32_t rounds)\r
+{\r
+ TDES->TDES_XTEA_RNDR = TDES_XTEA_RNDR_XTEA_RNDS(rounds);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _TDES_\r
+#define _TDES_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define MODE_SINGLE_DES 0x00\r
+#define MODE_TRIPLE_DES 0x01\r
+#define MODE_XTEA 0x02\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Starts Manual encryption/decryption process.\r
+ */\r
+void tdes_start(void);\r
+\r
+/**\r
+ * \brief Resets the TDES.\r
+ * A software triggered hardware reset of the TDES interface is performed.\r
+ */\r
+void tdes_soft_reset(void);\r
+\r
+/**\r
+ * \brief Configures an TDES peripheral with the specified parameters.\r
+ * \param mode Desired value for the TDES_MR mode register (see the datasheet).\r
+ */\r
+void tdes_configure(uint32_t mode);\r
+\r
+/**\r
+ * \brief Enables the selected interrupts sources on a TDES peripheral.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void tdes_enable_it(uint32_t sources);\r
+\r
+/**\r
+ * \brief Disables the selected interrupts sources on a TDES peripheral.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void tdes_disable_it(uint32_t sources);\r
+\r
+/**\r
+ * \brief Get the current status register of the given TDES peripheral.\r
+ * \return TDES status register.\r
+ */\r
+extern uint32_t tdes_get_status(void);\r
+\r
+/**\r
+ * \brief Set KEY 1/2/3.\r
+ * \param key_word0 Key x, word 0\r
+ * \param key_word1 Key x, word 1\r
+ */\r
+void tdes_write_key1(uint32_t key_word0, uint32_t key_word1);\r
+void tdes_write_key2(uint32_t key_word0, uint32_t key_word1);\r
+void tdes_write_key3(uint32_t key_word0, uint32_t key_word1);\r
+\r
+/**\r
+ * \brief Set the two 32-bit input data registers. Allows to set the 64-bit data\r
+ * block used for encryption/decryption.\r
+ * \param data0 Corresponds to the first word of the data to be processed.\r
+ * \param data1 Corresponds to the last word of the data to be processed.\r
+ */\r
+void tdes_set_input(uint32_t data0, uint32_t data1);\r
+\r
+/**\r
+ * \brief Read from the two 32-bit data registers containing the 64-bit data\r
+ * block which has been encrypted/decrypted.\r
+ * \param data0 Points to the first word.\r
+ * \param data1 Points to the second word.\r
+ */\r
+void tdes_get_output(uint32_t *data0, uint32_t *data1);\r
+\r
+/**\r
+ * \brief Set the 64-bit initialization vector data block, which is used by\r
+ * specific modes of operation as an additional initial input.\r
+ * \param v0 Corresponds to the first word of the initialization vector.\r
+ * \param v1 Corresponds to the second word of the initialization vector.\r
+ */\r
+void tdes_set_vector(uint32_t v0, uint32_t v1);\r
+\r
+/**\r
+ * \brief Set the 6-bit complete rounds.\r
+ * \param rounds Corresponds to rounds+1 complete round.\r
+ */\r
+void tdes_set_xtea_rounds(uint32_t rounds);\r
+\r
+#endif /* #ifndef _TDES_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup rtng_module Working with RTNG\r
+ * \ingroup peripherals_module\r
+ * The TRNG driver provides the interface to configure and use the TRNG\r
+ * peripheral.\r
+ * \n\r
+ *\r
+ * The True Random Number Generator (TRNG) passes the American NIST Special\r
+ * Publication 800-22 and Diehard Random Tests Suites. As soon as the TRNG is\r
+ * enabled (trng_enable()), the generator provides one 32-bit value every 84\r
+ * clock cycles. TRNG Interrupt can be enabled through trng_enable_it()\r
+ * (respectively disabled with trng_disable_it()). When new random data is\r
+ * ready, the interrupt will fire and the configured callback will be called.\r
+ * Alternatively, the TRNG can also be used in polling mode using\r
+ * trng_get_random_data().\r
+ *\r
+ * For more accurate information, please look at the TRNG section of the\r
+ * datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref trng.c\n\r
+ * \ref trng.h\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of True Random Number Generator (TRNG)\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/aic.h"\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/trng.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local Data\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static trng_callback_t _trng_callback;\r
+static void* _trng_callback_arg;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+static void _trng_handler(void)\r
+{\r
+ if (TRNG->TRNG_ISR & TRNG_ISR_DATRDY) {\r
+ if (_trng_callback) {\r
+ _trng_callback(TRNG->TRNG_ODATA, _trng_callback_arg);\r
+ }\r
+ }\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+void trng_enable()\r
+{\r
+ pmc_enable_peripheral(ID_TRNG);\r
+ TRNG->TRNG_CR = TRNG_CR_ENABLE | TRNG_CR_KEY_PASSWD;\r
+}\r
+\r
+void trng_disable()\r
+{\r
+ TRNG->TRNG_CR = TRNG_CR_KEY_PASSWD;\r
+ pmc_disable_peripheral(ID_TRNG);\r
+}\r
+\r
+void trng_enable_it(trng_callback_t cb, void* user_arg)\r
+{\r
+ _trng_callback = cb;\r
+ _trng_callback_arg = user_arg;\r
+ aic_set_source_vector(ID_TRNG, _trng_handler);\r
+ aic_enable(ID_TRNG);\r
+ TRNG->TRNG_IER = TRNG_IER_DATRDY;\r
+}\r
+\r
+void trng_disable_it(void)\r
+{\r
+ TRNG->TRNG_IDR = TRNG_IDR_DATRDY;\r
+ aic_disable(ID_TRNG);\r
+ _trng_callback = NULL;\r
+ _trng_callback_arg = NULL;\r
+}\r
+\r
+uint32_t trng_get_random_data(void)\r
+{\r
+ while (!(TRNG->TRNG_ISR & TRNG_ISR_DATRDY));\r
+ return TRNG->TRNG_ODATA;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _TRNG_H_\r
+#define _TRNG_H_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+#include "chip.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Types\r
+ *------------------------------------------------------------------------------*/\r
+\r
+typedef void (*trng_callback_t)(uint32_t random_value, void* user_arg);\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Enables the TRNG.\r
+ */\r
+extern void trng_enable(void);\r
+\r
+/**\r
+ * \brief Disables the TRNG.\r
+ */\r
+extern void trng_disable(void);\r
+\r
+/**\r
+ * \brief Enable the TRNG interrupt, the callback will be called for each new\r
+ * generated random value.\r
+ *\r
+ * \param cb user callback\r
+ * \param user_arg user argument passed as-is to the callback\r
+ */\r
+extern void trng_enable_it(trng_callback_t cb, void* user_arg);\r
+\r
+/**\r
+ * \brief Disable the TRNG interrupt.\r
+ */\r
+extern void trng_disable_it(void);\r
+\r
+/**\r
+ * \brief Get the next random value generated by the TRNG. This function will\r
+ * block until a value is available.\r
+ * \return a random value\r
+ */\r
+extern uint32_t trng_get_random_data(void);\r
+\r
+#endif /* _TRNG_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup twi_module Working with TWI\r
+ * \section Purpose\r
+ * The TWI driver provides the interface to configure and use the TWI\r
+ * peripheral.\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Configures a TWI peripheral to operate in master mode, at the given\r
+ * frequency (in Hz) using twi_configure(). </li>\r
+ * <li> Sends a STOP condition on the TWI using twi_stop().</li>\r
+ * <li> Starts a read operation on the TWI bus with the specified slave using\r
+ * twi_start_read(). Data must then be read using twi_read_byte() whenever\r
+ * a byte is available (poll using twi_is_byte_received()).</li>\r
+ * <li> Starts a write operation on the TWI to access the selected slave using\r
+ * twi_start_write(). A byte of data must be provided to start the write;\r
+ * other bytes are written next.</li>\r
+ * <li> Sends a byte of data to one of the TWI slaves on the bus using twi_write_byte().\r
+ * This function must be called once before twi_start_write() with the first byte of data\r
+ * to send, then it shall be called repeatedly after that to send the remaining bytes.</li>\r
+ * <li> Check if a byte has been received and can be read on the given TWI\r
+ * peripheral using twi_is_byte_received().<\r
+ * Check if a byte has been sent using twi_byte_sent().</li>\r
+ * <li> Check if the current transmission is complete (the STOP has been sent)\r
+ * using twi_is_transfer_complete().</li>\r
+ * <li> Enables & disable the selected interrupts sources on a TWI peripheral\r
+ * using twi_enable_it() and twi_enable_it().</li>\r
+ * <li> Get current status register of the given TWI peripheral using\r
+ * twi_get_status(). Get current status register of the given TWI peripheral, but\r
+ * masking interrupt sources which are not currently enabled using\r
+ * twi_get_masked_status().</li>\r
+ * </ul>\r
+ * For more accurate information, please look at the TWI section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref twi.c\n\r
+ * \ref twi.h.\n\r
+*/\r
+/*@{*/\r
+/*@}*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Two Wire Interface (TWI).\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/twi.h"\r
+#include "peripherals/pmc.h"\r
+#include "trace.h"\r
+\r
+#include "timer.h"\r
+#include "io.h"\r
+\r
+#include <stddef.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures a TWI peripheral to operate in master mode, at the given\r
+ * frequency (in Hz). The duty cycle of the TWI clock is set to 50%.\r
+ * \param twi Pointer to an Twi instance.\r
+ * \param twi_clock Desired TWI clock frequency.\r
+ */\r
+void twi_configure_master(Twi * pTwi, uint32_t twi_clock)\r
+{\r
+ uint32_t ck_div, cl_div, hold, ok, clock;\r
+ uint32_t id = get_twi_id_from_addr(pTwi);\r
+\r
+ trace_debug("twi_configure_master(%u)\n\r", (unsigned)twi_clock);\r
+ assert(pTwi);\r
+ assert(id < ID_PERIPH_COUNT);\r
+\r
+ /* SVEN: TWI Slave Mode Enabled */\r
+ pTwi->TWI_CR = TWI_CR_SVEN;\r
+\r
+ /* Reset the TWI */\r
+ pTwi->TWI_CR = TWI_CR_SWRST;\r
+ pTwi->TWI_RHR;\r
+ timer_sleep(10);\r
+\r
+ /* TWI Slave Mode Disabled, TWI Master Mode Disabled. */\r
+ pTwi->TWI_MMR = 0;\r
+ pTwi->TWI_CR = TWI_CR_SVDIS;\r
+ pTwi->TWI_CR = TWI_CR_MSDIS;\r
+ clock = pmc_get_peripheral_clock(id);\r
+\r
+ /* Compute clock */\r
+ ck_div = 0; ok = 0;\r
+ while (!ok) {\r
+ cl_div = ((clock / (2 * twi_clock)) - 3) >> ck_div;\r
+ if (cl_div <= 255)\r
+ ok = 1;\r
+ else\r
+ ck_div++;\r
+ }\r
+ twi_clock = ROUND_INT_DIV(clock, (((cl_div * 2) << ck_div) + 3));\r
+ assert(ck_div < 8);\r
+ trace_debug("twi: CKDIV=%u CLDIV=CHDIV=%u -> TWI Clock %uHz\n\r",\r
+ (unsigned)ck_div, (unsigned)cl_div, (unsigned)twi_clock);\r
+\r
+ /* Compute holding time (I2C spec requires 300ns) */\r
+ hold = ROUND_INT_DIV((uint32_t)(0.3 * clock), 1000000) - 3;\r
+ trace_debug("twi: HOLD=%u -> Holding Time %uns\n\r",\r
+ (unsigned)hold, (unsigned)((1000000 * (hold + 3)) / (clock / 1000)));\r
+\r
+ /* Configure clock */\r
+ pTwi->TWI_CWGR = 0;\r
+ pTwi->TWI_CWGR = TWI_CWGR_CKDIV(ck_div) | TWI_CWGR_CHDIV(cl_div) |\r
+ TWI_CWGR_CLDIV(cl_div) | TWI_CWGR_HOLD(hold);\r
+\r
+ /* Set master mode */\r
+ pTwi->TWI_CR = TWI_CR_MSEN;\r
+ timer_sleep(10);\r
+ assert((pTwi->TWI_CR & TWI_CR_SVDIS) != TWI_CR_MSDIS);\r
+\r
+}\r
+\r
+/**\r
+ * \brief Configures a TWI peripheral to operate in slave mode.\r
+ * \param twi Pointer to an Twi instance.\r
+ * \param slaveAddress Slave address.\r
+ */\r
+void twi_configure_slave(Twi * pTwi, uint8_t slave_address)\r
+{\r
+ trace_debug("twi_configure_slave()\n\r");\r
+ assert(pTwi);\r
+ /* TWI software reset */\r
+ pTwi->TWI_CR = TWI_CR_SWRST;\r
+ pTwi->TWI_RHR;\r
+ /* Wait at least 10 ms */\r
+ timer_sleep(10);\r
+ /* TWI Slave Mode Disabled, TWI Master Mode Disabled */\r
+ pTwi->TWI_CR = TWI_CR_SVDIS | TWI_CR_MSDIS;\r
+ /* Configure slave address. */\r
+ pTwi->TWI_SMR = 0;\r
+ pTwi->TWI_SMR = TWI_SMR_SADR(slave_address);\r
+ /* SVEN: TWI Slave Mode Enabled */\r
+ pTwi->TWI_CR = TWI_CR_SVEN;\r
+ /* Wait at least 10 ms */\r
+ timer_sleep(10);\r
+ assert((pTwi->TWI_CR & TWI_CR_SVDIS) != TWI_CR_SVDIS);\r
+}\r
+\r
+/**\r
+ * \brief Sends a STOP condition on the TWI.\r
+ * \param twi Pointer to an Twi instance.\r
+ */\r
+void twi_stop(Twi * pTwi)\r
+{\r
+ assert(pTwi != NULL);\r
+ pTwi->TWI_CR = TWI_CR_STOP;\r
+}\r
+\r
+/**\r
+ * \brief Starts a read operation on the TWI bus with the specified slave, it returns\r
+ * immediately. Data must then be read using twi_read_byte() whenever a byte is\r
+ * available (poll using twi_is_byte_received()).\r
+ * \param twi Pointer to an Twi instance.\r
+ * \param address Slave address on the bus.\r
+ * \param iaddress Optional internal address bytes.\r
+ * \param isize Number of internal address bytes.\r
+ */\r
+void twi_start_read(Twi * pTwi, uint8_t address,\r
+ uint32_t iaddress, uint8_t isize)\r
+{\r
+ assert(pTwi != NULL);\r
+ assert((address & 0x80) == 0);\r
+ assert((iaddress & 0xFF000000) == 0);\r
+ assert(isize < 4);\r
+ /* Set slave address and number of internal address bytes. */\r
+ pTwi->TWI_MMR = 0;\r
+ pTwi->TWI_MMR = (isize << 8) | TWI_MMR_MREAD | (address << 16);\r
+ /* Set internal address bytes */\r
+ pTwi->TWI_IADR = 0;\r
+ pTwi->TWI_IADR = iaddress;\r
+ /* Send START condition */\r
+ pTwi->TWI_CR = TWI_CR_START;\r
+}\r
+\r
+/**\r
+ * \brief Reads a byte from the TWI bus. The read operation must have been started\r
+ * using twi_start_read() and a byte must be available (check with twi_is_byte_received()).\r
+ * \param twi Pointer to an Twi instance.\r
+ * \return byte read.\r
+ */\r
+uint8_t twi_read_byte(Twi * twi)\r
+{\r
+ assert(twi != NULL);\r
+ uint8_t value;\r
+ readb(&twi->TWI_RHR, &value);\r
+ return value;\r
+}\r
+\r
+/**\r
+ * \brief Sends a byte of data to one of the TWI slaves on the bus.\r
+ * \note This function must be called once before twi_start_write() with\r
+ * the first byte of data to send, then it shall be called repeatedly\r
+ * after that to send the remaining bytes.\r
+ * \param twi Pointer to an Twi instance.\r
+ * \param byte Byte to send.\r
+ */\r
+void twi_write_byte(Twi * twi, uint8_t byte)\r
+{\r
+ assert(twi != NULL);\r
+ writeb(&twi->TWI_THR, byte);\r
+}\r
+\r
+/**\r
+ * \brief Starts a write operation on the TWI to access the selected slave, then\r
+ * returns immediately. A byte of data must be provided to start the write;\r
+ * other bytes are written next.\r
+ * after that to send the remaining bytes.\r
+ * \param twi Pointer to an Twi instance.\r
+ * \param address Address of slave to acccess on the bus.\r
+ * \param iaddress Optional slave internal address.\r
+ * \param isize Number of internal address bytes.\r
+ * \param byte First byte to send.\r
+ */\r
+void twi_start_write(Twi * pTwi, uint8_t address, uint32_t iaddress,\r
+ uint8_t isize, uint8_t byte)\r
+{\r
+ assert(pTwi != NULL);\r
+ assert((address & 0x80) == 0);\r
+ assert((iaddress & 0xFF000000) == 0);\r
+ assert(isize < 4);\r
+ /* Set slave address and number of internal address bytes. */\r
+ pTwi->TWI_MMR = 0;\r
+ pTwi->TWI_MMR = (isize << 8) | (address << 16);\r
+ /* Set internal address bytes. */\r
+ pTwi->TWI_IADR = 0;\r
+ pTwi->TWI_IADR = iaddress;\r
+ /* Write first byte to send. */\r
+ twi_write_byte(pTwi, byte);\r
+}\r
+\r
+/**\r
+ * \brief Check if a byte have been receiced from TWI.\r
+ * \param twi Pointer to an Twi instance.\r
+ * \return 1 if a byte has been received and can be read on the given TWI\r
+ * peripheral; otherwise, returns 0. This function resets the status register.\r
+ */\r
+uint8_t twi_is_byte_received(Twi * pTwi)\r
+{\r
+ assert(pTwi != NULL);\r
+ return ((pTwi->TWI_SR & TWI_SR_RXRDY) == TWI_SR_RXRDY);\r
+}\r
+\r
+/**\r
+ * \brief Check if a byte have been sent to TWI.\r
+ * \param twi Pointer to an Twi instance.\r
+ * \return 1 if a byte has been sent so another one can be stored for\r
+ * transmission; otherwise returns 0. This function clears the status register.\r
+ */\r
+uint8_t twi_byte_sent(Twi * pTwi)\r
+{\r
+ assert(pTwi != NULL);\r
+ return ((pTwi->TWI_SR & TWI_SR_TXRDY) == TWI_SR_TXRDY);\r
+}\r
+\r
+/**\r
+ * \brief Check if current transmission is complet.\r
+ * \param twi Pointer to an Twi instance.\r
+ * \return 1 if the current transmission is complete (the STOP has been sent);\r
+ * otherwise returns 0.\r
+ */\r
+uint8_t twi_is_transfer_complete(Twi * pTwi)\r
+{\r
+ assert(pTwi != NULL);\r
+ return ((pTwi->TWI_SR & TWI_SR_TXCOMP) == TWI_SR_TXCOMP);\r
+}\r
+\r
+/**\r
+ * \brief Enables the selected interrupts sources on a TWI peripheral.\r
+ * \param twi Pointer to an Twi instance.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void twi_enable_it(Twi * pTwi, uint32_t sources)\r
+{\r
+ assert(pTwi != NULL);\r
+ pTwi->TWI_IER = sources;\r
+}\r
+\r
+/**\r
+ * \brief Disables the selected interrupts sources on a TWI peripheral.\r
+ * \param twi Pointer to an Twi instance.\r
+ * \param sources Bitwise OR of selected interrupt sources.\r
+ */\r
+void twi_disable_it(Twi * pTwi, uint32_t sources)\r
+{\r
+ assert(pTwi != NULL);\r
+ pTwi->TWI_IDR = sources;\r
+}\r
+\r
+/**\r
+ * \brief Get the current status register of the given TWI peripheral.\r
+ * \note This resets the internal value of the status register, so further\r
+ * read may yield different values.\r
+ * \param twi Pointer to an Twi instance.\r
+ * \return TWI status register.\r
+ */\r
+uint32_t twi_get_status(Twi * pTwi)\r
+{\r
+ assert(pTwi != NULL);\r
+ return pTwi->TWI_SR;\r
+}\r
+\r
+/**\r
+ * \brief Returns the current status register of the given TWI peripheral, but\r
+ * masking interrupt sources which are not currently enabled.\r
+ * \note This resets the internal value of the status register, so further\r
+ * read may yield different values.\r
+ * \param twi Pointer to an Twi instance.\r
+ */\r
+uint32_t twi_get_masked_status(Twi * pTwi)\r
+{\r
+ uint32_t status;\r
+ assert(pTwi != NULL);\r
+ status = pTwi->TWI_SR;\r
+ status &= pTwi->TWI_IMR;\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Sends a STOP condition. STOP Condition is sent just after completing\r
+ * the current byte transmission in master read mode.\r
+ * \param twi Pointer to an Twi instance.\r
+ */\r
+void twi_send_stop_condition(Twi * pTwi)\r
+{\r
+ assert(pTwi != NULL);\r
+ pTwi->TWI_CR |= TWI_CR_STOP;\r
+}\r
+\r
+#ifdef CONFIG_HAVE_TWI_ALTERNATE_CMD\r
+void twi_init_write_transfert(Twi * twi, uint8_t addr, uint32_t iaddress,\r
+ uint8_t isize, uint8_t len)\r
+{\r
+ twi->TWI_RHR;\r
+ twi->TWI_CR = TWI_CR_MSDIS;\r
+ twi->TWI_CR = TWI_CR_MSEN;\r
+ twi->TWI_CR = TWI_CR_MSEN | TWI_CR_SVDIS | TWI_CR_ACMEN;\r
+ twi->TWI_ACR = 0;\r
+ twi->TWI_ACR = TWI_ACR_DATAL(len);\r
+ twi->TWI_MMR = 0;\r
+ twi->TWI_MMR = TWI_MMR_DADR(addr) | TWI_MMR_IADRSZ(isize);\r
+ /* Set internal address bytes. */\r
+ twi->TWI_IADR = 0;\r
+ twi->TWI_IADR = iaddress;\r
+}\r
+\r
+void twi_init_read_transfert(Twi * twi, uint8_t addr, uint32_t iaddress,\r
+ uint8_t isize, uint8_t len)\r
+{\r
+ twi->TWI_RHR;\r
+ twi->TWI_CR = TWI_CR_MSEN | TWI_CR_SVDIS | TWI_CR_ACMEN;\r
+ twi->TWI_ACR = 0;\r
+ twi->TWI_ACR = TWI_ACR_DATAL(len) | TWI_ACR_DIR;\r
+ twi->TWI_MMR = 0;\r
+ twi->TWI_MMR = TWI_MMR_DADR(addr) | TWI_MMR_MREAD\r
+ | TWI_MMR_IADRSZ(isize);\r
+ /* Set internal address bytes. */\r
+ twi->TWI_IADR = 0;\r
+ twi->TWI_IADR = iaddress;\r
+ twi->TWI_CR = TWI_CR_START;\r
+ while(twi->TWI_SR & TWI_SR_TXCOMP);\r
+}\r
+#endif\r
+\r
+#ifdef CONFIG_HAVE_TWI_FIFO\r
+void twi_fifo_configure(Twi* twi, uint8_t tx_thres,\r
+ uint8_t rx_thres,\r
+ uint32_t ready_modes)\r
+{\r
+ /* Disable TWI master and slave mode and activate FIFO */\r
+ twi->TWI_CR = TWI_CR_MSDIS | TWI_CR_SVDIS | TWI_CR_FIFOEN;\r
+\r
+ /* Configure FIFO */\r
+ twi->TWI_FMR = TWI_FMR_TXFTHRES(tx_thres) | TWI_FMR_RXFTHRES(rx_thres)\r
+ | ready_modes;\r
+}\r
+\r
+uint32_t twi_fifo_rx_size(Twi *twi)\r
+{\r
+ return (twi->TWI_FLR & TWI_FLR_RXFL_Msk) >> TWI_FLR_RXFL_Pos;\r
+}\r
+\r
+uint32_t twi_fifo_tx_size(Twi *twi)\r
+{\r
+ return (twi->TWI_FLR & TWI_FLR_TXFL_Msk) >> TWI_FLR_TXFL_Pos;\r
+}\r
+\r
+uint32_t twi_read_stream(Twi *twi, uint32_t addr, uint32_t iaddr,\r
+ uint32_t isize, const void *stream, uint8_t len)\r
+{\r
+ const uint8_t* buffer = stream;\r
+ uint8_t left = len;\r
+\r
+ twi_init_read_transfert(twi, addr, iaddr, isize, len);\r
+ if (twi_get_status(twi) & TWI_SR_NACK) {\r
+ trace_error("twid2: command NACK!\r\n");\r
+ return 0;\r
+ }\r
+\r
+ while (left > 0) {\r
+ if ((twi->TWI_SR & TWI_SR_RXRDY) == 0) continue;\r
+\r
+ /* Get FIFO free size (int octet) and clamp it */\r
+ uint32_t buf_size = twi_fifo_rx_size(twi);\r
+ buf_size = buf_size > left ? left : buf_size;\r
+\r
+ /* Fill the FIFO as must as possible */\r
+ while (buf_size > sizeof(uint32_t)) {\r
+ *(uint32_t*)buffer = twi->TWI_RHR;\r
+ buffer += sizeof(uint32_t);\r
+ left -= sizeof(uint32_t);\r
+ buf_size -= sizeof(uint32_t);\r
+ }\r
+ while (buf_size >= sizeof(uint8_t)) {\r
+ readb(&twi->TWI_RHR, (uint8_t*)buffer);\r
+ buffer += sizeof(uint8_t);\r
+ left -= sizeof(uint8_t);\r
+ buf_size -= sizeof(uint8_t);\r
+ }\r
+ }\r
+ return len - left;\r
+}\r
+\r
+uint32_t twi_write_stream(Twi *twi, uint32_t addr, uint32_t iaddr,\r
+ uint32_t isize, const void *stream, uint8_t len)\r
+{\r
+ const uint8_t* buffer = stream;\r
+ uint8_t left = len;\r
+\r
+ int32_t fifo_size = get_peripheral_fifo_depth(twi);\r
+ if (fifo_size < 0)\r
+ return 0;\r
+\r
+ twi_init_write_transfert(twi, addr, iaddr, isize, len);\r
+ if (twi_get_status(twi) & TWI_SR_NACK) {\r
+ trace_error("twid2: command NACK!\r\n");\r
+ return 0;\r
+ }\r
+ while (left > 0) {\r
+ if ((twi->TWI_SR & TWI_SR_TXRDY) == 0) continue;\r
+\r
+ /* Get FIFO free size (int octet) and clamp it */\r
+ uint32_t buf_size = fifo_size - twi_fifo_tx_size(twi);\r
+ buf_size = buf_size > left ? left : buf_size;\r
+\r
+ /* /\* Fill the FIFO as must as possible *\/ */\r
+ while (buf_size >= sizeof(uint8_t)) {\r
+ writeb(&twi->TWI_THR,*buffer);\r
+ buffer += sizeof(uint8_t);\r
+ left -= sizeof(uint8_t);\r
+ buf_size -= sizeof(uint8_t);\r
+ }\r
+ }\r
+ return len - left;\r
+}\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for configuration the Two Wire Interface (TWI) peripheral.\r
+ *\r
+ */\r
+\r
+#ifndef _TWI_H_\r
+#define _TWI_H_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macros\r
+ *----------------------------------------------------------------------------*/\r
+/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given status register value.*/\r
+#define TWI_STATUS_TXRDY(status) ((status & TWI_SR_TXRDY) == TWI_SR_TXRDY)\r
+\r
+/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given status register value.*/\r
+#define TWI_STATUS_RXRDY(status) ((status & TWI_SR_RXRDY) == TWI_SR_RXRDY)\r
+\r
+/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given status register value.*/\r
+#define TWI_STATUS_TXCOMP(status) ((status & TWI_SR_TXCOMP) == TWI_SR_TXCOMP)\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * External function\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void twi_configure_master(Twi * pTwi, uint32_t twck);\r
+extern void twi_configure_slave(Twi * pTwi, uint8_t slaveAddress);\r
+extern void twi_stop(Twi * pTwi);\r
+extern void twi_start_read(Twi * pTwi, uint8_t address,\r
+ uint32_t iaddress, uint8_t isize);\r
+extern uint8_t twi_read_byte(Twi * pTwi);\r
+extern void twi_write_byte(Twi * pTwi, uint8_t byte);\r
+extern void twi_start_write(Twi * pTwi, uint8_t address, uint32_t iaddress,\r
+ uint8_t isize, uint8_t byte);\r
+extern uint8_t twi_is_byte_received(Twi * pTwi);\r
+extern uint8_t twi_byte_sent(Twi * pTwi);\r
+extern uint8_t twi_is_transfer_complete(Twi * pTwi);\r
+extern void twi_enable_it(Twi * pTwi, uint32_t sources);\r
+extern void twi_disable_it(Twi * pTwi, uint32_t sources);\r
+extern uint32_t twi_get_status(Twi * pTwi);\r
+extern uint32_t twi_get_masked_status(Twi * pTwi);\r
+extern void twi_send_stop_condition(Twi * pTwi);\r
+\r
+#ifdef CONFIG_HAVE_TWI_ALTERNATE_CMD\r
+extern void twi_init_write_transfert(Twi * twi, uint8_t addr, uint32_t iaddress,\r
+ uint8_t isize, uint8_t len);\r
+extern void twi_init_read_transfert(Twi * twi, uint8_t addr, uint32_t iaddress,\r
+ uint8_t isize, uint8_t len);\r
+#endif\r
+\r
+#ifdef CONFIG_HAVE_TWI_FIFO\r
+extern void twi_fifo_configure(Twi* twi, uint8_t tx_thres,\r
+ uint8_t rx_thres,\r
+ uint32_t ready_modes);\r
+extern void twi_fifo_disable(Twi* twi);\r
+\r
+extern uint32_t twi_fifo_rx_size(Twi *twi);\r
+extern uint32_t twi_fifo_tx_size(Twi *twi);\r
+\r
+extern uint32_t twi_read_stream(Twi *twi, uint32_t addr, uint32_t iaddr,\r
+ uint32_t isize, const void *stream, uint8_t len);\r
+extern uint32_t twi_write_stream(Twi *twi, uint32_t addr, uint32_t iaddr,\r
+ uint32_t isize, const void *stream, uint8_t len);\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* #ifndef _TWI_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+#ifdef CONFIG_HAVE_FLEXCOM\r
+#include "peripherals/flexcom.h"\r
+#endif\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/twid.h"\r
+#include "peripherals/twi.h"\r
+#include "peripherals/xdmad.h"\r
+#include "peripherals/l2cc.h"\r
+\r
+#include "cortex-a/cp15.h"\r
+\r
+#include "trace.h"\r
+#include "io.h"\r
+#include "timer.h"\r
+\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+#define TWID_DMA_THRESHOLD 16\r
+#define TWID_TIMEOUT 100\r
+\r
+static uint32_t _twid_wait_twi_transfer(struct _twi_desc* desc)\r
+{\r
+ struct _timeout timeout;\r
+ timer_start_timeout(&timeout, TWID_TIMEOUT);\r
+ while(!twi_is_transfer_complete(desc->addr)){\r
+ if (timer_timeout_reached(&timeout)) {\r
+ trace_error("twid: Unable to complete transfert!\r\n");\r
+ twid_configure(desc);\r
+ return TWID_ERROR_TRANSFER;\r
+ }\r
+ }\r
+ return TWID_SUCCESS;\r
+}\r
+\r
+static void _twid_xdmad_callback_wrapper(struct _xdmad_channel* channel,\r
+ void* args)\r
+{\r
+ trace_debug("TWID DMA Transfert Finished\r\n");\r
+ struct _twi_desc* twid = (struct _twi_desc*) args;\r
+\r
+ xdmad_free_channel(channel);\r
+\r
+ if (twid->region_start && twid->region_end) {\r
+ l2cc_invalidate_region(twid->region_start, twid->region_end);\r
+ }\r
+\r
+ if (twid && twid->callback)\r
+ twid->callback(twid, twid->cb_args);\r
+\r
+}\r
+\r
+static void _twid_init_dma_read_channel(const struct _twi_desc* desc,\r
+ struct _xdmad_channel** channel,\r
+ struct _xdmad_cfg* cfg)\r
+{\r
+ assert(cfg);\r
+ assert(channel);\r
+\r
+ uint32_t id = get_twi_id_from_addr(desc->addr);\r
+ assert(id < ID_PERIPH_COUNT);\r
+\r
+ memset(cfg, 0x0, sizeof(*cfg));\r
+\r
+ *channel =\r
+ xdmad_allocate_channel(id, XDMAD_PERIPH_MEMORY);\r
+ assert(*channel);\r
+\r
+ xdmad_prepare_channel(*channel);\r
+ cfg->cfg.uint32_value = XDMAC_CC_TYPE_PER_TRAN\r
+ | XDMAC_CC_DSYNC_PER2MEM\r
+ | XDMAC_CC_MEMSET_NORMAL_MODE\r
+ | XDMAC_CC_CSIZE_CHK_1\r
+ | XDMAC_CC_DWIDTH_BYTE\r
+ | XDMAC_CC_DIF_AHB_IF0\r
+ | XDMAC_CC_SIF_AHB_IF1\r
+ | XDMAC_CC_SAM_FIXED_AM;\r
+\r
+ cfg->src_addr = (void*)&desc->addr->TWI_RHR;\r
+}\r
+\r
+static void _twid_dma_read(const struct _twi_desc* desc,\r
+ struct _buffer* buffer)\r
+{\r
+ struct _xdmad_channel* channel = NULL;\r
+ struct _xdmad_cfg cfg;\r
+\r
+ _twid_init_dma_read_channel(desc, &channel, &cfg);\r
+\r
+ cfg.cfg.bitfield.dam = XDMAC_CC_DAM_INCREMENTED_AM\r
+ >> XDMAC_CC_DAM_Pos;\r
+ cfg.dest_addr = buffer->data;\r
+ cfg.ublock_size = buffer->size;\r
+ cfg.block_size = 0;\r
+ xdmad_configure_transfer(channel, &cfg, 0, 0);\r
+ xdmad_set_callback(channel, _twid_xdmad_callback_wrapper,\r
+ (void*)desc);\r
+\r
+ l2cc_clean_region(desc->region_start, desc->region_end);\r
+\r
+ xdmad_start_transfer(channel);\r
+}\r
+\r
+static void _twid_init_dma_write_channel(struct _twi_desc* desc,\r
+ struct _xdmad_channel** channel,\r
+ struct _xdmad_cfg* cfg)\r
+{\r
+ assert(cfg);\r
+ assert(channel);\r
+\r
+ uint32_t id = get_twi_id_from_addr(desc->addr);\r
+ assert(id < ID_PERIPH_COUNT);\r
+ memset(cfg, 0x0, sizeof(*cfg));\r
+\r
+ *channel =\r
+ xdmad_allocate_channel(XDMAD_PERIPH_MEMORY, id);\r
+ assert(*channel);\r
+\r
+ xdmad_prepare_channel(*channel);\r
+ cfg->cfg.uint32_value = XDMAC_CC_TYPE_PER_TRAN\r
+ | XDMAC_CC_DSYNC_MEM2PER\r
+ | XDMAC_CC_MEMSET_NORMAL_MODE\r
+ | XDMAC_CC_CSIZE_CHK_1\r
+ | XDMAC_CC_DWIDTH_BYTE\r
+ | XDMAC_CC_DIF_AHB_IF1\r
+ | XDMAC_CC_SIF_AHB_IF0\r
+ | XDMAC_CC_DAM_FIXED_AM;\r
+\r
+ cfg->dest_addr = (void*)&desc->addr->TWI_THR;\r
+}\r
+\r
+static void _twid_dma_write(struct _twi_desc* desc,\r
+ struct _buffer* buffer)\r
+{\r
+ struct _xdmad_channel* channel = NULL;\r
+ struct _xdmad_cfg cfg;\r
+\r
+ _twid_init_dma_write_channel(desc, &channel, &cfg);\r
+\r
+ cfg.cfg.bitfield.sam = XDMAC_CC_SAM_INCREMENTED_AM\r
+ >> XDMAC_CC_SAM_Pos;\r
+ cfg.src_addr = buffer->data;\r
+ cfg.ublock_size = buffer->size;\r
+ cfg.block_size = 0;\r
+ xdmad_configure_transfer(channel, &cfg, 0, 0);\r
+ xdmad_set_callback(channel, _twid_xdmad_callback_wrapper,\r
+ (void*)desc);\r
+\r
+ l2cc_clean_region(desc->region_start, desc->region_end);\r
+\r
+ xdmad_start_transfer(channel);\r
+}\r
+\r
+void twid_configure(struct _twi_desc* desc)\r
+{\r
+ uint32_t id = get_twi_id_from_addr(desc->addr);\r
+ assert(id < ID_PERIPH_COUNT);\r
+\r
+#ifdef CONFIG_HAVE_FLEXCOM\r
+ Flexcom* flexcom = get_flexcom_addr_from_id(get_twi_id_from_addr(desc->addr));\r
+ if (flexcom) {\r
+ flexcom_select(flexcom, FLEX_MR_OPMODE_TWI);\r
+ }\r
+#endif\r
+\r
+ pmc_enable_peripheral(id);\r
+ twi_configure_master(desc->addr, desc->freq);\r
+\r
+#ifdef CONFIG_HAVE_TWI_FIFO\r
+ if (desc->transfert_mode == TWID_MODE_FIFO) {\r
+ uint32_t fifo_depth = get_peripheral_fifo_depth(desc->addr);\r
+ twi_fifo_configure(desc->addr, fifo_depth/2, fifo_depth/2,\r
+ TWI_FMR_RXRDYM_ONE_DATA | TWI_FMR_TXRDYM_ONE_DATA);\r
+ }\r
+#endif\r
+}\r
+\r
+static uint32_t _twid_poll_write(struct _twi_desc* desc, struct _buffer* buffer)\r
+{\r
+ int i = 0;\r
+ struct _timeout timeout;\r
+ twi_init_write_transfert(desc->addr,\r
+ desc->slave_addr,\r
+ desc->iaddr,\r
+ desc->isize,\r
+ buffer->size);\r
+ if (twi_get_status(desc->addr) & TWI_SR_NACK) {\r
+ trace_error("twid: command NACK!\r\n");\r
+ return TWID_ERROR_ACK;\r
+ }\r
+ for (i = 0; i < buffer->size; ++i) {\r
+ timer_start_timeout(&timeout, TWID_TIMEOUT);\r
+ while(!twi_byte_sent(desc->addr)) {\r
+ if (timer_timeout_reached(&timeout)) {\r
+ trace_error("twid: Device doesn't answer, "\r
+ "(TX TIMEOUT)\r\n");\r
+ break;\r
+ }\r
+ }\r
+ twi_write_byte(desc->addr, buffer->data[i]);\r
+ if(twi_get_status(desc->addr) & TWI_SR_NACK) {\r
+ trace_error("twid: command NACK!\r\n");\r
+ return TWID_ERROR_ACK;\r
+ }\r
+ }\r
+ /* wait transfert to be finished */\r
+ return _twid_wait_twi_transfer(desc);\r
+}\r
+\r
+static uint32_t _twid_poll_read(struct _twi_desc* desc, struct _buffer* buffer)\r
+{\r
+ int i = 0;\r
+ struct _timeout timeout;\r
+ twi_init_read_transfert(desc->addr,\r
+ desc->slave_addr,\r
+ desc->iaddr,\r
+ desc->isize,\r
+ buffer->size);\r
+ if (twi_get_status(desc->addr) & TWI_SR_NACK) {\r
+ trace_error("twid: command NACK!\r\n");\r
+ return TWID_ERROR_ACK;\r
+ }\r
+ for (i = 0; i < buffer->size; ++i) {\r
+ timer_start_timeout(&timeout, TWID_TIMEOUT);\r
+ while(!twi_is_byte_received(desc->addr)) {\r
+ if (timer_timeout_reached(&timeout)) {\r
+ trace_error("twid: Device doesn't answer, "\r
+ "(RX TIMEOUT)\r\n");\r
+ break;\r
+ }\r
+ }\r
+ buffer->data[i] = twi_read_byte(desc->addr);\r
+ if(twi_get_status(desc->addr) & TWI_SR_NACK) {\r
+ trace_error("twid: command NACK\r\n");\r
+ return TWID_ERROR_ACK;\r
+ }\r
+ }\r
+ /* wait transfert to be finished */\r
+ return _twid_wait_twi_transfer(desc);\r
+}\r
+\r
+uint32_t twid_transfert(struct _twi_desc* desc, struct _buffer* rx,\r
+ struct _buffer* tx, twid_callback_t cb,\r
+ void* user_args)\r
+{\r
+ uint32_t status = TWID_SUCCESS;\r
+\r
+ desc->callback = cb;\r
+ desc->cb_args = user_args;\r
+\r
+ if (mutex_try_lock(&desc->mutex)) {\r
+ return TWID_ERROR_LOCK;\r
+ }\r
+\r
+ switch (desc->transfert_mode) {\r
+ case TWID_MODE_POLLING:\r
+ if (tx) {\r
+ status = _twid_poll_write(desc, tx);\r
+ if (status) break;\r
+ }\r
+ if (rx) {\r
+ status = _twid_poll_read(desc, rx);\r
+ if (status) break;\r
+ }\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ mutex_free(&desc->mutex);\r
+ break;\r
+\r
+ case TWID_MODE_DMA:\r
+ if (!(rx || tx)) {\r
+ status = TWID_ERROR_DUPLEX;\r
+ break;\r
+ }\r
+ if (tx) {\r
+ if (tx->size < TWID_DMA_THRESHOLD) {\r
+ status = _twid_poll_write(desc, tx);\r
+ if (status) break;\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ mutex_free(&desc->mutex);\r
+ } else {\r
+ twi_init_write_transfert(desc->addr,\r
+ desc->slave_addr,\r
+ desc->iaddr,\r
+ desc->isize,\r
+ tx->size);\r
+ desc->region_start = (uint32_t)tx->data;\r
+ desc->region_end = desc->region_start\r
+ + tx->size;\r
+ _twid_dma_write(desc, tx);\r
+ }\r
+ }\r
+ if (rx) {\r
+ if (rx->size < TWID_DMA_THRESHOLD) {\r
+ status = _twid_poll_read(desc, rx);\r
+ if (status) break;\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ mutex_free(&desc->mutex);\r
+ } else {\r
+ twi_init_read_transfert(desc->addr,\r
+ desc->slave_addr,\r
+ desc->iaddr,\r
+ desc->isize,\r
+ rx->size);\r
+ desc->region_start = (uint32_t)rx->data;\r
+ desc->region_end = desc->region_start\r
+ + rx->size;\r
+ if(twi_get_status(desc->addr) & TWI_SR_NACK) {\r
+ trace_error("twid: Acknolegment "\r
+ "Error\r\n");\r
+ status = TWID_ERROR_ACK;\r
+ break;\r
+ }\r
+ _twid_dma_read(desc, rx);\r
+ }\r
+ }\r
+ break;\r
+\r
+#ifdef CONFIG_HAVE_TWI_FIFO\r
+ case TWID_MODE_FIFO:\r
+ if (tx) {\r
+ status = twi_write_stream(desc->addr, desc->slave_addr,\r
+ desc->iaddr, desc->isize,\r
+ tx->data, tx->size);\r
+ status = status ? TWID_SUCCESS : TWID_ERROR_ACK;\r
+ if (status)\r
+ break;\r
+ status = _twid_wait_twi_transfer(desc);\r
+ if (status)\r
+ break;\r
+ }\r
+ if (rx) {\r
+ status = twi_read_stream(desc->addr, desc->slave_addr,\r
+ desc->iaddr, desc->isize,\r
+ rx->data, rx->size);\r
+ status = status ? TWID_SUCCESS : TWID_ERROR_ACK;\r
+ if (status)\r
+ break;\r
+ status = _twid_wait_twi_transfer(desc);\r
+ if (status)\r
+ break;\r
+ }\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ mutex_free(&desc->mutex);\r
+ break;\r
+#endif\r
+ default:\r
+ trace_debug("Unkown mode");\r
+ }\r
+\r
+ if (status)\r
+ mutex_free(&desc->mutex);\r
+\r
+ return status;\r
+}\r
+\r
+void twid_finish_transfert_callback(struct _twi_desc* desc, void* user_args)\r
+{\r
+ (void)user_args;\r
+ twid_finish_transfert(desc);\r
+}\r
+\r
+void twid_finish_transfert(struct _twi_desc* desc)\r
+{\r
+ mutex_free(&desc->mutex);\r
+}\r
+\r
+uint32_t twid_is_busy(const struct _twi_desc* desc)\r
+{\r
+ return mutex_is_locked(&desc->mutex);\r
+}\r
+\r
+void twid_wait_transfert(const struct _twi_desc* desc)\r
+{\r
+ while (mutex_is_locked(&desc->mutex));\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef TWID_HEADER__\r
+#define TWID_HEADER__\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Header\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "peripherals/twi.h"\r
+#include "mutex.h"\r
+#include "io.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define TWID_SUCCESS (0)\r
+#define TWID_INVALID_ID (1)\r
+#define TWID_INVALID_BITRATE (2)\r
+#define TWID_ERROR_LOCK (3)\r
+#define TWID_ERROR_DUPLEX (4)\r
+#define TWID_ERROR_ACK (5)\r
+#define TWID_ERROR_TIMEOUT (6)\r
+#define TWID_ERROR_TRANSFER (7)\r
+\r
+enum _twid_trans_mode\r
+{\r
+ TWID_MODE_POLLING,\r
+ TWID_MODE_FIFO,\r
+ TWID_MODE_DMA\r
+};\r
+\r
+struct _twi_desc;\r
+\r
+typedef void (*twid_callback_t)(struct _twi_desc* spid, void* args);\r
+\r
+struct _twi_desc\r
+{\r
+ Twi* addr;\r
+ uint32_t freq;\r
+ uint32_t slave_addr;\r
+ uint32_t iaddr;\r
+ uint32_t isize;\r
+ uint8_t transfert_mode;\r
+ /* implicit internal padding is mandatory here */\r
+ mutex_t mutex;\r
+ uint32_t region_start;\r
+ uint32_t region_end;\r
+ twid_callback_t callback;\r
+ void* cb_args;\r
+};\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void twid_configure(struct _twi_desc* desc);\r
+extern uint32_t twid_transfert(struct _twi_desc* desc, struct _buffer* rx,\r
+ struct _buffer* tx, twid_callback_t cb,\r
+ void* user_args);\r
+extern void twid_finish_transfert_callback(struct _twi_desc* desc,\r
+ void* user_args);\r
+extern void twid_finish_transfert(struct _twi_desc* desc);\r
+extern uint32_t twid_is_busy(const struct _twi_desc* desc);\r
+extern void twid_wait_transfert(const struct _twi_desc* desc);\r
+\r
+#endif /* TWID_HEADER__ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "peripherals/twid_legacy.h"\r
+#include "peripherals/xdmad.h"\r
+#include "cortex-a/cp15.h"\r
+#include "trace.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definition\r
+ *----------------------------------------------------------------------------*/\r
+#define TWITIMEOUTMAX 0xfffff\r
+\r
+static struct _xdmad_cfg twi_dmaCfg;\r
+static struct _xdmad_channel *dmaWriteChannel;\r
+static struct _xdmad_channel *dmaReadChannel;\r
+static struct _xdmad_desc_view1 dmaWriteLinkList[1];\r
+static struct _xdmad_desc_view1 dmaReadLinkList[1];\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** TWI driver callback function.*/\r
+typedef void (*TwiCallback) (struct _async *);\r
+\r
+/** \brief TWI asynchronous transfer descriptor.*/\r
+struct _async_twi {\r
+ volatile uint32_t status; /** Asynchronous transfer status. */\r
+ TwiCallback callback; /** Callback function to invoke when transfer completes or fails.*/\r
+ uint8_t *pData; /** Pointer to the data buffer.*/\r
+ uint32_t num; /** Total number of bytes to transfer.*/\r
+ uint32_t transferred; /** Number of already transferred bytes.*/\r
+};\r
+\r
+//struct _async_twi async_twi ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Initializes a TWI DMA Read channel.\r
+ */\r
+static void twid_dma_initialize_read(uint8_t TWI_ID)\r
+{\r
+ /* Allocate a XDMA channel, Read accesses into TWI_THR */\r
+ dmaReadChannel = xdmad_allocate_channel(TWI_ID, XDMAD_PERIPH_MEMORY);\r
+ if (!dmaReadChannel) {\r
+ printf("-E- Can't allocate XDMA channel\n\r");\r
+ }\r
+ xdmad_prepare_channel(dmaReadChannel);\r
+}\r
+\r
+/**\r
+ * \brief Initializes a TWI DMA write channel.\r
+ */\r
+static void twid_dma_initialize_write(uint8_t TWI_ID)\r
+{\r
+\r
+ /* Allocate a XDMA channel, Write accesses into TWI_THR */\r
+ dmaWriteChannel = xdmad_allocate_channel(XDMAD_PERIPH_MEMORY, TWI_ID);\r
+ if (!dmaWriteChannel) {\r
+ printf("-E- Can't allocate XDMA channel\n\r");\r
+ }\r
+ xdmad_prepare_channel(dmaWriteChannel);\r
+\r
+}\r
+\r
+/**\r
+ * \brief Initializes a TWI driver instance, using the given TWI peripheral.\r
+ * \note The peripheral must have been initialized properly before calling this function.\r
+ * \param pTwid Pointer to the Twid instance to initialize.\r
+ * \param pTwi Pointer to the TWI peripheral to use.\r
+ */\r
+void twid_initialize(struct _twid* pTwid, Twi * pTwi)\r
+{\r
+ trace_debug("twid_initialize()\n\r");\r
+ assert(pTwid != NULL);\r
+ assert(pTwi != NULL);\r
+\r
+ /* Initialize driver. */\r
+ pTwid->pTwi = pTwi;\r
+ pTwid->pTransfer = 0;\r
+ /* Initialize XDMA driver instance with polling mode */\r
+\r
+ // ************* need to be updated XDMAD_Initialize(&twi_dma, 1);\r
+}\r
+\r
+/**\r
+ * \brief Configure xDMA write linker list for TWI transfer.\r
+ */\r
+static void _xdma_configure_write(uint8_t * buf, uint32_t len, uint8_t twi_id)\r
+{\r
+ uint32_t i;\r
+ uint32_t xdmaCndc, Thr;\r
+ Twi* twi = (Twi*)get_twi_addr_from_id(twi_id);\r
+\r
+ Thr = (uint32_t) & (TWI0->TWI_THR);\r
+ if (twi)\r
+ Thr = (uint32_t) & (twi->TWI_THR);\r
+ for (i = 0; i < 1; i++) {\r
+ dmaWriteLinkList[i].ublock_size = XDMA_UBC_NVIEW_NDV1\r
+ | ((i == len - 1) ? 0 : XDMA_UBC_NDE_FETCH_EN)\r
+ | len;\r
+ dmaWriteLinkList[i].src_addr = & buf[i];\r
+ dmaWriteLinkList[i].dest_addr = (void*)Thr;\r
+ if (i == len - 1)\r
+ dmaWriteLinkList[i].next_desc = 0;\r
+ else\r
+ dmaWriteLinkList[i].next_desc =\r
+ & dmaWriteLinkList[i + 1];\r
+ }\r
+ twi_dmaCfg.cfg.uint32_value = XDMAC_CC_TYPE_PER_TRAN\r
+ | XDMAC_CC_MBSIZE_SINGLE\r
+ | XDMAC_CC_DSYNC_MEM2PER\r
+ | XDMAC_CC_CSIZE_CHK_1\r
+ | XDMAC_CC_DWIDTH_BYTE\r
+ | XDMAC_CC_SIF_AHB_IF0\r
+ | XDMAC_CC_DIF_AHB_IF1\r
+ | XDMAC_CC_SAM_INCREMENTED_AM\r
+ | XDMAC_CC_DAM_FIXED_AM\r
+ |\r
+ XDMAC_CC_PERID(get_peripheral_xdma_channel(twi_id, XDMAC0, true));\r
+ xdmaCndc =\r
+ XDMAC_CNDC_NDVIEW_NDV1 | XDMAC_CNDC_NDE_DSCR_FETCH_EN |\r
+ XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED |\r
+ XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED;\r
+ cp15_coherent_dcache_for_dma((uint32_t) & dmaWriteLinkList,\r
+ ((uint32_t) & dmaWriteLinkList +\r
+ sizeof (*dmaWriteLinkList) * len));\r
+ xdmad_configure_transfer(dmaWriteChannel, &twi_dmaCfg,\r
+ xdmaCndc, dmaWriteLinkList);\r
+}\r
+\r
+/**\r
+ * \brief Configure xDMA read linker list for TWI transfer.\r
+ */\r
+static void _xdma_configure_read(uint8_t * buf, uint32_t len, uint8_t twi_id)\r
+{\r
+ uint32_t i;\r
+ uint32_t xdmaCndc, Rhr;\r
+ Twi* twi = get_twi_addr_from_id(twi_id);\r
+\r
+ Rhr = (uint32_t) & (TWI0->TWI_RHR);\r
+ if (twi) {\r
+ Rhr = twi->TWI_RHR;\r
+ }\r
+ /* if (twi_id == ID_TWI1) { */\r
+ /* Rhr = (uint32_t) & (TWI1->TWI_RHR); */\r
+ /* } */\r
+ /* if (twi_id == ID_TWI2) { */\r
+ /* Rhr = (uint32_t) & (TWI2->TWI_RHR); */\r
+ /* } */\r
+ for (i = 0; i < 1; i++) {\r
+ dmaReadLinkList[i].ublock_size = XDMA_UBC_NVIEW_NDV1\r
+ | ((i == len - 1) ? 0 : XDMA_UBC_NDE_FETCH_EN)\r
+ | len;\r
+ dmaReadLinkList[i].src_addr = (void*)Rhr;\r
+ dmaReadLinkList[i].dest_addr = & buf[i];\r
+ if (i == len - 1)\r
+ dmaReadLinkList[i].next_desc = 0;\r
+ else\r
+ dmaReadLinkList[i].next_desc =\r
+ & dmaReadLinkList[i + 1];\r
+ }\r
+ twi_dmaCfg.cfg.uint32_value = XDMAC_CC_TYPE_PER_TRAN\r
+ | XDMAC_CC_MBSIZE_SINGLE\r
+ | XDMAC_CC_DSYNC_PER2MEM\r
+ | XDMAC_CC_CSIZE_CHK_1\r
+ | XDMAC_CC_DWIDTH_BYTE\r
+ | XDMAC_CC_SIF_AHB_IF1\r
+ | XDMAC_CC_DIF_AHB_IF0\r
+ | XDMAC_CC_SAM_FIXED_AM\r
+ | XDMAC_CC_DAM_INCREMENTED_AM\r
+ |\r
+ XDMAC_CC_PERID(get_peripheral_xdma_channel(twi_id, XDMAC0, false));\r
+ xdmaCndc =\r
+ XDMAC_CNDC_NDVIEW_NDV1 | XDMAC_CNDC_NDE_DSCR_FETCH_EN |\r
+ XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED |\r
+ XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED;\r
+ cp15_coherent_dcache_for_dma((uint32_t) & dmaReadLinkList,\r
+ ((uint32_t) & dmaReadLinkList +\r
+ sizeof (*dmaReadLinkList) * len));\r
+ xdmad_configure_transfer(dmaReadChannel, &twi_dmaCfg, xdmaCndc,\r
+ dmaReadLinkList);\r
+}\r
+\r
+/**\r
+ * \brief Interrupt handler for a TWI peripheral. Manages asynchronous transfer\r
+ * occuring on the bus. This function MUST be called by the interrupt service\r
+ * routine of the TWI peripheral if asynchronous read/write are needed.\r
+ * \param pTwid Pointer to a Twid instance.\r
+ */\r
+void twid_handler(struct _twid* pTwid)\r
+{\r
+ uint32_t status;\r
+ struct _async_twi* pTransfer;\r
+ Twi *pTwi;\r
+\r
+ assert(pTwid != NULL);\r
+\r
+ pTransfer = (struct _async_twi *) pTwid->pTransfer;\r
+ assert(pTransfer != NULL);\r
+ pTwi = pTwid->pTwi;\r
+ assert(pTwi != NULL);\r
+\r
+ /* Retrieve interrupt status */\r
+ status = twi_get_masked_status(pTwi);\r
+\r
+ /* Byte received */\r
+ if (TWI_STATUS_RXRDY(status)) {\r
+\r
+ pTransfer->pData[pTransfer->transferred] = twi_read_byte(pTwi);\r
+ pTransfer->transferred++;\r
+\r
+ /* check for transfer finish */\r
+ if (pTransfer->transferred == pTransfer->num) {\r
+\r
+ twi_enable_it(pTwi, TWI_IDR_RXRDY);\r
+ twi_enable_it(pTwi, TWI_IER_TXCOMP);\r
+ }\r
+ /* Last byte? */\r
+ else if (pTransfer->transferred == (pTransfer->num - 1)) {\r
+\r
+ twi_stop(pTwi);\r
+ }\r
+ }\r
+ /* Byte sent */\r
+ else if (TWI_STATUS_TXRDY(status)) {\r
+\r
+ /* Transfer finished ? */\r
+ if (pTransfer->transferred == pTransfer->num) {\r
+\r
+ twi_enable_it(pTwi, TWI_IDR_TXRDY);\r
+ twi_enable_it(pTwi, TWI_IER_TXCOMP);\r
+ twi_send_stop_condition(pTwi);\r
+ }\r
+ /* Bytes remaining */\r
+ else {\r
+\r
+ twi_write_byte(pTwi,\r
+ pTransfer->pData[pTransfer->transferred]);\r
+ pTransfer->transferred++;\r
+ }\r
+ }\r
+ /* Transfer complete */\r
+ else if (TWI_STATUS_TXCOMP(status)) {\r
+\r
+ twi_enable_it(pTwi, TWI_IDR_TXCOMP);\r
+ pTransfer->status = 0;\r
+ if (pTransfer->callback) {\r
+ pTransfer->callback((struct _async *) (void *) pTransfer);\r
+ }\r
+ pTwid->pTransfer = 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Asynchronously reads data from a slave on the TWI bus. An optional\r
+ * callback function is triggered when the transfer is complete.\r
+ * \param pTwid Pointer to a Twid instance.\r
+ * \param address TWI slave address.\r
+ * \param iaddress Optional slave internal address.\r
+ * \param isize Internal address size in bytes.\r
+ * \param pData Data buffer for storing received bytes.\r
+ * \param num Number of bytes to read.\r
+ * \param pAsync Asynchronous transfer descriptor.\r
+ * \return 0 if the transfer has been started; otherwise returns a TWI error code.\r
+ */\r
+uint8_t twid_read(struct _twid* pTwid, uint8_t address, uint32_t iaddress,\r
+ uint8_t isize, uint8_t * pData, uint32_t num, struct _async * pAsync)\r
+{\r
+ Twi *pTwi;\r
+ struct _async_twi* pTransfer;\r
+ uint32_t timeout = 0;\r
+ uint32_t i = 0;\r
+ uint32_t status;\r
+\r
+ assert(pTwid != NULL);\r
+ pTwi = pTwid->pTwi;\r
+ pTransfer = (struct _async_twi*) pTwid->pTransfer;\r
+\r
+ assert((address & 0x80) == 0);\r
+ assert((iaddress & 0xFF000000) == 0);\r
+ assert(isize < 4);\r
+\r
+ /* Check that no transfer is already pending */\r
+ if (pTransfer) {\r
+\r
+ trace_error("twid_read: A transfer is already pending\n\r");\r
+ return TWID_ERROR_BUSY;\r
+ }\r
+\r
+ /* Asynchronous transfer */\r
+ if (pAsync) {\r
+\r
+ /* Update the transfer descriptor */\r
+ pTwid->pTransfer = pAsync;\r
+ pTransfer = (struct _async_twi*) pAsync;\r
+ pTransfer->status = ASYNC_STATUS_PENDING;\r
+ pTransfer->pData = pData;\r
+ pTransfer->num = num;\r
+ pTransfer->transferred = 0;\r
+\r
+ /* Enable read interrupt and start the transfer */\r
+ twi_enable_it(pTwi, TWI_IER_RXRDY);\r
+ twi_start_read(pTwi, address, iaddress, isize);\r
+ }\r
+ /* Synchronous transfer */\r
+ else {\r
+\r
+ /* Start read */\r
+ twi_start_read(pTwi, address, iaddress, isize);\r
+ if (num != 1) {\r
+ status = twi_get_status(pTwi);\r
+\r
+ if (status & TWI_SR_NACK)\r
+ trace_error("TWID NACK error\n\r");\r
+ timeout = 0;\r
+ while (!(status & TWI_SR_RXRDY)\r
+ && (++timeout < TWITIMEOUTMAX)) {\r
+ status = twi_get_status(pTwi);\r
+ //trace_error("TWID status %x\n\r",twi_get_status(pTwi));\r
+ }\r
+\r
+ pData[0] = twi_read_byte(pTwi);\r
+ for (i = 1; i < num - 1; i++) {\r
+ status = twi_get_status(pTwi);\r
+ if (status & TWI_SR_NACK)\r
+ trace_error("TWID NACK error\n\r");\r
+ timeout = 0;\r
+ while (!(status & TWI_SR_RXRDY)\r
+ && (++timeout < TWITIMEOUTMAX)) {\r
+ status = twi_get_status(pTwi);\r
+ //trace_error("TWID status %x\n\r",twi_get_status(pTwi));\r
+ }\r
+ pData[i] = twi_read_byte(pTwi);\r
+ }\r
+ }\r
+ twi_stop(pTwi);\r
+ status = twi_get_status(pTwi);\r
+ if (status & TWI_SR_NACK)\r
+ trace_error("TWID NACK error\n\r");\r
+ timeout = 0;\r
+ while (!(status & TWI_SR_RXRDY) && (++timeout < TWITIMEOUTMAX)) {\r
+ status = twi_get_status(pTwi);\r
+ //trace_error("TWID status %x\n\r",twi_get_status(pTwi));\r
+ }\r
+\r
+ pData[i] = twi_read_byte(pTwi);\r
+ timeout = 0;\r
+ status = twi_get_status(pTwi);\r
+ while (!(status & TWI_SR_TXCOMP) && (++timeout < TWITIMEOUTMAX)) {\r
+ status = twi_get_status(pTwi);\r
+ //trace_error("TWID status %x\n\r",twi_get_status(pTwi));\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Asynchronously reads data from a slave on the TWI bus. An optional\r
+ * callback function is triggered when the transfer is complete.\r
+ * \param pTwid Pointer to a Twid instance.\r
+ * \param address TWI slave address.\r
+ * \param iaddress Optional slave internal address.\r
+ * \param isize Internal address size in bytes.\r
+ * \param pData Data buffer for storing received bytes.\r
+ * \param num Number of bytes to read.\r
+ * \param pAsync Asynchronous transfer descriptor.\r
+ * \param twi_id TWI ID for TWI0, TWI1, TWI2.\r
+ * \return 0 if the transfer has been started; otherwise returns a TWI error code.\r
+ */\r
+uint8_t twid_dma_read(struct _twid* pTwid, uint8_t address, uint32_t iaddress,\r
+ uint8_t isize, uint8_t * pData, uint32_t num, struct _async * pAsync, uint8_t twi_id)\r
+{\r
+ Twi *pTwi;\r
+ struct _async_twi* pTransfer;\r
+ uint32_t timeout = 0;\r
+ uint32_t status;\r
+\r
+ assert(pTwid != NULL);\r
+ pTwi = pTwid->pTwi;\r
+ pTransfer = (struct _async_twi*) pTwid->pTransfer;\r
+\r
+ assert((address & 0x80) == 0);\r
+ assert((iaddress & 0xFF000000) == 0);\r
+ assert(isize < 4);\r
+\r
+ /* Check that no transfer is already pending */\r
+ if (pTransfer) {\r
+\r
+ trace_error("twid_read: A transfer is already pending\n\r");\r
+ return TWID_ERROR_BUSY;\r
+ }\r
+\r
+ /* Asynchronous transfer */\r
+ if (pAsync) {\r
+\r
+ /* Update the transfer descriptor */\r
+ pTwid->pTransfer = pAsync;\r
+ pTransfer = (struct _async_twi*) pAsync;\r
+ pTransfer->status = ASYNC_STATUS_PENDING;\r
+ pTransfer->pData = pData;\r
+ pTransfer->num = num;\r
+ pTransfer->transferred = 0;\r
+\r
+ /* Enable read interrupt and start the transfer */\r
+ twi_enable_it(pTwi, TWI_IER_RXRDY);\r
+ twi_start_read(pTwi, address, iaddress, isize);\r
+ }\r
+ /* Synchronous transfer */\r
+ else {\r
+\r
+ twid_dma_initialize_read(twi_id);\r
+ _xdma_configure_read(pData, num, twi_id);\r
+ /* Start read */\r
+ xdmad_start_transfer(dmaReadChannel);\r
+\r
+ twi_start_read(pTwi, address, iaddress, isize);\r
+\r
+ while ((!xdmad_is_transfer_done(dmaReadChannel))\r
+ && (++timeout < TWITIMEOUTMAX))\r
+ xdmad_poll();\r
+\r
+ xdmad_stop_transfer(dmaReadChannel);\r
+\r
+ status = twi_get_status(pTwi);\r
+ timeout = 0;\r
+ while (!(status & TWI_SR_RXRDY)\r
+ && (++timeout < TWITIMEOUTMAX)) ;\r
+\r
+ twi_stop(pTwi);\r
+\r
+ twi_read_byte(pTwi);\r
+\r
+ status = twi_get_status(pTwi);\r
+ timeout = 0;\r
+ while (!(status & TWI_SR_RXRDY)\r
+ && (++timeout < TWITIMEOUTMAX)) ;\r
+\r
+ twi_read_byte(pTwi);\r
+\r
+ status = twi_get_status(pTwi);\r
+ timeout = 0;\r
+ while (!(status & TWI_SR_TXCOMP)\r
+ && (++timeout < TWITIMEOUTMAX)) ;\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ trace_error("TWID Timeout Read\n\r");\r
+ }\r
+ xdmad_free_channel(dmaReadChannel);\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Asynchronously sends data to a slave on the TWI bus. An optional callback\r
+ * function is invoked whenever the transfer is complete.\r
+ * \param pTwid Pointer to a Twid instance.\r
+ * \param address TWI slave address.\r
+ * \param iaddress Optional slave internal address.\r
+ * \param isize Number of internal address bytes.\r
+ * \param pData Data buffer for storing received bytes.\r
+ * \param num Data buffer to send.\r
+ * \param pAsync Asynchronous transfer descriptor.\r
+ * \param twi_id TWI ID for TWI0, TWI1, TWI2.\r
+ * \return 0 if the transfer has been started; otherwise returns a TWI error code.\r
+ */\r
+uint8_t twid_dma_write(struct _twid* pTwid, uint8_t address, uint32_t iaddress,\r
+ uint8_t isize, uint8_t * pData, uint32_t num, struct _async * pAsync, uint8_t twi_id)\r
+{\r
+ Twi *pTwi = pTwid->pTwi;\r
+ struct _async_twi* pTransfer;\r
+ uint32_t timeout = 0;\r
+ uint32_t status;\r
+ //uint8_t singleTransfer = 0;\r
+\r
+ assert(pTwi != NULL);\r
+ assert((address & 0x80) == 0);\r
+ assert((iaddress & 0xFF000000) == 0);\r
+ assert(isize < 4);\r
+\r
+ pTransfer = (struct _async_twi *) pTwid->pTransfer;\r
+// if(num == 1) singleTransfer = 1;\r
+ /* Check that no transfer is already pending */\r
+ if (pTransfer) {\r
+ trace_error("TWI_Write: A transfer is already pending\n\r");\r
+ return TWID_ERROR_BUSY;\r
+ }\r
+\r
+ /* Asynchronous transfer */\r
+ if (pAsync) {\r
+ /* Update the transfer descriptor */\r
+ pTwid->pTransfer = pAsync;\r
+ pTransfer = (struct _async_twi*) pAsync;\r
+ pTransfer->status = ASYNC_STATUS_PENDING;\r
+ pTransfer->pData = pData;\r
+ pTransfer->num = num;\r
+ pTransfer->transferred = 1;\r
+ /* Enable write interrupt and start the transfer */\r
+ twi_start_write(pTwi, address, iaddress, isize, *pData);\r
+ twi_enable_it(pTwi, TWI_IER_TXRDY);\r
+ }\r
+ /* Synchronous transfer */\r
+ else {\r
+ cp15_coherent_dcache_for_dma((uint32_t) pData, (uint32_t) pData);\r
+ twid_dma_initialize_write(twi_id);\r
+ _xdma_configure_write(pData, num, twi_id);\r
+ /* Set slave address and number of internal address bytes. */\r
+ pTwi->TWI_MMR = 0;\r
+ pTwi->TWI_MMR = (isize << 8) | (address << 16);\r
+ /* Set internal address bytes. */\r
+ pTwi->TWI_IADR = 0;\r
+ pTwi->TWI_IADR = iaddress;\r
+ xdmad_start_transfer(dmaWriteChannel);\r
+ while (!xdmad_is_transfer_done(dmaWriteChannel))\r
+ xdmad_poll();\r
+ xdmad_stop_transfer(dmaWriteChannel);\r
+ status = twi_get_status(pTwi);\r
+ timeout = 0;\r
+ while (!(status & TWI_SR_TXRDY) && (timeout++ < TWITIMEOUTMAX)) {\r
+ status = twi_get_status(pTwi);\r
+ }\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ trace_error("TWID Timeout TXRDY\n\r");\r
+ }\r
+ /* Send a STOP condition */\r
+ twi_stop(pTwi);\r
+ status = twi_get_status(pTwi);\r
+ timeout = 0;\r
+ while (!(status & TWI_SR_TXCOMP) && (++timeout < TWITIMEOUTMAX)) {\r
+ status = twi_get_status(pTwi);\r
+ }\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ trace_error("TWID Timeout Write\n\r");\r
+ }\r
+ cp15_invalidate_dcache_for_dma((uint32_t) pData, (uint32_t) (pData));\r
+ xdmad_free_channel(dmaWriteChannel);\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Asynchronously sends data to a slave on the TWI bus. An optional callback\r
+ * function is invoked whenever the transfer is complete.\r
+ * \param pTwid Pointer to a Twid instance.\r
+ * \param address TWI slave address.\r
+ * \param iaddress Optional slave internal address.\r
+ * \param isize Number of internal address bytes.\r
+ * \param pData Data buffer for storing received bytes.\r
+ * \param num Data buffer to send.\r
+ * \param pAsync Asynchronous transfer descriptor.\r
+ * \return 0 if the transfer has been started; otherwise returns a TWI error code.\r
+ */\r
+uint8_t twid_write(struct _twid* pTwid, uint8_t address, uint32_t iaddress,\r
+ uint8_t isize, uint8_t * pData, uint32_t num, struct _async * pAsync)\r
+{\r
+ Twi *pTwi = pTwid->pTwi;\r
+ struct _async_twi* pTransfer;\r
+ uint32_t timeout = 0;\r
+ uint32_t status;\r
+ uint8_t singleTransfer = 0;\r
+\r
+ assert(pTwi != NULL);\r
+ assert((address & 0x80) == 0);\r
+ assert((iaddress & 0xFF000000) == 0);\r
+ assert(isize < 4);\r
+\r
+ pTransfer = (struct _async_twi *) pTwid->pTransfer;\r
+ if (num == 1)\r
+ singleTransfer = 1;\r
+ /* Check that no transfer is already pending */\r
+ if (pTransfer) {\r
+ trace_error("TWI_Write: A transfer is already pending\n\r");\r
+ return TWID_ERROR_BUSY;\r
+ }\r
+ /* Asynchronous transfer */\r
+ if (pAsync) {\r
+ /* Update the transfer descriptor */\r
+ pTwid->pTransfer = pAsync;\r
+ pTransfer = (struct _async_twi*) pAsync;\r
+ pTransfer->status = ASYNC_STATUS_PENDING;\r
+ pTransfer->pData = pData;\r
+ pTransfer->num = num;\r
+ pTransfer->transferred = 1;\r
+ /* Enable write interrupt and start the transfer */\r
+ twi_start_write(pTwi, address, iaddress, isize, *pData);\r
+ twi_enable_it(pTwi, TWI_IER_TXRDY);\r
+ }\r
+ /* Synchronous transfer */\r
+ else {\r
+ // Start write\r
+ twi_start_write(pTwi, address, iaddress, isize, *pData++);\r
+ num--;\r
+ if (singleTransfer) {\r
+ /* Send a STOP condition */\r
+ twi_send_stop_condition(pTwi);\r
+ }\r
+ status = twi_get_status(pTwi);\r
+ if (status & TWI_SR_NACK)\r
+ trace_error("TWID NACK error\n\r");\r
+ while (!(status & TWI_SR_TXRDY) && (timeout++ < TWITIMEOUTMAX)) {\r
+ status = twi_get_status(pTwi);\r
+ }\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ trace_error("TWID Timeout BS\n\r");\r
+ }\r
+ timeout = 0;\r
+ /* Send all bytes */\r
+ while (num > 0) {\r
+ /* Wait before sending the next byte */\r
+ timeout = 0;\r
+ twi_write_byte(pTwi, *pData++);\r
+ status = twi_get_status(pTwi);\r
+ if (status & TWI_SR_NACK)\r
+ trace_error("TWID NACK error\n\r");\r
+ while (!(status & TWI_SR_TXRDY)\r
+ && (timeout++ < TWITIMEOUTMAX)) {\r
+ status = twi_get_status(pTwi);\r
+ }\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ trace_error("TWID Timeout BS\n\r");\r
+ }\r
+ num--;\r
+ }\r
+ /* Wait for actual end of transfer */\r
+ timeout = 0;\r
+ if (!singleTransfer) {\r
+ /* Send a STOP condition */\r
+ twi_send_stop_condition(pTwi);\r
+ }\r
+ while (!twi_is_transfer_complete(pTwi)\r
+ && (++timeout < TWITIMEOUTMAX)) ;\r
+ if (timeout == TWITIMEOUTMAX) {\r
+ trace_error("TWID Timeout TC2\n\r");\r
+ }\r
+ }\r
+ return 0;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _TWID_\r
+#define _TWID_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "peripherals/twi.h"\r
+#include "async.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definition\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** TWI driver is currently busy. */\r
+#define TWID_ERROR_BUSY 1\r
+\r
+// TWI clock frequency in Hz.\r
+#define TWCK_400K 400000\r
+#define TWCK_200K 200000\r
+#define TWCK_100K 100000\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \brief TWI driver structure. Holds the internal state of the driver.*/\r
+struct _twid {\r
+ Twi *pTwi; /** Pointer to the underlying TWI peripheral.*/\r
+ struct _async *pTransfer; /** Current asynchronous transfer being processed.*/\r
+};\r
+\r
+struct _handler_twi\r
+{\r
+ uint8_t IdTwi; // ID TWI\r
+ uint8_t Status; // status of the TWI\r
+ uint8_t PeriphAddr; // Address of the component\r
+ uint8_t LenData; // Lenfth of the data to be read or write\r
+ uint8_t AddSize; // Size of the address\r
+ uint16_t RegMemAddr; // Address of the memory or register\r
+ uint32_t Twck; // default clock of the bus TWI\r
+ uint8_t* pData; // pointer to a data buffer\r
+ struct _twid twid;\r
+};\r
+\r
+\r
+enum TWI_CMD\r
+{\r
+ TWI_RD = 0,\r
+ TWI_WR = 1\r
+};\r
+\r
+enum TWI_STATUS\r
+{\r
+ TWI_STATUS_RESET = 0,\r
+ TWI_STATUS_HANDLE = 1u<<0,\r
+ TWI_STATUS_RFU2 = 1u<<1,\r
+ TWI_STATUS_RFU3 = 1u<<2,\r
+ TWI_STATUS_RFU4 = 1u<<3,\r
+ TWI_STATUS_READY = 1u<<7,\r
+};\r
+\r
+enum TWI_RESULT\r
+{\r
+ TWI_SUCCES = 0,\r
+ TWI_FAIL = 1\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Export functions\r
+ *----------------------------------------------------------------------------*/\r
+extern void twid_initialize(struct _twid* pTwid, Twi * pTwi);\r
+\r
+extern void twid_handler(struct _twid* pTwid);\r
+\r
+extern uint8_t twid_read(struct _twid* pTwid, uint8_t address, uint32_t iaddress,\r
+ uint8_t isize, uint8_t * pData, uint32_t num, struct _async * pAsync);\r
+\r
+extern uint8_t twid_dma_read(struct _twid* pTwid, uint8_t address, uint32_t iaddress,\r
+ uint8_t isize, uint8_t * pData, uint32_t num,\r
+ struct _async * pAsync, uint8_t TWI_ID);\r
+\r
+extern uint8_t twid_write(struct _twid* pTwid, uint8_t address, uint32_t iaddress,\r
+ uint8_t isize, uint8_t * pData, uint32_t num, struct _async * pAsync);\r
+\r
+extern uint8_t twid_dma_write(struct _twid* pTwid, uint8_t address,\r
+ uint32_t iaddress, uint8_t isize, uint8_t * pData,\r
+ uint32_t num, struct _async * pAsync, uint8_t TWI_ID);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif //#ifndef TWID_H\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/uart.h"\r
+#include "peripherals/pmc.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/*\r
+ * Initializes the UART with the given parameters, and enables both the\r
+ * transmitter and the receiver. The mode parameter contains the value of the\r
+ * UART_MR register.\r
+ * Value UART_STANDARD can be used for mode to get the most common configuration\r
+ * (i.e. aysnchronous, 8bits, no parity, 1 stop bit, no flow control).\r
+ * \param mode Operating mode to configure.\r
+ * \param baudrate Desired baudrate (e.g. 115200).\r
+ * \param mck Frequency of the system master clock in Hz.\r
+ */\r
+void uart_configure(Uart* pUart, uint32_t mode, uint32_t baudrate)\r
+{\r
+ uint32_t uart_id = get_uart_id_from_addr(pUart);\r
+ // Reset & disable receiver and transmitter, disable interrupts\r
+ pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS\r
+ | UART_CR_RSTSTA;\r
+ pUart->UART_IDR = 0xFFFFFFFF;\r
+ // Configure baud rate\r
+ pUart->UART_BRGR = pmc_get_peripheral_clock(uart_id) / (baudrate * 16);\r
+ // Configure mode register\r
+ pUart->UART_MR = mode;\r
+ // Enable receiver and transmitter\r
+ pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;\r
+}\r
+\r
+/* Enable transmitter\r
+ *\r
+ */\r
+void uart_set_transmitter_enabled (Uart* pUart, uint8_t enabled)\r
+{\r
+ if (enabled) pUart->UART_CR = UART_CR_TXEN;\r
+ else pUart->UART_CR = UART_CR_TXDIS;\r
+}\r
+\r
+/* Enable receiver\r
+ *\r
+ */\r
+void uart_set_receiver_enabled (Uart* pUart, uint8_t enabled)\r
+{\r
+ if (enabled)\r
+ pUart->UART_CR = UART_CR_RXEN;\r
+ else\r
+ pUart->UART_CR = UART_CR_RXDIS;\r
+}\r
+\r
+/* Set interrupt register\r
+ *\r
+ */\r
+void uart_set_int (Uart* pUart, uint32_t int_mask)\r
+{\r
+ pUart->UART_IER |= int_mask;\r
+}\r
+\r
+/**\r
+ * Outputs a character on the UART line.\r
+ * \note This function is synchronous (i.e. uses polling).\r
+ * \param c Character to send.\r
+ */\r
+void uart_put_char(Uart* pUart, uint8_t c)\r
+{\r
+ // Wait for the transmitter to be ready\r
+ while ((pUart->UART_SR & UART_SR_TXEMPTY) == 0);\r
+ // Send character\r
+ pUart->UART_THR = c;\r
+}\r
+\r
+/**\r
+ * Return 1 if a character can be read in UART\r
+ */\r
+uint32_t uart_is_rx_ready(Uart* pUart)\r
+{\r
+ return (pUart->UART_SR & UART_SR_RXRDY);\r
+}\r
+\r
+/**\r
+ * Return 1 if a character can be write in UART\r
+ */\r
+uint32_t uart_is_tx_ready(Uart* pUart)\r
+{\r
+ return (pUart->UART_SR & UART_SR_TXRDY);\r
+}\r
+\r
+/**\r
+ * \brief Reads and returns a character from the UART.\r
+ * \note This function is synchronous (i.e. uses polling).\r
+ * \return Character received.\r
+ */\r
+uint8_t uart_get_char(Uart* pUart)\r
+{\r
+ while ((pUart->UART_SR & UART_SR_RXRDY) == 0);\r
+ return pUart->UART_RHR;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * This module provides several definitions and methods for using an UART\r
+ * peripheral.\r
+ *\r
+ */\r
+\r
+#ifndef UART_H\r
+#define UART_H\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+extern void uart_configure(Uart* puart, uint32_t mode, uint32_t baudrate);\r
+extern void uart_set_transmitter_enabled(Uart* puart, uint8_t enabled);\r
+extern void uart_set_receiver_enabled (Uart* puart, uint8_t enabled);\r
+extern void uart_set_int (Uart* puart, uint32_t int_mask);\r
+extern void uart_put_char(Uart* puart, uint8_t c);\r
+extern uint32_t uart_is_rx_ready(Uart* puart);\r
+extern uint32_t uart_is_tx_ready(Uart* puart);\r
+extern uint8_t uart_get_char(Uart* puart);\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+#endif //#ifndef UART_H\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup usart_module Working with USART\r
+ * \section Purpose\r
+ * The USART driver provides the interface to configure and use the USART peripheral.\n\r
+ *\r
+ * The USART supports several kinds of communication modes such as full-duplex asynchronous/\r
+ * synchronous serial communication,RS485 with driver control signal,ISO7816,SPI and Test modes.\r
+ *\r
+ * To start a USART transfer with \ref dmad_module "DMA" support, the user could follow these steps:\r
+ * <ul>\r
+ * <li> Configure USART with expected mode and baudrate(see \ref usart_configure), which could be done by:\r
+ * -# Resetting and disabling transmitter and receiver by setting US_CR(Control Register). </li>\r
+ * -# Configuring the USART in a specific mode by setting USART_MODE bits in US_MR(Mode Register) </li>\r
+ * -# Setting baudrate which is different from mode to mode.\r
+ </li>\r
+ * <li> Enable transmitter or receiver respectively by set US_CR_TXEN or US_CR_RXEN in US_CR.</li>\r
+ * <li> Read from or write to the peripheral with \ref dmad_module </li>\r
+ * </ul>\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Enable or disable USART transmitter or receiver using\r
+ * usart_set_transmitter_enabled() and usart_set_receiver_enabled().\r
+ * <li> Enable or disable USART interrupt using usart_enable_it() or usart_disable_it().\r
+ * </li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the USART section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref usart.c\n\r
+ * \ref usart.h\n\r
+*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of USART (Universal Synchronous Asynchronous Receiver Transmitter)\r
+ * controller.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------\r
+* Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "compiler.h"\r
+#include "peripherals/usart.h"\r
+#include "peripherals/pmc.h"\r
+\r
+#include "trace.h"\r
+#include "io.h"\r
+\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+/*-----------------------------------------------------------------------------\r
+*\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#ifdef CONFIG_HAVE_USART_FIFO\r
+/* Clear FIFO related register if present. Dummy function otherwise. */\r
+static inline void _clear_fifo_control_flags(uint32_t* control_reg)\r
+{\r
+ *control_reg |= US_CR_FIFODIS | US_CR_TXFCLR | US_CR_RXFCLR | US_CR_TXFLCLR;\r
+}\r
+#else\r
+#define _clear_fifo_control_flags(dummy) do {} while(0)\r
+#endif\r
+\r
+/* The CD value scope programmed in MR register. */\r
+#define MIN_CD_VALUE 0x01\r
+#define MIN_CD_VALUE_SPI 0x04\r
+#define MAX_CD_VALUE US_BRGR_CD_Msk\r
+\r
+/* The receiver sampling divide of baudrate clock. */\r
+#define HIGH_FRQ_SAMPLE_DIV 16\r
+#define LOW_FRQ_SAMPLE_DIV 8\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR).\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_status(Usart *usart)\r
+{\r
+ usart->US_CR = US_CR_RSTSTA;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Configures an USART peripheral with the specified parameters.\r
+ * \param usart Pointer to the USART peripheral to configure.\r
+ * \param mode Desired value for the USART mode register (see the datasheet).\r
+ * \param baudrate Baudrate at which the USART should operate (in Hz).\r
+ * \param clock Frequency of the system master clock (in Hz).\r
+ */\r
+void usart_configure(Usart *usart, uint32_t mode, uint32_t baudrate)\r
+{\r
+ uint32_t clock = pmc_get_peripheral_clock(get_usart_id_from_addr(usart));\r
+ /* Reset and disable receiver & transmitter */\r
+ uint32_t control = US_CR_RSTRX | US_CR_RSTTX | US_CR_RXDIS | US_CR_TXDIS;\r
+ /* Reset and disable FIFO if present */\r
+ _clear_fifo_control_flags(&control);\r
+ /* apply */\r
+ usart->US_CR = control;\r
+ /* Configure mode */\r
+ usart->US_MR = mode;\r
+\r
+ /* Configure baudrate */\r
+ /* Asynchronous, no oversampling */\r
+ if (((mode & US_MR_SYNC) == 0) && ((mode & US_MR_OVER) == 0)) {\r
+ usart->US_BRGR = (clock / baudrate) / 16;\r
+ }\r
+#ifdef CONFIG_HAVE_USART_SPI_MODE\r
+ if (((mode & US_MR_USART_MODE_SPI_MASTER) ==\r
+ US_MR_USART_MODE_SPI_MASTER) || ((mode & US_MR_SYNC) == US_MR_SYNC)) {\r
+ if ((mode & US_MR_USCLKS_Msk) == US_MR_USCLKS_MCK) {\r
+ usart->US_BRGR = clock / baudrate;\r
+ } else {\r
+ if ((mode & US_MR_USCLKS_DIV) == US_MR_USCLKS_DIV) {\r
+ usart->US_BRGR = clock / baudrate / 8;\r
+ }\r
+ }\r
+ }\r
+#endif /* CONFIG_HAVE_USART_SPI_MODE */\r
+\r
+ /* TODO other modes */\r
+\r
+ /* Disable all interrupts */\r
+ usart->US_IDR = 0xFFFFFFFF;\r
+ /* Enable receiver and transmitter */\r
+ usart->US_CR = US_CR_RXEN | US_CR_TXEN;\r
+}\r
+\r
+/**\r
+ * \brief Get present status\r
+ * \param usart Pointer to an USART peripheral.\r
+ */\r
+uint32_t usart_get_status(Usart *usart)\r
+{\r
+ return usart->US_CSR;\r
+}\r
+\r
+/**\r
+ * \brief Enable interrupt\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \param mode Interrupt mode.\r
+ */\r
+void usart_enable_it(Usart *usart, uint32_t mode)\r
+{\r
+ usart->US_IER = mode;\r
+}\r
+\r
+/**\r
+ * \brief Disable interrupt\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \param mode Interrupt mode.\r
+ */\r
+void usart_disable_it(Usart *usart, uint32_t mode)\r
+{\r
+ usart->US_IDR = mode;\r
+}\r
+\r
+/**\r
+ * \brief Return interrupt mask\r
+ * \param usart Pointer to an USART peripheral.\r
+ */\r
+uint32_t usart_get_it_mask(Usart *usart)\r
+{\r
+ return usart->US_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Enables or disables the transmitter of an USART peripheral.\r
+ * \param usart Pointer to an USART peripheral\r
+ * \param enabled If true, the transmitter is enabled; otherwise it is\r
+ * disabled.\r
+ */\r
+void usart_set_transmitter_enabled(Usart *usart, uint8_t enabled)\r
+{\r
+ if (enabled) {\r
+ usart->US_CR = US_CR_TXEN;\r
+ } else {\r
+ usart->US_CR = US_CR_TXDIS;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enables or disables the receiver of an USART peripheral\r
+ * \param usart Pointer to an USART peripheral\r
+ * \param enabled If true, the receiver is enabled; otherwise it is disabled.\r
+ */\r
+void usart_set_receiver_enabled(Usart *usart, uint8_t enabled)\r
+{\r
+ if (enabled) {\r
+ usart->US_CR = US_CR_RXEN;\r
+ } else {\r
+ usart->US_CR = US_CR_RXDIS;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enables or disables the Request To Send (RTS) of an USART peripheral\r
+ * \param usart Pointer to an USART peripheral\r
+ * \param enabled If true, the RTS is enabled (0); otherwise it is disabled.\r
+ */\r
+void usart_set_rts_enabled(Usart *usart, uint8_t enabled)\r
+{\r
+ if (enabled) {\r
+ usart->US_CR = US_CR_RTSEN;\r
+ } else {\r
+ usart->US_CR = US_CR_RTSDIS;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Immediately stop and disable USART transmitter.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_tx(Usart *usart)\r
+{\r
+ /* Reset transmitter */\r
+ usart->US_CR = US_CR_RSTTX | US_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the transmit timeguard register.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ * \param timeguard The value of transmit timeguard.\r
+ */\r
+void usart_set_tx_timeguard(Usart *usart, uint32_t timeguard)\r
+{\r
+ usart->US_TTGR = timeguard;\r
+}\r
+\r
+/**\r
+ * \brief Immediately stop and disable USART receiver.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_rx(Usart *usart)\r
+{\r
+ /* Reset Receiver */\r
+ usart->US_CR = US_CR_RSTRX | US_CR_RXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the receive timeout register.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ * \param timeout The value of receive timeout.\r
+ */\r
+void usart_set_rx_timeout(Usart *usart, uint32_t timeout)\r
+{\r
+ usart->US_RTOR = timeout;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Start transmission of a break.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_start_tx_break(Usart *usart)\r
+{\r
+ usart->US_CR = US_CR_STTBRK;\r
+}\r
+\r
+/**\r
+ * \brief Stop transmission of a break.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_stop_tx_break(Usart *usart)\r
+{\r
+ usart->US_CR = US_CR_STPBRK;\r
+}\r
+\r
+/**\r
+ * \brief Start waiting for a character before clocking the timeout count.\r
+ * Reset the status bit TIMEOUT in US_CSR.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_start_rx_timeout(Usart *usart)\r
+{\r
+ usart->US_CR = US_CR_STTTO;\r
+}\r
+\r
+/**\r
+ * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_iterations(Usart *usart)\r
+{\r
+ usart->US_CR = US_CR_RSTIT;\r
+}\r
+\r
+/**\r
+ * \brief Reset NACK in US_CSR.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_nack(Usart *usart)\r
+{\r
+ usart->US_CR = US_CR_RSTNACK;\r
+}\r
+\r
+/**\r
+ * \brief Restart the receive timeout.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_restart_rx_timeout(Usart *usart)\r
+{\r
+ usart->US_CR = US_CR_RETTO;\r
+}\r
+\r
+/**\r
+ * \brief Sends one packet of data through the specified USART peripheral. This\r
+ * function operates synchronously, so it only returns when the data has been\r
+ * actually sent.\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \param data Data to send including 9nth bit and sync field if necessary (in\r
+ * the same format as the US_THR register in the datasheet).\r
+ * \param timeout Time out value (0 = no timeout).\r
+ */\r
+void usart_write(Usart *usart, uint16_t data, volatile uint32_t timeout)\r
+{\r
+ if (timeout == 0) {\r
+ while ((usart->US_CSR & US_CSR_TXRDY) == 0) ;\r
+ } else {\r
+ while ((usart->US_CSR & US_CSR_TXRDY) == 0) {\r
+ if (timeout == 0) {\r
+ trace_error("usart_write: Timed out.\n\r");\r
+ return;\r
+ }\r
+ timeout--;\r
+ }\r
+ }\r
+ usart->US_THR = data;\r
+}\r
+\r
+/**\r
+ * \brief Reads and return a packet of data on the specified USART peripheral. This\r
+ * function operates asynchronously, so it waits until some data has been\r
+ * received.\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \param timeout Time out value (0 -> no timeout).\r
+ */\r
+uint16_t usart_read(Usart *usart, volatile uint32_t timeout)\r
+{\r
+ if (timeout == 0) {\r
+ while ((usart->US_CSR & US_CSR_RXRDY) == 0) ;\r
+ } else {\r
+ while ((usart->US_CSR & US_CSR_RXRDY) == 0) {\r
+ if (timeout == 0) {\r
+ trace_error("usart_read: Timed out.\n\r");\r
+ return 0;\r
+ }\r
+ timeout--;\r
+ }\r
+ }\r
+ return usart->US_RHR;\r
+}\r
+\r
+/**\r
+ * \brief Returns 1 if some data has been received and can be read from an USART;\r
+ * otherwise returns 0.\r
+ * \param usart Pointer to an USART instance.\r
+ */\r
+uint8_t usart_is_data_available(Usart *usart)\r
+{\r
+ if ((usart->US_CSR & US_CSR_RXRDY) != 0) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if a character can be read in USART\r
+ * \param usart Pointer to an USART peripheral.\r
+ */\r
+uint32_t usart_is_rx_ready(Usart *usart)\r
+{\r
+ return (usart->US_CSR & US_CSR_RXRDY);\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if a character send in USART\r
+ * \param usart Pointer to an USART peripheral.\r
+ */\r
+uint32_t usart_is_tx_ready(Usart *usart)\r
+{\r
+ return (usart->US_CSR & US_CSR_TXRDY);\r
+}\r
+\r
+/**\r
+ * \brief Sends one packet of data through the specified USART peripheral. This\r
+ * function operates synchronously, so it only returns when the data has been\r
+ * actually sent.\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \param c Character to send\r
+ */\r
+void usart_put_char(Usart *usart, uint8_t c)\r
+{\r
+ /* Wait for the transmitter to be ready */\r
+ while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) ;\r
+ /* Send character */\r
+ /* Force an octet write to avoid race conditions with FIFO mode */\r
+ writeb(&usart->US_THR, c);\r
+}\r
+\r
+/**\r
+ * \brief Reads and returns a character from the USART.\r
+ * \note This function is synchronous (i.e. uses polling).\r
+ * \param usart Pointer to an USART peripheral.\r
+ * \return Character received.\r
+ */\r
+uint8_t usart_get_char(Usart *usart)\r
+{\r
+ while ((usart->US_CSR & US_CSR_RXRDY) == 0) ;\r
+ /* Force an octet read to avoid race conditions with FIFO mode */\r
+ uint8_t v;\r
+ readb(&usart->US_RHR, &v);\r
+ return v;\r
+}\r
+\r
+/**\r
+ * \brief Sets the filter value for the IRDA demodulator.\r
+ * \param usart Pointer to an USART instance.\r
+ * \param filter Filter value.\r
+ */\r
+void usart_set_irda_filter(Usart *usart, uint8_t filter)\r
+{\r
+ assert(usart != NULL);\r
+\r
+ usart->US_IF = filter;\r
+ /* Set IrDA mode. */\r
+ usart->US_MR = (usart->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_IRDA;\r
+}\r
+\r
+/**\r
+ * \brief Select the SCK pin as the source of baud rate for the USART\r
+ * synchronous slave modes.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_set_sync_slave_baudrate(Usart *usart)\r
+{\r
+ usart->US_MR = (usart->US_MR & ~US_MR_USCLKS_Msk) | US_MR_USCLKS_SCK | US_MR_SYNC;\r
+}\r
+\r
+/**\r
+ * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to\r
+ * generate a baud rate as close as possible to the baud rate set point.\r
+ *\r
+ * \note Baud rate calculation:\r
+ * \f$ Baudrate = \frac{SelectedClock}{CD} \f$.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock\r
+ * frequency.\r
+ */\r
+uint32_t usart_set_spi_master_baudrate(Usart *usart, uint32_t baudrate)\r
+{\r
+ uint32_t cd;\r
+ uint32_t clock = pmc_get_peripheral_clock(get_usart_id_from_addr(usart));\r
+\r
+ /* Calculate the clock divider according to the formula in SPI mode. */\r
+ cd = (clock + baudrate / 2) / baudrate;\r
+ if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+ usart->US_BRGR = cd << US_BRGR_CD_Pos;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Select the SCK pin as the source of baudrate for the USART SPI slave\r
+ * mode.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_set_spi_slave_baudrate(Usart *usart)\r
+{\r
+ usart->US_MR &= ~US_MR_USCLKS_Msk;\r
+ usart->US_MR |= US_MR_USCLKS_SCK;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in hardware handshaking mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_hw_handshaking(Usart *usart)\r
+{\r
+ /* The USART should be initialized first as standard RS232. */\r
+ /* Set hardware handshaking mode. */\r
+ usart->US_MR = (usart->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_HW_HANDSHAKING;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Calculate a clock divider(CD) and a fractional part (FP) for the\r
+ * USART asynchronous modes to generate a baudrate as close as possible to\r
+ * the baudrate set point.\r
+ *\r
+ * \note Baud rate calculation: Baudrate = mck/(Over * (CD + FP/8))\r
+ * (Over being 16 or 8). The maximal oversampling is selected if it allows to\r
+ * generate a baudrate close to the set point.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock\r
+ * frequency.\r
+ */\r
+uint32_t usart_set_async_baudrate(Usart *usart, uint32_t baudrate)\r
+{\r
+ uint32_t over, cd_fp, cd, fp;\r
+ uint32_t mck;\r
+\r
+ /* get peripheral clock */\r
+ mck = pmc_get_peripheral_clock(get_usart_id_from_addr(usart));\r
+\r
+ /* Calculate the receiver sampling divide of baudrate clock. */\r
+ if (mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) {\r
+ over = HIGH_FRQ_SAMPLE_DIV;\r
+ } else {\r
+ over = LOW_FRQ_SAMPLE_DIV;\r
+ }\r
+\r
+ /* Calculate clock divider according to the fraction calculated formula. */\r
+ cd_fp = (8 * mck + (over * baudrate) / 2) / (over * baudrate);\r
+ cd = cd_fp >> 0x03;\r
+ fp = cd_fp & 0x07;\r
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the OVER bit in MR register. */\r
+ if (over == 8) {\r
+ usart->US_MR |= US_MR_OVER;\r
+ }\r
+\r
+ /* Configure the baudrate generate register. */\r
+ usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos);\r
+\r
+ return 0;\r
+}\r
+\r
+/*-----------------------------------------------------------------------------\r
+* Functions if FIFO are used\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#ifdef CONFIG_HAVE_USART_FIFO\r
+/**\r
+ * \brief Configure the FIFO of USART device\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \param tx_thres\r
+ * \param rx_down_thres\r
+ * \param rx_up_thres\r
+ * \param ready_modes\r
+ */\r
+void usart_fifo_configure(Usart *usart, uint8_t tx_thres,\r
+ uint8_t rx_down_thres, uint8_t rx_up_thres,\r
+ uint32_t ready_modes)\r
+{\r
+ /* Disable transmitter & receiver */\r
+ usart->US_CR = US_CR_RXDIS | US_CR_TXDIS;\r
+ /* Enable FIFO */\r
+ usart->US_CR = US_CR_FIFOEN;\r
+ /* Configure FIFO */\r
+ usart->US_FMR = US_FMR_TXFTHRES(tx_thres) | US_FMR_RXFTHRES(rx_down_thres)\r
+ | US_FMR_RXFTHRES2(rx_up_thres) | ready_modes;\r
+\r
+ /* Disable all fifo related interrupts */\r
+ usart->US_FIDR = 0xFFFFFFFF;\r
+\r
+ /* Reenable receiver & transmitter */\r
+ usart->US_CR = US_CR_RXEN | US_CR_TXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable the FIFO mode from the USART device\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \note receiver and transmitter are reenabled.\r
+ */\r
+void usart_fifo_disable(Usart *usart)\r
+{\r
+ /* Reset and disable receiver & transmitter */\r
+ uint32_t control = US_CR_RSTRX | US_CR_RSTTX | US_CR_RXDIS | US_CR_TXDIS;\r
+ /* clear and disable FIFO */\r
+ _clear_fifo_control_flags(&control);\r
+ /* apply */\r
+ usart->US_CR = control;\r
+\r
+ /* Reenable receiver & transmitter */\r
+ usart->US_CR = US_CR_RXEN | US_CR_TXEN;\r
+}\r
+\r
+/**\r
+ * \brief Enable FIFO related interrupts according to the given mask\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \param interrupt_mask The mask to apply\r
+ */\r
+void usart_fifo_enable_it(Usart *usart, uint32_t interrupt_mask)\r
+{\r
+ usart->US_FIER = interrupt_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable FIFO related interrupts according to the given mask\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \param interrupt_mask The mask to apply\r
+ */\r
+void usart_fifo_disable_it(Usart *usart, uint32_t interrupt_mask)\r
+{\r
+ usart->US_FIDR = interrupt_mask;\r
+}\r
+\r
+/**\r
+ * \brief Retrive FIFO related interrupt mask.\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \return current FIFO interrupt mask.\r
+ */\r
+uint32_t usart_fifo_get_interrupts(Usart *usart)\r
+{\r
+ return usart->US_FIMR;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Get the size occupied in the input FIFO of USART device.\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \return Size occupied in the input FIFO (not read yet) in octet\r
+ */\r
+uint32_t usart_fifo_rx_size(Usart *usart)\r
+{\r
+ return (usart->US_FLR & US_FLR_RXFL_Msk) >> US_FLR_RXFL_Pos;\r
+}\r
+\r
+/**\r
+ * \brief Get the size occupied in the ouput FIFO of USART device.\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \return Size occupied in the output FIFO (not sent yet) in octet\r
+ */\r
+uint32_t usart_fifo_tx_size(Usart *usart)\r
+{\r
+ return (usart->US_FLR & US_FLR_TXFL_Msk) >> US_FLR_TXFL_Pos;\r
+}\r
+\r
+/**\r
+ * \brief Reads from USART device input channel until the specified length is\r
+ * reached.\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \param stream Pointer to the receive buffer.\r
+ * \param len Size of the receive buffer, in octets.\r
+ *\r
+ * \return Number of read octets\r
+ *\r
+ * \warning WORKS ONLY IN LITTLE ENDIAN MODE!\r
+ *\r
+ * \note The FIFO must be configured before using this function.\r
+ * \note In case of a TIMEOUT or a BREAK, a null character is appended to the\r
+ * buffer and the returned value should be inferior to \ref len.\r
+ */\r
+uint32_t usart_read_stream(Usart *usart, void *stream, uint32_t len)\r
+{\r
+ uint8_t* buffer = stream;\r
+ uint32_t left = len;\r
+ while (left > 0) {\r
+ /* Stop reception if a timeout or break occur */\r
+ if ((usart->US_CSR & (US_CSR_TIMEOUT | US_CSR_RXBRK)) != 0) {\r
+ *buffer = '\0';\r
+ break;\r
+ }\r
+\r
+ if ((usart->US_CSR & US_CSR_RXRDY) == 0) continue;\r
+\r
+ /* Get FIFO size (in octets) and clamp it */\r
+ uint32_t buf_size = usart_fifo_rx_size(usart);\r
+ buf_size = buf_size > left ? left : buf_size;\r
+\r
+ /* Fill the buffer as must as possible with four data reads */\r
+ while (buf_size >= sizeof(uint32_t)) {\r
+ *(uint32_t*)buffer = usart->US_RHR;\r
+ buffer += sizeof(uint32_t);\r
+ left -= sizeof(uint32_t);\r
+ buf_size -= sizeof(uint32_t);\r
+ }\r
+ /* Add tail data if stream is not 4 octet aligned */\r
+ if (buf_size >= sizeof(uint16_t)) {\r
+ /* two data read */\r
+ readhw(&usart->US_RHR, (uint16_t*)buffer);\r
+ left -= sizeof(uint16_t);\r
+ buffer += sizeof(uint16_t);\r
+ buf_size -= sizeof(uint16_t);\r
+ }\r
+ if (buf_size >= sizeof(uint8_t)) {\r
+ /* one data read */\r
+ readb(&usart->US_RHR, buffer);\r
+ buffer += sizeof(uint8_t);\r
+ left -= sizeof(uint8_t);\r
+ buf_size -= sizeof(uint8_t);\r
+ }\r
+ }\r
+ return len - left;\r
+}\r
+\r
+/**\r
+ * \brief Writes given data to USART device output channel until the specified\r
+ * length is reached.\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \param stream Pointer to the data to send.\r
+ * \param len Size of the data to send, in octets.\r
+ *\r
+ * \return Number of written octets\r
+ *\r
+ * \warning WORKS ONLY IN LITTLE ENDIAN MODE!\r
+ *\r
+ * \note The FIFO must be configured before using this function.\r
+ * \note This function do not wait for the FIFO to be empty.\r
+ * \note In case of a TIMEOUT the transmission is aborted and the returned value\r
+ * should be inferior to \ref len.\r
+ */\r
+uint32_t usart_write_stream(Usart *usart, const void *stream, uint32_t len)\r
+{\r
+ const uint8_t* buffer = stream;\r
+ uint32_t left = len;\r
+ int32_t fifo_size = get_peripheral_fifo_depth(usart);\r
+ if (fifo_size < 0)\r
+ return 0;\r
+\r
+ while (left > 0) {\r
+ if ((usart->US_CSR & US_CSR_TXRDY) == 0) continue;\r
+\r
+ /* Get FIFO free size (int octet) and clamp it */\r
+ uint32_t buf_size = fifo_size - usart_fifo_tx_size(usart);\r
+ buf_size = buf_size > left ? left : buf_size;\r
+\r
+ /* Fill the FIFO as must as possible with four data writes */\r
+ while (buf_size >= sizeof(uint32_t)) {\r
+ usart->US_THR = *(uint32_t*)buffer;\r
+ buffer += sizeof(uint32_t);\r
+ left -= sizeof(uint32_t);\r
+ buf_size -= sizeof(uint32_t);\r
+ }\r
+ /* Add tail data if stream is not 4 octet aligned */\r
+ if (buf_size >= sizeof(uint16_t)) {\r
+ /* two data write */\r
+ writehw(&usart->US_THR, *(uint16_t*)buffer);\r
+ buffer += sizeof(uint16_t);\r
+ left -= sizeof(uint16_t);\r
+ buf_size -= sizeof(uint16_t);\r
+ }\r
+ if (buf_size >= sizeof(uint8_t)) {\r
+ /* one data write */\r
+ writeb(&usart->US_THR, *buffer);\r
+ buffer += sizeof(uint8_t);\r
+ left -= sizeof(uint8_t);\r
+ buf_size -= sizeof(uint8_t);\r
+ }\r
+ }\r
+ return len - left;\r
+}\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * This module provides several definitions and methods for using an USART\r
+ * peripheral.\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Enable the USART peripheral clock in the PMC.\r
+ * -# Enable the required USART PIOs (see pio.h).\r
+ * -# Configure the UART by calling usart_configure.\r
+ * -# Enable the transmitter and/or the receiver of the USART using\r
+ * usart_set_transmitter_enabled and usart_set_receiver_enabled.\r
+ * -# Send data through the USART using the usart_write methods.\r
+ * -# Receive data from the USART using the usart_read functions; the availability of data can be polled\r
+ * with usart_is_data_available.\r
+ * -# Disable the transmitter and/or the receiver of the USART with\r
+ * usart_set_transmitter_enabled and usart_set_receiver_enabled.\r
+ */\r
+\r
+#ifndef _USART_\r
+#define _USART_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/** \section USART_mode USART modes\r
+ * This section lists several common operating modes for an USART peripheral.\r
+ *\r
+ * \b Modes\r
+ * - USART_MODE_ASYNCHRONOUS\r
+ * - USART_MODE_IRDA\r
+ */\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+extern void usart_reset_status(Usart *usart);\r
+extern void usart_configure(Usart *usart, uint32_t mode, uint32_t baudrate);\r
+extern uint32_t usart_get_status(Usart * usart);\r
+extern void usart_enable_it(Usart *usart, uint32_t mode);\r
+extern void usart_disable_it(Usart *usart, uint32_t mode);\r
+extern uint32_t usart_get_it_mask(Usart *usart);\r
+extern void usart_set_transmitter_enabled(Usart *usart, uint8_t enabled);\r
+extern void usart_set_receiver_enabled(Usart *usart, uint8_t enabled);\r
+extern void usart_set_rts_enabled(Usart *usart, uint8_t enabled);\r
+\r
+extern void usart_reset_tx(Usart *usart);\r
+extern void usart_set_tx_timeguard(Usart *usart, uint32_t timeguard);\r
+extern void usart_reset_rx(Usart *usart);\r
+extern void usart_set_rx_timeout(Usart *usart, uint32_t timeout);\r
+extern void usart_start_tx_break(Usart *usart);\r
+extern void usart_stop_tx_break(Usart *usart);\r
+extern void usart_start_rx_timeout(Usart *usart);\r
+extern void usart_reset_iterations(Usart *usart);\r
+extern void usart_reset_nack(Usart *usart);\r
+extern void usart_restart_rx_timeout(Usart *usart);\r
+\r
+extern void usart_write(Usart *usart, uint16_t data, volatile uint32_t timeout);\r
+extern uint16_t usart_read(Usart *usart, volatile uint32_t timeout);\r
+extern uint8_t usart_is_data_available(Usart *usart);\r
+extern uint32_t usart_is_rx_ready(Usart *usart);\r
+extern uint32_t usart_is_tx_ready(Usart *usart);\r
+\r
+extern void usart_put_char(Usart *usart, uint8_t c);\r
+extern uint8_t usart_get_char(Usart *usart);\r
+\r
+extern void usart_set_irda_filter(Usart *usart, uint8_t filter);\r
+\r
+extern void usart_set_sync_slave_baudrate(Usart *usart);\r
+extern uint32_t usart_set_spi_master_baudrate(Usart *usart, uint32_t baudrate);\r
+extern void usart_set_spi_slave_baudrate(Usart *usart);\r
+extern uint32_t usart_init_hw_handshaking(Usart *usart);\r
+extern uint32_t usart_set_async_baudrate(Usart *usart, uint32_t baudrate);\r
+\r
+#ifdef CONFIG_HAVE_USART_FIFO\r
+extern void usart_fifo_configure(Usart *usart, uint8_t tx_thres,\r
+ uint8_t rx_down_thres, uint8_t rx_up_thres,\r
+ uint32_t ready_modes);\r
+extern void usart_fifo_disable(Usart *usart);\r
+extern void usart_fifo_enable_it(Usart *usart, uint32_t interrupt_mask);\r
+extern void usart_fifo_disable_it(Usart *usart, uint32_t interrupt_mask);\r
+extern uint32_t usart_fifo_get_interrupts(Usart *usart);\r
+extern uint32_t usart_fifo_rx_size(Usart *usart);\r
+extern uint32_t usart_fifo_tx_size(Usart *usart);\r
+extern uint32_t usart_read_stream(Usart *usart, void *stream, uint32_t len);\r
+extern uint32_t usart_write_stream(Usart *usart, const void *stream, uint32_t len);\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _USART_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * ISO 7816 driver\r
+ *\r
+ * \section Usage\r
+ *\r
+ * Explanation on the usage of the code made available through the header file.\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "chip.h"\r
+\r
+#ifdef CONFIG_HAVE_FLEXCOM\r
+#include "peripherals/flexcom.h"\r
+#endif\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/usart_iso7816_4.h"\r
+#include "peripherals/usart.h"\r
+\r
+#include "trace.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+/** Case for APDU commands*/\r
+#define CASE1 1\r
+#define CASE2 2\r
+#define CASE3 3\r
+\r
+/** Flip flop for send and receive char */\r
+#define USART_SEND 0\r
+#define USART_RCV 1\r
+\r
+/*-----------------------------------------------------------------------------\r
+ * Internal variables\r
+ *-----------------------------------------------------------------------------*/\r
+/** Variable for state of send and receive froom USART */\r
+static uint8_t state_usart_global = USART_RCV;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Internal functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Get a character from iso7816\r
+ * \param pchar_to_receive Pointer for store the received char\r
+ * \return 0: if timeout else status of US_CSR\r
+ */\r
+static uint32_t iso7816_get_char(Usart* usart, uint8_t * pchar_to_receive)\r
+{\r
+ uint32_t status;\r
+ uint32_t timeout = 0;\r
+\r
+ if (state_usart_global == USART_SEND) {\r
+ while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) {\r
+ }\r
+ usart->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;\r
+ state_usart_global = USART_RCV;\r
+ }\r
+\r
+ /* Wait USART ready for reception */\r
+ while (((usart->US_CSR & US_CSR_RXRDY) == 0)) {\r
+ if (timeout++ > 12000 * (pmc_get_master_clock() / 1000000)) {\r
+ trace_debug("TimeOut\n\r");\r
+ return (0);\r
+ }\r
+ }\r
+ trace_debug("T: %u\n\r", (unsigned)timeout);\r
+\r
+ /* At least one complete character has been received and US_RHR has not yet been read. */\r
+ /* Get a char */\r
+ *pchar_to_receive = ((usart->US_RHR) & 0xFF);\r
+\r
+ status = (usart-> US_CSR & (US_CSR_OVRE | US_CSR_FRAME | US_CSR_PARE | US_CSR_TIMEOUT | US_CSR_NACK | (1 << 10)));\r
+\r
+ if (status != 0) {\r
+ /* trace_debug("R:0x%X\n\r", status); */\r
+ trace_debug("R:0x%X\n\r", (unsigned)usart->US_CSR);\r
+ trace_debug("Nb:0x%X\n\r", (unsigned)usart->US_NER);\r
+ usart->US_CR = US_CR_RSTSTA;\r
+ }\r
+ /* Return status */\r
+ return (status);\r
+}\r
+\r
+/**\r
+ * Send a char to iso7816\r
+ * \param char_to_send char to be send\r
+ * \return status of US_CSR\r
+ */\r
+static uint32_t iso7816_send_char(Usart* usart, uint8_t char_to_send)\r
+{\r
+ uint32_t status;\r
+\r
+ if (state_usart_global == USART_RCV) {\r
+ usart->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;\r
+ state_usart_global = USART_SEND;\r
+ }\r
+\r
+ /* Wait USART ready for transmit */\r
+ while ((usart->US_CSR & US_CSR_TXRDY) == 0) {\r
+ }\r
+ /* There is no character in the US_THR */\r
+ /* Transmit a char */\r
+ usart->US_THR = char_to_send;\r
+\r
+ status = (usart-> US_CSR & (US_CSR_OVRE | US_CSR_FRAME | US_CSR_PARE | US_CSR_TIMEOUT | US_CSR_NACK | (1 << 10)));\r
+\r
+ if (status != 0) {\r
+ trace_debug("E:0x%X\n\r", (unsigned)usart->US_CSR);\r
+ trace_debug("Nb:0x%X\n\r", (unsigned)usart->US_NER);\r
+ usart->US_CR = US_CR_RSTSTA;\r
+ }\r
+ /* Return status */\r
+ return (status);\r
+}\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Iso 7816 ICC power off\r
+ */\r
+void iso7816_icc_power_off(const struct _pin* pinrst)\r
+{\r
+ /* Clear RESET Master Card */\r
+ pio_clear(pinrst);\r
+}\r
+\r
+/**\r
+ * Iso 7816 ICC power on\r
+ */\r
+static void iso7816_icc_power_on(const struct _pin* pinrst)\r
+{\r
+ /* Set RESET Master Card */\r
+ pio_set(pinrst);\r
+}\r
+\r
+\r
+/**\r
+ * Transfert Block TPDU T=0\r
+ * \param pAPDU APDU buffer\r
+ * \param pMessage Message buffer\r
+ * \param length Block length\r
+ * \return Message index\r
+ */\r
+uint16_t iso7816_xfr_block_TPDU_T0(const struct _iso7816_desc* iso7816, const uint8_t * pAPDU,\r
+ uint8_t * pMessage, uint16_t length)\r
+{\r
+ uint16_t NeNc, indexApdu = 4, indexMessage = 0;\r
+ uint8_t SW1 = 0, procByte, cmdCase, ins;\r
+ Usart* usart = iso7816->addr;\r
+\r
+ trace_debug("pAPDU[0]=0x%X\n\r", pAPDU[0]);\r
+ trace_debug("pAPDU[1]=0x%X\n\r", pAPDU[1]);\r
+ trace_debug("pAPDU[2]=0x%X\n\r", pAPDU[2]);\r
+ trace_debug("pAPDU[3]=0x%X\n\r", pAPDU[3]);\r
+ trace_debug("pAPDU[4]=0x%X\n\r", pAPDU[4]);\r
+ trace_debug("pAPDU[5]=0x%X\n\r", pAPDU[5]);\r
+ trace_debug("wlength=%d\n\r", length);\r
+\r
+ iso7816_send_char(usart, pAPDU[0]); /* CLA */\r
+ iso7816_send_char(usart, pAPDU[1]); /* INS */\r
+ iso7816_send_char(usart, pAPDU[2]); /* P1 */\r
+ iso7816_send_char(usart, pAPDU[3]); /* P2 */\r
+ iso7816_send_char(usart, pAPDU[4]); /* P3 */\r
+\r
+ /* Handle the four structures of command APDU */\r
+ indexApdu = 4;\r
+\r
+ if (length == 4) {\r
+ cmdCase = CASE1;\r
+ NeNc = 0;\r
+ } else if (length == 5) {\r
+ cmdCase = CASE2;\r
+ NeNc = pAPDU[4]; /* C5 */\r
+ if (NeNc == 0) {\r
+ NeNc = 256;\r
+ }\r
+ } else if (length == 6) {\r
+ NeNc = pAPDU[4]; /* C5 */\r
+ cmdCase = CASE3;\r
+ } else if (length == 7) {\r
+ NeNc = pAPDU[4]; /* C5 */\r
+ if (NeNc == 0) {\r
+ cmdCase = CASE2;\r
+ NeNc = (pAPDU[5] << 8) + pAPDU[6];\r
+ } else {\r
+ cmdCase = CASE3;\r
+ }\r
+ } else {\r
+ NeNc = pAPDU[4]; /* C5 */\r
+ if (NeNc == 0) {\r
+ cmdCase = CASE3;\r
+ NeNc = (pAPDU[5] << 8) + pAPDU[6];\r
+ } else {\r
+ cmdCase = CASE3;\r
+ }\r
+ }\r
+\r
+ trace_debug("CASE=0x%X NeNc=0x%X\n\r", cmdCase, NeNc);\r
+\r
+ /* Handle Procedure Bytes */\r
+ do {\r
+ iso7816_get_char(usart, &procByte);\r
+ ins = procByte ^ 0xff;\r
+ /* Handle NULL */\r
+ if (procByte == ISO_NULL_VAL) {\r
+ trace_debug("INS\n\r");\r
+ continue;\r
+ }\r
+ /* Handle SW1 */\r
+ else if (((procByte & 0xF0) == 0x60) || ((procByte & 0xF0) == 0x90)) {\r
+ trace_debug("SW1\n\r");\r
+ SW1 = 1;\r
+ }\r
+ /* Handle INS */\r
+ else if (pAPDU[1] == procByte) {\r
+ trace_debug("HdlINS\n\r");\r
+ if (cmdCase == CASE2) {\r
+ /* receive data from card */\r
+ do {\r
+ iso7816_get_char(usart, &pMessage[indexMessage++]);\r
+ } while (0 != --NeNc);\r
+ } else {\r
+ /* Send data */\r
+ do {\r
+ iso7816_send_char(usart, pAPDU[indexApdu++]);\r
+ } while (0 != --NeNc);\r
+ }\r
+ }\r
+ /* Handle INS ^ 0xff */\r
+ else if (pAPDU[1] == ins) {\r
+ trace_debug("HdlINS+\n\r");\r
+ if (cmdCase == CASE2) {\r
+ /* receive data from card */\r
+ iso7816_get_char(usart, &pMessage[indexMessage++]);\r
+ } else {\r
+ iso7816_send_char(usart, pAPDU[indexApdu++]);\r
+ }\r
+ NeNc--;\r
+ } else {\r
+ /* ?? */\r
+ trace_debug("procByte=0x%X\n\r", procByte);\r
+ break;\r
+ }\r
+ } while (NeNc != 0);\r
+\r
+ /* Status Bytes */\r
+ if (SW1 == 0) {\r
+ iso7816_get_char(usart, &pMessage[indexMessage++]); /* SW1 */\r
+ } else {\r
+ pMessage[indexMessage++] = procByte;\r
+ }\r
+ iso7816_get_char(usart, &pMessage[indexMessage++]); /* SW2 */\r
+\r
+ return (indexMessage);\r
+}\r
+\r
+/**\r
+ * Escape iso7816\r
+ */\r
+void iso7816_escape(void)\r
+{\r
+ trace_debug("For user, if needed\n\r");\r
+}\r
+\r
+/**\r
+ * Restart clock iso7816\r
+ */\r
+void iso7816_restart_clock(struct _iso7816_desc* iso7816)\r
+{\r
+ Usart* usart = iso7816->addr;\r
+ trace_debug("iso7816_restart_clock\n\r");\r
+ usart->US_BRGR = 13;\r
+}\r
+\r
+/**\r
+ * Stop clock iso7816\r
+ */\r
+void iso7816_stop_clock(struct _iso7816_desc* iso7816)\r
+{\r
+ Usart* usart = iso7816->addr;\r
+ trace_debug("iso7816_stop_clock\n\r");\r
+ usart->US_BRGR = 0;\r
+}\r
+\r
+/**\r
+ * T0 APDU\r
+ */\r
+void iso7816_to_APDU(void)\r
+{\r
+ trace_debug("iso7816_toAPDU\n\r");\r
+ trace_debug("Not supported at this time\n\r");\r
+}\r
+\r
+/**\r
+ * Answer To Reset (ATR)\r
+ * \param pAtr ATR buffer\r
+ * \param plength Pointer for store the ATR length\r
+ */\r
+void iso7816_get_data_block_ATR(struct _iso7816_desc* iso7816, uint8_t * pAtr, uint8_t * plength)\r
+{\r
+ uint32_t i, j, y;\r
+ Usart* usart = iso7816->addr;\r
+\r
+ *plength = 0;\r
+\r
+ /* Read ATR TS */\r
+ iso7816_get_char(usart, &pAtr[0]);\r
+ /* Read ATR T0 */\r
+ iso7816_get_char(usart, &pAtr[1]);\r
+ y = pAtr[1] & 0xF0;\r
+ i = 2;\r
+\r
+ /* Read ATR Ti */\r
+ while (y) {\r
+ if (y & 0x10) { /* TA[i] */\r
+ iso7816_get_char(usart, &pAtr[i++]);\r
+ }\r
+ if (y & 0x20) { /* TB[i] */\r
+ iso7816_get_char(usart, &pAtr[i++]);\r
+ }\r
+ if (y & 0x40) { /* TC[i] */\r
+ iso7816_get_char(usart, &pAtr[i++]);\r
+ }\r
+ if (y & 0x80) { /* TD[i] */\r
+ iso7816_get_char(usart, &pAtr[i]);\r
+ y = pAtr[i++] & 0xF0;\r
+ } else {\r
+ y = 0;\r
+ }\r
+ }\r
+ /* Historical Bytes */\r
+ y = pAtr[1] & 0x0F;\r
+ for (j = 0; j < y; j++) {\r
+ iso7816_get_char(usart, &pAtr[i++]);\r
+ }\r
+ *plength = i;\r
+}\r
+\r
+/**\r
+ * Set data rate and clock frequency\r
+ * \param clock_frequency ICC clock frequency in KHz.\r
+ * \param data_rate ICC data rate in bpd\r
+ */\r
+void iso7816_set_data_rate_and_clock_frequency(struct _iso7816_desc* iso7816, uint32_t clock_frequency, uint32_t data_rate)\r
+{\r
+ uint8_t clk_frequency;\r
+ uint32_t per_mck;\r
+ Usart* usart = iso7816->addr;\r
+\r
+ /* Define the baud rate divisor register */\r
+ per_mck = pmc_get_peripheral_clock(iso7816->id);\r
+ usart->US_BRGR = per_mck / (clock_frequency * 1000);\r
+ clk_frequency = per_mck / usart->US_BRGR;\r
+ usart->US_FIDI = (clk_frequency) / data_rate;\r
+}\r
+\r
+/**\r
+ * Pin status for iso7816 RESET\r
+ * \return 1 if the Pin RstMC is high; otherwise 0.\r
+ */\r
+uint8_t iso7816_get_status_pin_reset(const struct _pin* pinrst)\r
+{\r
+ return pio_get(pinrst);\r
+}\r
+\r
+/**\r
+ * cold reset\r
+ */\r
+void iso7816_cold_reset(struct _iso7816_desc* iso7816)\r
+{\r
+ volatile uint32_t i;\r
+ Usart* usart = iso7816->addr;\r
+\r
+ /* tb: wait 400 cycles */\r
+ for (i = 0; i < (120 * (pmc_get_master_clock() / 1000000)); i++) {\r
+ }\r
+ usart->US_RHR;\r
+ usart->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;\r
+ iso7816_icc_power_on(&iso7816->pin_rst);\r
+}\r
+\r
+/**\r
+ * Warm reset\r
+ */\r
+void iso7816_warm_reset(struct _iso7816_desc* iso7816)\r
+{\r
+ volatile uint32_t i;\r
+ Usart* usart = iso7816->addr;\r
+\r
+ iso7816_icc_power_off(&iso7816->pin_rst);\r
+ /* tb: wait 400 cycles, 40000cycles/t(277ns)=11ms */\r
+ for (i = 0; i < (30 * (pmc_get_master_clock() / 1000000)); i++) {\r
+ }\r
+ usart->US_RHR;\r
+ usart->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK;\r
+ iso7816_icc_power_on(&iso7816->pin_rst);\r
+}\r
+\r
+/**\r
+ * Decode ATR trace\r
+ * \param pAtr pointer on ATR buffer\r
+ */\r
+void iso7816_decode_ATR(uint8_t * pAtr)\r
+{\r
+ uint32_t i, j, y;\r
+ uint8_t offset;\r
+\r
+ printf("\n\r");\r
+ printf("ATR: Answer To Reset:\n\r");\r
+ printf("TS = 0x%X Initial character ", pAtr[0]);\r
+\r
+ switch (pAtr[0])\r
+ {\r
+ case 0x3B:\r
+ printf("Direct Convention\n\r");\r
+ break;\r
+ case 0x3F:\r
+ printf("Inverse Convention\n\r");\r
+ break;\r
+ default:\r
+ printf("BAD Convention\n\r");\r
+ break;\r
+ }\r
+ printf("T0 = 0x%X Format caracter\n\r", pAtr[1]);\r
+ printf(" Number of historical bytes: K = %d\n\r", pAtr[1] & 0x0F);\r
+ printf(" Presence further interface byte:\n\r");\r
+ if (pAtr[1] & 0x80) {\r
+ printf("TA ");\r
+ }\r
+ if (pAtr[1] & 0x40) {\r
+ printf("TB ");\r
+ }\r
+ if (pAtr[1] & 0x20) {\r
+ printf("TC ");\r
+ }\r
+ if (pAtr[1] & 0x10) {\r
+ printf("TD ");\r
+ }\r
+ if (pAtr[1] != 0) {\r
+ printf(" present\n\r");\r
+ }\r
+\r
+ i = 2;\r
+ y = pAtr[1] & 0xF0;\r
+\r
+ /* Read ATR Ti */\r
+ offset = 1;\r
+ while (y) {\r
+\r
+ if (y & 0x10) { /* TA[i] */\r
+ printf("TA[%d] = 0x%X ", offset, pAtr[i]);\r
+ if (offset == 1) {\r
+ printf("FI = %d ", (pAtr[i] >> 8));\r
+ printf("DI = %d", (pAtr[i] & 0x0F));\r
+ }\r
+ printf("\n\r");\r
+ i++;\r
+ }\r
+ if (y & 0x20) { /* TB[i] */\r
+ printf("TB[%d] = 0x%X\n\r", offset, pAtr[i]);\r
+ i++;\r
+ }\r
+ if (y & 0x40) { /* TC[i] */\r
+ printf("TC[%d] = 0x%X ", offset, pAtr[i]);\r
+ if (offset == 1) {\r
+ printf("Extra Guard Time: N = %d", pAtr[i]);\r
+ }\r
+ printf("\n\r");\r
+ i++;\r
+ }\r
+ if (y & 0x80) { /* TD[i] */\r
+ printf("TD[%d] = 0x%X\n\r", offset, pAtr[i]);\r
+ y = pAtr[i++] & 0xF0;\r
+ } else {\r
+ y = 0;\r
+ }\r
+ offset++;\r
+ }\r
+\r
+ /* Historical Bytes */\r
+ printf("Historical bytes:\n\r");\r
+ y = pAtr[1] & 0x0F;\r
+ for (j = 0; j < y; j++) {\r
+\r
+ printf(" 0x%X", pAtr[i]);\r
+ if ((pAtr[i] > 0x21) && (pAtr[i] < 0x7D)) { /* ASCII */\r
+ printf("(%c) ", pAtr[i]);\r
+ }\r
+ i++;\r
+ }\r
+ printf("\n\r\n\r");\r
+\r
+}\r
+\r
+/** Initializes a usart ISO7816\r
+ * \param\r
+ */\r
+static void _usart_iso7816_configure(Usart* usart, const struct _iso7816_opt* opt, uint32_t mode)\r
+{\r
+ /* Reset and disable receiver & transmitter */\r
+ usart->US_CR = US_CR_RSTRX | US_CR_RSTTX | US_CR_RXDIS | US_CR_TXDIS;\r
+ /* Configure mode */\r
+ usart->US_MR = mode;\r
+\r
+ /* Disable all interrupts */\r
+ usart->US_IDR = 0xFFFFFFFF;\r
+ usart->US_FIDI = opt->fidi_ratio;\r
+ /* Define the baud rate divisor register */\r
+ /* CD = MCK /(FIDI x BAUD) = periph_mck / (372x9600) */\r
+ uint32_t per_mck = pmc_get_peripheral_clock(get_usart_id_from_addr(usart));\r
+ usart->US_BRGR = per_mck / opt->iso7816_hz;\r
+ /* Write the Timeguard Register */\r
+ usart->US_TTGR = opt->time_guard;\r
+ /* Enable receiver and transmitter */\r
+ usart->US_CR = US_CR_RXEN | US_CR_TXEN;\r
+}\r
+\r
+/** Initializes a ISO driver\r
+ * \param\r
+ */\r
+uint8_t iso7816_init(struct _iso7816_desc* iso7816, const struct _iso7816_opt* opt)\r
+{\r
+ uint32_t mode = 0;\r
+ Usart* usart = iso7816->addr;\r
+\r
+ trace_debug("ISO_Init\n\r");\r
+\r
+ /* Configure control Pios */\r
+ pio_configure(&iso7816->pin_stop, 1);\r
+ pio_configure(&iso7816->pin_mod_vcc, 1);\r
+ pio_configure(&iso7816->pin_rst, 1);\r
+\r
+ /* STOP = 1, normal operation */\r
+ pio_set(&iso7816->pin_stop);\r
+ /* MOD = 1, 3V3 */\r
+ pio_set(&iso7816->pin_mod_vcc);\r
+\r
+ pmc_enable_peripheral(iso7816->id);\r
+\r
+#ifdef CONFIG_HAVE_FLEXCOM\r
+ /* switch Flexcom to Usart mode */\r
+ Flexcom* flexcom = get_flexcom_addr_from_id(iso7816->id);\r
+ if (flexcom) {\r
+ flexcom_select(flexcom, FLEX_MR_OPMODE_USART);\r
+ }\r
+#endif\r
+\r
+ /* Initialize driver to use */\r
+ mode = opt->clock_sel | opt->char_length | opt->sync | opt->parity_type ;\r
+ mode |= opt->inhibit_nack | opt->dis_suc_nack ;\r
+ mode |= US_MR_CLKO ; /* The USART drives the SCK pin */\r
+\r
+ /* Check whether the input values are legal. */\r
+ if ( (opt->parity_type != US_MR_PAR_EVEN) && (opt->parity_type != US_MR_PAR_ODD) ) {\r
+ return 1;\r
+ }\r
+ if (opt->protocol_type == US_MR_USART_MODE_IS07816_T_0) {\r
+ mode |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT | US_MR_MAX_ITERATION(opt->max_iterations);\r
+ if (opt->bit_order) {\r
+ mode |= US_MR_MSBF;\r
+ }\r
+ } else if (opt->protocol_type == US_MR_USART_MODE_IS07816_T_1) {\r
+ /*\r
+ * Only LSBF is used in the T=1 protocol, and max_iterations field\r
+ * is only used in T=0 mode.\r
+ */\r
+ if (opt->bit_order || opt->max_iterations) {\r
+ return 1;\r
+ }\r
+ /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */\r
+ mode |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT;\r
+ } else {\r
+ return 1;\r
+ }\r
+\r
+ _usart_iso7816_configure (usart, opt, mode);\r
+ return 0;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+//------------------------------------------------------------------------------\r
+/** \addtogroup iso7816_4 ISO7816-4 Driver\r
+ * \section Purpose\r
+ *\r
+ * Definition of methods for ISO7816 driver.\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# ISO7816_Init()\r
+ * -# ISO7816_IccPowerOff()\r
+ * -# ISO7816_XfrBlockTPDU_T0()\r
+ * -# ISO7816_Escape()\r
+ * -# ISO7816_RestartClock()\r
+ * -# ISO7816_StopClock()\r
+ * -# ISO7816_toAPDU()\r
+ * -# ISO7816_Datablock_ATR()\r
+ * -# ISO7816_SetDataRateandClockFrequency()\r
+ * -# ISO7816_StatusReset()\r
+ * -# ISO7816_cold_reset()\r
+ * -# ISO7816_warm_reset()\r
+ * -# ISO7816_Decode_ATR()\r
+ */\r
+\r
+#ifndef ISO7816_4_H\r
+#define ISO7816_4_H\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Include headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "peripherals/pio.h"\r
+#include "peripherals/usart.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Constants Definition\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Size max of Answer To Reset */\r
+#define ATR_SIZE_MAX 55\r
+\r
+/** NULL byte to restart byte procedure */\r
+#define ISO_NULL_VAL 0x60\r
+\r
+/* MOD_VCC The signal present on this pin programs the SIM_VCC value */\r
+#define MOD_VCC_1V8 0\r
+#define MOD_VCC_3V3 1\r
+\r
+/* STOP pin, Power Down Mode pin */\r
+#define STOP_SHUTDOWN 0\r
+#define STOP_NORMAL 1\r
+\r
+struct _iso7816_opt {\r
+ uint32_t protocol_type; /* Which protocol is used 0: T = 0, 1: T = 1*/\r
+ uint32_t clock_sel; /* Clock Selection */\r
+ uint32_t char_length; /* Character Length*/\r
+ uint32_t sync; /* Synchronous Mode Select */\r
+ uint32_t parity_type; /* Parity Type*/\r
+ uint32_t num_stop_bits; /* Number of Stop Bits*/\r
+ uint32_t bit_order; /* Bit order in transmitted characters 0: LSB first 1: MSB first.*/\r
+ uint32_t inhibit_nack; /* Inhibit Non Acknowledge*/\r
+ uint32_t dis_suc_nack; /* Disable Successive NACK*/\r
+\r
+ uint32_t max_iterations;/* */\r
+ uint32_t iso7816_hz; /* Set the frequency of the ISO7816 clock. */\r
+ uint32_t fidi_ratio; /* */\r
+ uint32_t time_guard; /* */\r
+};\r
+\r
+\r
+struct _iso7816_desc {\r
+ const struct _pin pin_stop;\r
+ const struct _pin pin_mod_vcc;\r
+ const struct _pin pin_rst;\r
+\r
+ Usart* addr;\r
+ uint8_t id;\r
+};\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void iso7816_icc_power_off(const struct _pin* pinrst);\r
+extern uint16_t iso7816_xfr_block_TPDU_T0(const struct _iso7816_desc* iso7816, const uint8_t* pAPDU, uint8_t* pMessage, uint16_t length);\r
+extern void iso7816_escape(void);\r
+extern void iso7816_restart_clock(struct _iso7816_desc* iso7816);\r
+extern void iso7816_stop_clock(struct _iso7816_desc* iso7816);\r
+extern void iso7816_to_APDU(void);\r
+extern void iso7816_get_data_block_ATR(struct _iso7816_desc* iso7816, uint8_t * pAtr, uint8_t * plength);\r
+extern void iso7816_set_data_rate_and_clock_frequency(struct _iso7816_desc* iso7816, uint32_t clock_frequency, uint32_t data_rate);\r
+\r
+extern uint8_t iso7816_get_status_pin_reset(const struct _pin* pinrst);\r
+extern void iso7816_cold_reset(struct _iso7816_desc* iso7816);\r
+extern void iso7816_warm_reset(struct _iso7816_desc* iso7816);\r
+extern void iso7816_decode_ATR(uint8_t * pAtr);\r
+\r
+extern uint8_t iso7816_init(struct _iso7816_desc* iso7816, const struct _iso7816_opt* opt);\r
+\r
+\r
+\r
+\r
+#endif /* ISO7816_4_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup usart_module Working with USART_LIN\r
+ * \section Purpose\r
+ * The USART_LIN driver provides the interface to configure and use the USART peripheral in LIN mode.\n\r
+ *\r
+ *\r
+ * For more accurate information, please look at the USART LIN section of the\r
+ * Datasheet.\r
+ *\r
+ * Related files :\n\r
+ * \ref usart_lin.c\n\r
+ * \ref usart_lin.h\n\r
+*/\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of USART in LIN mode (Universal Synchronous Asynchronous Receiver Transmitter)\r
+ * controller.\r
+ *\r
+ */\r
+/*-----------------------------------------------------------------------------\r
+* Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "compiler.h"\r
+\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/usart.h"\r
+#include "peripherals/usart_lin.h"\r
+\r
+#include "trace.h"\r
+#include "io.h"\r
+\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+/*-----------------------------------------------------------------------------\r
+*\r
+ *---------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void usart_lin_reset_status_bits(Usart *usart)\r
+{\r
+ usart->US_CR = US_CR_RSTSTA;\r
+}\r
+\r
+\r
+uint32_t usart_lin_get_status_register(Usart *usart)\r
+{\r
+ return usart->US_CSR;\r
+}\r
+\r
+void usart_lin_set_mode_master_or_slave (Usart* usart, uint32_t mode_master_or_slave)\r
+{\r
+ /* Set LIN master or slave mode. */\r
+ usart->US_MR = (usart->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE(mode_master_or_slave);\r
+}\r
+\r
+/**\r
+ * \brief Abort the current LIN transmission.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_abort_tx(Usart *usart)\r
+{\r
+ usart->US_CR = US_CR_LINABT;\r
+}\r
+\r
+/**\r
+ * \brief Send a wakeup signal on the LIN bus.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_send_wakeup_signal(Usart *usart)\r
+{\r
+ usart->US_CR = US_CR_LINWKUP;\r
+}\r
+\r
+/**\r
+ * \brief Configure the LIN node action, which should be one of PUBLISH,\r
+ * SUBSCRIBE or IGNORE.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ * \param action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE.\r
+ */\r
+void usart_lin_set_node_action(Usart *usart, uint8_t action)\r
+{\r
+ usart->US_LINMR = (usart->US_LINMR & ~US_LINMR_NACT_Msk) | (action << US_LINMR_NACT_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Disable the parity check during the LIN communication.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_parity(Usart *usart)\r
+{\r
+ usart->US_LINMR |= US_LINMR_PARDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the parity check during the LIN communication.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_parity(Usart *usart)\r
+{\r
+ usart->US_LINMR &= ~US_LINMR_PARDIS;\r
+}\r
+\r
+/**\r
+ * \brief Disable the checksum during the LIN communication.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_checksum(Usart *usart)\r
+{\r
+ usart->US_LINMR |= US_LINMR_CHKDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the checksum during the LIN communication.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_checksum(Usart *usart)\r
+{\r
+ usart->US_LINMR &= ~US_LINMR_CHKDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the checksum type during the LIN communication.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ * \param type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic\r
+ * checksum.\r
+ */\r
+void usart_lin_set_checksum_type(Usart *usart, uint8_t type)\r
+{\r
+ usart->US_LINMR = (usart->US_LINMR & ~US_LINMR_CHKTYP) | (type << 4);\r
+}\r
+\r
+/**\r
+ * \brief Configure the data length mode during the LIN communication.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ * \param mode Indicate the data length type: 0 if the data length is\r
+ * defined by the DLC of LIN mode register or 1 if the data length is defined\r
+ * by the bit 5 and 6 of the identifier.\r
+ */\r
+void usart_lin_set_data_len_mode(Usart *usart, uint8_t mode)\r
+{\r
+ usart->US_LINMR = (usart->US_LINMR & ~US_LINMR_DLM) | (mode << 5);\r
+}\r
+\r
+/**\r
+ * \brief Disable the frame slot mode during the LIN communication.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_frame_slot(Usart *usart)\r
+{\r
+ usart->US_LINMR |= US_LINMR_FSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the frame slot mode during the LIN communication.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_frame_slot(Usart *usart)\r
+{\r
+ usart->US_LINMR &= ~US_LINMR_FSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the wakeup signal type during the LIN communication.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ * \param type Indicate the checksum type: 0 if the wakeup signal is a\r
+ * LIN 2.0 wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal.\r
+ */\r
+void usart_lin_set_wakeup_signal_type(Usart *usart, uint8_t type)\r
+{\r
+ usart->US_LINMR = (usart->US_LINMR & ~US_LINMR_WKUPTYP) | (type << 7);\r
+}\r
+\r
+/**\r
+ * \brief Configure the response data length if the data length is defined by\r
+ * the DLC field during the LIN communication.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ * \param len Indicate the response data length.\r
+ */\r
+void usart_lin_set_frame_data_len(Usart *usart, uint8_t len)\r
+{\r
+ usart->US_LINMR = (usart->US_LINMR & ~US_LINMR_DLC_Msk) | ((len-1) << US_LINMR_DLC_Pos);\r
+}\r
+\r
+/**\r
+ * \brief The LIN mode register is not written by the DMAC.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_dmac_mode(Usart *usart)\r
+{\r
+ usart->US_LINMR &= ~US_LINMR_PDCM;\r
+}\r
+\r
+/**\r
+ * \brief The LIN mode register (except this flag) is written by the DMAC.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_dmac_mode(Usart *usart)\r
+{\r
+ usart->US_LINMR |= US_LINMR_PDCM;\r
+}\r
+\r
+/**\r
+ * \brief Configure the LIN identifier when USART works in LIN master mode.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ * \param id The identifier to be transmitted.\r
+ */\r
+void usart_lin_set_tx_identifier(Usart *usart, uint8_t id)\r
+{\r
+ usart->US_LINIR = (usart->US_LINIR & ~US_LINIR_IDCHR_Msk) | US_LINIR_IDCHR(id);\r
+}\r
+\r
+/**\r
+ * \brief Read the identifier when USART works in LIN mode.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ *\r
+ * \return The last identifier received in LIN slave mode or the last\r
+ * identifier transmitted in LIN master mode.\r
+ */\r
+uint8_t usart_lin_read_identifier(Usart *usart)\r
+{\r
+ return (usart->US_LINIR & US_LINIR_IDCHR_Msk);\r
+}\r
+\r
+/**\r
+ * \brief Get data length.\r
+ *\r
+ * \param usart Pointer to a USART instance.\r
+ *\r
+ * \return Data length.\r
+ */\r
+uint8_t usart_lin_get_data_length(Usart *usart)\r
+{\r
+ if (usart->US_LINMR & US_LINMR_DLM) {\r
+ uint8_t data_length = 1 << ((usart->US_LINIR >> (US_LINIR_IDCHR_Pos + 4)) & 0x03);\r
+ return data_length;\r
+ } else {\r
+ return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1;\r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------------------------\r
+* Functions if FIFO are used\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#ifdef CONFIG_HAVE_USART_FIFO\r
+\r
+/**\r
+ * \brief Reads from USART device input channel until the specified length is\r
+ * reached.\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \param stream Pointer to the receive buffer.\r
+ * \param len Size of the receive buffer, in octets.\r
+ *\r
+ * \return Number of read octets\r
+ *\r
+ * \warning WORKS ONLY IN LITTLE ENDIAN MODE!\r
+ *\r
+ * \note The FIFO must be configured before using this function.\r
+ * \note In case of a TIMEOUT or a BREAK, a null character is appended to the\r
+ * buffer and the returned value should be inferior to \ref len.\r
+ */\r
+uint32_t usart_lin_read_stream(Usart *usart, uint8_t *stream, uint32_t len)\r
+{\r
+ uint8_t* buffer = stream;\r
+ uint32_t left = len;\r
+ while (left > 0) {\r
+ /* Stop reception if a timeout or break occur */\r
+ if ((usart->US_CSR & (US_CSR_TIMEOUT | US_CSR_RXBRK)) != 0) {\r
+ *buffer = '\0';\r
+ break;\r
+ }\r
+ if ((usart->US_CSR & (US_CSR_RXRDY | US_CSR_LINTC)) == 0) continue;\r
+\r
+ /* Get FIFO size (in octets) and clamp it */\r
+ uint32_t buf_size = usart_fifo_rx_size(usart);\r
+ buf_size = buf_size > left ? left : buf_size;\r
+\r
+ /* Fill the buffer with data received */\r
+ while (buf_size) {\r
+ readb(&usart->US_RHR, buffer);\r
+ buffer ++;\r
+ left -= sizeof(uint8_t);\r
+ buf_size -= sizeof(uint8_t);\r
+ }\r
+ }\r
+ return len - left;\r
+}\r
+\r
+/**\r
+ * \brief Writes given data to USART device output channel until the specified\r
+ * length is reached.\r
+ *\r
+ * \param usart Pointer to an USART instance.\r
+ * \param stream Pointer to the data to send.\r
+ * \param len Size of the data to send, in octets.\r
+ *\r
+ * \return Number of written octets\r
+ *\r
+ * \warning WORKS ONLY IN LITTLE ENDIAN MODE!\r
+ *\r
+ * \note The FIFO must be configured before using this function.\r
+ * \note This function do not wait for the FIFO to be empty.\r
+ * \note In case of a TIMEOUT the transmission is aborted and the returned value\r
+ * should be inferior to \ref len.\r
+ */\r
+uint32_t usart_lin_write_stream(Usart *usart, uint8_t *stream, uint32_t len)\r
+{\r
+ uint8_t* buffer = stream;\r
+ uint32_t left = len;\r
+ int32_t fifo_size = get_peripheral_fifo_depth(usart);\r
+ if (fifo_size < 0)\r
+ return 0;\r
+\r
+ while (left > 0) {\r
+ if ((usart->US_CSR & US_CSR_TXRDY) == 0) continue;\r
+\r
+ /* Get FIFO free size (int octet) and clamp it */\r
+ uint32_t buf_size = fifo_size - usart_fifo_tx_size(usart);\r
+ buf_size = buf_size > left ? left : buf_size;\r
+\r
+ /* Fill the FIFO with data to send */\r
+ while (buf_size) {\r
+ writeb(&usart->US_THR, *buffer);\r
+ buffer ++ ;\r
+ left -= sizeof(uint8_t);\r
+ buf_size -= sizeof(uint8_t);\r
+ }\r
+ }\r
+ return len - left;\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * This module provides several definitions and methods for using an USART\r
+ * peripheral in LIN mode.\r
+ *\r
+ */\r
+\r
+#ifndef _USART_LIN_\r
+#define _USART_LIN_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------*/\r
+/* Exported functions */\r
+/*------------------------------------------------------------------------------*/\r
+\r
+extern void usart_lin_reset_status_bits(Usart *usart);\r
+extern uint32_t usart_lin_get_status_register(Usart *usart);\r
+extern void usart_lin_set_mode_master_or_slave (Usart* usart, uint32_t mode_master_or_slave);\r
+extern void usart_lin_abort_tx(Usart *usart);\r
+extern void usart_lin_send_wakeup_signal(Usart *usart);\r
+extern void usart_lin_set_node_action(Usart *usart, uint8_t action);\r
+extern void usart_lin_disable_parity(Usart *usart);\r
+extern void usart_lin_enable_parity(Usart *usart);\r
+extern void usart_lin_disable_checksum(Usart *usart);\r
+extern void usart_lin_enable_checksum(Usart *usart);\r
+extern void usart_lin_set_checksum_type(Usart *usart, uint8_t type);\r
+extern void usart_lin_set_data_len_mode(Usart *usart, uint8_t mode);\r
+extern void usart_lin_disable_frame_slot(Usart *usart);\r
+extern void usart_lin_enable_frame_slot(Usart *usart);\r
+extern void usart_lin_set_wakeup_signal_type(Usart *usart, uint8_t type);\r
+extern void usart_lin_set_frame_data_len(Usart *usart, uint8_t len);\r
+extern void usart_lin_disable_dmac_mode(Usart *usart);\r
+extern void usart_lin_enable_dmac_mode(Usart *usart);\r
+extern void usart_lin_set_tx_identifier(Usart *usart, uint8_t id);\r
+extern uint8_t usart_lin_read_identifier(Usart *usart);\r
+extern uint8_t usart_lin_get_data_length(Usart *usart);\r
+\r
+\r
+#ifdef CONFIG_HAVE_USART_FIFO\r
+extern uint32_t usart_lin_read_stream(Usart *usart, uint8_t *stream, uint32_t len);\r
+extern uint32_t usart_lin_write_stream(Usart *usart, uint8_t *stream, uint32_t len);\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* #ifndef _USART_LIN_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#include "chip.h"\r
+\r
+#ifdef CONFIG_HAVE_FLEXCOM\r
+#include "peripherals/flexcom.h"\r
+#endif\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/usartd.h"\r
+#include "peripherals/usart.h"\r
+#include "peripherals/xdmac.h"\r
+#include "peripherals/xdmad.h"\r
+#include "peripherals/l2cc.h"\r
+\r
+#include "cortex-a/cp15.h"\r
+\r
+#include "trace.h"\r
+#include "mutex.h"\r
+\r
+#include <assert.h>\r
+#include <string.h>\r
+#include <stdint.h>\r
+\r
+#define USARTD_ATTRIBUTE_MASK (0)\r
+#define USARTD_DMA_THRESHOLD 16\r
+\r
+static void _usartd_xdmad_callback_wrapper(struct _xdmad_channel* channel,\r
+ void* args)\r
+{\r
+ trace_debug("USARTD DMA Transfert Finished\r\n");\r
+ struct _usart_desc* usartd = (struct _usart_desc*) args;\r
+\r
+ xdmad_free_channel(channel);\r
+\r
+ if (usartd->region_start && usartd->region_end) {\r
+ l2cc_invalidate_region(usartd->region_start,\r
+ usartd->region_end);\r
+ }\r
+\r
+ if (usartd && usartd->callback)\r
+ usartd->callback(usartd, usartd->cb_args);\r
+}\r
+\r
+static void _usartd_init_dma_read_channel(const struct _usart_desc* desc,\r
+ struct _xdmad_channel** channel,\r
+ struct _xdmad_cfg* cfg)\r
+{\r
+ assert(cfg);\r
+ assert(channel);\r
+\r
+ uint32_t id = get_usart_id_from_addr(desc->addr);\r
+\r
+ memset(cfg, 0x0, sizeof(*cfg));\r
+\r
+ *channel =\r
+ xdmad_allocate_channel(id, XDMAD_PERIPH_MEMORY);\r
+ assert(*channel);\r
+\r
+ xdmad_prepare_channel(*channel);\r
+ cfg->cfg.uint32_value = XDMAC_CC_TYPE_PER_TRAN\r
+ | XDMAC_CC_DSYNC_PER2MEM\r
+ | XDMAC_CC_MEMSET_NORMAL_MODE\r
+ | XDMAC_CC_CSIZE_CHK_1\r
+ | XDMAC_CC_DWIDTH_BYTE\r
+ | XDMAC_CC_DIF_AHB_IF0\r
+ | XDMAC_CC_SIF_AHB_IF1\r
+ | XDMAC_CC_SAM_FIXED_AM;\r
+\r
+ cfg->src_addr = (void*)&desc->addr->US_RHR;\r
+}\r
+\r
+static void _usartd_dma_read(const struct _usart_desc* desc,\r
+ struct _buffer* buffer)\r
+{\r
+ struct _xdmad_channel* channel = NULL;\r
+ struct _xdmad_cfg cfg;\r
+\r
+ _usartd_init_dma_read_channel(desc, &channel, &cfg);\r
+\r
+ cfg.cfg.bitfield.dam = XDMAC_CC_DAM_INCREMENTED_AM\r
+ >> XDMAC_CC_DAM_Pos;\r
+ cfg.dest_addr = buffer->data;\r
+ cfg.ublock_size = buffer->size;\r
+ cfg.block_size = 0;\r
+ xdmad_configure_transfer(channel, &cfg, 0, 0);\r
+ xdmad_set_callback(channel, _usartd_xdmad_callback_wrapper,\r
+ (void*)desc);\r
+\r
+ l2cc_clean_region(desc->region_start, desc->region_end);\r
+\r
+ xdmad_start_transfer(channel);\r
+}\r
+\r
+static void _usartd_init_dma_write_channel(const struct _usart_desc* desc,\r
+ struct _xdmad_channel** channel,\r
+ struct _xdmad_cfg* cfg)\r
+{\r
+ assert(cfg);\r
+ assert(channel);\r
+\r
+ uint32_t id = get_usart_id_from_addr(desc->addr);\r
+\r
+ memset(cfg, 0x0, sizeof(*cfg));\r
+\r
+ *channel =\r
+ xdmad_allocate_channel(XDMAD_PERIPH_MEMORY, id);\r
+ assert(*channel);\r
+\r
+ xdmad_prepare_channel(*channel);\r
+ cfg->cfg.uint32_value = XDMAC_CC_TYPE_PER_TRAN\r
+ | XDMAC_CC_DSYNC_MEM2PER\r
+ | XDMAC_CC_MEMSET_NORMAL_MODE\r
+ | XDMAC_CC_CSIZE_CHK_1\r
+ | XDMAC_CC_DWIDTH_BYTE\r
+ | XDMAC_CC_DIF_AHB_IF1\r
+ | XDMAC_CC_SIF_AHB_IF0\r
+ | XDMAC_CC_DAM_FIXED_AM;\r
+\r
+ cfg->dest_addr = (void*)&desc->addr->US_THR;\r
+}\r
+\r
+static void _usartd_dma_write(const struct _usart_desc* desc,\r
+ struct _buffer* buffer)\r
+{\r
+ struct _xdmad_channel* channel = NULL;\r
+ struct _xdmad_cfg cfg;\r
+\r
+ _usartd_init_dma_write_channel(desc, &channel, &cfg);\r
+\r
+ cfg.cfg.bitfield.sam = XDMAC_CC_SAM_INCREMENTED_AM\r
+ >> XDMAC_CC_SAM_Pos;\r
+ cfg.src_addr = buffer->data;\r
+ cfg.ublock_size = buffer->size;\r
+ cfg.block_size = 0;\r
+ xdmad_configure_transfer(channel, &cfg, 0, 0);\r
+ xdmad_set_callback(channel, _usartd_xdmad_callback_wrapper,\r
+ (void*)desc);\r
+\r
+ l2cc_clean_region(desc->region_start, desc->region_end);\r
+\r
+ xdmad_start_transfer(channel);\r
+}\r
+\r
+void usartd_configure(struct _usart_desc* desc)\r
+{\r
+ uint32_t id = get_usart_id_from_addr(desc->addr);\r
+ assert(id < ID_PERIPH_COUNT);\r
+\r
+#ifdef CONFIG_HAVE_FLEXCOM\r
+ Flexcom* flexcom = get_flexcom_addr_from_id(id);\r
+ if (flexcom) {\r
+ flexcom_select(flexcom, FLEX_MR_OPMODE_USART);\r
+ }\r
+#endif\r
+ pmc_enable_peripheral(id);\r
+ usart_configure(desc->addr, desc->mode, desc->baudrate);\r
+\r
+#ifdef CONFIG_HAVE_USART_FIFO\r
+ if (desc->transfert_mode == USARTD_MODE_FIFO) {\r
+ uint32_t fifo_size = get_peripheral_fifo_depth(desc->addr);\r
+ uint32_t tx_thres = fifo_size >> 1;\r
+ uint32_t rx_thres1 = (fifo_size >> 1) + (fifo_size >> 2);\r
+ uint32_t rx_thres2 = (fifo_size >> 1) - (fifo_size >> 2);\r
+ usart_fifo_configure(desc->addr, tx_thres, rx_thres1, rx_thres2,\r
+ US_FMR_RXRDYM_ONE_DATA | US_FMR_TXRDYM_FOUR_DATA);\r
+ }\r
+#endif\r
+}\r
+\r
+uint32_t usartd_transfert(struct _usart_desc* desc, struct _buffer* rx,\r
+ struct _buffer* tx, usartd_callback_t cb,\r
+ void* user_args)\r
+{\r
+ uint32_t i = 0;\r
+\r
+ desc->callback = cb;\r
+ desc->cb_args = user_args;\r
+\r
+ if (mutex_try_lock(&desc->mutex)) {\r
+ return USARTD_ERROR_LOCK;\r
+ }\r
+\r
+ switch (desc->transfert_mode) {\r
+ case USARTD_MODE_POLLING:\r
+ if (tx) {\r
+ for (i = 0; i < tx->size; ++i) {\r
+ usart_put_char(desc->addr, tx->data[i]);\r
+ }\r
+ }\r
+ if (rx) {\r
+ for (i = 0; i < rx->size; ++i) {\r
+ rx->data[i] = usart_get_char(desc->addr);\r
+ }\r
+ }\r
+ mutex_free(&desc->mutex);\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ break;\r
+ case USARTD_MODE_DMA:\r
+ if (!(rx || tx)) {\r
+ return USARTD_ERROR_DUPLEX;\r
+ }\r
+\r
+ if (tx) {\r
+ if (tx->size < USARTD_DMA_THRESHOLD) {\r
+ for (i = 0; i < tx->size; ++i) {\r
+ usart_put_char(desc->addr, tx->data[i]);\r
+ }\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ mutex_free(&desc->mutex);\r
+ } else {\r
+ desc->region_start = (uint32_t)tx->data;\r
+ desc->region_end = desc->region_start\r
+ + tx->size;\r
+ _usartd_dma_write(desc, tx);\r
+ }\r
+ } else if (rx) {\r
+ if (rx->size < USARTD_DMA_THRESHOLD) {\r
+ for (i = 0; i < rx->size; ++i) {\r
+ rx->data[i] = usart_get_char(desc->addr);\r
+ }\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ mutex_free(&desc->mutex);\r
+ } else {\r
+ desc->region_start = (uint32_t)rx->data;\r
+ desc->region_end = desc->region_start\r
+ + rx->size;\r
+ _usartd_dma_read(desc, rx);\r
+ }\r
+ } else {\r
+ mutex_free(&desc->mutex);\r
+ }\r
+ break;\r
+#ifdef CONFIG_HAVE_USART_FIFO\r
+ case USARTD_MODE_FIFO:\r
+ if (tx) {\r
+ usart_write_stream(desc->addr, tx->data, tx->size);\r
+ }\r
+ if (rx) {\r
+ usart_read_stream(desc->addr, rx->data, rx->size);\r
+ }\r
+ mutex_free(&desc->mutex);\r
+ if (cb)\r
+ cb(desc, user_args);\r
+ break;\r
+#endif\r
+ default:\r
+ trace_debug("Unkown mode");\r
+ }\r
+\r
+ return USARTD_SUCCESS;\r
+}\r
+\r
+void usartd_finish_transfert_callback(struct _usart_desc* desc,\r
+ void* user_args)\r
+{\r
+ (void)user_args;\r
+ usartd_finish_transfert(desc);\r
+}\r
+\r
+void usartd_finish_transfert(struct _usart_desc* desc)\r
+{\r
+ mutex_free(&desc->mutex);\r
+}\r
+\r
+uint32_t usartd_is_busy(const struct _usart_desc* desc)\r
+{\r
+ return mutex_is_locked(&desc->mutex);\r
+}\r
+\r
+void usartd_wait_transfert(const struct _usart_desc* desc)\r
+{\r
+ while (mutex_is_locked(&desc->mutex));\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef USARTD_HEADER__\r
+#define USARTD_HEADER__\r
+\r
+#include "mutex.h"\r
+#include "io.h"\r
+\r
+#define USARTD_SUCCESS (0)\r
+#define USARTD_INVALID_ID (1)\r
+#define USARTD_INVALID_BITRATE (2)\r
+#define USARTD_ERROR_LOCK (3)\r
+#define USARTD_ERROR_DUPLEX (4)\r
+\r
+struct _usart_desc;\r
+\r
+typedef void (*usartd_callback_t)(struct _usart_desc* spid, void* args);\r
+\r
+struct _usart_desc\r
+{\r
+ Usart* addr;\r
+ uint32_t mode;\r
+ uint32_t baudrate;\r
+ uint8_t transfert_mode;\r
+ /* implicit internal padding is mandatory here */\r
+ mutex_t mutex;\r
+ uint32_t region_start;\r
+ uint32_t region_end;\r
+ usartd_callback_t callback;\r
+ void* cb_args;\r
+};\r
+\r
+enum _usartd_trans_mode\r
+{\r
+ USARTD_MODE_POLLING,\r
+ USARTD_MODE_FIFO,\r
+ USARTD_MODE_DMA\r
+};\r
+\r
+extern void usartd_configure(struct _usart_desc* desc);\r
+extern uint32_t usartd_transfert(struct _usart_desc* desc, struct _buffer* rx,\r
+ struct _buffer* tx, usartd_callback_t cb,\r
+ void* user_args);\r
+extern void usartd_finish_transfert_callback(struct _usart_desc* desc,\r
+ void* user_args);\r
+extern void usartd_finish_transfert(struct _usart_desc* desc);\r
+extern uint32_t usartd_is_busy(const struct _usart_desc* desc);\r
+extern void usartd_wait_transfert(const struct _usart_desc* desc);\r
+\r
+#endif /* USARTD_HEADER__ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of Watchdog Timer (WDT) controller.\r
+ *\r
+ */\r
+\r
+/** \addtogroup wdt_module Working with WDT\r
+ * \section Purpose\r
+ * The WDT driver provides the interface to configure and use the WDT\r
+ * peripheral.\r
+ *\r
+ * The WDT can be used to prevent system lock-up if the software becomes\r
+ * trapped in a deadlock. It can generate a general reset or a processor\r
+ * reset only. It is clocked by slow clock divided by 128.\r
+ *\r
+ * The WDT is running at reset with 16 seconds watchdog period (slow clock at 32.768 kHz)\r
+ * and external reset generation enabled. The user must either disable it or\r
+ * reprogram it to meet the application requires.\r
+ *\r
+ * \section Usage\r
+ * To use the WDT, the user could follow these few steps:\r
+ * <ul>\r
+ * <li>Enable watchdog with given mode using \ref wdt_enable().\r
+ * <li>Restart the watchdog using \ref wdt_restart() within the watchdog period.\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the WDT section of the\r
+ * Datasheet.\r
+ *\r
+ * \note\r
+ * The Watchdog Mode Register (WDT_MR) can be written only once.\n\r
+ *\r
+ * Related files :\n\r
+ * \ref wdt.c\n\r
+ * \ref wdt.h.\n\r
+ */\r
+/*@{*/\r
+/*@}*/\r
+\r
+/*---------------------------------------------------------------------------\r
+ * Headers\r
+ *---------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/wdt.h"\r
+#include <stdio.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static uint32_t _wdt_compute_period(uint32_t period)\r
+{\r
+ uint32_t value = period * (pmc_get_slow_clock() >> 7) / 1000;\r
+ if (value > 0xfff)\r
+ value = 0xfff;\r
+ return value;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void wdt_enable(uint32_t mode, uint32_t delta, uint32_t counter)\r
+{\r
+ WDT->WDT_MR = (mode & ~(WDT_MR_WDDIS | WDT_MR_WDD_Msk | WDT_MR_WDV_Msk)) |\r
+ WDT_MR_WDD(_wdt_compute_period(delta)) |\r
+ WDT_MR_WDV(_wdt_compute_period(counter));\r
+}\r
+\r
+void wdt_disable(void)\r
+{\r
+ WDT->WDT_MR = WDT_MR_WDDIS;\r
+}\r
+\r
+void wdt_restart()\r
+{\r
+ WDT->WDT_CR = WDT_CR_KEY_PASSWD | WDT_CR_WDRSTT;\r
+}\r
+\r
+uint32_t wdt_get_status(void)\r
+{\r
+ return WDT->WDT_SR & (WDT_SR_WDUNF | WDT_SR_WDERR);\r
+}\r
+\r
+uint32_t wdt_get_counter_value(void)\r
+{\r
+ return (WDT->WDT_MR & WDT_MR_WDV_Msk) >> WDT_MR_WDV_Pos;\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ * Interface for Watchdog Timer (WDT) controller.\r
+ *\r
+ * \section Usage\r
+ * -# Enable watchdog with given mode using \ref wdt_enable().\r
+ * -# Disable watchdog using \ref wdt_disable()\r
+ * -# Restart the watchdog using \ref wdt_restart().\r
+ * -# Get watchdog status using \ref wdt_get_status().\r
+ */\r
+\r
+#ifndef _WDT_H_\r
+#define _WDT_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * \brief Enable watchdog with given mode.\r
+ *\r
+ * \note The Watchdog Mode Register (WDT_MR) can be written only once.\r
+ * Only a processor reset resets it.\r
+ *\r
+ * \param mode WDT mode to be set\r
+ * \param delta WDT delta value\r
+ * \param counter WDT counter value\r
+ */\r
+extern void wdt_enable(uint32_t mode, uint32_t delta, uint32_t counter);\r
+\r
+/**\r
+ * \brief Disable watchdog.\r
+ *\r
+ * \note The Watchdog Mode Register (WDT_MR) can be written only once.\r
+ * Only a processor reset resets it.\r
+ */\r
+extern void wdt_disable(void);\r
+\r
+/**\r
+ * \brief Watchdog restart.\r
+ */\r
+extern void wdt_restart(void);\r
+\r
+/**\r
+ * \brief Watchdog get status.\r
+ */\r
+extern uint32_t wdt_get_status(void);\r
+\r
+/**\r
+ * \brief Watchdog get counter value.\r
+ */\r
+extern uint32_t wdt_get_counter_value(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _WDT_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of xDMA controller (XDMAC).\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/xdmac.h"\r
+\r
+#include <assert.h>\r
+#include "compiler.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+Xdmac *xdmac_get_instance(uint32_t index)\r
+{\r
+ assert(index < XDMAC_CONTROLLERS);\r
+ if (index == 0)\r
+ return XDMAC0;\r
+ else if (index == 1)\r
+ return XDMAC1;\r
+ else\r
+ return NULL;\r
+}\r
+\r
+uint32_t xdmac_get_periph_id(Xdmac *xdmac)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ if (xdmac == XDMAC0)\r
+ return ID_XDMAC0;\r
+ else if (xdmac == XDMAC1)\r
+ return ID_XDMAC1;\r
+ else\r
+ return ID_PERIPH_COUNT;\r
+}\r
+\r
+uint32_t xdmac_get_type(Xdmac *xdmac)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ return xdmac->XDMAC_GTYPE;\r
+}\r
+\r
+uint32_t xdmac_get_config(Xdmac *xdmac)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ return xdmac->XDMAC_GCFG;\r
+}\r
+\r
+uint32_t xdmac_get_arbiter(Xdmac *xdmac)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ return xdmac->XDMAC_GWAC;\r
+}\r
+\r
+void xdmac_enable_global_it(Xdmac *xdmac, uint32_t int_mask)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ xdmac->XDMAC_GIE = int_mask;\r
+}\r
+\r
+void xdmac_disable_global_it(Xdmac *xdmac, uint32_t int_mask)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ xdmac->XDMAC_GID = int_mask;\r
+}\r
+\r
+uint32_t xdmac_get_global_it_mask(Xdmac *xdmac)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ return xdmac->XDMAC_GIM;\r
+}\r
+\r
+uint32_t xdmac_get_global_isr(Xdmac *xdmac)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ return xdmac->XDMAC_GIS;\r
+}\r
+\r
+uint32_t xdmac_get_masked_global_isr(Xdmac *xdmac)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ uint32_t mask = xdmac->XDMAC_GIM;\r
+\r
+ return xdmac->XDMAC_GIS & mask;\r
+}\r
+\r
+void xdmac_enable_channel(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_GE |= XDMAC_GE_EN0 << channel;\r
+}\r
+\r
+void xdmac_enable_channels(Xdmac *xdmac, uint8_t channel_mask)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ xdmac->XDMAC_GE = channel_mask;\r
+}\r
+\r
+void xdmac_disable_channel(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_GD |= XDMAC_GD_DI0 << channel;\r
+}\r
+\r
+void xdmac_disable_channels(Xdmac *xdmac, uint8_t channel_mask)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ xdmac->XDMAC_GD = channel_mask;\r
+}\r
+\r
+uint32_t xdmac_get_global_channel_status(Xdmac *xdmac)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ return xdmac->XDMAC_GS;\r
+}\r
+\r
+void xdmac_suspend_read_channel(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_GRS |= XDMAC_GRS_RS0 << channel;\r
+}\r
+\r
+void xdmac_suspend_write_channel(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_GWS |= XDMAC_GWS_WS0 << channel;\r
+}\r
+\r
+void xdmac_suspend_read_write_channel(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_GRWS |= XDMAC_GRWS_RWS0 << channel;\r
+}\r
+\r
+void xdmac_resume_read_write_channel(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_GRWR |= XDMAC_GRWR_RWR0 << channel;\r
+}\r
+\r
+void xdmac_software_transfer_request(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_GSWR |= (XDMAC_GSWR_SWREQ0 << channel);\r
+}\r
+\r
+uint32_t xdmac_get_software_transfer_status(Xdmac *xdmac)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+\r
+ return xdmac->XDMAC_GSWS;\r
+}\r
+\r
+void xdmac_software_flush_request(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_GSWF |= XDMAC_GSWF_SWF0 << channel;\r
+}\r
+\r
+void xdmac_enable_channel_it(Xdmac *xdmac, uint8_t channel, uint32_t int_mask)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CIE = int_mask;\r
+}\r
+\r
+void xdmac_disable_channel_it(Xdmac *xdmac, uint8_t channel, uint32_t int_mask)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CID = int_mask;\r
+}\r
+\r
+uint32_t xdmac_get_channel_it_mask(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ return xdmac->XDMAC_CHID[channel].XDMAC_CIM;\r
+}\r
+\r
+uint32_t xdmac_get_channel_isr(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ return xdmac->XDMAC_CHID[channel].XDMAC_CIS;\r
+}\r
+\r
+uint32_t xdmac_get_masked_channel_isr(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ uint32_t mask = xdmac->XDMAC_CHID[channel].XDMAC_CIM;\r
+\r
+ return xdmac->XDMAC_CHID[channel].XDMAC_CIS & mask;\r
+}\r
+\r
+void xdmac_set_src_addr(Xdmac *xdmac, uint8_t channel, void *addr)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CSA = (uint32_t)addr;\r
+}\r
+\r
+void xdmac_set_dest_addr(Xdmac *xdmac, uint8_t channel, void *addr)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CDA = (uint32_t)addr;\r
+}\r
+\r
+void xdmac_set_descriptor_addr(Xdmac *xdmac, uint8_t channel, void *addr,\r
+ uint32_t ndaif)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CNDA = (((uint32_t)addr) & 0xFFFFFFFC) | ndaif;\r
+}\r
+\r
+void xdmac_set_descriptor_control(Xdmac *xdmac, uint8_t channel,\r
+ uint32_t config)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CNDC = config;\r
+}\r
+\r
+void xdmac_set_microblock_control(Xdmac *xdmac, uint8_t channel,\r
+ uint32_t ublen)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CUBC = ublen;\r
+}\r
+\r
+void xdmac_set_block_control(Xdmac *xdmac, uint8_t channel, uint32_t blen)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CBC = blen;\r
+}\r
+\r
+void xdmac_set_channel_config(Xdmac *xdmac, uint8_t channel, uint32_t config)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CC = config;\r
+}\r
+\r
+uint32_t xdmac_get_channel_config(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ return xdmac->XDMAC_CHID[channel].XDMAC_CC;\r
+}\r
+\r
+void xdmac_set_data_stride_mem_pattern(Xdmac *xdmac, uint8_t channel,\r
+ uint32_t dds_msp)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CDS_MSP = dds_msp;\r
+}\r
+\r
+void xdmac_set_src_microblock_stride(Xdmac *xdmac, uint8_t channel,\r
+ uint32_t subs)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CSUS = subs;\r
+}\r
+\r
+void xdmac_set_dest_microblock_stride(Xdmac *xdmac, uint8_t channel,\r
+ uint32_t dubs)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ xdmac->XDMAC_CHID[channel].XDMAC_CDUS = dubs;\r
+}\r
+\r
+uint32_t xdmac_get_channel_dest_addr(Xdmac *xdmac, uint8_t channel)\r
+{\r
+ assert(xdmac == XDMAC0 || xdmac == XDMAC1);\r
+ assert(channel < XDMAC_CHANNELS);\r
+\r
+ return xdmac->XDMAC_CHID[channel].XDMAC_CDA;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup dmac_module Working with DMAC\r
+ *\r
+ * \section Usage\r
+ * <ul>\r
+ * <li> Enable or disable DMAC channel with XDMAC_EnableChannel() and XDMAC_EnableChannels() or XDMAC_DisableChannel() and XDMAC_DisableChannels().</li>\r
+ * <li> Enable or disable %DMA interrupt using XDMAC_EnableGIt() and XDMAC_EnableChannelIt() or XDMAC_DisableGIt() and XDMAC_DisableChannelIt().</li>\r
+ * <li> Get %DMA interrupt status by XDMAC_GetChannelIsr() and XDMAC_GetMaskChannelIsr().</li>\r
+ * <li> Enable or disable specified %DMA channel with XDMAC_EnableChannel() or XDMAC_DisableChannel().</li>\r
+ * <li> Suspend or resume specified %DMA channel with XDMAC_SuspendReadChannel(), XDMAC_SuspendWriteChannel() and XDMAC_SuspendReadWriteChannel() or XDMAC_ResumeReadWriteChannel().</li>\r
+ * <li> Get %DMA channel status by XDMAC_GetGlobalChStatus().</li>\r
+ * <li> Configure source and/or destination start address with XDMAC_SetSourceAddr() and/or XDMAC_SetDestinationAddr().</li>\r
+ * <li> Set %DMA descriptor address using XDMAC_SetDescriptorAddr().</li>\r
+ * <li> Set source transfer buffer size with XDMAC_SetMicroblockControl() or XDMAC_SetBlockControl().</li>\r
+ * <li> Configure source and destination memory pattern with XDMAC_SetDataStride_MemPattern().</li>\r
+ * <li> Configure source or destination Microblock stride with XDMAC_SetSourceMicroBlockStride() or XDMAC_SetDestinationMicroBlockStride().</li>\r
+ * </ul>\r
+ *\r
+ * For more accurate information, please look at the DMAC section of the\r
+ * Datasheet.\r
+ *\r
+ * \sa \ref dmad_module\r
+ *\r
+ * Related files :\n\r
+ * \ref xdmac.c\n\r
+ * \ref xdmac.h\n\r
+ *\r
+ */\r
+\r
+#ifndef _XDMAC_H_\r
+#define _XDMAC_H_\r
+\r
+/**@{*/\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup dmac_defines DMAC Definitions\r
+ * @{\r
+ */\r
+\r
+/** Number of DMA channels */\r
+#define XDMAC_CONTROLLERS 2\r
+\r
+/** Number of DMA channels */\r
+#define XDMAC_CHANNELS (XDMACCHID_NUMBER)\r
+\r
+/** Max DMA single transfer size */\r
+#define XDMAC_MAX_BT_SIZE 0xFFFF\r
+\r
+/** @}*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Macro\r
+ *----------------------------------------------------------------------------*/\r
+#define XDMA_GET_DATASIZE(size) ((size==0)? XDMAC_CC_DWIDTH_BYTE : \\r
+ ((size==1)? XDMAC_CC_DWIDTH_HALFWORD : \\r
+ ((size==2)? XDMAC_CC_DWIDTH_WORD : XDMAC_CC_DWIDTH_DWORD )))\r
+#define XDMA_GET_CC_SAM(s) ((s==0)? XDMAC_CC_SAM_FIXED_AM : \\r
+ ((s==1)? XDMAC_CC_SAM_INCREMENTED_AM : \\r
+ ((s==2)? XDMAC_CC_SAM_UBS_AM : XDMAC_CC_SAM_UBS_DS_AM )))\r
+#define XDMA_GET_CC_DAM(d) ((d==0)? XDMAC_CC_DAM_FIXED_AM : \\r
+ ((d==1)? XDMAC_CC_DAM_INCREMENTED_AM : \\r
+ ((d==2)? XDMAC_CC_DAM_UBS_AM : XDMAC_CC_DAM_UBS_DS_AM )))\r
+#define XDMA_GET_CC_MEMSET(m) ((m==0)? XDMAC_CC_MEMSET_NORMAL_MODE : XDMAC_CC_MEMSET_HW_MODE)\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup dmac_functions XDMAC Functions\r
+ * @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \brief Enable the XDMAC peripheral clock\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ */\r
+extern Xdmac *xdmac_get_instance(uint32_t index);\r
+\r
+/**\r
+ * \brief Get the XDMAC peripheral ID for a given XDMAC instance\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ */\r
+extern uint32_t xdmac_get_periph_id(Xdmac *xdmac);\r
+\r
+/**\r
+ * \brief Get XDMAC global type.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ */\r
+extern uint32_t xdmac_get_type(Xdmac *xdmac);\r
+\r
+/**\r
+ * \brief Get XDMAC global configuration.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ */\r
+extern uint32_t xdmac_get_config(Xdmac *xdmac);\r
+\r
+/**\r
+ * \brief Get XDMAC global weighted arbiter configuration.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ */\r
+extern uint32_t xdmac_get_arbiter(Xdmac *xdmac);\r
+\r
+/**\r
+ * \brief Enables XDMAC global interrupt.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param int_mask IT to be enabled.\r
+ */\r
+extern void xdmac_enable_global_it(Xdmac *xdmac, uint32_t int_mask);\r
+\r
+/**\r
+ * \brief Disables XDMAC global interrupt\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param int_mask IT to be enabled\r
+ */\r
+extern void xdmac_disable_global_it(Xdmac *xdmac, uint32_t int_mask);\r
+\r
+/**\r
+ * \brief Get XDMAC global interrupt mask.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ */\r
+extern uint32_t xdmac_get_global_it_mask(Xdmac *xdmac);\r
+\r
+/**\r
+ * \brief Get XDMAC global interrupt status.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ */\r
+extern uint32_t xdmac_get_global_isr(Xdmac *xdmac);\r
+\r
+/**\r
+ * \brief Get XDMAC masked global interrupt.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ */\r
+extern uint32_t xdmac_get_masked_global_isr(Xdmac *xdmac);\r
+\r
+/**\r
+ * \brief enables the relevant channel of given XDMAC.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern void xdmac_enable_channel(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief enables the relevant channels of given XDMAC.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel_mask Channels bitmap.\r
+ */\r
+extern void xdmac_enable_channels(Xdmac *xdmac, uint8_t channel_mask);\r
+\r
+/**\r
+ * \brief Disables the relevant channel of given XDMAC.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern void xdmac_disable_channel(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Disables the relevant channels of given XDMAC.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel_mask Channels bitmap.\r
+ */\r
+extern void xdmac_disable_channels(Xdmac *xdmac, uint8_t channel_mask);\r
+\r
+/**\r
+ * \brief Get Global channel status of given XDMAC.\r
+ * \note: When set to 1, this bit indicates that the channel x is enabled. If a channel disable request is issued, this bit remains asserted\r
+ until pending transaction is completed.\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ */\r
+extern uint32_t xdmac_get_global_channel_status(Xdmac *xdmac);\r
+\r
+/**\r
+ * \brief Suspend the relevant channel's read.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern void xdmac_suspend_read_channel(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Suspend the relevant channel's write.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern void xdmac_suspend_write_channel(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Suspend the relevant channel's read & write.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern void xdmac_suspend_read_write_channel(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Resume the relevant channel's read & write.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern void xdmac_resume_read_write_channel(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Set software transfer request on the relevant channel.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern void xdmac_software_transfer_request(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Get software transfer status of the relevant channel.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ */\r
+extern uint32_t xdmac_get_software_transfer_status(Xdmac *xdmac);\r
+\r
+/**\r
+ * \brief Set software flush request on the relevant channel.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern void xdmac_software_flush_request(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Disable interrupt with mask on the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param int_mask Interrupt mask.\r
+ */\r
+extern void xdmac_enable_channel_it(Xdmac *xdmac, uint8_t channel, uint32_t int_mask);\r
+\r
+/**\r
+ * \brief Enable interrupt with mask on the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param int_mask Interrupt mask.\r
+ */\r
+extern void xdmac_disable_channel_it(Xdmac *xdmac, uint8_t channel, uint32_t int_mask);\r
+\r
+/**\r
+ * \brief Get interrupt mask for the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern uint32_t xdmac_get_channel_it_mask(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Get interrupt status for the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern uint32_t xdmac_get_channel_isr(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Get masked interrupt status for the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern uint32_t xdmac_get_masked_channel_isr(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Set source address for the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param addr Source address.\r
+ */\r
+extern void xdmac_set_src_addr(Xdmac *xdmac, uint8_t channel, void *addr);\r
+\r
+/**\r
+ * \brief Set destination address for the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param addr Destination address.\r
+ */\r
+extern void xdmac_set_dest_addr(Xdmac *xdmac, uint8_t channel, void *addr);\r
+\r
+/**\r
+ * \brief Set next descriptor's address & interface for the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param addr Address of next descriptor.\r
+ * \param nda Next Descriptor Interface.\r
+ */\r
+extern void xdmac_set_descriptor_addr(Xdmac *xdmac, uint8_t channel, void *addr, uint32_t ndaif);\r
+\r
+/**\r
+ * \brief Set next descriptor's configuration for the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param config Configuration of next descriptor.\r
+ */\r
+extern void xdmac_set_descriptor_control(Xdmac *xdmac, uint8_t channel, uint32_t config);\r
+\r
+/**\r
+ * \brief Set microblock length for the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param ublen Microblock length.\r
+ */\r
+extern void xdmac_set_microblock_control(Xdmac *xdmac, uint8_t channel, uint32_t ublen);\r
+\r
+/**\r
+ * \brief Set block length for the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param blen Block length.\r
+ */\r
+extern void xdmac_set_block_control(Xdmac *xdmac, uint8_t channel, uint32_t blen);\r
+\r
+/**\r
+ * \brief Set configuration for the relevant channel of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param config Channel configuration.\r
+ */\r
+extern void xdmac_set_channel_config(Xdmac *xdmac, uint8_t channel, uint32_t config);\r
+\r
+/**\r
+ * \brief Get the relevant channel's configuration of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern uint32_t xdmac_get_channel_config(Xdmac *xdmac, uint8_t channel);\r
+\r
+/**\r
+ * \brief Set the relevant channel's data stride memory pattern of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param dds_msp Data stride memory pattern.\r
+ */\r
+extern void xdmac_set_data_stride_mem_pattern(Xdmac *xdmac, uint8_t channel,\r
+ uint32_t dds_msp);\r
+\r
+/**\r
+ * \brief Set the relevant channel's source microblock stride of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param subs Source microblock stride.\r
+ */\r
+extern void xdmac_set_src_microblock_stride(Xdmac *xdmac, uint8_t channel, uint32_t subs);\r
+\r
+/**\r
+ * \brief Set the relevant channel's destination microblock stride of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ * \param dubs Destination microblock stride.\r
+ */\r
+extern void xdmac_set_dest_microblock_stride(Xdmac *xdmac, uint8_t channel, uint32_t dubs);\r
+\r
+/**\r
+ * \brief Get the relevant channel's destination address of given XDMA.\r
+ *\r
+ * \param xdmac Pointer to the XDMAC instance.\r
+ * \param channel Particular channel number.\r
+ */\r
+extern uint32_t xdmac_get_channel_dest_addr(Xdmac *xdmac, uint8_t channel);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/** @}*//**@}*/\r
+\r
+#endif /* _XDMAC_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup xdmad_module\r
+ *\r
+ * \section Xdma xDma Configuration Usage\r
+ *\r
+ * To configure a XDMA channel, the user has to follow these few steps :\r
+ * <ul>\r
+ * <li> Initialize a XDMA driver instance by XDMAD_Initialize().</li>\r
+ * <li> choose an available (disabled) channel using XDMAD_AllocateChannel().</li>\r
+ * <li> After the XDMAC selected channel has been programmed, XDMAD_PrepareChannel() is to enable\r
+ * clock and dma peripheral of the DMA, and set Configuration register to set up the transfer type\r
+ * (memory or non-memory peripheral for source and destination) and flow control device.</li>\r
+ * <li> Invoke XDMAD_StartTransfer() to start DMA transfer or XDMAD_StopTransfer() to force stop DMA transfer.</li>\r
+ * <li> Once the buffer of data is transferred, XDMAD_IsTransferDone() checks if DMA transfer is finished.</li>\r
+ * <li> XDMAD_Handler() handles XDMA interrupt, and invoking XDMAD_SetCallback() if provided.</li>\r
+ * </ul>\r
+ *\r
+ * Related files:\n\r
+ * \ref xdmad.h\n\r
+ * \ref xdmad.c\n\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup dmad_functions\r
+ @{*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Includes\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "peripherals/aic.h"\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/xdmad.h"\r
+\r
+#include <assert.h>\r
+#include "compiler.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define XDMAD_CHANNELS (XDMAC_CONTROLLERS * XDMAC_CHANNELS)\r
+\r
+/** DMA state for channel */\r
+enum {\r
+ XDMAD_STATE_FREE = 0, /**< Free channel */\r
+ XDMAD_STATE_ALLOCATED, /**< Allocated to some peripheral */\r
+ XDMAD_STATE_STARTED, /**< DMA started */\r
+ XDMAD_STATE_DONE, /**< DMA transfer done */\r
+};\r
+\r
+/** DMA driver channel */\r
+struct _xdmad_channel\r
+{\r
+ Xdmac *xdmac; /**< XDMAC instance */\r
+ uint32_t id; /**< Channel ID */\r
+ xdmad_callback_t callback; /**< Callback */\r
+ void *user_arg; /**< Callback argument */\r
+ uint8_t src_txif; /**< Source TX Interface ID */\r
+ uint8_t src_rxif; /**< Source RX Interface ID */\r
+ uint8_t dest_txif; /**< Destination TX Interface ID */\r
+ uint8_t dest_rxif; /**< Destination RX Interface ID */\r
+ volatile uint8_t state; /**< Channel State */\r
+};\r
+\r
+/** DMA driver instance */\r
+struct _xdmad {\r
+ struct _xdmad_channel channels[XDMAD_CHANNELS];\r
+ bool polling;\r
+ uint8_t polling_timeout;\r
+};\r
+\r
+static struct _xdmad _xdmad;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static inline struct _xdmad_channel *_xdmad_channel(uint32_t controller, uint32_t channel)\r
+{\r
+ return &_xdmad.channels[controller * XDMAC_CHANNELS + channel];\r
+}\r
+\r
+/**\r
+ * \brief xDMA interrupt handler\r
+ * \param pXdmad Pointer to DMA driver instance.\r
+ */\r
+static void xdmad_handler(void)\r
+{\r
+ uint32_t cont;\r
+\r
+ for (cont= 0; cont< XDMAC_CONTROLLERS; cont++) {\r
+ uint32_t chan, gis, gcs;\r
+\r
+ Xdmac *xdmac = xdmac_get_instance(cont);\r
+\r
+ gis = xdmac_get_global_isr(xdmac);\r
+ if ((gis & 0xFFFF) == 0)\r
+ continue;\r
+\r
+ gcs = xdmac_get_global_channel_status(xdmac);\r
+ for (chan = 0; chan < XDMAC_CHANNELS; chan++) {\r
+ struct _xdmad_channel *channel;\r
+ bool exec = false;\r
+\r
+ if (!(gis & (1 << chan)))\r
+ continue;\r
+\r
+ channel = _xdmad_channel(cont, chan);\r
+ if (channel->state == XDMAD_STATE_FREE)\r
+ continue;\r
+\r
+ if (!(gcs & (1 << chan))) {\r
+ uint32_t cis = xdmac_get_channel_isr(xdmac, chan);\r
+\r
+ if (cis & XDMAC_CIS_BIS) {\r
+ if (!(xdmac_get_channel_it_mask(xdmac, chan) & XDMAC_CIM_LIM)) {\r
+ channel->state = XDMAD_STATE_DONE;\r
+ exec = 1;\r
+ }\r
+ }\r
+\r
+ if (cis & XDMAC_CIS_LIS) {\r
+ channel->state = XDMAD_STATE_DONE;\r
+ exec = 1;\r
+ }\r
+\r
+ if (cis & XDMAC_CIS_DIS) {\r
+ channel->state = XDMAD_STATE_DONE;\r
+ exec = 1;\r
+ }\r
+ }\r
+\r
+ /* Execute callback */\r
+ if (exec && channel->callback) {\r
+ channel->callback(channel, channel->user_arg);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void xdmad_initialize(bool polling)\r
+{\r
+ uint32_t cont, chan;\r
+\r
+ _xdmad.polling = polling;\r
+\r
+ for (cont = 0; cont < XDMAC_CONTROLLERS; cont++) {\r
+ Xdmac* xdmac = xdmac_get_instance(cont);\r
+ for (chan = 0; chan < XDMAC_CHANNELS; chan++) {\r
+ xdmac_get_channel_isr(xdmac, chan);\r
+ struct _xdmad_channel *channel = _xdmad_channel(cont, chan);\r
+ channel->xdmac = xdmac;\r
+ channel->id = chan;\r
+ channel->callback = 0;\r
+ channel->user_arg = 0;\r
+ channel->src_txif = 0;\r
+ channel->src_rxif = 0;\r
+ channel->dest_txif = 0;\r
+ channel->dest_rxif = 0;\r
+ channel->state = XDMAD_STATE_FREE;\r
+ }\r
+\r
+ if (!polling) {\r
+ uint32_t pid = xdmac_get_periph_id(xdmac);\r
+ /* enable interrupts */\r
+ aic_set_source_vector(pid, xdmad_handler);\r
+ aic_enable(pid);\r
+ }\r
+ }\r
+}\r
+\r
+void xdmad_poll(void)\r
+{\r
+ if (_xdmad.polling)\r
+ xdmad_handler();\r
+}\r
+\r
+struct _xdmad_channel *xdmad_allocate_channel(uint8_t src, uint8_t dest)\r
+{\r
+ uint32_t i;\r
+\r
+ /* Reject peripheral to peripheral transfers */\r
+ if (src != XDMAD_PERIPH_MEMORY && dest != XDMAD_PERIPH_MEMORY) {\r
+ return NULL;\r
+ }\r
+\r
+ for (i = 0; i < XDMAD_CHANNELS; i++) {\r
+ struct _xdmad_channel *channel = &_xdmad.channels[i];\r
+ Xdmac *xdmac = channel->xdmac;\r
+\r
+ if (channel->state == XDMAD_STATE_FREE) {\r
+ /* Check if source peripheral matches this channel controller */\r
+ if (src != XDMAD_PERIPH_MEMORY)\r
+ if (!is_peripheral_on_xdma_controller(src, xdmac))\r
+ continue;\r
+\r
+ /* Check if destination peripheral matches this channel controller */\r
+ if (dest != XDMAD_PERIPH_MEMORY)\r
+ if (!is_peripheral_on_xdma_controller(dest, xdmac))\r
+ continue;\r
+\r
+ /* Allocate the channel */\r
+ channel->state = XDMAD_STATE_ALLOCATED;\r
+ channel->src_txif = get_peripheral_xdma_channel(src, xdmac, true);\r
+ channel->src_rxif = get_peripheral_xdma_channel(src, xdmac, false);\r
+ channel->dest_txif = get_peripheral_xdma_channel(dest, xdmac, true);\r
+ channel->dest_rxif = get_peripheral_xdma_channel(dest, xdmac, false);\r
+\r
+ return channel;\r
+ }\r
+ }\r
+ return NULL;\r
+}\r
+\r
+uint32_t xdmad_free_channel(struct _xdmad_channel *channel)\r
+{\r
+ switch (channel->state) {\r
+ case XDMAD_STATE_STARTED:\r
+ return XDMAD_BUSY;\r
+ case XDMAD_STATE_ALLOCATED:\r
+ case XDMAD_STATE_DONE:\r
+ channel->state = XDMAD_STATE_FREE;\r
+ break;\r
+ }\r
+ return XDMAD_OK;\r
+}\r
+\r
+uint32_t xdmad_set_callback(struct _xdmad_channel *channel,\r
+ xdmad_callback_t callback, void *user_arg)\r
+{\r
+ if (channel->state == XDMAD_STATE_FREE)\r
+ return XDMAD_ERROR;\r
+ else if (channel->state == XDMAD_STATE_STARTED)\r
+ return XDMAD_BUSY;\r
+\r
+ channel->callback = callback;\r
+ channel->user_arg = user_arg;\r
+\r
+ return XDMAD_OK;\r
+}\r
+\r
+uint32_t xdmad_prepare_channel(struct _xdmad_channel *channel)\r
+{\r
+ Xdmac *xdmac = channel->xdmac;\r
+\r
+ if (channel->state == XDMAD_STATE_FREE)\r
+ return XDMAD_ERROR;\r
+ else if (channel->state == XDMAD_STATE_STARTED)\r
+ return XDMAD_BUSY;\r
+\r
+ /* Clear status */\r
+ xdmac_get_global_channel_status(xdmac);\r
+ xdmac_get_global_isr(xdmac);\r
+\r
+ /* Enable clock of the DMA peripheral */\r
+ pmc_enable_peripheral(xdmac_get_periph_id(xdmac));\r
+\r
+ /* Clear status */\r
+ xdmac_get_channel_isr(xdmac, channel->id);\r
+\r
+ /* Disables XDMAC interrupt for the given channel */\r
+ xdmac_disable_global_it(xdmac, -1);\r
+ xdmac_disable_channel_it(xdmac, channel->id, -1);\r
+\r
+ /* Disable the given dma channel */\r
+ xdmac_disable_channel(xdmac, channel->id);\r
+ xdmac_set_src_addr(xdmac, channel->id, 0);\r
+ xdmac_set_dest_addr(xdmac, channel->id, 0);\r
+ xdmac_set_block_control(xdmac, channel->id, 0);\r
+ xdmac_set_channel_config(xdmac, channel->id, XDMAC_CC_PROT_UNSEC);\r
+ xdmac_set_descriptor_addr(xdmac, channel->id, 0, 0);\r
+ xdmac_set_descriptor_control(xdmac, channel->id, 0);\r
+\r
+ return XDMAD_OK;\r
+}\r
+\r
+bool xdmad_is_transfer_done(struct _xdmad_channel *channel)\r
+{\r
+ return channel->state != XDMAD_STATE_STARTED;\r
+}\r
+\r
+uint32_t xdmad_configure_transfer(struct _xdmad_channel *channel,\r
+ struct _xdmad_cfg *cfg,\r
+ uint32_t desc_cntrl,\r
+ void *desc_addr)\r
+{\r
+ if (channel->state == XDMAD_STATE_FREE)\r
+ return XDMAD_ERROR;\r
+ else if (channel->state == XDMAD_STATE_STARTED)\r
+ return XDMAD_BUSY;\r
+\r
+ Xdmac *xdmac = channel->xdmac;\r
+\r
+ if (cfg->cfg.bitfield.dsync == XDMAC_CC_DSYNC_PER2MEM) {\r
+ cfg->cfg.bitfield.perid = channel->src_rxif;\r
+ } else {\r
+ cfg->cfg.bitfield.perid = channel->dest_txif;\r
+ }\r
+\r
+ /* Clear status */\r
+ xdmac_get_global_isr(xdmac);\r
+ xdmac_get_channel_isr(xdmac, channel->id);\r
+\r
+ if ((desc_cntrl & XDMAC_CNDC_NDE) == XDMAC_CNDC_NDE_DSCR_FETCH_EN) {\r
+ /* Linked List is enabled */\r
+ if ((desc_cntrl & XDMAC_CNDC_NDVIEW_Msk)\r
+ == XDMAC_CNDC_NDVIEW_NDV0) {\r
+ xdmac_set_channel_config(xdmac, channel->id,\r
+ cfg->cfg.uint32_value);\r
+ xdmac_set_src_addr(xdmac, channel->id, cfg->src_addr);\r
+ xdmac_set_dest_addr(xdmac, channel->id, cfg->dest_addr);\r
+ }\r
+ else if ((desc_cntrl & XDMAC_CNDC_NDVIEW_Msk)\r
+ == XDMAC_CNDC_NDVIEW_NDV1) {\r
+ xdmac_set_channel_config(xdmac, channel->id,\r
+ cfg->cfg.uint32_value);\r
+ }\r
+ xdmac_set_descriptor_addr(xdmac, channel->id, desc_addr, 0);\r
+ xdmac_set_descriptor_control(xdmac, channel->id, desc_cntrl);\r
+ xdmac_disable_channel_it(xdmac, channel->id, -1);\r
+ xdmac_enable_channel_it(xdmac, channel->id, XDMAC_CIE_LIE);\r
+ } else {\r
+ /* Linked List is disabled. */\r
+ xdmac_set_src_addr(xdmac, channel->id, cfg->src_addr);\r
+ xdmac_set_dest_addr(xdmac, channel->id, cfg->dest_addr);\r
+ xdmac_set_microblock_control(xdmac, channel->id, cfg->ublock_size);\r
+ xdmac_set_block_control(xdmac, channel->id,\r
+ cfg->block_size > 1 ? cfg->block_size : 0);\r
+ xdmac_set_data_stride_mem_pattern(xdmac, channel->id,\r
+ cfg->data_stride);\r
+ xdmac_set_src_microblock_stride(xdmac, channel->id,\r
+ cfg->src_ublock_stride);\r
+ xdmac_set_dest_microblock_stride(xdmac, channel->id,\r
+ cfg->dest_ublock_stride);\r
+ xdmac_set_channel_config(xdmac, channel->id, cfg->cfg.uint32_value);\r
+ xdmac_set_descriptor_addr(xdmac, channel->id, 0, 0);\r
+ xdmac_set_descriptor_control(xdmac, channel->id, 0);\r
+ xdmac_enable_channel_it(xdmac, channel->id,\r
+ XDMAC_CIE_BIE | XDMAC_CIE_DIE |\r
+ XDMAC_CIE_FIE | XDMAC_CIE_RBIE |\r
+ XDMAC_CIE_WBIE | XDMAC_CIE_ROIE);\r
+ }\r
+ return XDMAD_OK;\r
+}\r
+\r
+uint32_t xdmad_start_transfer(struct _xdmad_channel *channel)\r
+{\r
+ if (channel->state == XDMAD_STATE_FREE)\r
+ return XDMAD_ERROR;\r
+ else if (channel->state == XDMAD_STATE_STARTED)\r
+ return XDMAD_BUSY;\r
+\r
+ /* Change state to 'started' */\r
+ channel->state = XDMAD_STATE_STARTED;\r
+\r
+ /* Start DMA transfer */\r
+ xdmac_enable_channel(channel->xdmac, channel->id);\r
+ if (!_xdmad.polling) {\r
+ xdmac_enable_global_it(channel->xdmac, 1 << channel->id);\r
+ }\r
+\r
+ return XDMAD_OK;\r
+}\r
+\r
+uint32_t xdmad_stop_transfer(struct _xdmad_channel *channel)\r
+{\r
+ Xdmac *xdmac = channel->xdmac;\r
+\r
+ /* Disable channel */\r
+ xdmac_disable_channel(xdmac, channel->id);\r
+\r
+ /* Disable interrupts */\r
+ xdmac_disable_channel_it(xdmac, channel->id, -1);\r
+\r
+ /* Clear pending status */\r
+ xdmac_get_channel_isr(xdmac, channel->id);\r
+ xdmac_get_global_channel_status(xdmac);\r
+\r
+ /* Change state to 'allocated' */\r
+ channel->state = XDMAD_STATE_ALLOCATED;\r
+\r
+ return XDMAD_OK;\r
+}\r
+\r
+/**@}*/\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _XDMAD_H_\r
+#define _XDMAD_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Includes\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "peripherals/xdmac.h"\r
+\r
+#include <stdbool.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Consts\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup dmad_defines DMA Driver Defines\r
+ @{*/\r
+\r
+/** Pseudo Peripheral ID for memory transfers */\r
+#define XDMAD_PERIPH_MEMORY 0xFF\r
+\r
+/* XDMA_MBR_UBC */\r
+\r
+#define XDMA_UBC_NDE (0x1u << 24)\r
+#define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24)\r
+#define XDMA_UBC_NDE_FETCH_EN (0x1u << 24)\r
+\r
+#define XDMA_UBC_NSEN (0x1u << 25)\r
+#define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25)\r
+#define XDMA_UBC_NSEN_UPDATED (0x1u << 25)\r
+\r
+#define XDMA_UBC_NDEN (0x1u << 26)\r
+#define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26)\r
+#define XDMA_UBC_NDEN_UPDATED (0x1u << 26)\r
+\r
+#define XDMA_UBC_NVIEW_Pos 27\r
+#define XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos)\r
+#define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos)\r
+#define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos)\r
+#define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos)\r
+#define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos)\r
+\r
+/** @}*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \addtogroup dmad_structs DMA Driver Structs\r
+ @{*/\r
+\r
+/** DMA status or return code */\r
+enum {\r
+ XDMAD_OK = 0, /**< Operation is sucessful */\r
+ XDMAD_PARTIAL_DONE,\r
+ XDMAD_DONE,\r
+ XDMAD_BUSY, /**< Channel occupied or transfer not finished */\r
+ XDMAD_ERROR, /**< Operation failed */\r
+ XDMAD_CANCELED /**< Operation canceled */\r
+};\r
+\r
+/** DMA channel */\r
+struct _xdmad_channel;\r
+\r
+/** DMA transfer callback */\r
+typedef void (*xdmad_callback_t)(struct _xdmad_channel *channel, void *arg);\r
+\r
+union _xdmac_cfg_reg {\r
+ uint32_t uint32_value;\r
+ struct {\r
+ uint32_t type: 1,\r
+ mbsize: 2,\r
+ dummy1: 1,\r
+ dsync: 1,\r
+ prot: 1,\r
+ sweq: 1,\r
+ memset: 1,\r
+ csize: 3,\r
+ dwidth: 2,\r
+ sif: 1,\r
+ dif: 1,\r
+ dummy2: 1,\r
+ sam: 2,\r
+ dam: 2,\r
+ dummy3: 1,\r
+ initd: 1,\r
+ rdip: 1,\r
+ wrip: 1,\r
+ perid: 7;\r
+ } bitfield;\r
+};\r
+\r
+struct _xdmad_cfg {\r
+ uint32_t ublock_size; /**< Microblock Size */\r
+ uint32_t block_size; /**< Block Size (number of Microblock) */\r
+ uint32_t data_stride; /**< Data Stride */\r
+ uint32_t src_ublock_stride; /**< Source Microblock Stride */\r
+ uint32_t dest_ublock_stride; /**< Destination Microblock Stride */\r
+ void *src_addr; /**< Source Address */\r
+ void *dest_addr; /**< Destination Address */\r
+ union _xdmac_cfg_reg cfg; /**< Configuration Register */\r
+};\r
+\r
+/** Structure for storing parameters for DMA view0 that can be performed by the\r
+ * DMA Master transfer.*/\r
+struct _xdmad_desc_view0 {\r
+ void *next_desc; /**< Next Descriptor Address */\r
+ uint32_t ublock_size; /**< Microblock Control */\r
+ uint32_t mbr_ta; /**< Transfer Address */\r
+};\r
+\r
+/** Structure for storing parameters for DMA view1 that can be performed by the\r
+ * DMA Master transfer.*/\r
+struct _xdmad_desc_view1 {\r
+ void *next_desc; /**< Next Descriptor Address */\r
+ uint32_t ublock_size; /**< Microblock Control */\r
+ void *src_addr; /**< Source Address */\r
+ void *dest_addr; /**< Destination Address */\r
+};\r
+\r
+/** Structure for storing parameters for DMA view2 that can be performed by the\r
+ * DMA Master transfer.*/\r
+struct _xdmad_desc_view2 {\r
+ void *next_desc; /**< Next Descriptor Address */\r
+ uint32_t ublock_size; /**< Microblock Control */\r
+ void *src_addr; /**< Source Address */\r
+ void *dest_addr; /**< Destination Address */\r
+ union _xdmac_cfg_reg cfg; /**< Configuration Register */\r
+};\r
+\r
+/** Structure for storing parameters for DMA view3 that can be performed by the\r
+ * DMA Master transfer.*/\r
+struct _xdmad_desc_view3 {\r
+ void *next_desc; /**< Next Descriptor Address */\r
+ uint32_t ublock_size; /**< Microblock Control */\r
+ void *src_addr; /**< Source Address */\r
+ void *dest_addr; /**< Destination Address */\r
+ union _xdmac_cfg_reg cfg;\r
+ uint32_t block_size; /**< Block Control */\r
+ uint32_t data_stride; /**< Data Stride */\r
+ uint32_t src_ublock_stride; /**< Source Microblock Stride */\r
+ uint32_t dest_ublock_stride; /**< Destination Microblock Stride */\r
+};\r
+\r
+/** @}*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/** \addtogroup dmad_functions DMA Driver Functionos\r
+ @{*/\r
+\r
+/**\r
+ * \brief Initialize DMA driver instance.\r
+ * \param polling if true, interrupts will not be configured and xdmad_poll\r
+ * must be called to poll for transfer completion\r
+ */\r
+extern void xdmad_initialize(bool polling);\r
+\r
+/**\r
+ * \brief Poll for transfers completion.\r
+ * If polling mode is enabled, this function will call callbacks for completed\r
+ * transfers. If interrupt mode is enabled, this function will do nothing.\r
+ */\r
+extern void xdmad_poll(void);\r
+\r
+/**\r
+ * \brief Allocate an DMA channel\r
+ * \param src Source peripheral ID, XDMAD_PERIPH_MEMORY for memory.\r
+ * \param dest Destination peripheral ID, XDMAD_PERIPH_MEMORY for memory.\r
+ * \return Channel pointer if allocation successful, or NULL if channel\r
+ * allocation failed.\r
+ */\r
+extern struct _xdmad_channel *xdmad_allocate_channel(uint8_t src, uint8_t dest);\r
+\r
+/**\r
+ * \brief Free the specified DMA channel.\r
+ * \param channel Channel pointer\r
+ */\r
+extern uint32_t xdmad_free_channel(struct _xdmad_channel *channel);\r
+\r
+/**\r
+ * \brief Set the callback function for an DMA channel transfer.\r
+ * \param channel Channel pointer\r
+ * \param callback Pointer to callback function.\r
+ * \param user_arg Pointer to user argument for callback.\r
+ */\r
+extern uint32_t xdmad_set_callback(struct _xdmad_channel *channel,\r
+ xdmad_callback_t callback, void *user_arg);\r
+\r
+/**\r
+ * \brief Enable clock of the DMA peripheral, Enable the peripheral,\r
+ * setup configuration register for transfer.\r
+ * \param channel Channel pointer\r
+ */\r
+extern uint32_t xdmad_prepare_channel(struct _xdmad_channel *channel);\r
+\r
+/**\r
+ * \brief Configure DMA for a single transfer.\r
+ * \param channel Channel pointer\r
+ * \param cfg DMA transfer configuration\r
+ * \param desc_cntrl optional descriptor control\r
+ * \param desc_addr optional descriptor address\r
+ */\r
+extern uint32_t xdmad_configure_transfer(struct _xdmad_channel *channel,\r
+ struct _xdmad_cfg *cfg, uint32_t desc_cntrl, void *desc_addr);\r
+\r
+/**\r
+ * \brief Start DMA transfer.\r
+ * \param channel Channel pointer\r
+ */\r
+extern uint32_t xdmad_start_transfer(struct _xdmad_channel *channel);\r
+\r
+/**\r
+ * \brief Check if DMA transfer is finished.\r
+ * \param channel Channel pointer\r
+ */\r
+extern bool xdmad_is_transfer_done(struct _xdmad_channel *channel);\r
+\r
+/**\r
+ * \brief Stop DMA transfer.\r
+ * \param channel Channel pointer\r
+ */\r
+extern uint32_t xdmad_stop_transfer(struct _xdmad_channel *channel);\r
+\r
+/** @}*/\r
+\r
+/**@}*/\r
+\r
+#endif /* _XDMAD_H_ */\r
--- /dev/null
+# ----------------------------------------------------------------------------\r
+# SAM Software Package License\r
+# ----------------------------------------------------------------------------\r
+# Copyright (c) 2015, Atmel Corporation\r
+#\r
+# All rights reserved.\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# - Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the disclaimer below.\r
+#\r
+# Atmel's name may not be used to endorse or promote products derived from\r
+# this software without specific prior written permission.\r
+#\r
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+# ----------------------------------------------------------------------------\r
+\r
+\r
+drivers-$(CONFIG_HAVE_PMIC_ACT8945A) += drivers/power/act8945a.o\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "chip.h"\r
+\r
+#include "peripherals/pio.h"\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/flexcom.h"\r
+#include "peripherals/twi.h"\r
+#include "peripherals/twid.h"\r
+\r
+#include "power/act8945a.h"\r
+\r
+#include "trace.h"\r
+\r
+#include <stdio.h>\r
+#include <stdint.h>\r
+#include <string.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#define STATE_VSEL 1 // HW config DDR3L\r
+\r
+// SYS @0x00\r
+union _sys0 {\r
+ struct {\r
+ uint8_t\r
+ trst: 1, // Reset time out 0->260 1->65ms\r
+ nsysmode: 1, // response of SYSLEV voltage detector, 1->int 0>shutdown\r
+ nsyslevmsk: 1, // 1->unmask int\r
+ nsysstat: 1, // 1 if vsys < syslev voltage threshold\r
+ syslev: 4; // defines SYSLEV voltage threshold\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+// SYS @0x01\r
+union _sys1 {\r
+ struct {\r
+ uint8_t\r
+ scratch: 4, // user area to store system status information\r
+ ruf4: 1,\r
+ mstroff: 1, // Set bit to 1 to turn off all regulators\r
+ ruf67: 2;\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+// REG1 @0x20, REG2 @0x30, REG3 @0x40\r
+union _vset1 {\r
+ struct {\r
+ uint8_t\r
+ vset1: 6,\r
+ ruf_67: 2;\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+// REG1 @0x21, REG2 @0x31, REG3 @0x41\r
+union _vset2 {\r
+ struct {\r
+ uint8_t\r
+ vset2: 6,\r
+ ruf_67: 2;\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+// REG1 @0x22, REG2 @0x32, REG3 @0x42\r
+union _ctrl1 {\r
+ struct {\r
+ uint8_t\r
+ ok: 1,\r
+ nfltmsk: 1,\r
+ delay: 3,\r
+ mode: 1,\r
+ phase: 1,\r
+ on: 1;\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+// REG4 @0x51, REG5 @0x55, REG6 @0x61, REG7 @0x65\r
+union _ctrl2 {\r
+ struct {\r
+ uint8_t\r
+ ok: 1,\r
+ nfltmsk: 1,\r
+ delay: 3,\r
+ lowiq: 1,\r
+ dis: 1,\r
+ on: 1;\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+union _apch_70 {\r
+ struct {\r
+ uint8_t\r
+ ruf_0: 1,\r
+ ruf_1: 1,\r
+ ruf_2: 1,\r
+ ruf_3: 1,\r
+ ruf_45: 2,\r
+ ruf_67: 2;\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+union _apch_71 {\r
+ struct {\r
+ uint8_t\r
+ ovpset: 2,\r
+ pretimo: 2,\r
+ tottimo: 2,\r
+ ruf6: 1,\r
+ suschg: 1;\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+union _apch_78 {\r
+ struct {\r
+ uint8_t\r
+ chgdat: 1,\r
+ indat: 1,\r
+ tempdat: 1,\r
+ timrdat: 1,\r
+ chgstat: 1,\r
+ instat: 1,\r
+ tempstat: 1,\r
+ timrstat: 1;\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+union _apch_79 {\r
+ struct {\r
+ uint8_t\r
+ chgeocout: 1,\r
+ indis: 1,\r
+ tempout: 1,\r
+ timrpre: 1,\r
+ chgeocin: 1,\r
+ incon: 1,\r
+ tempin: 1,\r
+ timrtot: 1;\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+union _apch_7a {\r
+ struct {\r
+ uint8_t\r
+ ruf0: 1,\r
+ acinstat: 1,\r
+ ruf32: 2,\r
+ cstate: 2,\r
+ ruf76: 2;\r
+ } bits;\r
+ uint8_t u8;\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Constants\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/// Slave address\r
+#define ACT8945A_TWI_ADDRESS 0x5B\r
+\r
+#define NUM_REGULATORS 7\r
+\r
+#define IADDR_SYS0 0x00\r
+#define IADDR_SYS1 0x01\r
+#define IADDR_REG1 0x20\r
+#define IADDR_REG2 0x30\r
+#define IADDR_REG3 0x40\r
+#define IADDR_REG4 0x50\r
+#define IADDR_REG5 0x54\r
+#define IADDR_REG6 0x60\r
+#define IADDR_REG7 0x64\r
+#define IADDR_APCH_70 0x70\r
+#define IADDR_APCH_71 0x71\r
+#define IADDR_APCH_78 0x78\r
+#define IADDR_APCH_79 0x79\r
+#define IADDR_APCH_7A 0x7a\r
+\r
+static const uint8_t _iaddr_reg[] = {\r
+ IADDR_REG1, IADDR_REG2, IADDR_REG3, IADDR_REG4,\r
+ IADDR_REG5, IADDR_REG6, IADDR_REG7,\r
+};\r
+\r
+static const char* _charging_states[4] = {\r
+ "Suspend/Disable/Fault",\r
+ "End of charge",\r
+ "Fast charge/Top-off",\r
+ "Precondition",\r
+};\r
+\r
+struct _reg\r
+{\r
+ const char* name;\r
+ uint8_t iaddr;\r
+};\r
+\r
+static const struct _reg _regs[] = {\r
+ { "SYS0 ", IADDR_SYS0 },\r
+ { "SYS1 ", IADDR_SYS1 },\r
+ { "REG1_20", IADDR_REG1 },\r
+ { "REG1_21", IADDR_REG1 + 1 },\r
+ { "REG1_22", IADDR_REG1 + 2 },\r
+ { "REG2_30", IADDR_REG2 },\r
+ { "REG2_31", IADDR_REG2 + 1 },\r
+ { "REG2_32", IADDR_REG2 + 2 },\r
+ { "REG3_40", IADDR_REG3 },\r
+ { "REG3_41", IADDR_REG3 + 1 },\r
+ { "REG3_42", IADDR_REG3 + 2 },\r
+ { "REG4_50", IADDR_REG4 },\r
+ { "REG4_51", IADDR_REG4 + 1 },\r
+ { "REG5_54", IADDR_REG5 },\r
+ { "REG5_55", IADDR_REG5 + 1 },\r
+ { "REG6_60", IADDR_REG6 },\r
+ { "REG6_61", IADDR_REG6 + 1 },\r
+ { "REG7_64", IADDR_REG7 },\r
+ { "REG7_65", IADDR_REG7 + 1 },\r
+ { "APCH_70", IADDR_APCH_70 },\r
+ { "APCH_71", IADDR_APCH_71 },\r
+ { "APCH_78", IADDR_APCH_78 },\r
+ { "APCH_79", IADDR_APCH_79 },\r
+ { "APCH_7A", IADDR_APCH_7A },\r
+};\r
+\r
+static const char *_ovp_setting[4] = {\r
+ "6.6V", "7.0V", "7.5V", "8.0V",\r
+} ;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static bool _act8945a_read_reg(struct _act8945a* act8945a, uint32_t iaddr,\r
+ uint8_t* value)\r
+{\r
+ uint32_t status;\r
+ struct _buffer in = {\r
+ .data = value,\r
+ .size = 1\r
+ };\r
+ act8945a->twid->slave_addr = ACT8945A_TWI_ADDRESS;\r
+ act8945a->twid->iaddr = iaddr;\r
+ act8945a->twid->isize = 1;\r
+ status = twid_transfert(act8945a->twid, &in, 0,\r
+ twid_finish_transfert_callback, 0);\r
+ if (status != TWID_SUCCESS)\r
+ return false;\r
+ twid_wait_transfert(act8945a->twid);\r
+ return true;\r
+}\r
+\r
+static bool _act8945a_write_reg(struct _act8945a* act8945a, uint32_t iaddr,\r
+ uint8_t value)\r
+{\r
+ uint32_t status;\r
+ struct _buffer out = {\r
+ .data = (uint8_t*)&value,\r
+ .size = 1\r
+ };\r
+ act8945a->twid->slave_addr = ACT8945A_TWI_ADDRESS;\r
+ act8945a->twid->iaddr = iaddr;\r
+ act8945a->twid->isize = 1;\r
+ status = twid_transfert(act8945a->twid, 0, &out,\r
+ twid_finish_transfert_callback, 0);\r
+ if (status != TWID_SUCCESS)\r
+ return false;\r
+ twid_wait_transfert(act8945a->twid);\r
+ return true;\r
+}\r
+\r
+static bool _act8945a_update_cached_registers(struct _act8945a *act8945a)\r
+{\r
+ return _act8945a_read_reg(act8945a, IADDR_SYS0, &act8945a->sys0) &&\r
+ _act8945a_read_reg(act8945a, IADDR_APCH_78, &act8945a->apch78) &&\r
+ _act8945a_read_reg(act8945a, IADDR_APCH_79, &act8945a->apch79) &&\r
+ _act8945a_read_reg(act8945a, IADDR_APCH_7A, &act8945a->apch7a);\r
+}\r
+\r
+static void _act8945a_irq_handler(uint32_t group, uint32_t status, void* user_arg)\r
+{\r
+ struct _act8945a *act8945a = (struct _act8945a*)user_arg;\r
+\r
+ if (status & act8945a->desc.pin_irq.mask) {\r
+ union _sys0 sys0;\r
+ union _apch_78 apch78;\r
+ union _apch_79 apch79;\r
+ union _apch_7a apch7a;\r
+\r
+ // save previous values\r
+ sys0.u8 = act8945a->sys0;\r
+ apch78.u8 = act8945a->apch78;\r
+ apch79.u8 = act8945a->apch79;\r
+ apch7a.u8 = act8945a->apch7a;\r
+\r
+ // update values\r
+ _act8945a_update_cached_registers(act8945a);\r
+\r
+ // show changes\r
+ if (sys0.u8 != act8945a->sys0) {\r
+ trace_debug("PMIC IRQ: SYST0 changed\r\n");\r
+ }\r
+ if (apch78.u8 != act8945a->apch78) {\r
+ if (apch78.bits.chgdat == 0x01)\r
+ trace_debug("PMIC IRQ: charger state machine, END-OF-CHARGE state\r\n");\r
+ }\r
+ if (apch79.u8 != act8945a->apch79) {\r
+ printf("PMIC IRQ: APCH79 changed\r\n");\r
+ }\r
+ if (apch7a.u8 != act8945a->apch7a) {\r
+ trace_debug("PMIC IRQ: %s\r\n", _charging_states[apch7a.bits.cstate]);\r
+ }\r
+ }\r
+}\r
+\r
+static void _act8945a_lbo_handler(uint32_t group, uint32_t status, void* user_arg)\r
+{\r
+ struct _act8945a *act8945a = (struct _act8945a*)user_arg;\r
+\r
+ if (status & act8945a->desc.pin_lbo.mask) {\r
+ trace_debug("PMIC LBO: Low Battery Output\r\n");\r
+ if( act8945a->lbo_count++ >= 10)\r
+ pio_disable_it(&act8945a->desc.pin_lbo);\r
+ }\r
+}\r
+\r
+// Enable interrupt on nIRQ pin to MPU\r
+static void _act8945a_enable_interrupt_handlers(struct _act8945a *act8945a)\r
+{\r
+ /* Configure PMIC line interrupts. */\r
+ pio_configure_it(&act8945a->desc.pin_irq);\r
+ pio_add_handler_to_group(act8945a->desc.pin_irq.group,\r
+ act8945a->desc.pin_irq.mask,\r
+ &_act8945a_irq_handler,\r
+ act8945a);\r
+ pio_enable_it(&act8945a->desc.pin_irq);\r
+\r
+ /* Configure LBO line interrupts. */\r
+ act8945a->lbo_count = 0;\r
+ pio_configure_it(&act8945a->desc.pin_lbo);\r
+ pio_add_handler_to_group(act8945a->desc.pin_lbo.group,\r
+ act8945a->desc.pin_lbo.mask,\r
+ &_act8945a_lbo_handler,\r
+ act8945a);\r
+ pio_enable_it(&act8945a->desc.pin_lbo);\r
+}\r
+\r
+static uint16_t _act8945a_convert_voltage_setting(uint8_t setting)\r
+{\r
+ uint8_t mul20, mul53;\r
+\r
+ mul20 = (setting & 0x07) >> 0;\r
+ mul53 = (setting & 0x38) >> 3;\r
+\r
+ if (setting <= 0x17)\r
+ return (uint16_t)(1000 * (0.6 + (0.2 * mul53) + (0.025 * mul20)));\r
+ else if (setting <= 0x2F)\r
+ return (uint16_t)(1000 * (1.2 + (0.4 * (mul53 - 3)) + (0.050 * mul20)));\r
+ else\r
+ return (uint16_t)(1000 * (2.4 + (0.8 * (mul53 - 6)) + (0.1 * mul20)));\r
+}\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+bool act8945a_configure(struct _act8945a *act8945a, struct _twi_desc *twid)\r
+{\r
+ uint8_t data = 0;\r
+\r
+ act8945a->twid = twid;\r
+ twid_configure(twid);\r
+\r
+ pio_configure(&act8945a->desc.pin_chglev, 1);\r
+ pio_configure(&act8945a->desc.pin_irq, 1);\r
+ pio_configure(&act8945a->desc.pin_lbo, 1);\r
+\r
+ if (!_act8945a_read_reg(act8945a, IADDR_SYS0, &data))\r
+ return false;\r
+\r
+ /* Set Charge Level */\r
+ act8945a_set_charge_level(act8945a, ACT8945A_CHARGE_LEVEL_450MA);\r
+\r
+ /* Set level interrupt */\r
+ act8945a_disable_all_apch_interrupts(act8945a);\r
+ act8945a_configure_apch_interrupt(act8945a, CHARGE_STATE_INTO_EOC_STATE, true);\r
+ act8945a_configure_apch_interrupt(act8945a, CHARGE_STATE_OUT_EOC_STATE, true);\r
+ act8945a_configure_apch_interrupt(act8945a, PRECHARGE_TIME_OUT, true);\r
+ act8945a_configure_apch_interrupt(act8945a, TOTAL_CHARGE_TIME_OUT, true);\r
+ act8945a_enable_system_voltage_level_interrupt(act8945a, true);\r
+\r
+ /* Update cached register values */\r
+ if (!_act8945a_update_cached_registers(act8945a))\r
+ return false;\r
+\r
+ act8945a_enable_regulator_fault_interrupt(act8945a, 1, true);\r
+ act8945a_enable_regulator_fault_interrupt(act8945a, 5, true);\r
+\r
+ /* Enable interrupts */\r
+ _act8945a_enable_interrupt_handlers(act8945a);\r
+\r
+ return true;\r
+}\r
+\r
+// Charge Current Selection Input\r
+// In USB-Mode: CHGLEV = 1 -> I charge 450mA\r
+// CHGLEV = 0 -> I charge 100mA\r
+void act8945a_set_charge_level(struct _act8945a *act8945a,\r
+ enum _act8945a_charge_level level)\r
+{\r
+ switch (level) {\r
+ case ACT8945A_CHARGE_LEVEL_100MA:\r
+ pio_clear(&act8945a->desc.pin_chglev);\r
+ trace_debug("Charge Level: 100mA\r\n");\r
+ break;\r
+ case ACT8945A_CHARGE_LEVEL_450MA:\r
+ pio_set(&act8945a->desc.pin_chglev);\r
+ trace_debug("Charge Level: 450mA\r\n");\r
+ break;\r
+ default:\r
+ trace_warning("Invalid charge level requested: %d\r\n",\r
+ (int)level)\r
+ break;\r
+ }\r
+}\r
+\r
+// Set or Clear an APCH interrupt\r
+// Set bit to 1 enable interrupt,\r
+// Clear bit to 0 to disable interrupt\r
+bool act8945a_configure_apch_interrupt(struct _act8945a *act8945a,\r
+ enum _act8945a_interrupt interrupt, bool enable)\r
+{\r
+ bool status;\r
+ union _apch_78 apch78;\r
+ union _apch_79 apch79;\r
+\r
+ if (!_act8945a_read_reg(act8945a, IADDR_APCH_78, &apch78.u8) ||\r
+ !_act8945a_read_reg(act8945a, IADDR_APCH_79, &apch79.u8))\r
+ return false;\r
+\r
+ switch (interrupt)\r
+ {\r
+ // Interrupt generated any time the input supply is disconnected when\r
+ // INSTAT[] bit is set to 1 and the INDIS[] bit is set to 1.\r
+ case INPUT_VOLTAGE_OUT_VALID_RANGE: // Interrupt\r
+ apch78.bits.instat = enable ? 1 : 0;\r
+ apch79.bits.indis = enable ? 1 : 0;\r
+ break;\r
+\r
+ // Interrupt generated any time the input supply is connected when\r
+ // INSTAT[] bit is set to 1 and the INCON[] bit is set to 1.\r
+ case INPUT_VOLTAGE_INTO_VALID_RANGE:\r
+ apch78.bits.instat = enable ? 1 : 0;\r
+ apch79.bits.incon = enable ? 1 : 0;\r
+ break;\r
+\r
+ // Interrupts based upon the status of the battery temperature.\r
+ // Set the TEMPOUT[] bit to 1 and TEMPSTAT[] bit to 1 to generate\r
+ // an interrupt when battery temperature goes out of the valid\r
+ // temperature range.\r
+ case BATTERY_TEMPERATURE_OUT_RANGE:\r
+ apch78.bits.tempstat = enable ? 1 : 0;\r
+ apch79.bits.tempout = enable ? 1 : 0;\r
+ break;\r
+\r
+ // Interrupts based upon the status of the battery temperature.\r
+ // Set the TEMPIN[] bit to 1 and TEMPSTAT[] bit to 1 to generate\r
+ // an interrupt when battery temperature returns to the valid range.\r
+ case BATTERY_TEMPERATURE_INTO_RANGE:\r
+ apch78.bits.tempstat = enable ? 1 : 0;\r
+ apch79.bits.tempin = enable ? 1 : 0;\r
+ break;\r
+\r
+ // Interrupt when the charger state machine goes into the\r
+ // END-OF-CHARGE (EOC). Set CHGEOCIN[] bit to 1 and CHGSTAT[] bit\r
+ // to 1 to generate an interrupt when the charger state machine goes\r
+ // into the END-OF-CHARGE (EOC)state.\r
+ case CHARGE_STATE_INTO_EOC_STATE:\r
+ apch78.bits.chgstat = enable ? 1 : 0;\r
+ apch79.bits.chgeocin = enable ? 1 : 0;\r
+ break;\r
+\r
+ // Interrupt when the charger state machine exit the\r
+ // END-OF-CHARGE (EOC). Set CHGEOCOUT[] bit to 1 and CHGSTAT[] bit\r
+ // to 1 to generate an interrupt when the charger state machine exits\r
+ // the EOC state.\r
+ case CHARGE_STATE_OUT_EOC_STATE:\r
+ apch78.bits.chgstat = enable ? 1 : 0;\r
+ apch79.bits.chgeocout = enable ? 1 : 0;\r
+ break;\r
+\r
+ // Interrupts based upon the status of the charge timers.\r
+ // Set the TIMRPRE[] bit to 1 and TIMRSTAT[] bit to 1 to generate an\r
+ // interrupt when the Precondition Timer expires.\r
+ case PRECHARGE_TIME_OUT:\r
+ apch78.bits.timrstat = enable ? 1 : 0;\r
+ apch79.bits.timrpre = enable ? 1 : 0;\r
+ break;\r
+\r
+ // Set the TIMRTOT[] bit to 1 and TIMRSTAT[] bit to 1 to generate an\r
+ // interrupt when the Total-Charge Timer expires.\r
+ case TOTAL_CHARGE_TIME_OUT:\r
+ apch78.bits.timrstat = enable ? 1 : 0;\r
+ apch79.bits.timrtot = enable ? 1 : 0;\r
+ break;\r
+\r
+ default:\r
+ trace_warning("Unknown interrupt %d\r\n", interrupt);\r
+ return false;\r
+ }\r
+\r
+ // Write configuration to registers\r
+ status = _act8945a_write_reg(act8945a, IADDR_APCH_78, apch78.u8);\r
+ status |= _act8945a_write_reg(act8945a, IADDR_APCH_79, apch79.u8);\r
+ return status;\r
+\r
+}\r
+\r
+// Disable all interrupt from APCH\r
+bool act8945a_disable_all_apch_interrupts(struct _act8945a *act8945a)\r
+{\r
+ return act8945a_configure_apch_interrupt(act8945a, CHARGE_STATE_OUT_EOC_STATE, false) &&\r
+ act8945a_configure_apch_interrupt(act8945a, INPUT_VOLTAGE_OUT_VALID_RANGE, false) &&\r
+ act8945a_configure_apch_interrupt(act8945a, BATTERY_TEMPERATURE_OUT_RANGE, false) &&\r
+ act8945a_configure_apch_interrupt(act8945a, PRECHARGE_TIME_OUT, false) &&\r
+ act8945a_configure_apch_interrupt(act8945a, CHARGE_STATE_INTO_EOC_STATE, false) &&\r
+ act8945a_configure_apch_interrupt(act8945a, INPUT_VOLTAGE_INTO_VALID_RANGE, false) &&\r
+ act8945a_configure_apch_interrupt(act8945a, BATTERY_TEMPERATURE_INTO_RANGE, false) &&\r
+ act8945a_configure_apch_interrupt(act8945a, TOTAL_CHARGE_TIME_OUT, false);\r
+}\r
+\r
+extern bool act8945a_set_system_voltage_detect_threshold(struct _act8945a *act8945a,\r
+ uint16_t threshold)\r
+{\r
+ union _sys0 sys0;\r
+\r
+ if (threshold < 2300 || threshold > 3800)\r
+ return false;\r
+ if (!_act8945a_read_reg(act8945a, IADDR_SYS0, &sys0.u8))\r
+ return false;\r
+ sys0.bits.syslev = (threshold - 2300) / 100;\r
+ return _act8945a_write_reg(act8945a, IADDR_SYS0, sys0.u8);\r
+}\r
+\r
+bool act8945a_enable_system_voltage_level_interrupt(struct _act8945a *act8945a,\r
+ bool enable)\r
+{\r
+ union _sys0 sys0;\r
+\r
+ if (!_act8945a_read_reg(act8945a, IADDR_SYS0, &sys0.u8))\r
+ return false;\r
+ sys0.bits.nsyslevmsk = enable ? 1 : 0;\r
+\r
+ sys0.bits.nsysmode = 1; //*************\r
+\r
+ return _act8945a_write_reg(act8945a, IADDR_SYS0, sys0.u8);\r
+}\r
+\r
+bool act8945a_set_regulator_voltage(struct _act8945a *act8945a,\r
+ uint8_t reg, uint16_t vout)\r
+{\r
+ // minimum is 600mV\r
+ if (vout < 600) {\r
+ trace_warning("Cannot set regulator %d voltage to %dmV, using 600mV instead\r\n", reg, vout);\r
+ vout = 600;\r
+ }\r
+ // maximum is 3900mV\r
+ if (vout > 3900) {\r
+ trace_warning("Cannot set regulator %d voltage to %dmV, using 3900mV instead\r\n", reg, vout);\r
+ vout = 3900;\r
+ }\r
+\r
+ // can only set voltage for regulators 4 to 7\r
+ if (reg < 4 || reg > 7) {\r
+ trace_error("Cannot change voltage of regulator %d\r\n", reg);\r
+ return false;\r
+ };\r
+\r
+ uint8_t value = 0;\r
+ if (vout < 1200) {\r
+ value = (vout - 600) / 25;\r
+ } else if (vout < 2400) {\r
+ value = 0x18 + (vout - 1200) / 50;\r
+ } else if (vout <= 3900) {\r
+ value = 0x30 + (vout - 2400) / 100;\r
+ }\r
+\r
+ uint32_t iaddr = _iaddr_reg[reg - 1];\r
+ return _act8945a_write_reg(act8945a, iaddr, value & 0x3f);\r
+}\r
+\r
+bool act8945a_enable_regulator(struct _act8945a *act8945a,\r
+ uint8_t reg, bool enable)\r
+{\r
+ if (reg >= 1 && reg <= 3) {\r
+ union _ctrl1 ctrl1;\r
+ uint32_t iaddr = _iaddr_reg[reg - 1] + 1;\r
+\r
+ if (!_act8945a_read_reg(act8945a, iaddr, &ctrl1.u8))\r
+ return false;\r
+\r
+ ctrl1.bits.on = enable ? 1 : 0;\r
+\r
+ if (!_act8945a_write_reg(act8945a, iaddr, ctrl1.u8))\r
+ return false;\r
+ } else if (reg >= 4 && reg <= 7) {\r
+ union _ctrl2 ctrl2;\r
+ uint32_t iaddr = _iaddr_reg[reg - 1] + 1;\r
+\r
+ if (!_act8945a_read_reg(act8945a, iaddr, &ctrl2.u8))\r
+ return false;\r
+\r
+ ctrl2.bits.on = enable ? 1 : 0;\r
+\r
+ if (!_act8945a_write_reg(act8945a, iaddr, ctrl2.u8))\r
+ return false;\r
+ } else {\r
+ trace_error("Invalid regulator number %d\r\n", reg);\r
+ return false;\r
+ }\r
+\r
+ return true;\r
+}\r
+\r
+bool act8945a_enable_regulator_fault_interrupt(struct _act8945a *act8945a,\r
+ uint8_t reg, bool enable)\r
+{\r
+ if (reg >= 1 && reg <= 3) {\r
+ union _ctrl1 ctrl1;\r
+ uint8_t iaddr = (_iaddr_reg[reg-1]) + 2;\r
+\r
+\r
+ if (!_act8945a_read_reg(act8945a, iaddr, &ctrl1.u8))\r
+ return false;\r
+\r
+ ctrl1.bits.nfltmsk = enable ? 1 : 0;\r
+\r
+ if (!_act8945a_write_reg(act8945a, iaddr, ctrl1.u8))\r
+ return false;\r
+ } else if (reg >= 4 && reg <= 7) {\r
+ union _ctrl2 ctrl2;\r
+ uint8_t iaddr = (_iaddr_reg[reg-1]) + 1;\r
+\r
+ if (!_act8945a_read_reg(act8945a, iaddr, &ctrl2.u8))\r
+ return false;\r
+\r
+ ctrl2.bits.nfltmsk = enable ? 1 : 0;\r
+\r
+ if (!_act8945a_write_reg(act8945a, iaddr, ctrl2.u8))\r
+ return false;\r
+ } else {\r
+ trace_error("Invalid regulator number %d\r\n", reg);\r
+ return false;\r
+ }\r
+\r
+ return true;\r
+}\r
+\r
+extern bool act8945a_get_lbo_pin_state(struct _act8945a *act8945a)\r
+{\r
+ return pio_get(&act8945a->desc.pin_lbo) ? true : false;\r
+}\r
+\r
+\r
+\r
+extern void act8945a_display_voltage_settings(struct _act8945a *act8945a)\r
+{\r
+ int reg;\r
+\r
+ trace_info_wp("\r\n-- ACT8945A - Voltage Settings & State --\r\n");\r
+\r
+ for (reg = 0; reg < NUM_REGULATORS; reg++)\r
+ {\r
+ uint8_t iadd_reg, setting, ctrl;\r
+ uint16_t u;\r
+\r
+ /* Warning VSEL state */\r
+ iadd_reg = _iaddr_reg[reg];\r
+ if( (iadd_reg < IADDR_REG4) && (STATE_VSEL == 1) )\r
+ iadd_reg ++;\r
+\r
+ if (!_act8945a_read_reg(act8945a, iadd_reg, &setting))\r
+ return;\r
+\r
+ if (!_act8945a_read_reg(act8945a, iadd_reg + 1, &ctrl))\r
+ return;\r
+\r
+ u = _act8945a_convert_voltage_setting(setting);\r
+ trace_info_wp(" - VOUT_%d (0x%02x) = %dmV", reg + 1, ctrl, u);\r
+ if (reg <= 3) {\r
+ union _ctrl1 *ctrl1 = (union _ctrl1*)&ctrl;\r
+ trace_info_wp(" %s", ctrl1->bits.on ? "on" : "off");\r
+ trace_info_wp(" %s", ctrl1->bits.phase ? "180" : "osc");\r
+ trace_info_wp(" %s", ctrl1->bits.mode ? "pwm" : "pow-saving");\r
+ trace_info_wp(" delay:0x%02x", ctrl1->bits.delay);\r
+ trace_info_wp(" %s", ctrl1->bits.nfltmsk ? "en" : "dis");\r
+ trace_info_wp(" %s", ctrl1->bits.ok ? "OK" : "<tresh");\r
+ } else {\r
+ union _ctrl2 *ctrl2 = (union _ctrl2*)&ctrl;\r
+ trace_info_wp(" %s", ctrl2->bits.on ? "on": "off");\r
+ trace_info_wp(" %s", ctrl2->bits.dis ? "off" : "on");\r
+ trace_info_wp(" %s", ctrl2->bits.lowiq ? "normal" : "low-power");\r
+ trace_info_wp(" delay:0x%02x", ctrl2->bits.delay);\r
+ trace_info_wp(" %s", ctrl2->bits.nfltmsk ? "en" : "dis");\r
+ trace_info_wp(" %s", ctrl2->bits.ok ? "OK" : "<tresh");\r
+ }\r
+ trace_info_wp("\r\n");\r
+ }\r
+\r
+ union _sys0 sys0;\r
+ if (!_act8945a_read_reg(act8945a, IADDR_SYS0, &sys0.u8))\r
+ return;\r
+ trace_info_wp(" - SYSLEV Failing Treshold (0x%02x) = %dmV\r\n", sys0.u8,\r
+ 2300 + sys0.bits.syslev * 100);\r
+}\r
+\r
+void act8945a_dump_registers(struct _act8945a *act8945a)\r
+{\r
+ uint8_t reg, data, mask, i;\r
+\r
+\r
+ trace_info_wp("\r\n-- ACT8945A - Registers Dump --\r\n");\r
+ for (reg = 0; reg < ARRAY_SIZE(_regs); reg++) {\r
+ if (!_act8945a_read_reg(act8945a, _regs[reg].iaddr, &data))\r
+ return;\r
+ trace_info_wp(" - %s: 0x%02X b:", _regs[reg].name, data);\r
+ mask = 0x80;\r
+ for (i=0; i<8; i++, mask>>=1) {\r
+ printf ("%x", (data&mask) ? 1 : 0);\r
+ }\r
+ trace_info_wp("\r\n");\r
+ }\r
+ trace_info_wp("\r\n");\r
+}\r
+\r
+void act8945a_display_apch_registers(struct _act8945a *act8945a)\r
+{\r
+ union _apch_71 apch71;\r
+ union _apch_78 apch78;\r
+ union _apch_79 apch79;\r
+ union _apch_7a apch7a;\r
+\r
+ trace_info_wp("\r\n-- ACT8945A - APCH Registers --\r\n");\r
+\r
+// if (!_act8945a_read_reg(act8945a, IADDR_APCH_70, &data))\r
+// return;\r
+// trace_info_wp(" - APCH @0x70: 0x%02x (reserved)\r\n", data);\r
+\r
+ if (!_act8945a_read_reg(act8945a, IADDR_APCH_71, &apch71.u8))\r
+ return;\r
+ trace_info_wp(" - APCH @0x71: 0x%02x\r\n", apch71.u8);\r
+ trace_info_wp(" Charge Suspend Control Input: %x\r\n",\r
+ apch71.bits.suschg);\r
+ trace_info_wp(" Total Charge Time-out Selection: %x\r\n",\r
+ apch71.bits.tottimo);\r
+ trace_info_wp(" Precondition Charge Time-out Sel: %x\r\n",\r
+ apch71.bits.pretimo);\r
+ trace_info_wp(" Input Over-Volt Prot.Threshold Sel: %x (%s)\r\n",\r
+ apch71.bits.ovpset, _ovp_setting[apch71.bits.ovpset]);\r
+\r
+ if (!_act8945a_read_reg(act8945a, IADDR_APCH_78, &apch78.u8))\r
+ return;\r
+ trace_info_wp(" - APCH @0x78: 0x%02x\r\n", apch78.u8);\r
+ trace_info_wp(" Charge Time-out Interrupt Status: %x\r\n",\r
+ apch78.bits.timrstat);\r
+ trace_info_wp(" Battery Temperature Interrupt Status: %x\r\n",\r
+ apch78.bits.tempstat);\r
+ trace_info_wp(" Input Voltage Interrupt Status: %x\r\n",\r
+ apch78.bits.instat);\r
+ trace_info_wp(" Charge State Interrupt Status: %x\r\n",\r
+ apch78.bits.chgstat);\r
+ trace_info_wp(" Charge Timer Status %x\r\n",\r
+ apch78.bits.timrdat);\r
+ trace_info_wp(" Temperature Status %x\r\n",\r
+ apch78.bits.tempdat);\r
+ trace_info_wp(" Input Voltage Status %x\r\n",\r
+ apch78.bits.indat);\r
+ trace_info_wp(" Charge State Machine Status %x\r\n",\r
+ apch78.bits.chgdat);\r
+\r
+ if (!_act8945a_read_reg(act8945a, IADDR_APCH_79, &apch79.u8))\r
+ return;\r
+ trace_info_wp(" - APCH @0x79: 0x%02x\r\n", apch79.u8);\r
+ trace_info_wp(" Total Charge Time-out Int Control: %x\r\n",\r
+ apch79.bits.timrtot);\r
+ trace_info_wp(" Batt.Temp.Int.Ctrl into valid range: %x\r\n",\r
+ apch79.bits.tempin);\r
+ trace_info_wp(" Inp.Voltage Int.Ctrl into valid range: %x\r\n",\r
+ apch79.bits.incon);\r
+ trace_info_wp(" Charge State Int Ctrl into EOC state: %x\r\n",\r
+ apch79.bits.chgeocin);\r
+ trace_info_wp(" Precharge Time-out Int Ctrl: %x\r\n",\r
+ apch79.bits.timrpre);\r
+ trace_info_wp(" Batt.Temp.Int.Ctrl. out valid range: %x\r\n",\r
+ apch79.bits.tempout);\r
+ trace_info_wp(" Inp.Voltage Int.Ctrl. out valid range: %x\r\n",\r
+ apch79.bits.indis);\r
+ trace_info_wp(" Charge State Int.Ctrl. out EOC state: %x\r\n",\r
+ apch79.bits.chgeocout);\r
+\r
+ if (!_act8945a_read_reg(act8945a, IADDR_APCH_7A, &apch7a.u8))\r
+ return;\r
+ trace_info_wp(" - APCH @0x7a: 0x%02x\r\n", apch7a.u8);\r
+ trace_info_wp(" Charge State: %x (%s)\r\n",\r
+ apch7a.bits.cstate, _charging_states[apch7a.bits.cstate]);\r
+ trace_info_wp(" ACIN Status: %x\r\n",\r
+ apch7a.bits.acinstat);\r
+}\r
+\r
+void act8945a_display_system_registers(struct _act8945a *act8945a)\r
+{\r
+ union _sys0 sys0;\r
+ union _sys1 sys1;\r
+\r
+ trace_info_wp("\r\n-- ACT8945A - System Registers --\r\n");\r
+\r
+ if (!_act8945a_read_reg(act8945a, IADDR_SYS0, &sys0.u8))\r
+ return;\r
+ trace_info_wp(" - SYS0 @0x00: 0x%02x\r\n", sys0.u8);\r
+ trace_info_wp(" Reset Timer Setting: %s\r\n",\r
+ sys0.bits.trst ? "64ms" : "260ms");\r
+ trace_info_wp(" SYSLEV Mode Select: %s\r\n",\r
+ sys0.bits.nsysmode ?"int" : "shutdown");\r
+ trace_info_wp(" System Voltage Level Int.Mask: %s\r\n",\r
+ sys0.bits.nsyslevmsk ?"int" : "noint");\r
+ trace_info_wp(" System Voltage Status: %s\r\n",\r
+ sys0.bits.nsysstat ? "vsys<syslev" : "vsys>syslev");\r
+ trace_info_wp(" SYSLEV Failing Treshold value: %dmV\r\n",\r
+ 2300 + sys0.bits.syslev * 100);\r
+\r
+ if (!_act8945a_read_reg(act8945a, IADDR_SYS1, &sys1.u8))\r
+ return;\r
+ trace_info_wp(" - SYS1 @0x01: 0x%02x\r\n", sys1.u8);\r
+ trace_info_wp(" Master Off Ctrl, All regul: %s\r\n",\r
+ sys1.bits.mstroff ? "off" : "on");\r
+ trace_info_wp(" Scratchpad Bits, free user: %x\r\n",\r
+ sys1.bits.scratch);\r
+}\r
+\r
+void act8945a_display_charge_state(struct _act8945a *act8945a)\r
+{\r
+ union _apch_7a apch7a;\r
+ if (!_act8945a_read_reg(act8945a, IADDR_APCH_7A, &apch7a.u8)) return;\r
+\r
+ if (act8945a->apch7a != apch7a.u8) {\r
+ trace_info_wp(" Charge State: %x (%s)\r\n", apch7a.bits.cstate, _charging_states[apch7a.bits.cstate]);\r
+ act8945a->apch7a = apch7a.u8;\r
+ }\r
+}
\ No newline at end of file
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _ACT_8945A_H_\r
+#define _ACT_8945A_H_\r
+\r
+#include <stdint.h>\r
+#include <stdbool.h>\r
+\r
+#include "peripherals/twid.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+enum _act8945a_charge_level\r
+{\r
+ ACT8945A_CHARGE_LEVEL_100MA,\r
+ ACT8945A_CHARGE_LEVEL_450MA,\r
+};\r
+\r
+enum _act8945a_interrupt\r
+{\r
+ CHARGE_STATE_OUT_EOC_STATE,\r
+ INPUT_VOLTAGE_OUT_VALID_RANGE,\r
+ BATTERY_TEMPERATURE_OUT_RANGE,\r
+ PRECHARGE_TIME_OUT,\r
+ CHARGE_STATE_INTO_EOC_STATE,\r
+ INPUT_VOLTAGE_INTO_VALID_RANGE,\r
+ BATTERY_TEMPERATURE_INTO_RANGE,\r
+ TOTAL_CHARGE_TIME_OUT,\r
+};\r
+\r
+struct _act8945a_desc {\r
+ const struct _pin pin_chglev;\r
+ const struct _pin pin_irq;\r
+ const struct _pin pin_lbo;\r
+};\r
+\r
+struct _act8945a {\r
+ struct _twi_desc* twid;\r
+ struct _act8945a_desc desc;\r
+\r
+ uint8_t sys0;\r
+ uint8_t apch78;\r
+ uint8_t apch79;\r
+ uint8_t apch7a;\r
+ uint8_t lbo_count;\r
+};\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern bool act8945a_configure(struct _act8945a *act8945a,\r
+ struct _twi_desc *twid);\r
+\r
+extern void act8945a_set_charge_level(struct _act8945a *act8945a,\r
+ enum _act8945a_charge_level level);\r
+\r
+extern bool act8945a_configure_apch_interrupt(struct _act8945a *act8945a,\r
+ enum _act8945a_interrupt interrupt, bool enable);\r
+\r
+extern bool act8945a_disable_all_apch_interrupts(struct _act8945a *act8945a);\r
+\r
+// Set the Programmable System Voltage Monitor\r
+// Input: Value in mv from 2300mv to 3800mv\r
+extern bool act8945a_set_system_voltage_detect_threshold(struct _act8945a *act8945a,\r
+ uint16_t threshold);\r
+\r
+// System Voltage Level Interrupt Mask. SYSLEV interrupt is masked by default,\r
+// set to 1 to unmask this interrupt.\r
+extern bool act8945a_enable_system_voltage_level_interrupt(\r
+ struct _act8945a *act8945a, bool enable);\r
+\r
+extern bool act8945a_set_regulator_voltage(struct _act8945a *act8945a,\r
+ uint8_t reg, uint16_t vout);\r
+\r
+extern bool act8945a_enable_regulator(struct _act8945a *act8945a,\r
+ uint8_t reg, bool enable);\r
+\r
+// Regulator Fault Mask Control.\r
+// Set bit to 1 enable fault-interrupts, clear bit to 0 to disable fault-interrupts\r
+// Input: regulator (1-7)\r
+bool act8945a_enable_regulator_fault_interrupt(struct _act8945a *act8945a,\r
+ uint8_t reg, bool enable);\r
+\r
+extern bool act8945a_get_lbo_pin_state(struct _act8945a *act8945a);\r
+\r
+extern void act8945a_display_voltage_settings(struct _act8945a *act8945a);\r
+\r
+extern void act8945a_dump_registers(struct _act8945a *act8945a);\r
+\r
+extern void act8945a_display_apch_registers(struct _act8945a *act8945a);\r
+\r
+extern void act8945a_display_system_registers(struct _act8945a *act8945a);\r
+\r
+extern void act8945a_display_charge_state(struct _act8945a *act8945a);\r
+\r
+#endif /* _ACT_8945A_H_ */\r
--- /dev/null
+# ----------------------------------------------------------------------------\r
+# SAM Software Package License\r
+# ----------------------------------------------------------------------------\r
+# Copyright (c) 2015, Atmel Corporation\r
+#\r
+# All rights reserved.\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# - Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the disclaimer below.\r
+#\r
+# Atmel's name may not be used to endorse or promote products derived from\r
+# this software without specific prior written permission.\r
+#\r
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+# ----------------------------------------------------------------------------\r
+\r
+lib-y += target/target.a\r
+\r
+target-y :=\r
+\r
+include $(TOP)/target/sama5d2/Makefile.inc\r
+\r
+TARGET_OBJS := $(addprefix $(BUILDDIR)/,$(target-y))\r
+\r
+-include $(TARGET_OBJS:.o=.d)\r
+\r
+$(BUILDDIR)/target/target.a: $(TARGET_OBJS)\r
+ @mkdir -p $(dir $@)\r
+ $(ECHO) AR $@\r
+ $(Q)$(AR) -cr $@ $^\r
+\r
+ifeq ($(VARIANT),ddram)\r
+BOOTSTRAP_OBJS := $(addprefix $(BUILDDIR)/,$(bootstrap-y))\r
+BOOTSTRAP_OBJS += $(addprefix $(BUILDDIR)/,$(gnu-cstartup-y:.S=.o))\r
+\r
+-include $(BOOTSTRAP_OBJS:.o:.d)\r
+endif\r
--- /dev/null
+# ----------------------------------------------------------------------------\r
+# SAM Software Package License\r
+# ----------------------------------------------------------------------------\r
+# Copyright (c) 2013, Atmel Corporation\r
+#\r
+# All rights reserved.\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# - Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the disclaimer below.\r
+#\r
+# Atmel's name may not be used to endorse or promote products derived from\r
+# this software without specific prior written permission.\r
+#\r
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+# ----------------------------------------------------------------------------\r
+\r
+ifeq ($(CONFIG_SOC_SAMA5D2),y)\r
+\r
+CFLAGS_INC += -I$(TOP)/target/sama5d2\r
+\r
+gnu-debug-lib-y ?= $(TOP)/target/sama5d2/toolchain/gnu/common.gdb\r
+gnu-cstartup-y ?= target/sama5d2/toolchain/gnu/cstartup.S\r
+iar-cstartup-y ?= target/sama5d2/toolchain/iar/cstartup.s\r
+\r
+ifeq ($(VARIANT),sram)\r
+gnu-linker-script-y ?= $(TOP)/target/sama5d2/toolchain/gnu/sram.ld\r
+gnu-debug-script-y ?= $(TOP)/target/sama5d2/toolchain/gnu/sram.gdb\r
+iar-linker-script-y ?= $(TOP)/target/sama5d2/toolchain/iar/sram.icf\r
+iar-debug-script-y ?= $(TOP)/target/sama5d2/toolchain/iar/sram.mac\r
+endif\r
+\r
+ifeq ($(VARIANT),ddram)\r
+gnu-linker-script-y ?= $(TOP)/target/sama5d2/toolchain/gnu/ddram.ld\r
+gnu-debug-script-y ?= $(TOP)/target/sama5d2/toolchain/gnu/ddram.gdb\r
+iar-linker-script-y ?= $(TOP)/target/sama5d2/toolchain/iar/ddram.icf\r
+ifeq ($(CONFIG_BOARD_SAMA5D2_XPLAINED),y)\r
+iar-debug-script-y ?= $(TOP)/target/sama5d2/toolchain/iar/ddram_sama5d2-xplained.mac\r
+endif\r
+ifeq ($(CONFIG_BOARD_SAMA5D2_XPLAINED_PROTO),y)\r
+iar-debug-script-y ?= $(TOP)/target/sama5d2/toolchain/iar/ddram_sama5d2-xplained.mac\r
+endif\r
+bootstrap-y ?= target/sama5d2/bootstrap.o\r
+bootstrap-linker-script-y ?= $(TOP)/target/sama5d2/toolchain/gnu/sram.ld\r
+endif\r
+\r
+chip-serie-name-y = sama5d2\r
+\r
+target-y += target/sama5d2/chip.o\r
+target-y += target/sama5d2/board_lowlevel.o\r
+target-y += target/sama5d2/board_memories.o\r
+\r
+endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _BOARD_HEADER_\r
+#define _BOARD_HEADER_\r
+\r
+#if defined(CONFIG_BOARD_SAMA5D2_XPLAINED)\r
+ #include "board_sama5d2-xplained.h"\r
+#elif defined(CONFIG_BOARD_SAMA5D2_XPLAINED_PROTO)\r
+ #include "board_sama5d2-xplained-proto.h"\r
+#elif defined(CONFIG_BOARD_SAMA5D2_VB_BGA196)\r
+ #include "board_sama5d2-vb-bga196.h"\r
+#elif defined(CONFIG_BOARD_SAMA5D2_VB_BGA289)\r
+ #include "board_sama5d2-vb-bga289.h"\r
+#elif defined(CONFIG_BOARD_SAMA5D2_PTC_ENGI)\r
+ #include "board_sama5d2-ptc-engi.h"\r
+#else\r
+ #error "No board defined"\r
+#endif\r
+\r
+#endif /* _BOARD_HEADER_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Provides the low-level initialization function that called on chip startup.\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "board.h"\r
+#include "compiler.h"\r
+#include "timer.h"\r
+\r
+#include "cortex-a/cpsr.h"\r
+\r
+#include "peripherals/aic.h"\r
+#include "peripherals/matrix.h"\r
+#include "peripherals/pio.h"\r
+#include "peripherals/pmc.h"\r
+\r
+#include <stdio.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern void Undefined_Handler();\r
+extern void Abort_Handler();\r
+extern void FIQ_Handler();\r
+extern void FreeRTOS_IRQ_Handler();\r
+\r
+/**\r
+ * \brief Performs the low-level initialization of the chip.\r
+ * It also enable a low level on the pin NRST triggers a user reset.\r
+ */\r
+void low_level_init(void)\r
+{\r
+ uint32_t i;\r
+\r
+ /* Setup default interrupt handlers */\r
+ aic_initialize();\r
+\r
+ /* Configure clocking if code is not in external mem */\r
+ if ((uint32_t)low_level_init < DDR_CS_ADDR)\r
+ {\r
+ pmc_switch_mck_to_slck();\r
+ pmc_set_mck_h32mxdiv(PMC_MCKR_H32MXDIV_H32MXDIV2);\r
+ pmc_set_mck_plla_div(PMC_MCKR_PLLADIV2);\r
+ pmc_set_mck_prescaler(PMC_MCKR_PRES_CLOCK);\r
+ pmc_set_mck_divider(PMC_MCKR_MDIV_EQ_PCK);\r
+ /* Disable PLLA */\r
+ pmc_set_plla(0, PMC_PLLICPR_IPLL_PLLA(0x3));\r
+ pmc_select_external_osc();\r
+ /* Configure PLLA */\r
+ pmc_set_plla(CKGR_PLLAR_ONE | CKGR_PLLAR_PLLACOUNT(0x3F) |\r
+ CKGR_PLLAR_OUTA(0x0) | CKGR_PLLAR_MULA(82) |\r
+ CKGR_PLLAR_DIVA_BYPASS, PMC_PLLICPR_IPLL_PLLA(0x3));\r
+ pmc_set_mck_divider(PMC_MCKR_MDIV_PCK_DIV3);\r
+ pmc_set_mck_prescaler(PMC_MCKR_PRES_CLOCK);\r
+ pmc_switch_mck_to_pll();\r
+ }\r
+\r
+ /* select FIQ */\r
+ AIC->AIC_SSR = 0;\r
+ AIC->AIC_SVR = (unsigned int) FIQ_Handler;\r
+\r
+ for (i = 1; i < 31; i++)\r
+ {\r
+ AIC->AIC_SSR = i;\r
+ AIC->AIC_SVR = (unsigned int) FreeRTOS_IRQ_Handler;\r
+ }\r
+\r
+ AIC->AIC_SPU = (unsigned int) Undefined_Handler;\r
+\r
+ /* Disable all interrupts */\r
+ for (i = 1; i < 31; i++)\r
+ {\r
+ AIC->AIC_SSR = i;\r
+ AIC->AIC_IDCR = 1 ;\r
+ }\r
+ /* Clear All pending interrupts flags */\r
+ for (i = 1; i < 31; i++)\r
+ {\r
+ AIC->AIC_SSR = i;\r
+ AIC->AIC_ICCR = 1 ;\r
+ }\r
+ /* Perform 8 IT acknoledge (write any value in EOICR) */\r
+ for (i = 0; i < 8 ; i++)\r
+ {\r
+ AIC->AIC_EOICR = 0;\r
+ }\r
+\r
+ /* Remap */\r
+ matrix_remap_ram();\r
+\r
+ // timer_configure(BOARD_TIMER_RESOLUTION);\r
+}\r
+\r
+/**\r
+ * \brief Restore all IOs to default state after power-on reset.\r
+ */\r
+void board_restore_pio_reset_state(void)\r
+{\r
+ unsigned int i;\r
+\r
+ /* all pins, excluding JTAG and NTRST */\r
+ struct _pin pins[] = {\r
+ { PIO_GROUP_A, 0xFFFFFFFF, PIO_INPUT, PIO_PULLUP },\r
+ { PIO_GROUP_B, 0xFFFFFFFF, PIO_INPUT, PIO_PULLUP },\r
+ { PIO_GROUP_C, 0xFFFFFFFF, PIO_INPUT, PIO_PULLUP },\r
+ { PIO_GROUP_D, 0xFFF83FFF, PIO_INPUT, PIO_PULLUP },\r
+ };\r
+\r
+ pio_configure(pins, ARRAY_SIZE(pins));\r
+ for (i = 0; i < ARRAY_SIZE(pins); i++)\r
+ pio_clear(&pins[i]);\r
+}\r
+\r
+void board_save_misc_power(void)\r
+{\r
+ int i;\r
+\r
+ /* disable USB clock */\r
+ pmc_disable_upll_clock();\r
+ pmc_disable_upll_bias();\r
+\r
+ /* Disable audio clock */\r
+// pmc_disable_audio();\r
+\r
+ /* disable system clocks */\r
+ pmc_disable_system_clock(PMC_SYSTEM_CLOCK_DDR);\r
+ pmc_disable_system_clock(PMC_SYSTEM_CLOCK_LCD);\r
+ pmc_disable_system_clock(PMC_SYSTEM_CLOCK_SMD);\r
+ pmc_disable_system_clock(PMC_SYSTEM_CLOCK_UHP);\r
+ pmc_disable_system_clock(PMC_SYSTEM_CLOCK_UDP);\r
+ pmc_disable_system_clock(PMC_SYSTEM_CLOCK_PCK0);\r
+ pmc_disable_system_clock(PMC_SYSTEM_CLOCK_PCK1);\r
+ pmc_disable_system_clock(PMC_SYSTEM_CLOCK_PCK2);\r
+ pmc_disable_system_clock(PMC_SYSTEM_CLOCK_ISC);\r
+\r
+ /* disable all peripheral clocks except PIOA for JTAG, serial debug port */\r
+ for (i = ID_PIT; i < ID_PERIPH_COUNT; i++) {\r
+ if (i == ID_PIOA)\r
+ continue;\r
+ pmc_disable_peripheral(i);\r
+ }\r
+}\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for the low-level initialization function.\r
+ *\r
+ */\r
+\r
+#ifndef BOARD_LOWLEVEL_H\r
+#define BOARD_LOWLEVEL_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Low-Level chip initialization -- called by startup\r
+ */\r
+extern void low_level_init(void);\r
+\r
+/**\r
+ * \brief Restore all IOs to default state after power-on reset.\r
+ */\r
+extern void board_restore_pio_reset_state(void);\r
+\r
+/**\r
+ * \brief Save power by disabling most peripherals\r
+ */\r
+extern void board_save_misc_power(void);\r
+\r
+#endif /* BOARD_LOWLEVEL_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Implementation of memories configuration on board.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "board_memories.h"\r
+#include "trace.h"\r
+\r
+#include "cortex-a/mmu.h"\r
+\r
+#include "peripherals/hsmc.h"\r
+#include "peripherals/l2cc.h"\r
+#include "peripherals/matrix.h"\r
+#include "peripherals/pmc.h"\r
+\r
+#include "memories/ddram.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local constants\r
+ *----------------------------------------------------------------------------*/\r
+\r
+const static struct _l2cc_control l2cc_cfg = {\r
+ .instruct_prefetch = true, // Instruction prefetch enable\r
+ .data_prefetch = true, // Data prefetch enable\r
+ .double_linefill = true,\r
+ .incr_double_linefill = true,\r
+ /* Disable Write back (enables write through, Use this setting\r
+ if DDR2 mem is not write-back) */\r
+ //cfg.no_write_back = true,\r
+ .force_write_alloc = FWA_NO_ALLOCATE,\r
+ .offset = 31,\r
+ .prefetch_drop = true,\r
+ .standby_mode = true,\r
+ .dyn_clock_gating = true\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#ifdef BOARD_DDRAM_TYPE\r
+static void matrix_configure_slave_ddr(void)\r
+{\r
+ int i;\r
+\r
+ /* Disable write protection */\r
+ matrix_remove_write_protection(MATRIX0);\r
+\r
+ /* External DDR */\r
+ /* DDR port 0 not used */\r
+ for (i = H64MX_SLAVE_DDR_PORT1; i <= H64MX_SLAVE_DDR_PORT7; i++) {\r
+ matrix_configure_slave_sec(MATRIX0, i, 0xff, 0xff, 0xff);\r
+ matrix_set_slave_split_addr(MATRIX0, i, MATRIX_AREA_128M, 0xf);\r
+ matrix_set_slave_region_size(MATRIX0, i, MATRIX_AREA_128M, 0x1);\r
+ }\r
+}\r
+#endif\r
+\r
+#ifdef CONFIG_HAVE_NANDFLASH\r
+static void matrix_configure_slave_nand(void)\r
+{\r
+ /* Disable write protection */\r
+ matrix_remove_write_protection(MATRIX1);\r
+\r
+ /* NFC Command Register */\r
+ matrix_configure_slave_sec(MATRIX1,\r
+ H32MX_SLAVE_NFC_CMD, 0xc0, 0xc0, 0xc0);\r
+ matrix_set_slave_split_addr(MATRIX1,\r
+ H32MX_SLAVE_NFC_CMD, MATRIX_AREA_128M, 0xc0);\r
+ matrix_set_slave_region_size(MATRIX1,\r
+ H32MX_SLAVE_NFC_CMD, MATRIX_AREA_128M, 0xc0);\r
+\r
+ /* NFC SRAM */\r
+ matrix_configure_slave_sec(MATRIX1,\r
+ H32MX_SLAVE_NFC_SRAM, 0x1, 0x1, 0x1);\r
+ matrix_set_slave_split_addr(MATRIX1,\r
+ H32MX_SLAVE_NFC_SRAM, MATRIX_AREA_8K, 0x1);\r
+ matrix_set_slave_region_size(MATRIX1,\r
+ H32MX_SLAVE_NFC_SRAM, MATRIX_AREA_8K, 0x1);\r
+}\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+void board_setup_tlb(uint32_t *tlb)\r
+{\r
+ uint32_t addr;\r
+\r
+ /* TODO: some peripherals are configured TTB_SECT_STRONGLY_ORDERED\r
+ instead of TTB_SECT_SHAREABLE_DEVICE because their drivers have to\r
+ be verified for correct operation when write-back is enabled */\r
+\r
+ /* Reset table entries */\r
+ for (addr = 0; addr < 4096; addr++)\r
+ tlb[addr] = 0;\r
+\r
+ /* 0x00000000: ROM */\r
+ tlb[0x000] = TTB_SECT_ADDR(0x00000000)\r
+ | TTB_SECT_AP_READ_ONLY\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_CACHEABLE_WB\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x00100000: NFC SRAM */\r
+ tlb[0x001] = TTB_SECT_ADDR(0x00100000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x00200000: SRAM */\r
+ tlb[0x002] = TTB_SECT_ADDR(0x00200000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_CACHEABLE_WB\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x00300000: UDPHS (RAM) */\r
+ tlb[0x003] = TTB_SECT_ADDR(0x00300000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x00400000: UHPHS (OHCI) */\r
+ tlb[0x004] = TTB_SECT_ADDR(0x00400000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x00500000: UDPHS (EHCI) */\r
+ tlb[0x005] = TTB_SECT_ADDR(0x00500000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x00600000: AXIMX */\r
+ tlb[0x006] = TTB_SECT_ADDR(0x00600000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x00700000: DAP */\r
+ tlb[0x007] = TTB_SECT_ADDR(0x00700000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x00a00000: L2CC */\r
+ tlb[0x00a] = TTB_SECT_ADDR(0x00a00000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_TYPE_SECT;\r
+ tlb[0x00b] = TTB_SECT_ADDR(0x00b00000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x10000000: EBI Chip Select 0 */\r
+ for (addr = 0x100; addr < 0x200; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x20000000: DDR Chip Select */\r
+ /* (64MB cacheable, 448MB strongly ordered) */\r
+ for (addr = 0x200; addr < 0x240; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_CACHEABLE_WB\r
+ | TTB_TYPE_SECT;\r
+ for (addr = 0x240; addr < 0x400; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x40000000: DDR AESB Chip Select */\r
+ for (addr = 0x400; addr < 0x600; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_CACHEABLE_WB\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x60000000: EBI Chip Select 1 */\r
+ for (addr = 0x600; addr < 0x700; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x70000000: EBI Chip Select 2 */\r
+ for (addr = 0x700; addr < 0x800; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x80000000: EBI Chip Select 3 */\r
+ for (addr = 0x800; addr < 0x900; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0x90000000: QSPI0/1 AESB MEM */\r
+ for (addr = 0x900; addr < 0xa00; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0xa0000000: SDMMC0 */\r
+ for (addr = 0xa00; addr < 0xb00; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ //| TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0xb0000000: SDMMC1 */\r
+ for (addr = 0xb00; addr < 0xc00; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ //| TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0xc0000000: NFC Command Register */\r
+ for (addr = 0xc00; addr < 0xd00; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC_NEVER\r
+ //| TTB_SECT_SHAREABLE_DEVICE\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0xd0000000: QSPI0/1 MEM */\r
+ for (addr = 0xe00; addr < 0xe00; addr++)\r
+ tlb[addr] = TTB_SECT_ADDR(addr << 20)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0xf0000000: Internal Peripherals */\r
+ tlb[0xf00] = TTB_SECT_ADDR(0xf0000000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0xf8000000: Internal Peripherals */\r
+ tlb[0xf80] = TTB_SECT_ADDR(0xf8000000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+\r
+ /* 0xfc000000: Internal Peripherals */\r
+ tlb[0xfc0] = TTB_SECT_ADDR(0xfc000000)\r
+ | TTB_SECT_AP_FULL_ACCESS\r
+ | TTB_SECT_DOMAIN(0xf)\r
+ | TTB_SECT_EXEC\r
+ | TTB_SECT_STRONGLY_ORDERED\r
+ | TTB_TYPE_SECT;\r
+}\r
+\r
+void board_cfg_l2cc(void)\r
+{\r
+ l2cc_configure(&l2cc_cfg);\r
+}\r
+\r
+void board_cfg_ddram (void)\r
+{\r
+#ifdef BOARD_DDRAM_TYPE\r
+ matrix_configure_slave_ddr();\r
+ struct _mpddrc_desc desc;\r
+ ddram_init_descriptor(&desc, BOARD_DDRAM_TYPE);\r
+ ddram_configure(&desc);\r
+#else\r
+ trace_fatal("Cannot configure DDRAM: target board have no DDRAM type definition!");\r
+#endif\r
+}\r
+\r
+#ifdef CONFIG_HAVE_NANDFLASH\r
+void board_cfg_nand_flash(void)\r
+{\r
+ matrix_configure_slave_nand();\r
+ hsmc_nand_configure(BOARD_NANDFLASH_CS, BOARD_NANDFLASH_BUS_WIDTH);\r
+}\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2013, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for memories configuration on board.\r
+ *\r
+ */\r
+\r
+#ifndef BOARD_MEMORIES_H\r
+#define BOARD_MEMORIES_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Setup TLB for the board\r
+ */\r
+extern void board_setup_tlb(uint32_t *tlb);\r
+\r
+/**\r
+ * \brief Configures L2CC for the board\r
+ */\r
+extern void board_cfg_l2cc(void);\r
+\r
+/**\r
+ * \brief Configures DDR for the board\r
+ */\r
+extern void board_cfg_ddram(void);\r
+\r
+#ifdef CONFIG_HAVE_NANDFLASH\r
+/**\r
+ * \brief Configures SMC for the board NAND flash.\r
+ */\r
+extern void board_cfg_nand_flash(void);\r
+#endif\r
+\r
+#endif /* BOARD_MEMORIES_H */\r
--- /dev/null
+/**\r
+ * \page sama5d2_ptc_engi_board_desc sama5d2-PTC-ENGI - Board Description\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * This file is dedicated to describe the sama5d2-PTC-ENGI board.\r
+ *\r
+ * \section Contents\r
+ *\r
+ * - sama5d2-PTC-ENGI\r
+ * - For sama5d2-PTC-ENGI information, see \subpage sama5d2_ptc_engi_board_info.\r
+ * - For operating frequency information, see \subpage sama5d2_ptc_engi_opfreq.\r
+ * - For using portable PIO definitions, see \subpage sama5d2_ptc_engi_piodef.\r
+ * - For on-board memories, see \subpage sama5d2_ptc_engi_mem.\r
+ * - Several USB definitions are included here, see \subpage sama5d2_ptc_engi_usb.\r
+ * - For External components, see \subpage sama5d2_ptc_engi_extcomp.\r
+ * - For Individual chip definition, see \subpage sama5d2_ptc_engi_chipdef.\r
+ *\r
+ * To get more software details and the full list of parameters related to the\r
+ * sama5d2-PTC-ENGI board configuration, please have a look at the source file:\r
+ * \ref board.h\n\r
+ *\r
+ * \section Usage\r
+ *\r
+ * - The code for booting the board is provided by board_cstartup_xxx.c and\r
+ * board_lowlevel.c.\r
+ * - For using board PIOs, board characteristics (clock, etc.) and external\r
+ * components, see board.h.\r
+ * - For manipulating memories, see board_memories.h.\r
+ *\r
+ * This file can be used as a template and modified to fit a custom board, with\r
+ * specific PIOs usage or memory connections.\r
+ */\r
+\r
+/**\r
+ * \file board.h\r
+ *\r
+ * Definition of sama5d2-PTC-ENGI\r
+ * characteristics, sama5d4-dependant PIOs and external components interfacing.\r
+ */\r
+\r
+#ifndef _BOARD_D2_H\r
+#define _BOARD_D2_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include "board_lowlevel.h"\r
+#include "board_memories.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * HW BOARD Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \page sama5d2_ptc_engi_board_info "sama5d2-PTC-ENGI - Board informations"\r
+ * This page lists several definition related to the board description.\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_NAME\r
+ */\r
+\r
+/** Name of the board */\r
+#define BOARD_NAME "sama5d2-ptc-engi"\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sama5d2_ptc_engi_opfreq "sama5d2-PTC-ENGI - Operating frequencies"\r
+ * This page lists several definition related to the board operating frequency\r
+ * (when using the initialization done by board_lowlevel.c).\r
+ */\r
+\r
+/** Frequency of the board slow clock oscillator */\r
+#define BOARD_SLOW_CLOCK_EXT_OSC 32768\r
+\r
+/** Frequency of the board main clock oscillator */\r
+#define BOARD_MAIN_CLOCK_EXT_OSC 12000000\r
+\r
+/** /def Definition of DDRAM's type */\r
+#define BOARD_DDRAM_TYPE MT41K128M16\r
+\r
+/** \def Board DDR memory size in bytes */\r
+#define BOARD_DDR_MEMORY_SIZE 512*1024*1024\r
+\r
+/** \def Board PIT tick resolution */\r
+#define BOARD_TIMER_RESOLUTION 1000\r
+\r
+/* =================== PIN CONSOLE definition ================== */\r
+\r
+/** CONSOLE pin definition, Use only UART */\r
+#define PINS_CONSOLE PINS_UART0_IOS1\r
+#define CONSOLE_PER_ADD UART0\r
+#define CONSOLE_ID ID_UART0\r
+#define CONSOLE_BAUDRATE 57600\r
+#define CONSOLE_DRIVER DRV_UART\r
+\r
+/* =================== PIN LED definition ====================== */\r
+\r
+/* RGB LED index */\r
+#define LED_RED 0\r
+#define LED_GREEN 1\r
+#define LED_BLUE 2\r
+\r
+/** LED #0 pin definition (Red). */\r
+#define PIN_LED_0 { PIO_GROUP_A, PIO_PA30, PIO_OUTPUT_1, PIO_OPENDRAIN }\r
+\r
+/** LED #1 pin definition (Green). */\r
+#define PIN_LED_1 { PIO_GROUP_A, PIO_PA31, PIO_OUTPUT_1, PIO_OPENDRAIN }\r
+\r
+/** LED #2 pin definition (Blue). */\r
+#define PIN_LED_2 { PIO_GROUP_B, PIO_PB2, PIO_OUTPUT_1, PIO_OPENDRAIN }\r
+\r
+/** List of all LEDs definitions. */\r
+#define PINS_LEDS { PIN_LED_0, PIN_LED_1, PIN_LED_2 }\r
+\r
+/* =================== PIN PUSH BUTTON definition ============== */\r
+\r
+#define PIO_CFG_PB (PIO_PULLUP | PIO_DEBOUNCE)\r
+\r
+#define PIN_PUSHBUTTON_1 { PIO_GROUP_B, PIO_PB9, PIO_INPUT, PIO_CFG_PB }\r
+\r
+/** List of all push button definitions. */\r
+#define PINS_PUSHBUTTONS { PIN_PUSHBUTTON_1 }\r
+\r
+/** Push button index. */\r
+#define PUSHBUTTON_BP1 0\r
+\r
+/* ================== ACT8945A PMIC definition ====================== */\r
+\r
+#define ACT8945A_PINS PINS_FLEXCOM4_TWI_IOS3\r
+#define ACT8945A_ADDR TWI0\r
+#define ACT8945A_FREQ 400000\r
+#define ACT8945A_PIN_CHGLEV \\r
+ { PIO_GROUP_A, PIO_PA22, PIO_OUTPUT_0, PIO_PULLUP }\r
+#define ACT8945A_PIN_IRQ \\r
+ { PIO_GROUP_B, PIO_PB13, PIO_INPUT, PIO_PULLUP | PIO_IT_FALL_EDGE }\r
+#define ACT8945A_PIN_LBO \\r
+ { PIO_GROUP_C, PIO_PC8, PIO_INPUT, PIO_PULLUP }\r
+\r
+/* ================== PIN USB definition ======================= */\r
+\r
+/** USB VBus pin */\r
+#define PIN_USB_VBUS {\\r
+ { PIO_GROUP_A, PIO_PA27, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_BOTH_EDGE },\\r
+}\r
+\r
+/** USB OverCurrent detection*/\r
+#define PIN_USB_OVCUR {\\r
+ { PIO_GROUP_A, PIO_PA29, PIO_INPUT, PIO_DEFAULT },\\r
+}\r
+\r
+/** USB Power Enable B, Active high */\r
+#define PIN_USB_POWER_ENB {\\r
+ { PIO_GROUP_A, PIO_PBA28, PIO_OUTPUT_0, PIO_DEFAULT },\\r
+}\r
+\r
+/* =================== AT25 device definition =================== */\r
+\r
+#define AT25_PINS PINS_SPI0_NPCS0_IOS1\r
+#define AT25_ADDR SPI0\r
+#define AT25_CS 0\r
+#define AT25_ATTRS (SPI_MR_MODFDIS | SPI_MR_WDRBT | SPI_MR_MSTR)\r
+#define AT25_FREQ 40000 /* (value in KHz) */\r
+#define AT25_LOW_FREQ 20000 /* (value in KHz) */\r
+#define AT25_DLYBS 0\r
+#define AT25_DLYCT 0\r
+#define AT25_SPI_MODE (SPI_CSR_NCPHA | SPI_CSR_BITS_8_BIT)\r
+\r
+/* =================== AT24 device definition =================== */\r
+#define AT24_PINS PINS_TWI1_IOS1;\r
+#define AT24_ADDR ((Twi*)TWIHS1)\r
+#define AT24_FREQ 400000\r
+#define AT24_DESC {"AT24MAC402", 0xFF, 16}\r
+\r
+/* =================== GMAC/PHY definition =================== */\r
+\r
+#define GMAC0_ADDR GMAC0\r
+#define GMAC0_PINS PINS_GMAC_RMII_IOS3\r
+#define GMAC0_PHY_ADDR 0\r
+#define GMAC0_PHY_IRQ_PIN PIN_GTSUCOM_IOS1\r
+#define GMAC0_PHY_RETRIES PHY_DEFAULT_RETRIES\r
+\r
+/* =================== NANDFLASH device definition =================== */\r
+\r
+#define BOARD_NANDFLASH_PINS PINS_NFC_IOS2\r
+#define BOARD_NANDFLASH_ADDR EBI_CS3_ADDR\r
+#define BOARD_NANDFLASH_CS 3\r
+#define BOARD_NANDFLASH_BUS_WIDTH 8\r
+\r
+#endif /* #ifndef _BOARD_D2_H */\r
--- /dev/null
+/**\r
+ * \page sama5d2_xult_board_desc sama5d2-XULT - Board Description\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * This file is dedicated to describe the sama5d2-XULT board.\r
+ *\r
+ * \section Contents\r
+ *\r
+ * - sama5d2-XULT\r
+ * - For sama5d2-XULT information, see \subpage sama5d2_xult_board_info.\r
+ * - For operating frequency information, see \subpage sama5d2_xult_opfreq.\r
+ * - For using portable PIO definitions, see \subpage sama5d2_xult_piodef.\r
+ * - For on-board memories, see \subpage sama5d2_xult_mem.\r
+ * - Several USB definitions are included here, see \subpage sama5d2_xult_usb.\r
+ * - For External components, see \subpage sama5d2_xult_extcomp.\r
+ * - For Individual chip definition, see \subpage sama5d2_xult_chipdef.\r
+ *\r
+ * To get more software details and the full list of parameters related to the\r
+ * sama5d2-XULT board configuration, please have a look at the source file:\r
+ * \ref board.h\n\r
+ *\r
+ * \section Usage\r
+ *\r
+ * - The code for booting the board is provided by board_cstartup_xxx.c and\r
+ * board_lowlevel.c.\r
+ * - For using board PIOs, board characteristics (clock, etc.) and external\r
+ * components, see board.h.\r
+ * - For manipulating memories, see board_memories.h.\r
+ *\r
+ * This file can be used as a template and modified to fit a custom board, with\r
+ * specific PIOs usage or memory connections.\r
+ */\r
+\r
+/**\r
+ * \file board.h\r
+ *\r
+ * Definition of sama5d2-xb\r
+ * characteristics, sama5d2-dependant PIOs and external components interfacing.\r
+ */\r
+\r
+#ifndef _BOARD_D2_H\r
+#define _BOARD_D2_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include "board_lowlevel.h"\r
+#include "board_memories.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * HW BOARD Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \page sama5d2_vb_board_info "sama5d2-vb - Board informations"\r
+ * This page lists several definition related to the board description.\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_NAME\r
+ */\r
+\r
+/** Name of the board */\r
+#define BOARD_NAME "sama5d2-vb-bga196"\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sama5d2_xult_opfreq "sama5d2-XULT - Operating frequencies"\r
+ * This page lists several definition related to the board operating frequency\r
+ * (when using the initialization done by board_lowlevel.c).\r
+ */\r
+\r
+/** Frequency of the board slow clock oscillator */\r
+#define BOARD_SLOW_CLOCK_EXT_OSC 32768\r
+\r
+/** Frequency of the board main clock oscillator */\r
+#define BOARD_MAIN_CLOCK_EXT_OSC 12000000\r
+\r
+/** \def Board PIT tick resolution */\r
+#define BOARD_TIMER_RESOLUTION 1000\r
+\r
+/* =================== PIN CONSOLE definition ================== */\r
+\r
+/** CONSOLE pin definition, Use only UART */\r
+#define PINS_CONSOLE PINS_UART0_IOS1\r
+#define CONSOLE_PER_ADD UART0\r
+#define CONSOLE_ID ID_UART0\r
+#define CONSOLE_BAUDRATE 57600\r
+#define CONSOLE_DRIVER DRV_UART\r
+\r
+/* =================== PIN LED definition ====================== */\r
+\r
+/* RGB LED index */\r
+#define LED_RED 0 /* led red shared with SDMMC0 (eMMC) card detect used only by RomBoot */\r
+#define LED_GREEN 1\r
+#define LED_BLUE 2\r
+\r
+/** LED #0 pin definition (Red). */\r
+#define PIN_LED_0 { PIO_GROUP_D, PIO_PD21, PIO_OUTPUT_0, PIO_OPENDRAIN }\r
+\r
+/** LED #1 pin definition (Green). */\r
+#define PIN_LED_1 { PIO_GROUP_D, PIO_PD22, PIO_OUTPUT_0, PIO_OPENDRAIN }\r
+\r
+/** List of all LEDs definitions. */\r
+#define PINS_LEDS { PIN_LED_0, PIN_LED_1 }\r
+\r
+/* =================== PIN PUSH BUTTON definition ============== */\r
+\r
+#define PIO_CFG_PB (PIO_PULLUP | PIO_DEBOUNCE)\r
+\r
+#define PIN_PUSHBUTTON_1 { PIO_GROUP_D, PIO_PD19, PIO_INPUT, PIO_CFG_PB }\r
+\r
+#define PIN_PUSHBUTTON_2 { PIO_GROUP_D, PIO_PD20, PIO_INPUT, PIO_CFG_PB }\r
+\r
+/** List of all push button definitions. */\r
+#define PINS_PUSHBUTTONS { PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 }\r
+\r
+/** Push button index. */\r
+#define PUSHBUTTON_BP1 0\r
+#define PUSHBUTTON_BP2 1\r
+\r
+/* ================== PIN USB definition ======================= */\r
+\r
+/** USB VBus pin */\r
+#define PIN_USB_VBUS {\\r
+ { PIO_GROUP_A, PIO_PA31, PIO_INPUT, PIO_DEFAULT },\\r
+}\r
+/** USB OverCurrent detection*/\r
+#define PIN_USB_OVCUR {\\r
+ { PIO_GROUP_A, PIO_PA29, PIO_INPUT, PIO_DEFAULT },\\r
+}\r
+/** USB Power Enable A, Active high */\r
+#define PIN_USB_POWER_ENA {\\r
+ { PIO_GROUP_B, PIO_PB9, PIO_OUTPUT_0, PIO_DEFAULT },\\r
+}\r
+/** USB Power Enable B, Active high */\r
+#define PIN_USB_POWER_ENB {\\r
+ { PIO_GROUP_B, PIO_PB10, PIO_OUTPUT_0, PIO_DEFAULT },\\r
+}\r
+\r
+/* ================= PIN LCD IRQ definition ===================== */\r
+\r
+#define PIO_CFG_LCD_IRQ (PIO_PULLUP | PIO_IT_FALL_EDGE)\r
+\r
+#define PIN_QT1070_IRQ {\\r
+ { PIO_GROUP_B, PIO_PB7, PIO_INPUT, PIO_CFG_LCD_IRQ },\\r
+}\r
+#define PIN_MXT336S_IRQ {\\r
+ { PIO_GROUP_B, PIO_PB8, PIO_INPUT, PIO_CFG_LCD_IRQ },\\r
+}\r
+#define PIN_MXT768E_IRQ {\\r
+ { PIO_GROUP_B, PIO_PB8, PIO_INPUT, PIO_CFG_LCD_IRQ },\\r
+}\r
+\r
+/* =================== PIN ISC definition ======================= */\r
+\r
+#define PIN_ISC_RST {\\r
+ { PIO_GROUP_B, PIO_PB11, PIO_OUTPUT_1, PIO_DEFAULT },\\r
+}\r
+#define PIN_ISC_PWD {\\r
+ { PIO_GROUP_B, PIO_PB12, PIO_OUTPUT_1, PIO_DEFAULT },\\r
+}\r
+\r
+/* =================== PIN SDMMC definition ===================== */\r
+\r
+#define SDMMC0_PINS { PINS_SDMMC0_4B_IOS1, PIN_SDMMC0_CK_IOS1,\\r
+ PIN_SDMMC0_CD_IOS1, PIN_SDMMC0_RSTN_IOS1,\\r
+ PIN_SDMMC0_WP_IOS1 }\r
+\r
+/* =================== PIN CAN definition ======================= */\r
+/* CAN0 {PC1; PC2} is wired to the J18 connector via an AT6561 transceiver. */\r
+\r
+#define CAN0_PINS PINS_CAN0_IOS0\r
+\r
+/* =================== NANDFLASH device definition =================== */\r
+\r
+#define BOARD_NANDFLASH_PINS PINS_NFC_IOS1\r
+#define BOARD_NANDFLASH_ADDR EBI_CS3_ADDR\r
+#define BOARD_NANDFLASH_CS 3\r
+#define BOARD_NANDFLASH_BUS_WIDTH 8\r
+\r
+#endif /* #ifndef _BOARD_D2_H */\r
--- /dev/null
+/**\r
+ * \page sama5d2_xult_board_desc sama5d2-XULT - Board Description\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * This file is dedicated to describe the sama5d2-XULT board.\r
+ *\r
+ * \section Contents\r
+ *\r
+ * - sama5d2-XULT\r
+ * - For sama5d2-XULT information, see \subpage sama5d2_xult_board_info.\r
+ * - For operating frequency information, see \subpage sama5d2_xult_opfreq.\r
+ * - For using portable PIO definitions, see \subpage sama5d2_xult_piodef.\r
+ * - For on-board memories, see \subpage sama5d2_xult_mem.\r
+ * - Several USB definitions are included here, see \subpage sama5d2_xult_usb.\r
+ * - For External components, see \subpage sama5d2_xult_extcomp.\r
+ * - For Individual chip definition, see \subpage sama5d2_xult_chipdef.\r
+ *\r
+ * To get more software details and the full list of parameters related to the\r
+ * sama5d2-XULT board configuration, please have a look at the source file:\r
+ * \ref board.h\n\r
+ *\r
+ * \section Usage\r
+ *\r
+ * - The code for booting the board is provided by board_cstartup_xxx.c and\r
+ * board_lowlevel.c.\r
+ * - For using board PIOs, board characteristics (clock, etc.) and external\r
+ * components, see board.h.\r
+ * - For manipulating memories, see board_memories.h.\r
+ *\r
+ * This file can be used as a template and modified to fit a custom board, with\r
+ * specific PIOs usage or memory connections.\r
+ */\r
+\r
+/**\r
+ * \file board.h\r
+ *\r
+ * Definition of sama5d2-xb\r
+ * characteristics, sama5d2-dependant PIOs and external components interfacing.\r
+ */\r
+\r
+#ifndef _BOARD_D2_H\r
+#define _BOARD_D2_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include "board_lowlevel.h"\r
+#include "board_memories.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * HW BOARD Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \page sama5d2_vb_board_info "sama5d2-vb - Board informations"\r
+ * This page lists several definition related to the board description.\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_NAME\r
+ */\r
+\r
+/** Name of the board */\r
+#define BOARD_NAME "sama5d2-vb-bga289"\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sama5d2_xult_opfreq "sama5d2-XULT - Operating frequencies"\r
+ * This page lists several definition related to the board operating frequency\r
+ * (when using the initialization done by board_lowlevel.c).\r
+ */\r
+\r
+/** Frequency of the board slow clock oscillator */\r
+#define BOARD_SLOW_CLOCK_EXT_OSC 32768\r
+\r
+/** Frequency of the board main clock oscillator */\r
+#define BOARD_MAIN_CLOCK_EXT_OSC 12000000\r
+\r
+/** \def Board PIT tick resolution */\r
+#define BOARD_TIMER_RESOLUTION 1000\r
+\r
+/* =================== PIN CONSOLE definition ================== */\r
+\r
+/** CONSOLE pin definition, Use only UART */\r
+#define PINS_CONSOLE PINS_UART0_IOS1\r
+#define CONSOLE_PER_ADD UART0\r
+#define CONSOLE_ID ID_UART0\r
+#define CONSOLE_BAUDRATE 57600\r
+#define CONSOLE_DRIVER DRV_UART\r
+\r
+/* =================== PIN LED definition ====================== */\r
+\r
+/* RGB LED index */\r
+#define LED_RED 0 /* led red shared with SDMMC0 (eMMC) card detect used only by RomBoot */\r
+#define LED_GREEN 1\r
+#define LED_BLUE 2\r
+\r
+/** LED #0 pin definition (Red). */\r
+#define PIN_LED_0 { PIO_GROUP_D, PIO_PD21, PIO_OUTPUT_0, PIO_OPENDRAIN }\r
+\r
+/** LED #1 pin definition (Green). */\r
+#define PIN_LED_1 { PIO_GROUP_D, PIO_PD22, PIO_OUTPUT_0, PIO_OPENDRAIN }\r
+\r
+/** List of all LEDs definitions. */\r
+#define PINS_LEDS { PIN_LED_0, PIN_LED_1 }\r
+\r
+/* =================== PIN PUSH BUTTON definition ============== */\r
+\r
+#define PIO_CFG_PB (PIO_PULLUP | PIO_DEBOUNCE)\r
+\r
+#define PIN_PUSHBUTTON_1 { PIO_GROUP_D, PIO_PD23, PIO_INPUT, PIO_CFG_PB }\r
+\r
+#define PIN_PUSHBUTTON_2 { PIO_GROUP_D, PIO_PD24, PIO_INPUT, PIO_CFG_PB }\r
+\r
+/** List of all push button definitions. */\r
+#define PINS_PUSHBUTTONS { PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 }\r
+\r
+/** Push button index. */\r
+#define PUSHBUTTON_BP1 0\r
+#define PUSHBUTTON_BP2 1\r
+\r
+/* ================== PIN USB definition ======================= */\r
+\r
+/** USB VBus pin */\r
+#define PIN_USB_VBUS {\\r
+ { PIO_GROUP_C, PIO_PC29, PIO_INPUT, PIO_DEFAULT },\\r
+}\r
+/** USB OverCurrent detection*/\r
+#define PIN_USB_OVCUR {\\r
+ { PIO_GROUP_C, PIO_PC31, PIO_INPUT, PIO_DEFAULT },\\r
+}\r
+/** USB Power Enable A, Active high */\r
+#define PIN_USB_POWER_ENA {\\r
+ { PIO_GROUP_C, PIO_PC30, PIO_OUTPUT_0, PIO_DEFAULT },\\r
+}\r
+/** USB Power Enable B, Active high */\r
+#define PIN_USB_POWER_ENB {\\r
+ { PIO_GROUP_D, PIO_PD0, PIO_OUTPUT_0, PIO_DEFAULT },\\r
+}\r
+\r
+/* ================= PIN LCD IRQ definition ===================== */\r
+\r
+#define PIO_CFG_LCD_IRQ (PIO_PULLUP | PIO_IT_FALL_EDGE)\r
+\r
+#define PIN_QT1070_IRQ {\\r
+ { PIO_GROUP_B, PIO_PB7, PIO_INPUT, PIO_CFG_LCD_IRQ },\\r
+}\r
+#define PIN_MXT336S_IRQ {\\r
+ { PIO_GROUP_B, PIO_PB8, PIO_INPUT, PIO_CFG_LCD_IRQ },\\r
+}\r
+#define PIN_MXT768E_IRQ {\\r
+ { PIO_GROUP_B, PIO_PB8, PIO_INPUT, PIO_CFG_LCD_IRQ },\\r
+}\r
+\r
+/* =================== PIN ISC definition ======================= */\r
+\r
+#define PIN_ISC_RST {\\r
+ { PIO_GROUP_B, PIO_PB11, PIO_OUTPUT_1, PIO_DEFAULT },\\r
+}\r
+#define PIN_ISC_PWD {\\r
+ { PIO_GROUP_B, PIO_PB12, PIO_OUTPUT_1, PIO_DEFAULT },\\r
+}\r
+\r
+/* =================== PIN SDMMC definition ===================== */\r
+\r
+#define SDMMC0_PINS { PINS_SDMMC0_8B_IOS1, PIN_SDMMC0_CK_IOS1,\\r
+ PIN_SDMMC0_CD_IOS1, PIN_SDMMC0_VDDSEL_IOS1,\\r
+ PIN_SDMMC0_RSTN_IOS1, PIN_SDMMC0_WP_IOS1 }\r
+\r
+#define SDMMC1_PINS { PINS_SDMMC1_4B_IOS1, PIN_SDMMC1_CK_IOS1,\\r
+ PIN_SDMMC1_CD_IOS1, PIN_SDMMC1_RSTN_IOS1,\\r
+ PIN_SDMMC1_WP_IOS1 }\r
+\r
+/* =================== PIN CAN definition ======================= */\r
+/* CAN0 {PC1; PC2} is wired to the J18 connector via an AT6561 transceiver. */\r
+/* CAN1 {PC26; PC27} is wired to the J19 connector via an AT6561 transceiver. */\r
+\r
+#define CAN0_PINS PINS_CAN0_IOS0\r
+\r
+#ifdef MCAN1\r
+#define CAN1_PINS PINS_CAN1_IOS0\r
+#endif\r
+\r
+/* =================== NANDFLASH device definition =================== */\r
+\r
+#define BOARD_NANDFLASH_PINS PINS_NFC_IOS1\r
+#define BOARD_NANDFLASH_ADDR EBI_CS3_ADDR\r
+#define BOARD_NANDFLASH_CS 3\r
+#define BOARD_NANDFLASH_BUS_WIDTH 8\r
+\r
+#endif /* #ifndef _BOARD_D2_H */\r
--- /dev/null
+/**\r
+ * \page sama5d2_xult_board_desc sama5d2-XULT - Board Description\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * This file is dedicated to describe the sama5d2-XULT board.\r
+ *\r
+ * \section Contents\r
+ *\r
+ * - sama5d2-XULT\r
+ * - For sama5d2-XULT information, see \subpage sama5d2_xult_board_info.\r
+ * - For operating frequency information, see \subpage sama5d2_xult_opfreq.\r
+ * - For using portable PIO definitions, see \subpage sama5d2_xult_piodef.\r
+ * - For on-board memories, see \subpage sama5d2_xult_mem.\r
+ * - Several USB definitions are included here, see \subpage sama5d2_xult_usb.\r
+ * - For External components, see \subpage sama5d2_xult_extcomp.\r
+ * - For Individual chip definition, see \subpage sama5d2_xult_chipdef.\r
+ *\r
+ * To get more software details and the full list of parameters related to the\r
+ * sama5d2-XULT board configuration, please have a look at the source file:\r
+ * \ref board.h\n\r
+ *\r
+ * \section Usage\r
+ *\r
+ * - The code for booting the board is provided by board_cstartup_xxx.c and\r
+ * board_lowlevel.c.\r
+ * - For using board PIOs, board characteristics (clock, etc.) and external\r
+ * components, see board.h.\r
+ * - For manipulating memories, see board_memories.h.\r
+ *\r
+ * This file can be used as a template and modified to fit a custom board, with\r
+ * specific PIOs usage or memory connections.\r
+ */\r
+\r
+/**\r
+ * \file board.h\r
+ *\r
+ * Definition of sama5d2-XULT\r
+ * characteristics, sama5d4-dependant PIOs and external components interfacing.\r
+ */\r
+\r
+#ifndef _BOARD_D2_H\r
+#define _BOARD_D2_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include "board_lowlevel.h"\r
+#include "board_memories.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * HW BOARD Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \page sama5d2_xult_board_info "sama5d2-XULT - Board informations"\r
+ * This page lists several definition related to the board description.\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_NAME\r
+ */\r
+\r
+/** Name of the board */\r
+#define BOARD_NAME "sama5d2-xult-proto"\r
+\r
+/** Family definition */\r
+#if !defined sama5d2\r
+ #define sama5d2\r
+#endif\r
+\r
+/** Board definition */\r
+#define sama5d2xult\r
+\r
+/** Core definition */\r
+#define cortexa5\r
+\r
+#define BOARD_REV_A_XULT\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sama5d2_xult_opfreq "sama5d2-XULT - Operating frequencies"\r
+ * This page lists several definition related to the board operating frequency\r
+ * (when using the initialization done by board_lowlevel.c).\r
+ */\r
+\r
+/** Frequency of the board slow clock oscillator */\r
+#define BOARD_SLOW_CLOCK_EXT_OSC 32768\r
+\r
+/** Frequency of the board main clock oscillator */\r
+#define BOARD_MAIN_CLOCK_EXT_OSC 12000000\r
+\r
+/** /def Definition of DDRAM's type */\r
+#define BOARD_DDRAM_TYPE MT41K128M16\r
+\r
+/** \def Board DDR memory size in bytes */\r
+#define BOARD_DDR_MEMORY_SIZE 512*1024*1024\r
+\r
+/** \def Board PIT tick resolution */\r
+#define BOARD_TIMER_RESOLUTION 1000\r
+\r
+/* =================== PIN CONSOLE definition ================== */\r
+\r
+/** CONSOLE pin definition, Use only UART */\r
+#define PINS_CONSOLE PINS_UART1_IOS1\r
+#define CONSOLE_PER_ADD UART1\r
+#define CONSOLE_ID ID_UART1\r
+#define CONSOLE_BAUDRATE 57600\r
+#define CONSOLE_DRIVER DRV_UART\r
+\r
+/* =================== PIN LED definition ====================== */\r
+\r
+/* RGB LED index */\r
+#define LED_RED 0 /* led red shared with SDMMC0 (eMMC) card detect used only by RomBoot */\r
+#define LED_GREEN 1\r
+#define LED_BLUE 2\r
+\r
+/** LED #0 pin definition (Red). */\r
+#define PIN_LED_0 { PIO_GROUP_A, PIO_PA13, PIO_OUTPUT_0, PIO_OPENDRAIN }\r
+\r
+/** LED #1 pin definition (Green). */\r
+#define PIN_LED_1 { PIO_GROUP_B, PIO_PB5, PIO_OUTPUT_1, PIO_OPENDRAIN }\r
+\r
+/** LED #2 pin definition (Blue). */\r
+#define PIN_LED_2 { PIO_GROUP_B, PIO_PB0, PIO_OUTPUT_1, PIO_OPENDRAIN }\r
+\r
+/** List of all LEDs definitions. */\r
+#define PINS_LEDS { PIN_LED_0, PIN_LED_1, PIN_LED_2 }\r
+\r
+/* =================== LWM LED definition ====================== */\r
+\r
+/** LED #1 PWM Channel */\r
+#define PWM_LED_CH_0 2\r
+\r
+/** LED #2 PWM Channel */\r
+#define PWM_LED_CH_1 1\r
+\r
+/** LED #1 pin definition (Green). */\r
+#define PIN_PWM_LED_0 { PIO_GROUP_B, PIO_PB5C_PWMH2, PIO_PERIPH_C, PIO_PULLUP }\r
+\r
+/** LED #2 pin definition (Blue). */\r
+#define PIN_PWM_LED_1 { PIO_GROUP_B, PIO_PB0D_PWMH1, PIO_PERIPH_D, PIO_PULLUP }\r
+\r
+/** List of all PWM LED channels */\r
+#define PWM_LEDS_CH { PWM_LED_CH_0, PWM_LED_CH_1 }\r
+\r
+/** List of all LEDs definitions in PWM mode (red LED is not on a PWM pin) */\r
+#define PINS_PWM_LEDS { PIN_PWM_LED_0, PIN_PWM_LED_1 }\r
+\r
+/* =================== PIN PUSH BUTTON definition ============== */\r
+\r
+#define PIO_CFG_PB (PIO_PULLUP | PIO_DEBOUNCE)\r
+\r
+#define PIN_PUSHBUTTON_1 { PIO_GROUP_B, PIO_PB6, PIO_INPUT, PIO_CFG_PB }\r
+\r
+/** List of all push button definitions. */\r
+#define PINS_PUSHBUTTONS { PIN_PUSHBUTTON_1 }\r
+\r
+/** Push button index. */\r
+#define PUSHBUTTON_BP1 0\r
+\r
+/* ================== ACT8945A PMIC definition ====================== */\r
+\r
+#define ACT8945A_PINS PINS_FLEXCOM4_TWI_IOS3\r
+#define ACT8945A_ADDR TWI4\r
+#define ACT8945A_FREQ 400000\r
+#define ACT8945A_PIN_CHGLEV \\r
+ { PIO_GROUP_A, PIO_PA12, PIO_OUTPUT_0, PIO_PULLUP }\r
+#define ACT8945A_PIN_IRQ \\r
+ { PIO_GROUP_B, PIO_PB13, PIO_INPUT, PIO_PULLUP | PIO_IT_FALL_EDGE }\r
+#define ACT8945A_PIN_LBO \\r
+ { PIO_GROUP_A, PIO_PB13, PIO_INPUT, PIO_PULLUP }\r
+\r
+/* ================== PIN USB definition ======================= */\r
+\r
+/** USB VBus pin */\r
+#define PIN_USB_VBUS {\\r
+ { PIO_GROUP_A, PIO_PA31, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_BOTH_EDGE },\\r
+}\r
+/** USB OverCurrent detection*/\r
+#define PIN_USB_OVCUR {\\r
+ { PIO_GROUP_A, PIO_PA29, PIO_INPUT, PIO_DEFAULT },\\r
+}\r
+/** USB Power Enable A, Active high */\r
+#define PIN_USB_POWER_ENA {\\r
+ { PIO_GROUP_B, PIO_PB9, PIO_OUTPUT_0, PIO_DEFAULT },\\r
+}\r
+/** USB Power Enable B, Active high */\r
+#define PIN_USB_POWER_ENB {\\r
+ { PIO_GROUP_B, PIO_PB10, PIO_OUTPUT_0, PIO_DEFAULT },\\r
+}\r
+\r
+/* ================= PIN LCD IRQ definition ===================== */\r
+\r
+#define PIO_CFG_LCD_IRQ (PIO_PULLUP | PIO_IT_FALL_EDGE)\r
+\r
+#define PIN_QT1070_IRQ {\\r
+ { PIO_GROUP_B, PIO_PB8, PIO_INPUT, PIO_CFG_LCD_IRQ },\\r
+}\r
+#define PIN_MXT336S_IRQ {\\r
+ { PIO_GROUP_B, PIO_PB7, PIO_INPUT, PIO_CFG_LCD_IRQ },\\r
+}\r
+#define PIN_MXT768E_IRQ {\\r
+ { PIO_GROUP_B, PIO_PB7, PIO_INPUT, PIO_CFG_LCD_IRQ },\\r
+}\r
+\r
+/* =================== PIN ISC definition ======================= */\r
+\r
+#define ISC_TWI_ADDR ((Twi*)TWIHS0)\r
+#define ISC_TWI_PINS PINS_TWI0_IOS4\r
+#define ISC_PINS PINS_ISC_IOS3\r
+#define ISC_PIN_RST { PIO_GROUP_B, PIO_PB11, PIO_OUTPUT_1, PIO_DEFAULT }\r
+#define ISC_PIN_PWD { PIO_GROUP_B, PIO_PB12, PIO_OUTPUT_1, PIO_DEFAULT }\r
+\r
+/* =================== PIN ClassD definition ==================== */\r
+\r
+#define CLASSD_PINS PINS_CLASSD_IOS1\r
+\r
+/* =================== PIN SDMMC definition ===================== */\r
+\r
+#define SDMMC0_PINS { PINS_SDMMC0_8B_IOS1, PIN_SDMMC0_CK_IOS1,\\r
+ PIN_SDMMC0_VDDSEL_IOS1, PIN_SDMMC0_RSTN_IOS1 }\r
+\r
+#define SDMMC1_PINS { PINS_SDMMC1_4B_IOS1, PIN_SDMMC1_CK_IOS1,\\r
+ PIN_SDMMC1_CD_IOS1 }\r
+\r
+/* =================== AT25 device definition =================== */\r
+\r
+#define AT25_PINS PINS_SPI0_NPCS0_IOS1\r
+#define AT25_ADDR SPI0\r
+#define AT25_CS 0\r
+#define AT25_ATTRS (SPI_MR_MODFDIS | SPI_MR_WDRBT | SPI_MR_MSTR)\r
+#define AT25_FREQ 40000 /* (value in KHz) */\r
+#define AT25_LOW_FREQ 20000 /* (value in KHz) */\r
+#define AT25_DLYBS 0\r
+#define AT25_DLYCT 0\r
+#define AT25_SPI_MODE (SPI_CSR_NCPHA | SPI_CSR_BITS_8_BIT)\r
+\r
+/* =================== AT24 device definition =================== */\r
+#define AT24_PINS PINS_TWI1_IOS2;\r
+#define AT24_ADDR ((Twi*)TWIHS1)\r
+#define AT24_FREQ 400000\r
+#define AT24_DESC {"AT24MAC402", 0xFF, 16}\r
+\r
+/* =================== QSPI serial flashdevice definition ======= */\r
+\r
+#define QSPIFLASH_PINS PINS_QSPI0_IOS3\r
+#define QSPIFLASH_ADDR QSPI0\r
+#define QSPIFLASH_BAUDRATE 50000000 /* 50 MHz */\r
+\r
+/* =================== CAN device definition ==================== */\r
+/* Both ports are wired to the J9 connector:\r
+ * CANTX0 = PC10 = J9:8\r
+ * CANRX0 = PC11 = J9:7\r
+ * CANTX1 = PC26 = J9:6\r
+ * CANRX1 = PC27 = J9:5 */\r
+\r
+#define CAN0_PINS PINS_CAN0_IOS1\r
+#define CAN1_PINS PINS_CAN1_IOS0\r
+\r
+/* =================== GMAC/PHY definition =================== */\r
+\r
+#define GMAC0_ADDR GMAC0\r
+#define GMAC0_PINS PINS_GMAC_RMII_IOS3\r
+#define GMAC0_PHY_ADDR 0\r
+#define GMAC0_PHY_IRQ_PIN PIN_GTSUCOM_IOS1\r
+#define GMAC0_PHY_RETRIES PHY_DEFAULT_RETRIES\r
+\r
+/* =================== ILI9488 device definition =================== */\r
+/* Connected on board A5D2, XPRO EXT2 connector */\r
+\r
+/* ILI9488 ID code */\r
+#define ILI9488_DEVICE_CODE 0x2810\r
+\r
+#define ILI9488_PINS PINS_SPI1_NPCS1_IOS3\r
+#define ILI9488_ADDR SPI1\r
+#define ILI9488_CS 1\r
+#define ILI9488_ATTRS (SPI_MR_MODFDIS | SPI_MR_MSTR) // | SPI_MR_WDRBT\r
+#define ILI9488_FREQ 40000 /* (value in KHz) */\r
+#define ILI9488_DLYBS 100\r
+#define ILI9488_DLYCT 100\r
+//#define ILI9488_SPI_MODE (SPI_CSR_NCPHA | SPI_CSR_BITS_9_BIT)\r
+#define ILI9488_SPI_MODE (SPI_CSR_CPOL | SPI_CSR_BITS_9_BIT)\r
+\r
+#define MXTX_RESET_PIN {\\r
+ {PIO_GROUP_D, PIO_PD28, PIO_OUTPUT_1, PIO_DEFAULT} \\r
+ }\r
+#define MXTX_BACKLIGHT_PIN {\\r
+ {PIO_GROUP_B, PIO_PB5C_PWMH2, PIO_PERIPH_C, PIO_DEFAULT} \\r
+ }\r
+\r
+/* =================== LCD Touch board definition =================== */\r
+\r
+/** PIO pins for LCD */\r
+#define BOARD_LCD_PINS PINS_LCD_IOS2\r
+\r
+/** Display width in pixels. */\r
+#define BOARD_LCD_WIDTH 480\r
+/** Display height in pixels. */\r
+#define BOARD_LCD_HEIGHT 272\r
+/** Frame rate in Hz. */\r
+#define BOARD_LCD_FRAMERATE 40\r
+\r
+/** Vertical front porch in number of lines. */\r
+#define BOARD_LCD_TIMING_VFP 22\r
+/** Vertical back porch in number of lines. */\r
+#define BOARD_LCD_TIMING_VBP 21\r
+/** Vertical pulse width in number of lines. */\r
+#define BOARD_LCD_TIMING_VPW 2\r
+/** Horizontal front porch in LCDDOTCLK cycles. */\r
+#define BOARD_LCD_TIMING_HFP 64\r
+/** Horizontal back porch in LCDDOTCLK cycles. */\r
+#define BOARD_LCD_TIMING_HBP 64\r
+/** Horizontal pulse width in LCDDOTCLK cycles. */\r
+#define BOARD_LCD_TIMING_HPW 128\r
+\r
+/* =================== QT1070 device definition =================== */\r
+#define QT1070_PINS PINS_TWI1_IOS2;\r
+#define QT1070_ADDR ((Twi*)TWIHS1)\r
+#define QT1070_FREQ 400000\r
+#define QT1070_DESC {"QT1070", 0x00, 00}\r
+\r
+#endif /* #ifndef _BOARD_D2_H */\r
--- /dev/null
+/**\r
+ * \page sama5d2_xult_board_desc sama5d2-XULT - Board Description\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * This file is dedicated to describe the sama5d2-XULT board.\r
+ *\r
+ * \section Contents\r
+ *\r
+ * - sama5d2-XULT\r
+ * - For sama5d2-XULT information, see \subpage sama5d2_xult_board_info.\r
+ * - For operating frequency information, see \subpage sama5d2_xult_opfreq.\r
+ * - For using portable PIO definitions, see \subpage sama5d2_xult_piodef.\r
+ * - For on-board memories, see \subpage sama5d2_xult_mem.\r
+ * - Several USB definitions are included here, see \subpage sama5d2_xult_usb.\r
+ * - For External components, see \subpage sama5d2_xult_extcomp.\r
+ * - For Individual chip definition, see \subpage sama5d2_xult_chipdef.\r
+ *\r
+ * To get more software details and the full list of parameters related to the\r
+ * sama5d2-XULT board configuration, please have a look at the source file:\r
+ * \ref board.h\n\r
+ *\r
+ * \section Usage\r
+ *\r
+ * - The code for booting the board is provided by board_cstartup_xxx.c and\r
+ * board_lowlevel.c.\r
+ * - For using board PIOs, board characteristics (clock, etc.) and external\r
+ * components, see board.h.\r
+ * - For manipulating memories, see board_memories.h.\r
+ *\r
+ * This file can be used as a template and modified to fit a custom board, with\r
+ * specific PIOs usage or memory connections.\r
+ */\r
+\r
+/**\r
+ * \file board.h\r
+ *\r
+ * Definition of sama5d2-XULT\r
+ * characteristics, sama5d4-dependant PIOs and external components interfacing.\r
+ */\r
+\r
+#ifndef _BOARD_D2_H\r
+#define _BOARD_D2_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+\r
+#include "board_lowlevel.h"\r
+#include "board_memories.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * HW BOARD Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \page sama5d2_xult_board_info "sama5d2-XULT - Board informations"\r
+ * This page lists several definition related to the board description.\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_NAME\r
+ */\r
+\r
+/** Name of the board */\r
+#define BOARD_NAME "sama5d2-xult"\r
+\r
+/** Family definition */\r
+#if !defined sama5d2\r
+ #define sama5d2\r
+#endif\r
+\r
+/** Board definition */\r
+#define sama5d2xult\r
+\r
+/** Core definition */\r
+#define cortexa5\r
+\r
+#define BOARD_REV_A_XULT\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sama5d2_xult_opfreq "sama5d2-XULT - Operating frequencies"\r
+ * This page lists several definition related to the board operating frequency\r
+ * (when using the initialization done by board_lowlevel.c).\r
+ */\r
+\r
+/** Frequency of the board slow clock oscillator */\r
+#define BOARD_SLOW_CLOCK_EXT_OSC 32768\r
+\r
+/** Frequency of the board main clock oscillator */\r
+#define BOARD_MAIN_CLOCK_EXT_OSC 12000000\r
+\r
+/** /def Definition of DDRAM's type */\r
+#define BOARD_DDRAM_TYPE MT41K128M16\r
+\r
+/** \def Board DDR memory size in bytes */\r
+#define BOARD_DDR_MEMORY_SIZE 512*1024*1024\r
+\r
+/** \def Board PIT tick resolution */\r
+#define BOARD_TIMER_RESOLUTION 1000\r
+\r
+/* =================== PIN CONSOLE definition ================== */\r
+\r
+/** CONSOLE pin definition, Use only UART */\r
+#define PINS_CONSOLE PINS_UART1_IOS1\r
+#define CONSOLE_PER_ADD UART1\r
+#define CONSOLE_ID ID_UART1\r
+#define CONSOLE_BAUDRATE 57600\r
+#define CONSOLE_DRIVER DRV_UART\r
+\r
+/* =================== PIN LED definition ====================== */\r
+\r
+/* RGB LED index */\r
+#define LED_RED 0\r
+#define LED_GREEN 1\r
+#define LED_BLUE 2\r
+\r
+/* WHIS: ADDED CODE BELOW TO RE-MAP THE LED DEFINITIONS TO BOARD\r
+ CONNECTOR-ACCESSIBLE GPIOs, AS ON OUR EXAMPLE BOARD, VDD_LED WAS OFF\r
+ BY DEFAULT AND THE DEPENDENCIES INVOLVED IN COMPTROLLING THE\r
+ ACT8945a POWER/CHARGER CHIP DRIVER ARE ONEROUS FOR A SIMPLE DEMO.\r
+\r
+ These come out on pins 30, 32, 34 of J17. Pin 36 is GND. Configured\r
+ for push/pull operation with HI drive, connect LEDs between pins and\r
+ GND via circa 100R resistors (max drive current 18mA, voltage 1.8v)\r
+\r
+ Define LEDS_ON_J17 in project pre-processor options to use this. */\r
+\r
+#ifdef LEDS_ON_J17\r
+\r
+/** LED #0 pin definition. Pin 30 */\r
+#define PIN_LED_0 { PIO_GROUP_B, PIO_PB25, PIO_OUTPUT_0, PIO_DEFAULT | PIO_DRVSTR_HI }\r
+\r
+/** LED #1 pin definition Pin 32. */\r
+#define PIN_LED_1 { PIO_GROUP_C, PIO_PC8, PIO_OUTPUT_0, PIO_DEFAULT | PIO_DRVSTR_HI }\r
+\r
+/** LED #2 pin definition Pin 34 */\r
+#define PIN_LED_2 { PIO_GROUP_C, PIO_PC26, PIO_OUTPUT_0, PIO_DEFAULT | PIO_DRVSTR_HI }\r
+\r
+#else\r
+/** LED #0 pin definition (Red). */\r
+#define PIN_LED_0 { PIO_GROUP_B, PIO_PB6, PIO_OUTPUT_1, PIO_OPENDRAIN }\r
+\r
+/** LED #1 pin definition (Green). */\r
+#define PIN_LED_1 { PIO_GROUP_B, PIO_PB5, PIO_OUTPUT_1, PIO_OPENDRAIN }\r
+\r
+/** LED #2 pin definition (Blue). */\r
+#define PIN_LED_2 { PIO_GROUP_B, PIO_PB0, PIO_OUTPUT_1, PIO_OPENDRAIN }\r
+#endif\r
+\r
+/** List of all LEDs definitions. */\r
+#define PINS_LEDS { PIN_LED_0, PIN_LED_1, PIN_LED_2 }\r
+\r
+/* =================== LWM LED definition ====================== */\r
+\r
+/** LED #1 PWM Channel */\r
+#define PWM_LED_CH_0 2\r
+\r
+/** LED #2 PWM Channel */\r
+#define PWM_LED_CH_1 1\r
+\r
+/** LED #1 pin definition (Green). */\r
+#define PIN_PWM_LED_0 { PIO_GROUP_B, PIO_PB5C_PWMH2, PIO_PERIPH_C, PIO_PULLUP }\r
+\r
+/** LED #2 pin definition (Blue). */\r
+#define PIN_PWM_LED_1 { PIO_GROUP_B, PIO_PB0D_PWMH1, PIO_PERIPH_D, PIO_PULLUP }\r
+\r
+/** List of all PWM LED channels */\r
+#define PWM_LEDS_CH { PWM_LED_CH_0, PWM_LED_CH_1 }\r
+\r
+/** List of all LEDs definitions in PWM mode (red LED is not on a PWM pin) */\r
+#define PINS_PWM_LEDS { PIN_PWM_LED_0, PIN_PWM_LED_1 }\r
+\r
+/* =================== PIN PUSH BUTTON definition ============== */\r
+\r
+#define PIO_CFG_PB (PIO_PULLUP | PIO_DEBOUNCE)\r
+\r
+#define PIN_PUSHBUTTON_1 { PIO_GROUP_B, PIO_PB9, PIO_INPUT, PIO_CFG_PB }\r
+\r
+/** List of all push button definitions. */\r
+#define PINS_PUSHBUTTONS { PIN_PUSHBUTTON_1 }\r
+\r
+/** Push button index. */\r
+#define PUSHBUTTON_BP1 0\r
+\r
+/* ================== ACT8945A PMIC definition ====================== */\r
+\r
+#define ACT8945A_PINS PINS_FLEXCOM4_TWI_IOS3\r
+#define ACT8945A_ADDR TWI4\r
+#define ACT8945A_FREQ 400000\r
+#define ACT8945A_PIN_CHGLEV \\r
+ { PIO_GROUP_A, PIO_PA12, PIO_OUTPUT_0, PIO_PULLUP }\r
+#define ACT8945A_PIN_IRQ \\r
+ { PIO_GROUP_B, PIO_PB13, PIO_INPUT, PIO_PULLUP | PIO_IT_FALL_EDGE }\r
+#define ACT8945A_PIN_LBO \\r
+ { PIO_GROUP_C, PIO_PC8, PIO_INPUT, PIO_PULLUP | PIO_IT_FALL_EDGE }\r
+\r
+/* ================== PIN USB definition ======================= */\r
+\r
+/** USB VBus pin */\r
+#define PIN_USB_VBUS \\r
+ { PIO_GROUP_A, PIO_PA31, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_BOTH_EDGE }\r
+\r
+/** USB OverCurrent detection*/\r
+#define PIN_USB_OVCUR \\r
+ { PIO_GROUP_A, PIO_PA29, PIO_INPUT, PIO_DEFAULT }\r
+\r
+/** USB Power Enable A, Active high */\r
+#define PIN_USB_POWER_ENA \\r
+ { PIO_GROUP_B, PIO_PB9, PIO_OUTPUT_0, PIO_DEFAULT }\r
+\r
+/** USB Power Enable B, Active high */\r
+#define PIN_USB_POWER_ENB \\r
+ { PIO_GROUP_B, PIO_PB10, PIO_OUTPUT_0, PIO_DEFAULT }\r
+\r
+/* ================= PIN LCD IRQ definition ===================== */\r
+\r
+#define PIO_CFG_LCD_IRQ (PIO_PULLUP | PIO_IT_FALL_EDGE)\r
+\r
+#define PIN_QT1070_IRQ { PIO_GROUP_B, PIO_PB8, PIO_INPUT, PIO_CFG_LCD_IRQ }\r
+\r
+#define PIN_MXT_IRQ { PIO_GROUP_B, PIO_PB7, PIO_INPUT, PIO_PULLUP | PIO_IT_LOW_LEVEL }\r
+\r
+//#define PIN_MXT_IRQ { PIO_GROUP_B, PIO_PB7, PIO_INPUT, PIO_PULLUP }\r
+\r
+/* =================== PIN ISC definition ======================= */\r
+\r
+#define ISC_TWI_ADDR ((Twi*)TWIHS1)\r
+#define ISC_TWI_PINS PINS_TWI1_IOS2\r
+#define ISC_PINS PINS_ISC_IOS3\r
+#define ISC_PIN_RST { PIO_GROUP_B, PIO_PB11, PIO_OUTPUT_1, PIO_DEFAULT }\r
+#define ISC_PIN_PWD { PIO_GROUP_B, PIO_PB12, PIO_OUTPUT_1, PIO_DEFAULT }\r
+\r
+/* =================== PIN ClassD definition ==================== */\r
+\r
+#define BOARD_CLASSD_PINS { PIN_CLASSD_R0_IOS1, PIN_CLASSD_R1_IOS1,\\r
+ PIN_CLASSD_R2_IOS1, PIN_CLASSD_R3_IOS1 }\r
+#define BOARD_CLASSD_MODE CLASSD_OUTPUT_FULL_BRIDGE\r
+#define BOARD_CLASSD_MONO true\r
+#define BOARD_CLASSD_MONO_MODE CLASSD_MONO_MIXED\r
+\r
+/* =================== PIN SDMMC definition ===================== */\r
+\r
+#define SDMMC0_PINS { PINS_SDMMC0_8B_IOS1, PIN_SDMMC0_CK_IOS1,\\r
+ PIN_SDMMC0_CD_IOS1, PIN_SDMMC0_VDDSEL_IOS1,\\r
+ PIN_SDMMC0_RSTN_IOS1 }\r
+\r
+#define SDMMC1_PINS { PINS_SDMMC1_4B_IOS1, PIN_SDMMC1_CK_IOS1,\\r
+ PIN_SDMMC1_CD_IOS1 }\r
+\r
+/* =================== AT25 device definition =================== */\r
+\r
+#define AT25_PINS PINS_SPI0_NPCS0_IOS1\r
+#define AT25_ADDR SPI0\r
+#define AT25_CS 0\r
+#define AT25_ATTRS (SPI_MR_MODFDIS | SPI_MR_WDRBT | SPI_MR_MSTR)\r
+#define AT25_FREQ 40000 /* (value in KHz) */\r
+#define AT25_LOW_FREQ 20000 /* (value in KHz) */\r
+#define AT25_DLYBS 0\r
+#define AT25_DLYCT 0\r
+#define AT25_SPI_MODE (SPI_CSR_NCPHA | SPI_CSR_BITS_8_BIT)\r
+\r
+/* =================== AT24 device definition =================== */\r
+#define AT24_PINS PINS_TWI1_IOS2;\r
+#define AT24_ADDR ((Twi*)TWIHS1)\r
+#define AT24_FREQ 400000\r
+#define AT24_DESC {"AT24MAC402", 0xFF, 16}\r
+\r
+/* =================== QSPI serial flashdevice definition ======= */\r
+\r
+#define QSPIFLASH_PINS PINS_QSPI0_IOS3\r
+#define QSPIFLASH_ADDR QSPI0\r
+#define QSPIFLASH_BAUDRATE 50000000 /* 50 MHz */\r
+\r
+/* =================== CAN device definition ==================== */\r
+/* Both ports are wired to the J9 connector:\r
+ * CANTX0 = PC10 = J9:8\r
+ * CANRX0 = PC11 = J9:7\r
+ * CANTX1 = PC26 = J9:6\r
+ * CANRX1 = PC27 = J9:5 */\r
+\r
+#define CAN0_PINS PINS_CAN0_IOS1\r
+#define CAN1_PINS PINS_CAN1_IOS0\r
+\r
+/* =================== GMAC/PHY definition =================== */\r
+\r
+#define GMAC0_ADDR GMAC0\r
+#define GMAC0_PINS PINS_GMAC_RMII_IOS3\r
+#define GMAC0_PHY_ADDR 0\r
+#define GMAC0_PHY_IRQ_PIN PIN_GTSUCOM_IOS1\r
+#define GMAC0_PHY_RETRIES PHY_DEFAULT_RETRIES\r
+\r
+/* =================== ILI9488 device definition =================== */\r
+/* Connected on board A5D2, XPRO EXT2 connector */\r
+\r
+/* ILI9488 ID code */\r
+#define ILI9488_DEVICE_CODE 0x2810\r
+\r
+#define ILI9488_PINS PINS_SPI1_NPCS1_IOS3\r
+#define ILI9488_ADDR SPI1\r
+#define ILI9488_CS 1\r
+#define ILI9488_ATTRS (SPI_MR_MODFDIS | SPI_MR_MSTR) // | SPI_MR_WDRBT\r
+#define ILI9488_FREQ 40000 /* (value in KHz) */\r
+#define ILI9488_DLYBS 100\r
+#define ILI9488_DLYCT 100\r
+//#define ILI9488_SPI_MODE (SPI_CSR_NCPHA | SPI_CSR_BITS_9_BIT)\r
+#define ILI9488_SPI_MODE (SPI_CSR_CPOL | SPI_CSR_BITS_9_BIT)\r
+\r
+#define MXTX_RESET_PIN {\\r
+ {PIO_GROUP_D, PIO_PD28, PIO_OUTPUT_1, PIO_DEFAULT} \\r
+ }\r
+#define MXTX_BACKLIGHT_PIN {\\r
+ {PIO_GROUP_B, PIO_PB5C_PWMH2, PIO_PERIPH_C, PIO_DEFAULT} \\r
+ }\r
+\r
+/* ======================== LCD definition ======================== */\r
+\r
+/** PIO pins for LCD */\r
+#define BOARD_LCD_PINS PINS_LCD_IOS2\r
+\r
+/** Display width in pixels. */\r
+#define BOARD_LCD_WIDTH 480\r
+/** Display height in pixels. */\r
+#define BOARD_LCD_HEIGHT 272\r
+/** Frame rate in Hz. */\r
+#define BOARD_LCD_FRAMERATE 40\r
+\r
+/** Vertical front porch in number of lines. */\r
+#define BOARD_LCD_TIMING_VFP 22\r
+/** Vertical back porch in number of lines. */\r
+#define BOARD_LCD_TIMING_VBP 21\r
+/** Vertical pulse width in number of lines. */\r
+#define BOARD_LCD_TIMING_VPW 2\r
+/** Horizontal front porch in LCDDOTCLK cycles. */\r
+#define BOARD_LCD_TIMING_HFP 64\r
+/** Horizontal back porch in LCDDOTCLK cycles. */\r
+#define BOARD_LCD_TIMING_HBP 64\r
+/** Horizontal pulse width in LCDDOTCLK cycles. */\r
+#define BOARD_LCD_TIMING_HPW 128\r
+\r
+/* =================== QT1070 device definition =================== */\r
+#define QT1070_PINS PINS_TWI1_IOS2;\r
+#define QT1070_ADDR ((Twi*)TWIHS1)\r
+#define QT1070_FREQ 400000\r
+#define QT1070_DESC {"QT1070", 0x00, 00}\r
+\r
+/* =================== MXTxxx device definition =================== */\r
+#define MXT_PINS PINS_TWI1_IOS2;\r
+#define MXT_ADDR ((Twi*)TWIHS1)\r
+#define MXT_FREQ 400000\r
+#define MXT_DESC {"MXT", 0x00, 00}\r
+\r
+/**\r
+ * USB attributes configuration descriptor (bus or self powered,\r
+ * remote wakeup)\r
+ */\r
+#define BOARD_USB_BMATTRIBUTES \\r
+ USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP\r
+\r
+#endif /* #ifndef _BOARD_D2_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#include "board.h"\r
+\r
+int main(void)\r
+{\r
+ board_cfg_ddram();\r
+ asm("BKPT");\r
+ /* never reached */\r
+ return 0;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "compiler.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+struct peripheral_xdma {\r
+ uint32_t id; /**< Peripheral ID */\r
+ uint8_t iftx; /**< DMA Interface for TX */\r
+ uint8_t ifrx; /**< DMA Interface for RX */\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local constants\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static uint8_t _h64_peripherals[] = {\r
+ ID_ARM_PMU, /* 2: Performance Monitor Unit (PMU) (ARM_PMU) */\r
+ ID_XDMAC0, /* 6: DMA Controller 0 (XDMAC0) */\r
+ ID_XDMAC1, /* 7: DMA Controller 1 (XDMAC1) */\r
+ ID_AES, /* 9: Advanced Enion Standard (AES) */\r
+ ID_AESB, /* 10: AES bridge (AESB) */\r
+ ID_SHA, /* 12: SHA Signature (SHA) */\r
+ ID_MPDDRC, /* 13: MPDDR controller (MPDDRC) */\r
+ ID_MATRIX0, /* 15: H64MX, 64-bit AHB Matrix (MATRIX0) */\r
+ ID_SDMMC0, /* 31: Secure Digital Multimedia Card Controller 0 (SDMMC0) */\r
+ ID_SDMMC1, /* 32: Secure Digital Multimedia Card Controller 1 (SDMMC1) */\r
+ ID_LCDC, /* 45: LCD Controller (LCDC) */\r
+ ID_ISC, /* 46: Camera Interface (ISC) */\r
+ ID_QSPI0, /* 52: QSPI 0 (QSPI0) */\r
+ ID_QSPI1, /* 53: QSPI 1 (QSPI1) */\r
+ ID_L2CC, /* 63: L2 Cache Controller (L2CC) */\r
+};\r
+\r
+static const struct peripheral_xdma _xdmac_peripherals[] = {\r
+ { ID_TWIHS0, 0, 1 },\r
+ { ID_TWIHS1, 2, 3 },\r
+ { ID_QSPI0, 4, 5 },\r
+ { ID_SPI0, 6, 7 },\r
+ { ID_SPI1, 8, 9 },\r
+ { ID_PWM, 10, 0xff },\r
+ { ID_FLEXCOM0, 11, 12 },\r
+ { ID_FLEXCOM1, 13, 14 },\r
+ { ID_FLEXCOM2, 15, 16 },\r
+ { ID_FLEXCOM3, 17, 18 },\r
+ { ID_FLEXCOM4, 19, 20 },\r
+ { ID_SSC0, 21, 22 },\r
+ { ID_SSC1, 23, 24 },\r
+ { ID_ADC, 0xff, 25 },\r
+ { ID_AES, 26, 27 },\r
+ { ID_TDES, 28, 29 },\r
+ { ID_SHA, 30, 0xff },\r
+ { ID_I2SC0, 31, 32 },\r
+ { ID_I2SC1, 33, 34 },\r
+ { ID_UART0, 35, 36 },\r
+ { ID_UART1, 37, 38 },\r
+ { ID_UART2, 39, 40 },\r
+ { ID_UART3, 41, 42 },\r
+ { ID_UART4, 43, 44 },\r
+ { ID_TC0, 0xff, 45 },\r
+ { ID_TC1, 0xff, 46 },\r
+ { ID_CLASSD, 47, 0xff },\r
+ { ID_QSPI0, 48, 49 },\r
+ { ID_PDMIC, 0xff, 50 },\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Private functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+static const struct peripheral_xdma *get_peripheral_xdma(uint32_t id, Xdmac *xdmac)\r
+{\r
+ unsigned int i;\r
+\r
+ if (xdmac != XDMAC0 && xdmac != XDMAC1) {\r
+ return NULL;\r
+ }\r
+\r
+ for (i = 0; i < ARRAY_SIZE(_xdmac_peripherals); i++) {\r
+ if (_xdmac_peripherals[i].id == id) {\r
+ return &_xdmac_peripherals[i];\r
+ }\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+Flexcom* get_flexcom_addr_from_id(const uint32_t id)\r
+{\r
+ if (id == ID_FLEXCOM0) return FLEXCOM0; /**< \brief FLEXCOM 0 (FLEXCOM0) */\r
+#ifdef FLEXCOM1\r
+ else if (id == ID_FLEXCOM1) return FLEXCOM1; /**< \brief FLEXCOM 1 (FLEXCOM1) */\r
+#endif\r
+#ifdef FLEXCOM2\r
+ else if (id == ID_FLEXCOM2) return FLEXCOM2; /**< \brief FLEXCOM 2 (FLEXCOM2) */\r
+#endif\r
+#ifdef FLEXCOM3\r
+ else if (id == ID_FLEXCOM3) return FLEXCOM3; /**< \brief FLEXCOM 3 (FLEXCOM3) */\r
+#endif\r
+#ifdef FLEXCOM4\r
+ else if (id == ID_FLEXCOM4) return FLEXCOM4; /**< \brief FLEXCOM 4 (FLEXCOM4) */\r
+#endif\r
+ else return (void*)0;\r
+}\r
+\r
+uint32_t get_twi_id_from_addr(const Twi* addr)\r
+{\r
+ if (addr == (void*)TWI0) return ID_FLEXCOM0; /**< \brief FLEXCOM 0 (FLEXCOM0) */\r
+#ifdef TWI1\r
+ else if (addr == (void*)TWI1) return ID_FLEXCOM1; /**< \brief FLEXCOM 1 (FLEXCOM1) */\r
+#endif\r
+#ifdef TWI2\r
+ else if (addr == (void*)TWI2) return ID_FLEXCOM2; /**< \brief FLEXCOM 2 (FLEXCOM2) */\r
+#endif\r
+#ifdef TWI3\r
+ else if (addr == (void*)TWI3) return ID_FLEXCOM3; /**< \brief FLEXCOM 3 (FLEXCOM3) */\r
+#endif\r
+#ifdef TWI4\r
+ else if (addr == (void*)TWI4) return ID_FLEXCOM4; /**< \brief FLEXCOM 4 (FLEXCOM4) */\r
+#endif\r
+#ifdef TWIHS0\r
+ else if (addr == (void*)TWIHS0) return ID_TWIHS0; /**< \brief TWIHS0 */\r
+#endif\r
+#ifdef TWIHS0\r
+ else if (addr == (void*)TWIHS1) return ID_TWIHS1; /**< \brief TWIHS1 */\r
+#endif\r
+ else return ID_PERIPH_COUNT;\r
+}\r
+\r
+Twi* get_twi_addr_from_id(const uint32_t id)\r
+{\r
+ if (id == ID_FLEXCOM0) return TWI0; /**< \brief FLEXCOM 0 (FLEXCOM0) */\r
+#ifdef TWI1\r
+ else if (id == ID_FLEXCOM1) return TWI1; /**< \brief FLEXCOM 1 (FLEXCOM1) */\r
+#endif\r
+#ifdef TWI2\r
+ else if (id == ID_FLEXCOM2) return TWI2; /**< \brief FLEXCOM 2 (FLEXCOM2) */\r
+#endif\r
+#ifdef TWI3\r
+ else if (id == ID_FLEXCOM3) return TWI3; /**< \brief FLEXCOM 3 (FLEXCOM3) */\r
+#endif\r
+#ifdef TWI4\r
+ else if (id == ID_FLEXCOM4) return TWI4; /**< \brief FLEXCOM 4 (FLEXCOM4) */\r
+#endif\r
+#ifdef TWIHS0\r
+ else if (id == ID_TWIHS0) return (Twi*)TWIHS0; /**< \brief TWIHS0 */\r
+#endif\r
+#ifdef TWIHS1\r
+ else if (id == ID_TWIHS1) return (Twi*)TWIHS1; /**< \brief TWIHS1 */\r
+#endif\r
+ else return (void*)0;\r
+}\r
+\r
+uint32_t get_spi_id_from_addr(const Spi* addr)\r
+{\r
+ if (addr == (void*)SPI0) return ID_SPI0;\r
+#ifdef SPI1\r
+ else if (addr == (void*)SPI1) return ID_SPI1;\r
+#endif\r
+#ifdef FCOMSPI0\r
+ else if (addr == (void*)FCOMSPI0) return ID_FCOMSPI0;\r
+#endif\r
+#ifdef FCOMSPI1\r
+ else if (addr == (void*)FCOMSPI1) return ID_FCOMSPI1;\r
+#endif\r
+#ifdef FCOMSPI2\r
+ else if (addr == (void*)FCOMSPI2) return ID_FCOMSPI2;\r
+#endif\r
+#ifdef FCOMSPI3\r
+ else if (addr == (void*)FCOMSPI3) return ID_FCOMSPI3;\r
+#endif\r
+#ifdef FCOMSPI4\r
+ else if (addr == (void*)FCOMSPI4) return ID_FCOMSPI4;\r
+#endif\r
+ else return ID_PERIPH_COUNT;\r
+}\r
+\r
+Spi* get_spi_addr_from_id(const uint32_t id)\r
+{\r
+ if (id == ID_SPI0) return SPI0; /**< \brief SPI 0 (SPI0) */\r
+#ifdef SPI1\r
+ else if (id == ID_SPI1) return SPI1; /**< \brief SPI 1 (SPI1) */\r
+#endif\r
+#ifdef FCOMSPI0\r
+ else if (id == ID_FCOMSPI0) return FCOMSPI0; /**< \brief FLEXCOM SPI 0 (FCOMSPI0) */\r
+#endif\r
+#ifdef FCOMSPI1\r
+ else if (id == ID_FCOMSPI1) return FCOMSPI1; /**< \brief FLEXCOM SPI 1 (FCOMSPI1) */\r
+#endif\r
+#ifdef FCOMSPI2\r
+ else if (id == ID_FCOMSPI2) return FCOMSPI2; /**< \brief FLEXCOM SPI 1 (FCOMSPI1) */\r
+#endif\r
+#ifdef FCOMSPI3\r
+ else if (id == ID_FCOMSPI3) return FCOMSPI3; /**< \brief FLEXCOM SPI 3 (FCOMSPI3) */\r
+#endif\r
+#ifdef FCOMSPI4\r
+ else if (id == ID_FCOMSPI4) return FCOMSPI4; /**< \brief FLEXCOM SPI 4 (FCOMSPI4) */\r
+#endif\r
+ else return (void*)0;\r
+}\r
+\r
+uint32_t get_uart_id_from_addr(const Uart* addr)\r
+{\r
+ if (addr == (void*)UART0) return ID_UART0;\r
+#ifdef UART1\r
+ else if (addr == (void*)UART1) return ID_UART1;\r
+#endif\r
+#ifdef UART2\r
+ else if (addr == (void*)UART2) return ID_UART2;\r
+#endif\r
+#ifdef UART3\r
+ else if (addr == (void*)UART3) return ID_UART3;\r
+#endif\r
+#ifdef UART4\r
+ else if (addr == (void*)UART4) return ID_UART4;\r
+#endif\r
+ else return ID_PERIPH_COUNT;\r
+}\r
+\r
+uint32_t get_usart_id_from_addr(const Usart* addr)\r
+{\r
+ if (addr == (void*)USART0) return ID_USART0;\r
+#ifdef USART1\r
+ else if (addr == (void*)USART1) return ID_USART1;\r
+#endif\r
+#ifdef USART2\r
+ else if (addr == (void*)USART2) return ID_USART2;\r
+#endif\r
+#ifdef USART3\r
+ else if (addr == (void*)USART3) return ID_USART3;\r
+#endif\r
+#ifdef USART4\r
+ else if (addr == (void*)USART4) return ID_USART4;\r
+#endif\r
+ else return ID_PERIPH_COUNT;\r
+}\r
+\r
+uint32_t get_tc_id_from_addr(const Tc* addr)\r
+{\r
+ if (addr == TC0) return ID_TC0;\r
+#ifdef TC1\r
+ else if (addr == TC1) return ID_TC1;\r
+#endif\r
+ else return ID_PERIPH_COUNT;\r
+}\r
+\r
+Tc* get_tc_addr_from_id(const uint32_t id)\r
+{\r
+ if (id == ID_TC0) return TC0; /**< \brief Timer/Counter 0 (TC0) */\r
+#ifdef TC1\r
+ else if (id == ID_TC1) return TC1; /**< \brief Timer/Counter 1 (TC1) */\r
+#endif\r
+ else return (void*)0;\r
+}\r
+\r
+uint32_t get_qspi_id_from_addr(const Qspi* addr)\r
+{\r
+ if (addr == (void*)QSPI0) return ID_QSPI0;\r
+ else if (addr == (void*)QSPI1) return ID_QSPI1;\r
+ else return ID_PERIPH_COUNT;\r
+}\r
+\r
+void *get_qspi_mem_from_addr(const Qspi* addr)\r
+{\r
+ if (addr == (void*)QSPI0) return (void*)QSPIMEM0_ADDR;\r
+ else if (addr == (void*)QSPI1) return (void*)QSPIMEM1_ADDR;\r
+ else return NULL;\r
+}\r
+\r
+uint32_t get_gmac_id_from_addr(const Gmac* addr)\r
+{\r
+ if (addr == (void*)GMAC0) return ID_GMAC0;\r
+ else return ID_PERIPH_COUNT;\r
+}\r
+\r
+Matrix* get_peripheral_matrix(uint32_t id)\r
+{\r
+ unsigned int i;\r
+\r
+ for (i = 0; i < ARRAY_SIZE(_h64_peripherals); i++)\r
+ if (_h64_peripherals[i] == id)\r
+ return MATRIX0; // AHB 64-bit matrix\r
+ return MATRIX1; // AHB 32-bit matrix\r
+}\r
+\r
+uint32_t get_peripheral_clock_divider(uint32_t id)\r
+{\r
+ Matrix* matrix = get_peripheral_matrix(id);\r
+\r
+ if (matrix == MATRIX1) {\r
+ if (PMC->PMC_MCKR & PMC_MCKR_H32MXDIV_H32MXDIV2)\r
+ return 2;\r
+ else\r
+ return 1;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+uint8_t get_peripheral_xdma_channel(uint32_t id, Xdmac *xdmac, bool transmit)\r
+{\r
+ const struct peripheral_xdma *periph_xdma = get_peripheral_xdma(id, xdmac);\r
+ if (periph_xdma) {\r
+ return transmit ? periph_xdma->iftx : periph_xdma->ifrx;\r
+ } else {\r
+ return 0xff;\r
+ }\r
+}\r
+\r
+bool is_peripheral_on_xdma_controller(uint32_t id, Xdmac *xdmac)\r
+{\r
+ return get_peripheral_xdma(id, xdmac) != NULL;\r
+}\r
+\r
+int32_t get_peripheral_fifo_depth(void* addr)\r
+{\r
+ uint32_t size = (uint32_t)-1;\r
+ uint32_t tmp = (uint32_t)addr;\r
+ switch (tmp) {\r
+ case (uint32_t)USART0:\r
+#ifdef USART1\r
+ case (uint32_t)USART1:\r
+#endif\r
+#ifdef USART2\r
+ case (uint32_t)USART2:\r
+#endif\r
+ case (uint32_t)USART3:\r
+#ifdef USART3\r
+ case (uint32_t)USART4:\r
+#endif\r
+ size = FLEXCOM_USART_FIFO_DEPTH;\r
+ break;\r
+\r
+ case (uint32_t)FCOMSPI0:\r
+#ifdef FCOMSPI1\r
+ case (uint32_t)FCOMSPI1:\r
+#endif\r
+#ifdef FCOMSPI2\r
+ case (uint32_t)FCOMSPI2:\r
+#endif\r
+#ifdef FCOMSPI3\r
+ case (uint32_t)FCOMSPI3:\r
+#endif\r
+#ifdef FCOMSPI4\r
+ case (uint32_t)FCOMSPI4:\r
+#endif\r
+ size = FLEXCOM_SPI_FIFO_DEPTH;\r
+ break;\r
+ case (uint32_t)SPI0:\r
+#ifdef SPI1\r
+ case (uint32_t)SPI1:\r
+#endif\r
+ size = SPI_FIFO_DEPTH;\r
+ break;\r
+ case (uint32_t)TWI0:\r
+#ifdef TWI1\r
+ case (uint32_t)TWI1:\r
+#endif\r
+#ifdef TWI2\r
+ case (uint32_t)TWI2:\r
+#endif\r
+#ifdef TWI3\r
+ case (uint32_t)TWI3:\r
+#endif\r
+#ifdef TWI4\r
+ case (uint32_t)TWI4:\r
+#endif\r
+#ifdef TWIHS0\r
+ case (uint32_t)TWIHS0:\r
+#endif\r
+#ifdef TWIHS1\r
+ case (uint32_t)TWIHS1:\r
+#endif\r
+ size = TWI_FIFO_DEPTH;\r
+ break;\r
+ default:\r
+ size = (uint32_t)-1;\r
+ }\r
+ return size;\r
+}\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+/* */\r
+\r
+#ifndef _CHIP_H_\r
+#define _CHIP_H_\r
+\r
+#include <stdint.h>\r
+#include <stdbool.h>\r
+\r
+#ifdef __cplusplus\r
+#define __I volatile /**< Defines 'read-only' permissions */\r
+#else\r
+#define __I volatile const /**< Defines 'read-only' permissions */\r
+#endif\r
+#define __O volatile /**< Defines 'write-only' permissions */\r
+#define __IO volatile /**< Defines 'read/write' permissions */\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAMA5D2x */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D2x_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SAIC_FIQ ( 0) /**< \brief FIQ Interrupt ID (SAIC_FIQ) */\r
+#define ID_ARM_PMU ( 2) /**< \brief Performance Monitor Unit (PMU) (ARM_PMU) */\r
+#define ID_PIT ( 3) /**< \brief Periodic Interval Timer Interrupt (PIT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog timer Interrupt (WDT) */\r
+#define ID_GMAC0 ( 5) /**< \brief Ethernet MAC (GMAC0) */\r
+#define ID_XDMAC0 ( 6) /**< \brief DMA Controller 0 (XDMAC0) */\r
+#define ID_XDMAC1 ( 7) /**< \brief DMA Controller 1 (XDMAC1) */\r
+#define ID_ICM ( 8) /**< \brief Integritry Check Monitor (ICM) */\r
+#define ID_AES ( 9) /**< \brief Advanced Enion Standard (AES) */\r
+#define ID_AESB (10) /**< \brief AES bridge (AESB) */\r
+#define ID_TDES (11) /**< \brief Triple Data Enion Standard (TDES) */\r
+#define ID_SHA (12) /**< \brief SHA Signature (SHA) */\r
+#define ID_MPDDRC (13) /**< \brief MPDDR controller (MPDDRC) */\r
+#define ID_MATRIX1 (14) /**< \brief H32MX, 32-bit AHB Matrix (MATRIX1) */\r
+#define ID_MATRIX0 (15) /**< \brief H64MX, 64-bit AHB Matrix (MATRIX0) */\r
+#define ID_HSMC (17) /**< \brief Multi-bit ECC Interrupt (HSMC) */\r
+#define ID_PIOA (18) /**< \brief Parallel I/O Controller (PIOA) */\r
+#define ID_FLEXCOM0 (19) /**< \brief FLEXCOM 0 (FLEXCOM0) */\r
+#define ID_USART0 (19) /**< \brief USART (USART0) from FLEXCOM0 */\r
+#define ID_FCOMSPI0 (19) /**< \brief Serial Peripheral Interface (SPI0) from FLEXCOM0 */\r
+#define ID_TWI0 (19) /**< \brief Two-Wire Interface (TWI0) from FLEXCOM0 */\r
+#define ID_FLEXCOM1 (20) /**< \brief FLEXCOM 1 (FLEXCOM1) */\r
+#define ID_USART1 (20) /**< \brief USART (USART1) from FLEXCOM1 */\r
+#define ID_FCOMSPI1 (20) /**< \brief Serial Peripheral Interface (SPI1) from FLEXCOM1 */\r
+#define ID_TWI1 (20) /**< \brief Two-Wire Interface (TWI1) from FLEXCOM1 */\r
+#define ID_FLEXCOM2 (21) /**< \brief FLEXCOM 1 (FLEXCOM1) */\r
+#define ID_USART2 (21) /**< \brief USART (USART1) from FLEXCOM1 */\r
+#define ID_FCOMSPI2 (21) /**< \brief Serial Peripheral Interface (SPI1) from FLEXCOM1 */\r
+#define ID_TWI2 (21) /**< \brief Two-Wire Interface (TWI1) from FLEXCOM1 */\r
+#define ID_FLEXCOM3 (22) /**< \brief FLEXCOM 3 (FLEXCOM3) */\r
+#define ID_USART3 (22) /**< \brief USART (USART3) from FLEXCOM3 */\r
+#define ID_FCOMSPI3 (22) /**< \brief Serial Peripheral Interface (SPI3) from FLEXCOM3 */\r
+#define ID_TWI3 (22) /**< \brief Two-Wire Interface (TWI3) from FLEXCOM3 */\r
+#define ID_FLEXCOM4 (23) /**< \brief FLEXCOM 4 (FLEXCOM4) */\r
+#define ID_USART4 (23) /**< \brief USART (USART4) from FLEXCOM4 */\r
+#define ID_FCOMSPI4 (23) /**< \brief Serial Peripheral Interface (SPI4) from FLEXCOM4 */\r
+#define ID_TWI4 (23) /**< \brief Two-Wire Interface (TWI4) from FLEXCOM4 */\r
+#define ID_UART0 (24) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 (25) /**< \brief UART 1 (UART1) */\r
+#define ID_UART2 (26) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (27) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (28) /**< \brief UART 4 (UART4) */\r
+#define ID_TWIHS0 (29) /**< \brief Two-Wire Interface 0 (TWIHS0) */\r
+#define ID_TWIHS1 (30) /**< \brief Two-Wire Interface 1 (TWIHS1) */\r
+#define ID_SDMMC0 (31) /**< \brief Secure Digital Multimedia Card Controller 0 (SDMMC0) */\r
+#define ID_SDMMC1 (32) /**< \brief Secure Digital Multimedia Card Controller 1 (SDMMC1) */\r
+#define ID_SPI0 (33) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SPI1 (34) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_TC0 (35) /**< \brief Timer Counter 0 (ch. 0, 1, 2) (TC0) */\r
+#define ID_TC1 (36) /**< \brief Timer Counter 1 (ch. 3, 4, 5) (TC1) */\r
+#define ID_PWM (38) /**< \brief Pulse Width Modulation Controller0 (ch. 0, 1, 2, 3) (PWM) */\r
+#define ID_ADC (40) /**< \brief Touch Screen ADC Controller (ADC) */\r
+#define ID_UHPHS (41) /**< \brief USB Host High Speed (UHPHS) */\r
+#define ID_UDPHS (42) /**< \brief USB Device High Speed (UDPHS) */\r
+#define ID_SSC0 (43) /**< \brief Synchronous Serial Controller 0 (SSC0) */\r
+#define ID_SSC1 (44) /**< \brief Synchronous Serial Controller 1 (SSC1) */\r
+#define ID_LCDC (45) /**< \brief LCD Controller (LCDC) */\r
+#define ID_ISC (46) /**< \brief Camera Interface (ISC) */\r
+#define ID_TRNG (47) /**< \brief True Random Number Generator (TRNG) */\r
+#define ID_PDMIC (48) /**< \brief Pulse Density Modulation Interface Controller (PDMIC) */\r
+#define ID_AIC_IRQ (49) /**< \brief IRQ Interrupt ID (AIC_IRQ) */\r
+#define ID_SFC (50) /**< \brief Fuse Controller (SFC) */\r
+#define ID_SECURAM (51) /**< \brief Secured RAM (SECURAM) */\r
+#define ID_QSPI0 (52) /**< \brief QSPI 0 (QSPI0) */\r
+#define ID_QSPI1 (53) /**< \brief QSPI 1 (QSPI1) */\r
+#define ID_I2SC0 (54) /**< \brief Inter-IC Sound Controller 0 (I2SC0) */\r
+#define ID_I2SC1 (55) /**< \brief Inter-IC Sound Controller 1 (I2SC1) */\r
+#define ID_CAN0_INT0 (56) /**< \brief MCAN 0 Interrupt0 (CAN0_INT0) */\r
+#define ID_CAN1_INT0 (57) /**< \brief MCAN 1 Interrupt0 (CAN1_INT0) */\r
+#define ID_CLASSD (59) /**< \brief Audio Class D amplifier (CLASSD) */\r
+#define ID_SFR (60) /**< \brief Special Function Register (SFR) */\r
+#define ID_SAIC (61) /**< \brief Secured Advanced Interrupt Controller (SAIC) */\r
+#define ID_AIC (62) /**< \brief Advanced Interrupt Controller (AIC) */\r
+#define ID_L2CC (63) /**< \brief L2 Cache Controller (L2CC) */\r
+#define ID_CAN0_INT1 (64) /**< \brief MCAN 0 Interrupt1 (CAN0_INT1) */\r
+#define ID_CAN1_INT1 (65) /**< \brief MCAN 1 Interrupt1 (CAN1_INT1) */\r
+#define ID_GMAC0_Q1 (66) /**< \brief GMAC Queue 1 Interrupt (GMAC0_Q1) */\r
+#define ID_GMAC0_Q2 (67) /**< \brief GMAC Queue 2 Interrupt (GMAC0_Q2) */\r
+#define ID_PIOB (68) /**< \brief (PIOB) */\r
+#define ID_PIOC (69) /**< \brief (PIOC) */\r
+#define ID_PIOD (70) /**< \brief (PIOD) */\r
+#define ID_SDMMC0_TIMER (71) /**< \brief (SDMMC0_TIMER) */\r
+#define ID_SDMMC1_TIMER (72) /**< \brief (SDMMC1_TIMER) */\r
+#define ID_SYSC (74) /**< \brief System Controller Interrupt, RTC, RSTC, PMC (SYSC) */\r
+#define ID_ACC (75) /**< \brief Analog Comparator (ACC) */\r
+#define ID_RXLP (76) /**< \brief Uart Low Power (RXLP) */\r
+#define ID_CHIPID (78) /**< \brief Chip ID (CHIPID) */\r
+\r
+#define ID_PERIPH_COUNT (79) /**< \brief Number of peripheral IDs */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* SLAVE MATRIX ID DEFINITIONS FOR SAMA5D2x */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D2x_matrix Matrix Ids Definitions */\r
+/*@{*/\r
+\r
+#define H64MX_SLAVE_BRIDGE_H32MX 0 /**< Bridge from H64MX to H32MX */\r
+#define H64MX_SLAVE_APB 1 /**< H64MX APB - User interfaces */\r
+#define H64MX_SLAVE_SDMMC 1 /**< SDMMC0 - SDMMC1 */\r
+#define H64MX_SLAVE_DDR_PORT0 2 /**< DDR Port 0 */\r
+#define H64MX_SLAVE_DDR_PORT1 3 /**< DDR Port 1 */\r
+#define H64MX_SLAVE_DDR_PORT2 4 /**< DDR Port 2 */\r
+#define H64MX_SLAVE_DDR_PORT3 5 /**< DDR Port 3 */\r
+#define H64MX_SLAVE_DDR_PORT4 6 /**< DDR Port 4 */\r
+#define H64MX_SLAVE_DDR_PORT5 7 /**< DDR Port 5 */\r
+#define H64MX_SLAVE_DDR_PORT6 8 /**< DDR Port 6 */\r
+#define H64MX_SLAVE_DDR_PORT7 9 /**< DDR Port 7 */\r
+#define H64MX_SLAVE_SRAM 10 /**< Internal SRAM 128K */\r
+#define H64MX_SLAVE_L2C_SRAM 11 /**< Internal SRAM 128K (L2) */\r
+#define H64MX_SLAVE_QSPI0 12 /**< QSPI0 */\r
+#define H64MX_SLAVE_QSPI1 13 /**< QSPI1 */\r
+#define H64MX_SLAVE_AESB 14 /**< AESB */\r
+\r
+#define H32MX_SLAVE_BRIDGE_H64MX 0 /**< Bridge from H32MX to H64MX */\r
+#define H32MX_SLAVE_APB0 1 /**< H32MX APB0 - User interfaces */\r
+#define H32MX_SLAVE_APB1 2 /**< H32MX APB1 - User interfaces */\r
+#define H32MX_SLAVE_EBI 3 /**< External Bus Interface CS0..CS3 */\r
+#define H32MX_SLAVE_NFC_CMD 3 /**< NFC Command Register */\r
+#define H32MX_SLAVE_NFC_SRAM 4 /**< NFC SRAM */\r
+#define H32MX_SLAVE_USB 5 /**< USB */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PMECC DEFINITIONS FOR SAMA5D2x */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D2x_pmecc PMECC Definitions */\r
+/*@{*/\r
+\r
+/** defines the maximum value of the error correcting capability */\r
+#define PMECC_NB_ERROR_MAX (25)\r
+\r
+/** Address of Galois Field Table 512 mapping in ROM. */\r
+#define GALOIS_TABLE_512_ROM_MAPPING (0x40000)\r
+\r
+/** Address of Galois Field Table 1024 mapping in ROM. */\r
+#define GALOIS_TABLE_1024_ROM_MAPPING (0x48000)\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* INCLUDE FOR SAMA5D2x */\r
+/* ************************************************************************** */\r
+\r
+#if defined(CONFIG_SOC_SAMA5D21)\r
+ #include "sama5d21.h"\r
+#elif defined(CONFIG_SOC_SAMA5D22)\r
+ #include "sama5d22.h"\r
+#elif defined(CONFIG_SOC_SAMA5D23)\r
+ #include "sama5d23.h"\r
+#elif defined(CONFIG_SOC_SAMA5D24)\r
+ #include "sama5d24.h"\r
+#elif defined(CONFIG_SOC_SAMA5D26)\r
+ #include "sama5d26.h"\r
+#elif defined(CONFIG_SOC_SAMA5D27)\r
+ #include "sama5d27.h"\r
+#elif defined(CONFIG_SOC_SAMA5D28)\r
+ #include "sama5d28.h"\r
+#else\r
+ #error Library does not support the specified device.\r
+#endif\r
+\r
+#include "chip_pins.h"\r
+\r
+/** Size of Cortex-A5 L1 cache line */\r
+#define L1_CACHE_WORDS (8u)\r
+#define L1_CACHE_BYTES (32u)\r
+\r
+/** FLEXCOM USART FIFO depth */\r
+#define FLEXCOM_USART_FIFO_DEPTH (32u)\r
+\r
+/** FLEXCOM SPI FIFO depth */\r
+#define FLEXCOM_SPI_FIFO_DEPTH (32u)\r
+\r
+/** SPI FIFO depth */\r
+#define SPI_FIFO_DEPTH (16u)\r
+\r
+/** TWI FIFO depth */\r
+#define TWI_FIFO_DEPTH (16u)\r
+\r
+/** Frequency of the on-chip slow clock oscillator */\r
+#define SLOW_CLOCK_INT_OSC 32000\r
+\r
+/** Frequency of the on-chip main clock oscillator */\r
+#define MAIN_CLOCK_INT_OSC 12000000\r
+\r
+/** AIC redirection unlock key */\r
+#define AICREDIR_KEY 0x5B6C0E26u\r
+\r
+/** Indicates chip has an UDP High Speed. */\r
+#define CHIP_USB_UDPHS\r
+\r
+/** Indicates chip has an internal pull-up. */\r
+#define CHIP_USB_PULLUP_INTERNAL\r
+\r
+/** Number of USB endpoints */\r
+#define CHIP_USB_ENDPOINTS 16\r
+\r
+/** Endpoints max paxcket size */\r
+#define CHIP_USB_ENDPOINT_MAXPACKETSIZE(ep) \\r
+ ((ep == 0) ? 64 : 1024)\r
+\r
+/** Endpoints Number of Bank */\r
+#define CHIP_USB_ENDPOINT_BANKS(ep) \\r
+ ((ep == 0) ? 1 : ((ep == 1) ? 3 : ((ep == 2) ? 3 : 2)))\r
+\r
+/** Endpoints DMA support */\r
+#define CHIP_USB_ENDPOINT_HAS_DMA(ep) \\r
+ ((ep == 0) ? false : ((ep < 7) ? true : false ))\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \brief retrieve Flexcom base address from its ID\r
+ * \return Flexcom base address on success, 0 otherwise\r
+ */\r
+extern Flexcom* get_flexcom_addr_from_id(const uint32_t id);\r
+\r
+/**\r
+ * \brief retrieve TWI ID from its base address\r
+ * \return TWI ID on success, ID_PERIPH_COUNT otherwise\r
+ */\r
+extern uint32_t get_twi_id_from_addr(const Twi* addr);\r
+\r
+/**\r
+ * \brief retrieve TWI base address from its ID\r
+ * \return TWI base address on success, 0 otherwise\r
+ */\r
+extern Twi* get_twi_addr_from_id(const uint32_t id);\r
+\r
+/**\r
+ *\r
+ */\r
+extern uint32_t get_spi_id_from_addr(const Spi* addr);\r
+\r
+extern Spi* get_spi_addr_from_id(const uint32_t id);\r
+\r
+extern uint32_t get_uart_id_from_addr(const Uart* addr);\r
+\r
+extern uint32_t get_usart_id_from_addr(const Usart* addr);\r
+\r
+/**\r
+ * \brief retrieve Timer/Counter ID from its base address\r
+ * \return TC ID on success, ID_PERIPH_COUNT otherwise\r
+ */\r
+extern uint32_t get_tc_id_from_addr(const Tc* addr);\r
+\r
+/**\r
+ * \brief retrieve Timer/Counter base address from its ID\r
+ * \return TC base address on success, 0 otherwise\r
+ */\r
+extern Tc* get_tc_addr_from_id(const uint32_t id);\r
+\r
+/**\r
+ * \brief retrieve QSPI ID from its base address\r
+ * \return QSPI ID on success, ID_PERIPH_COUNT otherwise\r
+ */\r
+uint32_t get_qspi_id_from_addr(const Qspi* addr);\r
+\r
+/**\r
+ * \brief retrieve QSPI memory start from its base address\r
+ * \return QSPI memory start on success, NULL otherwise\r
+ */\r
+void *get_qspi_mem_from_addr(const Qspi* addr);\r
+\r
+/**\r
+ * \brief retrieve GMAC ID from its base address\r
+ * \return GMAC ID on success, ID_PERIPH_COUNT otherwise\r
+ */\r
+uint32_t get_gmac_id_from_addr(const Gmac* addr);\r
+\r
+/** \brief Returns the matrix on which the given peripheral is connected\r
+ *\r
+ * \param id the Peripheral ID\r
+ * \return a pointer to the Matrix instance\r
+ */\r
+extern Matrix* get_peripheral_matrix(uint32_t id);\r
+\r
+/** \brief Returns the clock divider for the given peripheral\r
+ *\r
+ * \param id the Peripheral ID\r
+ * \return the clock divider for the peripheral\r
+ */\r
+extern uint32_t get_peripheral_clock_divider(uint32_t id);\r
+\r
+/** \brief Returns the XDMAC interface number for a given peripheral\r
+ *\r
+ * \param id the Peripheral ID\r
+ * \param xdmac the XDMAC controller instance\r
+ * \param transmit a boolean, true for transmit, false for receive\r
+ * \return the XDMAC interface number or 0xff if none\r
+ */\r
+extern uint8_t get_peripheral_xdma_channel(uint32_t id, Xdmac *xdmac,\r
+ bool transmit);\r
+\r
+/** \brief Checks if a peripheral is usable with a XDMAC controller\r
+ *\r
+ * \param id the Peripheral ID\r
+ * \param xdmac the XDMAC controller instance\r
+ * \return true if the peripheral is usable on the given XDMAC controller,\r
+ * false otherwise\r
+ */\r
+extern bool is_peripheral_on_xdma_controller(uint32_t id, Xdmac *xdmac);\r
+\r
+/** \brief Retrive peripheral FIFO size from its base address\r
+ *\r
+ * \param addr the Peripheral base addr\r
+ * \return Size in number of data of the peripherals FIFO if\r
+ * available, negative value otherwise.\r
+ */\r
+extern int32_t get_peripheral_fifo_depth(void* addr);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _CHIP_H_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+/* */\r
+\r
+#ifndef _CHIP_PINS_H_\r
+#define _CHIP_PINS_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * PIOs Define\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * This pages lists all the pio definitions contained in chip.h.\r
+ * The constants are named using the following convention: PIN_* for a constant\r
+ * which defines a single Pin instance (but may include several PIOs sharing the\r
+ * same controller), and PINS_* for a list of Pin instances.\r
+ */\r
+\r
+/* ========== Pio PIN definition for ADC peripheral ========== */\r
+\r
+#define PIN_AD0 { PIO_GROUP_D, PIO_PD19X1_AD0, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD1 { PIO_GROUP_D, PIO_PD20X1_AD1, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD2 { PIO_GROUP_D, PIO_PD21X1_AD2, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD3 { PIO_GROUP_D, PIO_PD22X1_AD3, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD4 { PIO_GROUP_D, PIO_PD23X1_AD4, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD5 { PIO_GROUP_D, PIO_PD24X1_AD5, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD6 { PIO_GROUP_D, PIO_PD25X1_AD6, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD7 { PIO_GROUP_D, PIO_PD26X1_AD7, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD8 { PIO_GROUP_D, PIO_PD27X1_AD8, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD9 { PIO_GROUP_D, PIO_PD28X1_AD9, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD10 { PIO_GROUP_D, PIO_PD29X1_AD10, PIO_PERIPH_F, PIO_DEFAULT }\r
+#define PIN_AD11 { PIO_GROUP_D, PIO_PD30X1_AD11, PIO_PERIPH_F, PIO_DEFAULT }\r
+\r
+#define PIN_ADTRG { PIO_GROUP_D, PIO_PD31A_ADTRG, PIO_PERIPH_A, PIO_DEFAULT }\r
+\r
+/* ========== Pio PIN definition for ARM JTAG peripheral ========== */\r
+\r
+/* JTAG IOSET 1 */\r
+\r
+#define PINS_JTAG_IOS1 {\\r
+ { PIO_GROUP_D, 0x0007c000, PIO_PERIPH_A, PIO_DEFAULT }}\r
+\r
+/* JTAG IOSET 2 */\r
+\r
+#define PINS_JTAG_IOS2 {\\r
+ { PIO_GROUP_D, 0x000007c0, PIO_PERIPH_A, PIO_DEFAULT }}\r
+\r
+/* JTAG IOSET 3 */\r
+\r
+#define PINS_JTAG_IOS3 {\\r
+ { PIO_GROUP_D, 0xf8000000, PIO_PERIPH_B, PIO_DEFAULT }}\r
+\r
+/* JTAG IOSET 4 */\r
+\r
+#define PINS_JTAG_IOS4 {\\r
+ { PIO_GROUP_D, 0x07c00000, PIO_PERIPH_C, PIO_DEFAULT }}\r
+\r
+\r
+/* ========== Pio PIN definition for CAN0 peripheral ========== */\r
+\r
+#define PINS_CAN0_IOS0 {\\r
+ { PIO_GROUP_C, PIO_PC1C_CANTX0 | PIO_PC2C_CANRX0, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+#ifdef PIO_PC10E_CANTX0\r
+#define PINS_CAN0_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC10E_CANTX0 | PIO_PC11E_CANRX0, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+#endif\r
+\r
+/* ========== Pio PIN definition for CAN1 peripheral ========== */\r
+\r
+#ifdef MCAN1\r
+#define PINS_CAN1_IOS0 {\\r
+ { PIO_GROUP_C, PIO_PC26D_CANTX1 | PIO_PC27D_CANRX1, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+#endif\r
+\r
+/* ========== Pio PIN definition for CLASSD peripheral ========== */\r
+\r
+#define PIN_CLASSD_L0_IOS1 \\r
+ { PIO_GROUP_A, PIO_PA28F_CLASSD_L0, PIO_PERIPH_F, PIO_DEFAULT }\r
+\r
+#define PIN_CLASSD_L1_IOS1 \\r
+ { PIO_GROUP_A, PIO_PA29F_CLASSD_L1, PIO_PERIPH_F, PIO_DEFAULT }\r
+\r
+#define PIN_CLASSD_L2_IOS1 \\r
+ { PIO_GROUP_A, PIO_PA30F_CLASSD_L2, PIO_PERIPH_F, PIO_DEFAULT }\r
+\r
+#define PIN_CLASSD_L3_IOS1 \\r
+ { PIO_GROUP_A, PIO_PA31F_CLASSD_L3, PIO_PERIPH_F, PIO_DEFAULT }\r
+\r
+#define PIN_CLASSD_R0_IOS1 \\r
+ { PIO_GROUP_B, PIO_PB1F_CLASSD_R0, PIO_PERIPH_F, PIO_DEFAULT }\r
+\r
+#define PIN_CLASSD_R1_IOS1 \\r
+ { PIO_GROUP_B, PIO_PB2F_CLASSD_R1, PIO_PERIPH_F, PIO_DEFAULT }\r
+\r
+#define PIN_CLASSD_R2_IOS1 \\r
+ { PIO_GROUP_B, PIO_PB3F_CLASSD_R2, PIO_PERIPH_F, PIO_DEFAULT }\r
+\r
+#define PIN_CLASSD_R3_IOS1 \\r
+ { PIO_GROUP_B, PIO_PB4F_CLASSD_R3, PIO_PERIPH_F, PIO_DEFAULT }\r
+\r
+#define PINS_CLASSD_IOS1 {\\r
+ PIN_CLASSD_L0_IOS1, PIN_CLASSD_L1_IOS1, \\r
+ PIN_CLASSD_L2_IOS1, PIN_CLASSD_L3_IOS1, \\r
+ PIN_CLASSD_R0_IOS1, PIN_CLASSD_R1_IOS1, \\r
+ PIN_CLASSD_R2_IOS1, PIN_CLASSD_R3_IOS1, \\r
+};\r
+\r
+/* ========== Pio PIN definition for EBI peripheral ========== */\r
+\r
+/* NFC IOSET 1 */\r
+\r
+#define PINS_NFC_IOS1 {\\r
+ { PIO_GROUP_A, 0xffc00000, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, 0x000007ff, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, 0x00000100, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* NFC IOSET 2 */\r
+\r
+#define PINS_NFC_IOS2 {\\r
+ { PIO_GROUP_A, 0x003fffff, PIO_PERIPH_F, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for FLEXCOM0 peripheral ========== */\r
+\r
+/* FLEXCOM0 IOSET 1 (TWI) */\r
+\r
+#define PINS_FLEXCOM0_TWI_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB28C_FLEXCOM0_IO0 | PIO_PB29C_FLEXCOM0_IO1, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM0 IOSET 1 (USART) */\r
+\r
+#define PINS_FLEXCOM0_USART_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB28C_FLEXCOM0_IO0 | PIO_PB29C_FLEXCOM0_IO1, PIO_PERIPH_C, PIO_DEFAULT },\\r
+};\r
+\r
+\r
+/* FLEXCOM0 IOSET 1 (USART with handshake) */\r
+\r
+#define PINS_FLEXCOM0_USART_HS_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB28C_FLEXCOM0_IO0 | PIO_PB29C_FLEXCOM0_IO1 | PIO_PB31C_FLEXCOM0_IO3, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC0C_FLEXCOM0_IO4, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM0 IOSET 1 (RS485) */\r
+\r
+#define PINS_FLEXCOM0_USART_IOS1_RS485 {\\r
+ { PIO_GROUP_B, PIO_PB28C_FLEXCOM0_IO0 | PIO_PB29C_FLEXCOM0_IO1 | PIO_PC0C_FLEXCOM0_IO4, PIO_PERIPH_C, PIO_DEFAULT },\\r
+};\r
+\r
+/* FLEXCOM0 IOSET 1 (SPI) */\r
+\r
+#define PIN_FLEXCOM0_SPI_NPCS0_IOS1 \\r
+ { PIO_GROUP_B, PIO_PB31C_FLEXCOM0_IO3, PIO_PERIPH_C, PIO_PULLUP }\r
+\r
+#define PIN_FLEXCOM0_SPI_NPCS1_IOS1 \\r
+ { PIO_GROUP_C, PIO_PC0C_FLEXCOM0_IO4, PIO_PERIPH_C, PIO_PULLUP }\r
+\r
+#define PINS_FLEXCOM0_SPI_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB28C_FLEXCOM0_IO0 | PIO_PB29C_FLEXCOM0_IO1 | PIO_PB30C_FLEXCOM0_IO2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_FLEXCOM0_SPI_NPCS0_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB28C_FLEXCOM0_IO0 | PIO_PB29C_FLEXCOM0_IO1 | PIO_PB30C_FLEXCOM0_IO2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ PIN_FLEXCOM0_SPI_NPCS0_IOS1,\\r
+}\r
+\r
+#define PINS_FLEXCOM0_SPI_NPCS1_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB28C_FLEXCOM0_IO0 | PIO_PB29C_FLEXCOM0_IO1 | PIO_PB30C_FLEXCOM0_IO2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ PIN_FLEXCOM0_SPI_NPCS1_IOS1,\\r
+}\r
+\r
+/* ========== Pio PIN definition for FLEXCOM1 peripheral ========== */\r
+\r
+/* FLEXCOM1 IOSET 1 (TWI) */\r
+\r
+#define PINS_FLEXCOM1_TWI_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA24A_FLEXCOM1_IO0 | PIO_PA23A_FLEXCOM1_IO1, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM1 IOSET 1 (USART) */\r
+\r
+#define PINS_FLEXCOM1_USART_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA24A_FLEXCOM1_IO0 | PIO_PA23A_FLEXCOM1_IO1, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM1 IOSET 1 (USART with handshake) */\r
+\r
+#define PINS_FLEXCOM1_USART_HS_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA24A_FLEXCOM1_IO0 | PIO_PA23A_FLEXCOM1_IO1 | PIO_PA25A_FLEXCOM1_IO3 | PIO_PA26A_FLEXCOM1_IO4, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM1 IOSET 1 (RS485) */\r
+\r
+#define PINS_FLEXCOM1_USART_IOS1_RS485 {\\r
+ { PIO_GROUP_A, PIO_PA24A_FLEXCOM1_IO0 | PIO_PA23A_FLEXCOM1_IO1 | PIO_PA26A_FLEXCOM1_IO4, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM1 IOSET 1 (SPI) */\r
+\r
+#define PIN_FLEXCOM1_SPI_NPCS0_IOS1 \\r
+ { PIO_GROUP_A, PIO_PA25A_FLEXCOM1_IO3, PIO_PERIPH_A, PIO_PULLUP }\r
+\r
+#define PIN_FLEXCOM1_SPI_NPCS1_IOS1 \\r
+ { PIO_GROUP_A, PIO_PA26A_FLEXCOM1_IO4, PIO_PERIPH_A, PIO_PULLUP }\r
+\r
+#define PINS_FLEXCOM1_SPI_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA24A_FLEXCOM1_IO0 | PIO_PA23A_FLEXCOM1_IO1 | PIO_PA22A_FLEXCOM1_IO2, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_FLEXCOM1_SPI_NPCS0_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA24A_FLEXCOM1_IO0 | PIO_PA23A_FLEXCOM1_IO1 | PIO_PA22A_FLEXCOM1_IO2, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ PIN_FLEXCOM1_SPI_NPCS0_IOS1,\\r
+}\r
+\r
+#define PINS_FLEXCOM1_SPI_NPCS1_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA24A_FLEXCOM1_IO0 | PIO_PA23A_FLEXCOM1_IO1 | PIO_PA22A_FLEXCOM1_IO2, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ PIN_FLEXCOM1_SPI_NPCS1_IOS1,\\r
+}\r
+\r
+/* ========== Pio PIN definition for FLEXCOM2 peripheral ========== */\r
+\r
+/* FLEXCOM2 IOSET 1 (TWI) */\r
+\r
+#define PINS_FLEXCOM2_TWI_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA6E_FLEXCOM2_IO0 | PIO_PA7E_FLEXCOM2_IO1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM2 IOSET 1 (USART) */\r
+\r
+#define PINS_FLEXCOM2_USART_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA6E_FLEXCOM2_IO0 | PIO_PA7E_FLEXCOM2_IO1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM2 IOSET 1 (USART with handshake) */\r
+\r
+#define PINS_FLEXCOM2_USART_HS_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA6E_FLEXCOM2_IO0 | PIO_PA7E_FLEXCOM2_IO1 | PIO_PA9E_FLEXCOM2_IO3 | PIO_PA10E_FLEXCOM2_IO4, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM2 IOSET 1 (RS485) */\r
+\r
+#define PINS_FLEXCOM2_RS485_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA6E_FLEXCOM2_IO0 | PIO_PA7E_FLEXCOM2_IO1 | PIO_PA10E_FLEXCOM2_IO4, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM2 IOSET 1 (SPI) */\r
+\r
+#define PIN_FLEXCOM2_SPI_NPCS0_IOS1 \\r
+ { PIO_GROUP_A, PIO_PA9E_FLEXCOM2_IO3, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PIN_FLEXCOM2_SPI_NPCS1_IOS1 \\r
+ { PIO_GROUP_A, PIO_PA10E_FLEXCOM2_IO4, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PINS_FLEXCOM2_SPI_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA6E_FLEXCOM2_IO0 | PIO_PA7E_FLEXCOM2_IO1 | PIO_PA8E_FLEXCOM2_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_FLEXCOM2_SPI_NPCS0_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA6E_FLEXCOM2_IO0 | PIO_PA7E_FLEXCOM2_IO1 | PIO_PA8E_FLEXCOM2_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ PIN_FLEXCOM2_SPI_NPCS0_IOS1, \\r
+}\r
+\r
+#define PINS_FLEXCOM2_SPI_NPCS1_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA6E_FLEXCOM2_IO0 | PIO_PA7E_FLEXCOM2_IO1 | PIO_PA8E_FLEXCOM2_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ PIN_FLEXCOM2_SPI_NPCS1_IOS1, \\r
+}\r
+\r
+/* FLEXCOM2 IOSET 2 (TWI) */\r
+\r
+#define PINS_FLEXCOM2_TWI_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD26C_FLEXCOM2_IO0 | PIO_PD27C_FLEXCOM2_IO1, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM2 IOSET 2 (USART) */\r
+\r
+#define PINS_FLEXCOM2_USART_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD26C_FLEXCOM2_IO0 | PIO_PD27C_FLEXCOM2_IO1, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM2 IOSET 2 (USART with handshake) */\r
+\r
+#define PINS_FLEXCOM2_USART_HS_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD26C_FLEXCOM2_IO0 | PIO_PD27C_FLEXCOM2_IO1 | PIO_PD29C_FLEXCOM2_IO3 | PIO_PD30C_FLEXCOM2_IO4, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM2 IOSET 2 (RS485) */\r
+\r
+#define PINS_FLEXCOM2_RS485_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD26C_FLEXCOM2_IO0 | PIO_PD27C_FLEXCOM2_IO1 | PIO_PD30C_FLEXCOM2_IO4, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM2 IOSET 2 (SPI) */\r
+\r
+#define PIN_FLEXCOM2_SPI_NPCS0_IOS2 \\r
+ { PIO_GROUP_D, PIO_PD29C_FLEXCOM2_IO3, PIO_PERIPH_C, PIO_PULLUP }\r
+\r
+#define PIN_FLEXCOM2_SPI_NPCS1_IOS2 \\r
+ { PIO_GROUP_D, PIO_PD30C_FLEXCOM2_IO4, PIO_PERIPH_C, PIO_PULLUP }\r
+\r
+#define PINS_FLEXCOM2_SPI_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD26C_FLEXCOM2_IO0 | PIO_PD27C_FLEXCOM2_IO1 | PIO_PD28C_FLEXCOM2_IO2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_FLEXCOM2_SPI_NPCS0_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD26C_FLEXCOM2_IO0 | PIO_PD27C_FLEXCOM2_IO1 | PIO_PD28C_FLEXCOM2_IO2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ PIN_FLEXCOM2_SPI_NPCS0_IOS2,\\r
+}\r
+\r
+#define PINS_FLEXCOM2_SPI_NPCS1_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD26C_FLEXCOM2_IO0 | PIO_PD27C_FLEXCOM2_IO1 | PIO_PD28C_FLEXCOM2_IO2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ PIN_FLEXCOM2_SPI_NPCS1_IOS2,\\r
+}\r
+\r
+/* ========== Pio PIN definition for FLEXCOM3 peripheral ========== */\r
+\r
+/* FLEXCOM3 IOSET 1 (TWI) */\r
+\r
+#define PINS_FLEXCOM3_TWI_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA15E_FLEXCOM3_IO0 | PIO_PA13E_FLEXCOM3_IO1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 1 (USART) */\r
+\r
+#define PINS_FLEXCOM3_USART_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA15E_FLEXCOM3_IO0 | PIO_PA13E_FLEXCOM3_IO1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 1 (USART with handshake) */\r
+\r
+#define PINS_FLEXCOM3_USART_HS_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA15E_FLEXCOM3_IO0 | PIO_PA13E_FLEXCOM3_IO1 | PIO_PA16E_FLEXCOM3_IO3 | PIO_PA17E_FLEXCOM3_IO4, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 1 (RS585) */\r
+\r
+#define PINS_FLEXCOM3_RS485_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA15E_FLEXCOM3_IO0 | PIO_PA13E_FLEXCOM3_IO1 | PIO_PA17E_FLEXCOM3_IO4, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 1 (SPI) */\r
+\r
+#define PIN_FLEXCOM3_SPI_NPCS0_IOS1 \\r
+ { PIO_GROUP_A, PIO_PA16E_FLEXCOM3_IO3, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PIN_FLEXCOM3_SPI_NPCS1_IOS1 \\r
+ { PIO_GROUP_A, PIO_PA17E_FLEXCOM3_IO4, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PINS_FLEXCOM3_SPI_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA15E_FLEXCOM3_IO0 | PIO_PA13E_FLEXCOM3_IO1 | PIO_PA14E_FLEXCOM3_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_FLEXCOM3_SPI_NPCS0_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA15E_FLEXCOM3_IO0 | PIO_PA13E_FLEXCOM3_IO1 | PIO_PA14E_FLEXCOM3_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ PIN_FLEXCOM3_SPI_NPCS0_IOS1,\\r
+}\r
+\r
+#define PINS_FLEXCOM3_SPI_NPCS1_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA15E_FLEXCOM3_IO0 | PIO_PA13E_FLEXCOM3_IO1 | PIO_PA14E_FLEXCOM3_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ PIN_FLEXCOM3_SPI_NPCS1_IOS1,\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 2 (TWI) */\r
+\r
+#define PINS_FLEXCOM3_TWI_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC20E_FLEXCOM3_IO0 | PIO_PC19E_FLEXCOM3_IO1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 2 (USART) */\r
+\r
+#define PINS_FLEXCOM3_USART_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC20E_FLEXCOM3_IO0 | PIO_PC19E_FLEXCOM3_IO1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 2 (USART with handshake) */\r
+\r
+#define PINS_FLEXCOM3_USART_HS_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC20E_FLEXCOM3_IO0 | PIO_PC19E_FLEXCOM3_IO1 | PIO_PC21E_FLEXCOM3_IO3 | PIO_PC22E_FLEXCOM3_IO4, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 2 (RS485) */\r
+\r
+#define PINS_FLEXCOM3_RS485_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC20E_FLEXCOM3_IO0 | PIO_PC19E_FLEXCOM3_IO1 | PIO_PC22E_FLEXCOM3_IO4, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 2 (SPI) */\r
+\r
+#define PIN_FLEXCOM3_SPI_NPCS0_IOS2 \\r
+ { PIO_GROUP_C, PIO_PC21E_FLEXCOM3_IO3, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PIN_FLEXCOM3_SPI_NPCS1_IOS2 \\r
+ { PIO_GROUP_C, PIO_PC22E_FLEXCOM3_IO4, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PINS_FLEXCOM3_SPI_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC20E_FLEXCOM3_IO0 | PIO_PC19E_FLEXCOM3_IO1 | PIO_PC18E_FLEXCOM3_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_FLEXCOM3_SPI_NPCS0_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC20E_FLEXCOM3_IO0 | PIO_PC19E_FLEXCOM3_IO1 | PIO_PC18E_FLEXCOM3_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ PIN_FLEXCOM3_SPI_NPCS0_IOS2,\\r
+}\r
+\r
+#define PINS_FLEXCOM3_SPI_NPCS1_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC20E_FLEXCOM3_IO0 | PIO_PC19E_FLEXCOM3_IO1 | PIO_PC18E_FLEXCOM3_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ PIN_FLEXCOM3_SPI_NPCS1_IOS2,\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 3 (TWI) */\r
+\r
+#define PINS_FLEXCOM3_TWI_IOS3 {\\r
+ { PIO_GROUP_B, PIO_PB23E_FLEXCOM3_IO0 | PIO_PB22E_FLEXCOM3_IO1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 3 (USART) */\r
+\r
+#define PINS_FLEXCOM3_USART_IOS3 {\\r
+ { PIO_GROUP_B, PIO_PB23E_FLEXCOM3_IO0 | PIO_PB22E_FLEXCOM3_IO1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 3 (USART with handshake) */\r
+\r
+#define PINS_FLEXCOM3_USART_HS_IOS3 {\\r
+ { PIO_GROUP_B, PIO_PB23E_FLEXCOM3_IO0 | PIO_PB22E_FLEXCOM3_IO1 | PIO_PB24E_FLEXCOM3_IO3 | PIO_PB25E_FLEXCOM3_IO4, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 3 (RS485) */\r
+\r
+#define PINS_FLEXCOM3_RS485_IOS3 {\\r
+ { PIO_GROUP_B, PIO_PB23E_FLEXCOM3_IO0 | PIO_PB22E_FLEXCOM3_IO1 | PIO_PB25E_FLEXCOM3_IO4, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM3 IOSET 3 (SPI) */\r
+\r
+#define PIN_FLEXCOM3_SPI_NPCS0_IOS3 \\r
+ { PIO_GROUP_B, PIO_PB24E_FLEXCOM3_IO3, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PIN_FLEXCOM3_SPI_NPCS1_IOS3 \\r
+ { PIO_GROUP_B, PIO_PB25E_FLEXCOM3_IO4, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PINS_FLEXCOM3_SPI_IOS3 {\\r
+ { PIO_GROUP_B, PIO_PB23E_FLEXCOM3_IO0 | PIO_PB22E_FLEXCOM3_IO1 | PIO_PB21E_FLEXCOM3_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_FLEXCOM3_SPI_NPCS0_IOS3 {\\r
+ { PIO_GROUP_B, PIO_PB23E_FLEXCOM3_IO0 | PIO_PB22E_FLEXCOM3_IO1 | PIO_PB21E_FLEXCOM3_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ PIN_FLEXCOM3_SPI_NPCS0_IOS3,\\r
+}\r
+\r
+#define PINS_FLEXCOM3_SPI_NPCS1_IOS3 {\\r
+ { PIO_GROUP_B, PIO_PB23E_FLEXCOM3_IO0 | PIO_PB22E_FLEXCOM3_IO1 | PIO_PB21E_FLEXCOM3_IO2, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ PIN_FLEXCOM3_SPI_NPCS1_IOS3,\\r
+}\r
+\r
+/* ========== Pio PIN definition for FLEXCOM4 peripheral ========== */\r
+\r
+/* FLEXCOM4 IOSET 1 (TWI) */\r
+\r
+#define PINS_FLEXCOM4_TWI_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC28B_FLEXCOM4_IO0 | PIO_PC29B_FLEXCOM4_IO1, PIO_PERIPH_B, PIO_DEFAULT } \\r
+}\r
+\r
+/* FLEXCOM4 IOSET 1 (USART) */\r
+\r
+#define PINS_FLEXCOM4_USART_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC28B_FLEXCOM4_IO0 | PIO_PC29B_FLEXCOM4_IO1, PIO_PERIPH_B, PIO_DEFAULT } \\r
+}\r
+\r
+/* FLEXCOM4 IOSET 1 (USART with handshake) */\r
+\r
+#define PINS_FLEXCOM4_USART_HS_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC28B_FLEXCOM4_IO0 | PIO_PC29B_FLEXCOM4_IO1 | PIO_PC31B_FLEXCOM4_IO3, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD0B_FLEXCOM4_IO4, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 1 (RS485) */\r
+\r
+#define PINS_FLEXCOM4_RS485_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC28B_FLEXCOM4_IO0 | PIO_PC29B_FLEXCOM4_IO1, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD0B_FLEXCOM4_IO4, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 1 (SPI) */\r
+\r
+#define PIN_FLEXCOM4_SPI_NPCS0_IOS1 \\r
+ { PIO_GROUP_C, PIO_PC31B_FLEXCOM4_IO3, PIO_PERIPH_B, PIO_PULLUP }\r
+\r
+#define PIN_FLEXCOM4_SPI_NPCS1_IOS1 \\r
+ { PIO_GROUP_D, PIO_PD0B_FLEXCOM4_IO4, PIO_PERIPH_B, PIO_PULLUP }\r
+\r
+#define PINS_FLEXCOM4_SPI_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC28B_FLEXCOM4_IO0 | PIO_PC29B_FLEXCOM4_IO1 | PIO_PC30B_FLEXCOM4_IO2, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_FLEXCOM4_SPI_NPCS0_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC28B_FLEXCOM4_IO0 | PIO_PC29B_FLEXCOM4_IO1 | PIO_PC30B_FLEXCOM4_IO2, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ PIN_FLEXCOM4_SPI_NPCS0_IOS1,\\r
+}\r
+\r
+#define PINS_FLEXCOM4_SPI_NPCS1_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC28B_FLEXCOM4_IO0 | PIO_PC29B_FLEXCOM4_IO1 | PIO_PC30B_FLEXCOM4_IO2, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ PIN_FLEXCOM4_SPI_NPCS1_IOS1,\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 2 (TWI) */\r
+\r
+#define PINS_FLEXCOM4_TWI_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD12B_FLEXCOM4_IO0 | PIO_PD13B_FLEXCOM4_IO1, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 2 (USART) */\r
+\r
+#define PINS_FLEXCOM4_USART_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD12B_FLEXCOM4_IO0 | PIO_PD13B_FLEXCOM4_IO1, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 2 (USART with handshake) */\r
+\r
+#define PINS_FLEXCOM4_USART_HS_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD12B_FLEXCOM4_IO0 | PIO_PD13B_FLEXCOM4_IO1 | PIO_PD15B_FLEXCOM4_IO3 | PIO_PD16B_FLEXCOM4_IO4, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 2 (RS485) */\r
+\r
+#define PINS_FLEXCOM4_RS485_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD12B_FLEXCOM4_IO0 | PIO_PD13B_FLEXCOM4_IO1 | PIO_PD16B_FLEXCOM4_IO4, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 2 (SPI) */\r
+\r
+#define PIN_FLEXCOM4_SPI_NPCS0_IOS2 \\r
+ { PIO_GROUP_D, PIO_PD15B_FLEXCOM4_IO3, PIO_PERIPH_B, PIO_PULLUP }\r
+\r
+#define PIN_FLEXCOM4_SPI_NPCS1_IOS2 \\r
+ { PIO_GROUP_D, PIO_PD16B_FLEXCOM4_IO4, PIO_PERIPH_B, PIO_PULLUP }\r
+\r
+#define PINS_FLEXCOM4_SPI_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD12B_FLEXCOM4_IO0 | PIO_PD13B_FLEXCOM4_IO1 | PIO_PD14B_FLEXCOM4_IO2, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_FLEXCOM4_SPI_NPCS0_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD12B_FLEXCOM4_IO0 | PIO_PD13B_FLEXCOM4_IO1 | PIO_PD14B_FLEXCOM4_IO2, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ PIN_FLEXCOM4_SPI_NPCS0_IOS2,\\r
+}\r
+\r
+#define PINS_FLEXCOM4_SPI_NPCS1_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD12B_FLEXCOM4_IO0 | PIO_PD13B_FLEXCOM4_IO1 | PIO_PD14B_FLEXCOM4_IO2, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ PIN_FLEXCOM4_SPI_NPCS1_IOS2,\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 3 (TWI) */\r
+\r
+#define PINS_FLEXCOM4_TWI_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD21C_FLEXCOM4_IO0 | PIO_PD22C_FLEXCOM4_IO1, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 3 (USART) */\r
+\r
+#define PINS_FLEXCOM4_USART_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD21C_FLEXCOM4_IO0 | PIO_PD22C_FLEXCOM4_IO1, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 3 (USART with handshake) */\r
+\r
+#define PINS_FLEXCOM4_USART_HS_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD21C_FLEXCOM4_IO0 | PIO_PD22C_FLEXCOM4_IO1 | PIO_PD24C_FLEXCOM4_IO3 | PIO_PD25C_FLEXCOM4_IO4, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 3 (RS485) */\r
+\r
+#define PINS_FLEXCOM4_RS485_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD21C_FLEXCOM4_IO0 | PIO_PD22C_FLEXCOM4_IO1 | PIO_PD25C_FLEXCOM4_IO4, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* FLEXCOM4 IOSET 3 (SPI) */\r
+\r
+#define PIN_FLEXCOM4_SPI_NPCS0_IOS3 \\r
+ { PIO_GROUP_D, PIO_PD24C_FLEXCOM4_IO3, PIO_PERIPH_C, PIO_PULLUP }\r
+\r
+#define PIN_FLEXCOM4_SPI_NPCS1_IOS3 \\r
+ { PIO_GROUP_D, PIO_PD25C_FLEXCOM4_IO4, PIO_PERIPH_C, PIO_PULLUP }\r
+\r
+#define PINS_FLEXCOM4_SPI_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD21C_FLEXCOM4_IO0 | PIO_PD22C_FLEXCOM4_IO1 | PIO_PD23C_FLEXCOM4_IO2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_FLEXCOM4_SPI_NPCS0_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD21C_FLEXCOM4_IO0 | PIO_PD22C_FLEXCOM4_IO1 | PIO_PD23C_FLEXCOM4_IO2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ PIN_FLEXCOM4_SPI_NPCS0_IOS3,\\r
+}\r
+\r
+#define PINS_FLEXCOM4_SPI_NPCS1_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD21C_FLEXCOM4_IO0 | PIO_PD22C_FLEXCOM4_IO1 | PIO_PD23C_FLEXCOM4_IO2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ PIN_FLEXCOM4_SPI_NPCS1_IOS3,\\r
+}\r
+\r
+/* ========== Pio PIN definition for GMAC peripheral ========== */\r
+\r
+#define PIN_GTSUCOM_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC9B_GTSUCOMP, PIO_PERIPH_B, PIO_PULLUP | PIO_IT_FALL_EDGE },\\r
+}\r
+\r
+#define PINS_GMAC_MII_IOS1 {\\r
+ { PIO_GROUP_C, 0x0FFFFC00, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_GMAC_RMII_IOS1 {\\r
+ { PIO_GROUP_C, 0x000FFC00, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+#define PIN_GTSUCOM_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD0D_GTSUCOMP, PIO_PERIPH_D, PIO_PULLUP | PIO_IT_FALL_EDGE },\\r
+}\r
+\r
+#define PINS_GMAC_MII_IOS2 {\\r
+ { PIO_GROUP_D, 0x0007FFFE, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_GMAC_RMII_IOS2 {\\r
+ { PIO_GROUP_D, 0x0007FE00, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+#define PIN_GTSUCOM_IOS3 {\\r
+ { PIO_GROUP_B, PIO_PB5F_GTSUCOMP, PIO_PERIPH_F, PIO_PULLUP | PIO_IT_FALL_EDGE },\\r
+}\r
+\r
+#define PINS_GMAC_MII_IOS3 {\\r
+ { PIO_GROUP_B, 0x00FFFFC0, PIO_PERIPH_F, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_GMAC_RMII_IOS3 {\\r
+ { PIO_GROUP_B, 0x00FFC000, PIO_PERIPH_F, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for I2SC0 peripheral ========== */\r
+\r
+#define I2S0_IOS1 (PIO_PC1E_I2SCK0 | PIO_PC2E_I2SMCK0 | PIO_PC3E_I2SWS0 | PIO_PC4E_I2SDI0 | PIO_PC5E_I2SDO0)\r
+#define PINS_I2S0_IOS1 {\\r
+ { PIO_GROUP_C, I2S0_IOS1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+#define I2S0_IOS2 (PIO_PD19E_I2SCK0 | PIO_PD20E_I2SMCK0 | PIO_PD21E_I2SWS0 | PIO_PD22E_I2SDI0 | PIO_PD23E_I2SDO0)\r
+#define PINS_I2S0_IOS2 {\\r
+ { PIO_GROUP_D, I2S0_IOS1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for I2SC1 peripheral ========== */\r
+\r
+#define I2S1_IOS1 (PIO_PB14D_I2SMCK1 | PIO_PB15D_I2SCK1 | PIO_PB16D_I2SWS1 | PIO_PB17D_I2SDI1 | PIO_PB18D_I2SDO1)\r
+#define PINS_I2S1_IOS1 {\\r
+ { PIO_GROUP_B, I2S_IOS1, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+#define I2S1_IOS2 (PIO_PA14D_I2SMCK1 | PIO_PA15D_I2SCK1 | PIO_PA16D_I2SWS1 | PIO_PA17D_I2SDI1 | PIO_PA18D_I2SDO1)\r
+#define PINS_I2S1_IOS2 {\\r
+ { PIO_GROUP_A, I2S_IOS2, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for ISI peripheral ========== */\r
+\r
+#define PIN_ISC_FIELD_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC25C_ISC_FIELD, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_ISC_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC22C_ISC_VSYNC, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC23C_ISC_HSYNC, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC24C_ISC_MCK, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC21C_ISC_PCK, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, 0x001FFE00, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+#define PIN_ISC_FIELD_IOS2 {\\r
+ { ID_PIOD, PIO_PD18E_ISC_FIELD, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_ISC_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD16E_ISC_VSYNC, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD17E_ISC_HSYNC, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD2E_ISC_MCK, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD15E_ISC_PCK, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, 0x00007FF8, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+#define PIN_ISC_FIELD_IOS3 {\\r
+ { PIO_GROUP_C, PIO_PC8F_ISC_FIELD, PIO_PERIPH_F, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_ISC_IOS3 {\\r
+ { PIO_GROUP_C, PIO_PC5F_ISC_VSYNC, PIO_PERIPH_F, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC6F_ISC_HSYNC, PIO_PERIPH_F, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC7F_ISC_MCK, PIO_PERIPH_F, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC4F_ISC_PCK, PIO_PERIPH_F, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, 0xFF000000, PIO_PERIPH_F, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, 0x0000000F, PIO_PERIPH_F, PIO_DEFAULT },\\r
+}\r
+\r
+#define PIN_ISC_FIELD_IOS4 {\\r
+ { PIO_GROUP_D, PIO_PD23F_ISC_FIELD, PIO_PERIPH_F, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_ISC_IOS4 {\\r
+ { PIO_GROUP_D, PIO_PD21F_ISC_VSYNC, PIO_PERIPH_F, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD22F_ISC_HSYNC, PIO_PERIPH_F, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD11F_ISC_MCK, PIO_PERIPH_F, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD20F_ISC_PCK, PIO_PERIPH_F, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, 0x000FF000, PIO_PERIPH_F, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for LCDC peripheral ========== */\r
+\r
+/* LCD 24 bits */\r
+#define PINS_LCD_IOS1 {\\r
+ { PIO_GROUP_B, 0xFFFFF800, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, 0x000001FF, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+/* LCD 18 bits */\r
+#define PINS_LCD_IOS2 {\\r
+ { PIO_GROUP_C, 0xFFFFF800, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, 0x00000003, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for PDMIC peripheral ========== */\r
+\r
+#define PINS_PDMIC_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB26D_PDMDAT | PIO_PB27D_PDMCLK, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_PDMIC_IOS2 {\\r
+ { PIO_GROUP_B, PIO_PB11D_PDMDAT | PIO_PB12D_PDMCLK, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for PMC peripheral ========== */\r
+\r
+#define PINS_PCK0_IOS1 {\\r
+ { PIO_GROUP_D, PIO_PD19A_PCK0, PIO_PERIPH_A, PIO_DEFAULT }}\r
+\r
+#define PINS_PCK0_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD31E_PCK0, PIO_PERIPH_E, PIO_DEFAULT }}\r
+\r
+#define PINS_PCK0_IOS3 {\\r
+ { PIO_GROUP_C, PIO_PC8D_PCK0, PIO_PERIPH_D, PIO_DEFAULT }}\r
+\r
+#define PINS_PCK1_IOS1 {\\r
+ { PIO_GROUP_D, PIO_PD6B_PCK1, PIO_PERIPH_B, PIO_DEFAULT }}\r
+\r
+#define PINS_PCK1_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC27C_PCK1, PIO_PERIPH_C, PIO_DEFAULT }}\r
+\r
+#define PINS_PCK1_IOS3 {\\r
+ { PIO_GROUP_B, PIO_PB13C_PCK1, PIO_PERIPH_C, PIO_DEFAULT }}\r
+\r
+#define PINS_PCK1_IOS4 {\\r
+ { PIO_GROUP_B, PIO_PB20E_PCK1, PIO_PERIPH_E, PIO_DEFAULT }}\r
+\r
+#define PINS_PCK2_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC28C_PCK2, PIO_PERIPH_C, PIO_DEFAULT }}\r
+\r
+#define PINS_PCK2_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD11B_PCK2, PIO_PERIPH_B, PIO_DEFAULT }}\r
+\r
+#define PINS_PCK2_IOS3 {\\r
+ { PIO_GROUP_A, PIO_PA21B_PCK2, PIO_PERIPH_B, PIO_DEFAULT }}\r
+\r
+/* ========== Pio PIN definition for PWM peripheral ========== */\r
+\r
+#define PINS_PWMH0_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA30D_PWMH0, PIO_PERIPH_D, PIO_DEFAULT }}\r
+\r
+#define PINS_PWML0_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA31D_PWML0, PIO_PERIPH_D, PIO_DEFAULT }}\r
+\r
+#define PINS_PWMH1_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB0D_PWMH1, PIO_PERIPH_D, PIO_DEFAULT }}\r
+\r
+#define PINS_PWML1_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB1D_PWML1, PIO_PERIPH_D, PIO_DEFAULT }}\r
+\r
+#define PINS_PWMH2_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB5C_PWMH2, PIO_PERIPH_C, PIO_DEFAULT }}\r
+\r
+#define PINS_PWML2_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB6C_PWML2, PIO_PERIPH_C, PIO_DEFAULT }}\r
+\r
+#define PINS_PWMH3_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB7C_PWMH3, PIO_PERIPH_C, PIO_DEFAULT }}\r
+\r
+#define PINS_PWML3_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB8C_PWML3, PIO_PERIPH_C, PIO_DEFAULT }}\r
+\r
+#define PINS_EXTRG0_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB3D_PWMEXTRG0, PIO_PERIPH_D, PIO_DEFAULT }}\r
+\r
+#define PINS_EXTRG1_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB10C_PWMEXTRG1, PIO_PERIPH_C, PIO_DEFAULT }}\r
+\r
+#define PINS_PWMFI0_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB2D_PWMFI0, PIO_PERIPH_D, PIO_DEFAULT }}\r
+\r
+#define PINS_PWMFI1_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB9C_PWMFI1, PIO_PERIPH_C, PIO_DEFAULT }}\r
+\r
+/* ========== Pio PIN definition for QSPI0 peripheral ========== */\r
+\r
+/* QSPI0 IOSET 1 */\r
+#define PINS_QSPI0_IOS1 {\\r
+ { PIO_GROUP_A, 0x0000003f, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* QSPI0 IOSET 2 */\r
+#define PINS_QSPI0_IOS2 {\\r
+ { PIO_GROUP_A, 0x000fc000, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* QSPI0 IOSET 3 */\r
+#define PINS_QSPI0_IOS3 {\\r
+ { PIO_GROUP_A, 0x0fc00000, PIO_PERIPH_F, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for QSPI1 peripheral ========== */\r
+\r
+/* QSPI1 IOSET 1 */\r
+#define PINS_QSPI1_IOS1 {\\r
+ { PIO_GROUP_A, 0x00000fc0, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* QSPI1 IOSET 2 */\r
+#define PINS_QSPI1_IOS2 {\\r
+ { PIO_GROUP_B, 0x000007e0, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+/* QSPI1 IOSET 3 */\r
+#define PINS_QSPI1_IOS3 {\\r
+ { PIO_GROUP_B, 0x000fc000, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for SDMMC0 peripheral ========== */\r
+\r
+#if defined(PIO_PA1A_SDMMC0_CMD)\r
+\r
+#define PINS_SDMMC0_1B_IOS1 { PIO_GROUP_A, PIO_PA1A_SDMMC0_CMD\\r
+ | PIO_PA2A_SDMMC0_DAT0, PIO_PERIPH_A, PIO_PULLUP }\r
+\r
+#define PINS_SDMMC0_4B_IOS1 { PIO_GROUP_A, PIO_PA1A_SDMMC0_CMD\\r
+ | PIO_PA5A_SDMMC0_DAT3 | PIO_PA4A_SDMMC0_DAT2 | PIO_PA3A_SDMMC0_DAT1\\r
+ | PIO_PA2A_SDMMC0_DAT0, PIO_PERIPH_A, PIO_PULLUP }\r
+\r
+#define PINS_SDMMC0_8B_IOS1 { PIO_GROUP_A, PIO_PA1A_SDMMC0_CMD\\r
+ | PIO_PA9A_SDMMC0_DAT7 | PIO_PA8A_SDMMC0_DAT6 | PIO_PA7A_SDMMC0_DAT5\\r
+ | PIO_PA6A_SDMMC0_DAT4 | PIO_PA5A_SDMMC0_DAT3 | PIO_PA4A_SDMMC0_DAT2\\r
+ | PIO_PA3A_SDMMC0_DAT1 | PIO_PA2A_SDMMC0_DAT0, PIO_PERIPH_A, PIO_PULLUP }\r
+\r
+#define PIN_SDMMC0_CD_IOS1 { PIO_GROUP_A, PIO_PA13A_SDMMC0_CD, PIO_PERIPH_A, PIO_PULLUP }\r
+#define PIN_SDMMC0_VDDSEL_IOS1 { PIO_GROUP_A, PIO_PA11A_SDMMC0_VDDSEL, PIO_PERIPH_A, PIO_DEFAULT }\r
+#define PIN_SDMMC0_RSTN_IOS1 { PIO_GROUP_A, PIO_PA10A_SDMMC0_RSTN, PIO_PERIPH_A, PIO_PULLUP }\r
+#define PIN_SDMMC0_CK_IOS1 { PIO_GROUP_A, PIO_PA0A_SDMMC0_CK, PIO_PERIPH_A, PIO_DEFAULT }\r
+#define PIN_SDMMC0_RES_IOS1 { PIO_GROUP_A, PIO_PA5A_SDMMC0_DAT3, PIO_PERIPH_A, PIO_PULLUP }\r
+#define PIN_SDMMC0_WP_IOS1 { PIO_GROUP_A, PIO_PA12A_SDMMC0_WP, PIO_PERIPH_A, PIO_PULLUP }\r
+\r
+#elif defined(PIO_PA28E_SDMMC0_CMD)\r
+\r
+#define PINS_SDMMC0_1B_IOS1 { PIO_GROUP_A, PIO_PA28E_SDMMC0_CMD\\r
+ | PIO_PA18E_SDMMC0_DAT0, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PINS_SDMMC0_4B_IOS1 { PIO_GROUP_A, PIO_PA28E_SDMMC0_CMD\\r
+ | PIO_PA21E_SDMMC0_DAT3 | PIO_PA20E_SDMMC0_DAT2 | PIO_PA19E_SDMMC0_DAT1\\r
+ | PIO_PA18E_SDMMC0_DAT0, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PIN_SDMMC0_CD_IOS1 { PIO_GROUP_A, PIO_PA30E_SDMMC0_CD, PIO_PERIPH_E, PIO_PULLUP }\r
+#define PIN_SDMMC0_RSTN_IOS1 { PIO_GROUP_A, PIO_PA27E_SDMMC0_RSTN, PIO_PERIPH_E, PIO_PULLUP }\r
+#define PIN_SDMMC0_CK_IOS1 { PIO_GROUP_A, PIO_PA22E_SDMMC0_CK, PIO_PERIPH_E, PIO_DEFAULT }\r
+#define PIN_SDMMC0_RES_IOS1 { PIO_GROUP_A, PIO_PA21E_SDMMC0_DAT3, PIO_PERIPH_E, PIO_PULLUP }\r
+#define PIN_SDMMC0_WP_IOS1 { PIO_GROUP_A, PIO_PA29E_SDMMC0_WP, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#endif\r
+\r
+/* ========== Pio PIN definition for SDMMC1 peripheral ========== */\r
+\r
+#ifdef SDMMC1\r
+#define PINS_SDMMC1_1B_IOS1 { PIO_GROUP_A, PIO_PA28E_SDMMC1_CMD\\r
+ | PIO_PA18E_SDMMC1_DAT0, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PINS_SDMMC1_4B_IOS1 { PIO_GROUP_A, PIO_PA28E_SDMMC1_CMD\\r
+ | PIO_PA21E_SDMMC1_DAT3 | PIO_PA20E_SDMMC1_DAT2 | PIO_PA19E_SDMMC1_DAT1\\r
+ | PIO_PA18E_SDMMC1_DAT0, PIO_PERIPH_E, PIO_PULLUP }\r
+\r
+#define PIN_SDMMC1_CD_IOS1 { PIO_GROUP_A, PIO_PA30E_SDMMC1_CD, PIO_PERIPH_E, PIO_PULLUP }\r
+#define PIN_SDMMC1_RSTN_IOS1 { PIO_GROUP_A, PIO_PA27E_SDMMC1_RSTN, PIO_PERIPH_E, PIO_PULLUP }\r
+#define PIN_SDMMC1_CK_IOS1 { PIO_GROUP_A, PIO_PA22E_SDMMC1_CK, PIO_PERIPH_E, PIO_DEFAULT }\r
+#define PIN_SDMMC1_RES_IOS1 { PIO_GROUP_A, PIO_PA21E_SDMMC1_DAT3, PIO_PERIPH_E, PIO_PULLUP }\r
+#define PIN_SDMMC1_WP_IOS1 { PIO_GROUP_A, PIO_PA29E_SDMMC1_WP, PIO_PERIPH_E, PIO_PULLUP }\r
+#endif\r
+\r
+/* ========== Pio PIN definition for SPI0 peripheral ========== */\r
+\r
+/* SPI0 IOSET 1 */\r
+\r
+#define PIN_SPI0_NPCS0_IOS1 { PIO_GROUP_A, PIO_PA17A_SPI0_NPCS0, PIO_PERIPH_A, PIO_PULLUP }\r
+#define PIN_SPI0_NPCS1_IOS1 { PIO_GROUP_A, PIO_PA18A_SPI0_NPCS1, PIO_PERIPH_A, PIO_PULLUP }\r
+#define PIN_SPI0_NPCS2_IOS1 { PIO_GROUP_A, PIO_PA19A_SPI0_NPCS2, PIO_PERIPH_A, PIO_PULLUP }\r
+#define PIN_SPI0_NPCS3_IOS1 { PIO_GROUP_A, PIO_PA20A_SPI0_NPCS3, PIO_PERIPH_A, PIO_PULLUP }\r
+\r
+#define PINS_SPI0_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA14A_SPI0_SPCK | PIO_PA15A_SPI0_MOSI | PIO_PA16A_SPI0_MISO, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_SPI0_NPCS0_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA14A_SPI0_SPCK | PIO_PA15A_SPI0_MOSI | PIO_PA16A_SPI0_MISO, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ PIN_SPI0_NPCS0_IOS1,\\r
+}\r
+\r
+#define PINS_SPI0_NPCS1_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA14A_SPI0_SPCK | PIO_PA15A_SPI0_MOSI | PIO_PA16A_SPI0_MISO, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ PIN_SPI0_NPCS1_IOS1,\\r
+}\r
+\r
+#define PINS_SPI0_NPCS2_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA14A_SPI0_SPCK | PIO_PA15A_SPI0_MOSI | PIO_PA16A_SPI0_MISO, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ PIN_SPI0_NPCS2_IOS1,\\r
+}\r
+\r
+#define PINS_SPI0_NPCS3_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA14A_SPI0_SPCK | PIO_PA15A_SPI0_MOSI | PIO_PA16A_SPI0_MISO, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ PIN_SPI0_NPCS3_IOS1,\\r
+}\r
+\r
+/* SPI0 IOSET 2 */\r
+\r
+#define PIN_SPI0_NPCS0_IOS2 { PIO_GROUP_A, PIO_PA30C_SPI0_NPCS0, PIO_PERIPH_C, PIO_PULLUP }\r
+#define PIN_SPI0_NPCS1_IOS2 { PIO_GROUP_A, PIO_PA29C_SPI0_NPCS1, PIO_PERIPH_C, PIO_PULLUP }\r
+#define PIN_SPI0_NPCS2_IOS2 { PIO_GROUP_A, PIO_PA27C_SPI0_NPCS2, PIO_PERIPH_C, PIO_PULLUP }\r
+#define PIN_SPI0_NPCS3_IOS2 { PIO_GROUP_A, PIO_PA28C_SPI0_NPCS3, PIO_PERIPH_C, PIO_PULLUP }\r
+\r
+#define PINS_SPI0_IOS2 {\\r
+ { PIO_GROUP_B, PIO_PB1C_SPI0_SPCK | PIO_PB0C_SPI0_MOSI, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA31C_SPI0_MISO, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_SPI0_NPCS0_IOS2 {\\r
+ { PIO_GROUP_B, PIO_PB1C_SPI0_SPCK | PIO_PB0C_SPI0_MOSI, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA31C_SPI0_MISO, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ PIN_SPI0_NPCS0_IOS2,\\r
+}\r
+\r
+#define PINS_SPI0_NPCS1_IOS2 {\\r
+ { PIO_GROUP_B, PIO_PB1C_SPI0_SPCK | PIO_PB0C_SPI0_MOSI, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA31C_SPI0_MISO, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ PIN_SPI0_NPCS1_IOS2,\\r
+}\r
+\r
+#define PINS_SPI0_NPCS2_IOS2 {\\r
+ { PIO_GROUP_B, PIO_PB1C_SPI0_SPCK | PIO_PB0C_SPI0_MOSI, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA31C_SPI0_MISO, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ PIN_SPI0_NPCS2_IOS2,\\r
+}\r
+\r
+#define PINS_SPI0_NPCS3_IOS2 {\\r
+ { PIO_GROUP_B, PIO_PB1C_SPI0_SPCK | PIO_PB0C_SPI0_MOSI, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA31C_SPI0_MISO, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ PIN_SPI0_NPCS3_IOS2,\\r
+}\r
+\r
+/* ========== Pio PIN definition for SPI1 peripheral ========== */\r
+\r
+/* SPI1 IOSET 1 */\r
+\r
+#define PIN_SPI1_NPCS0_IOS1 { PIO_GROUP_C, PIO_PC4D_SPI1_NPCS0, PIO_PERIPH_D, PIO_PULLUP }\r
+#define PIN_SPI1_NPCS1_IOS1 { PIO_GROUP_C, PIO_PC5D_SPI1_NPCS1, PIO_PERIPH_D, PIO_PULLUP }\r
+#define PIN_SPI1_NPCS2_IOS1 { PIO_GROUP_C, PIO_PC6D_SPI1_NPCS2, PIO_PERIPH_D, PIO_PULLUP }\r
+#define PIN_SPI1_NPCS3_IOS1 { PIO_GROUP_C, PIO_PC7D_SPI1_NPCS3, PIO_PERIPH_D, PIO_PULLUP }\r
+\r
+#define PINS_SPI1_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC1D_SPI1_SPCK | PIO_PC2D_SPI1_MOSI | PIO_PC3D_SPI1_MISO, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_SPI1_NPCS0_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC1D_SPI1_SPCK | PIO_PC2D_SPI1_MOSI | PIO_PC3D_SPI1_MISO, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS0_IOS1,\\r
+}\r
+\r
+#define PINS_SPI1_NPCS1_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC1D_SPI1_SPCK | PIO_PC2D_SPI1_MOSI | PIO_PC3D_SPI1_MISO, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS1_IOS1,\\r
+}\r
+\r
+#define PINS_SPI1_NPCS2_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC1D_SPI1_SPCK | PIO_PC2D_SPI1_MOSI | PIO_PC3D_SPI1_MISO, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS2_IOS1,\\r
+}\r
+\r
+#define PINS_SPI1_NPCS3_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC1D_SPI1_SPCK | PIO_PC2D_SPI1_MOSI | PIO_PC3D_SPI1_MISO, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS3_IOS1,\\r
+}\r
+\r
+/* SPI1 IOSET 2 */\r
+\r
+#define PIN_SPI1_NPCS0_IOS2 { PIO_GROUP_A, PIO_PA25D_SPI1_NPCS0, PIO_PERIPH_D, PIO_PULLUP }\r
+#define PIN_SPI1_NPCS1_IOS2 { PIO_GROUP_A, PIO_PA26D_SPI1_NPCS1, PIO_PERIPH_D, PIO_PULLUP }\r
+#define PIN_SPI1_NPCS2_IOS2 { PIO_GROUP_A, PIO_PA27D_SPI1_NPCS2, PIO_PERIPH_D, PIO_PULLUP }\r
+#define PIN_SPI1_NPCS3_IOS2 { PIO_GROUP_A, PIO_PA28D_SPI1_NPCS3, PIO_PERIPH_D, PIO_PULLUP }\r
+\r
+#define PINS_SPI1_IOS2 {\\r
+ { PIO_GROUP_A, PIO_PA22D_SPI1_SPCK | PIO_PA23D_SPI1_MOSI | PIO_PA24D_SPI1_MISO, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_SPI1_NPCS0_IOS2 {\\r
+ { PIO_GROUP_A, PIO_PA22D_SPI1_SPCK | PIO_PA23D_SPI1_MOSI | PIO_PA24D_SPI1_MISO, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS0_IOS2,\\r
+}\r
+\r
+#define PINS_SPI1_NPCS1_IOS2 {\\r
+ { PIO_GROUP_A, PIO_PA22D_SPI1_SPCK | PIO_PA23D_SPI1_MOSI | PIO_PA24D_SPI1_MISO, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS1_IOS2,\\r
+}\r
+\r
+#define PINS_SPI1_NPCS2_IOS2 {\\r
+ { PIO_GROUP_A, PIO_PA22D_SPI1_SPCK | PIO_PA23D_SPI1_MOSI | PIO_PA24D_SPI1_MISO, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS2_IOS2,\\r
+}\r
+\r
+#define PINS_SPI1_NPCS3_IOS2 {\\r
+ { PIO_GROUP_A, PIO_PA22D_SPI1_SPCK | PIO_PA23D_SPI1_MOSI | PIO_PA24D_SPI1_MISO, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS3_IOS2,\\r
+}\r
+\r
+/* SPI1 IOSET 3 */\r
+\r
+#define PIN_SPI1_NPCS0_IOS3 { PIO_GROUP_D, PIO_PD28A_SPI1_NPCS0, PIO_PERIPH_A, PIO_PULLUP }\r
+#define PIN_SPI1_NPCS1_IOS3 { PIO_GROUP_D, PIO_PD29A_SPI1_NPCS1, PIO_PERIPH_A, PIO_PULLUP }\r
+#define PIN_SPI1_NPCS2_IOS3 { PIO_GROUP_D, PIO_PD30A_SPI1_NPCS2, PIO_PERIPH_A, PIO_PULLUP }\r
+\r
+#define PINS_SPI1_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD25A_SPI1_SPCK | PIO_PD26A_SPI1_MOSI | PIO_PD27A_SPI1_MISO, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_SPI1_NPCS0_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD25A_SPI1_SPCK | PIO_PD26A_SPI1_MOSI | PIO_PD27A_SPI1_MISO, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS0_IOS3,\\r
+}\r
+\r
+#define PINS_SPI1_NPCS1_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD25A_SPI1_SPCK | PIO_PD26A_SPI1_MOSI | PIO_PD27A_SPI1_MISO, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS1_IOS3,\\r
+}\r
+\r
+#define PINS_SPI1_NPCS2_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD25A_SPI1_SPCK | PIO_PD26A_SPI1_MOSI | PIO_PD27A_SPI1_MISO, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ PIN_SPI1_NPCS2_IOS3,\\r
+}\r
+\r
+/* ========== Pio PIN definition for SSC0 peripheral ========== */\r
+\r
+#define SSC0_IOS1_TX (PIO_PB20C_TK0 | PIO_PB21C_TF0 | PIO_PB22C_TD0)\r
+#define SSC0_IOS1_RX (PIO_PB23C_RD0 | PIO_PB24C_RK0 | PIO_PB25C_RF0)\r
+#define PINS_SSC0_IOS1 {\\r
+ { PIO_GROUP_C, SSC0_IOS1_TX | SSC0_IOS1_RX, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+#define SSC0_IOS2_TX (PIO_PC12E_TK0 | PIO_PC13E_TF0 | PIO_PB2PIO_PC14E_TD02C_TD0)\r
+#define SSC0_IOS2_RX (PIO_PC15E_RD0 | PIO_PC16E_RK0 | PIO_PC17E_RF0)\r
+#define PINS_SSC0_IOS2 {\\r
+ { PIO_GROUP_C, SSC0_IOS2_TX | SSC0_IOS2_RX, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for SSC1 peripheral ========== */\r
+\r
+#define SSC1_IOS1_TX (PIO_PA14B_TK1 | PIO_PA15B_TF1 | PIO_PA16B_TD1)\r
+#define SSC1_IOS1_RX (PIO_PA17B_RD1 | PIO_PA18B_RK1 | PIO_PA19B_RF1)\r
+#define PINS_SSC1_IOS1 {\\r
+ { PIO_GROUP_A, SSC1_IOS1_TX | SSC1_IOS1_RX, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+#define SSC1_IOS2_TX (PIO_PB14C_TK1 | PIO_PB15C_TF1 | PIO_PB16C_TD1)\r
+#define SSC1_IOS2_RX (PIO_PB17C_RD1 | PIO_PB18C_RK1 | PIO_PB19C_RF1)\r
+#define PINS_SSC1_IOS2 {\\r
+ { PIO_GROUP_B, SSC1_IOS2_TX | SSC1_IOS2_RX, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for TC0 peripheral ========== */\r
+\r
+#define PINS_TC0_TIO0_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA19D_TIOA0, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA20D_TIOB0, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA21D_TCLK0, PIO_PERIPH_D, PIO_DEFAULT }\\r
+}\r
+\r
+#define PINS_TC0_TIO1_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC3C_TIOA1, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC4C_TIOB1, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC5C_TCLK1, PIO_PERIPH_C, PIO_DEFAULT }\\r
+}\r
+\r
+#define PINS_TC0_TIO1_IOS2 {\\r
+ { PIO_GROUP_A, PIO_PA27A_TIOA1, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA28A_TIOB1, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA29A_TCLK1, PIO_PERIPH_A, PIO_DEFAULT }\\r
+}\r
+\r
+#define PINS_TC0_TIO1_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD11A_TIOA1, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD12A_TIOB1, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD13A_TCLK1, PIO_PERIPH_A, PIO_DEFAULT }\\r
+}\r
+\r
+#define PINS_TC0_TIO2_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB6A_TIOA2, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB7A_TIOB2, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_PB5A_TCLK2, PIO_CFGR_B, FUNC_PERIPH_A, PIO_DEFAULT }\\r
+}\r
+\r
+#define PINS_TC0_TIO2_IOS2 {\\r
+ { PIO_GROUP_B, PIO_PB22D_TIOA2, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB23D_TIOB2, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB24D_TCLK2, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_TC0_TIO2_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD20A_TIOA2, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD21A_TIOB2, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD22A_TCLK2, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for TC1 peripheral ========== */\r
+\r
+#define PINS_TC1_TIO3_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB9A_TIOA3, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB10A_TIOB3, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB8A_TCLK3, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_TC1_TIO3_IOS2 {\\r
+ { PIO_GROUP_B, PIO_PB19D_TIOA3, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB20D_TIOB3, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB21D_TCLK3, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_TC1_TIO3_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD29D_TIOA3, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD30D_TIOB3, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD31D_TCLK3, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+#define PINS_TC1_TIO4_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA9D_TIOA4, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA10D_TIOB4, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA11D_TCLK4, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+#define PINS_TC1_TIO4_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC9D_TIOA4, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC10D_TIOB4, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC11D_TCLK4, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_TC1_TIO5_IOS1 {\\r
+ { PIO_GROUP_A, PIO_PA6D_TIOA5, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA7D_TIOB5, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_A, PIO_PA8D_TCLK5, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+#define PINS_TC1_TIO5_IOS2 {\\r
+ { PIO_GROUP_B, PIO_PB28D_TIOA5, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB29D_TIOB5, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB30D_TCLK5, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for TWIHS0 peripheral ========== */\r
+\r
+/* TWI0 IOSET 1 */\r
+#define PINS_TWI0_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB31D_TWD0, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC0D_TWCK0, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+/* TWI0 IOSET 2 */\r
+#define PINS_TWI0_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC27E_TWD0, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC28E_TWCK0, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* TWI0 IOSET 3 */\r
+#define PINS_TWI0_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD29E_TWD0, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD30E_TWCK0, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* TWI0 IOSET 4 */\r
+#define PINS_TWI0_IOS4 {\\r
+ { PIO_GROUP_D, PIO_PD21B_TWD0, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD22B_TWCK0, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for TWIHS1 peripheral ========== */\r
+\r
+/* TWI1 IOSET 1 */\r
+#define PINS_TWI1_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC6C_TWD1, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC7C_TWCK1, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* TWI1 IOSET 2 */\r
+#define PINS_TWI1_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD4A_TWD1, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD5A_TWCK1, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+/* TWI1 IOSET 3 */\r
+#define PINS_TWI1_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD19B_TWD1, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD20B_TWCK1, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for UART0 peripheral ========== */\r
+\r
+/* UART0 IOSET 1 */\r
+#define PINS_UART0_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB26C_URXD0, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB27C_UTXD0, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for UART1 peripheral ========== */\r
+\r
+/* UART1 IOSET 1 */\r
+#define PINS_UART1_IOS1 {\\r
+ { PIO_GROUP_D, PIO_PD2A_URXD1, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD3A_UTXD1, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+/* UART1 IOSET 2 */\r
+#define PINS_UART1_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC7E_URXD1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC8E_UTXD1, PIO_PERIPH_E, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for UART2 peripheral ========== */\r
+\r
+/* UART2 IOSET 1 */\r
+#define PINS_UART2_IOS1 {\\r
+ { PIO_GROUP_D, PIO_PD4B_URXD2, PIO_PERIPH_B, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD5B_UTXD2, PIO_PERIPH_B, PIO_DEFAULT },\\r
+}\r
+\r
+/* UART2 IOSET 2 */\r
+#define PINS_UART2_IOS2 {\\r
+ { PIO_GROUP_D, PIO_PD23A_URXD2, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD24A_UTXD2, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+/* UART2 IOSET 3 */\r
+#define PINS_UART2_IOS3 {\\r
+ { PIO_GROUP_D, PIO_PD19C_URXD2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD20C_UTXD2, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for UART3 peripheral ========== */\r
+\r
+/* UART3 IOSET 1 */\r
+#define PINS_UART3_IOS1 {\\r
+ { PIO_GROUP_C, PIO_PC12D_URXD3, PIO_PERIPH_D, PIO_DEFAULT },\\r
+ { PIO_GROUP_C, PIO_PC13D_UTXD3, PIO_PERIPH_D, PIO_DEFAULT },\\r
+}\r
+\r
+/* UART3 IOSET 2 */\r
+#define PINS_UART3_IOS2 {\\r
+ { PIO_GROUP_C, PIO_PC31C_URXD3, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_D, PIO_PD0C_UTXD3, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* UART3 IOSET 3 */\r
+#define PINS_UART3_IOS3 {\\r
+ { PIO_GROUP_B, PIO_PB11C_URXD3, PIO_PERIPH_C, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB12C_UTXD3, PIO_PERIPH_C, PIO_DEFAULT },\\r
+}\r
+\r
+/* ========== Pio PIN definition for UART4 peripheral ========== */\r
+\r
+/* UART4 IOSET 1 */\r
+#define PINS_UART4_IOS1 {\\r
+ { PIO_GROUP_B, PIO_PB3A_URXD4, PIO_PERIPH_A, PIO_DEFAULT },\\r
+ { PIO_GROUP_B, PIO_PB4A_UTXD4, PIO_PERIPH_A, PIO_DEFAULT },\\r
+}\r
+\r
+//=============================================================================\r
+\r
+#endif /* _CHIP_PINS_H_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_ACC_COMPONENT_\r
+#define _SAMA5D2_ACC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_ACC Analog Comparator Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Acc hardware registers */\r
+typedef struct {\r
+ __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */\r
+ __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */\r
+ __I uint32_t Reserved1[7];\r
+ __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */\r
+ __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */\r
+ __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */\r
+ __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */\r
+ __I uint32_t Reserved2[24];\r
+ __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */\r
+ __I uint32_t Reserved3[19];\r
+ __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */\r
+} Acc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */\r
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */\r
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */\r
+#define ACC_MR_SELMINUS_Pos 0\r
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */\r
+#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)))\r
+#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */\r
+#define ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */\r
+#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */\r
+#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */\r
+#define ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */\r
+#define ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */\r
+#define ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */\r
+#define ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */\r
+#define ACC_MR_SELPLUS_Pos 4\r
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */\r
+#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)))\r
+#define ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */\r
+#define ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */\r
+#define ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */\r
+#define ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */\r
+#define ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */\r
+#define ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */\r
+#define ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */\r
+#define ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */\r
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */\r
+#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */\r
+#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */\r
+#define ACC_MR_EDGETYP_Pos 9\r
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */\r
+#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)))\r
+#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */\r
+#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */\r
+#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */\r
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */\r
+#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */\r
+#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */\r
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */\r
+#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */\r
+#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */\r
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */\r
+#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */\r
+#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */\r
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */\r
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */\r
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */\r
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */\r
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */\r
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */\r
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */\r
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */\r
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */\r
+#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */\r
+#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */\r
+#define ACC_ACR_HYST_Pos 1\r
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */\r
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))\r
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */\r
+#define ACC_WPMR_WPKEY_Pos 8\r
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */\r
+#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))\r
+#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */\r
+#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D2_ACC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_ADC_COMPONENT_\r
+#define _SAMA5D2_ADC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog-to-Digital Converter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_ADC Analog-to-Digital Converter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Adc hardware registers */\r
+typedef struct {\r
+ __O uint32_t ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */\r
+ __IO uint32_t ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */\r
+ __IO uint32_t ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */\r
+ __IO uint32_t ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */\r
+ __O uint32_t ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */\r
+ __O uint32_t ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */\r
+ __I uint32_t ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */\r
+ __I uint32_t Reserved1[1];\r
+ __I uint32_t ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */\r
+ __O uint32_t ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */\r
+ __O uint32_t ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */\r
+ __I uint32_t ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */\r
+ __I uint32_t ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */\r
+ __IO uint32_t ADC_LCTMR; /**< \brief (Adc Offset: 0x34) Last Channel Trigger Mode Register */\r
+ __IO uint32_t ADC_LCCWR; /**< \brief (Adc Offset: 0x38) Last Channel Compare Window Register */\r
+ __I uint32_t ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */\r
+ __IO uint32_t ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */\r
+ __IO uint32_t ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */\r
+ __IO uint32_t ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */\r
+ __IO uint32_t ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */\r
+ __I uint32_t ADC_CDR[12]; /**< \brief (Adc Offset: 0x50) Channel Data Registers */\r
+ __I uint32_t Reserved2[5];\r
+ __IO uint32_t ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */\r
+ __I uint32_t Reserved3[6];\r
+ __IO uint32_t ADC_TSMR; /**< \brief (Adc Offset: 0xB0) Touchscreen Mode Register */\r
+ __I uint32_t ADC_XPOSR; /**< \brief (Adc Offset: 0xB4) Touchscreen X Position Register */\r
+ __I uint32_t ADC_YPOSR; /**< \brief (Adc Offset: 0xB8) Touchscreen Y Position Register */\r
+ __I uint32_t ADC_PRESSR; /**< \brief (Adc Offset: 0xBC) Touchscreen Pressure Register */\r
+ __IO uint32_t ADC_TRGR; /**< \brief (Adc Offset: 0xC0) Trigger Register */\r
+ __I uint32_t Reserved4[3];\r
+ __IO uint32_t ADC_COSR; /**< \brief (Adc Offset: 0xD0) Correction Select Register */\r
+ __IO uint32_t ADC_CVR; /**< \brief (Adc Offset: 0xD4) Correction Values Register */\r
+ __IO uint32_t ADC_CECR; /**< \brief (Adc Offset: 0xD8) Channel Error Correction Register */\r
+ __I uint32_t Reserved5[2];\r
+ __IO uint32_t ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved6[4];\r
+ __I uint32_t ADC_VERSION; /**< \brief (Adc Offset: 0xFC) Version Register */\r
+} Adc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */\r
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */\r
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */\r
+#define ADC_CR_TSCALIB (0x1u << 2) /**< \brief (ADC_CR) Touchscreen Calibration */\r
+#define ADC_CR_CMPRST (0x1u << 4) /**< \brief (ADC_CR) Comparison Restart */\r
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */\r
+#define ADC_MR_TRGSEL_Pos 1\r
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */\r
+#define ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos)))\r
+#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) ADTRG */\r
+#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA0 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA1 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA2 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM event line 0 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM_even line 1 */\r
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */\r
+#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions. */\r
+#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The wake-up time can be modified by programming FWUP bit. */\r
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */\r
+#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) If SLEEP is 1, then both ADC core and reference voltage circuitry are OFF between conversions */\r
+#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) If SLEEP is 1, then Fast Wake-up Sleep mode: The voltage reference is ON between conversions and ADC core is OFF */\r
+#define ADC_MR_PRESCAL_Pos 8\r
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */\r
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))\r
+#define ADC_MR_STARTUP_Pos 16\r
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Startup Time */\r
+#define ADC_MR_STARTUP(value) ((ADC_MR_STARTUP_Msk & ((value) << ADC_MR_STARTUP_Pos)))\r
+#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCCLK */\r
+#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCCLK */\r
+#define ADC_MR_SETTLING_Pos 20\r
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */\r
+#define ADC_MR_SETTLING(value) ((ADC_MR_SETTLING_Msk & ((value) << ADC_MR_SETTLING_Pos)))\r
+#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCCLK */\r
+#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCCLK */\r
+#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCCLK */\r
+#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCCLK */\r
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */\r
+#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels. */\r
+#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR registers. */\r
+#define ADC_MR_TRACKTIM_Pos 24\r
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */\r
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))\r
+#define ADC_MR_TRANSFER_Pos 28\r
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Hold Time */\r
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))\r
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */\r
+#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. */\r
+#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert the same channel several times. */\r
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */\r
+#define ADC_SEQR1_USCH1_Pos 0\r
+#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */\r
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))\r
+#define ADC_SEQR1_USCH2_Pos 4\r
+#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */\r
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))\r
+#define ADC_SEQR1_USCH3_Pos 8\r
+#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */\r
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))\r
+#define ADC_SEQR1_USCH4_Pos 12\r
+#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */\r
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))\r
+#define ADC_SEQR1_USCH5_Pos 16\r
+#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */\r
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))\r
+#define ADC_SEQR1_USCH6_Pos 20\r
+#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */\r
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))\r
+#define ADC_SEQR1_USCH7_Pos 24\r
+#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */\r
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))\r
+#define ADC_SEQR1_USCH8_Pos 28\r
+#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */\r
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))\r
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */\r
+#define ADC_SEQR2_USCH9_Pos 0\r
+#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */\r
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))\r
+#define ADC_SEQR2_USCH10_Pos 4\r
+#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */\r
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))\r
+#define ADC_SEQR2_USCH11_Pos 8\r
+#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */\r
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))\r
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */\r
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */\r
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */\r
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */\r
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */\r
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */\r
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */\r
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */\r
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */\r
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */\r
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */\r
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */\r
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */\r
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */\r
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */\r
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */\r
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */\r
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */\r
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */\r
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */\r
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */\r
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */\r
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */\r
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */\r
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */\r
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */\r
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */\r
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */\r
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */\r
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */\r
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */\r
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */\r
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */\r
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */\r
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */\r
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */\r
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */\r
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */\r
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */\r
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */\r
+#define ADC_LCDR_LDATA_Pos 0\r
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */\r
+#define ADC_LCDR_CHNB_Pos 12\r
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */\r
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */\r
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */\r
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */\r
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */\r
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */\r
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */\r
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */\r
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */\r
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */\r
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */\r
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */\r
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */\r
+#define ADC_IER_VALUE_ (0x1u << 12) /**< \brief (ADC_IER) */\r
+#define ADC_IER_LCCHG (0x1u << 19) /**< \brief (ADC_IER) Last Channel Change Interrupt Enable */\r
+#define ADC_IER_XRDY (0x1u << 20) /**< \brief (ADC_IER) Touchscreen Measure XPOS Ready Interrupt Enable */\r
+#define ADC_IER_YRDY (0x1u << 21) /**< \brief (ADC_IER) Touchscreen Measure YPOS Ready Interrupt Enable */\r
+#define ADC_IER_PRDY (0x1u << 22) /**< \brief (ADC_IER) Touchscreen Measure Pressure Ready Interrupt Enable */\r
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */\r
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */\r
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */\r
+#define ADC_IER_PEN (0x1u << 29) /**< \brief (ADC_IER) Pen Contact Interrupt Enable */\r
+#define ADC_IER_NOPEN (0x1u << 30) /**< \brief (ADC_IER) No Pen Contact Interrupt Enable */\r
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */\r
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */\r
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */\r
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */\r
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */\r
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */\r
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */\r
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */\r
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */\r
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */\r
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */\r
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */\r
+#define ADC_IDR_VALUE_ (0x1u << 12) /**< \brief (ADC_IDR) */\r
+#define ADC_IDR_LCCHG (0x1u << 19) /**< \brief (ADC_IDR) Last Channel Change Interrupt Disable */\r
+#define ADC_IDR_XRDY (0x1u << 20) /**< \brief (ADC_IDR) Touchscreen Measure XPOS Ready Interrupt Disable */\r
+#define ADC_IDR_YRDY (0x1u << 21) /**< \brief (ADC_IDR) Touchscreen Measure YPOS Ready Interrupt Disable */\r
+#define ADC_IDR_PRDY (0x1u << 22) /**< \brief (ADC_IDR) Touchscreen Measure Pressure Ready Interrupt Disable */\r
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */\r
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */\r
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */\r
+#define ADC_IDR_PEN (0x1u << 29) /**< \brief (ADC_IDR) Pen Contact Interrupt Disable */\r
+#define ADC_IDR_NOPEN (0x1u << 30) /**< \brief (ADC_IDR) No Pen Contact Interrupt Disable */\r
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */\r
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */\r
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */\r
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */\r
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */\r
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */\r
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */\r
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */\r
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */\r
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */\r
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */\r
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */\r
+#define ADC_IMR_VALUE_ (0x1u << 12) /**< \brief (ADC_IMR) */\r
+#define ADC_IMR_LCCHG (0x1u << 19) /**< \brief (ADC_IMR) Last Channel Change Interrupt Mask */\r
+#define ADC_IMR_XRDY (0x1u << 20) /**< \brief (ADC_IMR) Touchscreen Measure XPOS Ready Interrupt Mask */\r
+#define ADC_IMR_YRDY (0x1u << 21) /**< \brief (ADC_IMR) Touchscreen Measure YPOS Ready Interrupt Mask */\r
+#define ADC_IMR_PRDY (0x1u << 22) /**< \brief (ADC_IMR) Touchscreen Measure Pressure Ready Interrupt Mask */\r
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */\r
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */\r
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */\r
+#define ADC_IMR_PEN (0x1u << 29) /**< \brief (ADC_IMR) Pen Contact Interrupt Mask */\r
+#define ADC_IMR_NOPEN (0x1u << 30) /**< \brief (ADC_IMR) No Pen Contact Interrupt Mask */\r
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */\r
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 (automatically set / cleared) */\r
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 (automatically set / cleared) */\r
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 (automatically set / cleared) */\r
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 (automatically set / cleared) */\r
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 (automatically set / cleared) */\r
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 (automatically set / cleared) */\r
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 (automatically set / cleared) */\r
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 (automatically set / cleared) */\r
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 (automatically set / cleared) */\r
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 (automatically set / cleared) */\r
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 (automatically set / cleared) */\r
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 (automatically set / cleared) */\r
+#define ADC_ISR_VALUE_ (0x1u << 12) /**< \brief (ADC_ISR) */\r
+#define ADC_ISR_LCCHG (0x1u << 19) /**< \brief (ADC_ISR) Last Channel Change (cleared on read) */\r
+#define ADC_ISR_XRDY (0x1u << 20) /**< \brief (ADC_ISR) Touchscreen XPOS Measure Ready (cleared on read) */\r
+#define ADC_ISR_YRDY (0x1u << 21) /**< \brief (ADC_ISR) Touchscreen YPOS Measure Ready (cleared on read) */\r
+#define ADC_ISR_PRDY (0x1u << 22) /**< \brief (ADC_ISR) Touchscreen Pressure Measure Ready (cleared on read) */\r
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready (automatically set / cleared) */\r
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error (cleared on read) */\r
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Event (cleared on read) */\r
+#define ADC_ISR_PEN (0x1u << 29) /**< \brief (ADC_ISR) Pen contact (cleared on read) */\r
+#define ADC_ISR_NOPEN (0x1u << 30) /**< \brief (ADC_ISR) No Pen Contact (cleared on read) */\r
+#define ADC_ISR_PENS (0x1u << 31) /**< \brief (ADC_ISR) Pen Detect Status */\r
+/* -------- ADC_LCTMR : (ADC Offset: 0x34) Last Channel Trigger Mode Register -------- */\r
+#define ADC_LCTMR_DUALTRIG (0x1u << 0) /**< \brief (ADC_LCTMR) Dual Trigger ON */\r
+#define ADC_LCTMR_CMPMOD_Pos 4\r
+#define ADC_LCTMR_CMPMOD_Msk (0x3u << ADC_LCTMR_CMPMOD_Pos) /**< \brief (ADC_LCTMR) Last Channel Comparison Mode */\r
+#define ADC_LCTMR_CMPMOD(value) ((ADC_LCTMR_CMPMOD_Msk & ((value) << ADC_LCTMR_CMPMOD_Pos)))\r
+#define ADC_LCTMR_CMPMOD_LOW (0x0u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is lower than the low threshold of the window. */\r
+#define ADC_LCTMR_CMPMOD_HIGH (0x1u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is higher than the high threshold of the window. */\r
+#define ADC_LCTMR_CMPMOD_IN (0x2u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is in the comparison window. */\r
+#define ADC_LCTMR_CMPMOD_OUT (0x3u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is out of the comparison window. */\r
+/* -------- ADC_LCCWR : (ADC Offset: 0x38) Last Channel Compare Window Register -------- */\r
+#define ADC_LCCWR_LOWTHRES_Pos 0\r
+#define ADC_LCCWR_LOWTHRES_Msk (0xfffu << ADC_LCCWR_LOWTHRES_Pos) /**< \brief (ADC_LCCWR) Low Threshold */\r
+#define ADC_LCCWR_LOWTHRES(value) ((ADC_LCCWR_LOWTHRES_Msk & ((value) << ADC_LCCWR_LOWTHRES_Pos)))\r
+#define ADC_LCCWR_HIGHTHRES_Pos 16\r
+#define ADC_LCCWR_HIGHTHRES_Msk (0xfffu << ADC_LCCWR_HIGHTHRES_Pos) /**< \brief (ADC_LCCWR) High Threshold */\r
+#define ADC_LCCWR_HIGHTHRES(value) ((ADC_LCCWR_HIGHTHRES_Msk & ((value) << ADC_LCCWR_HIGHTHRES_Pos)))\r
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */\r
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */\r
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */\r
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */\r
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */\r
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */\r
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */\r
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */\r
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */\r
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */\r
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */\r
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */\r
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */\r
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */\r
+#define ADC_EMR_CMPMODE_Pos 0\r
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */\r
+#define ADC_EMR_CMPMODE(value) ((ADC_EMR_CMPMODE_Msk & ((value) << ADC_EMR_CMPMODE_Pos)))\r
+#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */\r
+#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */\r
+#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */\r
+#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */\r
+#define ADC_EMR_CMPTYPE (0x1u << 2) /**< \brief (ADC_EMR) Comparison Type */\r
+#define ADC_EMR_CMPTYPE_FLAG_ONLY (0x0u << 2) /**< \brief (ADC_EMR) Any conversion is performed and comparison function drives the COMPE flag. */\r
+#define ADC_EMR_CMPTYPE_START_CONDITION (0x1u << 2) /**< \brief (ADC_EMR) Comparison conditions must be met to start the storage of all conversions until the CMPRST bit is set. */\r
+#define ADC_EMR_CMPSEL_Pos 4\r
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */\r
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))\r
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */\r
+#define ADC_EMR_CMPFILTER_Pos 12\r
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */\r
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))\r
+#define ADC_EMR_SRCCLK (0x1u << 21) /**< \brief (ADC_EMR) External Clock Selection */\r
+#define ADC_EMR_SRCCLK_PERIPH_CLK (0x0u << 21) /**< \brief (ADC_EMR) The peripheral clock is the source for the ADC prescaler. */\r
+#define ADC_EMR_SRCCLK_PMC_PCK (0x1u << 21) /**< \brief (ADC_EMR) PMC PCKx is the source clock for the ADC prescaler, thus the ADC clock can be independent of the core/peripheral clock. */\r
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) Tag of the ADC_LCDR */\r
+#define ADC_EMR_ADCMODE_Pos 28\r
+#define ADC_EMR_ADCMODE_Msk (0x3u << ADC_EMR_ADCMODE_Pos) /**< \brief (ADC_EMR) ADC Running Mode */\r
+#define ADC_EMR_ADCMODE(value) ((ADC_EMR_ADCMODE_Msk & ((value) << ADC_EMR_ADCMODE_Pos)))\r
+#define ADC_EMR_ADCMODE_NORMAL (0x0u << 28) /**< \brief (ADC_EMR) Normal mode of operation. */\r
+#define ADC_EMR_ADCMODE_OFFSET_ERROR (0x1u << 28) /**< \brief (ADC_EMR) Offset Error mode to measure the offset error. See Table 1-8. */\r
+#define ADC_EMR_ADCMODE_GAIN_ERROR_HIGH (0x2u << 28) /**< \brief (ADC_EMR) Gain Error mode to measure the gain error. See Table 1-8. */\r
+#define ADC_EMR_ADCMODE_GAIN_ERROR_LOW (0x3u << 28) /**< \brief (ADC_EMR) Gain Error mode to measure the gain error. See Table 1-8. */\r
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */\r
+#define ADC_CWR_LOWTHRES_Pos 0\r
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */\r
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))\r
+#define ADC_CWR_HIGHTHRES_Pos 16\r
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */\r
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))\r
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */\r
+#define ADC_CGR_GAIN0_Pos 0\r
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for Channel 0 */\r
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))\r
+#define ADC_CGR_GAIN0_SE1_DIFF0_5 (0x0u << 0) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN0_SE1_DIFF1 (0x1u << 0) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN0_SE2_DIFF2 (0x2u << 0) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN0_SE4_DIFF2 (0x3u << 0) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN1_Pos 2\r
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for Channel 1 */\r
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))\r
+#define ADC_CGR_GAIN1_SE1_DIFF0_5 (0x0u << 2) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN1_SE1_DIFF1 (0x1u << 2) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN1_SE2_DIFF2 (0x2u << 2) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN1_SE4_DIFF2 (0x3u << 2) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN2_Pos 4\r
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for Channel 2 */\r
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))\r
+#define ADC_CGR_GAIN2_SE1_DIFF0_5 (0x0u << 4) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN2_SE1_DIFF1 (0x1u << 4) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN2_SE2_DIFF2 (0x2u << 4) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN2_SE4_DIFF2 (0x3u << 4) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN3_Pos 6\r
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for Channel 3 */\r
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))\r
+#define ADC_CGR_GAIN3_SE1_DIFF0_5 (0x0u << 6) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN3_SE1_DIFF1 (0x1u << 6) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN3_SE2_DIFF2 (0x2u << 6) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN3_SE4_DIFF2 (0x3u << 6) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN4_Pos 8\r
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for Channel 4 */\r
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))\r
+#define ADC_CGR_GAIN4_SE1_DIFF0_5 (0x0u << 8) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN4_SE1_DIFF1 (0x1u << 8) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN4_SE2_DIFF2 (0x2u << 8) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN4_SE4_DIFF2 (0x3u << 8) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN5_Pos 10\r
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for Channel 5 */\r
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))\r
+#define ADC_CGR_GAIN5_SE1_DIFF0_5 (0x0u << 10) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN5_SE1_DIFF1 (0x1u << 10) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN5_SE2_DIFF2 (0x2u << 10) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN5_SE4_DIFF2 (0x3u << 10) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN6_Pos 12\r
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for Channel 6 */\r
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))\r
+#define ADC_CGR_GAIN6_SE1_DIFF0_5 (0x0u << 12) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN6_SE1_DIFF1 (0x1u << 12) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN6_SE2_DIFF2 (0x2u << 12) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN6_SE4_DIFF2 (0x3u << 12) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN7_Pos 14\r
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for Channel 7 */\r
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))\r
+#define ADC_CGR_GAIN7_SE1_DIFF0_5 (0x0u << 14) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN7_SE1_DIFF1 (0x1u << 14) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN7_SE2_DIFF2 (0x2u << 14) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN7_SE4_DIFF2 (0x3u << 14) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN8_Pos 16\r
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for Channel 8 */\r
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))\r
+#define ADC_CGR_GAIN8_SE1_DIFF0_5 (0x0u << 16) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN8_SE1_DIFF1 (0x1u << 16) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN8_SE2_DIFF2 (0x2u << 16) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN8_SE4_DIFF2 (0x3u << 16) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN9_Pos 18\r
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for Channel 9 */\r
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))\r
+#define ADC_CGR_GAIN9_SE1_DIFF0_5 (0x0u << 18) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN9_SE1_DIFF1 (0x1u << 18) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN9_SE2_DIFF2 (0x2u << 18) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN9_SE4_DIFF2 (0x3u << 18) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN10_Pos 20\r
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for Channel 10 */\r
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))\r
+#define ADC_CGR_GAIN10_SE1_DIFF0_5 (0x0u << 20) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN10_SE1_DIFF1 (0x1u << 20) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN10_SE2_DIFF2 (0x2u << 20) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN10_SE4_DIFF2 (0x3u << 20) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN11_Pos 22\r
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for Channel 11 */\r
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))\r
+#define ADC_CGR_GAIN11_SE1_DIFF0_5 (0x0u << 22) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN11_SE1_DIFF1 (0x1u << 22) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN11_SE2_DIFF2 (0x2u << 22) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+#define ADC_CGR_GAIN11_SE4_DIFF2 (0x3u << 22) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */\r
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */\r
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for Channel 0 */\r
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for Channel 1 */\r
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for Channel 2 */\r
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for Channel 3 */\r
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for Channel 4 */\r
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for Channel 5 */\r
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for Channel 6 */\r
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for Channel 7 */\r
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for Channel 8 */\r
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for Channel 9 */\r
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for Channel 10 */\r
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for Channel 11 */\r
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential Inputs for Channel 0 */\r
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential Inputs for Channel 1 */\r
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential Inputs for Channel 2 */\r
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential Inputs for Channel 3 */\r
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential Inputs for Channel 4 */\r
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential Inputs for Channel 5 */\r
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential Inputs for Channel 6 */\r
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential Inputs for Channel 7 */\r
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential Inputs for Channel 8 */\r
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential Inputs for Channel 9 */\r
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential Inputs for Channel 10 */\r
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential Inputs for Channel 11 */\r
+/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */\r
+#define ADC_CDR0_DATA_Pos 0\r
+#define ADC_CDR0_DATA_Msk (0xfffu << ADC_CDR0_DATA_Pos) /**< \brief (ADC_CDR0) Converted Data */\r
+/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */\r
+#define ADC_CDR1_DATA_Pos 0\r
+#define ADC_CDR1_DATA_Msk (0xfffu << ADC_CDR1_DATA_Pos) /**< \brief (ADC_CDR1) Converted Data */\r
+/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */\r
+#define ADC_CDR2_DATA_Pos 0\r
+#define ADC_CDR2_DATA_Msk (0xfffu << ADC_CDR2_DATA_Pos) /**< \brief (ADC_CDR2) Converted Data */\r
+/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */\r
+#define ADC_CDR3_DATA_Pos 0\r
+#define ADC_CDR3_DATA_Msk (0xfffu << ADC_CDR3_DATA_Pos) /**< \brief (ADC_CDR3) Converted Data */\r
+/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */\r
+#define ADC_CDR4_DATA_Pos 0\r
+#define ADC_CDR4_DATA_Msk (0xfffu << ADC_CDR4_DATA_Pos) /**< \brief (ADC_CDR4) Converted Data */\r
+/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */\r
+#define ADC_CDR5_DATA_Pos 0\r
+#define ADC_CDR5_DATA_Msk (0xfffu << ADC_CDR5_DATA_Pos) /**< \brief (ADC_CDR5) Converted Data */\r
+/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */\r
+#define ADC_CDR6_DATA_Pos 0\r
+#define ADC_CDR6_DATA_Msk (0xfffu << ADC_CDR6_DATA_Pos) /**< \brief (ADC_CDR6) Converted Data */\r
+/* -------- ADC_CDR7 : (ADC Offset: 0x6C) Channel Data Register 7 -------- */\r
+#define ADC_CDR7_DATA_Pos 0\r
+#define ADC_CDR7_DATA_Msk (0xfffu << ADC_CDR7_DATA_Pos) /**< \brief (ADC_CDR7) Converted Data */\r
+/* -------- ADC_CDR8 : (ADC Offset: 0x70) Channel Data Register 8 -------- */\r
+#define ADC_CDR8_DATA_Pos 0\r
+#define ADC_CDR8_DATA_Msk (0xfffu << ADC_CDR8_DATA_Pos) /**< \brief (ADC_CDR8) Converted Data */\r
+/* -------- ADC_CDR9 : (ADC Offset: 0x74) Channel Data Register 9 -------- */\r
+#define ADC_CDR9_DATA_Pos 0\r
+#define ADC_CDR9_DATA_Msk (0xfffu << ADC_CDR9_DATA_Pos) /**< \brief (ADC_CDR9) Converted Data */\r
+/* -------- ADC_CDR10 : (ADC Offset: 0x78) Channel Data Register 10 -------- */\r
+#define ADC_CDR10_DATA_Pos 0\r
+#define ADC_CDR10_DATA_Msk (0xfffu << ADC_CDR10_DATA_Pos) /**< \brief (ADC_CDR10) Converted Data */\r
+/* -------- ADC_CDR11 : (ADC Offset: 0x7C) Channel Data Register 11 -------- */\r
+#define ADC_CDR11_DATA_Pos 0\r
+#define ADC_CDR11_DATA_Msk (0xfffu << ADC_CDR11_DATA_Pos) /**< \brief (ADC_CDR11) Converted Data */\r
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */\r
+#define ADC_ACR_PENDETSENS_Pos 0\r
+#define ADC_ACR_PENDETSENS_Msk (0x3u << ADC_ACR_PENDETSENS_Pos) /**< \brief (ADC_ACR) Pen Detection Sensitivity */\r
+#define ADC_ACR_PENDETSENS(value) ((ADC_ACR_PENDETSENS_Msk & ((value) << ADC_ACR_PENDETSENS_Pos)))\r
+/* -------- ADC_TSMR : (ADC Offset: 0xB0) Touchscreen Mode Register -------- */\r
+#define ADC_TSMR_TSMODE_Pos 0\r
+#define ADC_TSMR_TSMODE_Msk (0x3u << ADC_TSMR_TSMODE_Pos) /**< \brief (ADC_TSMR) Touchscreen Mode */\r
+#define ADC_TSMR_TSMODE(value) ((ADC_TSMR_TSMODE_Msk & ((value) << ADC_TSMR_TSMODE_Pos)))\r
+#define ADC_TSMR_TSMODE_NONE (0x0u << 0) /**< \brief (ADC_TSMR) No Touchscreen */\r
+#define ADC_TSMR_TSMODE_4_WIRE_NO_PM (0x1u << 0) /**< \brief (ADC_TSMR) 4-wire Touchscreen without pressure measurement */\r
+#define ADC_TSMR_TSMODE_4_WIRE (0x2u << 0) /**< \brief (ADC_TSMR) 4-wire Touchscreen with pressure measurement */\r
+#define ADC_TSMR_TSMODE_5_WIRE (0x3u << 0) /**< \brief (ADC_TSMR) 5-wire Touchscreen */\r
+#define ADC_TSMR_TSAV_Pos 4\r
+#define ADC_TSMR_TSAV_Msk (0x3u << ADC_TSMR_TSAV_Pos) /**< \brief (ADC_TSMR) Touchscreen Average */\r
+#define ADC_TSMR_TSAV(value) ((ADC_TSMR_TSAV_Msk & ((value) << ADC_TSMR_TSAV_Pos)))\r
+#define ADC_TSMR_TSAV_NO_FILTER (0x0u << 4) /**< \brief (ADC_TSMR) No Filtering. Only one ADC conversion per measure */\r
+#define ADC_TSMR_TSAV_AVG2CONV (0x1u << 4) /**< \brief (ADC_TSMR) Averages 2 ADC conversions */\r
+#define ADC_TSMR_TSAV_AVG4CONV (0x2u << 4) /**< \brief (ADC_TSMR) Averages 4 ADC conversions */\r
+#define ADC_TSMR_TSAV_AVG8CONV (0x3u << 4) /**< \brief (ADC_TSMR) Averages 8 ADC conversions */\r
+#define ADC_TSMR_TSFREQ_Pos 8\r
+#define ADC_TSMR_TSFREQ_Msk (0xfu << ADC_TSMR_TSFREQ_Pos) /**< \brief (ADC_TSMR) Touchscreen Frequency */\r
+#define ADC_TSMR_TSFREQ(value) ((ADC_TSMR_TSFREQ_Msk & ((value) << ADC_TSMR_TSFREQ_Pos)))\r
+#define ADC_TSMR_TSSCTIM_Pos 16\r
+#define ADC_TSMR_TSSCTIM_Msk (0xfu << ADC_TSMR_TSSCTIM_Pos) /**< \brief (ADC_TSMR) Touchscreen Switches Closure Time */\r
+#define ADC_TSMR_TSSCTIM(value) ((ADC_TSMR_TSSCTIM_Msk & ((value) << ADC_TSMR_TSSCTIM_Pos)))\r
+#define ADC_TSMR_NOTSDMA (0x1u << 22) /**< \brief (ADC_TSMR) No TouchScreen DMA */\r
+#define ADC_TSMR_PENDET (0x1u << 24) /**< \brief (ADC_TSMR) Pen Contact Detection Enable */\r
+#define ADC_TSMR_PENDBC_Pos 28\r
+#define ADC_TSMR_PENDBC_Msk (0xfu << ADC_TSMR_PENDBC_Pos) /**< \brief (ADC_TSMR) Pen Detect Debouncing Period */\r
+#define ADC_TSMR_PENDBC(value) ((ADC_TSMR_PENDBC_Msk & ((value) << ADC_TSMR_PENDBC_Pos)))\r
+/* -------- ADC_XPOSR : (ADC Offset: 0xB4) Touchscreen X Position Register -------- */\r
+#define ADC_XPOSR_XPOS_Pos 0\r
+#define ADC_XPOSR_XPOS_Msk (0xfffu << ADC_XPOSR_XPOS_Pos) /**< \brief (ADC_XPOSR) X Position */\r
+#define ADC_XPOSR_XSCALE_Pos 16\r
+#define ADC_XPOSR_XSCALE_Msk (0xfffu << ADC_XPOSR_XSCALE_Pos) /**< \brief (ADC_XPOSR) Scale of XPOS */\r
+/* -------- ADC_YPOSR : (ADC Offset: 0xB8) Touchscreen Y Position Register -------- */\r
+#define ADC_YPOSR_YPOS_Pos 0\r
+#define ADC_YPOSR_YPOS_Msk (0xfffu << ADC_YPOSR_YPOS_Pos) /**< \brief (ADC_YPOSR) Y Position */\r
+#define ADC_YPOSR_YSCALE_Pos 16\r
+#define ADC_YPOSR_YSCALE_Msk (0xfffu << ADC_YPOSR_YSCALE_Pos) /**< \brief (ADC_YPOSR) Scale of YPOS */\r
+/* -------- ADC_PRESSR : (ADC Offset: 0xBC) Touchscreen Pressure Register -------- */\r
+#define ADC_PRESSR_Z1_Pos 0\r
+#define ADC_PRESSR_Z1_Msk (0xfffu << ADC_PRESSR_Z1_Pos) /**< \brief (ADC_PRESSR) Data of Z1 Measurement */\r
+#define ADC_PRESSR_Z2_Pos 16\r
+#define ADC_PRESSR_Z2_Msk (0xfffu << ADC_PRESSR_Z2_Pos) /**< \brief (ADC_PRESSR) Data of Z2 Measurement */\r
+/* -------- ADC_TRGR : (ADC Offset: 0xC0) Trigger Register -------- */\r
+#define ADC_TRGR_TRGMOD_Pos 0\r
+#define ADC_TRGR_TRGMOD_Msk (0x7u << ADC_TRGR_TRGMOD_Pos) /**< \brief (ADC_TRGR) Trigger Mode */\r
+#define ADC_TRGR_TRGMOD(value) ((ADC_TRGR_TRGMOD_Msk & ((value) << ADC_TRGR_TRGMOD_Pos)))\r
+#define ADC_TRGR_TRGMOD_NO_TRIGGER (0x0u << 0) /**< \brief (ADC_TRGR) No trigger, only software trigger can start conversions */\r
+#define ADC_TRGR_TRGMOD_EXT_TRIG_RISE (0x1u << 0) /**< \brief (ADC_TRGR) External trigger rising edge */\r
+#define ADC_TRGR_TRGMOD_EXT_TRIG_FALL (0x2u << 0) /**< \brief (ADC_TRGR) External trigger falling edge */\r
+#define ADC_TRGR_TRGMOD_EXT_TRIG_ANY (0x3u << 0) /**< \brief (ADC_TRGR) External trigger any edge */\r
+#define ADC_TRGR_TRGMOD_PEN_TRIG (0x4u << 0) /**< \brief (ADC_TRGR) Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode) */\r
+#define ADC_TRGR_TRGMOD_PERIOD_TRIG (0x5u << 0) /**< \brief (ADC_TRGR) ADC internal periodic trigger (see field TRGPER) */\r
+#define ADC_TRGR_TRGMOD_CONTINUOUS (0x6u << 0) /**< \brief (ADC_TRGR) Continuous Mode */\r
+#define ADC_TRGR_TRGPER_Pos 16\r
+#define ADC_TRGR_TRGPER_Msk (0xffffu << ADC_TRGR_TRGPER_Pos) /**< \brief (ADC_TRGR) Trigger Period */\r
+#define ADC_TRGR_TRGPER(value) ((ADC_TRGR_TRGPER_Msk & ((value) << ADC_TRGR_TRGPER_Pos)))\r
+/* -------- ADC_COSR : (ADC Offset: 0xD0) Correction Select Register -------- */\r
+#define ADC_COSR_CSEL_Pos 0\r
+#define ADC_COSR_CSEL_Msk (0x1fu << ADC_COSR_CSEL_Pos) /**< \brief (ADC_COSR) CORRECTION_TYPE Correction Select */\r
+#define ADC_COSR_CSEL(value) ((ADC_COSR_CSEL_Msk & ((value) << ADC_COSR_CSEL_Pos)))\r
+/* -------- ADC_CVR : (ADC Offset: 0xD4) Correction Values Register -------- */\r
+#define ADC_CVR_OFFSETCORR_Pos 0\r
+#define ADC_CVR_OFFSETCORR_Msk (0xffffu << ADC_CVR_OFFSETCORR_Pos) /**< \brief (ADC_CVR) Offset Correction */\r
+#define ADC_CVR_OFFSETCORR(value) ((ADC_CVR_OFFSETCORR_Msk & ((value) << ADC_CVR_OFFSETCORR_Pos)))\r
+#define ADC_CVR_GAINCORR_Pos 16\r
+#define ADC_CVR_GAINCORR_Msk (0xffffu << ADC_CVR_GAINCORR_Pos) /**< \brief (ADC_CVR) Gain Correction */\r
+#define ADC_CVR_GAINCORR(value) ((ADC_CVR_GAINCORR_Msk & ((value) << ADC_CVR_GAINCORR_Pos)))\r
+/* -------- ADC_CECR : (ADC Offset: 0xD8) Channel Error Correction Register -------- */\r
+#define ADC_CECR_ECORR0 (0x1u << 0) /**< \brief (ADC_CECR) Error Correction Enable for channel 0 */\r
+#define ADC_CECR_ECORR1 (0x1u << 1) /**< \brief (ADC_CECR) Error Correction Enable for channel 1 */\r
+#define ADC_CECR_ECORR2 (0x1u << 2) /**< \brief (ADC_CECR) Error Correction Enable for channel 2 */\r
+#define ADC_CECR_ECORR3 (0x1u << 3) /**< \brief (ADC_CECR) Error Correction Enable for channel 3 */\r
+#define ADC_CECR_ECORR4 (0x1u << 4) /**< \brief (ADC_CECR) Error Correction Enable for channel 4 */\r
+#define ADC_CECR_ECORR5 (0x1u << 5) /**< \brief (ADC_CECR) Error Correction Enable for channel 5 */\r
+#define ADC_CECR_ECORR6 (0x1u << 6) /**< \brief (ADC_CECR) Error Correction Enable for channel 6 */\r
+#define ADC_CECR_ECORR7 (0x1u << 7) /**< \brief (ADC_CECR) Error Correction Enable for channel 7 */\r
+#define ADC_CECR_ECORR8 (0x1u << 8) /**< \brief (ADC_CECR) Error Correction Enable for channel 8 */\r
+#define ADC_CECR_ECORR9 (0x1u << 9) /**< \brief (ADC_CECR) Error Correction Enable for channel 9 */\r
+#define ADC_CECR_ECORR10 (0x1u << 10) /**< \brief (ADC_CECR) Error Correction Enable for channel 10 */\r
+#define ADC_CECR_ECORR11 (0x1u << 11) /**< \brief (ADC_CECR) Error Correction Enable for channel 11 */\r
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protection Enable */\r
+#define ADC_WPMR_WPKEY_Pos 8\r
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protection Key */\r
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))\r
+#define ADC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (ADC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */\r
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protection Status Register -------- */\r
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protection Violation Status */\r
+#define ADC_WPSR_WPVSRC_Pos 8\r
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protection Violation Source */\r
+/* -------- ADC_VERSION : (ADC Offset: 0xFC) Version Register -------- */\r
+#define ADC_VERSION_VERSION_Pos 0\r
+#define ADC_VERSION_VERSION_Msk (0xfffu << ADC_VERSION_VERSION_Pos) /**< \brief (ADC_VERSION) Version of the Hardware Module */\r
+#define ADC_VERSION_MFN_Pos 16\r
+#define ADC_VERSION_MFN_Msk (0x7u << ADC_VERSION_MFN_Pos) /**< \brief (ADC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_ADC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_AES_COMPONENT_\r
+#define _SAMA5D2_AES_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_AES Advanced Encryption Standard */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Aes hardware registers */\r
+typedef struct {\r
+ __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */\r
+ __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */\r
+ __I uint32_t Reserved1[2];\r
+ __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */\r
+ __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */\r
+ __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */\r
+ __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */\r
+ __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */\r
+ __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */\r
+ __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */\r
+ __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */\r
+ __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */\r
+ __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */\r
+ __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */\r
+ __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */\r
+ __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */\r
+ __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t AES_EMR; /**< \brief (Aes Offset: 0xB0) Extended Mode Register */\r
+ __IO uint32_t AES_BCNT; /**< \brief (Aes Offset: 0xB4) Byte Counter Register */\r
+ __I uint32_t Reserved3[2];\r
+ __IO uint32_t AES_TWR[4]; /**< \brief (Aes Offset: 0xC0) Tweak Word Register */\r
+ __O uint32_t AES_ALPHAR[4]; /**< \brief (Aes Offset: 0xD0) Alpha Word Register */\r
+ __I uint32_t Reserved4[7];\r
+ __I uint32_t AES_VERSION; /**< \brief (Aes Offset: 0xFC) Version Register */\r
+} Aes;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */\r
+#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */\r
+#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */\r
+#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */\r
+/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */\r
+#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */\r
+#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */\r
+#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */\r
+#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */\r
+#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */\r
+#define AES_MR_PROCDLY_Pos 4\r
+#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */\r
+#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))\r
+#define AES_MR_SMOD_Pos 8\r
+#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */\r
+#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)))\r
+#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */\r
+#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */\r
+#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */\r
+#define AES_MR_KEYSIZE_Pos 10\r
+#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */\r
+#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)))\r
+#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */\r
+#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */\r
+#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */\r
+#define AES_MR_OPMOD_Pos 12\r
+#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */\r
+#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)))\r
+#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */\r
+#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */\r
+#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */\r
+#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */\r
+#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */\r
+#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */\r
+#define AES_MR_OPMOD_XTS (0x6u << 12) /**< \brief (AES_MR) XTS: XEX-based tweaked-codebook mode */\r
+#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */\r
+#define AES_MR_CFBS_Pos 16\r
+#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */\r
+#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)))\r
+#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */\r
+#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */\r
+#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */\r
+#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */\r
+#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */\r
+#define AES_MR_CKEY_Pos 20\r
+#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */\r
+#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)))\r
+#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */\r
+#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */\r
+#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */\r
+#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */\r
+#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */\r
+#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */\r
+#define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */\r
+#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */\r
+#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */\r
+#define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */\r
+#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */\r
+#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */\r
+#define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */\r
+#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */\r
+#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */\r
+#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */\r
+#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */\r
+#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */\r
+#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */\r
+/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */\r
+#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */\r
+#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */\r
+#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */\r
+#define AES_IER_EOPAD (0x1u << 17) /**< \brief (AES_IER) End of Padding Interrupt Enable */\r
+#define AES_IER_PLENERR (0x1u << 18) /**< \brief (AES_IER) Padding Length Error Interrupt Enable */\r
+/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */\r
+#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */\r
+#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */\r
+#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */\r
+#define AES_IDR_EOPAD (0x1u << 17) /**< \brief (AES_IDR) End of Padding Interrupt Disable */\r
+#define AES_IDR_PLENERR (0x1u << 18) /**< \brief (AES_IDR) Padding Length Error Interrupt Disable */\r
+/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */\r
+#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */\r
+#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */\r
+#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */\r
+#define AES_IMR_EOPAD (0x1u << 17) /**< \brief (AES_IMR) End of Padding Interrupt Mask */\r
+#define AES_IMR_PLENERR (0x1u << 18) /**< \brief (AES_IMR) Padding Length Error Interrupt Mask */\r
+/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */\r
+#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */\r
+#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */\r
+#define AES_ISR_URAT_Pos 12\r
+#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */\r
+#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */\r
+#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */\r
+#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */\r
+#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */\r
+#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */\r
+#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */\r
+#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */\r
+#define AES_ISR_EOPAD (0x1u << 17) /**< \brief (AES_ISR) End of Padding */\r
+#define AES_ISR_PLENERR (0x1u << 18) /**< \brief (AES_ISR) Padding Length Error */\r
+/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */\r
+#define AES_KEYWR_KEYW_Pos 0\r
+#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */\r
+#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))\r
+/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */\r
+#define AES_IDATAR_IDATA_Pos 0\r
+#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */\r
+#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))\r
+/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */\r
+#define AES_ODATAR_ODATA_Pos 0\r
+#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */\r
+/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */\r
+#define AES_IVR_IV_Pos 0\r
+#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */\r
+#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))\r
+/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */\r
+#define AES_AADLENR_AADLEN_Pos 0\r
+#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */\r
+#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)))\r
+/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */\r
+#define AES_CLENR_CLEN_Pos 0\r
+#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */\r
+#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)))\r
+/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */\r
+#define AES_GHASHR_GHASH_Pos 0\r
+#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */\r
+#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)))\r
+/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */\r
+#define AES_TAGR_TAG_Pos 0\r
+#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */\r
+/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */\r
+#define AES_CTRR_CTR_Pos 0\r
+#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */\r
+/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */\r
+#define AES_GCMHR_H_Pos 0\r
+#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */\r
+#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)))\r
+/* -------- AES_EMR : (AES Offset: 0xB0) Extended Mode Register -------- */\r
+#define AES_EMR_APEN (0x1u << 0) /**< \brief (AES_EMR) Auto Padding Enable */\r
+#define AES_EMR_APM (0x1u << 1) /**< \brief (AES_EMR) Auto Padding Mode */\r
+#define AES_EMR_PLIPEN (0x1u << 4) /**< \brief (AES_EMR) Protocol Layer Improved Performance Enable */\r
+#define AES_EMR_PLIPD (0x1u << 5) /**< \brief (AES_EMR) Protocol Layer Improved Performance Decipher */\r
+#define AES_EMR_PADLEN_Pos 8\r
+#define AES_EMR_PADLEN_Msk (0xffu << AES_EMR_PADLEN_Pos) /**< \brief (AES_EMR) Auto Padding Length */\r
+#define AES_EMR_PADLEN(value) ((AES_EMR_PADLEN_Msk & ((value) << AES_EMR_PADLEN_Pos)))\r
+#define AES_EMR_NHEAD_Pos 16\r
+#define AES_EMR_NHEAD_Msk (0xffu << AES_EMR_NHEAD_Pos) /**< \brief (AES_EMR) IPSEC Next Header */\r
+#define AES_EMR_NHEAD(value) ((AES_EMR_NHEAD_Msk & ((value) << AES_EMR_NHEAD_Pos)))\r
+/* -------- AES_BCNT : (AES Offset: 0xB4) Byte Counter Register -------- */\r
+#define AES_BCNT_BCNT_Pos 0\r
+#define AES_BCNT_BCNT_Msk (0xffffffffu << AES_BCNT_BCNT_Pos) /**< \brief (AES_BCNT) Auto Padding Byte Counter */\r
+#define AES_BCNT_BCNT(value) ((AES_BCNT_BCNT_Msk & ((value) << AES_BCNT_BCNT_Pos)))\r
+/* -------- AES_TWR[4] : (AES Offset: 0xC0) Tweak Word Register -------- */\r
+#define AES_TWR_TWEAK_Pos 0\r
+#define AES_TWR_TWEAK_Msk (0xffffffffu << AES_TWR_TWEAK_Pos) /**< \brief (AES_TWR[4]) Tweak Word x */\r
+#define AES_TWR_TWEAK(value) ((AES_TWR_TWEAK_Msk & ((value) << AES_TWR_TWEAK_Pos)))\r
+/* -------- AES_ALPHAR[4] : (AES Offset: 0xD0) Alpha Word Register -------- */\r
+#define AES_ALPHAR_ALPHA_Pos 0\r
+#define AES_ALPHAR_ALPHA_Msk (0xffffffffu << AES_ALPHAR_ALPHA_Pos) /**< \brief (AES_ALPHAR[4]) Alpha Word x */\r
+#define AES_ALPHAR_ALPHA(value) ((AES_ALPHAR_ALPHA_Msk & ((value) << AES_ALPHAR_ALPHA_Pos)))\r
+/* -------- AES_VERSION : (AES Offset: 0xFC) Version Register -------- */\r
+#define AES_VERSION_VERSION_Pos 0\r
+#define AES_VERSION_VERSION_Msk (0xfffu << AES_VERSION_VERSION_Pos) /**< \brief (AES_VERSION) Version of the Hardware Module */\r
+#define AES_VERSION_MFN_Pos 16\r
+#define AES_VERSION_MFN_Msk (0x7u << AES_VERSION_MFN_Pos) /**< \brief (AES_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_AES_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_AESB_COMPONENT_\r
+#define _SAMA5D2_AESB_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard Bridge */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_AESB Advanced Encryption Standard Bridge */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Aesb hardware registers */\r
+typedef struct {\r
+ __O uint32_t AESB_CR; /**< \brief (Aesb Offset: 0x00) Control Register */\r
+ __IO uint32_t AESB_MR; /**< \brief (Aesb Offset: 0x04) Mode Register */\r
+ __I uint32_t Reserved1[2];\r
+ __O uint32_t AESB_IER; /**< \brief (Aesb Offset: 0x10) Interrupt Enable Register */\r
+ __O uint32_t AESB_IDR; /**< \brief (Aesb Offset: 0x14) Interrupt Disable Register */\r
+ __I uint32_t AESB_IMR; /**< \brief (Aesb Offset: 0x18) Interrupt Mask Register */\r
+ __I uint32_t AESB_ISR; /**< \brief (Aesb Offset: 0x1C) Interrupt Status Register */\r
+ __O uint32_t AESB_KEYWR[4]; /**< \brief (Aesb Offset: 0x20) Key Word Register */\r
+ __I uint32_t Reserved2[4];\r
+ __O uint32_t AESB_IDATAR[4]; /**< \brief (Aesb Offset: 0x40) Input Data Register */\r
+ __I uint32_t AESB_ODATAR[4]; /**< \brief (Aesb Offset: 0x50) Output Data Register */\r
+ __O uint32_t AESB_IVR[4]; /**< \brief (Aesb Offset: 0x60) Initialization Vector Register */\r
+ __I uint32_t Reserved3[35];\r
+ __I uint32_t AESB_VERSION; /**< \brief (Aesb Offset: 0xFC) Version Register */\r
+} Aesb;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- AESB_CR : (AESB Offset: 0x00) Control Register -------- */\r
+#define AESB_CR_START (0x1u << 0) /**< \brief (AESB_CR) Start Processing */\r
+#define AESB_CR_SWRST (0x1u << 8) /**< \brief (AESB_CR) Software Reset */\r
+#define AESB_CR_LOADSEED (0x1u << 16) /**< \brief (AESB_CR) Random Number Generator Seed Loading */\r
+/* -------- AESB_MR : (AESB Offset: 0x04) Mode Register -------- */\r
+#define AESB_MR_CIPHER (0x1u << 0) /**< \brief (AESB_MR) Processing Mode */\r
+#define AESB_MR_AAHB (0x1u << 2) /**< \brief (AESB_MR) Automatic Bridge Mode */\r
+#define AESB_MR_DUALBUFF (0x1u << 3) /**< \brief (AESB_MR) Dual Input Buffer */\r
+#define AESB_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AESB_MR) AESB_IDATARx cannot be written during processing of previous block. */\r
+#define AESB_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AESB_MR) AESB_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */\r
+#define AESB_MR_PROCDLY_Pos 4\r
+#define AESB_MR_PROCDLY_Msk (0xfu << AESB_MR_PROCDLY_Pos) /**< \brief (AESB_MR) Processing Delay */\r
+#define AESB_MR_PROCDLY(value) ((AESB_MR_PROCDLY_Msk & ((value) << AESB_MR_PROCDLY_Pos)))\r
+#define AESB_MR_SMOD_Pos 8\r
+#define AESB_MR_SMOD_Msk (0x3u << AESB_MR_SMOD_Pos) /**< \brief (AESB_MR) Start Mode */\r
+#define AESB_MR_SMOD(value) ((AESB_MR_SMOD_Msk & ((value) << AESB_MR_SMOD_Pos)))\r
+#define AESB_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AESB_MR) Manual Mode */\r
+#define AESB_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AESB_MR) Auto Mode */\r
+#define AESB_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AESB_MR) AESB_IDATAR0 access only Auto Mode */\r
+#define AESB_MR_OPMOD_Pos 12\r
+#define AESB_MR_OPMOD_Msk (0x7u << AESB_MR_OPMOD_Pos) /**< \brief (AESB_MR) Operation Mode */\r
+#define AESB_MR_OPMOD(value) ((AESB_MR_OPMOD_Msk & ((value) << AESB_MR_OPMOD_Pos)))\r
+#define AESB_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AESB_MR) Electronic Code Book mode */\r
+#define AESB_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AESB_MR) Cipher Block Chaining mode */\r
+#define AESB_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AESB_MR) Counter mode (16-bit internal counter) */\r
+#define AESB_MR_LOD (0x1u << 15) /**< \brief (AESB_MR) Last Output Data Mode */\r
+#define AESB_MR_CKEY_Pos 20\r
+#define AESB_MR_CKEY_Msk (0xfu << AESB_MR_CKEY_Pos) /**< \brief (AESB_MR) Countermeasure Key */\r
+#define AESB_MR_CKEY(value) ((AESB_MR_CKEY_Msk & ((value) << AESB_MR_CKEY_Pos)))\r
+#define AESB_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AESB_MR) This field must be written with 0xE to allow CMTYPx fields change. Any other values will abort the write operation in CMTYPx fields.Always reads as 0. */\r
+#define AESB_MR_CMTYP1 (0x1u << 24) /**< \brief (AESB_MR) Countermeasure Type 1 */\r
+#define AESB_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AESB_MR) Countermeasure type 1 is disabled. */\r
+#define AESB_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AESB_MR) Countermeasure type 1 is enabled. */\r
+#define AESB_MR_CMTYP2 (0x1u << 25) /**< \brief (AESB_MR) Countermeasure Type 2 */\r
+#define AESB_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AESB_MR) Countermeasure type 2 is disabled. */\r
+#define AESB_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AESB_MR) Countermeasure type 2 is enabled. */\r
+#define AESB_MR_CMTYP3 (0x1u << 26) /**< \brief (AESB_MR) Countermeasure Type 3 */\r
+#define AESB_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AESB_MR) Countermeasure type 3 is disabled. */\r
+#define AESB_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AESB_MR) Countermeasure type 3 is enabled. */\r
+#define AESB_MR_CMTYP4 (0x1u << 27) /**< \brief (AESB_MR) Countermeasure Type 4 */\r
+#define AESB_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AESB_MR) Countermeasure type 4 is disabled. */\r
+#define AESB_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AESB_MR) Countermeasure type 4 is enabled. */\r
+#define AESB_MR_CMTYP5 (0x1u << 28) /**< \brief (AESB_MR) Countermeasure Type 5 */\r
+#define AESB_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AESB_MR) Countermeasure type 5 is disabled. */\r
+#define AESB_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AESB_MR) Countermeasure type 5 is enabled. */\r
+#define AESB_MR_CMTYP6 (0x1u << 29) /**< \brief (AESB_MR) CounterMeasure Type 6 */\r
+#define AESB_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AESB_MR) Countermeasure type 6 is disabled. */\r
+#define AESB_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AESB_MR) Countermeasure type 6 is enabled. */\r
+/* -------- AESB_IER : (AESB Offset: 0x10) Interrupt Enable Register -------- */\r
+#define AESB_IER_DATRDY (0x1u << 0) /**< \brief (AESB_IER) Data Ready Interrupt Enable */\r
+#define AESB_IER_URAD (0x1u << 8) /**< \brief (AESB_IER) Unspecified Register Access Detection Interrupt Enable */\r
+/* -------- AESB_IDR : (AESB Offset: 0x14) Interrupt Disable Register -------- */\r
+#define AESB_IDR_DATRDY (0x1u << 0) /**< \brief (AESB_IDR) Data Ready Interrupt Disable */\r
+#define AESB_IDR_URAD (0x1u << 8) /**< \brief (AESB_IDR) Unspecified Register Access Detection Interrupt Disable */\r
+/* -------- AESB_IMR : (AESB Offset: 0x18) Interrupt Mask Register -------- */\r
+#define AESB_IMR_DATRDY (0x1u << 0) /**< \brief (AESB_IMR) Data Ready Interrupt Mask */\r
+#define AESB_IMR_URAD (0x1u << 8) /**< \brief (AESB_IMR) Unspecified Register Access Detection Interrupt Mask */\r
+/* -------- AESB_ISR : (AESB Offset: 0x1C) Interrupt Status Register -------- */\r
+#define AESB_ISR_DATRDY (0x1u << 0) /**< \brief (AESB_ISR) Data Ready */\r
+#define AESB_ISR_URAD (0x1u << 8) /**< \brief (AESB_ISR) Unspecified Register Access Detection Status */\r
+#define AESB_ISR_URAT_Pos 12\r
+#define AESB_ISR_URAT_Msk (0xfu << AESB_ISR_URAT_Pos) /**< \brief (AESB_ISR) Unspecified Register Access */\r
+#define AESB_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AESB_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode */\r
+#define AESB_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AESB_ISR) Output Data Register read during the data processing */\r
+#define AESB_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AESB_ISR) Mode Register written during the data processing */\r
+#define AESB_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AESB_ISR) Output Data Register read during the sub-keys generation */\r
+#define AESB_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AESB_ISR) Mode Register written during the sub-keys generation */\r
+#define AESB_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AESB_ISR) Write-only register read access */\r
+/* -------- AESB_KEYWR[4] : (AESB Offset: 0x20) Key Word Register -------- */\r
+#define AESB_KEYWR_KEYW_Pos 0\r
+#define AESB_KEYWR_KEYW_Msk (0xffffffffu << AESB_KEYWR_KEYW_Pos) /**< \brief (AESB_KEYWR[4]) Key Word */\r
+#define AESB_KEYWR_KEYW(value) ((AESB_KEYWR_KEYW_Msk & ((value) << AESB_KEYWR_KEYW_Pos)))\r
+/* -------- AESB_IDATAR[4] : (AESB Offset: 0x40) Input Data Register -------- */\r
+#define AESB_IDATAR_IDATA_Pos 0\r
+#define AESB_IDATAR_IDATA_Msk (0xffffffffu << AESB_IDATAR_IDATA_Pos) /**< \brief (AESB_IDATAR[4]) Input Data Word */\r
+#define AESB_IDATAR_IDATA(value) ((AESB_IDATAR_IDATA_Msk & ((value) << AESB_IDATAR_IDATA_Pos)))\r
+/* -------- AESB_ODATAR[4] : (AESB Offset: 0x50) Output Data Register -------- */\r
+#define AESB_ODATAR_ODATA_Pos 0\r
+#define AESB_ODATAR_ODATA_Msk (0xffffffffu << AESB_ODATAR_ODATA_Pos) /**< \brief (AESB_ODATAR[4]) Output Data */\r
+/* -------- AESB_IVR[4] : (AESB Offset: 0x60) Initialization Vector Register -------- */\r
+#define AESB_IVR_IV_Pos 0\r
+#define AESB_IVR_IV_Msk (0xffffffffu << AESB_IVR_IV_Pos) /**< \brief (AESB_IVR[4]) Initialization Vector */\r
+#define AESB_IVR_IV(value) ((AESB_IVR_IV_Msk & ((value) << AESB_IVR_IV_Pos)))\r
+/* -------- AESB_VERSION : (AESB Offset: 0xFC) Version Register -------- */\r
+#define AESB_VERSION_VERSION_Pos 0\r
+#define AESB_VERSION_VERSION_Msk (0xfffu << AESB_VERSION_VERSION_Pos) /**< \brief (AESB_VERSION) Version of the Hardware Module */\r
+#define AESB_VERSION_MFN_Pos 16\r
+#define AESB_VERSION_MFN_Msk (0x7u << AESB_VERSION_MFN_Pos) /**< \brief (AESB_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_AESB_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_AIC_COMPONENT_\r
+#define _SAMA5D2_AIC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_AIC Advanced Interrupt Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Aic hardware registers */\r
+typedef struct {\r
+ __IO uint32_t AIC_SSR; /**< \brief (Aic Offset: 0x00) Source Select Register */\r
+ __IO uint32_t AIC_SMR; /**< \brief (Aic Offset: 0x04) Source Mode Register */\r
+ __IO uint32_t AIC_SVR; /**< \brief (Aic Offset: 0x08) Source Vector Register */\r
+ __I uint32_t Reserved1[1];\r
+ __I uint32_t AIC_IVR; /**< \brief (Aic Offset: 0x10) Interrupt Vector Register */\r
+ __I uint32_t AIC_FVR; /**< \brief (Aic Offset: 0x14) FIQ Vector Register */\r
+ __I uint32_t AIC_ISR; /**< \brief (Aic Offset: 0x18) Interrupt Status Register */\r
+ __I uint32_t Reserved2[1];\r
+ __I uint32_t AIC_IPR0; /**< \brief (Aic Offset: 0x20) Interrupt Pending Register 0 */\r
+ __I uint32_t AIC_IPR1; /**< \brief (Aic Offset: 0x24) Interrupt Pending Register 1 */\r
+ __I uint32_t AIC_IPR2; /**< \brief (Aic Offset: 0x28) Interrupt Pending Register 2 */\r
+ __I uint32_t AIC_IPR3; /**< \brief (Aic Offset: 0x2C) Interrupt Pending Register 3 */\r
+ __I uint32_t AIC_IMR; /**< \brief (Aic Offset: 0x30) Interrupt Mask Register */\r
+ __I uint32_t AIC_CISR; /**< \brief (Aic Offset: 0x34) Core Interrupt Status Register */\r
+ __O uint32_t AIC_EOICR; /**< \brief (Aic Offset: 0x38) End of Interrupt Command Register */\r
+ __IO uint32_t AIC_SPU; /**< \brief (Aic Offset: 0x3C) Spurious Interrupt Vector Register */\r
+ __O uint32_t AIC_IECR; /**< \brief (Aic Offset: 0x40) Interrupt Enable Command Register */\r
+ __O uint32_t AIC_IDCR; /**< \brief (Aic Offset: 0x44) Interrupt Disable Command Register */\r
+ __O uint32_t AIC_ICCR; /**< \brief (Aic Offset: 0x48) Interrupt Clear Command Register */\r
+ __O uint32_t AIC_ISCR; /**< \brief (Aic Offset: 0x4C) Interrupt Set Command Register */\r
+ __I uint32_t Reserved3[7];\r
+ __IO uint32_t AIC_DCR; /**< \brief (Aic Offset: 0x6C) Debug Control Register */\r
+ __I uint32_t Reserved4[29];\r
+ __IO uint32_t AIC_WPMR; /**< \brief (Aic Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t AIC_WPSR; /**< \brief (Aic Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved5[4];\r
+ __I uint32_t AIC_VERSION; /**< \brief (Aic Offset: 0XFC) AIC Version Register */\r
+} Aic;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- AIC_SSR : (AIC Offset: 0x00) Source Select Register -------- */\r
+#define AIC_SSR_INTSEL_Pos 0\r
+#define AIC_SSR_INTSEL_Msk (0x7fu << AIC_SSR_INTSEL_Pos) /**< \brief (AIC_SSR) Interrupt Line Selection */\r
+#define AIC_SSR_INTSEL(value) ((AIC_SSR_INTSEL_Msk & ((value) << AIC_SSR_INTSEL_Pos)))\r
+/* -------- AIC_SMR : (AIC Offset: 0x04) Source Mode Register -------- */\r
+#define AIC_SMR_PRIOR_Pos 0\r
+#define AIC_SMR_PRIOR_Msk (0x7u << AIC_SMR_PRIOR_Pos) /**< \brief (AIC_SMR) Priority Level */\r
+#define AIC_SMR_PRIOR(value) ((AIC_SMR_PRIOR_Msk & ((value) << AIC_SMR_PRIOR_Pos)))\r
+#define AIC_SMR_SRCTYPE_Pos 5\r
+#define AIC_SMR_SRCTYPE_Msk (0x3u << AIC_SMR_SRCTYPE_Pos) /**< \brief (AIC_SMR) Interrupt Source Type */\r
+#define AIC_SMR_SRCTYPE(value) ((AIC_SMR_SRCTYPE_Msk & ((value) << AIC_SMR_SRCTYPE_Pos)))\r
+#define AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE (0x0u << 5) /**< \brief (AIC_SMR) High level Sensitive for internal sourceLow level Sensitive for external source */\r
+#define AIC_SMR_SRCTYPE_INT_EDGE_TRIGGERED (0x1u << 5) /**< \brief (AIC_SMR) Positive edge triggered for internal sourceNegative edge triggered for external source */\r
+#define AIC_SMR_SRCTYPE_EXT_HIGH_LEVEL (0x2u << 5) /**< \brief (AIC_SMR) High level Sensitive for internal sourceHigh level Sensitive for external source */\r
+#define AIC_SMR_SRCTYPE_EXT_POSITIVE_EDGE (0x3u << 5) /**< \brief (AIC_SMR) Positive edge triggered for internal sourcePositive edge triggered for external source */\r
+/* -------- AIC_SVR : (AIC Offset: 0x08) Source Vector Register -------- */\r
+#define AIC_SVR_VECTOR_Pos 0\r
+#define AIC_SVR_VECTOR_Msk (0xffffffffu << AIC_SVR_VECTOR_Pos) /**< \brief (AIC_SVR) Source Vector */\r
+#define AIC_SVR_VECTOR(value) ((AIC_SVR_VECTOR_Msk & ((value) << AIC_SVR_VECTOR_Pos)))\r
+/* -------- AIC_IVR : (AIC Offset: 0x10) Interrupt Vector Register -------- */\r
+#define AIC_IVR_IRQV_Pos 0\r
+#define AIC_IVR_IRQV_Msk (0xffffffffu << AIC_IVR_IRQV_Pos) /**< \brief (AIC_IVR) Interrupt Vector Register */\r
+/* -------- AIC_FVR : (AIC Offset: 0x14) FIQ Vector Register -------- */\r
+#define AIC_FVR_FIQV_Pos 0\r
+#define AIC_FVR_FIQV_Msk (0xffffffffu << AIC_FVR_FIQV_Pos) /**< \brief (AIC_FVR) FIQ Vector Register */\r
+/* -------- AIC_ISR : (AIC Offset: 0x18) Interrupt Status Register -------- */\r
+#define AIC_ISR_IRQID_Pos 0\r
+#define AIC_ISR_IRQID_Msk (0x7fu << AIC_ISR_IRQID_Pos) /**< \brief (AIC_ISR) Current Interrupt Identifier */\r
+/* -------- AIC_IPR0 : (AIC Offset: 0x20) Interrupt Pending Register 0 -------- */\r
+#define AIC_IPR0_FIQ (0x1u << 0) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_SYS (0x1u << 1) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID2 (0x1u << 2) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID3 (0x1u << 3) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID4 (0x1u << 4) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID5 (0x1u << 5) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID6 (0x1u << 6) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID7 (0x1u << 7) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID8 (0x1u << 8) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID9 (0x1u << 9) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID10 (0x1u << 10) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID11 (0x1u << 11) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID12 (0x1u << 12) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID13 (0x1u << 13) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID14 (0x1u << 14) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID15 (0x1u << 15) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID16 (0x1u << 16) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID17 (0x1u << 17) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID18 (0x1u << 18) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID19 (0x1u << 19) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID20 (0x1u << 20) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID21 (0x1u << 21) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID22 (0x1u << 22) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID23 (0x1u << 23) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID24 (0x1u << 24) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID25 (0x1u << 25) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID26 (0x1u << 26) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID27 (0x1u << 27) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID28 (0x1u << 28) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID29 (0x1u << 29) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID30 (0x1u << 30) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+#define AIC_IPR0_PID31 (0x1u << 31) /**< \brief (AIC_IPR0) Interrupt Pending */\r
+/* -------- AIC_IPR1 : (AIC Offset: 0x24) Interrupt Pending Register 1 -------- */\r
+#define AIC_IPR1_PID32 (0x1u << 0) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID33 (0x1u << 1) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID34 (0x1u << 2) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID35 (0x1u << 3) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID36 (0x1u << 4) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID37 (0x1u << 5) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID38 (0x1u << 6) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID39 (0x1u << 7) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID40 (0x1u << 8) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID41 (0x1u << 9) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID42 (0x1u << 10) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID43 (0x1u << 11) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID44 (0x1u << 12) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID45 (0x1u << 13) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID46 (0x1u << 14) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID47 (0x1u << 15) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID48 (0x1u << 16) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID49 (0x1u << 17) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID50 (0x1u << 18) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID51 (0x1u << 19) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID52 (0x1u << 20) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID53 (0x1u << 21) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID54 (0x1u << 22) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID55 (0x1u << 23) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID56 (0x1u << 24) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID57 (0x1u << 25) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID58 (0x1u << 26) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID59 (0x1u << 27) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID60 (0x1u << 28) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID61 (0x1u << 29) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID62 (0x1u << 30) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+#define AIC_IPR1_PID63 (0x1u << 31) /**< \brief (AIC_IPR1) Interrupt Pending */\r
+/* -------- AIC_IPR2 : (AIC Offset: 0x28) Interrupt Pending Register 2 -------- */\r
+#define AIC_IPR2_PID64 (0x1u << 0) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID65 (0x1u << 1) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID66 (0x1u << 2) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID67 (0x1u << 3) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID68 (0x1u << 4) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID69 (0x1u << 5) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID70 (0x1u << 6) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID71 (0x1u << 7) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID72 (0x1u << 8) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID73 (0x1u << 9) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID74 (0x1u << 10) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID75 (0x1u << 11) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID76 (0x1u << 12) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID77 (0x1u << 13) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID78 (0x1u << 14) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID79 (0x1u << 15) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID80 (0x1u << 16) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID81 (0x1u << 17) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID82 (0x1u << 18) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID83 (0x1u << 19) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID84 (0x1u << 20) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID85 (0x1u << 21) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID86 (0x1u << 22) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID87 (0x1u << 23) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID88 (0x1u << 24) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID89 (0x1u << 25) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID90 (0x1u << 26) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID91 (0x1u << 27) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID92 (0x1u << 28) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID93 (0x1u << 29) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID94 (0x1u << 30) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+#define AIC_IPR2_PID95 (0x1u << 31) /**< \brief (AIC_IPR2) Interrupt Pending */\r
+/* -------- AIC_IPR3 : (AIC Offset: 0x2C) Interrupt Pending Register 3 -------- */\r
+#define AIC_IPR3_PID96 (0x1u << 0) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID97 (0x1u << 1) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID98 (0x1u << 2) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID99 (0x1u << 3) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID100 (0x1u << 4) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID101 (0x1u << 5) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID102 (0x1u << 6) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID103 (0x1u << 7) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID104 (0x1u << 8) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID105 (0x1u << 9) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID106 (0x1u << 10) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID107 (0x1u << 11) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID108 (0x1u << 12) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID109 (0x1u << 13) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID110 (0x1u << 14) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID111 (0x1u << 15) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID112 (0x1u << 16) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID113 (0x1u << 17) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID114 (0x1u << 18) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID115 (0x1u << 19) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID116 (0x1u << 20) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID117 (0x1u << 21) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID118 (0x1u << 22) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID119 (0x1u << 23) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID120 (0x1u << 24) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID121 (0x1u << 25) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID122 (0x1u << 26) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID123 (0x1u << 27) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID124 (0x1u << 28) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID125 (0x1u << 29) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID126 (0x1u << 30) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+#define AIC_IPR3_PID127 (0x1u << 31) /**< \brief (AIC_IPR3) Interrupt Pending */\r
+/* -------- AIC_IMR : (AIC Offset: 0x30) Interrupt Mask Register -------- */\r
+#define AIC_IMR_INTM (0x1u << 0) /**< \brief (AIC_IMR) Interrupt Mask */\r
+/* -------- AIC_CISR : (AIC Offset: 0x34) Core Interrupt Status Register -------- */\r
+#define AIC_CISR_NFIQ (0x1u << 0) /**< \brief (AIC_CISR) NFIQ Status */\r
+#define AIC_CISR_NIRQ (0x1u << 1) /**< \brief (AIC_CISR) NIRQ Status */\r
+/* -------- AIC_EOICR : (AIC Offset: 0x38) End of Interrupt Command Register -------- */\r
+#define AIC_EOICR_ENDIT (0x1u << 0) /**< \brief (AIC_EOICR) Interrupt Processing Complete Command */\r
+/* -------- AIC_SPU : (AIC Offset: 0x3C) Spurious Interrupt Vector Register -------- */\r
+#define AIC_SPU_SIVR_Pos 0\r
+#define AIC_SPU_SIVR_Msk (0xffffffffu << AIC_SPU_SIVR_Pos) /**< \brief (AIC_SPU) Spurious Interrupt Vector Register */\r
+#define AIC_SPU_SIVR(value) ((AIC_SPU_SIVR_Msk & ((value) << AIC_SPU_SIVR_Pos)))\r
+/* -------- AIC_IECR : (AIC Offset: 0x40) Interrupt Enable Command Register -------- */\r
+#define AIC_IECR_INTEN (0x1u << 0) /**< \brief (AIC_IECR) Interrupt Enable */\r
+/* -------- AIC_IDCR : (AIC Offset: 0x44) Interrupt Disable Command Register -------- */\r
+#define AIC_IDCR_INTD (0x1u << 0) /**< \brief (AIC_IDCR) Interrupt Disable */\r
+/* -------- AIC_ICCR : (AIC Offset: 0x48) Interrupt Clear Command Register -------- */\r
+#define AIC_ICCR_INTCLR (0x1u << 0) /**< \brief (AIC_ICCR) Interrupt Clear */\r
+/* -------- AIC_ISCR : (AIC Offset: 0x4C) Interrupt Set Command Register -------- */\r
+#define AIC_ISCR_INTSET (0x1u << 0) /**< \brief (AIC_ISCR) Interrupt Set */\r
+/* -------- AIC_DCR : (AIC Offset: 0x6C) Debug Control Register -------- */\r
+#define AIC_DCR_PROT (0x1u << 0) /**< \brief (AIC_DCR) Protection Mode */\r
+#define AIC_DCR_GMSK (0x1u << 1) /**< \brief (AIC_DCR) General Interrupt Mask */\r
+/* -------- AIC_WPMR : (AIC Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define AIC_WPMR_WPEN (0x1u << 0) /**< \brief (AIC_WPMR) Write Protection Enable */\r
+#define AIC_WPMR_WPKEY_Pos 8\r
+#define AIC_WPMR_WPKEY_Msk (0xffffffu << AIC_WPMR_WPKEY_Pos) /**< \brief (AIC_WPMR) Write Protection Key */\r
+#define AIC_WPMR_WPKEY(value) ((AIC_WPMR_WPKEY_Msk & ((value) << AIC_WPMR_WPKEY_Pos)))\r
+#define AIC_WPMR_WPKEY_PASSWD (0x414943u << 8) /**< \brief (AIC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- AIC_WPSR : (AIC Offset: 0xE8) Write Protection Status Register -------- */\r
+#define AIC_WPSR_WPVS (0x1u << 0) /**< \brief (AIC_WPSR) Write Protection Violation Status */\r
+#define AIC_WPSR_WPVSRC_Pos 8\r
+#define AIC_WPSR_WPVSRC_Msk (0xffffu << AIC_WPSR_WPVSRC_Pos) /**< \brief (AIC_WPSR) Write Protection Violation Source */\r
+/* -------- AIC_VERSION : (AIC Offset: 0XFC) AIC Version Register -------- */\r
+#define AIC_VERSION_VERSION_Pos 0\r
+#define AIC_VERSION_VERSION_Msk (0xfffu << AIC_VERSION_VERSION_Pos) /**< \brief (AIC_VERSION) Version of the Hardware Module */\r
+#define AIC_VERSION_MFN_Pos 16\r
+#define AIC_VERSION_MFN_Msk (0x7u << AIC_VERSION_MFN_Pos) /**< \brief (AIC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_AIC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_AXIMX_COMPONENT_\r
+#define _SAMA5D2_AXIMX_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR AXI Matrix */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_AXIMX AXI Matrix */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Aximx hardware registers */\r
+typedef struct {\r
+ __O uint32_t AXIMX_REMAP; /**< \brief (Aximx Offset: 0x00) AXI Matrix Remap Register */\r
+} Aximx;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- AXIMX_REMAP : (AXIMX Offset: 0x00) AXI Matrix Remap Register -------- */\r
+#define AXIMX_REMAP_REMAP0 (0x1u << 0) /**< \brief (AXIMX_REMAP) Remap State 0 */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_AXIMX_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_CHIPID_COMPONENT_\r
+#define _SAMA5D2_CHIPID_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Chip Identifier */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_CHIPID Chip Identifier */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Chipid hardware registers */\r
+typedef struct {\r
+ __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */\r
+ __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */\r
+} Chipid;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */\r
+#define CHIPID_CIDR_VERSION_Pos 0\r
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */\r
+#define CHIPID_CIDR_EPROC_Pos 5\r
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */\r
+#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */\r
+#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */\r
+#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */\r
+#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */\r
+#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */\r
+#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */\r
+#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */\r
+#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */\r
+#define CHIPID_CIDR_NVPSIZ_Pos 8\r
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_Pos 12\r
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */\r
+#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_Pos 16\r
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */\r
+#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */\r
+#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */\r
+#define CHIPID_CIDR_ARCH_Pos 20\r
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */\r
+#define CHIPID_CIDR_ARCH_SAM4CxxE (0x66u << 20) /**< \brief (CHIPID_CIDR) SAM4CxE (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAMA5 (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAMA5 */\r
+#define CHIPID_CIDR_NVPTYP_Pos 28\r
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */\r
+#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */\r
+#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */\r
+#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */\r
+#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */\r
+#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */\r
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */\r
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */\r
+#define CHIPID_EXID_EXID_Pos 0\r
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_CHIPID_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_CLASSD_COMPONENT_\r
+#define _SAMA5D2_CLASSD_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Audio Class D Amplifier */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_CLASSD Audio Class D Amplifier */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Classd hardware registers */\r
+typedef struct {\r
+ __O uint32_t CLASSD_CR; /**< \brief (Classd Offset: 0x00) Control Register */\r
+ __IO uint32_t CLASSD_MR; /**< \brief (Classd Offset: 0x04) Mode Register */\r
+ __IO uint32_t CLASSD_INTPMR; /**< \brief (Classd Offset: 0x08) Interpolator Mode Register */\r
+ __I uint32_t CLASSD_INTSR; /**< \brief (Classd Offset: 0x0C) Interpolator Status Register */\r
+ __IO uint32_t CLASSD_THR; /**< \brief (Classd Offset: 0x10) Transmit Holding Register */\r
+ __O uint32_t CLASSD_IER; /**< \brief (Classd Offset: 0x14) Interrupt Enable Register */\r
+ __O uint32_t CLASSD_IDR; /**< \brief (Classd Offset: 0x18) Interrupt Disable Register */\r
+ __IO uint32_t CLASSD_IMR; /**< \brief (Classd Offset: 0x1C) Interrupt Mask Register */\r
+ __I uint32_t CLASSD_ISR; /**< \brief (Classd Offset: 0x20) Interrupt Status Register */\r
+ __I uint32_t Reserved1[48];\r
+ __IO uint32_t CLASSD_WPMR; /**< \brief (Classd Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t Reserved2[5];\r
+ __I uint32_t CLASSD_VERSION; /**< \brief (Classd Offset: 0xFC) IP Version Register */\r
+} Classd;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CLASSD_CR : (CLASSD Offset: 0x00) Control Register -------- */\r
+#define CLASSD_CR_SWRST (0x1u << 0) /**< \brief (CLASSD_CR) Software Reset */\r
+/* -------- CLASSD_MR : (CLASSD Offset: 0x04) Mode Register -------- */\r
+#define CLASSD_MR_LEN (0x1u << 0) /**< \brief (CLASSD_MR) Left Channel Enable */\r
+#define CLASSD_MR_LMUTE (0x1u << 1) /**< \brief (CLASSD_MR) Left Channel Mute */\r
+#define CLASSD_MR_REN (0x1u << 4) /**< \brief (CLASSD_MR) Right Channel Enable */\r
+#define CLASSD_MR_RMUTE (0x1u << 5) /**< \brief (CLASSD_MR) Right Channel Mute */\r
+#define CLASSD_MR_PWMTYP (0x1u << 8) /**< \brief (CLASSD_MR) PWM Modulation Type */\r
+#define CLASSD_MR_NON_OVERLAP (0x1u << 16) /**< \brief (CLASSD_MR) Non-Overlapping Enable */\r
+#define CLASSD_MR_NOVRVAL_Pos 20\r
+#define CLASSD_MR_NOVRVAL_Msk (0x3u << CLASSD_MR_NOVRVAL_Pos) /**< \brief (CLASSD_MR) Non-Overlapping Value */\r
+#define CLASSD_MR_NOVRVAL(value) ((CLASSD_MR_NOVRVAL_Msk & ((value) << CLASSD_MR_NOVRVAL_Pos)))\r
+#define CLASSD_MR_NOVRVAL_5NS (0x0u << 20) /**< \brief (CLASSD_MR) Non-overlapping time is 5 ns */\r
+#define CLASSD_MR_NOVRVAL_10NS (0x1u << 20) /**< \brief (CLASSD_MR) Non-overlapping time is 10 ns */\r
+#define CLASSD_MR_NOVRVAL_15NS (0x2u << 20) /**< \brief (CLASSD_MR) Non-overlapping time is 15 ns */\r
+#define CLASSD_MR_NOVRVAL_20NS (0x3u << 20) /**< \brief (CLASSD_MR) Non-overlapping time is 20 ns */\r
+/* -------- CLASSD_INTPMR : (CLASSD Offset: 0x08) Interpolator Mode Register -------- */\r
+#define CLASSD_INTPMR_ATTL_Pos 0\r
+#define CLASSD_INTPMR_ATTL_Msk (0x7fu << CLASSD_INTPMR_ATTL_Pos) /**< \brief (CLASSD_INTPMR) Left Channel Attenuation */\r
+#define CLASSD_INTPMR_ATTL(value) ((CLASSD_INTPMR_ATTL_Msk & ((value) << CLASSD_INTPMR_ATTL_Pos)))\r
+#define CLASSD_INTPMR_ATTR_Pos 8\r
+#define CLASSD_INTPMR_ATTR_Msk (0x7fu << CLASSD_INTPMR_ATTR_Pos) /**< \brief (CLASSD_INTPMR) Right Channel Attenuation */\r
+#define CLASSD_INTPMR_ATTR(value) ((CLASSD_INTPMR_ATTR_Msk & ((value) << CLASSD_INTPMR_ATTR_Pos)))\r
+#define CLASSD_INTPMR_DSPCLKFREQ (0x1u << 16) /**< \brief (CLASSD_INTPMR) DSP Clock Frequency */\r
+#define CLASSD_INTPMR_DSPCLKFREQ_12M288 (0x0u << 16) /**< \brief (CLASSD_INTPMR) DSP Clock (DSPCLK) is 12.288 MHz */\r
+#define CLASSD_INTPMR_DSPCLKFREQ_11M2896 (0x1u << 16) /**< \brief (CLASSD_INTPMR) DSP Clock (DSPCLK) is 11.2896 MHz */\r
+#define CLASSD_INTPMR_DEEMP (0x1u << 18) /**< \brief (CLASSD_INTPMR) Enable De-emphasis Filter */\r
+#define CLASSD_INTPMR_DEEMP_DISABLED (0x0u << 18) /**< \brief (CLASSD_INTPMR) De-emphasis filter is disabled */\r
+#define CLASSD_INTPMR_DEEMP_ENABLED (0x1u << 18) /**< \brief (CLASSD_INTPMR) De-emphasis filter is enabled */\r
+#define CLASSD_INTPMR_SWAP (0x1u << 19) /**< \brief (CLASSD_INTPMR) Swap Left and Right Channels */\r
+#define CLASSD_INTPMR_SWAP_LEFT_ON_LSB (0x0u << 19) /**< \brief (CLASSD_INTPMR) Left channel is on CLASSD_THR[15:0], right channel is on CLASSD_THR[31:16] */\r
+#define CLASSD_INTPMR_SWAP_RIGHT_ON_LSB (0x1u << 19) /**< \brief (CLASSD_INTPMR) Right channel is on CLASSD_THR[15:0], left channel is on CLASSD_THR[31:16] */\r
+#define CLASSD_INTPMR_FRAME_Pos 20\r
+#define CLASSD_INTPMR_FRAME_Msk (0x7u << CLASSD_INTPMR_FRAME_Pos) /**< \brief (CLASSD_INTPMR) CLASSD Incoming Data Sampling Frequency */\r
+#define CLASSD_INTPMR_FRAME(value) ((CLASSD_INTPMR_FRAME_Msk & ((value) << CLASSD_INTPMR_FRAME_Pos)))\r
+#define CLASSD_INTPMR_FRAME_FRAME_8K (0x0u << 20) /**< \brief (CLASSD_INTPMR) 8 kHz */\r
+#define CLASSD_INTPMR_FRAME_FRAME_16K (0x1u << 20) /**< \brief (CLASSD_INTPMR) 16 kHz */\r
+#define CLASSD_INTPMR_FRAME_FRAME_32K (0x2u << 20) /**< \brief (CLASSD_INTPMR) 32 kHz */\r
+#define CLASSD_INTPMR_FRAME_FRAME_48K (0x3u << 20) /**< \brief (CLASSD_INTPMR) 48 kHz */\r
+#define CLASSD_INTPMR_FRAME_FRAME_96K (0x4u << 20) /**< \brief (CLASSD_INTPMR) 96 kHz */\r
+#define CLASSD_INTPMR_FRAME_FRAME_22K (0x5u << 20) /**< \brief (CLASSD_INTPMR) 22.05 kHz */\r
+#define CLASSD_INTPMR_FRAME_FRAME_44K (0x6u << 20) /**< \brief (CLASSD_INTPMR) 44.1 kHz */\r
+#define CLASSD_INTPMR_FRAME_FRAME_88K (0x7u << 20) /**< \brief (CLASSD_INTPMR) 88.2 kHz */\r
+#define CLASSD_INTPMR_EQCFG_Pos 24\r
+#define CLASSD_INTPMR_EQCFG_Msk (0xfu << CLASSD_INTPMR_EQCFG_Pos) /**< \brief (CLASSD_INTPMR) Equalization Selection */\r
+#define CLASSD_INTPMR_EQCFG(value) ((CLASSD_INTPMR_EQCFG_Msk & ((value) << CLASSD_INTPMR_EQCFG_Pos)))\r
+#define CLASSD_INTPMR_EQCFG_FLAT (0x0u << 24) /**< \brief (CLASSD_INTPMR) Flat Response */\r
+#define CLASSD_INTPMR_EQCFG_BBOOST12 (0x1u << 24) /**< \brief (CLASSD_INTPMR) Bass boost +12 dB */\r
+#define CLASSD_INTPMR_EQCFG_BBOOST6 (0x2u << 24) /**< \brief (CLASSD_INTPMR) Bass boost +6 dB */\r
+#define CLASSD_INTPMR_EQCFG_BCUT12 (0x3u << 24) /**< \brief (CLASSD_INTPMR) Bass cut -12 dB */\r
+#define CLASSD_INTPMR_EQCFG_BCUT6 (0x4u << 24) /**< \brief (CLASSD_INTPMR) Bass cut -6 dB */\r
+#define CLASSD_INTPMR_EQCFG_MBOOST3 (0x5u << 24) /**< \brief (CLASSD_INTPMR) Medium boost +3 dB */\r
+#define CLASSD_INTPMR_EQCFG_MBOOST8 (0x6u << 24) /**< \brief (CLASSD_INTPMR) Medium boost +8 dB */\r
+#define CLASSD_INTPMR_EQCFG_MCUT3 (0x7u << 24) /**< \brief (CLASSD_INTPMR) Medium cut -3 dB */\r
+#define CLASSD_INTPMR_EQCFG_MCUT8 (0x8u << 24) /**< \brief (CLASSD_INTPMR) Medium cut -8 dB */\r
+#define CLASSD_INTPMR_EQCFG_TBOOST12 (0x9u << 24) /**< \brief (CLASSD_INTPMR) Treble boost +12 dB */\r
+#define CLASSD_INTPMR_EQCFG_TBOOST6 (0xAu << 24) /**< \brief (CLASSD_INTPMR) Treble boost +6 dB */\r
+#define CLASSD_INTPMR_EQCFG_TCUT12 (0xBu << 24) /**< \brief (CLASSD_INTPMR) Treble cut -12 dB */\r
+#define CLASSD_INTPMR_EQCFG_TCUT6 (0xCu << 24) /**< \brief (CLASSD_INTPMR) Treble cut -6 dB */\r
+#define CLASSD_INTPMR_MONO (0x1u << 28) /**< \brief (CLASSD_INTPMR) Mono Signal */\r
+#define CLASSD_INTPMR_MONO_DISABLED (0x0u << 28) /**< \brief (CLASSD_INTPMR) The signal is sent stereo to the left and right channels. */\r
+#define CLASSD_INTPMR_MONO_ENABLED (0x1u << 28) /**< \brief (CLASSD_INTPMR) The same signal is sent on both left and right channels. The sent signal is defined by the MONOMODE field value. */\r
+#define CLASSD_INTPMR_MONOMODE_Pos 29\r
+#define CLASSD_INTPMR_MONOMODE_Msk (0x3u << CLASSD_INTPMR_MONOMODE_Pos) /**< \brief (CLASSD_INTPMR) Mono Mode Selection */\r
+#define CLASSD_INTPMR_MONOMODE(value) ((CLASSD_INTPMR_MONOMODE_Msk & ((value) << CLASSD_INTPMR_MONOMODE_Pos)))\r
+#define CLASSD_INTPMR_MONOMODE_MONOMIX (0x0u << 29) /**< \brief (CLASSD_INTPMR) (left + right) / 2 is sent on both channels */\r
+#define CLASSD_INTPMR_MONOMODE_MONOSAT (0x1u << 29) /**< \brief (CLASSD_INTPMR) (left + right) is sent to both channels. If the sum is too high, the result is saturated. */\r
+#define CLASSD_INTPMR_MONOMODE_MONOLEFT (0x2u << 29) /**< \brief (CLASSD_INTPMR) THR[15:0] is sent on both left and right channels */\r
+#define CLASSD_INTPMR_MONOMODE_MONORIGHT (0x3u << 29) /**< \brief (CLASSD_INTPMR) THR[31:16] is sent on both left and right channels */\r
+/* -------- CLASSD_INTSR : (CLASSD Offset: 0x0C) Interpolator Status Register -------- */\r
+#define CLASSD_INTSR_CFGERR (0x1u << 0) /**< \brief (CLASSD_INTSR) Configuration Error */\r
+/* -------- CLASSD_THR : (CLASSD Offset: 0x10) Transmit Holding Register -------- */\r
+#define CLASSD_THR_LDATA_Pos 0\r
+#define CLASSD_THR_LDATA_Msk (0xffffu << CLASSD_THR_LDATA_Pos) /**< \brief (CLASSD_THR) Left Channel Data */\r
+#define CLASSD_THR_LDATA(value) ((CLASSD_THR_LDATA_Msk & ((value) << CLASSD_THR_LDATA_Pos)))\r
+#define CLASSD_THR_RDATA_Pos 16\r
+#define CLASSD_THR_RDATA_Msk (0xffffu << CLASSD_THR_RDATA_Pos) /**< \brief (CLASSD_THR) Right Channel Data */\r
+#define CLASSD_THR_RDATA(value) ((CLASSD_THR_RDATA_Msk & ((value) << CLASSD_THR_RDATA_Pos)))\r
+/* -------- CLASSD_IER : (CLASSD Offset: 0x14) Interrupt Enable Register -------- */\r
+#define CLASSD_IER_DATRDY (0x1u << 0) /**< \brief (CLASSD_IER) Data Ready */\r
+/* -------- CLASSD_IDR : (CLASSD Offset: 0x18) Interrupt Disable Register -------- */\r
+#define CLASSD_IDR_DATRDY (0x1u << 0) /**< \brief (CLASSD_IDR) Data Ready */\r
+/* -------- CLASSD_IMR : (CLASSD Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define CLASSD_IMR_DATRDY (0x1u << 0) /**< \brief (CLASSD_IMR) Data Ready */\r
+/* -------- CLASSD_ISR : (CLASSD Offset: 0x20) Interrupt Status Register -------- */\r
+#define CLASSD_ISR_DATRDY (0x1u << 0) /**< \brief (CLASSD_ISR) Data Ready */\r
+/* -------- CLASSD_WPMR : (CLASSD Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define CLASSD_WPMR_WPEN (0x1u << 0) /**< \brief (CLASSD_WPMR) Write Protection Enable */\r
+#define CLASSD_WPMR_WPKEY_Pos 8\r
+#define CLASSD_WPMR_WPKEY_Msk (0xffffffu << CLASSD_WPMR_WPKEY_Pos) /**< \brief (CLASSD_WPMR) Write Protection Key */\r
+#define CLASSD_WPMR_WPKEY(value) ((CLASSD_WPMR_WPKEY_Msk & ((value) << CLASSD_WPMR_WPKEY_Pos)))\r
+#define CLASSD_WPMR_WPKEY_PASSWD (0x434C44u << 8) /**< \brief (CLASSD_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- CLASSD_VERSION : (CLASSD Offset: 0xFC) IP Version Register -------- */\r
+#define CLASSD_VERSION_VERSION_Pos 0\r
+#define CLASSD_VERSION_VERSION_Msk (0xfffu << CLASSD_VERSION_VERSION_Pos) /**< \brief (CLASSD_VERSION) Version of the Hardware Module */\r
+#define CLASSD_VERSION_MFN_Pos 16\r
+#define CLASSD_VERSION_MFN_Msk (0x7u << CLASSD_VERSION_MFN_Pos) /**< \brief (CLASSD_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_CLASSD_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_FLEXCOM_COMPONENT_\r
+#define _SAMA5D2_FLEXCOM_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Flexible Serial Communication */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_FLEXCOM Flexible Serial Communication */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+\r
+/** \brief Usart hardware registers */\r
+typedef struct {\r
+ __O uint32_t US_CR; /**< \brief (Flexcom Offset: 0x200) USART Control Register */\r
+ __IO uint32_t US_MR; /**< \brief (Flexcom Offset: 0x204) USART Mode Register */\r
+ __O uint32_t US_IER; /**< \brief (Flexcom Offset: 0x208) USART Interrupt Enable Register */\r
+ __O uint32_t US_IDR; /**< \brief (Flexcom Offset: 0x20C) USART Interrupt Disable Register */\r
+ __I uint32_t US_IMR; /**< \brief (Flexcom Offset: 0x210) USART Interrupt Mask Register */\r
+ __I uint32_t US_CSR; /**< \brief (Flexcom Offset: 0x214) USART Channel Status Register */\r
+ __I uint32_t US_RHR; /**< \brief (Flexcom Offset: 0x218) USART Receive Holding Register */\r
+ __O uint32_t US_THR; /**< \brief (Flexcom Offset: 0x21C) USART Transmit Holding Register */\r
+ __IO uint32_t US_BRGR; /**< \brief (Flexcom Offset: 0x220) USART Baud Rate Generator Register */\r
+ __IO uint32_t US_RTOR; /**< \brief (Flexcom Offset: 0x224) USART Receiver Timeout Register */\r
+ __IO uint32_t US_TTGR; /**< \brief (Flexcom Offset: 0x228) USART Transmitter Timeguard Register */\r
+ __I uint32_t Reserved5[5];\r
+ __IO uint32_t US_FIDI; /**< \brief (Flexcom Offset: 0x240) USART FI DI Ratio Register */\r
+ __I uint32_t US_NER; /**< \brief (Flexcom Offset: 0x244) USART Number of Errors Register */\r
+ __I uint32_t Reserved6[1];\r
+ __IO uint32_t US_IF; /**< \brief (Flexcom Offset: 0x24C) USART IrDA Filter Register */\r
+ __IO uint32_t US_MAN; /**< \brief (Flexcom Offset: 0x250) USART Manchester Configuration Register */\r
+ __IO uint32_t US_LINMR; /**< \brief (Flexcom Offset: 0x254) USART LIN Mode Register */\r
+ __IO uint32_t US_LINIR; /**< \brief (Flexcom Offset: 0x258) USART LIN Identifier Register */\r
+ __I uint32_t US_LINBRR; /**< \brief (Flexcom Offset: 0x25C) USART LIN Baud Rate Register */\r
+ __I uint32_t Reserved7[12];\r
+ __IO uint32_t US_CMPR; /**< \brief (Flexcom Offset: 0x290) USART Comparison Register */\r
+ __I uint32_t Reserved8[3];\r
+ __IO uint32_t US_FMR; /**< \brief (Flexcom Offset: 0x2A0) USART FIFO Mode Register */\r
+ __I uint32_t US_FLR; /**< \brief (Flexcom Offset: 0x2A4) USART FIFO Level Register */\r
+ __O uint32_t US_FIER; /**< \brief (Flexcom Offset: 0x2A8) USART FIFO Interrupt Enable Register */\r
+ __O uint32_t US_FIDR; /**< \brief (Flexcom Offset: 0x2AC) USART FIFO Interrupt Disable Register */\r
+ __I uint32_t US_FIMR; /**< \brief (Flexcom Offset: 0x2B0) USART FIFO Interrupt Mask Register */\r
+ __I uint32_t US_FESR; /**< \brief (Flexcom Offset: 0x2B4) USART FIFO Event Status Register */\r
+ __I uint32_t Reserved9[11];\r
+ __IO uint32_t US_WPMR; /**< \brief (Flexcom Offset: 0x2E4) USART Write Protection Mode Register */\r
+ __I uint32_t US_WPSR; /**< \brief (Flexcom Offset: 0x2E8) USART Write Protection Status Register */\r
+ __I uint32_t Reserved10[4];\r
+ __I uint32_t US_VERSION; /**< \brief (Flexcom Offset: 0x2FC) USART Version Register */\r
+} Usart;\r
+\r
+/** \brief Spi hardware registers */\r
+typedef struct {\r
+ __O uint32_t SPI_CR; /**< \brief (Flexcom Offset: 0x400) SPI Control Register */\r
+ __IO uint32_t SPI_MR; /**< \brief (Flexcom Offset: 0x404) SPI Mode Register */\r
+ __I uint32_t SPI_RDR; /**< \brief (Flexcom Offset: 0x408) SPI Receive Data Register */\r
+ __O uint32_t SPI_TDR; /**< \brief (Flexcom Offset: 0x40C) SPI Transmit Data Register */\r
+ __I uint32_t SPI_SR; /**< \brief (Flexcom Offset: 0x410) SPI Status Register */\r
+ __O uint32_t SPI_IER; /**< \brief (Flexcom Offset: 0x414) SPI Interrupt Enable Register */\r
+ __O uint32_t SPI_IDR; /**< \brief (Flexcom Offset: 0x418) SPI Interrupt Disable Register */\r
+ __I uint32_t SPI_IMR; /**< \brief (Flexcom Offset: 0x41C) SPI Interrupt Mask Register */\r
+ __I uint32_t Reserved1[4];\r
+ __IO uint32_t SPI_CSR[2]; /**< \brief (Flexcom Offset: 0x430) SPI Chip Select Register */\r
+ __I uint32_t Reserved2[2];\r
+ __IO uint32_t SPI_FMR; /**< \brief (Flexcom Offset: 0x440) SPI FIFO Mode Register */\r
+ __I uint32_t SPI_FLR; /**< \brief (Flexcom Offset: 0x444) SPI FIFO Level Register */\r
+ __IO uint32_t SPI_CMPR; /**< \brief (Flexcom Offset: 0x448) SPI Comparison Register */\r
+ __I uint32_t Reserved3[38];\r
+ __IO uint32_t SPI_WPMR; /**< \brief (Flexcom Offset: 0x4E4) SPI Write Protection Mode Register */\r
+ __I uint32_t SPI_WPSR; /**< \brief (Flexcom Offset: 0x4E8) SPI Write Protection Status Register */\r
+ __I uint32_t Reserved4[4];\r
+ __I uint32_t SPI_VERSION; /**< \brief (Flexcom Offset: 0x4FC) SPI Version Register */\r
+} Spi;\r
+\r
+/** \brief Twi hardware registers */\r
+typedef struct {\r
+ __O uint32_t TWI_CR; /**< \brief (Flexcom Offset: 0x600) TWI Control Register */\r
+ __IO uint32_t TWI_MMR; /**< \brief (Flexcom Offset: 0x604) TWI Master Mode Register */\r
+ __IO uint32_t TWI_SMR; /**< \brief (Flexcom Offset: 0x608) TWI Slave Mode Register */\r
+ __IO uint32_t TWI_IADR; /**< \brief (Flexcom Offset: 0x60C) TWI Internal Address Register */\r
+ __IO uint32_t TWI_CWGR; /**< \brief (Flexcom Offset: 0x610) TWI Clock Waveform Generator Register */\r
+ __I uint32_t Reserved17[3];\r
+ __I uint32_t TWI_SR; /**< \brief (Flexcom Offset: 0x620) TWI Status Register */\r
+ __O uint32_t TWI_IER; /**< \brief (Flexcom Offset: 0x624) TWI Interrupt Enable Register */\r
+ __O uint32_t TWI_IDR; /**< \brief (Flexcom Offset: 0x628) TWI Interrupt Disable Register */\r
+ __I uint32_t TWI_IMR; /**< \brief (Flexcom Offset: 0x62C) TWI Interrupt Mask Register */\r
+ __I uint32_t TWI_RHR; /**< \brief (Flexcom Offset: 0x630) TWI Receive Holding Register */\r
+ __O uint32_t TWI_THR; /**< \brief (Flexcom Offset: 0x634) TWI Transmit Holding Register */\r
+ __IO uint32_t TWI_SMBTR; /**< \brief (Flexcom Offset: 0x638) TWI SMBus Timing Register */\r
+ __I uint32_t Reserved18[1];\r
+ __IO uint32_t TWI_ACR; /**< \brief (Flexcom Offset: 0x640) TWI Alternative Command Register */\r
+ __IO uint32_t TWI_FILTR; /**< \brief (Flexcom Offset: 0x644) TWI Filter Register */\r
+ __I uint32_t Reserved19[1];\r
+ __IO uint32_t TWI_SWMR; /**< \brief (Flexcom Offset: 0x64C) TWI SleepWalking Matching Register */\r
+ __IO uint32_t TWI_FMR; /**< \brief (Flexcom Offset: 0x650) TWI FIFO Mode Register */\r
+ __I uint32_t TWI_FLR; /**< \brief (Flexcom Offset: 0x654) TWI FIFO Level Register */\r
+ __I uint32_t Reserved20[2];\r
+ __I uint32_t TWI_FSR; /**< \brief (Flexcom Offset: 0x660) TWI FIFO Status Register */\r
+ __O uint32_t TWI_FIER; /**< \brief (Flexcom Offset: 0x664) TWI FIFO Interrupt Enable Register */\r
+ __O uint32_t TWI_FIDR; /**< \brief (Flexcom Offset: 0x668) TWI FIFO Interrupt Disable Register */\r
+ __I uint32_t TWI_FIMR; /**< \brief (Flexcom Offset: 0x66C) TWI FIFO Interrupt Mask Register */\r
+ __I uint32_t Reserved21[24];\r
+ __I uint32_t TWI_DR; /**< \brief (Flexcom Offset: 0x6D0) TWI Debug Register */\r
+ __I uint32_t Reserved22[4];\r
+ __IO uint32_t TWI_WPMR; /**< \brief (Flexcom Offset: 0x6E4) TWI Protection Mode Register */\r
+ __I uint32_t TWI_WPSR; /**< \brief (Flexcom Offset: 0x6E8) TWI Protection Status Register */\r
+ __I uint32_t Reserved23[4];\r
+ __I uint32_t TWI_VER; /**< \brief (Flexcom Offset: 0x6FC) TWI Version Register */\r
+} Twi;\r
+\r
+/** \brief Flexcom hardware registers */\r
+typedef struct {\r
+ __IO uint32_t FLEX_MR; /**< \brief (Flexcom Offset: 0x000) FLEXCOM Mode Register */\r
+ __I uint32_t Reserved1[3];\r
+ __I uint32_t FLEX_RHR; /**< \brief (Flexcom Offset: 0x010) FLEXCOM Receive Holding Register */\r
+ __I uint32_t Reserved2[3];\r
+ __IO uint32_t FLEX_THR; /**< \brief (Flexcom Offset: 0x020) FLEXCOM Transmit Holding Register */\r
+ __I uint32_t Reserved3[54];\r
+ __I uint32_t FLEX_VERSION; /**< \brief (Flexcom Offset: 0x0FC) FLEXCOM Version Register */\r
+ __I uint32_t Reserved4[64];\r
+ Usart usart;\r
+ __I uint32_t Reserved11[64];\r
+ Spi spi;\r
+ __I uint32_t Reserved16[64];\r
+ Twi twi;\r
+} Flexcom;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- FLEX_MR : (FLEXCOM Offset: 0x000) FLEXCOM Mode Register -------- */\r
+#define FLEX_MR_OPMODE_Pos 0\r
+#define FLEX_MR_OPMODE_Msk (0x3u << FLEX_MR_OPMODE_Pos) /**< \brief (FLEX_MR) FLEXCOM Operating Mode */\r
+#define FLEX_MR_OPMODE(value) ((FLEX_MR_OPMODE_Msk & ((value) << FLEX_MR_OPMODE_Pos)))\r
+#define FLEX_MR_OPMODE_NO_COM (0x0u << 0) /**< \brief (FLEX_MR) No communication */\r
+#define FLEX_MR_OPMODE_USART (0x1u << 0) /**< \brief (FLEX_MR) All related UART related protocols are selected (RS232, RS485, IrDA, ISO7816, LIN,)All SPI/TWI related registers are not accessible and have no impact on IOs. */\r
+#define FLEX_MR_OPMODE_SPI (0x2u << 0) /**< \brief (FLEX_MR) SPI operating mode is selected.All USART/TWI related registers are not accessible and have no impact on IOs. */\r
+#define FLEX_MR_OPMODE_TWI (0x3u << 0) /**< \brief (FLEX_MR) All related TWI protocols are selected (TWI, SMBus). All USART/SPI related registers are not accessible and have no impact on IOs. */\r
+/* -------- FLEX_RHR : (FLEXCOM Offset: 0x010) FLEXCOM Receive Holding Register -------- */\r
+#define FLEX_RHR_RXDATA_Pos 0\r
+#define FLEX_RHR_RXDATA_Msk (0xffffu << FLEX_RHR_RXDATA_Pos) /**< \brief (FLEX_RHR) Receive Data */\r
+/* -------- FLEX_THR : (FLEXCOM Offset: 0x020) FLEXCOM Transmit Holding Register -------- */\r
+#define FLEX_THR_TXDATA_Pos 0\r
+#define FLEX_THR_TXDATA_Msk (0xffffu << FLEX_THR_TXDATA_Pos) /**< \brief (FLEX_THR) Transmit Data */\r
+#define FLEX_THR_TXDATA(value) ((FLEX_THR_TXDATA_Msk & ((value) << FLEX_THR_TXDATA_Pos)))\r
+/* -------- FLEX_VERSION : (FLEXCOM Offset: 0x0FC) FLEXCOM Version Register -------- */\r
+#define FLEX_VERSION_VERSION_Pos 0\r
+#define FLEX_VERSION_VERSION_Msk (0xfffu << FLEX_VERSION_VERSION_Pos) /**< \brief (FLEX_VERSION) Hardware Module Version */\r
+#define FLEX_VERSION_MFN_Pos 16\r
+#define FLEX_VERSION_MFN_Msk (0x7u << FLEX_VERSION_MFN_Pos) /**< \brief (FLEX_VERSION) Metal Fix Number */\r
+/* -------- US_CR : (FLEXCOM Offset: 0x200) USART Control Register -------- */\r
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */\r
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */\r
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */\r
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */\r
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */\r
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */\r
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */\r
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */\r
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */\r
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */\r
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */\r
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */\r
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */\r
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */\r
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */\r
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */\r
+#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */\r
+#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wake-up Signal */\r
+#define US_CR_TXFCLR (0x1u << 24) /**< \brief (US_CR) Transmit FIFO Clear */\r
+#define US_CR_RXFCLR (0x1u << 25) /**< \brief (US_CR) Receive FIFO Clear */\r
+#define US_CR_TXFLCLR (0x1u << 26) /**< \brief (US_CR) Transmit FIFO Lock CLEAR */\r
+#define US_CR_REQCLR (0x1u << 28) /**< \brief (US_CR) Request to Clear the Comparison Trigger */\r
+#define US_CR_FIFOEN (0x1u << 30) /**< \brief (US_CR) FIFO Enable */\r
+#define US_CR_FIFODIS (0x1u << 31) /**< \brief (US_CR) FIFO Disable */\r
+/* -------- US_MR : (FLEXCOM Offset: 0x204) USART Mode Register -------- */\r
+#define US_MR_USART_MODE_Pos 0\r
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */\r
+#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)))\r
+#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */\r
+#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */\r
+#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */\r
+#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */\r
+#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */\r
+#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */\r
+#define US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN master */\r
+#define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave */\r
+#define US_MR_USCLKS_Pos 4\r
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */\r
+#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)))\r
+#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */\r
+#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV = 8) is selected */\r
+#define US_MR_USCLKS_PMC_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */\r
+#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) External pin SCK is selected */\r
+#define US_MR_CHRL_Pos 6\r
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */\r
+#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)))\r
+#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */\r
+#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */\r
+#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */\r
+#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */\r
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */\r
+#define US_MR_PAR_Pos 9\r
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */\r
+#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)))\r
+#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */\r
+#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */\r
+#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */\r
+#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */\r
+#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */\r
+#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */\r
+#define US_MR_NBSTOP_Pos 12\r
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */\r
+#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)))\r
+#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */\r
+#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */\r
+#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */\r
+#define US_MR_CHMODE_Pos 14\r
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */\r
+#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)))\r
+#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */\r
+#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */\r
+#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */\r
+#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */\r
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */\r
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */\r
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */\r
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */\r
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */\r
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */\r
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */\r
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */\r
+#define US_MR_MAX_ITERATION_Pos 24\r
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */\r
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))\r
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */\r
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */\r
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */\r
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */\r
+/* -------- US_IER : (FLEXCOM Offset: 0x208) USART Interrupt Enable Register -------- */\r
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */\r
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */\r
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */\r
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */\r
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */\r
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */\r
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Timeout Interrupt Enable */\r
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */\r
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */\r
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */\r
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */\r
+#define US_IER_CMP (0x1u << 22) /**< \brief (US_IER) Comparison Interrupt Enable */\r
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */\r
+#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */\r
+#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */\r
+#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */\r
+#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */\r
+#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */\r
+#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */\r
+#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */\r
+#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */\r
+#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */\r
+#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */\r
+/* -------- US_IDR : (FLEXCOM Offset: 0x20C) USART Interrupt Disable Register -------- */\r
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */\r
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */\r
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */\r
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */\r
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */\r
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */\r
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Timeout Interrupt Disable */\r
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */\r
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */\r
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */\r
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */\r
+#define US_IDR_CMP (0x1u << 22) /**< \brief (US_IDR) Comparison Interrupt Disable */\r
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */\r
+#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */\r
+#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */\r
+#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */\r
+#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */\r
+#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */\r
+#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */\r
+#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */\r
+#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */\r
+#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */\r
+#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */\r
+/* -------- US_IMR : (FLEXCOM Offset: 0x210) USART Interrupt Mask Register -------- */\r
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */\r
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */\r
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */\r
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */\r
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */\r
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */\r
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Timeout Interrupt Mask */\r
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */\r
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */\r
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */\r
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */\r
+#define US_IMR_CMP (0x1u << 22) /**< \brief (US_IMR) Comparison Interrupt Mask */\r
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */\r
+#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */\r
+#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */\r
+#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */\r
+#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */\r
+#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */\r
+#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */\r
+#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */\r
+#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */\r
+#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */\r
+#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */\r
+/* -------- US_CSR : (FLEXCOM Offset: 0x214) USART Channel Status Register -------- */\r
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */\r
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */\r
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */\r
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */\r
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */\r
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */\r
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Timeout */\r
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */\r
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached */\r
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */\r
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */\r
+#define US_CSR_CMP (0x1u << 22) /**< \brief (US_CSR) Comparison Status */\r
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */\r
+#define US_CSR_MANE (0x1u << 24) /**< \brief (US_CSR) Manchester Error */\r
+#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */\r
+#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */\r
+#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */\r
+#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */\r
+#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */\r
+#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */\r
+#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */\r
+#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */\r
+#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */\r
+#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error */\r
+#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error */\r
+/* -------- US_RHR : (FLEXCOM Offset: 0x218) USART Receive Holding Register -------- */\r
+#define US_RHR_RXCHR_Pos 0\r
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */\r
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */\r
+#define US_RHR_RXCHR0_Pos 0\r
+#define US_RHR_RXCHR0_Msk (0xffu << US_RHR_RXCHR0_Pos) /**< \brief (US_RHR) Received Character */\r
+#define US_RHR_RXCHR1_Pos 8\r
+#define US_RHR_RXCHR1_Msk (0xffu << US_RHR_RXCHR1_Pos) /**< \brief (US_RHR) Received Character */\r
+#define US_RHR_RXCHR2_Pos 16\r
+#define US_RHR_RXCHR2_Msk (0xffu << US_RHR_RXCHR2_Pos) /**< \brief (US_RHR) Received Character */\r
+#define US_RHR_RXCHR3_Pos 24\r
+#define US_RHR_RXCHR3_Msk (0xffu << US_RHR_RXCHR3_Pos) /**< \brief (US_RHR) Received Character */\r
+/* -------- US_THR : (FLEXCOM Offset: 0x21C) USART Transmit Holding Register -------- */\r
+#define US_THR_TXCHR_Pos 0\r
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))\r
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */\r
+#define US_THR_TXCHR0_Pos 0\r
+#define US_THR_TXCHR0_Msk (0xffu << US_THR_TXCHR0_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR0(value) ((US_THR_TXCHR0_Msk & ((value) << US_THR_TXCHR0_Pos)))\r
+#define US_THR_TXCHR1_Pos 8\r
+#define US_THR_TXCHR1_Msk (0xffu << US_THR_TXCHR1_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR1(value) ((US_THR_TXCHR1_Msk & ((value) << US_THR_TXCHR1_Pos)))\r
+#define US_THR_TXCHR2_Pos 16\r
+#define US_THR_TXCHR2_Msk (0xffu << US_THR_TXCHR2_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR2(value) ((US_THR_TXCHR2_Msk & ((value) << US_THR_TXCHR2_Pos)))\r
+#define US_THR_TXCHR3_Pos 24\r
+#define US_THR_TXCHR3_Msk (0xffu << US_THR_TXCHR3_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR3(value) ((US_THR_TXCHR3_Msk & ((value) << US_THR_TXCHR3_Pos)))\r
+/* -------- US_BRGR : (FLEXCOM Offset: 0x220) USART Baud Rate Generator Register -------- */\r
+#define US_BRGR_CD_Pos 0\r
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */\r
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))\r
+#define US_BRGR_FP_Pos 16\r
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */\r
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))\r
+/* -------- US_RTOR : (FLEXCOM Offset: 0x224) USART Receiver Timeout Register -------- */\r
+#define US_RTOR_TO_Pos 0\r
+#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Timeout Value */\r
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))\r
+/* -------- US_TTGR : (FLEXCOM Offset: 0x228) USART Transmitter Timeguard Register -------- */\r
+#define US_TTGR_TG_Pos 0\r
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */\r
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))\r
+/* -------- US_FIDI : (FLEXCOM Offset: 0x240) USART FI DI Ratio Register -------- */\r
+#define US_FIDI_FI_DI_RATIO_Pos 0\r
+#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */\r
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))\r
+/* -------- US_NER : (FLEXCOM Offset: 0x244) USART Number of Errors Register -------- */\r
+#define US_NER_NB_ERRORS_Pos 0\r
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */\r
+/* -------- US_IF : (FLEXCOM Offset: 0x24C) USART IrDA Filter Register -------- */\r
+#define US_IF_IRDA_FILTER_Pos 0\r
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */\r
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))\r
+/* -------- US_MAN : (FLEXCOM Offset: 0x250) USART Manchester Configuration Register -------- */\r
+#define US_MAN_TX_PL_Pos 0\r
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */\r
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))\r
+#define US_MAN_TX_PP_Pos 8\r
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */\r
+#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)))\r
+#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */\r
+#define US_MAN_RX_PL_Pos 16\r
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */\r
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))\r
+#define US_MAN_RX_PP_Pos 24\r
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */\r
+#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)))\r
+#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */\r
+#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */\r
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */\r
+#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) Receiver Idle Value */\r
+/* -------- US_LINMR : (FLEXCOM Offset: 0x254) USART LIN Mode Register -------- */\r
+#define US_LINMR_NACT_Pos 0\r
+#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */\r
+#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)))\r
+#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */\r
+#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */\r
+#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */\r
+#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */\r
+#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */\r
+#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */\r
+#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */\r
+#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */\r
+#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wake-up Signal Type */\r
+#define US_LINMR_DLC_Pos 8\r
+#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */\r
+#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))\r
+#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */\r
+#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */\r
+/* -------- US_LINIR : (FLEXCOM Offset: 0x258) USART LIN Identifier Register -------- */\r
+#define US_LINIR_IDCHR_Pos 0\r
+#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */\r
+#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))\r
+/* -------- US_LINBRR : (FLEXCOM Offset: 0x25C) USART LIN Baud Rate Register -------- */\r
+#define US_LINBRR_LINCD_Pos 0\r
+#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */\r
+#define US_LINBRR_LINFP_Pos 16\r
+#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */\r
+/* -------- US_CMPR : (FLEXCOM Offset: 0x290) USART Comparison Register -------- */\r
+#define US_CMPR_VAL1_Pos 0\r
+#define US_CMPR_VAL1_Msk (0x1ffu << US_CMPR_VAL1_Pos) /**< \brief (US_CMPR) First Comparison Value for Received Character */\r
+#define US_CMPR_VAL1(value) ((US_CMPR_VAL1_Msk & ((value) << US_CMPR_VAL1_Pos)))\r
+#define US_CMPR_CMPMODE (0x1u << 12) /**< \brief (US_CMPR) Comparison Mode */\r
+#define US_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (US_CMPR) Any character is received and comparison function drives CMP flag. */\r
+#define US_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (US_CMPR) Comparison condition must be met to start reception. */\r
+#define US_CMPR_CMPPAR (0x1u << 14) /**< \brief (US_CMPR) Compare Parity */\r
+#define US_CMPR_VAL2_Pos 16\r
+#define US_CMPR_VAL2_Msk (0x1ffu << US_CMPR_VAL2_Pos) /**< \brief (US_CMPR) Second Comparison Value for Received Character */\r
+#define US_CMPR_VAL2(value) ((US_CMPR_VAL2_Msk & ((value) << US_CMPR_VAL2_Pos)))\r
+/* -------- US_FMR : (FLEXCOM Offset: 0x2A0) USART FIFO Mode Register -------- */\r
+#define US_FMR_TXRDYM_Pos 0\r
+#define US_FMR_TXRDYM_Msk (0x3u << US_FMR_TXRDYM_Pos) /**< \brief (US_FMR) Transmitter Ready Mode */\r
+#define US_FMR_TXRDYM(value) ((US_FMR_TXRDYM_Msk & ((value) << US_FMR_TXRDYM_Pos)))\r
+#define US_FMR_TXRDYM_ONE_DATA (0x0u << 0) /**< \brief (US_FMR) TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO */\r
+#define US_FMR_TXRDYM_TWO_DATA (0x1u << 0) /**< \brief (US_FMR) TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO */\r
+#define US_FMR_TXRDYM_FOUR_DATA (0x2u << 0) /**< \brief (US_FMR) TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO */\r
+#define US_FMR_RXRDYM_Pos 4\r
+#define US_FMR_RXRDYM_Msk (0x3u << US_FMR_RXRDYM_Pos) /**< \brief (US_FMR) Receiver Ready Mode */\r
+#define US_FMR_RXRDYM(value) ((US_FMR_RXRDYM_Msk & ((value) << US_FMR_RXRDYM_Pos)))\r
+#define US_FMR_RXRDYM_ONE_DATA (0x0u << 4) /**< \brief (US_FMR) RXRDY will be at level '1' when at least one unread data is in the Receive FIFO */\r
+#define US_FMR_RXRDYM_TWO_DATA (0x1u << 4) /**< \brief (US_FMR) RXRDY will be at level '1' when at least two unread data are in the Receive FIFO */\r
+#define US_FMR_RXRDYM_FOUR_DATA (0x2u << 4) /**< \brief (US_FMR) RXRDY will be at level '1' when at least four unread data are in the Receive FIFO */\r
+#define US_FMR_FRTSC (0x1u << 7) /**< \brief (US_FMR) FIFO RTS pin Control enable (Hardware Handshaking mode only) */\r
+#define US_FMR_TXFTHRES_Pos 8\r
+#define US_FMR_TXFTHRES_Msk (0x3fu << US_FMR_TXFTHRES_Pos) /**< \brief (US_FMR) Transmit FIFO Threshold */\r
+#define US_FMR_TXFTHRES(value) ((US_FMR_TXFTHRES_Msk & ((value) << US_FMR_TXFTHRES_Pos)))\r
+#define US_FMR_RXFTHRES_Pos 16\r
+#define US_FMR_RXFTHRES_Msk (0x3fu << US_FMR_RXFTHRES_Pos) /**< \brief (US_FMR) Receive FIFO Threshold */\r
+#define US_FMR_RXFTHRES(value) ((US_FMR_RXFTHRES_Msk & ((value) << US_FMR_RXFTHRES_Pos)))\r
+#define US_FMR_RXFTHRES2_Pos 24\r
+#define US_FMR_RXFTHRES2_Msk (0x3fu << US_FMR_RXFTHRES2_Pos) /**< \brief (US_FMR) Receive FIFO Threshold 2 */\r
+#define US_FMR_RXFTHRES2(value) ((US_FMR_RXFTHRES2_Msk & ((value) << US_FMR_RXFTHRES2_Pos)))\r
+/* -------- US_FLR : (FLEXCOM Offset: 0x2A4) USART FIFO Level Register -------- */\r
+#define US_FLR_TXFL_Pos 0\r
+#define US_FLR_TXFL_Msk (0x3fu << US_FLR_TXFL_Pos) /**< \brief (US_FLR) Transmit FIFO Level */\r
+#define US_FLR_RXFL_Pos 16\r
+#define US_FLR_RXFL_Msk (0x3fu << US_FLR_RXFL_Pos) /**< \brief (US_FLR) Receive FIFO Level */\r
+/* -------- US_FIER : (FLEXCOM Offset: 0x2A8) USART FIFO Interrupt Enable Register -------- */\r
+#define US_FIER_TXFEF (0x1u << 0) /**< \brief (US_FIER) TXFEF Interrupt Enable */\r
+#define US_FIER_TXFFF (0x1u << 1) /**< \brief (US_FIER) TXFFF Interrupt Enable */\r
+#define US_FIER_TXFTHF (0x1u << 2) /**< \brief (US_FIER) TXFTHF Interrupt Enable */\r
+#define US_FIER_RXFEF (0x1u << 3) /**< \brief (US_FIER) RXFEF Interrupt Enable */\r
+#define US_FIER_RXFFF (0x1u << 4) /**< \brief (US_FIER) RXFFF Interrupt Enable */\r
+#define US_FIER_RXFTHF (0x1u << 5) /**< \brief (US_FIER) RXFTHF Interrupt Enable */\r
+#define US_FIER_TXFPTEF (0x1u << 6) /**< \brief (US_FIER) TXFPTEF Interrupt Enable */\r
+#define US_FIER_RXFPTEF (0x1u << 7) /**< \brief (US_FIER) RXFPTEF Interrupt Enable */\r
+#define US_FIER_RXFTHF2 (0x1u << 9) /**< \brief (US_FIER) RXFTHF2 Interrupt Enable */\r
+/* -------- US_FIDR : (FLEXCOM Offset: 0x2AC) USART FIFO Interrupt Disable Register -------- */\r
+#define US_FIDR_TXFEF (0x1u << 0) /**< \brief (US_FIDR) TXFEF Interrupt Disable */\r
+#define US_FIDR_TXFFF (0x1u << 1) /**< \brief (US_FIDR) TXFFF Interrupt Disable */\r
+#define US_FIDR_TXFTHF (0x1u << 2) /**< \brief (US_FIDR) TXFTHF Interrupt Disable */\r
+#define US_FIDR_RXFEF (0x1u << 3) /**< \brief (US_FIDR) RXFEF Interrupt Disable */\r
+#define US_FIDR_RXFFF (0x1u << 4) /**< \brief (US_FIDR) RXFFF Interrupt Disable */\r
+#define US_FIDR_RXFTHF (0x1u << 5) /**< \brief (US_FIDR) RXFTHF Interrupt Disable */\r
+#define US_FIDR_TXFPTEF (0x1u << 6) /**< \brief (US_FIDR) TXFPTEF Interrupt Disable */\r
+#define US_FIDR_RXFPTEF (0x1u << 7) /**< \brief (US_FIDR) RXFPTEF Interrupt Disable */\r
+#define US_FIDR_RXFTHF2 (0x1u << 9) /**< \brief (US_FIDR) RXFTHF2 Interrupt Disable */\r
+/* -------- US_FIMR : (FLEXCOM Offset: 0x2B0) USART FIFO Interrupt Mask Register -------- */\r
+#define US_FIMR_TXFEF (0x1u << 0) /**< \brief (US_FIMR) TXFEF Interrupt Mask */\r
+#define US_FIMR_TXFFF (0x1u << 1) /**< \brief (US_FIMR) TXFFF Interrupt Mask */\r
+#define US_FIMR_TXFTHF (0x1u << 2) /**< \brief (US_FIMR) TXFTHF Interrupt Mask */\r
+#define US_FIMR_RXFEF (0x1u << 3) /**< \brief (US_FIMR) RXFEF Interrupt Mask */\r
+#define US_FIMR_RXFFF (0x1u << 4) /**< \brief (US_FIMR) RXFFF Interrupt Mask */\r
+#define US_FIMR_RXFTHF (0x1u << 5) /**< \brief (US_FIMR) RXFTHF Interrupt Mask */\r
+#define US_FIMR_TXFPTEF (0x1u << 6) /**< \brief (US_FIMR) TXFPTEF Interrupt Mask */\r
+#define US_FIMR_RXFPTEF (0x1u << 7) /**< \brief (US_FIMR) RXFPTEF Interrupt Mask */\r
+#define US_FIMR_RXFTHF2 (0x1u << 9) /**< \brief (US_FIMR) RXFTHF2 Interrupt Mask */\r
+/* -------- US_FESR : (FLEXCOM Offset: 0x2B4) USART FIFO Event Status Register -------- */\r
+#define US_FESR_TXFEF (0x1u << 0) /**< \brief (US_FESR) Transmit FIFO Empty Flag (cleared by writing RSTSTA bit in US_CR) */\r
+#define US_FESR_TXFFF (0x1u << 1) /**< \brief (US_FESR) Transmit FIFO Full Flag (cleared by writing RSTSTA bit in US_CR) */\r
+#define US_FESR_TXFTHF (0x1u << 2) /**< \brief (US_FESR) Transmit FIFO Threshold Flag (cleared by writing RSTSTA bit in US_CR) */\r
+#define US_FESR_RXFEF (0x1u << 3) /**< \brief (US_FESR) Receive FIFO Empty Flag (cleared by writing RSTSTA bit in US_CR) */\r
+#define US_FESR_RXFFF (0x1u << 4) /**< \brief (US_FESR) Receive FIFO Full Flag (cleared by writing RSTSTA bit in US_CR) */\r
+#define US_FESR_RXFTHF (0x1u << 5) /**< \brief (US_FESR) Receive FIFO Threshold Flag (cleared by writing RSTSTA bit in US_CR) */\r
+#define US_FESR_TXFPTEF (0x1u << 6) /**< \brief (US_FESR) Transmit FIFO Pointer Error Flag */\r
+#define US_FESR_RXFPTEF (0x1u << 7) /**< \brief (US_FESR) Receive FIFO Pointer Error Flag */\r
+#define US_FESR_TXFLOCK (0x1u << 8) /**< \brief (US_FESR) Transmit FIFO Lock */\r
+#define US_FESR_RXFTHF2 (0x1u << 9) /**< \brief (US_FESR) Receive FIFO Threshold Flag 2 (cleared by writing RSTSTA bit in US_CR) */\r
+/* -------- US_WPMR : (FLEXCOM Offset: 0x2E4) USART Write Protection Mode Register -------- */\r
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */\r
+#define US_WPMR_WPKEY_Pos 8\r
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */\r
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))\r
+#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */\r
+/* -------- US_WPSR : (FLEXCOM Offset: 0x2E8) USART Write Protection Status Register -------- */\r
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */\r
+#define US_WPSR_WPVSRC_Pos 8\r
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */\r
+/* -------- US_VERSION : (FLEXCOM Offset: 0x2FC) USART Version Register -------- */\r
+#define US_VERSION_VERSION_Pos 0\r
+#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) Hardware Module Version */\r
+#define US_VERSION_MFN_Pos 16\r
+#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) Metal Fix Number */\r
+/* -------- SPI_CR : (FLEXCOM Offset: 0x400) SPI Control Register -------- */\r
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */\r
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */\r
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */\r
+#define SPI_CR_REQCLR (0x1u << 12) /**< \brief (SPI_CR) Request to Clear the Comparison Trigger */\r
+#define SPI_CR_TXFCLR (0x1u << 16) /**< \brief (SPI_CR) Transmit FIFO Clear */\r
+#define SPI_CR_RXFCLR (0x1u << 17) /**< \brief (SPI_CR) Receive FIFO Clear */\r
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */\r
+#define SPI_CR_FIFOEN (0x1u << 30) /**< \brief (SPI_CR) FIFO Enable */\r
+#define SPI_CR_FIFODIS (0x1u << 31) /**< \brief (SPI_CR) FIFO Disable */\r
+/* -------- SPI_MR : (FLEXCOM Offset: 0x404) SPI Mode Register -------- */\r
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */\r
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */\r
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */\r
+#define SPI_MR_BRSRCCLK (0x1u << 3) /**< \brief (SPI_MR) Bit Rate Source Clock */\r
+#define SPI_MR_BRSRCCLK_PERIPH_CLK (0x0u << 3) /**< \brief (SPI_MR) The peripheral clock is the source clock for the bit rate generation. */\r
+#define SPI_MR_BRSRCCLK_PMC_PCK (0x1u << 3) /**< \brief (SPI_MR) PMC PCKx is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. */\r
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */\r
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */\r
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */\r
+#define SPI_MR_CMPMODE (0x1u << 12) /**< \brief (SPI_MR) Comparison Mode */\r
+#define SPI_MR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (SPI_MR) Any character is received and comparison function drives CMP flag. */\r
+#define SPI_MR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (SPI_MR) Comparison condition must be met to start reception of all incoming characters until REQCLR is set. */\r
+#define SPI_MR_PCS_Pos 16\r
+#define SPI_MR_PCS_Msk (0xFu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */\r
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))\r
+#define SPI_MR_DLYBCS_Pos 24\r
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */\r
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))\r
+/* -------- SPI_RDR : (FLEXCOM Offset: 0x408) SPI Receive Data Register -------- */\r
+#define SPI_RDR_RD_Pos 0\r
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_PCS_Pos 16\r
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */\r
+#define SPI_RDR_RD0_Pos 0\r
+#define SPI_RDR_RD0_Msk (0xffu << SPI_RDR_RD0_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD1_Pos 8\r
+#define SPI_RDR_RD1_Msk (0xffu << SPI_RDR_RD1_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD2_Pos 16\r
+#define SPI_RDR_RD2_Msk (0xffu << SPI_RDR_RD2_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD3_Pos 24\r
+#define SPI_RDR_RD3_Msk (0xffu << SPI_RDR_RD3_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD0_FIFO_MULTI_DATA_16_Pos 0\r
+#define SPI_RDR_RD0_FIFO_MULTI_DATA_16_Msk (0xffffu << SPI_RDR_RD0_FIFO_MULTI_DATA_16_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD1_FIFO_MULTI_DATA_16_Pos 16\r
+#define SPI_RDR_RD1_FIFO_MULTI_DATA_16_Msk (0xffffu << SPI_RDR_RD1_FIFO_MULTI_DATA_16_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+/* -------- SPI_TDR : (FLEXCOM Offset: 0x40C) SPI Transmit Data Register -------- */\r
+#define SPI_TDR_TD_Pos 0\r
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))\r
+#define SPI_TDR_PCS_Pos 16\r
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */\r
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))\r
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */\r
+#define SPI_TDR_TD0_Pos 0\r
+#define SPI_TDR_TD0_Msk (0xffffu << SPI_TDR_TD0_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD0(value) ((SPI_TDR_TD0_Msk & ((value) << SPI_TDR_TD0_Pos)))\r
+#define SPI_TDR_TD1_Pos 16\r
+#define SPI_TDR_TD1_Msk (0xffffu << SPI_TDR_TD1_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD1(value) ((SPI_TDR_TD1_Msk & ((value) << SPI_TDR_TD1_Pos)))\r
+/* -------- SPI_SR : (FLEXCOM Offset: 0x410) SPI Status Register -------- */\r
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */\r
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */\r
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */\r
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */\r
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */\r
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */\r
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode Only) (cleared on read) */\r
+#define SPI_SR_CMP (0x1u << 11) /**< \brief (SPI_SR) Comparison Status (cleared on read) */\r
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */\r
+#define SPI_SR_TXFEF (0x1u << 24) /**< \brief (SPI_SR) Transmit FIFO Empty Flag (cleared on read) */\r
+#define SPI_SR_TXFFF (0x1u << 25) /**< \brief (SPI_SR) Transmit FIFO Full Flag (cleared on read) */\r
+#define SPI_SR_TXFTHF (0x1u << 26) /**< \brief (SPI_SR) Transmit FIFO Threshold Flag (cleared on read) */\r
+#define SPI_SR_RXFEF (0x1u << 27) /**< \brief (SPI_SR) Receive FIFO Empty Flag */\r
+#define SPI_SR_RXFFF (0x1u << 28) /**< \brief (SPI_SR) Receive FIFO Full Flag */\r
+#define SPI_SR_RXFTHF (0x1u << 29) /**< \brief (SPI_SR) Receive FIFO Threshold Flag */\r
+#define SPI_SR_TXFPTEF (0x1u << 30) /**< \brief (SPI_SR) Transmit FIFO Pointer Error Flag */\r
+#define SPI_SR_RXFPTEF (0x1u << 31) /**< \brief (SPI_SR) Receive FIFO Pointer Error Flag */\r
+/* -------- SPI_IER : (FLEXCOM Offset: 0x414) SPI Interrupt Enable Register -------- */\r
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */\r
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */\r
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */\r
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */\r
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */\r
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */\r
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */\r
+#define SPI_IER_CMP (0x1u << 11) /**< \brief (SPI_IER) Comparison Interrupt Enable */\r
+#define SPI_IER_TXFEF (0x1u << 24) /**< \brief (SPI_IER) TXFEF Interrupt Enable */\r
+#define SPI_IER_TXFFF (0x1u << 25) /**< \brief (SPI_IER) TXFFF Interrupt Enable */\r
+#define SPI_IER_TXFTHF (0x1u << 26) /**< \brief (SPI_IER) TXFTHF Interrupt Enable */\r
+#define SPI_IER_RXFEF (0x1u << 27) /**< \brief (SPI_IER) RXFEF Interrupt Enable */\r
+#define SPI_IER_RXFFF (0x1u << 28) /**< \brief (SPI_IER) RXFFF Interrupt Enable */\r
+#define SPI_IER_RXFTHF (0x1u << 29) /**< \brief (SPI_IER) RXFTHF Interrupt Enable */\r
+#define SPI_IER_TXFPTEF (0x1u << 30) /**< \brief (SPI_IER) TXFPTEF Interrupt Enable */\r
+#define SPI_IER_RXFPTEF (0x1u << 31) /**< \brief (SPI_IER) RXFPTEF Interrupt Enable */\r
+/* -------- SPI_IDR : (FLEXCOM Offset: 0x418) SPI Interrupt Disable Register -------- */\r
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */\r
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */\r
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */\r
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */\r
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */\r
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */\r
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */\r
+#define SPI_IDR_CMP (0x1u << 11) /**< \brief (SPI_IDR) Comparison Interrupt Disable */\r
+#define SPI_IDR_TXFEF (0x1u << 24) /**< \brief (SPI_IDR) TXFEF Interrupt Disable */\r
+#define SPI_IDR_TXFFF (0x1u << 25) /**< \brief (SPI_IDR) TXFFF Interrupt Disable */\r
+#define SPI_IDR_TXFTHF (0x1u << 26) /**< \brief (SPI_IDR) TXFTHF Interrupt Disable */\r
+#define SPI_IDR_RXFEF (0x1u << 27) /**< \brief (SPI_IDR) RXFEF Interrupt Disable */\r
+#define SPI_IDR_RXFFF (0x1u << 28) /**< \brief (SPI_IDR) RXFFF Interrupt Disable */\r
+#define SPI_IDR_RXFTHF (0x1u << 29) /**< \brief (SPI_IDR) RXFTHF Interrupt Disable */\r
+#define SPI_IDR_TXFPTEF (0x1u << 30) /**< \brief (SPI_IDR) TXFPTEF Interrupt Disable */\r
+#define SPI_IDR_RXFPTEF (0x1u << 31) /**< \brief (SPI_IDR) RXFPTEF Interrupt Disable */\r
+/* -------- SPI_IMR : (FLEXCOM Offset: 0x41C) SPI Interrupt Mask Register -------- */\r
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */\r
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */\r
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */\r
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */\r
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */\r
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */\r
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */\r
+#define SPI_IMR_CMP (0x1u << 11) /**< \brief (SPI_IMR) Comparison Interrupt Mask */\r
+#define SPI_IMR_TXFEF (0x1u << 24) /**< \brief (SPI_IMR) TXFEF Interrupt Mask */\r
+#define SPI_IMR_TXFFF (0x1u << 25) /**< \brief (SPI_IMR) TXFFF Interrupt Mask */\r
+#define SPI_IMR_TXFTHF (0x1u << 26) /**< \brief (SPI_IMR) TXFTHF Interrupt Mask */\r
+#define SPI_IMR_RXFEF (0x1u << 27) /**< \brief (SPI_IMR) RXFEF Interrupt Mask */\r
+#define SPI_IMR_RXFFF (0x1u << 28) /**< \brief (SPI_IMR) RXFFF Interrupt Mask */\r
+#define SPI_IMR_RXFTHF (0x1u << 29) /**< \brief (SPI_IMR) RXFTHF Interrupt Mask */\r
+#define SPI_IMR_TXFPTEF (0x1u << 30) /**< \brief (SPI_IMR) TXFPTEF Interrupt Mask */\r
+#define SPI_IMR_RXFPTEF (0x1u << 31) /**< \brief (SPI_IMR) RXFPTEF Interrupt Mask */\r
+/* -------- SPI_CSR[2] : (FLEXCOM Offset: 0x430) SPI Chip Select Register -------- */\r
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[2]) Clock Polarity */\r
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[2]) Clock Phase */\r
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[2]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */\r
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[2]) Chip Select Active After Transfer */\r
+#define SPI_CSR_BITS_Pos 4\r
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[2]) Bits Per Transfer */\r
+#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)))\r
+#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[2]) 8 bits for transfer */\r
+#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[2]) 9 bits for transfer */\r
+#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[2]) 10 bits for transfer */\r
+#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[2]) 11 bits for transfer */\r
+#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[2]) 12 bits for transfer */\r
+#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[2]) 13 bits for transfer */\r
+#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[2]) 14 bits for transfer */\r
+#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[2]) 15 bits for transfer */\r
+#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[2]) 16 bits for transfer */\r
+#define SPI_CSR_SCBR_Pos 8\r
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[2]) Serial Clock Bit Rate */\r
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))\r
+#define SPI_CSR_DLYBS_Pos 16\r
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[2]) Delay Before SPCK */\r
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))\r
+#define SPI_CSR_DLYBCT_Pos 24\r
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[2]) Delay Between Consecutive Transfers */\r
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))\r
+/* -------- SPI_FMR : (FLEXCOM Offset: 0x440) SPI FIFO Mode Register -------- */\r
+#define SPI_FMR_TXRDYM_Pos 0\r
+#define SPI_FMR_TXRDYM_Msk (0x3u << SPI_FMR_TXRDYM_Pos) /**< \brief (SPI_FMR) Transmitter Data Register Empty Mode */\r
+#define SPI_FMR_TXRDYM(value) ((SPI_FMR_TXRDYM_Msk & ((value) << SPI_FMR_TXRDYM_Pos)))\r
+#define SPI_FMR_TXRDYM_ONE_DATA (0x0u << 0) /**< \brief (SPI_FMR) TDRE will be at level '1' when at least one data can be written in the Transmit FIFO. */\r
+#define SPI_FMR_TXRDYM_TWO_DATA (0x1u << 0) /**< \brief (SPI_FMR) TDRE will be at level '1' when at least two data can be written in the Transmit FIFO. */\r
+#define SPI_FMR_TXRDYM_FOUR_DATA (0x2u << 0) /**< \brief (SPI_FMR) TDRE will be at level '1' when at least four data can be written in the Transmit FIFO. */\r
+#define SPI_FMR_RXRDYM_Pos 4\r
+#define SPI_FMR_RXRDYM_Msk (0x3u << SPI_FMR_RXRDYM_Pos) /**< \brief (SPI_FMR) Receiver Data Register Full Mode */\r
+#define SPI_FMR_RXRDYM(value) ((SPI_FMR_RXRDYM_Msk & ((value) << SPI_FMR_RXRDYM_Pos)))\r
+#define SPI_FMR_RXRDYM_ONE_DATA (0x0u << 4) /**< \brief (SPI_FMR) RDRF will be at level '1' when at least one unread data is in the Receive FIFO. */\r
+#define SPI_FMR_RXRDYM_TWO_DATA (0x1u << 4) /**< \brief (SPI_FMR) RDRF will be at level '1' when at least two unread data are in the Receive FIFO. */\r
+#define SPI_FMR_RXRDYM_FOUR_DATA (0x2u << 4) /**< \brief (SPI_FMR) RDRF will be at level '1' when at least four unread data are in the Receive FIFO. */\r
+#define SPI_FMR_TXFTHRES_Pos 16\r
+#define SPI_FMR_TXFTHRES_Msk (0x3fu << SPI_FMR_TXFTHRES_Pos) /**< \brief (SPI_FMR) Transmit FIFO Threshold */\r
+#define SPI_FMR_TXFTHRES(value) ((SPI_FMR_TXFTHRES_Msk & ((value) << SPI_FMR_TXFTHRES_Pos)))\r
+#define SPI_FMR_RXFTHRES_Pos 24\r
+#define SPI_FMR_RXFTHRES_Msk (0x3fu << SPI_FMR_RXFTHRES_Pos) /**< \brief (SPI_FMR) Receive FIFO Threshold */\r
+#define SPI_FMR_RXFTHRES(value) ((SPI_FMR_RXFTHRES_Msk & ((value) << SPI_FMR_RXFTHRES_Pos)))\r
+/* -------- SPI_FLR : (FLEXCOM Offset: 0x444) SPI FIFO Level Register -------- */\r
+#define SPI_FLR_TXFL_Pos 0\r
+#define SPI_FLR_TXFL_Msk (0x3fu << SPI_FLR_TXFL_Pos) /**< \brief (SPI_FLR) Transmit FIFO Level */\r
+#define SPI_FLR_RXFL_Pos 16\r
+#define SPI_FLR_RXFL_Msk (0x3fu << SPI_FLR_RXFL_Pos) /**< \brief (SPI_FLR) Receive FIFO Level */\r
+/* -------- SPI_CMPR : (FLEXCOM Offset: 0x448) SPI Comparison Register -------- */\r
+#define SPI_CMPR_VAL1_Pos 0\r
+#define SPI_CMPR_VAL1_Msk (0xffffu << SPI_CMPR_VAL1_Pos) /**< \brief (SPI_CMPR) First Comparison Value for Received Character */\r
+#define SPI_CMPR_VAL1(value) ((SPI_CMPR_VAL1_Msk & ((value) << SPI_CMPR_VAL1_Pos)))\r
+#define SPI_CMPR_VAL2_Pos 16\r
+#define SPI_CMPR_VAL2_Msk (0xffffu << SPI_CMPR_VAL2_Pos) /**< \brief (SPI_CMPR) Second Comparison Value for Received Character */\r
+#define SPI_CMPR_VAL2(value) ((SPI_CMPR_VAL2_Msk & ((value) << SPI_CMPR_VAL2_Pos)))\r
+/* -------- SPI_WPMR : (FLEXCOM Offset: 0x4E4) SPI Write Protection Mode Register -------- */\r
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */\r
+#define SPI_WPMR_WPKEY_Pos 8\r
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */\r
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))\r
+#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */\r
+/* -------- SPI_WPSR : (FLEXCOM Offset: 0x4E8) SPI Write Protection Status Register -------- */\r
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */\r
+#define SPI_WPSR_WPVSRC_Pos 8\r
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */\r
+/* -------- SPI_VERSION : (FLEXCOM Offset: 0x4FC) SPI Version Register -------- */\r
+#define SPI_VERSION_VERSION_Pos 0\r
+#define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos) /**< \brief (SPI_VERSION) Version of the Hardware Module */\r
+#define SPI_VERSION_MFN_Pos 16\r
+#define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos) /**< \brief (SPI_VERSION) Metal Fix Number */\r
+/* -------- TWI_CR : (FLEXCOM Offset: 0x600) TWI Control Register -------- */\r
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */\r
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */\r
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */\r
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */\r
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */\r
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */\r
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBus Quick Command */\r
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */\r
+#define TWI_CR_HSEN (0x1u << 8) /**< \brief (TWI_CR) TWI High-Speed Mode Enabled */\r
+#define TWI_CR_HSDIS (0x1u << 9) /**< \brief (TWI_CR) TWI High-Speed Mode Disabled */\r
+#define TWI_CR_SMBEN (0x1u << 10) /**< \brief (TWI_CR) SMBus Mode Enabled */\r
+#define TWI_CR_SMBDIS (0x1u << 11) /**< \brief (TWI_CR) SMBus Mode Disabled */\r
+#define TWI_CR_PECEN (0x1u << 12) /**< \brief (TWI_CR) Packet Error Checking Enable */\r
+#define TWI_CR_PECDIS (0x1u << 13) /**< \brief (TWI_CR) Packet Error Checking Disable */\r
+#define TWI_CR_PECRQ (0x1u << 14) /**< \brief (TWI_CR) PEC Request */\r
+#define TWI_CR_CLEAR (0x1u << 15) /**< \brief (TWI_CR) Bus CLEAR Command */\r
+#define TWI_CR_ACMEN (0x1u << 16) /**< \brief (TWI_CR) Alternative Command Mode Enable */\r
+#define TWI_CR_ACMDIS (0x1u << 17) /**< \brief (TWI_CR) Alternative Command Mode Disable */\r
+#define TWI_CR_THRCLR (0x1u << 24) /**< \brief (TWI_CR) Transmit Holding Register Clear */\r
+#define TWI_CR_LOCKCLR (0x1u << 26) /**< \brief (TWI_CR) Lock Clear */\r
+#define TWI_CR_FIFOEN (0x1u << 28) /**< \brief (TWI_CR) FIFO Enable */\r
+#define TWI_CR_FIFODIS (0x1u << 29) /**< \brief (TWI_CR) FIFO Disable */\r
+/* -------- TWI_MMR : (FLEXCOM Offset: 0x604) TWI Master Mode Register -------- */\r
+#define TWI_MMR_IADRSZ_Pos 8\r
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */\r
+#define TWI_MMR_IADRSZ(value) ((TWI_MMR_IADRSZ_Msk & ((value) << TWI_MMR_IADRSZ_Pos)))\r
+#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */\r
+#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */\r
+#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */\r
+#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */\r
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */\r
+#define TWI_MMR_DADR_Pos 16\r
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */\r
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))\r
+/* -------- TWI_SMR : (FLEXCOM Offset: 0x608) TWI Slave Mode Register -------- */\r
+#define TWI_SMR_NACKEN (0x1u << 0) /**< \brief (TWI_SMR) Slave Receiver Data Phase NACK Enable */\r
+#define TWI_SMR_SMDA (0x1u << 2) /**< \brief (TWI_SMR) SMBus Default Address */\r
+#define TWI_SMR_SMHH (0x1u << 3) /**< \brief (TWI_SMR) SMBus Host Header */\r
+#define TWI_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWI_SMR) Clock Wait State Disable */\r
+#define TWI_SMR_MASK_Pos 8\r
+#define TWI_SMR_MASK_Msk (0x7fu << TWI_SMR_MASK_Pos) /**< \brief (TWI_SMR) Slave Address Mask */\r
+#define TWI_SMR_MASK(value) ((TWI_SMR_MASK_Msk & ((value) << TWI_SMR_MASK_Pos)))\r
+#define TWI_SMR_SADR_Pos 16\r
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */\r
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))\r
+#define TWI_SMR_SADR1EN (0x1u << 28) /**< \brief (TWI_SMR) Slave Address 1 Enable */\r
+#define TWI_SMR_SADR2EN (0x1u << 29) /**< \brief (TWI_SMR) Slave Address 2 Enable */\r
+#define TWI_SMR_SADR3EN (0x1u << 30) /**< \brief (TWI_SMR) Slave Address 3 Enable */\r
+#define TWI_SMR_DATAMEN (0x1u << 31) /**< \brief (TWI_SMR) Data Matching Enable */\r
+/* -------- TWI_IADR : (FLEXCOM Offset: 0x60C) TWI Internal Address Register -------- */\r
+#define TWI_IADR_IADR_Pos 0\r
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */\r
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))\r
+/* -------- TWI_CWGR : (FLEXCOM Offset: 0x610) TWI Clock Waveform Generator Register -------- */\r
+#define TWI_CWGR_CLDIV_Pos 0\r
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */\r
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))\r
+#define TWI_CWGR_CHDIV_Pos 8\r
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */\r
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))\r
+#define TWI_CWGR_CKDIV_Pos 16\r
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */\r
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))\r
+#define TWI_CWGR_BRSRCCLK (0x1u << 20) /**< \brief (TWI_CWGR) Bit Rate Source Clock */\r
+#define TWI_CWGR_BRSRCCLK_PERIPH_CLK (0x0u << 20) /**< \brief (TWI_CWGR) The peripheral clock is the source clock for the bit rate generation. */\r
+#define TWI_CWGR_BRSRCCLK_PMC_PCK (0x1u << 20) /**< \brief (TWI_CWGR) PMC PCKx is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. */\r
+#define TWI_CWGR_HOLD_Pos 24\r
+#define TWI_CWGR_HOLD_Msk (0x1fu << TWI_CWGR_HOLD_Pos) /**< \brief (TWI_CWGR) TWD Hold Time Versus TWCK Falling */\r
+#define TWI_CWGR_HOLD(value) ((TWI_CWGR_HOLD_Msk & ((value) << TWI_CWGR_HOLD_Pos)))\r
+/* -------- TWI_SR : (FLEXCOM Offset: 0x620) TWI Status Register -------- */\r
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (cleared by writing TWI_THR) */\r
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (cleared when reading TWI_RHR) */\r
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (cleared by writing TWI_THR) */\r
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read */\r
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access */\r
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (cleared on read) */\r
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (cleared on read) */\r
+#define TWI_SR_UNRE (0x1u << 7) /**< \brief (TWI_SR) Underrun Error (cleared on read) */\r
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (cleared on read) */\r
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (cleared on read) */\r
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State */\r
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (cleared on read) */\r
+#define TWI_SR_MCACK (0x1u << 16) /**< \brief (TWI_SR) Master Code Acknowledge (cleared on read) */\r
+#define TWI_SR_TOUT (0x1u << 18) /**< \brief (TWI_SR) Timeout Error (cleared on read) */\r
+#define TWI_SR_PECERR (0x1u << 19) /**< \brief (TWI_SR) PEC Error (cleared on read) */\r
+#define TWI_SR_SMBDAM (0x1u << 20) /**< \brief (TWI_SR) SMBus Default Address Match (cleared on read) */\r
+#define TWI_SR_SMBHHM (0x1u << 21) /**< \brief (TWI_SR) SMBus Host Header Address Match (cleared on read) */\r
+#define TWI_SR_LOCK (0x1u << 23) /**< \brief (TWI_SR) TWI Lock Due to Frame Errors */\r
+#define TWI_SR_SCL (0x1u << 24) /**< \brief (TWI_SR) SCL line value */\r
+#define TWI_SR_SDA (0x1u << 25) /**< \brief (TWI_SR) SDA line value */\r
+/* -------- TWI_IER : (FLEXCOM Offset: 0x624) TWI Interrupt Enable Register -------- */\r
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */\r
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */\r
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */\r
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */\r
+#define TWI_IER_UNRE (0x1u << 7) /**< \brief (TWI_IER) Underrun Error Interrupt Enable */\r
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */\r
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */\r
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */\r
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */\r
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */\r
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */\r
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define TWI_IER_MCACK (0x1u << 16) /**< \brief (TWI_IER) Master Code Acknowledge Interrupt Enable */\r
+#define TWI_IER_TOUT (0x1u << 18) /**< \brief (TWI_IER) Timeout Error Interrupt Enable */\r
+#define TWI_IER_PECERR (0x1u << 19) /**< \brief (TWI_IER) PEC Error Interrupt Enable */\r
+#define TWI_IER_SMBDAM (0x1u << 20) /**< \brief (TWI_IER) SMBus Default Address Match Interrupt Enable */\r
+#define TWI_IER_SMBHHM (0x1u << 21) /**< \brief (TWI_IER) SMBus Host Header Address Match Interrupt Enable */\r
+/* -------- TWI_IDR : (FLEXCOM Offset: 0x628) TWI Interrupt Disable Register -------- */\r
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */\r
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */\r
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */\r
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */\r
+#define TWI_IDR_UNRE (0x1u << 7) /**< \brief (TWI_IDR) Underrun Error Interrupt Disable */\r
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */\r
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */\r
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */\r
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */\r
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define TWI_IDR_MCACK (0x1u << 16) /**< \brief (TWI_IDR) Master Code Acknowledge Interrupt Disable */\r
+#define TWI_IDR_TOUT (0x1u << 18) /**< \brief (TWI_IDR) Timeout Error Interrupt Disable */\r
+#define TWI_IDR_PECERR (0x1u << 19) /**< \brief (TWI_IDR) PEC Error Interrupt Disable */\r
+#define TWI_IDR_SMBDAM (0x1u << 20) /**< \brief (TWI_IDR) SMBus Default Address Match Interrupt Disable */\r
+#define TWI_IDR_SMBHHM (0x1u << 21) /**< \brief (TWI_IDR) SMBus Host Header Address Match Interrupt Disable */\r
+/* -------- TWI_IMR : (FLEXCOM Offset: 0x62C) TWI Interrupt Mask Register -------- */\r
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */\r
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */\r
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */\r
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */\r
+#define TWI_IMR_UNRE (0x1u << 7) /**< \brief (TWI_IMR) Underrun Error Interrupt Mask */\r
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */\r
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */\r
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */\r
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */\r
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define TWI_IMR_MCACK (0x1u << 16) /**< \brief (TWI_IMR) Master Code Acknowledge Interrupt Mask */\r
+#define TWI_IMR_TOUT (0x1u << 18) /**< \brief (TWI_IMR) Timeout Error Interrupt Mask */\r
+#define TWI_IMR_PECERR (0x1u << 19) /**< \brief (TWI_IMR) PEC Error Interrupt Mask */\r
+#define TWI_IMR_SMBDAM (0x1u << 20) /**< \brief (TWI_IMR) SMBus Default Address Match Interrupt Mask */\r
+#define TWI_IMR_SMBHHM (0x1u << 21) /**< \brief (TWI_IMR) SMBus Host Header Address Match Interrupt Mask */\r
+/* -------- TWI_RHR : (FLEXCOM Offset: 0x630) TWI Receive Holding Register -------- */\r
+#define TWI_RHR_RXDATA_Pos 0\r
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */\r
+#define TWI_RHR_RXDATA0_Pos 0\r
+#define TWI_RHR_RXDATA0_Msk (0xffu << TWI_RHR_RXDATA0_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data 0 */\r
+#define TWI_RHR_RXDATA1_Pos 8\r
+#define TWI_RHR_RXDATA1_Msk (0xffu << TWI_RHR_RXDATA1_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data 1 */\r
+#define TWI_RHR_RXDATA2_Pos 16\r
+#define TWI_RHR_RXDATA2_Msk (0xffu << TWI_RHR_RXDATA2_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data 2 */\r
+#define TWI_RHR_RXDATA3_Pos 24\r
+#define TWI_RHR_RXDATA3_Msk (0xffu << TWI_RHR_RXDATA3_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data 3 */\r
+/* -------- TWI_THR : (FLEXCOM Offset: 0x634) TWI Transmit Holding Register -------- */\r
+#define TWI_THR_TXDATA_Pos 0\r
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */\r
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))\r
+#define TWI_THR_TXDATA0_Pos 0\r
+#define TWI_THR_TXDATA0_Msk (0xffu << TWI_THR_TXDATA0_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data 0 */\r
+#define TWI_THR_TXDATA0(value) ((TWI_THR_TXDATA0_Msk & ((value) << TWI_THR_TXDATA0_Pos)))\r
+#define TWI_THR_TXDATA1_Pos 8\r
+#define TWI_THR_TXDATA1_Msk (0xffu << TWI_THR_TXDATA1_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data 1 */\r
+#define TWI_THR_TXDATA1(value) ((TWI_THR_TXDATA1_Msk & ((value) << TWI_THR_TXDATA1_Pos)))\r
+#define TWI_THR_TXDATA2_Pos 16\r
+#define TWI_THR_TXDATA2_Msk (0xffu << TWI_THR_TXDATA2_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data 2 */\r
+#define TWI_THR_TXDATA2(value) ((TWI_THR_TXDATA2_Msk & ((value) << TWI_THR_TXDATA2_Pos)))\r
+#define TWI_THR_TXDATA3_Pos 24\r
+#define TWI_THR_TXDATA3_Msk (0xffu << TWI_THR_TXDATA3_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data 3 */\r
+#define TWI_THR_TXDATA3(value) ((TWI_THR_TXDATA3_Msk & ((value) << TWI_THR_TXDATA3_Pos)))\r
+/* -------- TWI_SMBTR : (FLEXCOM Offset: 0x638) TWI SMBus Timing Register -------- */\r
+#define TWI_SMBTR_PRESC_Pos 0\r
+#define TWI_SMBTR_PRESC_Msk (0xfu << TWI_SMBTR_PRESC_Pos) /**< \brief (TWI_SMBTR) SMBus Clock Prescaler */\r
+#define TWI_SMBTR_PRESC(value) ((TWI_SMBTR_PRESC_Msk & ((value) << TWI_SMBTR_PRESC_Pos)))\r
+#define TWI_SMBTR_TLOWS_Pos 8\r
+#define TWI_SMBTR_TLOWS_Msk (0xffu << TWI_SMBTR_TLOWS_Pos) /**< \brief (TWI_SMBTR) Slave Clock Stretch Maximum Cycles */\r
+#define TWI_SMBTR_TLOWS(value) ((TWI_SMBTR_TLOWS_Msk & ((value) << TWI_SMBTR_TLOWS_Pos)))\r
+#define TWI_SMBTR_TLOWM_Pos 16\r
+#define TWI_SMBTR_TLOWM_Msk (0xffu << TWI_SMBTR_TLOWM_Pos) /**< \brief (TWI_SMBTR) Master Clock Stretch Maximum Cycles */\r
+#define TWI_SMBTR_TLOWM(value) ((TWI_SMBTR_TLOWM_Msk & ((value) << TWI_SMBTR_TLOWM_Pos)))\r
+#define TWI_SMBTR_THMAX_Pos 24\r
+#define TWI_SMBTR_THMAX_Msk (0xffu << TWI_SMBTR_THMAX_Pos) /**< \brief (TWI_SMBTR) Clock High Maximum Cycles */\r
+#define TWI_SMBTR_THMAX(value) ((TWI_SMBTR_THMAX_Msk & ((value) << TWI_SMBTR_THMAX_Pos)))\r
+/* -------- TWI_ACR : (FLEXCOM Offset: 0x640) TWI Alternative Command Register -------- */\r
+#define TWI_ACR_DATAL_Pos 0\r
+#define TWI_ACR_DATAL_Msk (0xffu << TWI_ACR_DATAL_Pos) /**< \brief (TWI_ACR) Data Length */\r
+#define TWI_ACR_DATAL(value) ((TWI_ACR_DATAL_Msk & ((value) << TWI_ACR_DATAL_Pos)))\r
+#define TWI_ACR_DIR (0x1u << 8) /**< \brief (TWI_ACR) Transfer Direction */\r
+#define TWI_ACR_PEC (0x1u << 9) /**< \brief (TWI_ACR) PEC Request (SMBus Mode only) */\r
+#define TWI_ACR_NDATAL_Pos 16\r
+#define TWI_ACR_NDATAL_Msk (0xffu << TWI_ACR_NDATAL_Pos) /**< \brief (TWI_ACR) Next Data Length */\r
+#define TWI_ACR_NDATAL(value) ((TWI_ACR_NDATAL_Msk & ((value) << TWI_ACR_NDATAL_Pos)))\r
+#define TWI_ACR_NDIR (0x1u << 24) /**< \brief (TWI_ACR) Next Transfer Direction */\r
+#define TWI_ACR_NPEC (0x1u << 25) /**< \brief (TWI_ACR) Next PEC Request (SMBus Mode only) */\r
+/* -------- TWI_FILTR : (FLEXCOM Offset: 0x644) TWI Filter Register -------- */\r
+#define TWI_FILTR_FILT (0x1u << 0) /**< \brief (TWI_FILTR) RX Digital Filter */\r
+#define TWI_FILTR_PADFEN (0x1u << 1) /**< \brief (TWI_FILTR) PAD Filter Enable */\r
+#define TWI_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWI_FILTR) PAD Filter Config */\r
+#define TWI_FILTR_THRES_Pos 8\r
+#define TWI_FILTR_THRES_Msk (0x7u << TWI_FILTR_THRES_Pos) /**< \brief (TWI_FILTR) Digital Filter Threshold */\r
+#define TWI_FILTR_THRES(value) ((TWI_FILTR_THRES_Msk & ((value) << TWI_FILTR_THRES_Pos)))\r
+/* -------- TWI_SWMR : (FLEXCOM Offset: 0x64C) TWI SleepWalking Matching Register -------- */\r
+#define TWI_SWMR_SADR1_Pos 0\r
+#define TWI_SWMR_SADR1_Msk (0x7fu << TWI_SWMR_SADR1_Pos) /**< \brief (TWI_SWMR) Slave Address 1 */\r
+#define TWI_SWMR_SADR1(value) ((TWI_SWMR_SADR1_Msk & ((value) << TWI_SWMR_SADR1_Pos)))\r
+#define TWI_SWMR_SADR2_Pos 8\r
+#define TWI_SWMR_SADR2_Msk (0x7fu << TWI_SWMR_SADR2_Pos) /**< \brief (TWI_SWMR) Slave Address 2 */\r
+#define TWI_SWMR_SADR2(value) ((TWI_SWMR_SADR2_Msk & ((value) << TWI_SWMR_SADR2_Pos)))\r
+#define TWI_SWMR_SADR3_Pos 16\r
+#define TWI_SWMR_SADR3_Msk (0x7fu << TWI_SWMR_SADR3_Pos) /**< \brief (TWI_SWMR) Slave Address 3 */\r
+#define TWI_SWMR_SADR3(value) ((TWI_SWMR_SADR3_Msk & ((value) << TWI_SWMR_SADR3_Pos)))\r
+#define TWI_SWMR_DATAM_Pos 24\r
+#define TWI_SWMR_DATAM_Msk (0xffu << TWI_SWMR_DATAM_Pos) /**< \brief (TWI_SWMR) Data Match */\r
+#define TWI_SWMR_DATAM(value) ((TWI_SWMR_DATAM_Msk & ((value) << TWI_SWMR_DATAM_Pos)))\r
+/* -------- TWI_FMR : (FLEXCOM Offset: 0x650) TWI FIFO Mode Register -------- */\r
+#define TWI_FMR_TXRDYM_Pos 0\r
+#define TWI_FMR_TXRDYM_Msk (0x3u << TWI_FMR_TXRDYM_Pos) /**< \brief (TWI_FMR) Transmitter Ready Mode */\r
+#define TWI_FMR_TXRDYM(value) ((TWI_FMR_TXRDYM_Msk & ((value) << TWI_FMR_TXRDYM_Pos)))\r
+#define TWI_FMR_TXRDYM_ONE_DATA (0x0u << 0) /**< \brief (TWI_FMR) TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO */\r
+#define TWI_FMR_TXRDYM_TWO_DATA (0x1u << 0) /**< \brief (TWI_FMR) TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO */\r
+#define TWI_FMR_TXRDYM_FOUR_DATA (0x2u << 0) /**< \brief (TWI_FMR) TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO */\r
+#define TWI_FMR_RXRDYM_Pos 4\r
+#define TWI_FMR_RXRDYM_Msk (0x3u << TWI_FMR_RXRDYM_Pos) /**< \brief (TWI_FMR) Receiver Ready Mode */\r
+#define TWI_FMR_RXRDYM(value) ((TWI_FMR_RXRDYM_Msk & ((value) << TWI_FMR_RXRDYM_Pos)))\r
+#define TWI_FMR_RXRDYM_ONE_DATA (0x0u << 4) /**< \brief (TWI_FMR) RXRDY will be at level '1' when at least one unread data is in the Receive FIFO */\r
+#define TWI_FMR_RXRDYM_TWO_DATA (0x1u << 4) /**< \brief (TWI_FMR) RXRDY will be at level '1' when at least two unread data are in the Receive FIFO */\r
+#define TWI_FMR_RXRDYM_FOUR_DATA (0x2u << 4) /**< \brief (TWI_FMR) RXRDY will be at level '1' when at least four unread data are in the Receive FIFO */\r
+#define TWI_FMR_TXFTHRES_Pos 16\r
+#define TWI_FMR_TXFTHRES_Msk (0x3fu << TWI_FMR_TXFTHRES_Pos) /**< \brief (TWI_FMR) Transmit FIFO Threshold */\r
+#define TWI_FMR_TXFTHRES(value) ((TWI_FMR_TXFTHRES_Msk & ((value) << TWI_FMR_TXFTHRES_Pos)))\r
+#define TWI_FMR_RXFTHRES_Pos 24\r
+#define TWI_FMR_RXFTHRES_Msk (0x3fu << TWI_FMR_RXFTHRES_Pos) /**< \brief (TWI_FMR) Receive FIFO Threshold */\r
+#define TWI_FMR_RXFTHRES(value) ((TWI_FMR_RXFTHRES_Msk & ((value) << TWI_FMR_RXFTHRES_Pos)))\r
+/* -------- TWI_FLR : (FLEXCOM Offset: 0x654) TWI FIFO Level Register -------- */\r
+#define TWI_FLR_TXFL_Pos 0\r
+#define TWI_FLR_TXFL_Msk (0x3fu << TWI_FLR_TXFL_Pos) /**< \brief (TWI_FLR) Transmit FIFO Level */\r
+#define TWI_FLR_RXFL_Pos 16\r
+#define TWI_FLR_RXFL_Msk (0x3fu << TWI_FLR_RXFL_Pos) /**< \brief (TWI_FLR) Receive FIFO Level */\r
+/* -------- TWI_FSR : (FLEXCOM Offset: 0x660) TWI FIFO Status Register -------- */\r
+#define TWI_FSR_TXFEF (0x1u << 0) /**< \brief (TWI_FSR) Transmit FIFO Empty Flag (cleared on read) */\r
+#define TWI_FSR_TXFFF (0x1u << 1) /**< \brief (TWI_FSR) Transmit FIFO Full Flag (cleared on read) */\r
+#define TWI_FSR_TXFTHF (0x1u << 2) /**< \brief (TWI_FSR) Transmit FIFO Threshold Flag (cleared on read) */\r
+#define TWI_FSR_RXFEF (0x1u << 3) /**< \brief (TWI_FSR) Receive FIFO Empty Flag */\r
+#define TWI_FSR_RXFFF (0x1u << 4) /**< \brief (TWI_FSR) Receive FIFO Full Flag */\r
+#define TWI_FSR_RXFTHF (0x1u << 5) /**< \brief (TWI_FSR) Receive FIFO Threshold Flag */\r
+#define TWI_FSR_TXFPTEF (0x1u << 6) /**< \brief (TWI_FSR) Transmit FIFO Pointer Error Flag */\r
+#define TWI_FSR_RXFPTEF (0x1u << 7) /**< \brief (TWI_FSR) Receive FIFO Pointer Error Flag */\r
+/* -------- TWI_FIER : (FLEXCOM Offset: 0x664) TWI FIFO Interrupt Enable Register -------- */\r
+#define TWI_FIER_TXFEF (0x1u << 0) /**< \brief (TWI_FIER) TXFEF Interrupt Enable */\r
+#define TWI_FIER_TXFFF (0x1u << 1) /**< \brief (TWI_FIER) TXFFF Interrupt Enable */\r
+#define TWI_FIER_TXFTHF (0x1u << 2) /**< \brief (TWI_FIER) TXFTHF Interrupt Enable */\r
+#define TWI_FIER_RXFEF (0x1u << 3) /**< \brief (TWI_FIER) RXFEF Interrupt Enable */\r
+#define TWI_FIER_RXFFF (0x1u << 4) /**< \brief (TWI_FIER) RXFFF Interrupt Enable */\r
+#define TWI_FIER_RXFTHF (0x1u << 5) /**< \brief (TWI_FIER) RXFTHF Interrupt Enable */\r
+#define TWI_FIER_TXFPTEF (0x1u << 6) /**< \brief (TWI_FIER) TXFPTEF Interrupt Enable */\r
+#define TWI_FIER_RXFPTEF (0x1u << 7) /**< \brief (TWI_FIER) RXFPTEF Interrupt Enable */\r
+/* -------- TWI_FIDR : (FLEXCOM Offset: 0x668) TWI FIFO Interrupt Disable Register -------- */\r
+#define TWI_FIDR_TXFEF (0x1u << 0) /**< \brief (TWI_FIDR) TXFEF Interrupt Disable */\r
+#define TWI_FIDR_TXFFF (0x1u << 1) /**< \brief (TWI_FIDR) TXFFF Interrupt Disable */\r
+#define TWI_FIDR_TXFTHF (0x1u << 2) /**< \brief (TWI_FIDR) TXFTHF Interrupt Disable */\r
+#define TWI_FIDR_RXFEF (0x1u << 3) /**< \brief (TWI_FIDR) RXFEF Interrupt Disable */\r
+#define TWI_FIDR_RXFFF (0x1u << 4) /**< \brief (TWI_FIDR) RXFFF Interrupt Disable */\r
+#define TWI_FIDR_RXFTHF (0x1u << 5) /**< \brief (TWI_FIDR) RXFTHF Interrupt Disable */\r
+#define TWI_FIDR_TXFPTEF (0x1u << 6) /**< \brief (TWI_FIDR) TXFPTEF Interrupt Disable */\r
+#define TWI_FIDR_RXFPTEF (0x1u << 7) /**< \brief (TWI_FIDR) RXFPTEF Interrupt Disable */\r
+/* -------- TWI_FIMR : (FLEXCOM Offset: 0x66C) TWI FIFO Interrupt Mask Register -------- */\r
+#define TWI_FIMR_TXFEF (0x1u << 0) /**< \brief (TWI_FIMR) TXFEF Interrupt Mask */\r
+#define TWI_FIMR_TXFFF (0x1u << 1) /**< \brief (TWI_FIMR) TXFFF Interrupt Mask */\r
+#define TWI_FIMR_TXFTHF (0x1u << 2) /**< \brief (TWI_FIMR) TXFTHF Interrupt Mask */\r
+#define TWI_FIMR_RXFEF (0x1u << 3) /**< \brief (TWI_FIMR) RXFEF Interrupt Mask */\r
+#define TWI_FIMR_RXFFF (0x1u << 4) /**< \brief (TWI_FIMR) RXFFF Interrupt Mask */\r
+#define TWI_FIMR_RXFTHF (0x1u << 5) /**< \brief (TWI_FIMR) RXFTHF Interrupt Mask */\r
+#define TWI_FIMR_TXFPTEF (0x1u << 6) /**< \brief (TWI_FIMR) TXFPTEF Interrupt Mask */\r
+#define TWI_FIMR_RXFPTEF (0x1u << 7) /**< \brief (TWI_FIMR) RXFPTEF Interrupt Mask */\r
+/* -------- TWI_DR : (FLEXCOM Offset: 0x6D0) TWI Debug Register -------- */\r
+#define TWI_DR_SWEN (0x1u << 0) /**< \brief (TWI_DR) SleepWalking Enable */\r
+#define TWI_DR_CLKRQ (0x1u << 1) /**< \brief (TWI_DR) Clock Request */\r
+#define TWI_DR_SWMATCH (0x1u << 2) /**< \brief (TWI_DR) SleepWalking Match */\r
+#define TWI_DR_TRP (0x1u << 3) /**< \brief (TWI_DR) Transfer Pending */\r
+/* -------- TWI_WPMR : (FLEXCOM Offset: 0x6E4) TWI Protection Mode Register -------- */\r
+#define TWI_WPMR_WPEN (0x1u << 0) /**< \brief (TWI_WPMR) Write Protection Enable */\r
+#define TWI_WPMR_WPKEY_Pos 8\r
+#define TWI_WPMR_WPKEY_Msk (0xffffffu << TWI_WPMR_WPKEY_Pos) /**< \brief (TWI_WPMR) Write Protection Key */\r
+#define TWI_WPMR_WPKEY(value) ((TWI_WPMR_WPKEY_Msk & ((value) << TWI_WPMR_WPKEY_Pos)))\r
+#define TWI_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */\r
+/* -------- TWI_WPSR : (FLEXCOM Offset: 0x6E8) TWI Protection Status Register -------- */\r
+#define TWI_WPSR_WPVS (0x1u << 0) /**< \brief (TWI_WPSR) Write Protect Violation Status */\r
+#define TWI_WPSR_WPVSRC_Pos 8\r
+#define TWI_WPSR_WPVSRC_Msk (0xffffffu << TWI_WPSR_WPVSRC_Pos) /**< \brief (TWI_WPSR) Write Protection Violation Source */\r
+/* -------- TWI_VER : (FLEXCOM Offset: 0x6FC) TWI Version Register -------- */\r
+#define TWI_VER_VERSION_Pos 0\r
+#define TWI_VER_VERSION_Msk (0xfffu << TWI_VER_VERSION_Pos) /**< \brief (TWI_VER) Version of the Hardware Module */\r
+#define TWI_VER_MFN_Pos 16\r
+#define TWI_VER_MFN_Msk (0x7u << TWI_VER_MFN_Pos) /**< \brief (TWI_VER) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_FLEXCOM_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_GMAC_COMPONENT_\r
+#define _SAMA5D2_GMAC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_GMAC Gigabit Ethernet MAC */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief GmacSa hardware registers */\r
+typedef struct {\r
+ __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom Register */\r
+ __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top Register */\r
+} GmacSa;\r
+/** \brief Gmac hardware registers */\r
+#define GMACSA_NUMBER 4\r
+typedef struct {\r
+ __IO uint32_t GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */\r
+ __IO uint32_t GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */\r
+ __I uint32_t GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */\r
+ __IO uint32_t GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */\r
+ __IO uint32_t GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */\r
+ __IO uint32_t GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */\r
+ __IO uint32_t GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register */\r
+ __IO uint32_t GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register */\r
+ __IO uint32_t GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */\r
+ __I uint32_t GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */\r
+ __O uint32_t GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */\r
+ __O uint32_t GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */\r
+ __IO uint32_t GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */\r
+ __IO uint32_t GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */\r
+ __I uint32_t GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */\r
+ __IO uint32_t GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */\r
+ __IO uint32_t GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */\r
+ __IO uint32_t GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */\r
+ __IO uint32_t GMAC_RJFML; /**< \brief (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register */\r
+ __I uint32_t Reserved1[13];\r
+ __IO uint32_t GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom */\r
+ __IO uint32_t GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top */\r
+ GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */\r
+ __IO uint32_t GMAC_TIDM1; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */\r
+ __IO uint32_t GMAC_TIDM2; /**< \brief (Gmac Offset: 0x0AC) Type ID Match 2 Register */\r
+ __IO uint32_t GMAC_TIDM3; /**< \brief (Gmac Offset: 0x0B0) Type ID Match 3 Register */\r
+ __IO uint32_t GMAC_TIDM4; /**< \brief (Gmac Offset: 0x0B4) Type ID Match 4 Register */\r
+ __IO uint32_t GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */\r
+ __IO uint32_t GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */\r
+ __IO uint32_t GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */\r
+ __IO uint32_t GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */\r
+ __IO uint32_t GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register */\r
+ __IO uint32_t GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register */\r
+ __I uint32_t Reserved2[3];\r
+ __IO uint32_t GMAC_NSC; /**< \brief (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register */\r
+ __IO uint32_t GMAC_SCL; /**< \brief (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register */\r
+ __IO uint32_t GMAC_SCH; /**< \brief (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register */\r
+ __I uint32_t GMAC_EFTSH; /**< \brief (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register */\r
+ __I uint32_t GMAC_EFRSH; /**< \brief (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register */\r
+ __I uint32_t GMAC_PEFTSH; /**< \brief (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register */\r
+ __I uint32_t GMAC_PEFRSH; /**< \brief (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register */\r
+ __I uint32_t Reserved3[1];\r
+ __I uint32_t GMAC_MID; /**< \brief (Gmac Offset: 0x0FC) Module ID Register */\r
+ __I uint32_t GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted Low Register */\r
+ __I uint32_t GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted High Register */\r
+ __I uint32_t GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */\r
+ __I uint32_t GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */\r
+ __I uint32_t GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */\r
+ __I uint32_t GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */\r
+ __I uint32_t GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */\r
+ __I uint32_t GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Underruns Register */\r
+ __I uint32_t GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */\r
+ __I uint32_t GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */\r
+ __I uint32_t GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */\r
+ __I uint32_t GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */\r
+ __I uint32_t GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */\r
+ __I uint32_t GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */\r
+ __I uint32_t GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received Low Received Register */\r
+ __I uint32_t GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received High Received Register */\r
+ __I uint32_t GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */\r
+ __I uint32_t GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */\r
+ __I uint32_t GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */\r
+ __I uint32_t GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */\r
+ __I uint32_t GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */\r
+ __I uint32_t GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */\r
+ __I uint32_t GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */\r
+ __I uint32_t GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */\r
+ __I uint32_t GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */\r
+ __I uint32_t GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */\r
+ __I uint32_t GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */\r
+ __I uint32_t GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */\r
+ __I uint32_t GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */\r
+ __I uint32_t GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */\r
+ __I uint32_t GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */\r
+ __I uint32_t GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */\r
+ __I uint32_t GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */\r
+ __I uint32_t GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */\r
+ __I uint32_t Reserved4[2];\r
+ __IO uint32_t GMAC_TISUBN; /**< \brief (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */\r
+ __IO uint32_t GMAC_TSH; /**< \brief (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register */\r
+ __I uint32_t Reserved5[3];\r
+ __IO uint32_t GMAC_TSL; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register */\r
+ __IO uint32_t GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */\r
+ __O uint32_t GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */\r
+ __IO uint32_t GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */\r
+ __I uint32_t GMAC_EFTSL; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */\r
+ __I uint32_t GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */\r
+ __I uint32_t GMAC_EFRSL; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */\r
+ __I uint32_t GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */\r
+ __I uint32_t GMAC_PEFTSL; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */\r
+ __I uint32_t GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */\r
+ __I uint32_t GMAC_PEFRSL; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */\r
+ __I uint32_t GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */\r
+ __I uint32_t Reserved6[128];\r
+ __I uint32_t GMAC_ISRPQ[2]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) */\r
+ __I uint32_t Reserved7[14];\r
+ __IO uint32_t GMAC_TBQBAPQ[2]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */\r
+ __I uint32_t Reserved8[14];\r
+ __IO uint32_t GMAC_RBQBAPQ[2]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */\r
+ __I uint32_t Reserved9[6];\r
+ __IO uint32_t GMAC_RBSRPQ[2]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) */\r
+ __I uint32_t Reserved10[5];\r
+ __IO uint32_t GMAC_CBSCR; /**< \brief (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register */\r
+ __IO uint32_t GMAC_CBSISQA; /**< \brief (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */\r
+ __IO uint32_t GMAC_CBSISQB; /**< \brief (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */\r
+ __I uint32_t Reserved11[14];\r
+ __IO uint32_t GMAC_ST1RPQ[4]; /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) */\r
+ __I uint32_t Reserved12[12];\r
+ __IO uint32_t GMAC_ST2RPQ[8]; /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) */\r
+ __I uint32_t Reserved13[12];\r
+ __I uint32_t Reserved14[28];\r
+ __O uint32_t GMAC_IERPQ[2]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) */\r
+ __I uint32_t Reserved15[6];\r
+ __O uint32_t GMAC_IDRPQ[2]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) */\r
+ __I uint32_t Reserved16[6];\r
+ __IO uint32_t GMAC_IMRPQ[2]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) */\r
+ __I uint32_t Reserved17[38];\r
+ __IO uint32_t GMAC_ST2ER[4]; /**< \brief (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) */\r
+ __I uint32_t Reserved18[4];\r
+ __IO uint32_t GMAC_ST2CW00; /**< \brief (Gmac Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) */\r
+ __IO uint32_t GMAC_ST2CW10; /**< \brief (Gmac Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) */\r
+ __IO uint32_t GMAC_ST2CW01; /**< \brief (Gmac Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) */\r
+ __IO uint32_t GMAC_ST2CW11; /**< \brief (Gmac Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) */\r
+ __IO uint32_t GMAC_ST2CW02; /**< \brief (Gmac Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) */\r
+ __IO uint32_t GMAC_ST2CW12; /**< \brief (Gmac Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) */\r
+ __IO uint32_t GMAC_ST2CW03; /**< \brief (Gmac Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) */\r
+ __IO uint32_t GMAC_ST2CW13; /**< \brief (Gmac Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) */\r
+ __IO uint32_t GMAC_ST2CW04; /**< \brief (Gmac Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) */\r
+ __IO uint32_t GMAC_ST2CW14; /**< \brief (Gmac Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) */\r
+ __IO uint32_t GMAC_ST2CW05; /**< \brief (Gmac Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) */\r
+ __IO uint32_t GMAC_ST2CW15; /**< \brief (Gmac Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) */\r
+ __IO uint32_t GMAC_ST2CW06; /**< \brief (Gmac Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) */\r
+ __IO uint32_t GMAC_ST2CW16; /**< \brief (Gmac Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) */\r
+ __IO uint32_t GMAC_ST2CW07; /**< \brief (Gmac Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) */\r
+ __IO uint32_t GMAC_ST2CW17; /**< \brief (Gmac Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) */\r
+ __IO uint32_t GMAC_ST2CW08; /**< \brief (Gmac Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) */\r
+ __IO uint32_t GMAC_ST2CW18; /**< \brief (Gmac Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) */\r
+ __IO uint32_t GMAC_ST2CW09; /**< \brief (Gmac Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) */\r
+ __IO uint32_t GMAC_ST2CW19; /**< \brief (Gmac Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) */\r
+ __IO uint32_t GMAC_ST2CW010; /**< \brief (Gmac Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) */\r
+ __IO uint32_t GMAC_ST2CW110; /**< \brief (Gmac Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) */\r
+ __IO uint32_t GMAC_ST2CW011; /**< \brief (Gmac Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) */\r
+ __IO uint32_t GMAC_ST2CW111; /**< \brief (Gmac Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) */\r
+ __IO uint32_t GMAC_ST2CW012; /**< \brief (Gmac Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) */\r
+ __IO uint32_t GMAC_ST2CW112; /**< \brief (Gmac Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) */\r
+ __IO uint32_t GMAC_ST2CW013; /**< \brief (Gmac Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) */\r
+ __IO uint32_t GMAC_ST2CW113; /**< \brief (Gmac Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) */\r
+ __IO uint32_t GMAC_ST2CW014; /**< \brief (Gmac Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) */\r
+ __IO uint32_t GMAC_ST2CW114; /**< \brief (Gmac Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) */\r
+ __IO uint32_t GMAC_ST2CW015; /**< \brief (Gmac Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) */\r
+ __IO uint32_t GMAC_ST2CW115; /**< \brief (Gmac Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) */\r
+ __IO uint32_t GMAC_ST2CW016; /**< \brief (Gmac Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) */\r
+ __IO uint32_t GMAC_ST2CW116; /**< \brief (Gmac Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) */\r
+ __IO uint32_t GMAC_ST2CW017; /**< \brief (Gmac Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) */\r
+ __IO uint32_t GMAC_ST2CW117; /**< \brief (Gmac Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) */\r
+ __IO uint32_t GMAC_ST2CW018; /**< \brief (Gmac Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) */\r
+ __IO uint32_t GMAC_ST2CW118; /**< \brief (Gmac Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) */\r
+ __IO uint32_t GMAC_ST2CW019; /**< \brief (Gmac Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) */\r
+ __IO uint32_t GMAC_ST2CW119; /**< \brief (Gmac Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) */\r
+ __IO uint32_t GMAC_ST2CW020; /**< \brief (Gmac Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) */\r
+ __IO uint32_t GMAC_ST2CW120; /**< \brief (Gmac Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) */\r
+ __IO uint32_t GMAC_ST2CW021; /**< \brief (Gmac Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) */\r
+ __IO uint32_t GMAC_ST2CW121; /**< \brief (Gmac Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) */\r
+ __IO uint32_t GMAC_ST2CW022; /**< \brief (Gmac Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) */\r
+ __IO uint32_t GMAC_ST2CW122; /**< \brief (Gmac Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) */\r
+ __IO uint32_t GMAC_ST2CW023; /**< \brief (Gmac Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) */\r
+ __IO uint32_t GMAC_ST2CW123; /**< \brief (Gmac Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) */\r
+} Gmac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */\r
+#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */\r
+#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */\r
+#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */\r
+#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */\r
+#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */\r
+#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */\r
+#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */\r
+#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */\r
+#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */\r
+#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */\r
+#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */\r
+#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */\r
+#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */\r
+#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */\r
+#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */\r
+#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */\r
+/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */\r
+#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */\r
+#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */\r
+#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */\r
+#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */\r
+#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */\r
+#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */\r
+#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */\r
+#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */\r
+#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */\r
+#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */\r
+#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */\r
+#define GMAC_NCFGR_RXBUFO_Pos 14\r
+#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */\r
+#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)))\r
+#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */\r
+#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */\r
+#define GMAC_NCFGR_CLK_Pos 18\r
+#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */\r
+#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos)))\r
+#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */\r
+#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */\r
+#define GMAC_NCFGR_DBW_Pos 21\r
+#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */\r
+#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)))\r
+#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */\r
+#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */\r
+#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */\r
+#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */\r
+#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */\r
+#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */\r
+#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */\r
+/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */\r
+#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */\r
+#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */\r
+/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */\r
+#define GMAC_UR_RMII (0x1u << 0) /**< \brief (GMAC_UR) Reduced MII Mode */\r
+/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */\r
+#define GMAC_DCFGR_FBLDO_Pos 0\r
+#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */\r
+#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos)))\r
+#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */\r
+#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */\r
+#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */\r
+#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */\r
+#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */\r
+#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */\r
+#define GMAC_DCFGR_RXBMS_Pos 8\r
+#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */\r
+#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos)))\r
+#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 4/8 Kbyte Memory Size */\r
+#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 4/4 Kbytes Memory Size */\r
+#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4/2 Kbytes Memory Size */\r
+#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */\r
+#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */\r
+#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */\r
+#define GMAC_DCFGR_DRBS_Pos 16\r
+#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */\r
+#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)))\r
+#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */\r
+/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */\r
+#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */\r
+#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */\r
+#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */\r
+#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */\r
+#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */\r
+#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */\r
+#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */\r
+/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */\r
+#define GMAC_RBQB_ADDR_Pos 2\r
+#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */\r
+#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)))\r
+/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */\r
+#define GMAC_TBQB_ADDR_Pos 2\r
+#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */\r
+#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)))\r
+/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */\r
+#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */\r
+#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */\r
+#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */\r
+#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */\r
+/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */\r
+#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */\r
+#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */\r
+#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */\r
+#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */\r
+#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Underrun */\r
+#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */\r
+#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */\r
+#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */\r
+#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */\r
+#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */\r
+#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */\r
+#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */\r
+#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */\r
+#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */\r
+#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */\r
+#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */\r
+#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */\r
+#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */\r
+#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */\r
+#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */\r
+#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */\r
+#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */\r
+/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */\r
+#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */\r
+#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */\r
+#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */\r
+#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */\r
+#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Underrun */\r
+#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */\r
+#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */\r
+#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */\r
+#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */\r
+#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */\r
+#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */\r
+#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */\r
+#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */\r
+#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */\r
+#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */\r
+#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */\r
+#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */\r
+#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */\r
+#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */\r
+#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */\r
+#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */\r
+#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */\r
+/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */\r
+#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */\r
+#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */\r
+#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */\r
+#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */\r
+#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Underrun */\r
+#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */\r
+#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */\r
+#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */\r
+#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */\r
+#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */\r
+#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */\r
+#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */\r
+#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */\r
+#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */\r
+#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */\r
+#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */\r
+#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */\r
+#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */\r
+#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */\r
+#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */\r
+#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */\r
+#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */\r
+/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */\r
+#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */\r
+#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */\r
+#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */\r
+#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */\r
+#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Underrun */\r
+#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */\r
+#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */\r
+#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */\r
+#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */\r
+#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */\r
+#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */\r
+#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */\r
+#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */\r
+#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */\r
+#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */\r
+#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */\r
+#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */\r
+#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */\r
+#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */\r
+#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */\r
+#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */\r
+#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */\r
+/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */\r
+#define GMAC_MAN_DATA_Pos 0\r
+#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */\r
+#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)))\r
+#define GMAC_MAN_WTN_Pos 16\r
+#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */\r
+#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)))\r
+#define GMAC_MAN_REGA_Pos 18\r
+#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */\r
+#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)))\r
+#define GMAC_MAN_PHYA_Pos 23\r
+#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */\r
+#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)))\r
+#define GMAC_MAN_OP_Pos 28\r
+#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */\r
+#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)))\r
+#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */\r
+#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */\r
+/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */\r
+#define GMAC_RPQ_RPQ_Pos 0\r
+#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */\r
+/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */\r
+#define GMAC_TPQ_TPQ_Pos 0\r
+#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */\r
+#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)))\r
+/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */\r
+#define GMAC_TPSF_TPB1ADR_Pos 0\r
+#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) Transmit Partial Store and Forward Address */\r
+#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)))\r
+#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */\r
+/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */\r
+#define GMAC_RPSF_RPB1ADR_Pos 0\r
+#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) Receive Partial Store and Forward Address */\r
+#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)))\r
+#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */\r
+/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */\r
+#define GMAC_RJFML_FML_Pos 0\r
+#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) /**< \brief (GMAC_RJFML) Frame Max Length */\r
+#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos)))\r
+/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */\r
+#define GMAC_HRB_ADDR_Pos 0\r
+#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */\r
+#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)))\r
+/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */\r
+#define GMAC_HRT_ADDR_Pos 0\r
+#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */\r
+#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)))\r
+/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */\r
+#define GMAC_SAB_ADDR_Pos 0\r
+#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) /**< \brief (GMAC_SAB) Specific Address 1 */\r
+#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos)))\r
+/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */\r
+#define GMAC_SAT_ADDR_Pos 0\r
+#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) /**< \brief (GMAC_SAT) Specific Address 1 */\r
+#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos)))\r
+/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */\r
+#define GMAC_TIDM1_TID_Pos 0\r
+#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) /**< \brief (GMAC_TIDM1) Type ID Match 1 */\r
+#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos)))\r
+#define GMAC_TIDM1_ENID1 (0x1u << 31) /**< \brief (GMAC_TIDM1) Enable Copying of TID Matched Frames */\r
+/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */\r
+#define GMAC_TIDM2_TID_Pos 0\r
+#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) /**< \brief (GMAC_TIDM2) Type ID Match 2 */\r
+#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos)))\r
+#define GMAC_TIDM2_ENID2 (0x1u << 31) /**< \brief (GMAC_TIDM2) Enable Copying of TID Matched Frames */\r
+/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */\r
+#define GMAC_TIDM3_TID_Pos 0\r
+#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) /**< \brief (GMAC_TIDM3) Type ID Match 3 */\r
+#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos)))\r
+#define GMAC_TIDM3_ENID3 (0x1u << 31) /**< \brief (GMAC_TIDM3) Enable Copying of TID Matched Frames */\r
+/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */\r
+#define GMAC_TIDM4_TID_Pos 0\r
+#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) /**< \brief (GMAC_TIDM4) Type ID Match 4 */\r
+#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos)))\r
+#define GMAC_TIDM4_ENID4 (0x1u << 31) /**< \brief (GMAC_TIDM4) Enable Copying of TID Matched Frames */\r
+/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */\r
+#define GMAC_WOL_IP_Pos 0\r
+#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */\r
+#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)))\r
+#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */\r
+#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */\r
+#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */\r
+#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */\r
+/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */\r
+#define GMAC_IPGS_FL_Pos 0\r
+#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */\r
+#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)))\r
+/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */\r
+#define GMAC_SVLAN_VLAN_TYPE_Pos 0\r
+#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */\r
+#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)))\r
+#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */\r
+/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */\r
+#define GMAC_TPFCP_PEV_Pos 0\r
+#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */\r
+#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)))\r
+#define GMAC_TPFCP_PQ_Pos 8\r
+#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */\r
+#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)))\r
+/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */\r
+#define GMAC_SAMB1_ADDR_Pos 0\r
+#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */\r
+#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)))\r
+/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */\r
+#define GMAC_SAMT1_ADDR_Pos 0\r
+#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */\r
+#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)))\r
+/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */\r
+#define GMAC_NSC_NANOSEC_Pos 0\r
+#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) /**< \brief (GMAC_NSC) 1588 Timer Nanosecond Comparison Value */\r
+#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos)))\r
+/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */\r
+#define GMAC_SCL_SEC_Pos 0\r
+#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) /**< \brief (GMAC_SCL) 1588 Timer Second Comparison Value */\r
+#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos)))\r
+/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */\r
+#define GMAC_SCH_SEC_Pos 0\r
+#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) /**< \brief (GMAC_SCH) 1588 Timer Second Comparison Value */\r
+#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos)))\r
+/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */\r
+#define GMAC_EFTSH_RUD_Pos 0\r
+#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) /**< \brief (GMAC_EFTSH) Register Update */\r
+/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */\r
+#define GMAC_EFRSH_RUD_Pos 0\r
+#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) /**< \brief (GMAC_EFRSH) Register Update */\r
+/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */\r
+#define GMAC_PEFTSH_RUD_Pos 0\r
+#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) /**< \brief (GMAC_PEFTSH) Register Update */\r
+/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */\r
+#define GMAC_PEFRSH_RUD_Pos 0\r
+#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) /**< \brief (GMAC_PEFRSH) Register Update */\r
+/* -------- GMAC_MID : (GMAC Offset: 0x0FC) Module ID Register -------- */\r
+#define GMAC_MID_MREV_Pos 0\r
+#define GMAC_MID_MREV_Msk (0xffffu << GMAC_MID_MREV_Pos) /**< \brief (GMAC_MID) Module Revision */\r
+#define GMAC_MID_MID_Pos 16\r
+#define GMAC_MID_MID_Msk (0xffffu << GMAC_MID_MID_Pos) /**< \brief (GMAC_MID) Module Identification Number */\r
+/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */\r
+#define GMAC_OTLO_TXO_Pos 0\r
+#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */\r
+/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */\r
+#define GMAC_OTHI_TXO_Pos 0\r
+#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */\r
+/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */\r
+#define GMAC_FT_FTX_Pos 0\r
+#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */\r
+/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */\r
+#define GMAC_BCFT_BFTX_Pos 0\r
+#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */\r
+/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */\r
+#define GMAC_MFT_MFTX_Pos 0\r
+#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */\r
+/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */\r
+#define GMAC_PFT_PFTX_Pos 0\r
+#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */\r
+/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */\r
+#define GMAC_BFT64_NFTX_Pos 0\r
+#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT127_NFTX_Pos 0\r
+#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT255_NFTX_Pos 0\r
+#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT511_NFTX_Pos 0\r
+#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT1023_NFTX_Pos 0\r
+#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */\r
+#define GMAC_TBFT1518_NFTX_Pos 0\r
+#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */\r
+#define GMAC_GTBFT1518_NFTX_Pos 0\r
+#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */\r
+/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */\r
+#define GMAC_TUR_TXUNR_Pos 0\r
+#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Underruns */\r
+/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */\r
+#define GMAC_SCF_SCOL_Pos 0\r
+#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */\r
+/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */\r
+#define GMAC_MCF_MCOL_Pos 0\r
+#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */\r
+/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */\r
+#define GMAC_EC_XCOL_Pos 0\r
+#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */\r
+/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */\r
+#define GMAC_LC_LCOL_Pos 0\r
+#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */\r
+/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */\r
+#define GMAC_DTF_DEFT_Pos 0\r
+#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */\r
+/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */\r
+#define GMAC_CSE_CSR_Pos 0\r
+#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */\r
+/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */\r
+#define GMAC_ORLO_RXO_Pos 0\r
+#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */\r
+/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */\r
+#define GMAC_ORHI_RXO_Pos 0\r
+#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */\r
+/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */\r
+#define GMAC_FR_FRX_Pos 0\r
+#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */\r
+/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */\r
+#define GMAC_BCFR_BFRX_Pos 0\r
+#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */\r
+/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */\r
+#define GMAC_MFR_MFRX_Pos 0\r
+#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */\r
+/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */\r
+#define GMAC_PFR_PFRX_Pos 0\r
+#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */\r
+/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */\r
+#define GMAC_BFR64_NFRX_Pos 0\r
+#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR127_NFRX_Pos 0\r
+#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR255_NFRX_Pos 0\r
+#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR511_NFRX_Pos 0\r
+#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR1023_NFRX_Pos 0\r
+#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */\r
+/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */\r
+#define GMAC_TBFR1518_NFRX_Pos 0\r
+#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */\r
+/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */\r
+#define GMAC_TMXBFR_NFRX_Pos 0\r
+#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */\r
+/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */\r
+#define GMAC_UFR_UFRX_Pos 0\r
+#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */\r
+/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */\r
+#define GMAC_OFR_OFRX_Pos 0\r
+#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */\r
+/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */\r
+#define GMAC_JR_JRX_Pos 0\r
+#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */\r
+/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */\r
+#define GMAC_FCSE_FCKR_Pos 0\r
+#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */\r
+/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */\r
+#define GMAC_LFFE_LFER_Pos 0\r
+#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */\r
+/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */\r
+#define GMAC_RSE_RXSE_Pos 0\r
+#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */\r
+/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */\r
+#define GMAC_AE_AER_Pos 0\r
+#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */\r
+/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */\r
+#define GMAC_RRE_RXRER_Pos 0\r
+#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */\r
+/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */\r
+#define GMAC_ROE_RXOVR_Pos 0\r
+#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */\r
+/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */\r
+#define GMAC_IHCE_HCKER_Pos 0\r
+#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */\r
+/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */\r
+#define GMAC_TCE_TCKER_Pos 0\r
+#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */\r
+/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */\r
+#define GMAC_UCE_UCKER_Pos 0\r
+#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */\r
+/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */\r
+#define GMAC_TISUBN_LSBTIR_Pos 0\r
+#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register */\r
+#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos)))\r
+/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */\r
+#define GMAC_TSH_TCS_Pos 0\r
+#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) /**< \brief (GMAC_TSH) Timer Count in Seconds */\r
+#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos)))\r
+/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */\r
+#define GMAC_TSL_TCS_Pos 0\r
+#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) /**< \brief (GMAC_TSL) Timer Count in Seconds */\r
+#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos)))\r
+/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */\r
+#define GMAC_TN_TNS_Pos 0\r
+#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */\r
+#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)))\r
+/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */\r
+#define GMAC_TA_ITDT_Pos 0\r
+#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */\r
+#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)))\r
+#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */\r
+/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */\r
+#define GMAC_TI_CNS_Pos 0\r
+#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */\r
+#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)))\r
+#define GMAC_TI_ACNS_Pos 8\r
+#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */\r
+#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)))\r
+#define GMAC_TI_NIT_Pos 16\r
+#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */\r
+#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)))\r
+/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */\r
+#define GMAC_EFTSL_RUD_Pos 0\r
+#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) /**< \brief (GMAC_EFTSL) Register Update */\r
+/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */\r
+#define GMAC_EFTN_RUD_Pos 0\r
+#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */\r
+/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */\r
+#define GMAC_EFRSL_RUD_Pos 0\r
+#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) /**< \brief (GMAC_EFRSL) Register Update */\r
+/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */\r
+#define GMAC_EFRN_RUD_Pos 0\r
+#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */\r
+/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */\r
+#define GMAC_PEFTSL_RUD_Pos 0\r
+#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) /**< \brief (GMAC_PEFTSL) Register Update */\r
+/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */\r
+#define GMAC_PEFTN_RUD_Pos 0\r
+#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */\r
+/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */\r
+#define GMAC_PEFRSL_RUD_Pos 0\r
+#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) /**< \brief (GMAC_PEFRSL) Register Update */\r
+/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */\r
+#define GMAC_PEFRN_RUD_Pos 0\r
+#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */\r
+/* -------- GMAC_ISRPQ[2] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) -------- */\r
+#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[2]) Receive Complete */\r
+#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[2]) RX Used Bit Read */\r
+#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[2]) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[2]) Transmit Frame Corruption Due to AHB Error */\r
+#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[2]) Transmit Complete */\r
+#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[2]) Receive Overrun */\r
+#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[2]) HRESP Not OK */\r
+/* -------- GMAC_TBQBAPQ[2] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) -------- */\r
+#define GMAC_TBQBAPQ_TXBQBA_Pos 2\r
+#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[2]) Transmit Buffer Queue Base Address */\r
+#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)))\r
+/* -------- GMAC_RBQBAPQ[2] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) -------- */\r
+#define GMAC_RBQBAPQ_RXBQBA_Pos 2\r
+#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[2]) Receive Buffer Queue Base Address */\r
+#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)))\r
+/* -------- GMAC_RBSRPQ[2] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) -------- */\r
+#define GMAC_RBSRPQ_RBS_Pos 0\r
+#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[2]) Receive Buffer Size */\r
+#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)))\r
+/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */\r
+#define GMAC_CBSCR_QBE (0x1u << 0) /**< \brief (GMAC_CBSCR) Queue B CBS Enable */\r
+#define GMAC_CBSCR_QAE (0x1u << 1) /**< \brief (GMAC_CBSCR) Queue A CBS Enable */\r
+/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */\r
+#define GMAC_CBSISQA_IS_Pos 0\r
+#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) /**< \brief (GMAC_CBSISQA) IdleSlope */\r
+#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos)))\r
+/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */\r
+#define GMAC_CBSISQB_IS_Pos 0\r
+#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) /**< \brief (GMAC_CBSISQB) IdleSlope */\r
+#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos)))\r
+/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) -------- */\r
+#define GMAC_ST1RPQ_QNB_Pos 0\r
+#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[4]) Queue Number (0-2) */\r
+#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)))\r
+#define GMAC_ST1RPQ_DSTCM_Pos 4\r
+#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match */\r
+#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)))\r
+#define GMAC_ST1RPQ_UDPM_Pos 12\r
+#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match */\r
+#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)))\r
+#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable */\r
+#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match Enable */\r
+/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) -------- */\r
+#define GMAC_ST2RPQ_QNB_Pos 0\r
+#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Queue Number (0-2) */\r
+#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)))\r
+#define GMAC_ST2RPQ_VLANP_Pos 4\r
+#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[8]) VLAN Priority */\r
+#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)))\r
+#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[8]) VLAN Enable */\r
+#define GMAC_ST2RPQ_I2ETH_Pos 9\r
+#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x */\r
+#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos)))\r
+#define GMAC_ST2RPQ_ETHE (0x1u << 12) /**< \brief (GMAC_ST2RPQ[8]) EtherType Enable */\r
+#define GMAC_ST2RPQ_COMPA_Pos 13\r
+#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */\r
+#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos)))\r
+#define GMAC_ST2RPQ_COMPAE (0x1u << 18) /**< \brief (GMAC_ST2RPQ[8]) Compare A Enable */\r
+#define GMAC_ST2RPQ_COMPB_Pos 19\r
+#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */\r
+#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos)))\r
+#define GMAC_ST2RPQ_COMPBE (0x1u << 24) /**< \brief (GMAC_ST2RPQ[8]) Compare B Enable */\r
+#define GMAC_ST2RPQ_COMPC_Pos 25\r
+#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */\r
+#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos)))\r
+#define GMAC_ST2RPQ_COMPCE (0x1u << 30) /**< \brief (GMAC_ST2RPQ[8]) Compare C Enable */\r
+/* -------- GMAC_IERPQ[2] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) -------- */\r
+#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[2]) Receive Complete */\r
+#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[2]) RX Used Bit Read */\r
+#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[2]) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[2]) Transmit Frame Corruption Due to AHB Error */\r
+#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[2]) Transmit Complete */\r
+#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[2]) Receive Overrun */\r
+#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[2]) HRESP Not OK */\r
+/* -------- GMAC_IDRPQ[2] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) -------- */\r
+#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[2]) Receive Complete */\r
+#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[2]) RX Used Bit Read */\r
+#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[2]) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[2]) Transmit Frame Corruption Due to AHB Error */\r
+#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[2]) Transmit Complete */\r
+#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[2]) Receive Overrun */\r
+#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[2]) HRESP Not OK */\r
+/* -------- GMAC_IMRPQ[2] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) -------- */\r
+#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[2]) Receive Complete */\r
+#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[2]) RX Used Bit Read */\r
+#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[2]) Retry Limit Exceeded or Late Collision */\r
+#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[2]) AHB Error */\r
+#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[2]) Transmit Complete */\r
+#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[2]) Receive Overrun */\r
+#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[2]) HRESP Not OK */\r
+/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) -------- */\r
+#define GMAC_ST2ER_COMPVAL_Pos 0\r
+#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) /**< \brief (GMAC_ST2ER[4]) Ethertype Compare Value */\r
+#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) -------- */\r
+#define GMAC_ST2CW00_MASKVAL_Pos 0\r
+#define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos) /**< \brief (GMAC_ST2CW00) Mask Value */\r
+#define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos)))\r
+#define GMAC_ST2CW00_COMPVAL_Pos 16\r
+#define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos) /**< \brief (GMAC_ST2CW00) Compare Value */\r
+#define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) -------- */\r
+#define GMAC_ST2CW10_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW10) Offset Value in Bytes */\r
+#define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW10_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW10) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW10) Offset from the start of the frame */\r
+#define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) -------- */\r
+#define GMAC_ST2CW01_MASKVAL_Pos 0\r
+#define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos) /**< \brief (GMAC_ST2CW01) Mask Value */\r
+#define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos)))\r
+#define GMAC_ST2CW01_COMPVAL_Pos 16\r
+#define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos) /**< \brief (GMAC_ST2CW01) Compare Value */\r
+#define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) -------- */\r
+#define GMAC_ST2CW11_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW11) Offset Value in Bytes */\r
+#define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW11_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW11) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW11) Offset from the start of the frame */\r
+#define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) -------- */\r
+#define GMAC_ST2CW02_MASKVAL_Pos 0\r
+#define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos) /**< \brief (GMAC_ST2CW02) Mask Value */\r
+#define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos)))\r
+#define GMAC_ST2CW02_COMPVAL_Pos 16\r
+#define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos) /**< \brief (GMAC_ST2CW02) Compare Value */\r
+#define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) -------- */\r
+#define GMAC_ST2CW12_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW12) Offset Value in Bytes */\r
+#define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW12_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW12) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW12) Offset from the start of the frame */\r
+#define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) -------- */\r
+#define GMAC_ST2CW03_MASKVAL_Pos 0\r
+#define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos) /**< \brief (GMAC_ST2CW03) Mask Value */\r
+#define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos)))\r
+#define GMAC_ST2CW03_COMPVAL_Pos 16\r
+#define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos) /**< \brief (GMAC_ST2CW03) Compare Value */\r
+#define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) -------- */\r
+#define GMAC_ST2CW13_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW13) Offset Value in Bytes */\r
+#define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW13_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW13) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW13) Offset from the start of the frame */\r
+#define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) -------- */\r
+#define GMAC_ST2CW04_MASKVAL_Pos 0\r
+#define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos) /**< \brief (GMAC_ST2CW04) Mask Value */\r
+#define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos)))\r
+#define GMAC_ST2CW04_COMPVAL_Pos 16\r
+#define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos) /**< \brief (GMAC_ST2CW04) Compare Value */\r
+#define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) -------- */\r
+#define GMAC_ST2CW14_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW14) Offset Value in Bytes */\r
+#define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW14_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW14) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW14) Offset from the start of the frame */\r
+#define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) -------- */\r
+#define GMAC_ST2CW05_MASKVAL_Pos 0\r
+#define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos) /**< \brief (GMAC_ST2CW05) Mask Value */\r
+#define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos)))\r
+#define GMAC_ST2CW05_COMPVAL_Pos 16\r
+#define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos) /**< \brief (GMAC_ST2CW05) Compare Value */\r
+#define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) -------- */\r
+#define GMAC_ST2CW15_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW15) Offset Value in Bytes */\r
+#define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW15_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW15) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW15) Offset from the start of the frame */\r
+#define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) -------- */\r
+#define GMAC_ST2CW06_MASKVAL_Pos 0\r
+#define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos) /**< \brief (GMAC_ST2CW06) Mask Value */\r
+#define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos)))\r
+#define GMAC_ST2CW06_COMPVAL_Pos 16\r
+#define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos) /**< \brief (GMAC_ST2CW06) Compare Value */\r
+#define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) -------- */\r
+#define GMAC_ST2CW16_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW16) Offset Value in Bytes */\r
+#define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW16_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW16) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW16) Offset from the start of the frame */\r
+#define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) -------- */\r
+#define GMAC_ST2CW07_MASKVAL_Pos 0\r
+#define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos) /**< \brief (GMAC_ST2CW07) Mask Value */\r
+#define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos)))\r
+#define GMAC_ST2CW07_COMPVAL_Pos 16\r
+#define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos) /**< \brief (GMAC_ST2CW07) Compare Value */\r
+#define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) -------- */\r
+#define GMAC_ST2CW17_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW17) Offset Value in Bytes */\r
+#define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW17_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW17) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW17) Offset from the start of the frame */\r
+#define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) -------- */\r
+#define GMAC_ST2CW08_MASKVAL_Pos 0\r
+#define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos) /**< \brief (GMAC_ST2CW08) Mask Value */\r
+#define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos)))\r
+#define GMAC_ST2CW08_COMPVAL_Pos 16\r
+#define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos) /**< \brief (GMAC_ST2CW08) Compare Value */\r
+#define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) -------- */\r
+#define GMAC_ST2CW18_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW18) Offset Value in Bytes */\r
+#define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW18_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW18) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW18) Offset from the start of the frame */\r
+#define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) -------- */\r
+#define GMAC_ST2CW09_MASKVAL_Pos 0\r
+#define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos) /**< \brief (GMAC_ST2CW09) Mask Value */\r
+#define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos)))\r
+#define GMAC_ST2CW09_COMPVAL_Pos 16\r
+#define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos) /**< \brief (GMAC_ST2CW09) Compare Value */\r
+#define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) -------- */\r
+#define GMAC_ST2CW19_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW19) Offset Value in Bytes */\r
+#define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW19_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW19) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW19) Offset from the start of the frame */\r
+#define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) -------- */\r
+#define GMAC_ST2CW010_MASKVAL_Pos 0\r
+#define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos) /**< \brief (GMAC_ST2CW010) Mask Value */\r
+#define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos)))\r
+#define GMAC_ST2CW010_COMPVAL_Pos 16\r
+#define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos) /**< \brief (GMAC_ST2CW010) Compare Value */\r
+#define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) -------- */\r
+#define GMAC_ST2CW110_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW110) Offset Value in Bytes */\r
+#define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW110_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW110) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW110) Offset from the start of the frame */\r
+#define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) -------- */\r
+#define GMAC_ST2CW011_MASKVAL_Pos 0\r
+#define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos) /**< \brief (GMAC_ST2CW011) Mask Value */\r
+#define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos)))\r
+#define GMAC_ST2CW011_COMPVAL_Pos 16\r
+#define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos) /**< \brief (GMAC_ST2CW011) Compare Value */\r
+#define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) -------- */\r
+#define GMAC_ST2CW111_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW111) Offset Value in Bytes */\r
+#define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW111_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW111) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW111) Offset from the start of the frame */\r
+#define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) -------- */\r
+#define GMAC_ST2CW012_MASKVAL_Pos 0\r
+#define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos) /**< \brief (GMAC_ST2CW012) Mask Value */\r
+#define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos)))\r
+#define GMAC_ST2CW012_COMPVAL_Pos 16\r
+#define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos) /**< \brief (GMAC_ST2CW012) Compare Value */\r
+#define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) -------- */\r
+#define GMAC_ST2CW112_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW112) Offset Value in Bytes */\r
+#define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW112_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW112) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW112) Offset from the start of the frame */\r
+#define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) -------- */\r
+#define GMAC_ST2CW013_MASKVAL_Pos 0\r
+#define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos) /**< \brief (GMAC_ST2CW013) Mask Value */\r
+#define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos)))\r
+#define GMAC_ST2CW013_COMPVAL_Pos 16\r
+#define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos) /**< \brief (GMAC_ST2CW013) Compare Value */\r
+#define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) -------- */\r
+#define GMAC_ST2CW113_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW113) Offset Value in Bytes */\r
+#define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW113_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW113) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW113) Offset from the start of the frame */\r
+#define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) -------- */\r
+#define GMAC_ST2CW014_MASKVAL_Pos 0\r
+#define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos) /**< \brief (GMAC_ST2CW014) Mask Value */\r
+#define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos)))\r
+#define GMAC_ST2CW014_COMPVAL_Pos 16\r
+#define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos) /**< \brief (GMAC_ST2CW014) Compare Value */\r
+#define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) -------- */\r
+#define GMAC_ST2CW114_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW114) Offset Value in Bytes */\r
+#define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW114_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW114) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW114) Offset from the start of the frame */\r
+#define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) -------- */\r
+#define GMAC_ST2CW015_MASKVAL_Pos 0\r
+#define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos) /**< \brief (GMAC_ST2CW015) Mask Value */\r
+#define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos)))\r
+#define GMAC_ST2CW015_COMPVAL_Pos 16\r
+#define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos) /**< \brief (GMAC_ST2CW015) Compare Value */\r
+#define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) -------- */\r
+#define GMAC_ST2CW115_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW115) Offset Value in Bytes */\r
+#define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW115_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW115) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW115) Offset from the start of the frame */\r
+#define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) -------- */\r
+#define GMAC_ST2CW016_MASKVAL_Pos 0\r
+#define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos) /**< \brief (GMAC_ST2CW016) Mask Value */\r
+#define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos)))\r
+#define GMAC_ST2CW016_COMPVAL_Pos 16\r
+#define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos) /**< \brief (GMAC_ST2CW016) Compare Value */\r
+#define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) -------- */\r
+#define GMAC_ST2CW116_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW116) Offset Value in Bytes */\r
+#define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW116_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW116) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW116) Offset from the start of the frame */\r
+#define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) -------- */\r
+#define GMAC_ST2CW017_MASKVAL_Pos 0\r
+#define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos) /**< \brief (GMAC_ST2CW017) Mask Value */\r
+#define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos)))\r
+#define GMAC_ST2CW017_COMPVAL_Pos 16\r
+#define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos) /**< \brief (GMAC_ST2CW017) Compare Value */\r
+#define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) -------- */\r
+#define GMAC_ST2CW117_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW117) Offset Value in Bytes */\r
+#define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW117_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW117) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW117) Offset from the start of the frame */\r
+#define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) -------- */\r
+#define GMAC_ST2CW018_MASKVAL_Pos 0\r
+#define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos) /**< \brief (GMAC_ST2CW018) Mask Value */\r
+#define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos)))\r
+#define GMAC_ST2CW018_COMPVAL_Pos 16\r
+#define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos) /**< \brief (GMAC_ST2CW018) Compare Value */\r
+#define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) -------- */\r
+#define GMAC_ST2CW118_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW118) Offset Value in Bytes */\r
+#define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW118_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW118) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW118) Offset from the start of the frame */\r
+#define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) -------- */\r
+#define GMAC_ST2CW019_MASKVAL_Pos 0\r
+#define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos) /**< \brief (GMAC_ST2CW019) Mask Value */\r
+#define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos)))\r
+#define GMAC_ST2CW019_COMPVAL_Pos 16\r
+#define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos) /**< \brief (GMAC_ST2CW019) Compare Value */\r
+#define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) -------- */\r
+#define GMAC_ST2CW119_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW119) Offset Value in Bytes */\r
+#define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW119_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW119) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW119) Offset from the start of the frame */\r
+#define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) -------- */\r
+#define GMAC_ST2CW020_MASKVAL_Pos 0\r
+#define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos) /**< \brief (GMAC_ST2CW020) Mask Value */\r
+#define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos)))\r
+#define GMAC_ST2CW020_COMPVAL_Pos 16\r
+#define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos) /**< \brief (GMAC_ST2CW020) Compare Value */\r
+#define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) -------- */\r
+#define GMAC_ST2CW120_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW120) Offset Value in Bytes */\r
+#define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW120_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW120) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW120) Offset from the start of the frame */\r
+#define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) -------- */\r
+#define GMAC_ST2CW021_MASKVAL_Pos 0\r
+#define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos) /**< \brief (GMAC_ST2CW021) Mask Value */\r
+#define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos)))\r
+#define GMAC_ST2CW021_COMPVAL_Pos 16\r
+#define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos) /**< \brief (GMAC_ST2CW021) Compare Value */\r
+#define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) -------- */\r
+#define GMAC_ST2CW121_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW121) Offset Value in Bytes */\r
+#define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW121_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW121) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW121) Offset from the start of the frame */\r
+#define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) -------- */\r
+#define GMAC_ST2CW022_MASKVAL_Pos 0\r
+#define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos) /**< \brief (GMAC_ST2CW022) Mask Value */\r
+#define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos)))\r
+#define GMAC_ST2CW022_COMPVAL_Pos 16\r
+#define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos) /**< \brief (GMAC_ST2CW022) Compare Value */\r
+#define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) -------- */\r
+#define GMAC_ST2CW122_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW122) Offset Value in Bytes */\r
+#define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW122_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW122) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW122) Offset from the start of the frame */\r
+#define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field */\r
+/* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) -------- */\r
+#define GMAC_ST2CW023_MASKVAL_Pos 0\r
+#define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos) /**< \brief (GMAC_ST2CW023) Mask Value */\r
+#define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos)))\r
+#define GMAC_ST2CW023_COMPVAL_Pos 16\r
+#define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos) /**< \brief (GMAC_ST2CW023) Compare Value */\r
+#define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos)))\r
+/* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) -------- */\r
+#define GMAC_ST2CW123_OFFSVAL_Pos 0\r
+#define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW123) Offset Value in Bytes */\r
+#define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos)))\r
+#define GMAC_ST2CW123_OFFSSTRT_Pos 7\r
+#define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW123) Ethernet Frame Offset Start */\r
+#define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos)))\r
+#define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW123) Offset from the start of the frame */\r
+#define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the EtherType field */\r
+#define GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the IP header field */\r
+#define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_GMAC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_I2SC_COMPONENT_\r
+#define _SAMA5D2_I2SC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Inter-IC Sound Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_I2SC Inter-IC Sound Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief I2sc hardware registers */\r
+typedef struct {\r
+ __O uint32_t I2SC_CR; /**< \brief (I2sc Offset: 0x00) Control Register */\r
+ __IO uint32_t I2SC_MR; /**< \brief (I2sc Offset: 0x04) Mode Register */\r
+ __I uint32_t I2SC_SR; /**< \brief (I2sc Offset: 0x08) Status Register */\r
+ __O uint32_t I2SC_SCR; /**< \brief (I2sc Offset: 0x0C) Status Clear Register */\r
+ __O uint32_t I2SC_SSR; /**< \brief (I2sc Offset: 0x10) Status Set Register */\r
+ __O uint32_t I2SC_IER; /**< \brief (I2sc Offset: 0x14) Interrupt Enable Register */\r
+ __O uint32_t I2SC_IDR; /**< \brief (I2sc Offset: 0x18) Interrupt Disable Register */\r
+ __I uint32_t I2SC_IMR; /**< \brief (I2sc Offset: 0x1C) Interrupt Mask Register */\r
+ __I uint32_t I2SC_RHR; /**< \brief (I2sc Offset: 0x20) Receiver Holding Register */\r
+ __O uint32_t I2SC_THR; /**< \brief (I2sc Offset: 0x24) Transmitter Holding Register */\r
+ __I uint32_t I2SC_VERSION; /**< \brief (I2sc Offset: 0x28) Version Register */\r
+} I2sc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- I2SC_CR : (I2SC Offset: 0x00) Control Register -------- */\r
+#define I2SC_CR_RXEN (0x1u << 0) /**< \brief (I2SC_CR) Receiver Enable */\r
+#define I2SC_CR_RXDIS (0x1u << 1) /**< \brief (I2SC_CR) Receiver Disable */\r
+#define I2SC_CR_CKEN (0x1u << 2) /**< \brief (I2SC_CR) Clocks Enable */\r
+#define I2SC_CR_CKDIS (0x1u << 3) /**< \brief (I2SC_CR) Clocks Disable */\r
+#define I2SC_CR_TXEN (0x1u << 4) /**< \brief (I2SC_CR) Transmitter Enable */\r
+#define I2SC_CR_TXDIS (0x1u << 5) /**< \brief (I2SC_CR) Transmitter Disable */\r
+#define I2SC_CR_SWRST (0x1u << 7) /**< \brief (I2SC_CR) Software Reset */\r
+/* -------- I2SC_MR : (I2SC Offset: 0x04) Mode Register -------- */\r
+#define I2SC_MR_MODE (0x1u << 0) /**< \brief (I2SC_MR) Inter-IC Sound Controller Mode */\r
+#define I2SC_MR_MODE_SLAVE (0x0u << 0) /**< \brief (I2SC_MR) I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization. */\r
+#define I2SC_MR_MODE_MASTER (0x1u << 0) /**< \brief (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if I2SC_MR.IMCKMODE is set. */\r
+#define I2SC_MR_DATALENGTH_Pos 2\r
+#define I2SC_MR_DATALENGTH_Msk (0x7u << I2SC_MR_DATALENGTH_Pos) /**< \brief (I2SC_MR) Data Word Length */\r
+#define I2SC_MR_DATALENGTH(value) ((I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos)))\r
+#define I2SC_MR_DATALENGTH_32_BITS (0x0u << 2) /**< \brief (I2SC_MR) Data length is set to 32 bits */\r
+#define I2SC_MR_DATALENGTH_24_BITS (0x1u << 2) /**< \brief (I2SC_MR) Data length is set to 24 bits */\r
+#define I2SC_MR_DATALENGTH_20_BITS (0x2u << 2) /**< \brief (I2SC_MR) Data length is set to 20 bits */\r
+#define I2SC_MR_DATALENGTH_18_BITS (0x3u << 2) /**< \brief (I2SC_MR) Data length is set to 18 bits */\r
+#define I2SC_MR_DATALENGTH_16_BITS (0x4u << 2) /**< \brief (I2SC_MR) Data length is set to 16 bits */\r
+#define I2SC_MR_DATALENGTH_16_BITS_COMPACT (0x5u << 2) /**< \brief (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. */\r
+#define I2SC_MR_DATALENGTH_8_BITS (0x6u << 2) /**< \brief (I2SC_MR) Data length is set to 8 bits */\r
+#define I2SC_MR_DATALENGTH_8_BITS_COMPACT (0x7u << 2) /**< \brief (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. */\r
+#define I2SC_MR_FORMAT_Pos 6\r
+#define I2SC_MR_FORMAT_Msk (0x3u << I2SC_MR_FORMAT_Pos) /**< \brief (I2SC_MR) Data Format */\r
+#define I2SC_MR_FORMAT(value) ((I2SC_MR_FORMAT_Msk & ((value) << I2SC_MR_FORMAT_Pos)))\r
+#define I2SC_MR_FORMAT_I2S (0x0u << 6) /**< \brief (I2SC_MR) I2S format, stereo with I2SWS low for left channel, and MSB of sample starting one I2SCK period after I2SWS edge */\r
+#define I2SC_MR_FORMAT_LJ (0x1u << 6) /**< \brief (I2SC_MR) Left-justified format, stereo with I2SWS high for left channel, and MSB of sample starting on I2SWS edge */\r
+#define I2SC_MR_FORMAT_TDM (0x2u << 6) /**< \brief (I2SC_MR) TDM format, with (NBCHAN + 1) channels, I2SWS high at beginning of first channel, and MSB of sample starting one ISCK period after I2SWS edge */\r
+#define I2SC_MR_FORMAT_TDMLJ (0x3u << 6) /**< \brief (I2SC_MR) TDM format, left-justified, with (NBCHAN + 1) channels, I2SWS high at beginning of first channel, and MSB of sample starting on I2SWS edge */\r
+#define I2SC_MR_RXMONO (0x1u << 8) /**< \brief (I2SC_MR) Receive Mono */\r
+#define I2SC_MR_RXDMA (0x1u << 9) /**< \brief (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver */\r
+#define I2SC_MR_RXLOOP (0x1u << 10) /**< \brief (I2SC_MR) Loop-back Test Mode */\r
+#define I2SC_MR_TXMONO (0x1u << 12) /**< \brief (I2SC_MR) Transmit Mono */\r
+#define I2SC_MR_TXDMA (0x1u << 13) /**< \brief (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter */\r
+#define I2SC_MR_TXSAME (0x1u << 14) /**< \brief (I2SC_MR) Transmit Data when Underrun */\r
+#define I2SC_MR_NBCHAN_Pos 16\r
+#define I2SC_MR_NBCHAN_Msk (0x7u << I2SC_MR_NBCHAN_Pos) /**< \brief (I2SC_MR) Number of TDM Channels-1 */\r
+#define I2SC_MR_NBCHAN(value) ((I2SC_MR_NBCHAN_Msk & ((value) << I2SC_MR_NBCHAN_Pos)))\r
+#define I2SC_MR_TDMFS_Pos 22\r
+#define I2SC_MR_TDMFS_Msk (0x3u << I2SC_MR_TDMFS_Pos) /**< \brief (I2SC_MR) TDM Frame Synchronization */\r
+#define I2SC_MR_TDMFS(value) ((I2SC_MR_TDMFS_Msk & ((value) << I2SC_MR_TDMFS_Pos)))\r
+#define I2SC_MR_TDMFS_SLOT (0x0u << 22) /**< \brief (I2SC_MR) I2SWS pulse is high for one time slot at beginning of frame */\r
+#define I2SC_MR_TDMFS_HALF (0x1u << 22) /**< \brief (I2SC_MR) I2SWS pulse is high for half the time slots at beginning of frame, i.e., half the IWS period */\r
+#define I2SC_MR_TDMFS_BIT (0x2u << 22) /**< \brief (I2SC_MR) I2SWS pulse is high for one bit period at beginning of frame, i.e., one ISCK period */\r
+#define I2SC_MR_IMCKFS_Pos 24\r
+#define I2SC_MR_IMCKFS_Msk (0x3fu << I2SC_MR_IMCKFS_Pos) /**< \brief (I2SC_MR) Master Clock to fs Ratio */\r
+#define I2SC_MR_IMCKFS(value) ((I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos)))\r
+#define I2SC_MR_IMCKFS_M2SF32_64_96_128 (0x0u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 32 for two channels, set to 64 for 4 channels, set to 96 for 6 channels and set to 128 for 8 channels. */\r
+#define I2SC_MR_IMCKFS_M2SF64_128_192_256 (0x1u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 64 for two channels, set to 128 for 4 channels, set to 192 for 6 channels and set to 256 for 8 channels. */\r
+#define I2SC_MR_IMCKFS_M2SF96_192_384 (0x2u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 96 for two channels, set to 192 for 4 channels and set to 384 for 8 channels */\r
+#define I2SC_MR_IMCKFS_M2SF128_256_384_512 (0x3u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 128 for two channels, set to 256 for 4 channels set to 384 for 6 channels and set to 512 for 8 channels. */\r
+#define I2SC_MR_IMCKFS_M2SF192_384_768 (0x5u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 192 for two channels, set to 384 for 4 channels and set to 768 for 8 channels. */\r
+#define I2SC_MR_IMCKFS_M2SF256_512_768_1024 (0x7u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 256 for two channels, set to 512 for 4 channels, set to 768 for 6 channels and set to 1024 for 8 channels. */\r
+#define I2SC_MR_IMCKFS_M2SF384_768_1536 (0xBu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 384 for two channels, set to 768 for 4 channels and set to 1536 for 8 channels. */\r
+#define I2SC_MR_IMCKFS_M2SF512_1024_1536_2048 (0xFu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 512 for two channels, set to 1024 for 4 channels, set to 1536 for 6 channels and set to 2048 for 8 channels. */\r
+#define I2SC_MR_IMCKFS_M2SF768_1536 (0x17u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 768 for two channels and set to 1536 for 4 channels. */\r
+#define I2SC_MR_IMCKFS_M2SF1024_2048 (0x1Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 1024 for two channels and set to 2048 for 4 channels. */\r
+#define I2SC_MR_IMCKFS_M2SF1536 (0x2Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 1536. */\r
+#define I2SC_MR_IMCKFS_M2SF2048 (0x3Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 2048. */\r
+#define I2SC_MR_IMCKMODE (0x1u << 30) /**< \brief (I2SC_MR) Master Clock Mode */\r
+#define I2SC_MR_IWS (0x1u << 31) /**< \brief (I2SC_MR) I2SWS Slot Width */\r
+/* -------- I2SC_SR : (I2SC Offset: 0x08) Status Register -------- */\r
+#define I2SC_SR_RXEN (0x1u << 0) /**< \brief (I2SC_SR) Receiver Enabled */\r
+#define I2SC_SR_RXRDY (0x1u << 1) /**< \brief (I2SC_SR) Receive Ready */\r
+#define I2SC_SR_RXOR (0x1u << 2) /**< \brief (I2SC_SR) Receive Overrun */\r
+#define I2SC_SR_TXEN (0x1u << 4) /**< \brief (I2SC_SR) Transmitter Enabled */\r
+#define I2SC_SR_TXRDY (0x1u << 5) /**< \brief (I2SC_SR) Transmit Ready */\r
+#define I2SC_SR_TXUR (0x1u << 6) /**< \brief (I2SC_SR) Transmit Underrun */\r
+#define I2SC_SR_RXORCH_Pos 8\r
+#define I2SC_SR_RXORCH_Msk (0xffu << I2SC_SR_RXORCH_Pos) /**< \brief (I2SC_SR) Receive Overrun Channel */\r
+#define I2SC_SR_TXURCH30_Pos 20\r
+#define I2SC_SR_TXURCH30_Msk (0xfu << I2SC_SR_TXURCH30_Pos) /**< \brief (I2SC_SR) Transmit Underrun Channel */\r
+#define I2SC_SR_TXURCH74_Pos 24\r
+#define I2SC_SR_TXURCH74_Msk (0xfu << I2SC_SR_TXURCH74_Pos) /**< \brief (I2SC_SR) Transmit Underrun Channel */\r
+/* -------- I2SC_SCR : (I2SC Offset: 0x0C) Status Clear Register -------- */\r
+#define I2SC_SCR_RXOR (0x1u << 2) /**< \brief (I2SC_SCR) Receive Overrun Status Clear */\r
+#define I2SC_SCR_TXUR (0x1u << 6) /**< \brief (I2SC_SCR) Transmit Underrun Status Clear */\r
+#define I2SC_SCR_RXORCH_Pos 8\r
+#define I2SC_SCR_RXORCH_Msk (0xffu << I2SC_SCR_RXORCH_Pos) /**< \brief (I2SC_SCR) Receive Overrun Per Channel Status Clear */\r
+#define I2SC_SCR_RXORCH(value) ((I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos)))\r
+#define I2SC_SCR_TXURCH30_Pos 20\r
+#define I2SC_SCR_TXURCH30_Msk (0xfu << I2SC_SCR_TXURCH30_Pos) /**< \brief (I2SC_SCR) Transmit Underrun Per Channel for Channel 30 Status Clear */\r
+#define I2SC_SCR_TXURCH30(value) ((I2SC_SCR_TXURCH30_Msk & ((value) << I2SC_SCR_TXURCH30_Pos)))\r
+#define I2SC_SCR_TXURCH74_Pos 24\r
+#define I2SC_SCR_TXURCH74_Msk (0xfu << I2SC_SCR_TXURCH74_Pos) /**< \brief (I2SC_SCR) Transmit Underrun Per Channel for Channel 74 Status Clear */\r
+#define I2SC_SCR_TXURCH74(value) ((I2SC_SCR_TXURCH74_Msk & ((value) << I2SC_SCR_TXURCH74_Pos)))\r
+/* -------- I2SC_SSR : (I2SC Offset: 0x10) Status Set Register -------- */\r
+#define I2SC_SSR_RXOR (0x1u << 2) /**< \brief (I2SC_SSR) Receive Overrun Status Set */\r
+#define I2SC_SSR_TXUR (0x1u << 6) /**< \brief (I2SC_SSR) Transmit Underrun Status Set */\r
+#define I2SC_SSR_RXORCH_Pos 8\r
+#define I2SC_SSR_RXORCH_Msk (0xffu << I2SC_SSR_RXORCH_Pos) /**< \brief (I2SC_SSR) Receive Overrun Per Channel Status Set */\r
+#define I2SC_SSR_RXORCH(value) ((I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos)))\r
+#define I2SC_SSR_TXURCH30_Pos 20\r
+#define I2SC_SSR_TXURCH30_Msk (0xfu << I2SC_SSR_TXURCH30_Pos) /**< \brief (I2SC_SSR) Transmit Underrun Per Channel for Channel 30 Status Set */\r
+#define I2SC_SSR_TXURCH30(value) ((I2SC_SSR_TXURCH30_Msk & ((value) << I2SC_SSR_TXURCH30_Pos)))\r
+#define I2SC_SSR_TXURCH74_Pos 24\r
+#define I2SC_SSR_TXURCH74_Msk (0xfu << I2SC_SSR_TXURCH74_Pos) /**< \brief (I2SC_SSR) Transmit Underrun Per Channel for Channel 74 Status Set */\r
+#define I2SC_SSR_TXURCH74(value) ((I2SC_SSR_TXURCH74_Msk & ((value) << I2SC_SSR_TXURCH74_Pos)))\r
+/* -------- I2SC_IER : (I2SC Offset: 0x14) Interrupt Enable Register -------- */\r
+#define I2SC_IER_RXRDY (0x1u << 1) /**< \brief (I2SC_IER) Receiver Ready Interrupt Enable */\r
+#define I2SC_IER_RXOR (0x1u << 2) /**< \brief (I2SC_IER) Receiver Overrun Interrupt Enable */\r
+#define I2SC_IER_TXRDY (0x1u << 5) /**< \brief (I2SC_IER) Transmit Ready Interrupt Enable */\r
+#define I2SC_IER_TXUR (0x1u << 6) /**< \brief (I2SC_IER) Transmit Underflow Interrupt Enable */\r
+/* -------- I2SC_IDR : (I2SC Offset: 0x18) Interrupt Disable Register -------- */\r
+#define I2SC_IDR_RXRDY (0x1u << 1) /**< \brief (I2SC_IDR) Receiver Ready Interrupt Disable */\r
+#define I2SC_IDR_RXOR (0x1u << 2) /**< \brief (I2SC_IDR) Receiver Overrun Interrupt Disable */\r
+#define I2SC_IDR_TXRDY (0x1u << 5) /**< \brief (I2SC_IDR) Transmit Ready Interrupt Disable */\r
+#define I2SC_IDR_TXUR (0x1u << 6) /**< \brief (I2SC_IDR) Transmit Underflow Interrupt Disable */\r
+/* -------- I2SC_IMR : (I2SC Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define I2SC_IMR_RXRDY (0x1u << 1) /**< \brief (I2SC_IMR) Receiver Ready Interrupt Disable */\r
+#define I2SC_IMR_RXOR (0x1u << 2) /**< \brief (I2SC_IMR) Receiver Overrun Interrupt Disable */\r
+#define I2SC_IMR_TXRDY (0x1u << 5) /**< \brief (I2SC_IMR) Transmit Ready Interrupt Disable */\r
+#define I2SC_IMR_TXUR (0x1u << 6) /**< \brief (I2SC_IMR) Transmit Underflow Interrupt Disable */\r
+/* -------- I2SC_RHR : (I2SC Offset: 0x20) Receiver Holding Register -------- */\r
+#define I2SC_RHR_RHR_Pos 0\r
+#define I2SC_RHR_RHR_Msk (0xffffffffu << I2SC_RHR_RHR_Pos) /**< \brief (I2SC_RHR) Receiver Holding Register */\r
+/* -------- I2SC_THR : (I2SC Offset: 0x24) Transmitter Holding Register -------- */\r
+#define I2SC_THR_THR_Pos 0\r
+#define I2SC_THR_THR_Msk (0xffffffffu << I2SC_THR_THR_Pos) /**< \brief (I2SC_THR) Transmitter Holding Register */\r
+#define I2SC_THR_THR(value) ((I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos)))\r
+/* -------- I2SC_VERSION : (I2SC Offset: 0x28) Version Register -------- */\r
+#define I2SC_VERSION_VERSION_Pos 0\r
+#define I2SC_VERSION_VERSION_Msk (0xfffu << I2SC_VERSION_VERSION_Pos) /**< \brief (I2SC_VERSION) Version of the Hardware Module */\r
+#define I2SC_VERSION_MFN_Pos 16\r
+#define I2SC_VERSION_MFN_Msk (0x7u << I2SC_VERSION_MFN_Pos) /**< \brief (I2SC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_I2SC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_ICM_COMPONENT_\r
+#define _SAMA5D2_ICM_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_ICM Integrity Check Monitor */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Icm hardware registers */\r
+typedef struct {\r
+ __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */\r
+ __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */\r
+ __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */\r
+ __I uint32_t Reserved1[1];\r
+ __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */\r
+ __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */\r
+ __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */\r
+ __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */\r
+ __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */\r
+ __I uint32_t Reserved2[3];\r
+ __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */\r
+ __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */\r
+ __O uint32_t ICM_UIHVAL[16]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */\r
+ __I uint32_t Reserved3[29];\r
+ __I uint32_t ICM_ADDRSIZE; /**< \brief (Icm Offset: 0xEC) Address Size Register */\r
+ __I uint32_t ICM_IPNAME[2]; /**< \brief (Icm Offset: 0xF0) IP Name 1 Register */\r
+ __I uint32_t ICM_FEATURES; /**< \brief (Icm Offset: 0xF8) Feature Register */\r
+ __I uint32_t ICM_VERSION; /**< \brief (Icm Offset: 0xFC) Version Register */\r
+} Icm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */\r
+#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */\r
+#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */\r
+#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */\r
+#define ICM_CFG_BBC_Pos 4\r
+#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */\r
+#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)))\r
+#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */\r
+#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */\r
+#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */\r
+#define ICM_CFG_UALGO_Pos 13\r
+#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */\r
+#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)))\r
+#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */\r
+#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */\r
+#define ICM_CFG_UALGO_SHA384 (0x2u << 13) /**< \brief (ICM_CFG) SHA384 algorithm processed */\r
+#define ICM_CFG_UALGO_SHA512 (0x3u << 13) /**< \brief (ICM_CFG) SHA512 algorithm processed */\r
+#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */\r
+#define ICM_CFG_HAPROT_Pos 16\r
+#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */\r
+#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)))\r
+#define ICM_CFG_DAPROT_Pos 24\r
+#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */\r
+#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)))\r
+/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */\r
+#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */\r
+#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */\r
+#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */\r
+#define ICM_CTRL_REHASH_Pos 4\r
+#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */\r
+#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)))\r
+#define ICM_CTRL_RMDIS_Pos 8\r
+#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */\r
+#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)))\r
+#define ICM_CTRL_RMEN_Pos 12\r
+#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */\r
+#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)))\r
+/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */\r
+#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */\r
+#define ICM_SR_RAWRMDIS_Pos 8\r
+#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Raw Status */\r
+#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)))\r
+#define ICM_SR_RMDIS_Pos 12\r
+#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */\r
+#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)))\r
+/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */\r
+#define ICM_IER_RHC_Pos 0\r
+#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */\r
+#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)))\r
+#define ICM_IER_RDM_Pos 4\r
+#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */\r
+#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)))\r
+#define ICM_IER_RBE_Pos 8\r
+#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */\r
+#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)))\r
+#define ICM_IER_RWC_Pos 12\r
+#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */\r
+#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)))\r
+#define ICM_IER_REC_Pos 16\r
+#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */\r
+#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)))\r
+#define ICM_IER_RSU_Pos 20\r
+#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */\r
+#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)))\r
+#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */\r
+/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */\r
+#define ICM_IDR_RHC_Pos 0\r
+#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */\r
+#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)))\r
+#define ICM_IDR_RDM_Pos 4\r
+#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */\r
+#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)))\r
+#define ICM_IDR_RBE_Pos 8\r
+#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */\r
+#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)))\r
+#define ICM_IDR_RWC_Pos 12\r
+#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */\r
+#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)))\r
+#define ICM_IDR_REC_Pos 16\r
+#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */\r
+#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)))\r
+#define ICM_IDR_RSU_Pos 20\r
+#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */\r
+#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)))\r
+#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */\r
+/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */\r
+#define ICM_IMR_RHC_Pos 0\r
+#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */\r
+#define ICM_IMR_RDM_Pos 4\r
+#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */\r
+#define ICM_IMR_RBE_Pos 8\r
+#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */\r
+#define ICM_IMR_RWC_Pos 12\r
+#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */\r
+#define ICM_IMR_REC_Pos 16\r
+#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */\r
+#define ICM_IMR_RSU_Pos 20\r
+#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */\r
+#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */\r
+/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */\r
+#define ICM_ISR_RHC_Pos 0\r
+#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */\r
+#define ICM_ISR_RDM_Pos 4\r
+#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */\r
+#define ICM_ISR_RBE_Pos 8\r
+#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */\r
+#define ICM_ISR_RWC_Pos 12\r
+#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */\r
+#define ICM_ISR_REC_Pos 16\r
+#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */\r
+#define ICM_ISR_RSU_Pos 20\r
+#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */\r
+#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */\r
+/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */\r
+#define ICM_UASR_URAT_Pos 0\r
+#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */\r
+#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */\r
+#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */\r
+#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */\r
+#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */\r
+#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */\r
+/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */\r
+#define ICM_DSCR_DASA_Pos 6\r
+#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */\r
+#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)))\r
+/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */\r
+#define ICM_HASH_HASA_Pos 8\r
+#define ICM_HASH_HASA_Msk (0xffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */\r
+#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)))\r
+/* -------- ICM_UIHVAL[16] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */\r
+#define ICM_UIHVAL_VAL_Pos 0\r
+#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[16]) Initial Hash Value */\r
+#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)))\r
+/* -------- ICM_ADDRSIZE : (ICM Offset: 0xEC) Address Size Register -------- */\r
+#define ICM_ADDRSIZE_ADDRSIZE_Pos 0\r
+#define ICM_ADDRSIZE_ADDRSIZE_Msk (0xffffu << ICM_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (ICM_ADDRSIZE) Peripheral Bus Address Area Size */\r
+/* -------- ICM_IPNAME[2] : (ICM Offset: 0xF0) IP Name 1 Register -------- */\r
+#define ICM_IPNAME_IPNAME_Pos 0\r
+#define ICM_IPNAME_IPNAME_Msk (0xffffffffu << ICM_IPNAME_IPNAME_Pos) /**< \brief (ICM_IPNAME[2]) IP Name in ASCII Format */\r
+/* -------- ICM_FEATURES : (ICM Offset: 0xF8) Feature Register -------- */\r
+#define ICM_FEATURES_CFGALGO (0x1u << 0) /**< \brief (ICM_FEATURES) Configurable Algorithms */\r
+#define ICM_FEATURES_RFU (0x1u << 1) /**< \brief (ICM_FEATURES) Reserved for Future Use */\r
+#define ICM_FEATURES_CFGPP (0x1u << 2) /**< \brief (ICM_FEATURES) Configurable Processing Period */\r
+#define ICM_FEATURES_HDPP (0x1u << 3) /**< \brief (ICM_FEATURES) Hardcoded Processing Period */\r
+#define ICM_FEATURES_PDC (0x1u << 4) /**< \brief (ICM_FEATURES) Peripheral DMA Logic */\r
+#define ICM_FEATURES_NAIS (0x1u << 5) /**< \brief (ICM_FEATURES) No Access to Intermediate State */\r
+#define ICM_FEATURES_EF (0x1u << 6) /**< \brief (ICM_FEATURES) Embedded LFSR */\r
+#define ICM_FEATURES_SI (0x1u << 7) /**< \brief (ICM_FEATURES) Scan Intrusion */\r
+#define ICM_FEATURES_BTYP (0x1u << 8) /**< \brief (ICM_FEATURES) Bridge Type */\r
+#define ICM_FEATURES_PDCOFF0C (0x1u << 9) /**< \brief (ICM_FEATURES) PDC Offset is 0x0C */\r
+#define ICM_FEATURES_HSHA1 (0x1u << 16) /**< \brief (ICM_FEATURES) SHA1 Hardcoded Mode */\r
+#define ICM_FEATURES_HSHA224 (0x1u << 17) /**< \brief (ICM_FEATURES) SHA224 Hardcoded Mode */\r
+#define ICM_FEATURES_HSHA256 (0x1u << 18) /**< \brief (ICM_FEATURES) SHA256 Hardcoded Mode */\r
+#define ICM_FEATURES_HSHA384 (0x1u << 19) /**< \brief (ICM_FEATURES) SHA384 Hardcoded Mode */\r
+#define ICM_FEATURES_HSHA512 (0x1u << 20) /**< \brief (ICM_FEATURES) SHA512 Hardcoded Mode */\r
+/* -------- ICM_VERSION : (ICM Offset: 0xFC) Version Register -------- */\r
+#define ICM_VERSION_VERSION_Pos 0\r
+#define ICM_VERSION_VERSION_Msk (0xfffu << ICM_VERSION_VERSION_Pos) /**< \brief (ICM_VERSION) Version of the Hardware Module */\r
+#define ICM_VERSION_MFN_Pos 16\r
+#define ICM_VERSION_MFN_Msk (0x7u << ICM_VERSION_MFN_Pos) /**< \brief (ICM_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_ICM_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_ISC_COMPONENT_\r
+#define _SAMA5D2_ISC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Image Sensor Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_ISC Image Sensor Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief IscSub0 hardware registers */\r
+typedef struct {\r
+ __IO uint32_t ISC_DAD; /**< \brief (IscSub0 Offset: 0x0) DMA Address 0 Register */\r
+ __IO uint32_t ISC_DST; /**< \brief (IscSub0 Offset: 0x4) DMA Stride 0 Register */\r
+} IscSub0;\r
+/** \brief Isc hardware registers */\r
+#define ISCSUB0_NUMBER 3\r
+typedef struct {\r
+ __O uint32_t ISC_CTRLEN; /**< \brief (Isc Offset: 0x00) Control Enable Register */\r
+ __O uint32_t ISC_CTRLDIS; /**< \brief (Isc Offset: 0x04) Control Disable Register */\r
+ __I uint32_t ISC_CTRLSR; /**< \brief (Isc Offset: 0x08) Control Status Register */\r
+ __IO uint32_t ISC_PFE_CFG0; /**< \brief (Isc Offset: 0x0C) Parallel Front End Configuration 0 Register */\r
+ __IO uint32_t ISC_PFE_CFG1; /**< \brief (Isc Offset: 0x10) Parallel Front End Configuration 1 Register */\r
+ __IO uint32_t ISC_PFE_CFG2; /**< \brief (Isc Offset: 0x14) Parallel Front End Configuration 2 Register */\r
+ __O uint32_t ISC_CLKEN; /**< \brief (Isc Offset: 0x18) Clock Enable Register */\r
+ __O uint32_t ISC_CLKDIS; /**< \brief (Isc Offset: 0x1C) Clock Disable Register */\r
+ __I uint32_t ISC_CLKSR; /**< \brief (Isc Offset: 0x20) Clock Status Register */\r
+ __IO uint32_t ISC_CLKCFG; /**< \brief (Isc Offset: 0x24) Clock Configuration Register */\r
+ __O uint32_t ISC_INTEN; /**< \brief (Isc Offset: 0x28) Interrupt Enable Register */\r
+ __O uint32_t ISC_INTDIS; /**< \brief (Isc Offset: 0x2C) Interrupt Disable Register */\r
+ __I uint32_t ISC_INTMASK; /**< \brief (Isc Offset: 0x30) Interrupt Mask Register */\r
+ __I uint32_t ISC_INTSR; /**< \brief (Isc Offset: 0x34) Interrupt Status Register */\r
+ __I uint32_t Reserved1[8];\r
+ __IO uint32_t ISC_WB_CTRL; /**< \brief (Isc Offset: 0x58) White Balance Control Register */\r
+ __IO uint32_t ISC_WB_CFG; /**< \brief (Isc Offset: 0x5C) White Balance Configuration Register */\r
+ __IO uint32_t ISC_WB_O_RGR; /**< \brief (Isc Offset: 0x60) White Balance Offset for R, GR Register */\r
+ __IO uint32_t ISC_WB_O_BGB; /**< \brief (Isc Offset: 0x64) White Balance Offset for B, GB Register */\r
+ __IO uint32_t ISC_WB_G_RGR; /**< \brief (Isc Offset: 0x68) White Balance Gain for R, GR Register */\r
+ __IO uint32_t ISC_WB_G_BGB; /**< \brief (Isc Offset: 0x6C) White Balance Gain for B, GB Register */\r
+ __IO uint32_t ISC_CFA_CTRL; /**< \brief (Isc Offset: 0x70) Color Filter Array Control Register */\r
+ __IO uint32_t ISC_CFA_CFG; /**< \brief (Isc Offset: 0x74) Color Filter Array Configuration Register */\r
+ __IO uint32_t ISC_CC_CTRL; /**< \brief (Isc Offset: 0x78) Color Correction Control Register */\r
+ __IO uint32_t ISC_CC_RR_RG; /**< \brief (Isc Offset: 0x7C) Color Correction RR RG Register */\r
+ __IO uint32_t ISC_CC_RB_OR; /**< \brief (Isc Offset: 0x80) Color Correction RB OR Register */\r
+ __IO uint32_t ISC_CC_GR_GG; /**< \brief (Isc Offset: 0x84) Color Correction GR GG Register */\r
+ __IO uint32_t ISC_CC_GB_OG; /**< \brief (Isc Offset: 0x88) Color Correction GB OG Register */\r
+ __IO uint32_t ISC_CC_BR_BG; /**< \brief (Isc Offset: 0x8C) Color Correction BR BG Register */\r
+ __IO uint32_t ISC_CC_BB_OB; /**< \brief (Isc Offset: 0x90) Color Correction BB OB Register */\r
+ __IO uint32_t ISC_GAM_CTRL; /**< \brief (Isc Offset: 0x94) Gamma Correction Control Register */\r
+ __IO uint32_t ISC_GAM_BENTRY[64]; /**< \brief (Isc Offset: 0x98) Gamma Correction Blue Entry */\r
+ __IO uint32_t ISC_GAM_GENTRY[64]; /**< \brief (Isc Offset: 0x198) Gamma Correction Green Entry */\r
+ __IO uint32_t ISC_GAM_RENTRY[64]; /**< \brief (Isc Offset: 0x298) Gamma Correction Red Entry */\r
+ __IO uint32_t ISC_CSC_CTRL; /**< \brief (Isc Offset: 0x398) Color Space Conversion Control Register */\r
+ __IO uint32_t ISC_CSC_YR_YG; /**< \brief (Isc Offset: 0x39C) Color Space Conversion YR, YG Register */\r
+ __IO uint32_t ISC_CSC_YB_OY; /**< \brief (Isc Offset: 0x3A0) Color Space Conversion YB, OY Register */\r
+ __IO uint32_t ISC_CSC_CBR_CBG; /**< \brief (Isc Offset: 0x3A4) Color Space Conversion CBR CBG Register */\r
+ __IO uint32_t ISC_CSC_CBB_OCB; /**< \brief (Isc Offset: 0x3A8) Color Space Conversion CBB OCB Register */\r
+ __IO uint32_t ISC_CSC_CRR_CRG; /**< \brief (Isc Offset: 0x3AC) Color Space Conversion CRR CRG Register */\r
+ __IO uint32_t ISC_CSC_CRB_OCR; /**< \brief (Isc Offset: 0x3B0) Color Space Conversion CRB OCR Register */\r
+ __IO uint32_t ISC_CBC_CTRL; /**< \brief (Isc Offset: 0x3B4) Contrast and Brightness Control Register */\r
+ __IO uint32_t ISC_CBC_CFG; /**< \brief (Isc Offset: 0x3B8) Contrast and Brightness Configuration Register */\r
+ __IO uint32_t ISC_CBC_BRIGHT; /**< \brief (Isc Offset: 0x3BC) Contrast and Brightness, Brightness Register */\r
+ __IO uint32_t ISC_CBC_CONTRAST; /**< \brief (Isc Offset: 0x3C0) Contrast and Brightness, Contrast Register */\r
+ __IO uint32_t ISC_SUB422_CTRL; /**< \brief (Isc Offset: 0x3C4) Subsampling 4:4:4 to 4:2:2 Control Register */\r
+ __IO uint32_t ISC_SUB422_CFG; /**< \brief (Isc Offset: 0x3C8) Subsampling 4:4:4 to 4:2:2 Configuration Register */\r
+ __IO uint32_t ISC_SUB420_CTRL; /**< \brief (Isc Offset: 0x3CC) Subsampling 4:2:2 to 4:2:0 Control Register */\r
+ __IO uint32_t ISC_RLP_CFG; /**< \brief (Isc Offset: 0x3D0) Rounding, Limiting and Packing Config Register */\r
+ __IO uint32_t ISC_HIS_CTRL; /**< \brief (Isc Offset: 0x3D4) Histogram Control Register */\r
+ __IO uint32_t ISC_HIS_CFG; /**< \brief (Isc Offset: 0x3D8) Histogram Configuration Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t ISC_DCFG; /**< \brief (Isc Offset: 0x3E0) DMA Configuration Register */\r
+ __IO uint32_t ISC_DCTRL; /**< \brief (Isc Offset: 0x3E4) DMA Control Register */\r
+ __IO uint32_t ISC_DNDA; /**< \brief (Isc Offset: 0x3E8) DMA Descriptor Address Register */\r
+ IscSub0 ISC_SUB0[ISCSUB0_NUMBER]; /**< \brief (Isc Offset: 0x3EC) 0 .. 2 */\r
+ __I uint32_t Reserved3[2];\r
+ __I uint32_t IPB_VERSION; /**< \brief (Isc Offset: 0x40C) Version Register */\r
+ __I uint32_t ISC_HIS_ENTRY[512]; /**< \brief (Isc Offset: 0x410) Histogram Entry */\r
+} Isc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ISC_CTRLEN : (ISC Offset: 0x00) Control Enable Register -------- */\r
+#define ISC_CTRLEN_CAPTURE (0x1u << 0) /**< \brief (ISC_CTRLEN) Capture Input Stream Command */\r
+#define ISC_CTRLEN_UPPRO (0x1u << 1) /**< \brief (ISC_CTRLEN) Update Profile */\r
+#define ISC_CTRLEN_HISREQ (0x1u << 2) /**< \brief (ISC_CTRLEN) Histogram Request */\r
+#define ISC_CTRLEN_HISCLR (0x1u << 3) /**< \brief (ISC_CTRLEN) Histogram Clear */\r
+/* -------- ISC_CTRLDIS : (ISC Offset: 0x04) Control Disable Register -------- */\r
+#define ISC_CTRLDIS_DISABLE (0x1u << 0) /**< \brief (ISC_CTRLDIS) Capture Disable */\r
+#define ISC_CTRLDIS_SWRST (0x1u << 8) /**< \brief (ISC_CTRLDIS) Software Reset */\r
+/* -------- ISC_CTRLSR : (ISC Offset: 0x08) Control Status Register -------- */\r
+#define ISC_CTRLSR_CAPTURE (0x1u << 0) /**< \brief (ISC_CTRLSR) Capture pending */\r
+#define ISC_CTRLSR_UPPRO (0x1u << 1) /**< \brief (ISC_CTRLSR) Profile Update Pending */\r
+#define ISC_CTRLSR_HISREQ (0x1u << 2) /**< \brief (ISC_CTRLSR) Histogram Request Pending */\r
+#define ISC_CTRLSR_FIELD (0x1u << 4) /**< \brief (ISC_CTRLSR) Field Status (only relevant when the video stream is interlaced) */\r
+#define ISC_CTRLSR_SIP (0x1u << 31) /**< \brief (ISC_CTRLSR) Synchronization In Progress */\r
+/* -------- ISC_PFE_CFG0 : (ISC Offset: 0x0C) Parallel Front End Configuration 0 Register -------- */\r
+#define ISC_PFE_CFG0_HPOL (0x1u << 0) /**< \brief (ISC_PFE_CFG0) Horizontal Synchronization Polarity */\r
+#define ISC_PFE_CFG0_VPOL (0x1u << 1) /**< \brief (ISC_PFE_CFG0) Vertical Synchronization Polarity */\r
+#define ISC_PFE_CFG0_PPOL (0x1u << 2) /**< \brief (ISC_PFE_CFG0) Pixel Clock Polarity */\r
+#define ISC_PFE_CFG0_FPOL (0x1u << 3) /**< \brief (ISC_PFE_CFG0) Field Polarity */\r
+#define ISC_PFE_CFG0_MODE_Pos 4\r
+#define ISC_PFE_CFG0_MODE_Msk (0x7u << ISC_PFE_CFG0_MODE_Pos) /**< \brief (ISC_PFE_CFG0) Parallel Front End Mode */\r
+#define ISC_PFE_CFG0_MODE(value) ((ISC_PFE_CFG0_MODE_Msk & ((value) << ISC_PFE_CFG0_MODE_Pos)))\r
+#define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0u << 4) /**< \brief (ISC_PFE_CFG0) Video source is progressive. */\r
+#define ISC_PFE_CFG0_MODE_DF_TOP (0x1u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, two fields are captured starting with top field. */\r
+#define ISC_PFE_CFG0_MODE_DF_BOTTOM (0x2u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, two fields are captured starting with bottom field. */\r
+#define ISC_PFE_CFG0_MODE_DF_IMMEDIATE (0x3u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, two fields are captured immediately. */\r
+#define ISC_PFE_CFG0_MODE_SF_TOP (0x4u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, one field is captured starting with the top field. */\r
+#define ISC_PFE_CFG0_MODE_SF_BOTTOM (0x5u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, one field is captured starting with the bottom field. */\r
+#define ISC_PFE_CFG0_MODE_SF_IMMEDIATE (0x6u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, one field is captured starting immediately. */\r
+#define ISC_PFE_CFG0_CONT (0x1u << 7) /**< \brief (ISC_PFE_CFG0) Continuous Acquisition */\r
+#define ISC_PFE_CFG0_GATED (0x1u << 8) /**< \brief (ISC_PFE_CFG0) Gated input clock */\r
+#define ISC_PFE_CFG0_CCIR656 (0x1u << 9) /**< \brief (ISC_PFE_CFG0) CCIR656 input mode */\r
+#define ISC_PFE_CFG0_CCIR_CRC (0x1u << 10) /**< \brief (ISC_PFE_CFG0) CCIR656 CRC Decoder */\r
+#define ISC_PFE_CFG0_CCIR10_8N (0x1u << 11) /**< \brief (ISC_PFE_CFG0) CCIR 10 bits or 8 bits */\r
+#define ISC_PFE_CFG0_COLEN (0x1u << 12) /**< \brief (ISC_PFE_CFG0) Column Cropping Enable */\r
+#define ISC_PFE_CFG0_ROWEN (0x1u << 13) /**< \brief (ISC_PFE_CFG0) Row Cropping Enable */\r
+#define ISC_PFE_CFG0_SKIPCNT_Pos 16\r
+#define ISC_PFE_CFG0_SKIPCNT_Msk (0xffu << ISC_PFE_CFG0_SKIPCNT_Pos) /**< \brief (ISC_PFE_CFG0) Frame Skipping Counter */\r
+#define ISC_PFE_CFG0_SKIPCNT(value) ((ISC_PFE_CFG0_SKIPCNT_Msk & ((value) << ISC_PFE_CFG0_SKIPCNT_Pos)))\r
+#define ISC_PFE_CFG0_CCIR_REP (0x1u << 27) /**< \brief (ISC_PFE_CFG0) CCIR Replication */\r
+#define ISC_PFE_CFG0_BPS_Pos 28\r
+#define ISC_PFE_CFG0_BPS_Msk (0x7u << ISC_PFE_CFG0_BPS_Pos) /**< \brief (ISC_PFE_CFG0) Bits Per Sample */\r
+#define ISC_PFE_CFG0_BPS(value) ((ISC_PFE_CFG0_BPS_Msk & ((value) << ISC_PFE_CFG0_BPS_Pos)))\r
+#define ISC_PFE_CFG0_BPS_TWELVE (0x0u << 28) /**< \brief (ISC_PFE_CFG0) 12-bit input */\r
+#define ISC_PFE_CFG0_BPS_ELEVEN (0x1u << 28) /**< \brief (ISC_PFE_CFG0) 11-bit input */\r
+#define ISC_PFE_CFG0_BPS_TEN (0x2u << 28) /**< \brief (ISC_PFE_CFG0) 10-bit input */\r
+#define ISC_PFE_CFG0_BPS_NINE (0x3u << 28) /**< \brief (ISC_PFE_CFG0) 9-bit input */\r
+#define ISC_PFE_CFG0_BPS_EIGHT (0x4u << 28) /**< \brief (ISC_PFE_CFG0) 8-bit input */\r
+#define ISC_PFE_CFG0_REP (0x1u << 31) /**< \brief (ISC_PFE_CFG0) Up Multiply with Replication */\r
+/* -------- ISC_PFE_CFG1 : (ISC Offset: 0x10) Parallel Front End Configuration 1 Register -------- */\r
+#define ISC_PFE_CFG1_COLMIN_Pos 0\r
+#define ISC_PFE_CFG1_COLMIN_Msk (0xffffu << ISC_PFE_CFG1_COLMIN_Pos) /**< \brief (ISC_PFE_CFG1) Column Minimum Limit */\r
+#define ISC_PFE_CFG1_COLMIN(value) ((ISC_PFE_CFG1_COLMIN_Msk & ((value) << ISC_PFE_CFG1_COLMIN_Pos)))\r
+#define ISC_PFE_CFG1_COLMAX_Pos 16\r
+#define ISC_PFE_CFG1_COLMAX_Msk (0xffffu << ISC_PFE_CFG1_COLMAX_Pos) /**< \brief (ISC_PFE_CFG1) Column Maximum Limit */\r
+#define ISC_PFE_CFG1_COLMAX(value) ((ISC_PFE_CFG1_COLMAX_Msk & ((value) << ISC_PFE_CFG1_COLMAX_Pos)))\r
+/* -------- ISC_PFE_CFG2 : (ISC Offset: 0x14) Parallel Front End Configuration 2 Register -------- */\r
+#define ISC_PFE_CFG2_ROWMIN_Pos 0\r
+#define ISC_PFE_CFG2_ROWMIN_Msk (0xffffu << ISC_PFE_CFG2_ROWMIN_Pos) /**< \brief (ISC_PFE_CFG2) Row Minimum Limit */\r
+#define ISC_PFE_CFG2_ROWMIN(value) ((ISC_PFE_CFG2_ROWMIN_Msk & ((value) << ISC_PFE_CFG2_ROWMIN_Pos)))\r
+#define ISC_PFE_CFG2_ROWMAX_Pos 16\r
+#define ISC_PFE_CFG2_ROWMAX_Msk (0xffffu << ISC_PFE_CFG2_ROWMAX_Pos) /**< \brief (ISC_PFE_CFG2) Row Maximum Limit */\r
+#define ISC_PFE_CFG2_ROWMAX(value) ((ISC_PFE_CFG2_ROWMAX_Msk & ((value) << ISC_PFE_CFG2_ROWMAX_Pos)))\r
+/* -------- ISC_CLKEN : (ISC Offset: 0x18) Clock Enable Register -------- */\r
+#define ISC_CLKEN_ICEN (0x1u << 0) /**< \brief (ISC_CLKEN) ISP Clock Enable */\r
+#define ISC_CLKEN_MCEN (0x1u << 1) /**< \brief (ISC_CLKEN) Master Clock Enable */\r
+/* -------- ISC_CLKDIS : (ISC Offset: 0x1C) Clock Disable Register -------- */\r
+#define ISC_CLKDIS_ICDIS (0x1u << 0) /**< \brief (ISC_CLKDIS) ISP Clock Disable */\r
+#define ISC_CLKDIS_MCDIS (0x1u << 1) /**< \brief (ISC_CLKDIS) Master Clock Disable */\r
+#define ISC_CLKDIS_ICSWRST (0x1u << 8) /**< \brief (ISC_CLKDIS) ISP Clock Software Reset */\r
+#define ISC_CLKDIS_MCSWRST (0x1u << 9) /**< \brief (ISC_CLKDIS) Master Clock Software Reset */\r
+/* -------- ISC_CLKSR : (ISC Offset: 0x20) Clock Status Register -------- */\r
+#define ISC_CLKSR_ICSR (0x1u << 0) /**< \brief (ISC_CLKSR) ISP Clock Status Register */\r
+#define ISC_CLKSR_MCSR (0x1u << 1) /**< \brief (ISC_CLKSR) Master Clock Status Register */\r
+#define ISC_CLKSR_SIP (0x1u << 31) /**< \brief (ISC_CLKSR) Synchronization In Progress */\r
+/* -------- ISC_CLKCFG : (ISC Offset: 0x24) Clock Configuration Register -------- */\r
+#define ISC_CLKCFG_ICDIV_Pos 0\r
+#define ISC_CLKCFG_ICDIV_Msk (0xffu << ISC_CLKCFG_ICDIV_Pos) /**< \brief (ISC_CLKCFG) ISP Clock Divider */\r
+#define ISC_CLKCFG_ICDIV(value) ((ISC_CLKCFG_ICDIV_Msk & ((value) << ISC_CLKCFG_ICDIV_Pos)))\r
+#define ISC_CLKCFG_ICSEL (0x1u << 8) /**< \brief (ISC_CLKCFG) ISP Clock Selection */\r
+#define ISC_CLKCFG_MCDIV_Pos 16\r
+#define ISC_CLKCFG_MCDIV_Msk (0xffu << ISC_CLKCFG_MCDIV_Pos) /**< \brief (ISC_CLKCFG) Master Clock Divider */\r
+#define ISC_CLKCFG_MCDIV(value) ((ISC_CLKCFG_MCDIV_Msk & ((value) << ISC_CLKCFG_MCDIV_Pos)))\r
+#define ISC_CLKCFG_MCSEL_Pos 24\r
+#define ISC_CLKCFG_MCSEL_Msk (0x3u << ISC_CLKCFG_MCSEL_Pos) /**< \brief (ISC_CLKCFG) Master Clock Reference Clock Selection */\r
+#define ISC_CLKCFG_MCSEL(value) ((ISC_CLKCFG_MCSEL_Msk & ((value) << ISC_CLKCFG_MCSEL_Pos)))\r
+/* -------- ISC_INTEN : (ISC Offset: 0x28) Interrupt Enable Register -------- */\r
+#define ISC_INTEN_VD (0x1u << 0) /**< \brief (ISC_INTEN) Vertical Synchronization Detection Interrupt Enable */\r
+#define ISC_INTEN_HD (0x1u << 1) /**< \brief (ISC_INTEN) Horizontal Synchronization Detection Interrupt Enable */\r
+#define ISC_INTEN_SWRST (0x1u << 4) /**< \brief (ISC_INTEN) Software Reset Completed Interrupt Enable */\r
+#define ISC_INTEN_DIS (0x1u << 5) /**< \brief (ISC_INTEN) Disable Completed Interrupt Enable */\r
+#define ISC_INTEN_DDONE (0x1u << 8) /**< \brief (ISC_INTEN) DMA Done Interrupt Enable */\r
+#define ISC_INTEN_LDONE (0x1u << 9) /**< \brief (ISC_INTEN) DMA List Done Interrupt Enable */\r
+#define ISC_INTEN_HISDONE (0x1u << 12) /**< \brief (ISC_INTEN) Histogram Completed Interrupt Enable */\r
+#define ISC_INTEN_HISCLR (0x1u << 13) /**< \brief (ISC_INTEN) Histogram Clear Interrupt Enable */\r
+#define ISC_INTEN_WERR (0x1u << 16) /**< \brief (ISC_INTEN) Write Channel Error Interrupt Enable */\r
+#define ISC_INTEN_RERR (0x1u << 20) /**< \brief (ISC_INTEN) Read Channel Error Interrupt Enable */\r
+#define ISC_INTEN_VFPOV (0x1u << 24) /**< \brief (ISC_INTEN) Vertical Front Porch Overflow Interrupt Enable */\r
+#define ISC_INTEN_DAOV (0x1u << 25) /**< \brief (ISC_INTEN) Data Overflow Interrupt Enable */\r
+#define ISC_INTEN_VDTO (0x1u << 26) /**< \brief (ISC_INTEN) Vertical Synchronization Timeout Interrupt Enable */\r
+#define ISC_INTEN_HDTO (0x1u << 27) /**< \brief (ISC_INTEN) Horizontal Synchronization Timeout Interrupt Enable */\r
+#define ISC_INTEN_CCIRERR (0x1u << 28) /**< \brief (ISC_INTEN) CCIR Decoder Error Interrupt Enable */\r
+/* -------- ISC_INTDIS : (ISC Offset: 0x2C) Interrupt Disable Register -------- */\r
+#define ISC_INTDIS_VD (0x1u << 0) /**< \brief (ISC_INTDIS) Vertical Synchronization Detection Interrupt Disable */\r
+#define ISC_INTDIS_HD (0x1u << 1) /**< \brief (ISC_INTDIS) Horizontal Synchronization Detection Interrupt Disable */\r
+#define ISC_INTDIS_SWRST (0x1u << 4) /**< \brief (ISC_INTDIS) Software Reset Completed Interrupt Disable */\r
+#define ISC_INTDIS_DIS (0x1u << 5) /**< \brief (ISC_INTDIS) Disable Completed Interrupt Disable */\r
+#define ISC_INTDIS_DDONE (0x1u << 8) /**< \brief (ISC_INTDIS) DMA Done Interrupt Disable */\r
+#define ISC_INTDIS_LDONE (0x1u << 9) /**< \brief (ISC_INTDIS) DMA List Done Interrupt Disable */\r
+#define ISC_INTDIS_HISDONE (0x1u << 12) /**< \brief (ISC_INTDIS) Histogram Completed Interrupt Disable */\r
+#define ISC_INTDIS_HISCLR (0x1u << 13) /**< \brief (ISC_INTDIS) Histogram Clear Interrupt Disable */\r
+#define ISC_INTDIS_WERR (0x1u << 16) /**< \brief (ISC_INTDIS) Write Channel Error Interrupt Disable */\r
+#define ISC_INTDIS_RERR (0x1u << 20) /**< \brief (ISC_INTDIS) Read Channel Error Interrupt Disable */\r
+#define ISC_INTDIS_VFPOV (0x1u << 24) /**< \brief (ISC_INTDIS) Vertical Front Porch Overflow Interrupt Disable */\r
+#define ISC_INTDIS_DAOV (0x1u << 25) /**< \brief (ISC_INTDIS) Data Overflow Interrupt Disable */\r
+#define ISC_INTDIS_VDTO (0x1u << 26) /**< \brief (ISC_INTDIS) Vertical Synchronization Timeout Interrupt Disable */\r
+#define ISC_INTDIS_HDTO (0x1u << 27) /**< \brief (ISC_INTDIS) Horizontal Synchronization Timeout Interrupt Disable */\r
+#define ISC_INTDIS_CCIRERR (0x1u << 28) /**< \brief (ISC_INTDIS) CCIR Decoder Error Interrupt Disable */\r
+/* -------- ISC_INTMASK : (ISC Offset: 0x30) Interrupt Mask Register -------- */\r
+#define ISC_INTMASK_VD (0x1u << 0) /**< \brief (ISC_INTMASK) Vertical Synchronization Detection Interrupt Mask */\r
+#define ISC_INTMASK_HD (0x1u << 1) /**< \brief (ISC_INTMASK) Horizontal Synchronization Detection Interrupt Mask */\r
+#define ISC_INTMASK_SWRST (0x1u << 4) /**< \brief (ISC_INTMASK) Software Reset Completed Interrupt Mask */\r
+#define ISC_INTMASK_DIS (0x1u << 5) /**< \brief (ISC_INTMASK) Disable Completed Interrupt Mask */\r
+#define ISC_INTMASK_DDONE (0x1u << 8) /**< \brief (ISC_INTMASK) DMA Done Interrupt Mask */\r
+#define ISC_INTMASK_LDONE (0x1u << 9) /**< \brief (ISC_INTMASK) DMA List Done Interrupt Mask */\r
+#define ISC_INTMASK_HISDONE (0x1u << 12) /**< \brief (ISC_INTMASK) Histogram Completed Interrupt Mask */\r
+#define ISC_INTMASK_HISCLR (0x1u << 13) /**< \brief (ISC_INTMASK) Histogram Clear Interrupt Mask */\r
+#define ISC_INTMASK_WERR (0x1u << 16) /**< \brief (ISC_INTMASK) Write Channel Error Interrupt Mask */\r
+#define ISC_INTMASK_RERR (0x1u << 20) /**< \brief (ISC_INTMASK) Read Channel Error Interrupt Mask */\r
+#define ISC_INTMASK_VFPOV (0x1u << 24) /**< \brief (ISC_INTMASK) Vertical Front Porch Overflow Interrupt Mask */\r
+#define ISC_INTMASK_DAOV (0x1u << 25) /**< \brief (ISC_INTMASK) Data Overflow Interrupt Mask */\r
+#define ISC_INTMASK_VDTO (0x1u << 26) /**< \brief (ISC_INTMASK) Vertical Synchronization Timeout Interrupt Mask */\r
+#define ISC_INTMASK_HDTO (0x1u << 27) /**< \brief (ISC_INTMASK) Horizontal Synchronization Timeout Interrupt Mask */\r
+#define ISC_INTMASK_CCIRERR (0x1u << 28) /**< \brief (ISC_INTMASK) CCIR Decoder Error Interrupt Mask */\r
+/* -------- ISC_INTSR : (ISC Offset: 0x34) Interrupt Status Register -------- */\r
+#define ISC_INTSR_VD (0x1u << 0) /**< \brief (ISC_INTSR) Vertical Synchronization Detected Interrupt */\r
+#define ISC_INTSR_HD (0x1u << 1) /**< \brief (ISC_INTSR) Horizontal Synchronization Detected Interrupt */\r
+#define ISC_INTSR_SWRST (0x1u << 4) /**< \brief (ISC_INTSR) Software Reset Completed Interrupt */\r
+#define ISC_INTSR_DIS (0x1u << 5) /**< \brief (ISC_INTSR) Disable Completed Interrupt */\r
+#define ISC_INTSR_DDONE (0x1u << 8) /**< \brief (ISC_INTSR) DMA Done Interrupt */\r
+#define ISC_INTSR_LDONE (0x1u << 9) /**< \brief (ISC_INTSR) DMA List Done Interrupt */\r
+#define ISC_INTSR_HISDONE (0x1u << 12) /**< \brief (ISC_INTSR) Histogram Completed Interrupt */\r
+#define ISC_INTSR_HISCLR (0x1u << 13) /**< \brief (ISC_INTSR) Histogram Clear Interrupt */\r
+#define ISC_INTSR_WERR (0x1u << 16) /**< \brief (ISC_INTSR) Write Channel Error Interrupt */\r
+#define ISC_INTSR_WERRID_Pos 17\r
+#define ISC_INTSR_WERRID_Msk (0x3u << ISC_INTSR_WERRID_Pos) /**< \brief (ISC_INTSR) Write Channel Error Identifier */\r
+#define ISC_INTSR_WERRID_CH0 (0x0u << 17) /**< \brief (ISC_INTSR) An error occurred for Channel 0 (RAW/RGB/Y) */\r
+#define ISC_INTSR_WERRID_CH1 (0x1u << 17) /**< \brief (ISC_INTSR) An error occurred for Channel 1 (CbCr/Cb) */\r
+#define ISC_INTSR_WERRID_CH2 (0x2u << 17) /**< \brief (ISC_INTSR) An error occurred for Channel 2 (Cr) */\r
+#define ISC_INTSR_WERRID_WB (0x3u << 17) /**< \brief (ISC_INTSR) Write back channel error */\r
+#define ISC_INTSR_RERR (0x1u << 20) /**< \brief (ISC_INTSR) Read Channel Error Interrupt */\r
+#define ISC_INTSR_VFPOV (0x1u << 24) /**< \brief (ISC_INTSR) Vertical Front Porch Overflow Interrupt */\r
+#define ISC_INTSR_DAOV (0x1u << 25) /**< \brief (ISC_INTSR) Data Overflow Interrupt */\r
+#define ISC_INTSR_VDTO (0x1u << 26) /**< \brief (ISC_INTSR) Vertical Synchronization Timeout Interrupt */\r
+#define ISC_INTSR_HDTO (0x1u << 27) /**< \brief (ISC_INTSR) Horizontal Synchronization Timeout Interrupt */\r
+#define ISC_INTSR_CCIRERR (0x1u << 28) /**< \brief (ISC_INTSR) CCIR Decoder Error Interrupt */\r
+/* -------- ISC_WB_CTRL : (ISC Offset: 0x58) White Balance Control Register -------- */\r
+#define ISC_WB_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_WB_CTRL) White Balance Enable */\r
+/* -------- ISC_WB_CFG : (ISC Offset: 0x5C) White Balance Configuration Register -------- */\r
+#define ISC_WB_CFG_BAYCFG_Pos 0\r
+#define ISC_WB_CFG_BAYCFG_Msk (0x3u << ISC_WB_CFG_BAYCFG_Pos) /**< \brief (ISC_WB_CFG) White Balance Bayer Configuration (Pixel Color Pattern) */\r
+#define ISC_WB_CFG_BAYCFG(value) ((ISC_WB_CFG_BAYCFG_Msk & ((value) << ISC_WB_CFG_BAYCFG_Pos)))\r
+#define ISC_WB_CFG_BAYCFG_GRGR (0x0u << 0) /**< \brief (ISC_WB_CFG) Starting Row configuration is G R G R (Red Row) */\r
+#define ISC_WB_CFG_BAYCFG_RGRG (0x1u << 0) /**< \brief (ISC_WB_CFG) Starting Row configuration is R G R G (Red Row */\r
+#define ISC_WB_CFG_BAYCFG_GBGB (0x2u << 0) /**< \brief (ISC_WB_CFG) Starting Row configuration is G B G B (Blue Row */\r
+#define ISC_WB_CFG_BAYCFG_BGBG (0x3u << 0) /**< \brief (ISC_WB_CFG) Starting Row configuration is B G B G (Blue Row) */\r
+/* -------- ISC_WB_O_RGR : (ISC Offset: 0x60) White Balance Offset for R, GR Register -------- */\r
+#define ISC_WB_O_RGR_ROFST_Pos 0\r
+#define ISC_WB_O_RGR_ROFST_Msk (0x1fffu << ISC_WB_O_RGR_ROFST_Pos) /**< \brief (ISC_WB_O_RGR) Offset Red Component (signed 13 bits 1:12:0) */\r
+#define ISC_WB_O_RGR_ROFST(value) ((ISC_WB_O_RGR_ROFST_Msk & ((value) << ISC_WB_O_RGR_ROFST_Pos)))\r
+#define ISC_WB_O_RGR_GROFST_Pos 16\r
+#define ISC_WB_O_RGR_GROFST_Msk (0x1fffu << ISC_WB_O_RGR_GROFST_Pos) /**< \brief (ISC_WB_O_RGR) Offset Green Component for Red Row (signed 13 bits 1:12:0) */\r
+#define ISC_WB_O_RGR_GROFST(value) ((ISC_WB_O_RGR_GROFST_Msk & ((value) << ISC_WB_O_RGR_GROFST_Pos)))\r
+/* -------- ISC_WB_O_BGB : (ISC Offset: 0x64) White Balance Offset for B, GB Register -------- */\r
+#define ISC_WB_O_BGB_BOFST_Pos 0\r
+#define ISC_WB_O_BGB_BOFST_Msk (0x1fffu << ISC_WB_O_BGB_BOFST_Pos) /**< \brief (ISC_WB_O_BGB) Offset Blue Component (signed 13 bits, 1:12:0) */\r
+#define ISC_WB_O_BGB_BOFST(value) ((ISC_WB_O_BGB_BOFST_Msk & ((value) << ISC_WB_O_BGB_BOFST_Pos)))\r
+#define ISC_WB_O_BGB_GBOFST_Pos 16\r
+#define ISC_WB_O_BGB_GBOFST_Msk (0x1fffu << ISC_WB_O_BGB_GBOFST_Pos) /**< \brief (ISC_WB_O_BGB) Offset Green Component for Blue Row (signed 13 bits, 1:12:0) */\r
+#define ISC_WB_O_BGB_GBOFST(value) ((ISC_WB_O_BGB_GBOFST_Msk & ((value) << ISC_WB_O_BGB_GBOFST_Pos)))\r
+/* -------- ISC_WB_G_RGR : (ISC Offset: 0x68) White Balance Gain for R, GR Register -------- */\r
+#define ISC_WB_G_RGR_RGAIN_Pos 0\r
+#define ISC_WB_G_RGR_RGAIN_Msk (0x1fffu << ISC_WB_G_RGR_RGAIN_Pos) /**< \brief (ISC_WB_G_RGR) Red Component Gain (unsigned 13 bits, 0:4:9) */\r
+#define ISC_WB_G_RGR_RGAIN(value) ((ISC_WB_G_RGR_RGAIN_Msk & ((value) << ISC_WB_G_RGR_RGAIN_Pos)))\r
+#define ISC_WB_G_RGR_GRGAIN_Pos 16\r
+#define ISC_WB_G_RGR_GRGAIN_Msk (0x1fffu << ISC_WB_G_RGR_GRGAIN_Pos) /**< \brief (ISC_WB_G_RGR) Green Component (Red row) Gain (unsigned 13 bits, 0:4:9) */\r
+#define ISC_WB_G_RGR_GRGAIN(value) ((ISC_WB_G_RGR_GRGAIN_Msk & ((value) << ISC_WB_G_RGR_GRGAIN_Pos)))\r
+/* -------- ISC_WB_G_BGB : (ISC Offset: 0x6C) White Balance Gain for B, GB Register -------- */\r
+#define ISC_WB_G_BGB_BGAIN_Pos 0\r
+#define ISC_WB_G_BGB_BGAIN_Msk (0x1fffu << ISC_WB_G_BGB_BGAIN_Pos) /**< \brief (ISC_WB_G_BGB) Blue Component Gain (unsigned 13 bits, 0:4:9) */\r
+#define ISC_WB_G_BGB_BGAIN(value) ((ISC_WB_G_BGB_BGAIN_Msk & ((value) << ISC_WB_G_BGB_BGAIN_Pos)))\r
+#define ISC_WB_G_BGB_GBGAIN_Pos 16\r
+#define ISC_WB_G_BGB_GBGAIN_Msk (0x1fffu << ISC_WB_G_BGB_GBGAIN_Pos) /**< \brief (ISC_WB_G_BGB) Green Component (Blue row) Gain (unsigned 13 bits, 0:4:9) */\r
+#define ISC_WB_G_BGB_GBGAIN(value) ((ISC_WB_G_BGB_GBGAIN_Msk & ((value) << ISC_WB_G_BGB_GBGAIN_Pos)))\r
+/* -------- ISC_CFA_CTRL : (ISC Offset: 0x70) Color Filter Array Control Register -------- */\r
+#define ISC_CFA_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_CFA_CTRL) Color Filter Array Interpolation Enable */\r
+/* -------- ISC_CFA_CFG : (ISC Offset: 0x74) Color Filter Array Configuration Register -------- */\r
+#define ISC_CFA_CFG_BAYCFG_Pos 0\r
+#define ISC_CFA_CFG_BAYCFG_Msk (0x3u << ISC_CFA_CFG_BAYCFG_Pos) /**< \brief (ISC_CFA_CFG) Color Filter Array Pattern */\r
+#define ISC_CFA_CFG_BAYCFG(value) ((ISC_CFA_CFG_BAYCFG_Msk & ((value) << ISC_CFA_CFG_BAYCFG_Pos)))\r
+#define ISC_CFA_CFG_BAYCFG_GRGR (0x0u << 0) /**< \brief (ISC_CFA_CFG) Starting row configuration is G R G R (red row) */\r
+#define ISC_CFA_CFG_BAYCFG_RGRG (0x1u << 0) /**< \brief (ISC_CFA_CFG) Starting row configuration is R G R G (red row */\r
+#define ISC_CFA_CFG_BAYCFG_GBGB (0x2u << 0) /**< \brief (ISC_CFA_CFG) Starting row configuration is G B G B (blue row */\r
+#define ISC_CFA_CFG_BAYCFG_BGBG (0x3u << 0) /**< \brief (ISC_CFA_CFG) Starting row configuration is B G B G (blue row) */\r
+#define ISC_CFA_CFG_EITPOL (0x1u << 4) /**< \brief (ISC_CFA_CFG) Edge Interpolation */\r
+/* -------- ISC_CC_CTRL : (ISC Offset: 0x78) Color Correction Control Register -------- */\r
+#define ISC_CC_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_CC_CTRL) Color Correction Enable */\r
+/* -------- ISC_CC_RR_RG : (ISC Offset: 0x7C) Color Correction RR RG Register -------- */\r
+#define ISC_CC_RR_RG_RRGAIN_Pos 0\r
+#define ISC_CC_RR_RG_RRGAIN_Msk (0xfffu << ISC_CC_RR_RG_RRGAIN_Pos) /**< \brief (ISC_CC_RR_RG) Red Gain for Red Component (signed 12 bits, 1:3:8) */\r
+#define ISC_CC_RR_RG_RRGAIN(value) ((ISC_CC_RR_RG_RRGAIN_Msk & ((value) << ISC_CC_RR_RG_RRGAIN_Pos)))\r
+#define ISC_CC_RR_RG_RGGAIN_Pos 16\r
+#define ISC_CC_RR_RG_RGGAIN_Msk (0xfffu << ISC_CC_RR_RG_RGGAIN_Pos) /**< \brief (ISC_CC_RR_RG) Green Gain for Red Component (signed 12 bits, 1:3:8) */\r
+#define ISC_CC_RR_RG_RGGAIN(value) ((ISC_CC_RR_RG_RGGAIN_Msk & ((value) << ISC_CC_RR_RG_RGGAIN_Pos)))\r
+/* -------- ISC_CC_RB_OR : (ISC Offset: 0x80) Color Correction RB OR Register -------- */\r
+#define ISC_CC_RB_OR_RBGAIN_Pos 0\r
+#define ISC_CC_RB_OR_RBGAIN_Msk (0xfffu << ISC_CC_RB_OR_RBGAIN_Pos) /**< \brief (ISC_CC_RB_OR) Blue Gain for Red Component (signed 12 bits, 1:3:8) */\r
+#define ISC_CC_RB_OR_RBGAIN(value) ((ISC_CC_RB_OR_RBGAIN_Msk & ((value) << ISC_CC_RB_OR_RBGAIN_Pos)))\r
+#define ISC_CC_RB_OR_ROFST_Pos 16\r
+#define ISC_CC_RB_OR_ROFST_Msk (0x1fffu << ISC_CC_RB_OR_ROFST_Pos) /**< \brief (ISC_CC_RB_OR) Red Component Offset (signed 13 bits, 1:12:0) */\r
+#define ISC_CC_RB_OR_ROFST(value) ((ISC_CC_RB_OR_ROFST_Msk & ((value) << ISC_CC_RB_OR_ROFST_Pos)))\r
+/* -------- ISC_CC_GR_GG : (ISC Offset: 0x84) Color Correction GR GG Register -------- */\r
+#define ISC_CC_GR_GG_GRGAIN_Pos 0\r
+#define ISC_CC_GR_GG_GRGAIN_Msk (0xfffu << ISC_CC_GR_GG_GRGAIN_Pos) /**< \brief (ISC_CC_GR_GG) Red Gain for Green Component (signed 12 bits, 1:3:8) */\r
+#define ISC_CC_GR_GG_GRGAIN(value) ((ISC_CC_GR_GG_GRGAIN_Msk & ((value) << ISC_CC_GR_GG_GRGAIN_Pos)))\r
+#define ISC_CC_GR_GG_GGGAIN_Pos 16\r
+#define ISC_CC_GR_GG_GGGAIN_Msk (0xfffu << ISC_CC_GR_GG_GGGAIN_Pos) /**< \brief (ISC_CC_GR_GG) Green Gain for Green Component (signed 12 bits, 1:3:8) */\r
+#define ISC_CC_GR_GG_GGGAIN(value) ((ISC_CC_GR_GG_GGGAIN_Msk & ((value) << ISC_CC_GR_GG_GGGAIN_Pos)))\r
+/* -------- ISC_CC_GB_OG : (ISC Offset: 0x88) Color Correction GB OG Register -------- */\r
+#define ISC_CC_GB_OG_GBGAIN_Pos 0\r
+#define ISC_CC_GB_OG_GBGAIN_Msk (0xfffu << ISC_CC_GB_OG_GBGAIN_Pos) /**< \brief (ISC_CC_GB_OG) Blue Gain for Green Component (signed 12 bits, 1:3:8) */\r
+#define ISC_CC_GB_OG_GBGAIN(value) ((ISC_CC_GB_OG_GBGAIN_Msk & ((value) << ISC_CC_GB_OG_GBGAIN_Pos)))\r
+#define ISC_CC_GB_OG_ROFST_Pos 16\r
+#define ISC_CC_GB_OG_ROFST_Msk (0x1fffu << ISC_CC_GB_OG_ROFST_Pos) /**< \brief (ISC_CC_GB_OG) Green Component Offset (signed 13 bits, 1:12:0) */\r
+#define ISC_CC_GB_OG_ROFST(value) ((ISC_CC_GB_OG_ROFST_Msk & ((value) << ISC_CC_GB_OG_ROFST_Pos)))\r
+/* -------- ISC_CC_BR_BG : (ISC Offset: 0x8C) Color Correction BR BG Register -------- */\r
+#define ISC_CC_BR_BG_BRGAIN_Pos 0\r
+#define ISC_CC_BR_BG_BRGAIN_Msk (0xfffu << ISC_CC_BR_BG_BRGAIN_Pos) /**< \brief (ISC_CC_BR_BG) Red Gain for Blue Component (signed 12 bits, 1:3:8) */\r
+#define ISC_CC_BR_BG_BRGAIN(value) ((ISC_CC_BR_BG_BRGAIN_Msk & ((value) << ISC_CC_BR_BG_BRGAIN_Pos)))\r
+#define ISC_CC_BR_BG_BGGAIN_Pos 16\r
+#define ISC_CC_BR_BG_BGGAIN_Msk (0xfffu << ISC_CC_BR_BG_BGGAIN_Pos) /**< \brief (ISC_CC_BR_BG) Green Gain for Blue Component (signed 12 bits, 1:3:8) */\r
+#define ISC_CC_BR_BG_BGGAIN(value) ((ISC_CC_BR_BG_BGGAIN_Msk & ((value) << ISC_CC_BR_BG_BGGAIN_Pos)))\r
+/* -------- ISC_CC_BB_OB : (ISC Offset: 0x90) Color Correction BB OB Register -------- */\r
+#define ISC_CC_BB_OB_BBGAIN_Pos 0\r
+#define ISC_CC_BB_OB_BBGAIN_Msk (0xfffu << ISC_CC_BB_OB_BBGAIN_Pos) /**< \brief (ISC_CC_BB_OB) Blue Gain for Blue Component (signed 12 bits, 1:3:8) */\r
+#define ISC_CC_BB_OB_BBGAIN(value) ((ISC_CC_BB_OB_BBGAIN_Msk & ((value) << ISC_CC_BB_OB_BBGAIN_Pos)))\r
+#define ISC_CC_BB_OB_BOFST_Pos 16\r
+#define ISC_CC_BB_OB_BOFST_Msk (0x1fffu << ISC_CC_BB_OB_BOFST_Pos) /**< \brief (ISC_CC_BB_OB) Blue Component Offset (signed 13 bits, 1:12:0) */\r
+#define ISC_CC_BB_OB_BOFST(value) ((ISC_CC_BB_OB_BOFST_Msk & ((value) << ISC_CC_BB_OB_BOFST_Pos)))\r
+/* -------- ISC_GAM_CTRL : (ISC Offset: 0x94) Gamma Correction Control Register -------- */\r
+#define ISC_GAM_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_GAM_CTRL) Gamma Correction Enable */\r
+#define ISC_GAM_CTRL_BENABLE (0x1u << 1) /**< \brief (ISC_GAM_CTRL) Gamma Correction Enable for B Channel */\r
+#define ISC_GAM_CTRL_GENABLE (0x1u << 2) /**< \brief (ISC_GAM_CTRL) Gamma Correction Enable for G Channel */\r
+#define ISC_GAM_CTRL_RENABLE (0x1u << 3) /**< \brief (ISC_GAM_CTRL) Gamma Correction Enable for R Channel */\r
+/* -------- ISC_GAM_BENTRY[64] : (ISC Offset: 0x98) Gamma Correction Blue Entry -------- */\r
+#define ISC_GAM_BENTRY_BSLOPE_Pos 0\r
+#define ISC_GAM_BENTRY_BSLOPE_Msk (0x3ffu << ISC_GAM_BENTRY_BSLOPE_Pos) /**< \brief (ISC_GAM_BENTRY[64]) Blue Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6) */\r
+#define ISC_GAM_BENTRY_BSLOPE(value) ((ISC_GAM_BENTRY_BSLOPE_Msk & ((value) << ISC_GAM_BENTRY_BSLOPE_Pos)))\r
+#define ISC_GAM_BENTRY_BCONSTANT_Pos 16\r
+#define ISC_GAM_BENTRY_BCONSTANT_Msk (0x3ffu << ISC_GAM_BENTRY_BCONSTANT_Pos) /**< \brief (ISC_GAM_BENTRY[64]) Blue Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0) */\r
+#define ISC_GAM_BENTRY_BCONSTANT(value) ((ISC_GAM_BENTRY_BCONSTANT_Msk & ((value) << ISC_GAM_BENTRY_BCONSTANT_Pos)))\r
+/* -------- ISC_GAM_GENTRY[64] : (ISC Offset: 0x198) Gamma Correction Green Entry -------- */\r
+#define ISC_GAM_GENTRY_GSLOPE_Pos 0\r
+#define ISC_GAM_GENTRY_GSLOPE_Msk (0x3ffu << ISC_GAM_GENTRY_GSLOPE_Pos) /**< \brief (ISC_GAM_GENTRY[64]) Green Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6) */\r
+#define ISC_GAM_GENTRY_GSLOPE(value) ((ISC_GAM_GENTRY_GSLOPE_Msk & ((value) << ISC_GAM_GENTRY_GSLOPE_Pos)))\r
+#define ISC_GAM_GENTRY_GCONSTANT_Pos 16\r
+#define ISC_GAM_GENTRY_GCONSTANT_Msk (0x3ffu << ISC_GAM_GENTRY_GCONSTANT_Pos) /**< \brief (ISC_GAM_GENTRY[64]) Green Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0) */\r
+#define ISC_GAM_GENTRY_GCONSTANT(value) ((ISC_GAM_GENTRY_GCONSTANT_Msk & ((value) << ISC_GAM_GENTRY_GCONSTANT_Pos)))\r
+/* -------- ISC_GAM_RENTRY[64] : (ISC Offset: 0x298) Gamma Correction Red Entry -------- */\r
+#define ISC_GAM_RENTRY_RSLOPE_Pos 0\r
+#define ISC_GAM_RENTRY_RSLOPE_Msk (0x3ffu << ISC_GAM_RENTRY_RSLOPE_Pos) /**< \brief (ISC_GAM_RENTRY[64]) Red Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6) */\r
+#define ISC_GAM_RENTRY_RSLOPE(value) ((ISC_GAM_RENTRY_RSLOPE_Msk & ((value) << ISC_GAM_RENTRY_RSLOPE_Pos)))\r
+#define ISC_GAM_RENTRY_RCONSTANT_Pos 16\r
+#define ISC_GAM_RENTRY_RCONSTANT_Msk (0x3ffu << ISC_GAM_RENTRY_RCONSTANT_Pos) /**< \brief (ISC_GAM_RENTRY[64]) Red Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0) */\r
+#define ISC_GAM_RENTRY_RCONSTANT(value) ((ISC_GAM_RENTRY_RCONSTANT_Msk & ((value) << ISC_GAM_RENTRY_RCONSTANT_Pos)))\r
+/* -------- ISC_CSC_CTRL : (ISC Offset: 0x398) Color Space Conversion Control Register -------- */\r
+#define ISC_CSC_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_CSC_CTRL) RGB to YCbCr Color Space Conversion Enable */\r
+/* -------- ISC_CSC_YR_YG : (ISC Offset: 0x39C) Color Space Conversion YR, YG Register -------- */\r
+#define ISC_CSC_YR_YG_YRGAIN_Pos 0\r
+#define ISC_CSC_YR_YG_YRGAIN_Msk (0xfffu << ISC_CSC_YR_YG_YRGAIN_Pos) /**< \brief (ISC_CSC_YR_YG) Reg Gain for Luminance (signed 12 bits 1:3:8) */\r
+#define ISC_CSC_YR_YG_YRGAIN(value) ((ISC_CSC_YR_YG_YRGAIN_Msk & ((value) << ISC_CSC_YR_YG_YRGAIN_Pos)))\r
+#define ISC_CSC_YR_YG_YGGAIN_Pos 16\r
+#define ISC_CSC_YR_YG_YGGAIN_Msk (0xfffu << ISC_CSC_YR_YG_YGGAIN_Pos) /**< \brief (ISC_CSC_YR_YG) Green Gain for Luminance (signed 12 bits 1:3:8) */\r
+#define ISC_CSC_YR_YG_YGGAIN(value) ((ISC_CSC_YR_YG_YGGAIN_Msk & ((value) << ISC_CSC_YR_YG_YGGAIN_Pos)))\r
+/* -------- ISC_CSC_YB_OY : (ISC Offset: 0x3A0) Color Space Conversion YB, OY Register -------- */\r
+#define ISC_CSC_YB_OY_YBGAIN_Pos 0\r
+#define ISC_CSC_YB_OY_YBGAIN_Msk (0xfffu << ISC_CSC_YB_OY_YBGAIN_Pos) /**< \brief (ISC_CSC_YB_OY) Blue Gain for Luminance Component (12 bits signed 1:3:8) */\r
+#define ISC_CSC_YB_OY_YBGAIN(value) ((ISC_CSC_YB_OY_YBGAIN_Msk & ((value) << ISC_CSC_YB_OY_YBGAIN_Pos)))\r
+#define ISC_CSC_YB_OY_YOFST_Pos 16\r
+#define ISC_CSC_YB_OY_YOFST_Msk (0x7ffu << ISC_CSC_YB_OY_YOFST_Pos) /**< \brief (ISC_CSC_YB_OY) Luminance Offset (11 bits signed 1:10:0) */\r
+#define ISC_CSC_YB_OY_YOFST(value) ((ISC_CSC_YB_OY_YOFST_Msk & ((value) << ISC_CSC_YB_OY_YOFST_Pos)))\r
+/* -------- ISC_CSC_CBR_CBG : (ISC Offset: 0x3A4) Color Space Conversion CBR CBG Register -------- */\r
+#define ISC_CSC_CBR_CBG_CBRGAIN_Pos 0\r
+#define ISC_CSC_CBR_CBG_CBRGAIN_Msk (0xfffu << ISC_CSC_CBR_CBG_CBRGAIN_Pos) /**< \brief (ISC_CSC_CBR_CBG) Red Gain for Blue Chrominance (signed 12 bits, 1:3:8) */\r
+#define ISC_CSC_CBR_CBG_CBRGAIN(value) ((ISC_CSC_CBR_CBG_CBRGAIN_Msk & ((value) << ISC_CSC_CBR_CBG_CBRGAIN_Pos)))\r
+#define ISC_CSC_CBR_CBG_CBGGAIN_Pos 16\r
+#define ISC_CSC_CBR_CBG_CBGGAIN_Msk (0xfffu << ISC_CSC_CBR_CBG_CBGGAIN_Pos) /**< \brief (ISC_CSC_CBR_CBG) Green Gain for Blue Chrominance (signed 12 bits 1:3:8) */\r
+#define ISC_CSC_CBR_CBG_CBGGAIN(value) ((ISC_CSC_CBR_CBG_CBGGAIN_Msk & ((value) << ISC_CSC_CBR_CBG_CBGGAIN_Pos)))\r
+/* -------- ISC_CSC_CBB_OCB : (ISC Offset: 0x3A8) Color Space Conversion CBB OCB Register -------- */\r
+#define ISC_CSC_CBB_OCB_CBBGAIN_Pos 0\r
+#define ISC_CSC_CBB_OCB_CBBGAIN_Msk (0xfffu << ISC_CSC_CBB_OCB_CBBGAIN_Pos) /**< \brief (ISC_CSC_CBB_OCB) Blue Gain for Blue Chrominance (signed 12 bits 1:3:8) */\r
+#define ISC_CSC_CBB_OCB_CBBGAIN(value) ((ISC_CSC_CBB_OCB_CBBGAIN_Msk & ((value) << ISC_CSC_CBB_OCB_CBBGAIN_Pos)))\r
+#define ISC_CSC_CBB_OCB_CBOFST_Pos 16\r
+#define ISC_CSC_CBB_OCB_CBOFST_Msk (0x7ffu << ISC_CSC_CBB_OCB_CBOFST_Pos) /**< \brief (ISC_CSC_CBB_OCB) Blue Chrominance Offset (signed 11 bits 1:10:0) */\r
+#define ISC_CSC_CBB_OCB_CBOFST(value) ((ISC_CSC_CBB_OCB_CBOFST_Msk & ((value) << ISC_CSC_CBB_OCB_CBOFST_Pos)))\r
+/* -------- ISC_CSC_CRR_CRG : (ISC Offset: 0x3AC) Color Space Conversion CRR CRG Register -------- */\r
+#define ISC_CSC_CRR_CRG_CRRGAIN_Pos 0\r
+#define ISC_CSC_CRR_CRG_CRRGAIN_Msk (0xfffu << ISC_CSC_CRR_CRG_CRRGAIN_Pos) /**< \brief (ISC_CSC_CRR_CRG) Red Gain for Red Chrominance (signed 12 bits 1:3:8) */\r
+#define ISC_CSC_CRR_CRG_CRRGAIN(value) ((ISC_CSC_CRR_CRG_CRRGAIN_Msk & ((value) << ISC_CSC_CRR_CRG_CRRGAIN_Pos)))\r
+#define ISC_CSC_CRR_CRG_CRGGAIN_Pos 16\r
+#define ISC_CSC_CRR_CRG_CRGGAIN_Msk (0xfffu << ISC_CSC_CRR_CRG_CRGGAIN_Pos) /**< \brief (ISC_CSC_CRR_CRG) Green Gain for Red Chrominance (signed 12 bits 1:3:8) */\r
+#define ISC_CSC_CRR_CRG_CRGGAIN(value) ((ISC_CSC_CRR_CRG_CRGGAIN_Msk & ((value) << ISC_CSC_CRR_CRG_CRGGAIN_Pos)))\r
+/* -------- ISC_CSC_CRB_OCR : (ISC Offset: 0x3B0) Color Space Conversion CRB OCR Register -------- */\r
+#define ISC_CSC_CRB_OCR_CRBGAIN_Pos 0\r
+#define ISC_CSC_CRB_OCR_CRBGAIN_Msk (0xfffu << ISC_CSC_CRB_OCR_CRBGAIN_Pos) /**< \brief (ISC_CSC_CRB_OCR) Blue Gain for Red Chrominance (signed 12 bits 1:3:8) */\r
+#define ISC_CSC_CRB_OCR_CRBGAIN(value) ((ISC_CSC_CRB_OCR_CRBGAIN_Msk & ((value) << ISC_CSC_CRB_OCR_CRBGAIN_Pos)))\r
+#define ISC_CSC_CRB_OCR_CROFST_Pos 16\r
+#define ISC_CSC_CRB_OCR_CROFST_Msk (0x7ffu << ISC_CSC_CRB_OCR_CROFST_Pos) /**< \brief (ISC_CSC_CRB_OCR) Red Chrominance Offset (signed 11 bits 1:10:0) */\r
+#define ISC_CSC_CRB_OCR_CROFST(value) ((ISC_CSC_CRB_OCR_CROFST_Msk & ((value) << ISC_CSC_CRB_OCR_CROFST_Pos)))\r
+/* -------- ISC_CBC_CTRL : (ISC Offset: 0x3B4) Contrast and Brightness Control Register -------- */\r
+#define ISC_CBC_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_CBC_CTRL) Contrast and Brightness Control Enable */\r
+/* -------- ISC_CBC_CFG : (ISC Offset: 0x3B8) Contrast and Brightness Configuration Register -------- */\r
+#define ISC_CBC_CFG_CCIR (0x1u << 0) /**< \brief (ISC_CBC_CFG) CCIR656 Stream Enable */\r
+#define ISC_CBC_CFG_CCIRMODE_Pos 1\r
+#define ISC_CBC_CFG_CCIRMODE_Msk (0x3u << ISC_CBC_CFG_CCIRMODE_Pos) /**< \brief (ISC_CBC_CFG) CCIR656 Byte Ordering */\r
+#define ISC_CBC_CFG_CCIRMODE(value) ((ISC_CBC_CFG_CCIRMODE_Msk & ((value) << ISC_CBC_CFG_CCIRMODE_Pos)))\r
+#define ISC_CBC_CFG_CCIRMODE_CBY (0x0u << 1) /**< \brief (ISC_CBC_CFG) Byte ordering Cb0, Y0, Cr0, Y1 */\r
+#define ISC_CBC_CFG_CCIRMODE_CRY (0x1u << 1) /**< \brief (ISC_CBC_CFG) Byte ordering Cr0, Y0, Cb0, Y1 */\r
+#define ISC_CBC_CFG_CCIRMODE_YCB (0x2u << 1) /**< \brief (ISC_CBC_CFG) Byte ordering Y0, Cb0, Y1, Cr0 */\r
+#define ISC_CBC_CFG_CCIRMODE_YCR (0x3u << 1) /**< \brief (ISC_CBC_CFG) Byte ordering Y0, Cr0, Y1, Cb0 */\r
+/* -------- ISC_CBC_BRIGHT : (ISC Offset: 0x3BC) Contrast and Brightness, Brightness Register -------- */\r
+#define ISC_CBC_BRIGHT_BRIGHT_Pos 0\r
+#define ISC_CBC_BRIGHT_BRIGHT_Msk (0x7ffu << ISC_CBC_BRIGHT_BRIGHT_Pos) /**< \brief (ISC_CBC_BRIGHT) Brightness Control (signed 11 bits 1:10:0) */\r
+#define ISC_CBC_BRIGHT_BRIGHT(value) ((ISC_CBC_BRIGHT_BRIGHT_Msk & ((value) << ISC_CBC_BRIGHT_BRIGHT_Pos)))\r
+/* -------- ISC_CBC_CONTRAST : (ISC Offset: 0x3C0) Contrast and Brightness, Contrast Register -------- */\r
+#define ISC_CBC_CONTRAST_CONTRAST_Pos 0\r
+#define ISC_CBC_CONTRAST_CONTRAST_Msk (0xfffu << ISC_CBC_CONTRAST_CONTRAST_Pos) /**< \brief (ISC_CBC_CONTRAST) Contrast (signed 12 bits 1:3:8) */\r
+#define ISC_CBC_CONTRAST_CONTRAST(value) ((ISC_CBC_CONTRAST_CONTRAST_Msk & ((value) << ISC_CBC_CONTRAST_CONTRAST_Pos)))\r
+/* -------- ISC_SUB422_CTRL : (ISC Offset: 0x3C4) Subsampling 4:4:4 to 4:2:2 Control Register -------- */\r
+#define ISC_SUB422_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_SUB422_CTRL) 4:4:4 to 4:2:2 Chrominance Horizontal Subsampling Filter Enable */\r
+/* -------- ISC_SUB422_CFG : (ISC Offset: 0x3C8) Subsampling 4:4:4 to 4:2:2 Configuration Register -------- */\r
+#define ISC_SUB422_CFG_CCIR (0x1u << 0) /**< \brief (ISC_SUB422_CFG) CCIR656 Input Stream */\r
+#define ISC_SUB422_CFG_CCIRMODE_Pos 1\r
+#define ISC_SUB422_CFG_CCIRMODE_Msk (0x3u << ISC_SUB422_CFG_CCIRMODE_Pos) /**< \brief (ISC_SUB422_CFG) CCIR656 Byte Ordering */\r
+#define ISC_SUB422_CFG_CCIRMODE(value) ((ISC_SUB422_CFG_CCIRMODE_Msk & ((value) << ISC_SUB422_CFG_CCIRMODE_Pos)))\r
+#define ISC_SUB422_CFG_CCIRMODE_CBY (0x0u << 1) /**< \brief (ISC_SUB422_CFG) Byte ordering Cb0, Y0, Cr0, Y1 */\r
+#define ISC_SUB422_CFG_CCIRMODE_CRY (0x1u << 1) /**< \brief (ISC_SUB422_CFG) Byte ordering Cr0, Y0, Cb0, Y1 */\r
+#define ISC_SUB422_CFG_CCIRMODE_YCB (0x2u << 1) /**< \brief (ISC_SUB422_CFG) Byte ordering Y0, Cb0, Y1, Cr0 */\r
+#define ISC_SUB422_CFG_CCIRMODE_YCR (0x3u << 1) /**< \brief (ISC_SUB422_CFG) Byte ordering Y0, Cr0, Y1, Cb0 */\r
+#define ISC_SUB422_CFG_FILTER_Pos 4\r
+#define ISC_SUB422_CFG_FILTER_Msk (0x3u << ISC_SUB422_CFG_FILTER_Pos) /**< \brief (ISC_SUB422_CFG) Low Pass Filter Selection */\r
+#define ISC_SUB422_CFG_FILTER(value) ((ISC_SUB422_CFG_FILTER_Msk & ((value) << ISC_SUB422_CFG_FILTER_Pos)))\r
+#define ISC_SUB422_CFG_FILTER_FILT0CO (0x0u << 4) /**< \brief (ISC_SUB422_CFG) Cosited, {1} */\r
+#define ISC_SUB422_CFG_FILTER_FILT1CE (0x1u << 4) /**< \brief (ISC_SUB422_CFG) Centered {1, 1} */\r
+#define ISC_SUB422_CFG_FILTER_FILT2CO (0x2u << 4) /**< \brief (ISC_SUB422_CFG) Cosited {1,2,1} */\r
+#define ISC_SUB422_CFG_FILTER_FILT3CE (0x3u << 4) /**< \brief (ISC_SUB422_CFG) Centered {1, 3, 3, 1} */\r
+/* -------- ISC_SUB420_CTRL : (ISC Offset: 0x3CC) Subsampling 4:2:2 to 4:2:0 Control Register -------- */\r
+#define ISC_SUB420_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_SUB420_CTRL) 4:2:2 to 4:2:0 Vertical Subsampling Filter Enable (Center Aligned) */\r
+#define ISC_SUB420_CTRL_FILTER (0x1u << 4) /**< \brief (ISC_SUB420_CTRL) Interlaced or Progressive Chrominance Filter */\r
+/* -------- ISC_RLP_CFG : (ISC Offset: 0x3D0) Rounding, Limiting and Packing Config Register -------- */\r
+#define ISC_RLP_CFG_MODE_Pos 0\r
+#define ISC_RLP_CFG_MODE_Msk (0xfu << ISC_RLP_CFG_MODE_Pos) /**< \brief (ISC_RLP_CFG) Rounding, Limiting and Packing Mode */\r
+#define ISC_RLP_CFG_MODE(value) ((ISC_RLP_CFG_MODE_Msk & ((value) << ISC_RLP_CFG_MODE_Pos)))\r
+#define ISC_RLP_CFG_MODE_DAT8 (0x0u << 0) /**< \brief (ISC_RLP_CFG) 8-bit data */\r
+#define ISC_RLP_CFG_MODE_DAT9 (0x1u << 0) /**< \brief (ISC_RLP_CFG) 9-bit data */\r
+#define ISC_RLP_CFG_MODE_DAT10 (0x2u << 0) /**< \brief (ISC_RLP_CFG) 10-bit data */\r
+#define ISC_RLP_CFG_MODE_DAT11 (0x3u << 0) /**< \brief (ISC_RLP_CFG) 11-bit data */\r
+#define ISC_RLP_CFG_MODE_DAT12 (0x4u << 0) /**< \brief (ISC_RLP_CFG) 12-bit data */\r
+#define ISC_RLP_CFG_MODE_DATY8 (0x5u << 0) /**< \brief (ISC_RLP_CFG) 8-bit luminance only */\r
+#define ISC_RLP_CFG_MODE_DATY10 (0x6u << 0) /**< \brief (ISC_RLP_CFG) 10-bit luminance only */\r
+#define ISC_RLP_CFG_MODE_ARGB444 (0x7u << 0) /**< \brief (ISC_RLP_CFG) 12-bit RGB+4-bit Alpha (MSB) */\r
+#define ISC_RLP_CFG_MODE_ARGB555 (0x8u << 0) /**< \brief (ISC_RLP_CFG) 15-bit RGB+1-bit Alpha (MSB) */\r
+#define ISC_RLP_CFG_MODE_RGB565 (0x9u << 0) /**< \brief (ISC_RLP_CFG) 16-bit RGB */\r
+#define ISC_RLP_CFG_MODE_ARGB32 (0xAu << 0) /**< \brief (ISC_RLP_CFG) 24-bits RGB mode+8-bit Alpha */\r
+#define ISC_RLP_CFG_MODE_YYCC (0xBu << 0) /**< \brief (ISC_RLP_CFG) YCbCr mode (full range, [0-255]) */\r
+#define ISC_RLP_CFG_MODE_YYCC_LIMITED (0xCu << 0) /**< \brief (ISC_RLP_CFG) YCbCr mode (limited range) */\r
+#define ISC_RLP_CFG_ALPHA_Pos 8\r
+#define ISC_RLP_CFG_ALPHA_Msk (0xffu << ISC_RLP_CFG_ALPHA_Pos) /**< \brief (ISC_RLP_CFG) Alpha Value for Alpha-enabled RGB Mode */\r
+#define ISC_RLP_CFG_ALPHA(value) ((ISC_RLP_CFG_ALPHA_Msk & ((value) << ISC_RLP_CFG_ALPHA_Pos)))\r
+/* -------- ISC_HIS_CTRL : (ISC Offset: 0x3D4) Histogram Control Register -------- */\r
+#define ISC_HIS_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_HIS_CTRL) Histogram Sub Module Enable */\r
+/* -------- ISC_HIS_CFG : (ISC Offset: 0x3D8) Histogram Configuration Register -------- */\r
+#define ISC_HIS_CFG_MODE_Pos 0\r
+#define ISC_HIS_CFG_MODE_Msk (0x7u << ISC_HIS_CFG_MODE_Pos) /**< \brief (ISC_HIS_CFG) Histogram Operating Mode */\r
+#define ISC_HIS_CFG_MODE(value) ((ISC_HIS_CFG_MODE_Msk & ((value) << ISC_HIS_CFG_MODE_Pos)))\r
+#define ISC_HIS_CFG_MODE_Gr (0x0u << 0) /**< \brief (ISC_HIS_CFG) Gr sampling */\r
+#define ISC_HIS_CFG_MODE_R (0x1u << 0) /**< \brief (ISC_HIS_CFG) R sampling */\r
+#define ISC_HIS_CFG_MODE_Gb (0x2u << 0) /**< \brief (ISC_HIS_CFG) Gb sampling */\r
+#define ISC_HIS_CFG_MODE_B (0x3u << 0) /**< \brief (ISC_HIS_CFG) B sampling */\r
+#define ISC_HIS_CFG_MODE_Y (0x4u << 0) /**< \brief (ISC_HIS_CFG) Luminance-only mode */\r
+#define ISC_HIS_CFG_MODE_RAW (0x5u << 0) /**< \brief (ISC_HIS_CFG) Raw sampling */\r
+#define ISC_HIS_CFG_MODE_YCCIR656 (0x6u << 0) /**< \brief (ISC_HIS_CFG) Luminance only with CCIR656 10-bit or 8-bit mode */\r
+#define ISC_HIS_CFG_BAYSEL_Pos 4\r
+#define ISC_HIS_CFG_BAYSEL_Msk (0x3u << ISC_HIS_CFG_BAYSEL_Pos) /**< \brief (ISC_HIS_CFG) Bayer Color Component Selection */\r
+#define ISC_HIS_CFG_BAYSEL(value) ((ISC_HIS_CFG_BAYSEL_Msk & ((value) << ISC_HIS_CFG_BAYSEL_Pos)))\r
+#define ISC_HIS_CFG_BAYSEL_GRGR (0x0u << 4) /**< \brief (ISC_HIS_CFG) Starting row configuration is G R G R (red row) */\r
+#define ISC_HIS_CFG_BAYSEL_RGRG (0x1u << 4) /**< \brief (ISC_HIS_CFG) Starting row configuration is R G R G (red row */\r
+#define ISC_HIS_CFG_BAYSEL_GBGB (0x2u << 4) /**< \brief (ISC_HIS_CFG) Starting row configuration is G B G B (blue row */\r
+#define ISC_HIS_CFG_BAYSEL_BGBG (0x3u << 4) /**< \brief (ISC_HIS_CFG) Starting row configuration is B G B G (blue row) */\r
+#define ISC_HIS_CFG_RAR (0x1u << 8) /**< \brief (ISC_HIS_CFG) Histogram Reset After Read */\r
+/* -------- ISC_DCFG : (ISC Offset: 0x3E0) DMA Configuration Register -------- */\r
+#define ISC_DCFG_IMODE_Pos 0\r
+#define ISC_DCFG_IMODE_Msk (0x7u << ISC_DCFG_IMODE_Pos) /**< \brief (ISC_DCFG) DMA Input Mode Selection */\r
+#define ISC_DCFG_IMODE(value) ((ISC_DCFG_IMODE_Msk & ((value) << ISC_DCFG_IMODE_Pos)))\r
+#define ISC_DCFG_IMODE_PACKED8 (0x0u << 0) /**< \brief (ISC_DCFG) 8 bits, single channel packed */\r
+#define ISC_DCFG_IMODE_PACKED16 (0x1u << 0) /**< \brief (ISC_DCFG) 16 bits, single channel packed */\r
+#define ISC_DCFG_IMODE_PACKED32 (0x2u << 0) /**< \brief (ISC_DCFG) 32 bits, single channel packed */\r
+#define ISC_DCFG_IMODE_YC422SP (0x3u << 0) /**< \brief (ISC_DCFG) 32 bits, dual channel */\r
+#define ISC_DCFG_IMODE_YC422P (0x4u << 0) /**< \brief (ISC_DCFG) 32 bits, triple channel */\r
+#define ISC_DCFG_IMODE_YC420SP (0x5u << 0) /**< \brief (ISC_DCFG) 32 bits, dual channel */\r
+#define ISC_DCFG_IMODE_YC420P (0x6u << 0) /**< \brief (ISC_DCFG) 32 bits, triple channel */\r
+#define ISC_DCFG_YMBSIZE_Pos 4\r
+#define ISC_DCFG_YMBSIZE_Msk (0x3u << ISC_DCFG_YMBSIZE_Pos) /**< \brief (ISC_DCFG) DMA Memory Burst Size Y channel */\r
+#define ISC_DCFG_YMBSIZE(value) ((ISC_DCFG_YMBSIZE_Msk & ((value) << ISC_DCFG_YMBSIZE_Pos)))\r
+#define ISC_DCFG_YMBSIZE_SINGLE (0x0u << 4) /**< \brief (ISC_DCFG) DMA single access */\r
+#define ISC_DCFG_YMBSIZE_BEATS4 (0x1u << 4) /**< \brief (ISC_DCFG) 4-beat burst access */\r
+#define ISC_DCFG_YMBSIZE_BEATS8 (0x2u << 4) /**< \brief (ISC_DCFG) 8-beat burst access */\r
+#define ISC_DCFG_YMBSIZE_BEATS16 (0x3u << 4) /**< \brief (ISC_DCFG) 16-beat burst access */\r
+#define ISC_DCFG_CMBSIZE_Pos 8\r
+#define ISC_DCFG_CMBSIZE_Msk (0x3u << ISC_DCFG_CMBSIZE_Pos) /**< \brief (ISC_DCFG) DMA Memory Burst Size C channel */\r
+#define ISC_DCFG_CMBSIZE(value) ((ISC_DCFG_CMBSIZE_Msk & ((value) << ISC_DCFG_CMBSIZE_Pos)))\r
+#define ISC_DCFG_CMBSIZE_SINGLE (0x0u << 8) /**< \brief (ISC_DCFG) DMA single access */\r
+#define ISC_DCFG_CMBSIZE_BEATS4 (0x1u << 8) /**< \brief (ISC_DCFG) 4-beat burst access */\r
+#define ISC_DCFG_CMBSIZE_BEATS8 (0x2u << 8) /**< \brief (ISC_DCFG) 8-beat burst access */\r
+#define ISC_DCFG_CMBSIZE_BEATS16 (0x3u << 8) /**< \brief (ISC_DCFG) 16-beat burst access */\r
+/* -------- ISC_DCTRL : (ISC Offset: 0x3E4) DMA Control Register -------- */\r
+#define ISC_DCTRL_DE (0x1u << 0) /**< \brief (ISC_DCTRL) Descriptor Enable */\r
+#define ISC_DCTRL_DVIEW_Pos 1\r
+#define ISC_DCTRL_DVIEW_Msk (0x3u << ISC_DCTRL_DVIEW_Pos) /**< \brief (ISC_DCTRL) Descriptor View */\r
+#define ISC_DCTRL_DVIEW(value) ((ISC_DCTRL_DVIEW_Msk & ((value) << ISC_DCTRL_DVIEW_Pos)))\r
+#define ISC_DCTRL_DVIEW_PACKED (0x0u << 1) /**< \brief (ISC_DCTRL) Address {0} Stride {0} are updated */\r
+#define ISC_DCTRL_DVIEW_SEMIPLANAR (0x1u << 1) /**< \brief (ISC_DCTRL) Address {0,1} Stride {0,1} are updated */\r
+#define ISC_DCTRL_DVIEW_PLANAR (0x2u << 1) /**< \brief (ISC_DCTRL) Address {0,1,2} Stride {0,1,2} are updated */\r
+#define ISC_DCTRL_IE (0x1u << 4) /**< \brief (ISC_DCTRL) Interrupt Enable */\r
+#define ISC_DCTRL_WB (0x1u << 5) /**< \brief (ISC_DCTRL) Write Back Operation Enable */\r
+/* -------- ISC_DNDA : (ISC Offset: 0x3E8) DMA Descriptor Address Register -------- */\r
+#define ISC_DNDA_NDA_Pos 2\r
+#define ISC_DNDA_NDA_Msk (0x3fffffffu << ISC_DNDA_NDA_Pos) /**< \brief (ISC_DNDA) Next Descriptor Address Register */\r
+#define ISC_DNDA_NDA(value) ((ISC_DNDA_NDA_Msk & ((value) << ISC_DNDA_NDA_Pos)))\r
+/* -------- ISC_DAD : (ISC Offset: N/A) DMA Address 0 Register -------- */\r
+#define ISC_DAD_AD0_Pos 0\r
+#define ISC_DAD_AD0_Msk (0xffffffffu << ISC_DAD_AD0_Pos) /**< \brief (ISC_DAD) Channel 0 Address */\r
+#define ISC_DAD_AD0(value) ((ISC_DAD_AD0_Msk & ((value) << ISC_DAD_AD0_Pos)))\r
+/* -------- ISC_DST : (ISC Offset: N/A) DMA Stride 0 Register -------- */\r
+#define ISC_DST_ST0_Pos 0\r
+#define ISC_DST_ST0_Msk (0xffffffffu << ISC_DST_ST0_Pos) /**< \brief (ISC_DST) Channel 0 Stride */\r
+#define ISC_DST_ST0(value) ((ISC_DST_ST0_Msk & ((value) << ISC_DST_ST0_Pos)))\r
+/* -------- IPB_VERSION : (ISC Offset: 0x40C) Version Register -------- */\r
+#define IPB_VERSION_VERSION_Pos 0\r
+#define IPB_VERSION_VERSION_Msk (0xfffu << IPB_VERSION_VERSION_Pos) /**< \brief (IPB_VERSION) */\r
+#define IPB_VERSION_MFN_Pos 16\r
+#define IPB_VERSION_MFN_Msk (0x7u << IPB_VERSION_MFN_Pos) /**< \brief (IPB_VERSION) */\r
+/* -------- ISC_HIS_ENTRY[512] : (ISC Offset: 0x410) Histogram Entry -------- */\r
+#define ISC_HIS_ENTRY_COUNT_Pos 0\r
+#define ISC_HIS_ENTRY_COUNT_Msk (0xfffffu << ISC_HIS_ENTRY_COUNT_Pos) /**< \brief (ISC_HIS_ENTRY[512]) Entry Counter */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_ISC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_L2CC_COMPONENT_\r
+#define _SAMA5D2_L2CC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR L2 Cache Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_L2CC L2 Cache Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief L2cc hardware registers */\r
+typedef struct {\r
+ __I uint32_t L2CC_IDR; /**< \brief (L2cc Offset: 0x000) Cache ID Register */\r
+ __I uint32_t L2CC_TYPR; /**< \brief (L2cc Offset: 0x004) Cache Type Register */\r
+ __I uint32_t Reserved1[62];\r
+ __IO uint32_t L2CC_CR; /**< \brief (L2cc Offset: 0x100) Control Register */\r
+ __IO uint32_t L2CC_ACR; /**< \brief (L2cc Offset: 0x104) Auxiliary Control Register */\r
+ __IO uint32_t L2CC_TRCR; /**< \brief (L2cc Offset: 0x108) Tag RAM Control Register */\r
+ __IO uint32_t L2CC_DRCR; /**< \brief (L2cc Offset: 0x10C) Data RAM Control Register */\r
+ __I uint32_t Reserved2[60];\r
+ __IO uint32_t L2CC_ECR; /**< \brief (L2cc Offset: 0x200) Event Counter Control Register */\r
+ __IO uint32_t L2CC_ECFGR1; /**< \brief (L2cc Offset: 0x204) Event Counter 1 Configuration Register */\r
+ __IO uint32_t L2CC_ECFGR0; /**< \brief (L2cc Offset: 0x208) Event Counter 0 Configuration Register */\r
+ __IO uint32_t L2CC_EVR1; /**< \brief (L2cc Offset: 0x20C) Event Counter 1 Value Register */\r
+ __IO uint32_t L2CC_EVR0; /**< \brief (L2cc Offset: 0x210) Event Counter 0 Value Register */\r
+ __IO uint32_t L2CC_IMR; /**< \brief (L2cc Offset: 0x214) Interrupt Mask Register */\r
+ __I uint32_t L2CC_MISR; /**< \brief (L2cc Offset: 0x218) Masked Interrupt Status Register */\r
+ __I uint32_t L2CC_RISR; /**< \brief (L2cc Offset: 0x21C) Raw Interrupt Status Register */\r
+ __IO uint32_t L2CC_ICR; /**< \brief (L2cc Offset: 0x220) Interrupt Clear Register */\r
+ __I uint32_t Reserved3[323];\r
+ __IO uint32_t L2CC_CSR; /**< \brief (L2cc Offset: 0x730) Cache Synchronization Register */\r
+ __I uint32_t Reserved4[15];\r
+ __IO uint32_t L2CC_IPALR; /**< \brief (L2cc Offset: 0x770) Invalidate Physical Address Line Register */\r
+ __I uint32_t Reserved5[2];\r
+ __IO uint32_t L2CC_IWR; /**< \brief (L2cc Offset: 0x77C) Invalidate Way Register */\r
+ __I uint32_t Reserved6[12];\r
+ __IO uint32_t L2CC_CPALR; /**< \brief (L2cc Offset: 0x7B0) Clean Physical Address Line Register */\r
+ __I uint32_t Reserved7[1];\r
+ __IO uint32_t L2CC_CIR; /**< \brief (L2cc Offset: 0x7B8) Clean Index Register */\r
+ __IO uint32_t L2CC_CWR; /**< \brief (L2cc Offset: 0x7BC) Clean Way Register */\r
+ __I uint32_t Reserved8[12];\r
+ __IO uint32_t L2CC_CIPALR; /**< \brief (L2cc Offset: 0x7F0) Clean Invalidate Physical Address Line Register */\r
+ __I uint32_t Reserved9[1];\r
+ __IO uint32_t L2CC_CIIR; /**< \brief (L2cc Offset: 0x7F8) Clean Invalidate Index Register */\r
+ __IO uint32_t L2CC_CIWR; /**< \brief (L2cc Offset: 0x7FC) Clean Invalidate Way Register */\r
+ __I uint32_t Reserved10[64];\r
+ __IO uint32_t L2CC_DLKR; /**< \brief (L2cc Offset: 0x900) Data Lockdown Register */\r
+ __IO uint32_t L2CC_ILKR; /**< \brief (L2cc Offset: 0x904) Instruction Lockdown Register */\r
+ __I uint32_t Reserved11[398];\r
+ __IO uint32_t L2CC_DCR; /**< \brief (L2cc Offset: 0xF40) Debug Control Register */\r
+ __I uint32_t Reserved12[7];\r
+ __IO uint32_t L2CC_PCR; /**< \brief (L2cc Offset: 0xF60) Prefetch Control Register */\r
+ __I uint32_t Reserved13[7];\r
+ __IO uint32_t L2CC_POWCR; /**< \brief (L2cc Offset: 0xF80) Power Control Register */\r
+} L2cc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- L2CC_IDR : (L2CC Offset: 0x000) Cache ID Register -------- */\r
+#define L2CC_IDR_ID_Pos 0\r
+#define L2CC_IDR_ID_Msk (0xffffffffu << L2CC_IDR_ID_Pos) /**< \brief (L2CC_IDR) Cache Controller ID */\r
+/* -------- L2CC_TYPR : (L2CC Offset: 0x004) Cache Type Register -------- */\r
+#define L2CC_TYPR_IL2ASS (0x1u << 6) /**< \brief (L2CC_TYPR) Instruction L2 Cache Associativity */\r
+#define L2CC_TYPR_IL2WSIZE_Pos 8\r
+#define L2CC_TYPR_IL2WSIZE_Msk (0x7u << L2CC_TYPR_IL2WSIZE_Pos) /**< \brief (L2CC_TYPR) Instruction L2 Cache Way Size */\r
+#define L2CC_TYPR_DL2ASS (0x1u << 18) /**< \brief (L2CC_TYPR) Data L2 Cache Associativity */\r
+#define L2CC_TYPR_DL2WSIZE_Pos 20\r
+#define L2CC_TYPR_DL2WSIZE_Msk (0x7u << L2CC_TYPR_DL2WSIZE_Pos) /**< \brief (L2CC_TYPR) Data L2 Cache Way Size */\r
+/* -------- L2CC_CR : (L2CC Offset: 0x100) Control Register -------- */\r
+#define L2CC_CR_L2CEN (0x1u << 0) /**< \brief (L2CC_CR) L2 Cache Enable */\r
+/* -------- L2CC_ACR : (L2CC Offset: 0x104) Auxiliary Control Register -------- */\r
+#define L2CC_ACR_HPSO (0x1u << 10) /**< \brief (L2CC_ACR) High Priority for SO and Dev Reads Enable */\r
+#define L2CC_ACR_SBDLE (0x1u << 11) /**< \brief (L2CC_ACR) Store Buffer Device Limitation Enable */\r
+#define L2CC_ACR_EXCC (0x1u << 12) /**< \brief (L2CC_ACR) Exclusive Cache Configuration */\r
+#define L2CC_ACR_SAIE (0x1u << 13) /**< \brief (L2CC_ACR) Shared Attribute Invalidate Enable */\r
+#define L2CC_ACR_ASS (0x1u << 16) /**< \brief (L2CC_ACR) Associativity */\r
+#define L2CC_ACR_WAYSIZE_Pos 17\r
+#define L2CC_ACR_WAYSIZE_Msk (0x7u << L2CC_ACR_WAYSIZE_Pos) /**< \brief (L2CC_ACR) Way Size */\r
+#define L2CC_ACR_WAYSIZE(value) ((L2CC_ACR_WAYSIZE_Msk & ((value) << L2CC_ACR_WAYSIZE_Pos)))\r
+#define L2CC_ACR_WAYSIZE_16KB_WAY (0x1u << 17) /**< \brief (L2CC_ACR) 16-Kbyte way set associative */\r
+#define L2CC_ACR_EMBEN (0x1u << 20) /**< \brief (L2CC_ACR) Event Monitor Bus Enable */\r
+#define L2CC_ACR_PEN (0x1u << 21) /**< \brief (L2CC_ACR) Parity Enable */\r
+#define L2CC_ACR_SAOEN (0x1u << 22) /**< \brief (L2CC_ACR) Shared Attribute Override Enable */\r
+#define L2CC_ACR_FWA_Pos 23\r
+#define L2CC_ACR_FWA_Msk (0x3u << L2CC_ACR_FWA_Pos) /**< \brief (L2CC_ACR) Force Write Allocate */\r
+#define L2CC_ACR_FWA(value) ((L2CC_ACR_FWA_Msk & ((value) << L2CC_ACR_FWA_Pos)))\r
+#define L2CC_ACR_CRPOL (0x1u << 25) /**< \brief (L2CC_ACR) Cache Replacement Policy */\r
+#define L2CC_ACR_NSLEN (0x1u << 26) /**< \brief (L2CC_ACR) Non-Secure Lockdown Enable */\r
+#define L2CC_ACR_NSIAC (0x1u << 27) /**< \brief (L2CC_ACR) Non-Secure Interrupt Access Control */\r
+#define L2CC_ACR_DPEN (0x1u << 28) /**< \brief (L2CC_ACR) Data Prefetch Enable */\r
+#define L2CC_ACR_IPEN (0x1u << 29) /**< \brief (L2CC_ACR) Instruction Prefetch Enable */\r
+/* -------- L2CC_TRCR : (L2CC Offset: 0x108) Tag RAM Control Register -------- */\r
+#define L2CC_TRCR_TSETLAT_Pos 0\r
+#define L2CC_TRCR_TSETLAT_Msk (0x7u << L2CC_TRCR_TSETLAT_Pos) /**< \brief (L2CC_TRCR) Setup Latency */\r
+#define L2CC_TRCR_TSETLAT(value) ((L2CC_TRCR_TSETLAT_Msk & ((value) << L2CC_TRCR_TSETLAT_Pos)))\r
+#define L2CC_TRCR_TRDLAT_Pos 4\r
+#define L2CC_TRCR_TRDLAT_Msk (0x7u << L2CC_TRCR_TRDLAT_Pos) /**< \brief (L2CC_TRCR) Read Access Latency */\r
+#define L2CC_TRCR_TRDLAT(value) ((L2CC_TRCR_TRDLAT_Msk & ((value) << L2CC_TRCR_TRDLAT_Pos)))\r
+#define L2CC_TRCR_TWRLAT_Pos 8\r
+#define L2CC_TRCR_TWRLAT_Msk (0x7u << L2CC_TRCR_TWRLAT_Pos) /**< \brief (L2CC_TRCR) Write Access Latency */\r
+#define L2CC_TRCR_TWRLAT(value) ((L2CC_TRCR_TWRLAT_Msk & ((value) << L2CC_TRCR_TWRLAT_Pos)))\r
+/* -------- L2CC_DRCR : (L2CC Offset: 0x10C) Data RAM Control Register -------- */\r
+#define L2CC_DRCR_DSETLAT_Pos 0\r
+#define L2CC_DRCR_DSETLAT_Msk (0x7u << L2CC_DRCR_DSETLAT_Pos) /**< \brief (L2CC_DRCR) Setup Latency */\r
+#define L2CC_DRCR_DSETLAT(value) ((L2CC_DRCR_DSETLAT_Msk & ((value) << L2CC_DRCR_DSETLAT_Pos)))\r
+#define L2CC_DRCR_DRDLAT_Pos 4\r
+#define L2CC_DRCR_DRDLAT_Msk (0x7u << L2CC_DRCR_DRDLAT_Pos) /**< \brief (L2CC_DRCR) Read Access Latency */\r
+#define L2CC_DRCR_DRDLAT(value) ((L2CC_DRCR_DRDLAT_Msk & ((value) << L2CC_DRCR_DRDLAT_Pos)))\r
+#define L2CC_DRCR_DWRLAT_Pos 8\r
+#define L2CC_DRCR_DWRLAT_Msk (0x7u << L2CC_DRCR_DWRLAT_Pos) /**< \brief (L2CC_DRCR) Write Access Latency */\r
+#define L2CC_DRCR_DWRLAT(value) ((L2CC_DRCR_DWRLAT_Msk & ((value) << L2CC_DRCR_DWRLAT_Pos)))\r
+/* -------- L2CC_ECR : (L2CC Offset: 0x200) Event Counter Control Register -------- */\r
+#define L2CC_ECR_EVCEN (0x1u << 0) /**< \brief (L2CC_ECR) Event Counter Enable */\r
+#define L2CC_ECR_EVC0RST (0x1u << 1) /**< \brief (L2CC_ECR) Event Counter 0 Reset */\r
+#define L2CC_ECR_EVC1RST (0x1u << 2) /**< \brief (L2CC_ECR) Event Counter 1 Reset */\r
+/* -------- L2CC_ECFGR1 : (L2CC Offset: 0x204) Event Counter 1 Configuration Register -------- */\r
+#define L2CC_ECFGR1_EIGEN_Pos 0\r
+#define L2CC_ECFGR1_EIGEN_Msk (0x3u << L2CC_ECFGR1_EIGEN_Pos) /**< \brief (L2CC_ECFGR1) Event Counter Interrupt Generation */\r
+#define L2CC_ECFGR1_EIGEN(value) ((L2CC_ECFGR1_EIGEN_Msk & ((value) << L2CC_ECFGR1_EIGEN_Pos)))\r
+#define L2CC_ECFGR1_EIGEN_INT_DIS (0x0u << 0) /**< \brief (L2CC_ECFGR1) Disables (default) */\r
+#define L2CC_ECFGR1_EIGEN_INT_EN_INCR (0x1u << 0) /**< \brief (L2CC_ECFGR1) Enables with Increment condition */\r
+#define L2CC_ECFGR1_EIGEN_INT_EN_OVER (0x2u << 0) /**< \brief (L2CC_ECFGR1) Enables with Overflow condition */\r
+#define L2CC_ECFGR1_EIGEN_INT_GEN_DIS (0x3u << 0) /**< \brief (L2CC_ECFGR1) Disables Interrupt generation */\r
+#define L2CC_ECFGR1_ESRC_Pos 2\r
+#define L2CC_ECFGR1_ESRC_Msk (0xfu << L2CC_ECFGR1_ESRC_Pos) /**< \brief (L2CC_ECFGR1) Event Counter Source */\r
+#define L2CC_ECFGR1_ESRC(value) ((L2CC_ECFGR1_ESRC_Msk & ((value) << L2CC_ECFGR1_ESRC_Pos)))\r
+#define L2CC_ECFGR1_ESRC_CNT_DIS (0x0u << 2) /**< \brief (L2CC_ECFGR1) Counter Disabled */\r
+#define L2CC_ECFGR1_ESRC_SRC_CO (0x1u << 2) /**< \brief (L2CC_ECFGR1) Source is CO */\r
+#define L2CC_ECFGR1_ESRC_SRC_DRHIT (0x2u << 2) /**< \brief (L2CC_ECFGR1) Source is DRHIT */\r
+#define L2CC_ECFGR1_ESRC_SRC_DRREQ (0x3u << 2) /**< \brief (L2CC_ECFGR1) Source is DRREQ */\r
+#define L2CC_ECFGR1_ESRC_SRC_DWHIT (0x4u << 2) /**< \brief (L2CC_ECFGR1) Source is DWHIT */\r
+#define L2CC_ECFGR1_ESRC_SRC_DWREQ (0x5u << 2) /**< \brief (L2CC_ECFGR1) Source is DWREQ */\r
+#define L2CC_ECFGR1_ESRC_SRC_DWTREQ (0x6u << 2) /**< \brief (L2CC_ECFGR1) Source is DWTREQ */\r
+#define L2CC_ECFGR1_ESRC_SRC_IRHIT (0x7u << 2) /**< \brief (L2CC_ECFGR1) Source is IRHIT */\r
+#define L2CC_ECFGR1_ESRC_SRC_IRREQ (0x8u << 2) /**< \brief (L2CC_ECFGR1) Source is IRREQ */\r
+#define L2CC_ECFGR1_ESRC_SRC_WA (0x9u << 2) /**< \brief (L2CC_ECFGR1) Source is WA */\r
+#define L2CC_ECFGR1_ESRC_SRC_IPFALLOC (0xAu << 2) /**< \brief (L2CC_ECFGR1) Source is IPFALLOC */\r
+#define L2CC_ECFGR1_ESRC_SRC_EPFHIT (0xBu << 2) /**< \brief (L2CC_ECFGR1) Source is EPFHIT */\r
+#define L2CC_ECFGR1_ESRC_SRC_EPFALLOC (0xCu << 2) /**< \brief (L2CC_ECFGR1) Source is EPFALLOC */\r
+#define L2CC_ECFGR1_ESRC_SRC_SRRCVD (0xDu << 2) /**< \brief (L2CC_ECFGR1) Source is SRRCVD */\r
+#define L2CC_ECFGR1_ESRC_SRC_SRCONF (0xEu << 2) /**< \brief (L2CC_ECFGR1) Source is SRCONF */\r
+#define L2CC_ECFGR1_ESRC_SRC_EPFRCVD (0xFu << 2) /**< \brief (L2CC_ECFGR1) Source is EPFRCVD */\r
+/* -------- L2CC_ECFGR0 : (L2CC Offset: 0x208) Event Counter 0 Configuration Register -------- */\r
+#define L2CC_ECFGR0_EIGEN_Pos 0\r
+#define L2CC_ECFGR0_EIGEN_Msk (0x3u << L2CC_ECFGR0_EIGEN_Pos) /**< \brief (L2CC_ECFGR0) Event Counter Interrupt Generation */\r
+#define L2CC_ECFGR0_EIGEN(value) ((L2CC_ECFGR0_EIGEN_Msk & ((value) << L2CC_ECFGR0_EIGEN_Pos)))\r
+#define L2CC_ECFGR0_EIGEN_INT_DIS (0x0u << 0) /**< \brief (L2CC_ECFGR0) Disables (default) */\r
+#define L2CC_ECFGR0_EIGEN_INT_EN_INCR (0x1u << 0) /**< \brief (L2CC_ECFGR0) Enables with Increment condition */\r
+#define L2CC_ECFGR0_EIGEN_INT_EN_OVER (0x2u << 0) /**< \brief (L2CC_ECFGR0) Enables with Overflow condition */\r
+#define L2CC_ECFGR0_EIGEN_INT_GEN_DIS (0x3u << 0) /**< \brief (L2CC_ECFGR0) Disables Interrupt generation */\r
+#define L2CC_ECFGR0_ESRC_Pos 2\r
+#define L2CC_ECFGR0_ESRC_Msk (0xfu << L2CC_ECFGR0_ESRC_Pos) /**< \brief (L2CC_ECFGR0) Event Counter Source */\r
+#define L2CC_ECFGR0_ESRC(value) ((L2CC_ECFGR0_ESRC_Msk & ((value) << L2CC_ECFGR0_ESRC_Pos)))\r
+#define L2CC_ECFGR0_ESRC_CNT_DIS (0x0u << 2) /**< \brief (L2CC_ECFGR0) Counter Disabled */\r
+#define L2CC_ECFGR0_ESRC_SRC_CO (0x1u << 2) /**< \brief (L2CC_ECFGR0) Source is CO */\r
+#define L2CC_ECFGR0_ESRC_SRC_DRHIT (0x2u << 2) /**< \brief (L2CC_ECFGR0) Source is DRHIT */\r
+#define L2CC_ECFGR0_ESRC_SRC_DRREQ (0x3u << 2) /**< \brief (L2CC_ECFGR0) Source is DRREQ */\r
+#define L2CC_ECFGR0_ESRC_SRC_DWHIT (0x4u << 2) /**< \brief (L2CC_ECFGR0) Source is DWHIT */\r
+#define L2CC_ECFGR0_ESRC_SRC_DWREQ (0x5u << 2) /**< \brief (L2CC_ECFGR0) Source is DWREQ */\r
+#define L2CC_ECFGR0_ESRC_SRC_DWTREQ (0x6u << 2) /**< \brief (L2CC_ECFGR0) Source is DWTREQ */\r
+#define L2CC_ECFGR0_ESRC_SRC_IRHIT (0x7u << 2) /**< \brief (L2CC_ECFGR0) Source is IRHIT */\r
+#define L2CC_ECFGR0_ESRC_SRC_IRREQ (0x8u << 2) /**< \brief (L2CC_ECFGR0) Source is IRREQ */\r
+#define L2CC_ECFGR0_ESRC_SRC_WA (0x9u << 2) /**< \brief (L2CC_ECFGR0) Source is WA */\r
+#define L2CC_ECFGR0_ESRC_SRC_IPFALLOC (0xAu << 2) /**< \brief (L2CC_ECFGR0) Source is IPFALLOC */\r
+#define L2CC_ECFGR0_ESRC_SRC_EPFHIT (0xBu << 2) /**< \brief (L2CC_ECFGR0) Source is EPFHIT */\r
+#define L2CC_ECFGR0_ESRC_SRC_EPFALLOC (0xCu << 2) /**< \brief (L2CC_ECFGR0) Source is EPFALLOC */\r
+#define L2CC_ECFGR0_ESRC_SRC_SRRCVD (0xDu << 2) /**< \brief (L2CC_ECFGR0) Source is SRRCVD */\r
+#define L2CC_ECFGR0_ESRC_SRC_SRCONF (0xEu << 2) /**< \brief (L2CC_ECFGR0) Source is SRCONF */\r
+#define L2CC_ECFGR0_ESRC_SRC_EPFRCVD (0xFu << 2) /**< \brief (L2CC_ECFGR0) Source is EPFRCVD */\r
+/* -------- L2CC_EVR1 : (L2CC Offset: 0x20C) Event Counter 1 Value Register -------- */\r
+#define L2CC_EVR1_VALUE_Pos 0\r
+#define L2CC_EVR1_VALUE_Msk (0xffffffffu << L2CC_EVR1_VALUE_Pos) /**< \brief (L2CC_EVR1) Event Counter Value */\r
+#define L2CC_EVR1_VALUE(value) ((L2CC_EVR1_VALUE_Msk & ((value) << L2CC_EVR1_VALUE_Pos)))\r
+/* -------- L2CC_EVR0 : (L2CC Offset: 0x210) Event Counter 0 Value Register -------- */\r
+#define L2CC_EVR0_VALUE_Pos 0\r
+#define L2CC_EVR0_VALUE_Msk (0xffffffffu << L2CC_EVR0_VALUE_Pos) /**< \brief (L2CC_EVR0) Event Counter Value */\r
+#define L2CC_EVR0_VALUE(value) ((L2CC_EVR0_VALUE_Msk & ((value) << L2CC_EVR0_VALUE_Pos)))\r
+/* -------- L2CC_IMR : (L2CC Offset: 0x214) Interrupt Mask Register -------- */\r
+#define L2CC_IMR_ECNTR (0x1u << 0) /**< \brief (L2CC_IMR) Event Counter 1/0 Overflow Increment */\r
+#define L2CC_IMR_PARRT (0x1u << 1) /**< \brief (L2CC_IMR) Parity Error on L2 Tag RAM, Read */\r
+#define L2CC_IMR_PARRD (0x1u << 2) /**< \brief (L2CC_IMR) Parity Error on L2 Data RAM, Read */\r
+#define L2CC_IMR_ERRWT (0x1u << 3) /**< \brief (L2CC_IMR) Error on L2 Tag RAM, Write */\r
+#define L2CC_IMR_ERRWD (0x1u << 4) /**< \brief (L2CC_IMR) Error on L2 Data RAM, Write */\r
+#define L2CC_IMR_ERRRT (0x1u << 5) /**< \brief (L2CC_IMR) Error on L2 Tag RAM, Read */\r
+#define L2CC_IMR_ERRRD (0x1u << 6) /**< \brief (L2CC_IMR) Error on L2 Data RAM, Read */\r
+#define L2CC_IMR_SLVERR (0x1u << 7) /**< \brief (L2CC_IMR) SLVERR from L3 Memory */\r
+#define L2CC_IMR_DECERR (0x1u << 8) /**< \brief (L2CC_IMR) DECERR from L3 Memory */\r
+/* -------- L2CC_MISR : (L2CC Offset: 0x218) Masked Interrupt Status Register -------- */\r
+#define L2CC_MISR_ECNTR (0x1u << 0) /**< \brief (L2CC_MISR) Event Counter 1/0 Overflow Increment */\r
+#define L2CC_MISR_PARRT (0x1u << 1) /**< \brief (L2CC_MISR) Parity Error on L2 Tag RAM, Read */\r
+#define L2CC_MISR_PARRD (0x1u << 2) /**< \brief (L2CC_MISR) Parity Error on L2 Data RAM, Read */\r
+#define L2CC_MISR_ERRWT (0x1u << 3) /**< \brief (L2CC_MISR) Error on L2 Tag RAM, Write */\r
+#define L2CC_MISR_ERRWD (0x1u << 4) /**< \brief (L2CC_MISR) Error on L2 Data RAM, Write */\r
+#define L2CC_MISR_ERRRT (0x1u << 5) /**< \brief (L2CC_MISR) Error on L2 Tag RAM, Read */\r
+#define L2CC_MISR_ERRRD (0x1u << 6) /**< \brief (L2CC_MISR) Error on L2 Data RAM, Read */\r
+#define L2CC_MISR_SLVERR (0x1u << 7) /**< \brief (L2CC_MISR) SLVERR from L3 memory */\r
+#define L2CC_MISR_DECERR (0x1u << 8) /**< \brief (L2CC_MISR) DECERR from L3 memory */\r
+/* -------- L2CC_RISR : (L2CC Offset: 0x21C) Raw Interrupt Status Register -------- */\r
+#define L2CC_RISR_ECNTR (0x1u << 0) /**< \brief (L2CC_RISR) Event Counter 1/0 Overflow Increment */\r
+#define L2CC_RISR_PARRT (0x1u << 1) /**< \brief (L2CC_RISR) Parity Error on L2 Tag RAM, Read */\r
+#define L2CC_RISR_PARRD (0x1u << 2) /**< \brief (L2CC_RISR) Parity Error on L2 Data RAM, Read */\r
+#define L2CC_RISR_ERRWT (0x1u << 3) /**< \brief (L2CC_RISR) Error on L2 Tag RAM, Write */\r
+#define L2CC_RISR_ERRWD (0x1u << 4) /**< \brief (L2CC_RISR) Error on L2 Data RAM, Write */\r
+#define L2CC_RISR_ERRRT (0x1u << 5) /**< \brief (L2CC_RISR) Error on L2 Tag RAM, Read */\r
+#define L2CC_RISR_ERRRD (0x1u << 6) /**< \brief (L2CC_RISR) Error on L2 Data RAM, Read */\r
+#define L2CC_RISR_SLVERR (0x1u << 7) /**< \brief (L2CC_RISR) SLVERR from L3 memory */\r
+#define L2CC_RISR_DECERR (0x1u << 8) /**< \brief (L2CC_RISR) DECERR from L3 memory */\r
+/* -------- L2CC_ICR : (L2CC Offset: 0x220) Interrupt Clear Register -------- */\r
+#define L2CC_ICR_ECNTR (0x1u << 0) /**< \brief (L2CC_ICR) Event Counter 1/0 Overflow Increment */\r
+#define L2CC_ICR_PARRT (0x1u << 1) /**< \brief (L2CC_ICR) Parity Error on L2 Tag RAM, Read */\r
+#define L2CC_ICR_PARRD (0x1u << 2) /**< \brief (L2CC_ICR) Parity Error on L2 Data RAM, Read */\r
+#define L2CC_ICR_ERRWT (0x1u << 3) /**< \brief (L2CC_ICR) Error on L2 Tag RAM, Write */\r
+#define L2CC_ICR_ERRWD (0x1u << 4) /**< \brief (L2CC_ICR) Error on L2 Data RAM, Write */\r
+#define L2CC_ICR_ERRRT (0x1u << 5) /**< \brief (L2CC_ICR) Error on L2 Tag RAM, Read */\r
+#define L2CC_ICR_ERRRD (0x1u << 6) /**< \brief (L2CC_ICR) Error on L2 Data RAM, Read */\r
+#define L2CC_ICR_SLVERR (0x1u << 7) /**< \brief (L2CC_ICR) SLVERR from L3 memory */\r
+#define L2CC_ICR_DECERR (0x1u << 8) /**< \brief (L2CC_ICR) DECERR from L3 memory */\r
+/* -------- L2CC_CSR : (L2CC Offset: 0x730) Cache Synchronization Register -------- */\r
+#define L2CC_CSR_C (0x1u << 0) /**< \brief (L2CC_CSR) Cache Synchronization Status */\r
+/* -------- L2CC_IPALR : (L2CC Offset: 0x770) Invalidate Physical Address Line Register -------- */\r
+#define L2CC_IPALR_C (0x1u << 0) /**< \brief (L2CC_IPALR) Cache Synchronization Status */\r
+#define L2CC_IPALR_IDX_Pos 5\r
+#define L2CC_IPALR_IDX_Msk (0x1ffu << L2CC_IPALR_IDX_Pos) /**< \brief (L2CC_IPALR) Index Number */\r
+#define L2CC_IPALR_IDX(value) ((L2CC_IPALR_IDX_Msk & ((value) << L2CC_IPALR_IDX_Pos)))\r
+#define L2CC_IPALR_TAG_Pos 14\r
+#define L2CC_IPALR_TAG_Msk (0x3ffffu << L2CC_IPALR_TAG_Pos) /**< \brief (L2CC_IPALR) Tag Number */\r
+#define L2CC_IPALR_TAG(value) ((L2CC_IPALR_TAG_Msk & ((value) << L2CC_IPALR_TAG_Pos)))\r
+/* -------- L2CC_IWR : (L2CC Offset: 0x77C) Invalidate Way Register -------- */\r
+#define L2CC_IWR_WAY0 (0x1u << 0) /**< \brief (L2CC_IWR) Invalidate Way Number 0 */\r
+#define L2CC_IWR_WAY1 (0x1u << 1) /**< \brief (L2CC_IWR) Invalidate Way Number 1 */\r
+#define L2CC_IWR_WAY2 (0x1u << 2) /**< \brief (L2CC_IWR) Invalidate Way Number 2 */\r
+#define L2CC_IWR_WAY3 (0x1u << 3) /**< \brief (L2CC_IWR) Invalidate Way Number 3 */\r
+#define L2CC_IWR_WAY4 (0x1u << 4) /**< \brief (L2CC_IWR) Invalidate Way Number 4 */\r
+#define L2CC_IWR_WAY5 (0x1u << 5) /**< \brief (L2CC_IWR) Invalidate Way Number 5 */\r
+#define L2CC_IWR_WAY6 (0x1u << 6) /**< \brief (L2CC_IWR) Invalidate Way Number 6 */\r
+#define L2CC_IWR_WAY7 (0x1u << 7) /**< \brief (L2CC_IWR) Invalidate Way Number 7 */\r
+/* -------- L2CC_CPALR : (L2CC Offset: 0x7B0) Clean Physical Address Line Register -------- */\r
+#define L2CC_CPALR_C (0x1u << 0) /**< \brief (L2CC_CPALR) Cache Synchronization Status */\r
+#define L2CC_CPALR_IDX_Pos 5\r
+#define L2CC_CPALR_IDX_Msk (0x1ffu << L2CC_CPALR_IDX_Pos) /**< \brief (L2CC_CPALR) Index number */\r
+#define L2CC_CPALR_IDX(value) ((L2CC_CPALR_IDX_Msk & ((value) << L2CC_CPALR_IDX_Pos)))\r
+#define L2CC_CPALR_TAG_Pos 14\r
+#define L2CC_CPALR_TAG_Msk (0x3ffffu << L2CC_CPALR_TAG_Pos) /**< \brief (L2CC_CPALR) Tag number */\r
+#define L2CC_CPALR_TAG(value) ((L2CC_CPALR_TAG_Msk & ((value) << L2CC_CPALR_TAG_Pos)))\r
+/* -------- L2CC_CIR : (L2CC Offset: 0x7B8) Clean Index Register -------- */\r
+#define L2CC_CIR_C (0x1u << 0) /**< \brief (L2CC_CIR) Cache Synchronization Status */\r
+#define L2CC_CIR_IDX_Pos 5\r
+#define L2CC_CIR_IDX_Msk (0x1ffu << L2CC_CIR_IDX_Pos) /**< \brief (L2CC_CIR) Index number */\r
+#define L2CC_CIR_IDX(value) ((L2CC_CIR_IDX_Msk & ((value) << L2CC_CIR_IDX_Pos)))\r
+#define L2CC_CIR_WAY_Pos 28\r
+#define L2CC_CIR_WAY_Msk (0x7u << L2CC_CIR_WAY_Pos) /**< \brief (L2CC_CIR) Way number */\r
+#define L2CC_CIR_WAY(value) ((L2CC_CIR_WAY_Msk & ((value) << L2CC_CIR_WAY_Pos)))\r
+/* -------- L2CC_CWR : (L2CC Offset: 0x7BC) Clean Way Register -------- */\r
+#define L2CC_CWR_WAY0 (0x1u << 0) /**< \brief (L2CC_CWR) Clean Way Number 0 */\r
+#define L2CC_CWR_WAY1 (0x1u << 1) /**< \brief (L2CC_CWR) Clean Way Number 1 */\r
+#define L2CC_CWR_WAY2 (0x1u << 2) /**< \brief (L2CC_CWR) Clean Way Number 2 */\r
+#define L2CC_CWR_WAY3 (0x1u << 3) /**< \brief (L2CC_CWR) Clean Way Number 3 */\r
+#define L2CC_CWR_WAY4 (0x1u << 4) /**< \brief (L2CC_CWR) Clean Way Number 4 */\r
+#define L2CC_CWR_WAY5 (0x1u << 5) /**< \brief (L2CC_CWR) Clean Way Number 5 */\r
+#define L2CC_CWR_WAY6 (0x1u << 6) /**< \brief (L2CC_CWR) Clean Way Number 6 */\r
+#define L2CC_CWR_WAY7 (0x1u << 7) /**< \brief (L2CC_CWR) Clean Way Number 7 */\r
+/* -------- L2CC_CIPALR : (L2CC Offset: 0x7F0) Clean Invalidate Physical Address Line Register -------- */\r
+#define L2CC_CIPALR_C (0x1u << 0) /**< \brief (L2CC_CIPALR) Cache Synchronization Status */\r
+#define L2CC_CIPALR_IDX_Pos 5\r
+#define L2CC_CIPALR_IDX_Msk (0x1ffu << L2CC_CIPALR_IDX_Pos) /**< \brief (L2CC_CIPALR) Index Number */\r
+#define L2CC_CIPALR_IDX(value) ((L2CC_CIPALR_IDX_Msk & ((value) << L2CC_CIPALR_IDX_Pos)))\r
+#define L2CC_CIPALR_TAG_Pos 14\r
+#define L2CC_CIPALR_TAG_Msk (0x3ffffu << L2CC_CIPALR_TAG_Pos) /**< \brief (L2CC_CIPALR) Tag Number */\r
+#define L2CC_CIPALR_TAG(value) ((L2CC_CIPALR_TAG_Msk & ((value) << L2CC_CIPALR_TAG_Pos)))\r
+/* -------- L2CC_CIIR : (L2CC Offset: 0x7F8) Clean Invalidate Index Register -------- */\r
+#define L2CC_CIIR_C (0x1u << 0) /**< \brief (L2CC_CIIR) Cache Synchronization Status */\r
+#define L2CC_CIIR_IDX_Pos 5\r
+#define L2CC_CIIR_IDX_Msk (0x1ffu << L2CC_CIIR_IDX_Pos) /**< \brief (L2CC_CIIR) Index Number */\r
+#define L2CC_CIIR_IDX(value) ((L2CC_CIIR_IDX_Msk & ((value) << L2CC_CIIR_IDX_Pos)))\r
+#define L2CC_CIIR_WAY_Pos 28\r
+#define L2CC_CIIR_WAY_Msk (0x7u << L2CC_CIIR_WAY_Pos) /**< \brief (L2CC_CIIR) Way Number */\r
+#define L2CC_CIIR_WAY(value) ((L2CC_CIIR_WAY_Msk & ((value) << L2CC_CIIR_WAY_Pos)))\r
+/* -------- L2CC_CIWR : (L2CC Offset: 0x7FC) Clean Invalidate Way Register -------- */\r
+#define L2CC_CIWR_WAY0 (0x1u << 0) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 0 */\r
+#define L2CC_CIWR_WAY1 (0x1u << 1) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 1 */\r
+#define L2CC_CIWR_WAY2 (0x1u << 2) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 2 */\r
+#define L2CC_CIWR_WAY3 (0x1u << 3) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 3 */\r
+#define L2CC_CIWR_WAY4 (0x1u << 4) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 4 */\r
+#define L2CC_CIWR_WAY5 (0x1u << 5) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 5 */\r
+#define L2CC_CIWR_WAY6 (0x1u << 6) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 6 */\r
+#define L2CC_CIWR_WAY7 (0x1u << 7) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 7 */\r
+/* -------- L2CC_DLKR : (L2CC Offset: 0x900) Data Lockdown Register -------- */\r
+#define L2CC_DLKR_DLK0 (0x1u << 0) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 0 */\r
+#define L2CC_DLKR_DLK1 (0x1u << 1) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 1 */\r
+#define L2CC_DLKR_DLK2 (0x1u << 2) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 2 */\r
+#define L2CC_DLKR_DLK3 (0x1u << 3) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 3 */\r
+#define L2CC_DLKR_DLK4 (0x1u << 4) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 4 */\r
+#define L2CC_DLKR_DLK5 (0x1u << 5) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 5 */\r
+#define L2CC_DLKR_DLK6 (0x1u << 6) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 6 */\r
+#define L2CC_DLKR_DLK7 (0x1u << 7) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 7 */\r
+/* -------- L2CC_ILKR : (L2CC Offset: 0x904) Instruction Lockdown Register -------- */\r
+#define L2CC_ILKR_ILK0 (0x1u << 0) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 0 */\r
+#define L2CC_ILKR_ILK1 (0x1u << 1) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 1 */\r
+#define L2CC_ILKR_ILK2 (0x1u << 2) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 2 */\r
+#define L2CC_ILKR_ILK3 (0x1u << 3) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 3 */\r
+#define L2CC_ILKR_ILK4 (0x1u << 4) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 4 */\r
+#define L2CC_ILKR_ILK5 (0x1u << 5) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 5 */\r
+#define L2CC_ILKR_ILK6 (0x1u << 6) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 6 */\r
+#define L2CC_ILKR_ILK7 (0x1u << 7) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 7 */\r
+/* -------- L2CC_DCR : (L2CC Offset: 0xF40) Debug Control Register -------- */\r
+#define L2CC_DCR_DCL (0x1u << 0) /**< \brief (L2CC_DCR) Disable Cache Linefill */\r
+#define L2CC_DCR_DWB (0x1u << 1) /**< \brief (L2CC_DCR) Disable Write-back, Force Write-through */\r
+#define L2CC_DCR_SPNIDEN (0x1u << 2) /**< \brief (L2CC_DCR) SPNIDEN Value */\r
+/* -------- L2CC_PCR : (L2CC Offset: 0xF60) Prefetch Control Register -------- */\r
+#define L2CC_PCR_OFFSET_Pos 0\r
+#define L2CC_PCR_OFFSET_Msk (0x1fu << L2CC_PCR_OFFSET_Pos) /**< \brief (L2CC_PCR) Prefetch Offset */\r
+#define L2CC_PCR_OFFSET(value) ((L2CC_PCR_OFFSET_Msk & ((value) << L2CC_PCR_OFFSET_Pos)))\r
+#define L2CC_PCR_NSIDEN (0x1u << 21) /**< \brief (L2CC_PCR) Not Same ID on Exclusive Sequence Enable */\r
+#define L2CC_PCR_IDLEN (0x1u << 23) /**< \brief (L2CC_PCR) INCR Double Linefill Enable */\r
+#define L2CC_PCR_PDEN (0x1u << 24) /**< \brief (L2CC_PCR) Prefetch Drop Enable */\r
+#define L2CC_PCR_DLFWRDIS (0x1u << 27) /**< \brief (L2CC_PCR) Double Linefill on WRAP Read Disable */\r
+#define L2CC_PCR_DATPEN (0x1u << 28) /**< \brief (L2CC_PCR) Data Prefetch Enable */\r
+#define L2CC_PCR_INSPEN (0x1u << 29) /**< \brief (L2CC_PCR) Instruction Prefetch Enable */\r
+#define L2CC_PCR_DLEN (0x1u << 30) /**< \brief (L2CC_PCR) Double Linefill Enable */\r
+/* -------- L2CC_POWCR : (L2CC Offset: 0xF80) Power Control Register -------- */\r
+#define L2CC_POWCR_STBYEN (0x1u << 0) /**< \brief (L2CC_POWCR) Standby Mode Enable */\r
+#define L2CC_POWCR_DCKGATEN (0x1u << 1) /**< \brief (L2CC_POWCR) Dynamic Clock Gating Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_L2CC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_LCDC_COMPONENT_\r
+#define _SAMA5D2_LCDC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR LCD Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_LCDC LCD Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Lcdc hardware registers */\r
+typedef struct {\r
+ __IO uint32_t LCDC_LCDCFG0; /**< \brief (Lcdc Offset: 0x00000000) LCD Controller Configuration Register 0 */\r
+ __IO uint32_t LCDC_LCDCFG1; /**< \brief (Lcdc Offset: 0x00000004) LCD Controller Configuration Register 1 */\r
+ __IO uint32_t LCDC_LCDCFG2; /**< \brief (Lcdc Offset: 0x00000008) LCD Controller Configuration Register 2 */\r
+ __IO uint32_t LCDC_LCDCFG3; /**< \brief (Lcdc Offset: 0x0000000C) LCD Controller Configuration Register 3 */\r
+ __IO uint32_t LCDC_LCDCFG4; /**< \brief (Lcdc Offset: 0x00000010) LCD Controller Configuration Register 4 */\r
+ __IO uint32_t LCDC_LCDCFG5; /**< \brief (Lcdc Offset: 0x00000014) LCD Controller Configuration Register 5 */\r
+ __IO uint32_t LCDC_LCDCFG6; /**< \brief (Lcdc Offset: 0x00000018) LCD Controller Configuration Register 6 */\r
+ __I uint32_t Reserved1[1];\r
+ __O uint32_t LCDC_LCDEN; /**< \brief (Lcdc Offset: 0x00000020) LCD Controller Enable Register */\r
+ __O uint32_t LCDC_LCDDIS; /**< \brief (Lcdc Offset: 0x00000024) LCD Controller Disable Register */\r
+ __I uint32_t LCDC_LCDSR; /**< \brief (Lcdc Offset: 0x00000028) LCD Controller Status Register */\r
+ __O uint32_t LCDC_LCDIER; /**< \brief (Lcdc Offset: 0x0000002C) LCD Controller Interrupt Enable Register */\r
+ __O uint32_t LCDC_LCDIDR; /**< \brief (Lcdc Offset: 0x00000030) LCD Controller Interrupt Disable Register */\r
+ __I uint32_t LCDC_LCDIMR; /**< \brief (Lcdc Offset: 0x00000034) LCD Controller Interrupt Mask Register */\r
+ __I uint32_t LCDC_LCDISR; /**< \brief (Lcdc Offset: 0x00000038) LCD Controller Interrupt Status Register */\r
+ __O uint32_t LCDC_ATTR; /**< \brief (Lcdc Offset: 0x0000003C) LCD Controller Attribute Register */\r
+ __O uint32_t LCDC_BASECHER; /**< \brief (Lcdc Offset: 0x00000040) Base Layer Channel Enable Register */\r
+ __O uint32_t LCDC_BASECHDR; /**< \brief (Lcdc Offset: 0x00000044) Base Layer Channel Disable Register */\r
+ __I uint32_t LCDC_BASECHSR; /**< \brief (Lcdc Offset: 0x00000048) Base Layer Channel Status Register */\r
+ __O uint32_t LCDC_BASEIER; /**< \brief (Lcdc Offset: 0x0000004C) Base Layer Interrupt Enable Register */\r
+ __O uint32_t LCDC_BASEIDR; /**< \brief (Lcdc Offset: 0x00000050) Base Layer Interrupt Disabled Register */\r
+ __I uint32_t LCDC_BASEIMR; /**< \brief (Lcdc Offset: 0x00000054) Base Layer Interrupt Mask Register */\r
+ __I uint32_t LCDC_BASEISR; /**< \brief (Lcdc Offset: 0x00000058) Base Layer Interrupt Status Register */\r
+ __IO uint32_t LCDC_BASEHEAD; /**< \brief (Lcdc Offset: 0x0000005C) Base DMA Head Register */\r
+ __IO uint32_t LCDC_BASEADDR; /**< \brief (Lcdc Offset: 0x00000060) Base DMA Address Register */\r
+ __IO uint32_t LCDC_BASECTRL; /**< \brief (Lcdc Offset: 0x00000064) Base DMA Control Register */\r
+ __IO uint32_t LCDC_BASENEXT; /**< \brief (Lcdc Offset: 0x00000068) Base DMA Next Register */\r
+ __IO uint32_t LCDC_BASECFG0; /**< \brief (Lcdc Offset: 0x0000006C) Base Layer Configuration Register 0 */\r
+ __IO uint32_t LCDC_BASECFG1; /**< \brief (Lcdc Offset: 0x00000070) Base Layer Configuration Register 1 */\r
+ __IO uint32_t LCDC_BASECFG2; /**< \brief (Lcdc Offset: 0x00000074) Base Layer Configuration Register 2 */\r
+ __IO uint32_t LCDC_BASECFG3; /**< \brief (Lcdc Offset: 0x00000078) Base Layer Configuration Register 3 */\r
+ __IO uint32_t LCDC_BASECFG4; /**< \brief (Lcdc Offset: 0x0000007C) Base Layer Configuration Register 4 */\r
+ __IO uint32_t LCDC_BASECFG5; /**< \brief (Lcdc Offset: 0x00000080) Base Layer Configuration Register 5 */\r
+ __IO uint32_t LCDC_BASECFG6; /**< \brief (Lcdc Offset: 0x00000084) Base Layer Configuration Register 6 */\r
+ __I uint32_t Reserved2[46];\r
+ __O uint32_t LCDC_OVR1CHER; /**< \brief (Lcdc Offset: 0x00000140) Overlay 1 Channel Enable Register */\r
+ __O uint32_t LCDC_OVR1CHDR; /**< \brief (Lcdc Offset: 0x00000144) Overlay 1 Channel Disable Register */\r
+ __I uint32_t LCDC_OVR1CHSR; /**< \brief (Lcdc Offset: 0x00000148) Overlay 1 Channel Status Register */\r
+ __O uint32_t LCDC_OVR1IER; /**< \brief (Lcdc Offset: 0x0000014C) Overlay 1 Interrupt Enable Register */\r
+ __O uint32_t LCDC_OVR1IDR; /**< \brief (Lcdc Offset: 0x00000150) Overlay 1 Interrupt Disable Register */\r
+ __I uint32_t LCDC_OVR1IMR; /**< \brief (Lcdc Offset: 0x00000154) Overlay 1 Interrupt Mask Register */\r
+ __I uint32_t LCDC_OVR1ISR; /**< \brief (Lcdc Offset: 0x00000158) Overlay 1 Interrupt Status Register */\r
+ __IO uint32_t LCDC_OVR1HEAD; /**< \brief (Lcdc Offset: 0x0000015C) Overlay 1 DMA Head Register */\r
+ __IO uint32_t LCDC_OVR1ADDR; /**< \brief (Lcdc Offset: 0x00000160) Overlay 1 DMA Address Register */\r
+ __IO uint32_t LCDC_OVR1CTRL; /**< \brief (Lcdc Offset: 0x00000164) Overlay 1 DMA Control Register */\r
+ __IO uint32_t LCDC_OVR1NEXT; /**< \brief (Lcdc Offset: 0x00000168) Overlay 1 DMA Next Register */\r
+ __IO uint32_t LCDC_OVR1CFG0; /**< \brief (Lcdc Offset: 0x0000016C) Overlay 1 Configuration Register 0 */\r
+ __IO uint32_t LCDC_OVR1CFG1; /**< \brief (Lcdc Offset: 0x00000170) Overlay 1 Configuration Register 1 */\r
+ __IO uint32_t LCDC_OVR1CFG2; /**< \brief (Lcdc Offset: 0x00000174) Overlay 1 Configuration Register 2 */\r
+ __IO uint32_t LCDC_OVR1CFG3; /**< \brief (Lcdc Offset: 0x00000178) Overlay 1 Configuration Register 3 */\r
+ __IO uint32_t LCDC_OVR1CFG4; /**< \brief (Lcdc Offset: 0x0000017C) Overlay 1 Configuration Register 4 */\r
+ __IO uint32_t LCDC_OVR1CFG5; /**< \brief (Lcdc Offset: 0x00000180) Overlay 1 Configuration Register 5 */\r
+ __IO uint32_t LCDC_OVR1CFG6; /**< \brief (Lcdc Offset: 0x00000184) Overlay 1 Configuration Register 6 */\r
+ __IO uint32_t LCDC_OVR1CFG7; /**< \brief (Lcdc Offset: 0x00000188) Overlay 1 Configuration Register 7 */\r
+ __IO uint32_t LCDC_OVR1CFG8; /**< \brief (Lcdc Offset: 0x0000018C) Overlay 1 Configuration Register 8 */\r
+ __IO uint32_t LCDC_OVR1CFG9; /**< \brief (Lcdc Offset: 0x00000190) Overlay 1 Configuration Register 9 */\r
+ __I uint32_t Reserved3[43];\r
+ __O uint32_t LCDC_OVR2CHER; /**< \brief (Lcdc Offset: 0x00000240) Overlay 2 Channel Enable Register */\r
+ __O uint32_t LCDC_OVR2CHDR; /**< \brief (Lcdc Offset: 0x00000244) Overlay 2 Channel Disable Register */\r
+ __I uint32_t LCDC_OVR2CHSR; /**< \brief (Lcdc Offset: 0x00000248) Overlay 2 Channel Status Register */\r
+ __O uint32_t LCDC_OVR2IER; /**< \brief (Lcdc Offset: 0x0000024C) Overlay 2 Interrupt Enable Register */\r
+ __O uint32_t LCDC_OVR2IDR; /**< \brief (Lcdc Offset: 0x00000250) Overlay 2 Interrupt Disable Register */\r
+ __I uint32_t LCDC_OVR2IMR; /**< \brief (Lcdc Offset: 0x00000254) Overlay 2 Interrupt Mask Register */\r
+ __I uint32_t LCDC_OVR2ISR; /**< \brief (Lcdc Offset: 0x00000258) Overlay 2 Interrupt Status Register */\r
+ __IO uint32_t LCDC_OVR2HEAD; /**< \brief (Lcdc Offset: 0x0000025C) Overlay 2 DMA Head Register */\r
+ __IO uint32_t LCDC_OVR2ADDR; /**< \brief (Lcdc Offset: 0x00000260) Overlay 2 DMA Address Register */\r
+ __IO uint32_t LCDC_OVR2CTRL; /**< \brief (Lcdc Offset: 0x00000264) Overlay 2 DMA Control Register */\r
+ __IO uint32_t LCDC_OVR2NEXT; /**< \brief (Lcdc Offset: 0x00000268) Overlay 2 DMA Next Register */\r
+ __IO uint32_t LCDC_OVR2CFG0; /**< \brief (Lcdc Offset: 0x0000026C) Overlay 2 Configuration Register 0 */\r
+ __IO uint32_t LCDC_OVR2CFG1; /**< \brief (Lcdc Offset: 0x00000270) Overlay 2 Configuration Register 1 */\r
+ __IO uint32_t LCDC_OVR2CFG2; /**< \brief (Lcdc Offset: 0x00000274) Overlay 2 Configuration Register 2 */\r
+ __IO uint32_t LCDC_OVR2CFG3; /**< \brief (Lcdc Offset: 0x00000278) Overlay 2 Configuration Register 3 */\r
+ __IO uint32_t LCDC_OVR2CFG4; /**< \brief (Lcdc Offset: 0x0000027C) Overlay 2 Configuration Register 4 */\r
+ __IO uint32_t LCDC_OVR2CFG5; /**< \brief (Lcdc Offset: 0x00000280) Overlay 2 Configuration Register 5 */\r
+ __IO uint32_t LCDC_OVR2CFG6; /**< \brief (Lcdc Offset: 0x00000284) Overlay 2 Configuration Register 6 */\r
+ __IO uint32_t LCDC_OVR2CFG7; /**< \brief (Lcdc Offset: 0x00000288) Overlay 2 Configuration Register 7 */\r
+ __IO uint32_t LCDC_OVR2CFG8; /**< \brief (Lcdc Offset: 0x0000028C) Overlay 2 Configuration Register 8 */\r
+ __IO uint32_t LCDC_OVR2CFG9; /**< \brief (Lcdc Offset: 0x00000290) Overlay 2 Configuration Register 8 */\r
+ __I uint32_t Reserved4[43];\r
+ __O uint32_t LCDC_HEOCHER; /**< \brief (Lcdc Offset: 0x00000340) High End Overlay Channel Enable Register */\r
+ __O uint32_t LCDC_HEOCHDR; /**< \brief (Lcdc Offset: 0x00000344) High End Overlay Channel Disable Register */\r
+ __I uint32_t LCDC_HEOCHSR; /**< \brief (Lcdc Offset: 0x00000348) High End Overlay Channel Status Register */\r
+ __O uint32_t LCDC_HEOIER; /**< \brief (Lcdc Offset: 0x0000034C) High End Overlay Interrupt Enable Register */\r
+ __O uint32_t LCDC_HEOIDR; /**< \brief (Lcdc Offset: 0x00000350) High End Overlay Interrupt Disable Register */\r
+ __I uint32_t LCDC_HEOIMR; /**< \brief (Lcdc Offset: 0x00000354) High End Overlay Interrupt Mask Register */\r
+ __I uint32_t LCDC_HEOISR; /**< \brief (Lcdc Offset: 0x00000358) High End Overlay Interrupt Status Register */\r
+ __IO uint32_t LCDC_HEOHEAD; /**< \brief (Lcdc Offset: 0x0000035C) High End Overlay DMA Head Register */\r
+ __IO uint32_t LCDC_HEOADDR; /**< \brief (Lcdc Offset: 0x00000360) High End Overlay DMA Address Register */\r
+ __IO uint32_t LCDC_HEOCTRL; /**< \brief (Lcdc Offset: 0x00000364) High End Overlay DMA Control Register */\r
+ __IO uint32_t LCDC_HEONEXT; /**< \brief (Lcdc Offset: 0x00000368) High End Overlay DMA Next Register */\r
+ __IO uint32_t LCDC_HEOUHEAD; /**< \brief (Lcdc Offset: 0x0000036C) High End Overlay U-UV DMA Head Register */\r
+ __IO uint32_t LCDC_HEOUADDR; /**< \brief (Lcdc Offset: 0x00000370) High End Overlay U-UV DMA Address Register */\r
+ __IO uint32_t LCDC_HEOUCTRL; /**< \brief (Lcdc Offset: 0x00000374) High End Overlay U-UV DMA Control Register */\r
+ __IO uint32_t LCDC_HEOUNEXT; /**< \brief (Lcdc Offset: 0x00000378) High End Overlay U-UV DMA Next Register */\r
+ __IO uint32_t LCDC_HEOVHEAD; /**< \brief (Lcdc Offset: 0x0000037C) High End Overlay V DMA Head Register */\r
+ __IO uint32_t LCDC_HEOVADDR; /**< \brief (Lcdc Offset: 0x00000380) High End Overlay V DMA Address Register */\r
+ __IO uint32_t LCDC_HEOVCTRL; /**< \brief (Lcdc Offset: 0x00000384) High End Overlay V DMA Control Register */\r
+ __IO uint32_t LCDC_HEOVNEXT; /**< \brief (Lcdc Offset: 0x00000388) High End Overlay V DMA Next Register */\r
+ __IO uint32_t LCDC_HEOCFG0; /**< \brief (Lcdc Offset: 0x0000038C) High End Overlay Configuration Register 0 */\r
+ __IO uint32_t LCDC_HEOCFG1; /**< \brief (Lcdc Offset: 0x00000390) High End Overlay Configuration Register 1 */\r
+ __IO uint32_t LCDC_HEOCFG2; /**< \brief (Lcdc Offset: 0x00000394) High End Overlay Configuration Register 2 */\r
+ __IO uint32_t LCDC_HEOCFG3; /**< \brief (Lcdc Offset: 0x00000398) High End Overlay Configuration Register 3 */\r
+ __IO uint32_t LCDC_HEOCFG4; /**< \brief (Lcdc Offset: 0x0000039C) High End Overlay Configuration Register 4 */\r
+ __IO uint32_t LCDC_HEOCFG5; /**< \brief (Lcdc Offset: 0x000003A0) High End Overlay Configuration Register 5 */\r
+ __IO uint32_t LCDC_HEOCFG6; /**< \brief (Lcdc Offset: 0x000003A4) High End Overlay Configuration Register 6 */\r
+ __IO uint32_t LCDC_HEOCFG7; /**< \brief (Lcdc Offset: 0x000003A8) High End Overlay Configuration Register 7 */\r
+ __IO uint32_t LCDC_HEOCFG8; /**< \brief (Lcdc Offset: 0x000003AC) High End Overlay Configuration Register 8 */\r
+ __IO uint32_t LCDC_HEOCFG9; /**< \brief (Lcdc Offset: 0x000003B0) High End Overlay Configuration Register 9 */\r
+ __IO uint32_t LCDC_HEOCFG10; /**< \brief (Lcdc Offset: 0x000003B4) High End Overlay Configuration Register 10 */\r
+ __IO uint32_t LCDC_HEOCFG11; /**< \brief (Lcdc Offset: 0x000003B8) High End Overlay Configuration Register 11 */\r
+ __IO uint32_t LCDC_HEOCFG12; /**< \brief (Lcdc Offset: 0x000003BC) High End Overlay Configuration Register 12 */\r
+ __IO uint32_t LCDC_HEOCFG13; /**< \brief (Lcdc Offset: 0x000003C0) High End Overlay Configuration Register 13 */\r
+ __IO uint32_t LCDC_HEOCFG14; /**< \brief (Lcdc Offset: 0x000003C4) High End Overlay Configuration Register 14 */\r
+ __IO uint32_t LCDC_HEOCFG15; /**< \brief (Lcdc Offset: 0x000003C8) High End Overlay Configuration Register 15 */\r
+ __IO uint32_t LCDC_HEOCFG16; /**< \brief (Lcdc Offset: 0x000003CC) High End Overlay Configuration Register 16 */\r
+ __IO uint32_t LCDC_HEOCFG17; /**< \brief (Lcdc Offset: 0x000003D0) High End Overlay Configuration Register 17 */\r
+ __IO uint32_t LCDC_HEOCFG18; /**< \brief (Lcdc Offset: 0x000003D4) High End Overlay Configuration Register 18 */\r
+ __IO uint32_t LCDC_HEOCFG19; /**< \brief (Lcdc Offset: 0x000003D8) High End Overlay Configuration Register 19 */\r
+ __IO uint32_t LCDC_HEOCFG20; /**< \brief (Lcdc Offset: 0x000003DC) High End Overlay Configuration Register 20 */\r
+ __IO uint32_t LCDC_HEOCFG21; /**< \brief (Lcdc Offset: 0x000003E0) High End Overlay Configuration Register 21 */\r
+ __IO uint32_t LCDC_HEOCFG22; /**< \brief (Lcdc Offset: 0x000003E4) High End Overlay Configuration Register 22 */\r
+ __IO uint32_t LCDC_HEOCFG23; /**< \brief (Lcdc Offset: 0x000003E8) High End Overlay Configuration Register 23 */\r
+ __IO uint32_t LCDC_HEOCFG24; /**< \brief (Lcdc Offset: 0x000003EC) High End Overlay Configuration Register 24 */\r
+ __IO uint32_t LCDC_HEOCFG25; /**< \brief (Lcdc Offset: 0x000003F0) High End Overlay Configuration Register 25 */\r
+ __IO uint32_t LCDC_HEOCFG26; /**< \brief (Lcdc Offset: 0x000003F4) High End Overlay Configuration Register 26 */\r
+ __IO uint32_t LCDC_HEOCFG27; /**< \brief (Lcdc Offset: 0x000003F8) High End Overlay Configuration Register 27 */\r
+ __IO uint32_t LCDC_HEOCFG28; /**< \brief (Lcdc Offset: 0x000003FC) High End Overlay Configuration Register 28 */\r
+ __IO uint32_t LCDC_HEOCFG29; /**< \brief (Lcdc Offset: 0x00000400) High End Overlay Configuration Register 29 */\r
+ __IO uint32_t LCDC_HEOCFG30; /**< \brief (Lcdc Offset: 0x00000404) High End Overlay Configuration Register 30 */\r
+ __IO uint32_t LCDC_HEOCFG31; /**< \brief (Lcdc Offset: 0x00000408) High End Overlay Configuration Register 31 */\r
+ __IO uint32_t LCDC_HEOCFG32; /**< \brief (Lcdc Offset: 0x0000040C) High End Overlay Configuration Register 32 */\r
+ __IO uint32_t LCDC_HEOCFG33; /**< \brief (Lcdc Offset: 0x00000410) High End Overlay Configuration Register 33 */\r
+ __IO uint32_t LCDC_HEOCFG34; /**< \brief (Lcdc Offset: 0x00000414) High End Overlay Configuration Register 34 */\r
+ __IO uint32_t LCDC_HEOCFG35; /**< \brief (Lcdc Offset: 0x00000418) High End Overlay Configuration Register 35 */\r
+ __IO uint32_t LCDC_HEOCFG36; /**< \brief (Lcdc Offset: 0x0000041C) High End Overlay Configuration Register 36 */\r
+ __IO uint32_t LCDC_HEOCFG37; /**< \brief (Lcdc Offset: 0x00000420) High End Overlay Configuration Register 37 */\r
+ __IO uint32_t LCDC_HEOCFG38; /**< \brief (Lcdc Offset: 0x00000424) High End Overlay Configuration Register 38 */\r
+ __IO uint32_t LCDC_HEOCFG39; /**< \brief (Lcdc Offset: 0x00000428) High End Overlay Configuration Register 39 */\r
+ __IO uint32_t LCDC_HEOCFG40; /**< \brief (Lcdc Offset: 0x0000042C) High End Overlay Configuration Register 40 */\r
+ __IO uint32_t LCDC_HEOCFG41; /**< \brief (Lcdc Offset: 0x00000430) High End Overlay Configuration Register 41 */\r
+ __I uint32_t Reserved5[67];\r
+ __O uint32_t LCDC_PPCHER; /**< \brief (Lcdc Offset: 0x00000540) Post Processing Channel Enable Register */\r
+ __O uint32_t LCDC_PPCHDR; /**< \brief (Lcdc Offset: 0x00000544) Post Processing Channel Disable Register */\r
+ __I uint32_t LCDC_PPCHSR; /**< \brief (Lcdc Offset: 0x00000548) Post Processing Channel Status Register */\r
+ __O uint32_t LCDC_PPIER; /**< \brief (Lcdc Offset: 0x0000054C) Post Processing Interrupt Enable Register */\r
+ __O uint32_t LCDC_PPIDR; /**< \brief (Lcdc Offset: 0x00000550) Post Processing Interrupt Disable Register */\r
+ __I uint32_t LCDC_PPIMR; /**< \brief (Lcdc Offset: 0x00000554) Post Processing Interrupt Mask Register */\r
+ __I uint32_t LCDC_PPISR; /**< \brief (Lcdc Offset: 0x00000558) Post Processing Interrupt Status Register */\r
+ __IO uint32_t LCDC_PPHEAD; /**< \brief (Lcdc Offset: 0x0000055C) Post Processing Head Register */\r
+ __IO uint32_t LCDC_PPADDR; /**< \brief (Lcdc Offset: 0x00000560) Post Processing Address Register */\r
+ __IO uint32_t LCDC_PPCTRL; /**< \brief (Lcdc Offset: 0x00000564) Post Processing Control Register */\r
+ __IO uint32_t LCDC_PPNEXT; /**< \brief (Lcdc Offset: 0x00000568) Post Processing Next Register */\r
+ __IO uint32_t LCDC_PPCFG0; /**< \brief (Lcdc Offset: 0x0000056C) Post Processing Configuration Register 0 */\r
+ __IO uint32_t LCDC_PPCFG1; /**< \brief (Lcdc Offset: 0x00000570) Post Processing Configuration Register 1 */\r
+ __IO uint32_t LCDC_PPCFG2; /**< \brief (Lcdc Offset: 0x00000574) Post Processing Configuration Register 2 */\r
+ __IO uint32_t LCDC_PPCFG3; /**< \brief (Lcdc Offset: 0x00000578) Post Processing Configuration Register 3 */\r
+ __IO uint32_t LCDC_PPCFG4; /**< \brief (Lcdc Offset: 0x0000057C) Post Processing Configuration Register 4 */\r
+ __IO uint32_t LCDC_PPCFG5; /**< \brief (Lcdc Offset: 0x00000580) Post Processing Configuration Register 5 */\r
+ __I uint32_t Reserved6[31];\r
+ __IO uint32_t LCDC_BASECLUT[256]; /**< \brief (Lcdc Offset: 0x00000600) Base CLUT Register */\r
+ __IO uint32_t LCDC_OVR1CLUT[256]; /**< \brief (Lcdc Offset: 0x00000A00) Overlay 1 CLUT Register */\r
+ __IO uint32_t LCDC_OVR2CLUT[256]; /**< \brief (Lcdc Offset: 0x00000E00) Overlay 2 CLUT Register */\r
+ __IO uint32_t LCDC_HEOCLUT[256]; /**< \brief (Lcdc Offset: 0x00001200) High End Overlay CLUT Register */\r
+ __I uint32_t Reserved7[639];\r
+ __I uint32_t LCDC_VERSION; /**< \brief (Lcdc Offset: 0x00001FFC) Version Register */\r
+} Lcdc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- LCDC_LCDCFG0 : (LCDC Offset: 0x00000000) LCD Controller Configuration Register 0 -------- */\r
+#define LCDC_LCDCFG0_CLKPOL (0x1u << 0) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Polarity */\r
+#define LCDC_LCDCFG0_CLKSEL (0x1u << 2) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Source Selection */\r
+#define LCDC_LCDCFG0_CLKPWMSEL (0x1u << 3) /**< \brief (LCDC_LCDCFG0) LCD Controller PWM Clock Source Selection */\r
+#define LCDC_LCDCFG0_CGDISBASE (0x1u << 8) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Base Layer */\r
+#define LCDC_LCDCFG0_CGDISOVR1 (0x1u << 9) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Overlay 1 Layer */\r
+#define LCDC_LCDCFG0_CGDISOVR2 (0x1u << 10) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Overlay 2 Layer */\r
+#define LCDC_LCDCFG0_CGDISHEO (0x1u << 11) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the High End Overlay */\r
+#define LCDC_LCDCFG0_CGDISPP (0x1u << 13) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Post Processing Layer */\r
+#define LCDC_LCDCFG0_CLKDIV_Pos 16\r
+#define LCDC_LCDCFG0_CLKDIV_Msk (0xffu << LCDC_LCDCFG0_CLKDIV_Pos) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Divider */\r
+#define LCDC_LCDCFG0_CLKDIV(value) ((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))\r
+/* -------- LCDC_LCDCFG1 : (LCDC Offset: 0x00000004) LCD Controller Configuration Register 1 -------- */\r
+#define LCDC_LCDCFG1_HSPW_Pos 0\r
+#define LCDC_LCDCFG1_HSPW_Msk (0xffu << LCDC_LCDCFG1_HSPW_Pos) /**< \brief (LCDC_LCDCFG1) Horizontal Synchronization Pulse Width */\r
+#define LCDC_LCDCFG1_HSPW(value) ((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))\r
+#define LCDC_LCDCFG1_VSPW_Pos 16\r
+#define LCDC_LCDCFG1_VSPW_Msk (0xffu << LCDC_LCDCFG1_VSPW_Pos) /**< \brief (LCDC_LCDCFG1) Vertical Synchronization Pulse Width */\r
+#define LCDC_LCDCFG1_VSPW(value) ((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))\r
+/* -------- LCDC_LCDCFG2 : (LCDC Offset: 0x00000008) LCD Controller Configuration Register 2 -------- */\r
+#define LCDC_LCDCFG2_VFPW_Pos 0\r
+#define LCDC_LCDCFG2_VFPW_Msk (0xffu << LCDC_LCDCFG2_VFPW_Pos) /**< \brief (LCDC_LCDCFG2) Vertical Front Porch Width */\r
+#define LCDC_LCDCFG2_VFPW(value) ((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))\r
+#define LCDC_LCDCFG2_VBPW_Pos 16\r
+#define LCDC_LCDCFG2_VBPW_Msk (0xffu << LCDC_LCDCFG2_VBPW_Pos) /**< \brief (LCDC_LCDCFG2) Vertical Back Porch Width */\r
+#define LCDC_LCDCFG2_VBPW(value) ((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))\r
+/* -------- LCDC_LCDCFG3 : (LCDC Offset: 0x0000000C) LCD Controller Configuration Register 3 -------- */\r
+#define LCDC_LCDCFG3_HFPW_Pos 0\r
+#define LCDC_LCDCFG3_HFPW_Msk (0x3ffu << LCDC_LCDCFG3_HFPW_Pos) /**< \brief (LCDC_LCDCFG3) Horizontal Front Porch Width */\r
+#define LCDC_LCDCFG3_HFPW(value) ((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))\r
+#define LCDC_LCDCFG3_HBPW_Pos 16\r
+#define LCDC_LCDCFG3_HBPW_Msk (0x3ffu << LCDC_LCDCFG3_HBPW_Pos) /**< \brief (LCDC_LCDCFG3) Horizontal Back Porch Width */\r
+#define LCDC_LCDCFG3_HBPW(value) ((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))\r
+/* -------- LCDC_LCDCFG4 : (LCDC Offset: 0x00000010) LCD Controller Configuration Register 4 -------- */\r
+#define LCDC_LCDCFG4_PPL_Pos 0\r
+#define LCDC_LCDCFG4_PPL_Msk (0x7ffu << LCDC_LCDCFG4_PPL_Pos) /**< \brief (LCDC_LCDCFG4) Number of Pixels Per Line */\r
+#define LCDC_LCDCFG4_PPL(value) ((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))\r
+#define LCDC_LCDCFG4_RPF_Pos 16\r
+#define LCDC_LCDCFG4_RPF_Msk (0x7ffu << LCDC_LCDCFG4_RPF_Pos) /**< \brief (LCDC_LCDCFG4) Number of Active Row Per Frame */\r
+#define LCDC_LCDCFG4_RPF(value) ((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))\r
+/* -------- LCDC_LCDCFG5 : (LCDC Offset: 0x00000014) LCD Controller Configuration Register 5 -------- */\r
+#define LCDC_LCDCFG5_HSPOL (0x1u << 0) /**< \brief (LCDC_LCDCFG5) Horizontal Synchronization Pulse Polarity */\r
+#define LCDC_LCDCFG5_VSPOL (0x1u << 1) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse Polarity */\r
+#define LCDC_LCDCFG5_VSPDLYS (0x1u << 2) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse Start */\r
+#define LCDC_LCDCFG5_VSPDLYE (0x1u << 3) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse End */\r
+#define LCDC_LCDCFG5_DISPPOL (0x1u << 4) /**< \brief (LCDC_LCDCFG5) Display Signal Polarity */\r
+#define LCDC_LCDCFG5_DITHER (0x1u << 6) /**< \brief (LCDC_LCDCFG5) LCD Controller Dithering */\r
+#define LCDC_LCDCFG5_DISPDLY (0x1u << 7) /**< \brief (LCDC_LCDCFG5) LCD Controller Display Power Signal Synchronization */\r
+#define LCDC_LCDCFG5_MODE_Pos 8\r
+#define LCDC_LCDCFG5_MODE_Msk (0x3u << LCDC_LCDCFG5_MODE_Pos) /**< \brief (LCDC_LCDCFG5) LCD Controller Output Mode */\r
+#define LCDC_LCDCFG5_MODE(value) ((LCDC_LCDCFG5_MODE_Msk & ((value) << LCDC_LCDCFG5_MODE_Pos)))\r
+#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0u << 8) /**< \brief (LCDC_LCDCFG5) LCD Output mode is set to 12 bits per pixel */\r
+#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1u << 8) /**< \brief (LCDC_LCDCFG5) LCD Output mode is set to 16 bits per pixel */\r
+#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2u << 8) /**< \brief (LCDC_LCDCFG5) LCD Output mode is set to 18 bits per pixel */\r
+#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3u << 8) /**< \brief (LCDC_LCDCFG5) LCD Output mode is set to 24 bits per pixel */\r
+#define LCDC_LCDCFG5_PP (0x1u << 10) /**< \brief (LCDC_LCDCFG5) Post Processing Enable */\r
+#define LCDC_LCDCFG5_VSPSU (0x1u << 12) /**< \brief (LCDC_LCDCFG5) LCD Controller Vertical synchronization Pulse Setup Configuration */\r
+#define LCDC_LCDCFG5_VSPHO (0x1u << 13) /**< \brief (LCDC_LCDCFG5) LCD Controller Vertical synchronization Pulse Hold Configuration */\r
+#define LCDC_LCDCFG5_GUARDTIME_Pos 16\r
+#define LCDC_LCDCFG5_GUARDTIME_Msk (0xffu << LCDC_LCDCFG5_GUARDTIME_Pos) /**< \brief (LCDC_LCDCFG5) LCD DISPLAY Guard Time */\r
+#define LCDC_LCDCFG5_GUARDTIME(value) ((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))\r
+/* -------- LCDC_LCDCFG6 : (LCDC Offset: 0x00000018) LCD Controller Configuration Register 6 -------- */\r
+#define LCDC_LCDCFG6_PWMPS_Pos 0\r
+#define LCDC_LCDCFG6_PWMPS_Msk (0x7u << LCDC_LCDCFG6_PWMPS_Pos) /**< \brief (LCDC_LCDCFG6) PWM Clock Prescaler */\r
+#define LCDC_LCDCFG6_PWMPS(value) ((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))\r
+#define LCDC_LCDCFG6_PWMPS_DIV_1 (0x0u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK */\r
+#define LCDC_LCDCFG6_PWMPS_DIV_2 (0x1u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/2 */\r
+#define LCDC_LCDCFG6_PWMPS_DIV_4 (0x2u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/4 */\r
+#define LCDC_LCDCFG6_PWMPS_DIV_8 (0x3u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/8 */\r
+#define LCDC_LCDCFG6_PWMPS_DIV_16 (0x4u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/16 */\r
+#define LCDC_LCDCFG6_PWMPS_DIV_32 (0x5u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/32 */\r
+#define LCDC_LCDCFG6_PWMPS_DIV_64 (0x6u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/64 */\r
+#define LCDC_LCDCFG6_PWMPOL (0x1u << 4) /**< \brief (LCDC_LCDCFG6) LCD Controller PWM Signal Polarity */\r
+#define LCDC_LCDCFG6_PWMCVAL_Pos 8\r
+#define LCDC_LCDCFG6_PWMCVAL_Msk (0xffu << LCDC_LCDCFG6_PWMCVAL_Pos) /**< \brief (LCDC_LCDCFG6) LCD Controller PWM Compare Value */\r
+#define LCDC_LCDCFG6_PWMCVAL(value) ((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))\r
+/* -------- LCDC_LCDEN : (LCDC Offset: 0x00000020) LCD Controller Enable Register -------- */\r
+#define LCDC_LCDEN_CLKEN (0x1u << 0) /**< \brief (LCDC_LCDEN) LCD Controller Pixel Clock Enable */\r
+#define LCDC_LCDEN_SYNCEN (0x1u << 1) /**< \brief (LCDC_LCDEN) LCD Controller Horizontal and Vertical Synchronization Enable */\r
+#define LCDC_LCDEN_DISPEN (0x1u << 2) /**< \brief (LCDC_LCDEN) LCD Controller DISP Signal Enable */\r
+#define LCDC_LCDEN_PWMEN (0x1u << 3) /**< \brief (LCDC_LCDEN) LCD Controller Pulse Width Modulation Enable */\r
+/* -------- LCDC_LCDDIS : (LCDC Offset: 0x00000024) LCD Controller Disable Register -------- */\r
+#define LCDC_LCDDIS_CLKDIS (0x1u << 0) /**< \brief (LCDC_LCDDIS) LCD Controller Pixel Clock Disable */\r
+#define LCDC_LCDDIS_SYNCDIS (0x1u << 1) /**< \brief (LCDC_LCDDIS) LCD Controller Horizontal and Vertical Synchronization Disable */\r
+#define LCDC_LCDDIS_DISPDIS (0x1u << 2) /**< \brief (LCDC_LCDDIS) LCD Controller DISP Signal Disable */\r
+#define LCDC_LCDDIS_PWMDIS (0x1u << 3) /**< \brief (LCDC_LCDDIS) LCD Controller Pulse Width Modulation Disable */\r
+#define LCDC_LCDDIS_CLKRST (0x1u << 8) /**< \brief (LCDC_LCDDIS) LCD Controller Clock Reset */\r
+#define LCDC_LCDDIS_SYNCRST (0x1u << 9) /**< \brief (LCDC_LCDDIS) LCD Controller Horizontal and Vertical Synchronization Reset */\r
+#define LCDC_LCDDIS_DISPRST (0x1u << 10) /**< \brief (LCDC_LCDDIS) LCD Controller DISP Signal Reset */\r
+#define LCDC_LCDDIS_PWMRST (0x1u << 11) /**< \brief (LCDC_LCDDIS) LCD Controller PWM Reset */\r
+/* -------- LCDC_LCDSR : (LCDC Offset: 0x00000028) LCD Controller Status Register -------- */\r
+#define LCDC_LCDSR_CLKSTS (0x1u << 0) /**< \brief (LCDC_LCDSR) Clock Status */\r
+#define LCDC_LCDSR_LCDSTS (0x1u << 1) /**< \brief (LCDC_LCDSR) LCD Controller Synchronization status */\r
+#define LCDC_LCDSR_DISPSTS (0x1u << 2) /**< \brief (LCDC_LCDSR) LCD Controller DISP Signal Status */\r
+#define LCDC_LCDSR_PWMSTS (0x1u << 3) /**< \brief (LCDC_LCDSR) LCD Controller PWM Signal Status */\r
+#define LCDC_LCDSR_SIPSTS (0x1u << 4) /**< \brief (LCDC_LCDSR) Synchronization In Progress */\r
+/* -------- LCDC_LCDIER : (LCDC Offset: 0x0000002C) LCD Controller Interrupt Enable Register -------- */\r
+#define LCDC_LCDIER_SOFIE (0x1u << 0) /**< \brief (LCDC_LCDIER) Start of Frame Interrupt Enable Register */\r
+#define LCDC_LCDIER_DISIE (0x1u << 1) /**< \brief (LCDC_LCDIER) LCD Disable Interrupt Enable Register */\r
+#define LCDC_LCDIER_DISPIE (0x1u << 2) /**< \brief (LCDC_LCDIER) Power UP/Down Sequence Terminated Interrupt Enable Register */\r
+#define LCDC_LCDIER_FIFOERRIE (0x1u << 4) /**< \brief (LCDC_LCDIER) Output FIFO Error Interrupt Enable Register */\r
+#define LCDC_LCDIER_BASEIE (0x1u << 8) /**< \brief (LCDC_LCDIER) Base Layer Interrupt Enable Register */\r
+#define LCDC_LCDIER_OVR1IE (0x1u << 9) /**< \brief (LCDC_LCDIER) Overlay 1 Interrupt Enable Register */\r
+#define LCDC_LCDIER_OVR2IE (0x1u << 10) /**< \brief (LCDC_LCDIER) Overlay 2 Interrupt Enable Register */\r
+#define LCDC_LCDIER_HEOIE (0x1u << 11) /**< \brief (LCDC_LCDIER) High End Overlay Interrupt Enable Register */\r
+#define LCDC_LCDIER_PPIE (0x1u << 13) /**< \brief (LCDC_LCDIER) Post Processing Interrupt Enable Register */\r
+/* -------- LCDC_LCDIDR : (LCDC Offset: 0x00000030) LCD Controller Interrupt Disable Register -------- */\r
+#define LCDC_LCDIDR_SOFID (0x1u << 0) /**< \brief (LCDC_LCDIDR) Start of Frame Interrupt Disable Register */\r
+#define LCDC_LCDIDR_DISID (0x1u << 1) /**< \brief (LCDC_LCDIDR) LCD Disable Interrupt Disable Register */\r
+#define LCDC_LCDIDR_DISPID (0x1u << 2) /**< \brief (LCDC_LCDIDR) Power UP/Down Sequence Terminated Interrupt Disable Register */\r
+#define LCDC_LCDIDR_FIFOERRID (0x1u << 4) /**< \brief (LCDC_LCDIDR) Output FIFO Error Interrupt Disable Register */\r
+#define LCDC_LCDIDR_BASEID (0x1u << 8) /**< \brief (LCDC_LCDIDR) Base Layer Interrupt Disable Register */\r
+#define LCDC_LCDIDR_OVR1ID (0x1u << 9) /**< \brief (LCDC_LCDIDR) Overlay 1 Interrupt Disable Register */\r
+#define LCDC_LCDIDR_OVR2ID (0x1u << 10) /**< \brief (LCDC_LCDIDR) Overlay 2 Interrupt Disable Register */\r
+#define LCDC_LCDIDR_HEOID (0x1u << 11) /**< \brief (LCDC_LCDIDR) High End Overlay Interrupt Disable Register */\r
+#define LCDC_LCDIDR_PPID (0x1u << 13) /**< \brief (LCDC_LCDIDR) Post Processing Interrupt Disable Register */\r
+/* -------- LCDC_LCDIMR : (LCDC Offset: 0x00000034) LCD Controller Interrupt Mask Register -------- */\r
+#define LCDC_LCDIMR_SOFIM (0x1u << 0) /**< \brief (LCDC_LCDIMR) Start of Frame Interrupt Mask Register */\r
+#define LCDC_LCDIMR_DISIM (0x1u << 1) /**< \brief (LCDC_LCDIMR) LCD Disable Interrupt Mask Register */\r
+#define LCDC_LCDIMR_DISPIM (0x1u << 2) /**< \brief (LCDC_LCDIMR) Power UP/Down Sequence Terminated Interrupt Mask Register */\r
+#define LCDC_LCDIMR_FIFOERRIM (0x1u << 4) /**< \brief (LCDC_LCDIMR) Output FIFO Error Interrupt Mask Register */\r
+#define LCDC_LCDIMR_BASEIM (0x1u << 8) /**< \brief (LCDC_LCDIMR) Base Layer Interrupt Mask Register */\r
+#define LCDC_LCDIMR_OVR1IM (0x1u << 9) /**< \brief (LCDC_LCDIMR) Overlay 1 Interrupt Mask Register */\r
+#define LCDC_LCDIMR_OVR2IM (0x1u << 10) /**< \brief (LCDC_LCDIMR) Overlay 2 Interrupt Mask Register */\r
+#define LCDC_LCDIMR_HEOIM (0x1u << 11) /**< \brief (LCDC_LCDIMR) High End Overlay Interrupt Mask Register */\r
+#define LCDC_LCDIMR_PPIM (0x1u << 13) /**< \brief (LCDC_LCDIMR) Post Processing Interrupt Mask Register */\r
+/* -------- LCDC_LCDISR : (LCDC Offset: 0x00000038) LCD Controller Interrupt Status Register -------- */\r
+#define LCDC_LCDISR_SOF (0x1u << 0) /**< \brief (LCDC_LCDISR) Start of Frame Interrupt Status Register */\r
+#define LCDC_LCDISR_DIS (0x1u << 1) /**< \brief (LCDC_LCDISR) LCD Disable Interrupt Status Register */\r
+#define LCDC_LCDISR_DISP (0x1u << 2) /**< \brief (LCDC_LCDISR) Power-up/Power-down Sequence Terminated Interrupt Status Register */\r
+#define LCDC_LCDISR_FIFOERR (0x1u << 4) /**< \brief (LCDC_LCDISR) Output FIFO Error */\r
+#define LCDC_LCDISR_BASE (0x1u << 8) /**< \brief (LCDC_LCDISR) Base Layer Raw Interrupt Status Register */\r
+#define LCDC_LCDISR_OVR1 (0x1u << 9) /**< \brief (LCDC_LCDISR) Overlay 1 Raw Interrupt Status Register */\r
+#define LCDC_LCDISR_OVR2 (0x1u << 10) /**< \brief (LCDC_LCDISR) Overlay 2 Raw Interrupt Status Register */\r
+#define LCDC_LCDISR_HEO (0x1u << 11) /**< \brief (LCDC_LCDISR) High End Overlay Raw Interrupt Status Register */\r
+#define LCDC_LCDISR_PP (0x1u << 13) /**< \brief (LCDC_LCDISR) Post Processing Raw Interrupt Status Register */\r
+/* -------- LCDC_ATTR : (LCDC Offset: 0x0000003C) LCD Controller Attribute Register -------- */\r
+#define LCDC_ATTR_BASE (0x1u << 0) /**< \brief (LCDC_ATTR) Base Layer Update Attribute Register */\r
+#define LCDC_ATTR_OVR1 (0x1u << 1) /**< \brief (LCDC_ATTR) Overlay 1 Update Attribute Register */\r
+#define LCDC_ATTR_OVR2 (0x1u << 2) /**< \brief (LCDC_ATTR) Overlay 2 Update Attribute Register */\r
+#define LCDC_ATTR_HEO (0x1u << 3) /**< \brief (LCDC_ATTR) High End Overlay Update Attribute Register */\r
+#define LCDC_ATTR_PP (0x1u << 5) /**< \brief (LCDC_ATTR) Post-Processing Update Attribute Register */\r
+#define LCDC_ATTR_BASEA2Q (0x1u << 8) /**< \brief (LCDC_ATTR) Base Layer Update Add To Queue */\r
+#define LCDC_ATTR_OVR1A2Q (0x1u << 9) /**< \brief (LCDC_ATTR) Overlay 1 Update Add To Queue */\r
+#define LCDC_ATTR_OVR2A2Q (0x1u << 10) /**< \brief (LCDC_ATTR) Overlay 2 Update Add to Queue */\r
+#define LCDC_ATTR_HEOA2Q (0x1u << 11) /**< \brief (LCDC_ATTR) High End Overlay Update Add To Queue */\r
+#define LCDC_ATTR_PPA2Q (0x1u << 13) /**< \brief (LCDC_ATTR) Post-Processing Update Add To Queue */\r
+/* -------- LCDC_BASECHER : (LCDC Offset: 0x00000040) Base Layer Channel Enable Register -------- */\r
+#define LCDC_BASECHER_CHEN (0x1u << 0) /**< \brief (LCDC_BASECHER) Channel Enable Register */\r
+#define LCDC_BASECHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_BASECHER) Update Overlay Attributes Enable Register */\r
+#define LCDC_BASECHER_A2QEN (0x1u << 2) /**< \brief (LCDC_BASECHER) Add To Queue Enable Register */\r
+/* -------- LCDC_BASECHDR : (LCDC Offset: 0x00000044) Base Layer Channel Disable Register -------- */\r
+#define LCDC_BASECHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_BASECHDR) Channel Disable Register */\r
+#define LCDC_BASECHDR_CHRST (0x1u << 8) /**< \brief (LCDC_BASECHDR) Channel Reset Register */\r
+/* -------- LCDC_BASECHSR : (LCDC Offset: 0x00000048) Base Layer Channel Status Register -------- */\r
+#define LCDC_BASECHSR_CHSR (0x1u << 0) /**< \brief (LCDC_BASECHSR) Channel Status Register */\r
+#define LCDC_BASECHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_BASECHSR) Update Overlay Attributes In Progress Status Register */\r
+#define LCDC_BASECHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_BASECHSR) Add To Queue Status Register */\r
+/* -------- LCDC_BASEIER : (LCDC Offset: 0x0000004C) Base Layer Interrupt Enable Register -------- */\r
+#define LCDC_BASEIER_DMA (0x1u << 2) /**< \brief (LCDC_BASEIER) End of DMA Transfer Interrupt Enable Register */\r
+#define LCDC_BASEIER_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIER) Descriptor Loaded Interrupt Enable Register */\r
+#define LCDC_BASEIER_ADD (0x1u << 4) /**< \brief (LCDC_BASEIER) Head Descriptor Loaded Interrupt Enable Register */\r
+#define LCDC_BASEIER_DONE (0x1u << 5) /**< \brief (LCDC_BASEIER) End of List Interrupt Enable Register */\r
+#define LCDC_BASEIER_OVR (0x1u << 6) /**< \brief (LCDC_BASEIER) Overflow Interrupt Enable Register */\r
+/* -------- LCDC_BASEIDR : (LCDC Offset: 0x00000050) Base Layer Interrupt Disabled Register -------- */\r
+#define LCDC_BASEIDR_DMA (0x1u << 2) /**< \brief (LCDC_BASEIDR) End of DMA Transfer Interrupt Disable Register */\r
+#define LCDC_BASEIDR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIDR) Descriptor Loaded Interrupt Disable Register */\r
+#define LCDC_BASEIDR_ADD (0x1u << 4) /**< \brief (LCDC_BASEIDR) Head Descriptor Loaded Interrupt Disable Register */\r
+#define LCDC_BASEIDR_DONE (0x1u << 5) /**< \brief (LCDC_BASEIDR) End of List Interrupt Disable Register */\r
+#define LCDC_BASEIDR_OVR (0x1u << 6) /**< \brief (LCDC_BASEIDR) Overflow Interrupt Disable Register */\r
+/* -------- LCDC_BASEIMR : (LCDC Offset: 0x00000054) Base Layer Interrupt Mask Register -------- */\r
+#define LCDC_BASEIMR_DMA (0x1u << 2) /**< \brief (LCDC_BASEIMR) End of DMA Transfer Interrupt Mask Register */\r
+#define LCDC_BASEIMR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIMR) Descriptor Loaded Interrupt Mask Register */\r
+#define LCDC_BASEIMR_ADD (0x1u << 4) /**< \brief (LCDC_BASEIMR) Head Descriptor Loaded Interrupt Mask Register */\r
+#define LCDC_BASEIMR_DONE (0x1u << 5) /**< \brief (LCDC_BASEIMR) End of List Interrupt Mask Register */\r
+#define LCDC_BASEIMR_OVR (0x1u << 6) /**< \brief (LCDC_BASEIMR) Overflow Interrupt Mask Register */\r
+/* -------- LCDC_BASEISR : (LCDC Offset: 0x00000058) Base Layer Interrupt Status Register -------- */\r
+#define LCDC_BASEISR_DMA (0x1u << 2) /**< \brief (LCDC_BASEISR) End of DMA Transfer */\r
+#define LCDC_BASEISR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEISR) DMA Descriptor Loaded */\r
+#define LCDC_BASEISR_ADD (0x1u << 4) /**< \brief (LCDC_BASEISR) Head Descriptor Loaded */\r
+#define LCDC_BASEISR_DONE (0x1u << 5) /**< \brief (LCDC_BASEISR) End of List Detected */\r
+#define LCDC_BASEISR_OVR (0x1u << 6) /**< \brief (LCDC_BASEISR) Overflow Detected */\r
+/* -------- LCDC_BASEHEAD : (LCDC Offset: 0x0000005C) Base DMA Head Register -------- */\r
+#define LCDC_BASEHEAD_HEAD_Pos 2\r
+#define LCDC_BASEHEAD_HEAD_Msk (0x3fffffffu << LCDC_BASEHEAD_HEAD_Pos) /**< \brief (LCDC_BASEHEAD) DMA Head Pointer */\r
+#define LCDC_BASEHEAD_HEAD(value) ((LCDC_BASEHEAD_HEAD_Msk & ((value) << LCDC_BASEHEAD_HEAD_Pos)))\r
+/* -------- LCDC_BASEADDR : (LCDC Offset: 0x00000060) Base DMA Address Register -------- */\r
+#define LCDC_BASEADDR_ADDR_Pos 0\r
+#define LCDC_BASEADDR_ADDR_Msk (0xffffffffu << LCDC_BASEADDR_ADDR_Pos) /**< \brief (LCDC_BASEADDR) DMA Transfer Start Address */\r
+#define LCDC_BASEADDR_ADDR(value) ((LCDC_BASEADDR_ADDR_Msk & ((value) << LCDC_BASEADDR_ADDR_Pos)))\r
+/* -------- LCDC_BASECTRL : (LCDC Offset: 0x00000064) Base DMA Control Register -------- */\r
+#define LCDC_BASECTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_BASECTRL) Transfer Descriptor Fetch Enable */\r
+#define LCDC_BASECTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_BASECTRL) Lookup Table Fetch Enable */\r
+#define LCDC_BASECTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_BASECTRL) End of DMA Transfer Interrupt Enable */\r
+#define LCDC_BASECTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_BASECTRL) Descriptor Loaded Interrupt Enable */\r
+#define LCDC_BASECTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_BASECTRL) Add Head Descriptor to Queue Interrupt Enable */\r
+#define LCDC_BASECTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_BASECTRL) End of List Interrupt Enable */\r
+/* -------- LCDC_BASENEXT : (LCDC Offset: 0x00000068) Base DMA Next Register -------- */\r
+#define LCDC_BASENEXT_NEXT_Pos 0\r
+#define LCDC_BASENEXT_NEXT_Msk (0xffffffffu << LCDC_BASENEXT_NEXT_Pos) /**< \brief (LCDC_BASENEXT) DMA Descriptor Next Address */\r
+#define LCDC_BASENEXT_NEXT(value) ((LCDC_BASENEXT_NEXT_Msk & ((value) << LCDC_BASENEXT_NEXT_Pos)))\r
+/* -------- LCDC_BASECFG0 : (LCDC Offset: 0x0000006C) Base Layer Configuration Register 0 -------- */\r
+#define LCDC_BASECFG0_SIF (0x1u << 0) /**< \brief (LCDC_BASECFG0) Source Interface */\r
+#define LCDC_BASECFG0_BLEN_Pos 4\r
+#define LCDC_BASECFG0_BLEN_Msk (0x3u << LCDC_BASECFG0_BLEN_Pos) /**< \brief (LCDC_BASECFG0) AHB Burst Length */\r
+#define LCDC_BASECFG0_BLEN(value) ((LCDC_BASECFG0_BLEN_Msk & ((value) << LCDC_BASECFG0_BLEN_Pos)))\r
+#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_BASECFG0_DLBO (0x1u << 8) /**< \brief (LCDC_BASECFG0) Defined Length Burst Only For Channel Bus Transaction */\r
+/* -------- LCDC_BASECFG1 : (LCDC Offset: 0x00000070) Base Layer Configuration Register 1 -------- */\r
+#define LCDC_BASECFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_BASECFG1) Color Lookup Table Mode Enable */\r
+#define LCDC_BASECFG1_RGBMODE_Pos 4\r
+#define LCDC_BASECFG1_RGBMODE_Msk (0xfu << LCDC_BASECFG1_RGBMODE_Pos) /**< \brief (LCDC_BASECFG1) RGB Mode Input Selection */\r
+#define LCDC_BASECFG1_RGBMODE(value) ((LCDC_BASECFG1_RGBMODE_Msk & ((value) << LCDC_BASECFG1_RGBMODE_Pos)))\r
+#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_BASECFG1) 12 bpp RGB 444 */\r
+#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp ARGB 4444 */\r
+#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp RGBA 4444 */\r
+#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp RGB 565 */\r
+#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp TRGB 1555 */\r
+#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_BASECFG1) 18 bpp RGB 666 */\r
+#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_BASECFG1) 18 bpp RGB 666 PACKED */\r
+#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_BASECFG1) 19 bpp TRGB 1666 */\r
+#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_BASECFG1) 19 bpp TRGB 1666 PACKED */\r
+#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_BASECFG1) 24 bpp RGB 888 */\r
+#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_BASECFG1) 24 bpp RGB 888 PACKED */\r
+#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_BASECFG1) 25 bpp TRGB 1888 */\r
+#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_BASECFG1) 32 bpp ARGB 8888 */\r
+#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_BASECFG1) 32 bpp RGBA 8888 */\r
+#define LCDC_BASECFG1_CLUTMODE_Pos 8\r
+#define LCDC_BASECFG1_CLUTMODE_Msk (0x3u << LCDC_BASECFG1_CLUTMODE_Pos) /**< \brief (LCDC_BASECFG1) Color Lookup Table Mode Input Selection */\r
+#define LCDC_BASECFG1_CLUTMODE(value) ((LCDC_BASECFG1_CLUTMODE_Msk & ((value) << LCDC_BASECFG1_CLUTMODE_Pos)))\r
+#define LCDC_BASECFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_BASECFG1) Color Lookup Table mode set to 1 bit per pixel */\r
+#define LCDC_BASECFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_BASECFG1) Color Lookup Table mode set to 2 bits per pixel */\r
+#define LCDC_BASECFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_BASECFG1) Color Lookup Table mode set to 4 bits per pixel */\r
+#define LCDC_BASECFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_BASECFG1) Color Lookup Table mode set to 8 bits per pixel */\r
+/* -------- LCDC_BASECFG2 : (LCDC Offset: 0x00000074) Base Layer Configuration Register 2 -------- */\r
+#define LCDC_BASECFG2_XSTRIDE_Pos 0\r
+#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffffu << LCDC_BASECFG2_XSTRIDE_Pos) /**< \brief (LCDC_BASECFG2) Horizontal Stride */\r
+#define LCDC_BASECFG2_XSTRIDE(value) ((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))\r
+/* -------- LCDC_BASECFG3 : (LCDC Offset: 0x00000078) Base Layer Configuration Register 3 -------- */\r
+#define LCDC_BASECFG3_BDEF_Pos 0\r
+#define LCDC_BASECFG3_BDEF_Msk (0xffu << LCDC_BASECFG3_BDEF_Pos) /**< \brief (LCDC_BASECFG3) Blue Default */\r
+#define LCDC_BASECFG3_BDEF(value) ((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))\r
+#define LCDC_BASECFG3_GDEF_Pos 8\r
+#define LCDC_BASECFG3_GDEF_Msk (0xffu << LCDC_BASECFG3_GDEF_Pos) /**< \brief (LCDC_BASECFG3) Green Default */\r
+#define LCDC_BASECFG3_GDEF(value) ((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))\r
+#define LCDC_BASECFG3_RDEF_Pos 16\r
+#define LCDC_BASECFG3_RDEF_Msk (0xffu << LCDC_BASECFG3_RDEF_Pos) /**< \brief (LCDC_BASECFG3) Red Default */\r
+#define LCDC_BASECFG3_RDEF(value) ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))\r
+/* -------- LCDC_BASECFG4 : (LCDC Offset: 0x0000007C) Base Layer Configuration Register 4 -------- */\r
+#define LCDC_BASECFG4_DMA (0x1u << 8) /**< \brief (LCDC_BASECFG4) Use DMA Data Path */\r
+#define LCDC_BASECFG4_REP (0x1u << 9) /**< \brief (LCDC_BASECFG4) Use Replication logic to expand RGB color to 24 bits */\r
+#define LCDC_BASECFG4_DISCEN (0x1u << 11) /**< \brief (LCDC_BASECFG4) Discard Area Enable */\r
+/* -------- LCDC_BASECFG5 : (LCDC Offset: 0x00000080) Base Layer Configuration Register 5 -------- */\r
+#define LCDC_BASECFG5_DISCXPOS_Pos 0\r
+#define LCDC_BASECFG5_DISCXPOS_Msk (0x7ffu << LCDC_BASECFG5_DISCXPOS_Pos) /**< \brief (LCDC_BASECFG5) Discard Area Horizontal Coordinate */\r
+#define LCDC_BASECFG5_DISCXPOS(value) ((LCDC_BASECFG5_DISCXPOS_Msk & ((value) << LCDC_BASECFG5_DISCXPOS_Pos)))\r
+#define LCDC_BASECFG5_DISCYPOS_Pos 16\r
+#define LCDC_BASECFG5_DISCYPOS_Msk (0x7ffu << LCDC_BASECFG5_DISCYPOS_Pos) /**< \brief (LCDC_BASECFG5) Discard Area Vertical Coordinate */\r
+#define LCDC_BASECFG5_DISCYPOS(value) ((LCDC_BASECFG5_DISCYPOS_Msk & ((value) << LCDC_BASECFG5_DISCYPOS_Pos)))\r
+/* -------- LCDC_BASECFG6 : (LCDC Offset: 0x00000084) Base Layer Configuration Register 6 -------- */\r
+#define LCDC_BASECFG6_DISCXSIZE_Pos 0\r
+#define LCDC_BASECFG6_DISCXSIZE_Msk (0x7ffu << LCDC_BASECFG6_DISCXSIZE_Pos) /**< \brief (LCDC_BASECFG6) Discard Area Horizontal Size */\r
+#define LCDC_BASECFG6_DISCXSIZE(value) ((LCDC_BASECFG6_DISCXSIZE_Msk & ((value) << LCDC_BASECFG6_DISCXSIZE_Pos)))\r
+#define LCDC_BASECFG6_DISCYSIZE_Pos 16\r
+#define LCDC_BASECFG6_DISCYSIZE_Msk (0x7ffu << LCDC_BASECFG6_DISCYSIZE_Pos) /**< \brief (LCDC_BASECFG6) Discard Area Vertical Size */\r
+#define LCDC_BASECFG6_DISCYSIZE(value) ((LCDC_BASECFG6_DISCYSIZE_Msk & ((value) << LCDC_BASECFG6_DISCYSIZE_Pos)))\r
+/* -------- LCDC_OVR1CHER : (LCDC Offset: 0x00000140) Overlay 1 Channel Enable Register -------- */\r
+#define LCDC_OVR1CHER_CHEN (0x1u << 0) /**< \brief (LCDC_OVR1CHER) Channel Enable Register */\r
+#define LCDC_OVR1CHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_OVR1CHER) Update Overlay Attributes Enable Register */\r
+#define LCDC_OVR1CHER_A2QEN (0x1u << 2) /**< \brief (LCDC_OVR1CHER) Add To Queue Enable Register */\r
+/* -------- LCDC_OVR1CHDR : (LCDC Offset: 0x00000144) Overlay 1 Channel Disable Register -------- */\r
+#define LCDC_OVR1CHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_OVR1CHDR) Channel Disable Register */\r
+#define LCDC_OVR1CHDR_CHRST (0x1u << 8) /**< \brief (LCDC_OVR1CHDR) Channel Reset Register */\r
+/* -------- LCDC_OVR1CHSR : (LCDC Offset: 0x00000148) Overlay 1 Channel Status Register -------- */\r
+#define LCDC_OVR1CHSR_CHSR (0x1u << 0) /**< \brief (LCDC_OVR1CHSR) Channel Status Register */\r
+#define LCDC_OVR1CHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_OVR1CHSR) Update Overlay Attributes In Progress Status Register */\r
+#define LCDC_OVR1CHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_OVR1CHSR) Add To Queue Status Register */\r
+/* -------- LCDC_OVR1IER : (LCDC Offset: 0x0000014C) Overlay 1 Interrupt Enable Register -------- */\r
+#define LCDC_OVR1IER_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IER) End of DMA Transfer Interrupt Enable Register */\r
+#define LCDC_OVR1IER_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IER) Descriptor Loaded Interrupt Enable Register */\r
+#define LCDC_OVR1IER_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IER) Head Descriptor Loaded Interrupt Enable Register */\r
+#define LCDC_OVR1IER_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IER) End of List Interrupt Enable Register */\r
+#define LCDC_OVR1IER_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IER) Overflow Interrupt Enable Register */\r
+/* -------- LCDC_OVR1IDR : (LCDC Offset: 0x00000150) Overlay 1 Interrupt Disable Register -------- */\r
+#define LCDC_OVR1IDR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IDR) End of DMA Transfer Interrupt Disable Register */\r
+#define LCDC_OVR1IDR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IDR) Descriptor Loaded Interrupt Disable Register */\r
+#define LCDC_OVR1IDR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IDR) Head Descriptor Loaded Interrupt Disable Register */\r
+#define LCDC_OVR1IDR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IDR) End of List Interrupt Disable Register */\r
+#define LCDC_OVR1IDR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IDR) Overflow Interrupt Disable Register */\r
+/* -------- LCDC_OVR1IMR : (LCDC Offset: 0x00000154) Overlay 1 Interrupt Mask Register -------- */\r
+#define LCDC_OVR1IMR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IMR) End of DMA Transfer Interrupt Mask Register */\r
+#define LCDC_OVR1IMR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IMR) Descriptor Loaded Interrupt Mask Register */\r
+#define LCDC_OVR1IMR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IMR) Head Descriptor Loaded Interrupt Mask Register */\r
+#define LCDC_OVR1IMR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IMR) End of List Interrupt Mask Register */\r
+#define LCDC_OVR1IMR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IMR) Overflow Interrupt Mask Register */\r
+/* -------- LCDC_OVR1ISR : (LCDC Offset: 0x00000158) Overlay 1 Interrupt Status Register -------- */\r
+#define LCDC_OVR1ISR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1ISR) End of DMA Transfer */\r
+#define LCDC_OVR1ISR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1ISR) DMA Descriptor Loaded */\r
+#define LCDC_OVR1ISR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1ISR) Head Descriptor Loaded */\r
+#define LCDC_OVR1ISR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1ISR) End of List Detected */\r
+#define LCDC_OVR1ISR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1ISR) Overflow Detected */\r
+/* -------- LCDC_OVR1HEAD : (LCDC Offset: 0x0000015C) Overlay 1 DMA Head Register -------- */\r
+#define LCDC_OVR1HEAD_HEAD_Pos 2\r
+#define LCDC_OVR1HEAD_HEAD_Msk (0x3fffffffu << LCDC_OVR1HEAD_HEAD_Pos) /**< \brief (LCDC_OVR1HEAD) DMA Head Pointer */\r
+#define LCDC_OVR1HEAD_HEAD(value) ((LCDC_OVR1HEAD_HEAD_Msk & ((value) << LCDC_OVR1HEAD_HEAD_Pos)))\r
+/* -------- LCDC_OVR1ADDR : (LCDC Offset: 0x00000160) Overlay 1 DMA Address Register -------- */\r
+#define LCDC_OVR1ADDR_ADDR_Pos 0\r
+#define LCDC_OVR1ADDR_ADDR_Msk (0xffffffffu << LCDC_OVR1ADDR_ADDR_Pos) /**< \brief (LCDC_OVR1ADDR) DMA Transfer Overlay 1 Address */\r
+#define LCDC_OVR1ADDR_ADDR(value) ((LCDC_OVR1ADDR_ADDR_Msk & ((value) << LCDC_OVR1ADDR_ADDR_Pos)))\r
+/* -------- LCDC_OVR1CTRL : (LCDC Offset: 0x00000164) Overlay 1 DMA Control Register -------- */\r
+#define LCDC_OVR1CTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_OVR1CTRL) Transfer Descriptor Fetch Enable */\r
+#define LCDC_OVR1CTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_OVR1CTRL) Lookup Table Fetch Enable */\r
+#define LCDC_OVR1CTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_OVR1CTRL) End of DMA Transfer Interrupt Enable */\r
+#define LCDC_OVR1CTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_OVR1CTRL) Descriptor Loaded Interrupt Enable */\r
+#define LCDC_OVR1CTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_OVR1CTRL) Add Head Descriptor to Queue Interrupt Enable */\r
+#define LCDC_OVR1CTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_OVR1CTRL) End of List Interrupt Enable */\r
+/* -------- LCDC_OVR1NEXT : (LCDC Offset: 0x00000168) Overlay 1 DMA Next Register -------- */\r
+#define LCDC_OVR1NEXT_NEXT_Pos 0\r
+#define LCDC_OVR1NEXT_NEXT_Msk (0xffffffffu << LCDC_OVR1NEXT_NEXT_Pos) /**< \brief (LCDC_OVR1NEXT) DMA Descriptor Next Address */\r
+#define LCDC_OVR1NEXT_NEXT(value) ((LCDC_OVR1NEXT_NEXT_Msk & ((value) << LCDC_OVR1NEXT_NEXT_Pos)))\r
+/* -------- LCDC_OVR1CFG0 : (LCDC Offset: 0x0000016C) Overlay 1 Configuration Register 0 -------- */\r
+#define LCDC_OVR1CFG0_SIF (0x1u << 0) /**< \brief (LCDC_OVR1CFG0) Source Interface */\r
+#define LCDC_OVR1CFG0_BLEN_Pos 4\r
+#define LCDC_OVR1CFG0_BLEN_Msk (0x3u << LCDC_OVR1CFG0_BLEN_Pos) /**< \brief (LCDC_OVR1CFG0) AHB Burst Length */\r
+#define LCDC_OVR1CFG0_BLEN(value) ((LCDC_OVR1CFG0_BLEN_Msk & ((value) << LCDC_OVR1CFG0_BLEN_Pos)))\r
+#define LCDC_OVR1CFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_OVR1CFG0_DLBO (0x1u << 8) /**< \brief (LCDC_OVR1CFG0) Defined Length Burst Only for Channel Bus Transaction. */\r
+#define LCDC_OVR1CFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_OVR1CFG0) Hardware Rotation Optimization Disable */\r
+#define LCDC_OVR1CFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_OVR1CFG0) Hardware Rotation Lock Disable */\r
+/* -------- LCDC_OVR1CFG1 : (LCDC Offset: 0x00000170) Overlay 1 Configuration Register 1 -------- */\r
+#define LCDC_OVR1CFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table Mode Enable */\r
+#define LCDC_OVR1CFG1_RGBMODE_Pos 4\r
+#define LCDC_OVR1CFG1_RGBMODE_Msk (0xfu << LCDC_OVR1CFG1_RGBMODE_Pos) /**< \brief (LCDC_OVR1CFG1) RGB Mode Input Selection */\r
+#define LCDC_OVR1CFG1_RGBMODE(value) ((LCDC_OVR1CFG1_RGBMODE_Msk & ((value) << LCDC_OVR1CFG1_RGBMODE_Pos)))\r
+#define LCDC_OVR1CFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_OVR1CFG1) 12 bpp RGB 444 */\r
+#define LCDC_OVR1CFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp ARGB 4444 */\r
+#define LCDC_OVR1CFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp RGBA 4444 */\r
+#define LCDC_OVR1CFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp RGB 565 */\r
+#define LCDC_OVR1CFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp TRGB 1555 */\r
+#define LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_OVR1CFG1) 18 bpp RGB 666 */\r
+#define LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_OVR1CFG1) 18 bpp RGB 666 PACKED */\r
+#define LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_OVR1CFG1) 19 bpp TRGB 1666 */\r
+#define LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_OVR1CFG1) 19 bpp TRGB 1666 PACKED */\r
+#define LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_OVR1CFG1) 24 bpp RGB 888 */\r
+#define LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_OVR1CFG1) 24 bpp RGB 888 PACKED */\r
+#define LCDC_OVR1CFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_OVR1CFG1) 25 bpp TRGB 1888 */\r
+#define LCDC_OVR1CFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_OVR1CFG1) 32 bpp ARGB 8888 */\r
+#define LCDC_OVR1CFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_OVR1CFG1) 32 bpp RGBA 8888 */\r
+#define LCDC_OVR1CFG1_CLUTMODE_Pos 8\r
+#define LCDC_OVR1CFG1_CLUTMODE_Msk (0x3u << LCDC_OVR1CFG1_CLUTMODE_Pos) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table Mode Input Selection */\r
+#define LCDC_OVR1CFG1_CLUTMODE(value) ((LCDC_OVR1CFG1_CLUTMODE_Msk & ((value) << LCDC_OVR1CFG1_CLUTMODE_Pos)))\r
+#define LCDC_OVR1CFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table mode set to 1 bit per pixel */\r
+#define LCDC_OVR1CFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table mode set to 2 bits per pixel */\r
+#define LCDC_OVR1CFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table mode set to 4 bits per pixel */\r
+#define LCDC_OVR1CFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table mode set to 8 bits per pixel */\r
+/* -------- LCDC_OVR1CFG2 : (LCDC Offset: 0x00000174) Overlay 1 Configuration Register 2 -------- */\r
+#define LCDC_OVR1CFG2_XPOS_Pos 0\r
+#define LCDC_OVR1CFG2_XPOS_Msk (0x7ffu << LCDC_OVR1CFG2_XPOS_Pos) /**< \brief (LCDC_OVR1CFG2) Horizontal Window Position */\r
+#define LCDC_OVR1CFG2_XPOS(value) ((LCDC_OVR1CFG2_XPOS_Msk & ((value) << LCDC_OVR1CFG2_XPOS_Pos)))\r
+#define LCDC_OVR1CFG2_YPOS_Pos 16\r
+#define LCDC_OVR1CFG2_YPOS_Msk (0x7ffu << LCDC_OVR1CFG2_YPOS_Pos) /**< \brief (LCDC_OVR1CFG2) Vertical Window Position */\r
+#define LCDC_OVR1CFG2_YPOS(value) ((LCDC_OVR1CFG2_YPOS_Msk & ((value) << LCDC_OVR1CFG2_YPOS_Pos)))\r
+/* -------- LCDC_OVR1CFG3 : (LCDC Offset: 0x00000178) Overlay 1 Configuration Register 3 -------- */\r
+#define LCDC_OVR1CFG3_XSIZE_Pos 0\r
+#define LCDC_OVR1CFG3_XSIZE_Msk (0x7ffu << LCDC_OVR1CFG3_XSIZE_Pos) /**< \brief (LCDC_OVR1CFG3) Horizontal Window Size */\r
+#define LCDC_OVR1CFG3_XSIZE(value) ((LCDC_OVR1CFG3_XSIZE_Msk & ((value) << LCDC_OVR1CFG3_XSIZE_Pos)))\r
+#define LCDC_OVR1CFG3_YSIZE_Pos 16\r
+#define LCDC_OVR1CFG3_YSIZE_Msk (0x7ffu << LCDC_OVR1CFG3_YSIZE_Pos) /**< \brief (LCDC_OVR1CFG3) Vertical Window Size */\r
+#define LCDC_OVR1CFG3_YSIZE(value) ((LCDC_OVR1CFG3_YSIZE_Msk & ((value) << LCDC_OVR1CFG3_YSIZE_Pos)))\r
+/* -------- LCDC_OVR1CFG4 : (LCDC Offset: 0x0000017C) Overlay 1 Configuration Register 4 -------- */\r
+#define LCDC_OVR1CFG4_XSTRIDE_Pos 0\r
+#define LCDC_OVR1CFG4_XSTRIDE_Msk (0xffffffffu << LCDC_OVR1CFG4_XSTRIDE_Pos) /**< \brief (LCDC_OVR1CFG4) Horizontal Stride */\r
+#define LCDC_OVR1CFG4_XSTRIDE(value) ((LCDC_OVR1CFG4_XSTRIDE_Msk & ((value) << LCDC_OVR1CFG4_XSTRIDE_Pos)))\r
+/* -------- LCDC_OVR1CFG5 : (LCDC Offset: 0x00000180) Overlay 1 Configuration Register 5 -------- */\r
+#define LCDC_OVR1CFG5_PSTRIDE_Pos 0\r
+#define LCDC_OVR1CFG5_PSTRIDE_Msk (0xffffffffu << LCDC_OVR1CFG5_PSTRIDE_Pos) /**< \brief (LCDC_OVR1CFG5) Pixel Stride */\r
+#define LCDC_OVR1CFG5_PSTRIDE(value) ((LCDC_OVR1CFG5_PSTRIDE_Msk & ((value) << LCDC_OVR1CFG5_PSTRIDE_Pos)))\r
+/* -------- LCDC_OVR1CFG6 : (LCDC Offset: 0x00000184) Overlay 1 Configuration Register 6 -------- */\r
+#define LCDC_OVR1CFG6_BDEF_Pos 0\r
+#define LCDC_OVR1CFG6_BDEF_Msk (0xffu << LCDC_OVR1CFG6_BDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Blue Default */\r
+#define LCDC_OVR1CFG6_BDEF(value) ((LCDC_OVR1CFG6_BDEF_Msk & ((value) << LCDC_OVR1CFG6_BDEF_Pos)))\r
+#define LCDC_OVR1CFG6_GDEF_Pos 8\r
+#define LCDC_OVR1CFG6_GDEF_Msk (0xffu << LCDC_OVR1CFG6_GDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Green Default */\r
+#define LCDC_OVR1CFG6_GDEF(value) ((LCDC_OVR1CFG6_GDEF_Msk & ((value) << LCDC_OVR1CFG6_GDEF_Pos)))\r
+#define LCDC_OVR1CFG6_RDEF_Pos 16\r
+#define LCDC_OVR1CFG6_RDEF_Msk (0xffu << LCDC_OVR1CFG6_RDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Red Default */\r
+#define LCDC_OVR1CFG6_RDEF(value) ((LCDC_OVR1CFG6_RDEF_Msk & ((value) << LCDC_OVR1CFG6_RDEF_Pos)))\r
+/* -------- LCDC_OVR1CFG7 : (LCDC Offset: 0x00000188) Overlay 1 Configuration Register 7 -------- */\r
+#define LCDC_OVR1CFG7_BKEY_Pos 0\r
+#define LCDC_OVR1CFG7_BKEY_Msk (0xffu << LCDC_OVR1CFG7_BKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Blue Color Component Chroma Key */\r
+#define LCDC_OVR1CFG7_BKEY(value) ((LCDC_OVR1CFG7_BKEY_Msk & ((value) << LCDC_OVR1CFG7_BKEY_Pos)))\r
+#define LCDC_OVR1CFG7_GKEY_Pos 8\r
+#define LCDC_OVR1CFG7_GKEY_Msk (0xffu << LCDC_OVR1CFG7_GKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Green Color Component Chroma Key */\r
+#define LCDC_OVR1CFG7_GKEY(value) ((LCDC_OVR1CFG7_GKEY_Msk & ((value) << LCDC_OVR1CFG7_GKEY_Pos)))\r
+#define LCDC_OVR1CFG7_RKEY_Pos 16\r
+#define LCDC_OVR1CFG7_RKEY_Msk (0xffu << LCDC_OVR1CFG7_RKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Red Color Component Chroma Key */\r
+#define LCDC_OVR1CFG7_RKEY(value) ((LCDC_OVR1CFG7_RKEY_Msk & ((value) << LCDC_OVR1CFG7_RKEY_Pos)))\r
+/* -------- LCDC_OVR1CFG8 : (LCDC Offset: 0x0000018C) Overlay 1 Configuration Register 8 -------- */\r
+#define LCDC_OVR1CFG8_BMASK_Pos 0\r
+#define LCDC_OVR1CFG8_BMASK_Msk (0xffu << LCDC_OVR1CFG8_BMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Blue Color Component Chroma Key Mask */\r
+#define LCDC_OVR1CFG8_BMASK(value) ((LCDC_OVR1CFG8_BMASK_Msk & ((value) << LCDC_OVR1CFG8_BMASK_Pos)))\r
+#define LCDC_OVR1CFG8_GMASK_Pos 8\r
+#define LCDC_OVR1CFG8_GMASK_Msk (0xffu << LCDC_OVR1CFG8_GMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Green Color Component Chroma Key Mask */\r
+#define LCDC_OVR1CFG8_GMASK(value) ((LCDC_OVR1CFG8_GMASK_Msk & ((value) << LCDC_OVR1CFG8_GMASK_Pos)))\r
+#define LCDC_OVR1CFG8_RMASK_Pos 16\r
+#define LCDC_OVR1CFG8_RMASK_Msk (0xffu << LCDC_OVR1CFG8_RMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Red Color Component Chroma Key Mask */\r
+#define LCDC_OVR1CFG8_RMASK(value) ((LCDC_OVR1CFG8_RMASK_Msk & ((value) << LCDC_OVR1CFG8_RMASK_Pos)))\r
+/* -------- LCDC_OVR1CFG9 : (LCDC Offset: 0x00000190) Overlay 1 Configuration Register 9 -------- */\r
+#define LCDC_OVR1CFG9_CRKEY (0x1u << 0) /**< \brief (LCDC_OVR1CFG9) Blender Chroma Key Enable */\r
+#define LCDC_OVR1CFG9_INV (0x1u << 1) /**< \brief (LCDC_OVR1CFG9) Blender Inverted Blender Output Enable */\r
+#define LCDC_OVR1CFG9_ITER2BL (0x1u << 2) /**< \brief (LCDC_OVR1CFG9) Blender Iterated Color Enable */\r
+#define LCDC_OVR1CFG9_ITER (0x1u << 3) /**< \brief (LCDC_OVR1CFG9) Blender Use Iterated Color */\r
+#define LCDC_OVR1CFG9_REVALPHA (0x1u << 4) /**< \brief (LCDC_OVR1CFG9) Blender Reverse Alpha */\r
+#define LCDC_OVR1CFG9_GAEN (0x1u << 5) /**< \brief (LCDC_OVR1CFG9) Blender Global Alpha Enable */\r
+#define LCDC_OVR1CFG9_LAEN (0x1u << 6) /**< \brief (LCDC_OVR1CFG9) Blender Local Alpha Enable */\r
+#define LCDC_OVR1CFG9_OVR (0x1u << 7) /**< \brief (LCDC_OVR1CFG9) Blender Overlay Layer Enable */\r
+#define LCDC_OVR1CFG9_DMA (0x1u << 8) /**< \brief (LCDC_OVR1CFG9) Blender DMA Layer Enable */\r
+#define LCDC_OVR1CFG9_REP (0x1u << 9) /**< \brief (LCDC_OVR1CFG9) Use Replication logic to expand RGB color to 24 bits */\r
+#define LCDC_OVR1CFG9_DSTKEY (0x1u << 10) /**< \brief (LCDC_OVR1CFG9) Destination Chroma Keying */\r
+#define LCDC_OVR1CFG9_GA_Pos 16\r
+#define LCDC_OVR1CFG9_GA_Msk (0xffu << LCDC_OVR1CFG9_GA_Pos) /**< \brief (LCDC_OVR1CFG9) Blender Global Alpha */\r
+#define LCDC_OVR1CFG9_GA(value) ((LCDC_OVR1CFG9_GA_Msk & ((value) << LCDC_OVR1CFG9_GA_Pos)))\r
+/* -------- LCDC_OVR2CHER : (LCDC Offset: 0x00000240) Overlay 2 Channel Enable Register -------- */\r
+#define LCDC_OVR2CHER_CHEN (0x1u << 0) /**< \brief (LCDC_OVR2CHER) Channel Enable Register */\r
+#define LCDC_OVR2CHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_OVR2CHER) Update Overlay Attributes Enable Register */\r
+#define LCDC_OVR2CHER_A2QEN (0x1u << 2) /**< \brief (LCDC_OVR2CHER) Add To Queue Enable Register */\r
+/* -------- LCDC_OVR2CHDR : (LCDC Offset: 0x00000244) Overlay 2 Channel Disable Register -------- */\r
+#define LCDC_OVR2CHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_OVR2CHDR) Channel Disable Register */\r
+#define LCDC_OVR2CHDR_CHRST (0x1u << 8) /**< \brief (LCDC_OVR2CHDR) Channel Reset Register */\r
+/* -------- LCDC_OVR2CHSR : (LCDC Offset: 0x00000248) Overlay 2 Channel Status Register -------- */\r
+#define LCDC_OVR2CHSR_CHSR (0x1u << 0) /**< \brief (LCDC_OVR2CHSR) Channel Status Register */\r
+#define LCDC_OVR2CHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_OVR2CHSR) Update Overlay Attributes In Progress Status Register */\r
+#define LCDC_OVR2CHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_OVR2CHSR) Add To Queue Status Register */\r
+/* -------- LCDC_OVR2IER : (LCDC Offset: 0x0000024C) Overlay 2 Interrupt Enable Register -------- */\r
+#define LCDC_OVR2IER_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IER) End of DMA Transfer Interrupt Enable Register */\r
+#define LCDC_OVR2IER_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IER) Descriptor Loaded Interrupt Enable Register */\r
+#define LCDC_OVR2IER_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IER) Head Descriptor Loaded Interrupt Enable Register */\r
+#define LCDC_OVR2IER_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IER) End of List Interrupt Enable Register */\r
+#define LCDC_OVR2IER_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IER) Overflow Interrupt Enable Register */\r
+/* -------- LCDC_OVR2IDR : (LCDC Offset: 0x00000250) Overlay 2 Interrupt Disable Register -------- */\r
+#define LCDC_OVR2IDR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IDR) End of DMA Transfer Interrupt Disable Register */\r
+#define LCDC_OVR2IDR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IDR) Descriptor Loaded Interrupt Disable Register */\r
+#define LCDC_OVR2IDR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IDR) Head Descriptor Loaded Interrupt Disable Register */\r
+#define LCDC_OVR2IDR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IDR) End of List Interrupt Disable Register */\r
+#define LCDC_OVR2IDR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IDR) Overflow Interrupt Disable Register */\r
+/* -------- LCDC_OVR2IMR : (LCDC Offset: 0x00000254) Overlay 2 Interrupt Mask Register -------- */\r
+#define LCDC_OVR2IMR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IMR) End of DMA Transfer Interrupt Mask Register */\r
+#define LCDC_OVR2IMR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IMR) Descriptor Loaded Interrupt Mask Register */\r
+#define LCDC_OVR2IMR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IMR) Head Descriptor Loaded Interrupt Mask Register */\r
+#define LCDC_OVR2IMR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IMR) End of List Interrupt Mask Register */\r
+#define LCDC_OVR2IMR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IMR) Overflow Interrupt Mask Register */\r
+/* -------- LCDC_OVR2ISR : (LCDC Offset: 0x00000258) Overlay 2 Interrupt Status Register -------- */\r
+#define LCDC_OVR2ISR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2ISR) End of DMA Transfer */\r
+#define LCDC_OVR2ISR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2ISR) DMA Descriptor Loaded */\r
+#define LCDC_OVR2ISR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2ISR) Head Descriptor Loaded */\r
+#define LCDC_OVR2ISR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2ISR) End of List Detected */\r
+#define LCDC_OVR2ISR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2ISR) Overflow Detected */\r
+/* -------- LCDC_OVR2HEAD : (LCDC Offset: 0x0000025C) Overlay 2 DMA Head Register -------- */\r
+#define LCDC_OVR2HEAD_HEAD_Pos 2\r
+#define LCDC_OVR2HEAD_HEAD_Msk (0x3fffffffu << LCDC_OVR2HEAD_HEAD_Pos) /**< \brief (LCDC_OVR2HEAD) DMA Head Pointer */\r
+#define LCDC_OVR2HEAD_HEAD(value) ((LCDC_OVR2HEAD_HEAD_Msk & ((value) << LCDC_OVR2HEAD_HEAD_Pos)))\r
+/* -------- LCDC_OVR2ADDR : (LCDC Offset: 0x00000260) Overlay 2 DMA Address Register -------- */\r
+#define LCDC_OVR2ADDR_ADDR_Pos 0\r
+#define LCDC_OVR2ADDR_ADDR_Msk (0xffffffffu << LCDC_OVR2ADDR_ADDR_Pos) /**< \brief (LCDC_OVR2ADDR) DMA Transfer Overlay 2 Address */\r
+#define LCDC_OVR2ADDR_ADDR(value) ((LCDC_OVR2ADDR_ADDR_Msk & ((value) << LCDC_OVR2ADDR_ADDR_Pos)))\r
+/* -------- LCDC_OVR2CTRL : (LCDC Offset: 0x00000264) Overlay 2 DMA Control Register -------- */\r
+#define LCDC_OVR2CTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_OVR2CTRL) Transfer Descriptor Fetch Enable */\r
+#define LCDC_OVR2CTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_OVR2CTRL) Lookup Table Fetch Enable */\r
+#define LCDC_OVR2CTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_OVR2CTRL) End of DMA Transfer Interrupt Enable */\r
+#define LCDC_OVR2CTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_OVR2CTRL) Descriptor Loaded Interrupt Enable */\r
+#define LCDC_OVR2CTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_OVR2CTRL) Add Head Descriptor to Queue Interrupt Enable */\r
+#define LCDC_OVR2CTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_OVR2CTRL) End of List Interrupt Enable */\r
+/* -------- LCDC_OVR2NEXT : (LCDC Offset: 0x00000268) Overlay 2 DMA Next Register -------- */\r
+#define LCDC_OVR2NEXT_NEXT_Pos 0\r
+#define LCDC_OVR2NEXT_NEXT_Msk (0xffffffffu << LCDC_OVR2NEXT_NEXT_Pos) /**< \brief (LCDC_OVR2NEXT) DMA Descriptor Next Address */\r
+#define LCDC_OVR2NEXT_NEXT(value) ((LCDC_OVR2NEXT_NEXT_Msk & ((value) << LCDC_OVR2NEXT_NEXT_Pos)))\r
+/* -------- LCDC_OVR2CFG0 : (LCDC Offset: 0x0000026C) Overlay 2 Configuration Register 0 -------- */\r
+#define LCDC_OVR2CFG0_BLEN_Pos 4\r
+#define LCDC_OVR2CFG0_BLEN_Msk (0x3u << LCDC_OVR2CFG0_BLEN_Pos) /**< \brief (LCDC_OVR2CFG0) AHB Burst Length */\r
+#define LCDC_OVR2CFG0_BLEN(value) ((LCDC_OVR2CFG0_BLEN_Msk & ((value) << LCDC_OVR2CFG0_BLEN_Pos)))\r
+#define LCDC_OVR2CFG0_BLEN_AHB_SINGLE (0x0u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_OVR2CFG0_BLEN_AHB_INCR4 (0x1u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_OVR2CFG0_BLEN_AHB_INCR8 (0x2u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_OVR2CFG0_BLEN_AHB_INCR16 (0x3u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_OVR2CFG0_DLBO (0x1u << 8) /**< \brief (LCDC_OVR2CFG0) Defined Length Burst Only For Channel Bus Transaction. */\r
+#define LCDC_OVR2CFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_OVR2CFG0) Hardware Rotation Optimization Disable */\r
+#define LCDC_OVR2CFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_OVR2CFG0) Hardware Rotation Lock Disable */\r
+/* -------- LCDC_OVR2CFG1 : (LCDC Offset: 0x00000270) Overlay 2 Configuration Register 1 -------- */\r
+#define LCDC_OVR2CFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table Mode Enable */\r
+#define LCDC_OVR2CFG1_RGBMODE_Pos 4\r
+#define LCDC_OVR2CFG1_RGBMODE_Msk (0xfu << LCDC_OVR2CFG1_RGBMODE_Pos) /**< \brief (LCDC_OVR2CFG1) RGB Mode Input Selection */\r
+#define LCDC_OVR2CFG1_RGBMODE(value) ((LCDC_OVR2CFG1_RGBMODE_Msk & ((value) << LCDC_OVR2CFG1_RGBMODE_Pos)))\r
+#define LCDC_OVR2CFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_OVR2CFG1) 12 bpp RGB 444 */\r
+#define LCDC_OVR2CFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp ARGB 4444 */\r
+#define LCDC_OVR2CFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp RGBA 4444 */\r
+#define LCDC_OVR2CFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp RGB 565 */\r
+#define LCDC_OVR2CFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp TRGB 1555 */\r
+#define LCDC_OVR2CFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_OVR2CFG1) 18 bpp RGB 666 */\r
+#define LCDC_OVR2CFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_OVR2CFG1) 18 bpp RGB 666 PACKED */\r
+#define LCDC_OVR2CFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_OVR2CFG1) 19 bpp TRGB 1666 */\r
+#define LCDC_OVR2CFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_OVR2CFG1) 19 bpp TRGB 1666 PACKED */\r
+#define LCDC_OVR2CFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_OVR2CFG1) 24 bpp RGB 888 */\r
+#define LCDC_OVR2CFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_OVR2CFG1) 24 bpp RGB 888 PACKED */\r
+#define LCDC_OVR2CFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_OVR2CFG1) 25 bpp TRGB 1888 */\r
+#define LCDC_OVR2CFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_OVR2CFG1) 32 bpp ARGB 8888 */\r
+#define LCDC_OVR2CFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_OVR2CFG1) 32 bpp RGBA 8888 */\r
+#define LCDC_OVR2CFG1_CLUTMODE_Pos 8\r
+#define LCDC_OVR2CFG1_CLUTMODE_Msk (0x3u << LCDC_OVR2CFG1_CLUTMODE_Pos) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table Mode Input Selection */\r
+#define LCDC_OVR2CFG1_CLUTMODE(value) ((LCDC_OVR2CFG1_CLUTMODE_Msk & ((value) << LCDC_OVR2CFG1_CLUTMODE_Pos)))\r
+#define LCDC_OVR2CFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table mode set to 1 bit per pixel */\r
+#define LCDC_OVR2CFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table mode set to 2 bits per pixel */\r
+#define LCDC_OVR2CFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table mode set to 4 bits per pixel */\r
+#define LCDC_OVR2CFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table mode set to 8 bits per pixel */\r
+/* -------- LCDC_OVR2CFG2 : (LCDC Offset: 0x00000274) Overlay 2 Configuration Register 2 -------- */\r
+#define LCDC_OVR2CFG2_XPOS_Pos 0\r
+#define LCDC_OVR2CFG2_XPOS_Msk (0x7ffu << LCDC_OVR2CFG2_XPOS_Pos) /**< \brief (LCDC_OVR2CFG2) Horizontal Window Position */\r
+#define LCDC_OVR2CFG2_XPOS(value) ((LCDC_OVR2CFG2_XPOS_Msk & ((value) << LCDC_OVR2CFG2_XPOS_Pos)))\r
+#define LCDC_OVR2CFG2_YPOS_Pos 16\r
+#define LCDC_OVR2CFG2_YPOS_Msk (0x7ffu << LCDC_OVR2CFG2_YPOS_Pos) /**< \brief (LCDC_OVR2CFG2) Vertical Window Position */\r
+#define LCDC_OVR2CFG2_YPOS(value) ((LCDC_OVR2CFG2_YPOS_Msk & ((value) << LCDC_OVR2CFG2_YPOS_Pos)))\r
+/* -------- LCDC_OVR2CFG3 : (LCDC Offset: 0x00000278) Overlay 2 Configuration Register 3 -------- */\r
+#define LCDC_OVR2CFG3_XSIZE_Pos 0\r
+#define LCDC_OVR2CFG3_XSIZE_Msk (0x7ffu << LCDC_OVR2CFG3_XSIZE_Pos) /**< \brief (LCDC_OVR2CFG3) Horizontal Window Size */\r
+#define LCDC_OVR2CFG3_XSIZE(value) ((LCDC_OVR2CFG3_XSIZE_Msk & ((value) << LCDC_OVR2CFG3_XSIZE_Pos)))\r
+#define LCDC_OVR2CFG3_YSIZE_Pos 16\r
+#define LCDC_OVR2CFG3_YSIZE_Msk (0x7ffu << LCDC_OVR2CFG3_YSIZE_Pos) /**< \brief (LCDC_OVR2CFG3) Vertical Window Size */\r
+#define LCDC_OVR2CFG3_YSIZE(value) ((LCDC_OVR2CFG3_YSIZE_Msk & ((value) << LCDC_OVR2CFG3_YSIZE_Pos)))\r
+/* -------- LCDC_OVR2CFG4 : (LCDC Offset: 0x0000027C) Overlay 2 Configuration Register 4 -------- */\r
+#define LCDC_OVR2CFG4_XSTRIDE_Pos 0\r
+#define LCDC_OVR2CFG4_XSTRIDE_Msk (0xffffffffu << LCDC_OVR2CFG4_XSTRIDE_Pos) /**< \brief (LCDC_OVR2CFG4) Horizontal Stride */\r
+#define LCDC_OVR2CFG4_XSTRIDE(value) ((LCDC_OVR2CFG4_XSTRIDE_Msk & ((value) << LCDC_OVR2CFG4_XSTRIDE_Pos)))\r
+/* -------- LCDC_OVR2CFG5 : (LCDC Offset: 0x00000280) Overlay 2 Configuration Register 5 -------- */\r
+#define LCDC_OVR2CFG5_PSTRIDE_Pos 0\r
+#define LCDC_OVR2CFG5_PSTRIDE_Msk (0xffffffffu << LCDC_OVR2CFG5_PSTRIDE_Pos) /**< \brief (LCDC_OVR2CFG5) Pixel Stride */\r
+#define LCDC_OVR2CFG5_PSTRIDE(value) ((LCDC_OVR2CFG5_PSTRIDE_Msk & ((value) << LCDC_OVR2CFG5_PSTRIDE_Pos)))\r
+/* -------- LCDC_OVR2CFG6 : (LCDC Offset: 0x00000284) Overlay 2 Configuration Register 6 -------- */\r
+#define LCDC_OVR2CFG6_BDEF_Pos 0\r
+#define LCDC_OVR2CFG6_BDEF_Msk (0xffu << LCDC_OVR2CFG6_BDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Blue Default */\r
+#define LCDC_OVR2CFG6_BDEF(value) ((LCDC_OVR2CFG6_BDEF_Msk & ((value) << LCDC_OVR2CFG6_BDEF_Pos)))\r
+#define LCDC_OVR2CFG6_GDEF_Pos 8\r
+#define LCDC_OVR2CFG6_GDEF_Msk (0xffu << LCDC_OVR2CFG6_GDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Green Default */\r
+#define LCDC_OVR2CFG6_GDEF(value) ((LCDC_OVR2CFG6_GDEF_Msk & ((value) << LCDC_OVR2CFG6_GDEF_Pos)))\r
+#define LCDC_OVR2CFG6_RDEF_Pos 16\r
+#define LCDC_OVR2CFG6_RDEF_Msk (0xffu << LCDC_OVR2CFG6_RDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Red Default */\r
+#define LCDC_OVR2CFG6_RDEF(value) ((LCDC_OVR2CFG6_RDEF_Msk & ((value) << LCDC_OVR2CFG6_RDEF_Pos)))\r
+/* -------- LCDC_OVR2CFG7 : (LCDC Offset: 0x00000288) Overlay 2 Configuration Register 7 -------- */\r
+#define LCDC_OVR2CFG7_BKEY_Pos 0\r
+#define LCDC_OVR2CFG7_BKEY_Msk (0xffu << LCDC_OVR2CFG7_BKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Blue Color Component Chroma Key */\r
+#define LCDC_OVR2CFG7_BKEY(value) ((LCDC_OVR2CFG7_BKEY_Msk & ((value) << LCDC_OVR2CFG7_BKEY_Pos)))\r
+#define LCDC_OVR2CFG7_GKEY_Pos 8\r
+#define LCDC_OVR2CFG7_GKEY_Msk (0xffu << LCDC_OVR2CFG7_GKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Green Color Component Chroma Key */\r
+#define LCDC_OVR2CFG7_GKEY(value) ((LCDC_OVR2CFG7_GKEY_Msk & ((value) << LCDC_OVR2CFG7_GKEY_Pos)))\r
+#define LCDC_OVR2CFG7_RKEY_Pos 16\r
+#define LCDC_OVR2CFG7_RKEY_Msk (0xffu << LCDC_OVR2CFG7_RKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Red Color Component Chroma Key */\r
+#define LCDC_OVR2CFG7_RKEY(value) ((LCDC_OVR2CFG7_RKEY_Msk & ((value) << LCDC_OVR2CFG7_RKEY_Pos)))\r
+/* -------- LCDC_OVR2CFG8 : (LCDC Offset: 0x0000028C) Overlay 2 Configuration Register 8 -------- */\r
+#define LCDC_OVR2CFG8_BMASK_Pos 0\r
+#define LCDC_OVR2CFG8_BMASK_Msk (0xffu << LCDC_OVR2CFG8_BMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Blue Color Component Chroma Key Mask */\r
+#define LCDC_OVR2CFG8_BMASK(value) ((LCDC_OVR2CFG8_BMASK_Msk & ((value) << LCDC_OVR2CFG8_BMASK_Pos)))\r
+#define LCDC_OVR2CFG8_GMASK_Pos 8\r
+#define LCDC_OVR2CFG8_GMASK_Msk (0xffu << LCDC_OVR2CFG8_GMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Green Color Component Chroma Key Mask */\r
+#define LCDC_OVR2CFG8_GMASK(value) ((LCDC_OVR2CFG8_GMASK_Msk & ((value) << LCDC_OVR2CFG8_GMASK_Pos)))\r
+#define LCDC_OVR2CFG8_RMASK_Pos 16\r
+#define LCDC_OVR2CFG8_RMASK_Msk (0xffu << LCDC_OVR2CFG8_RMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Red Color Component Chroma Key Mask */\r
+#define LCDC_OVR2CFG8_RMASK(value) ((LCDC_OVR2CFG8_RMASK_Msk & ((value) << LCDC_OVR2CFG8_RMASK_Pos)))\r
+/* -------- LCDC_OVR2CFG9 : (LCDC Offset: 0x00000290) Overlay 2 Configuration Register 8 -------- */\r
+#define LCDC_OVR2CFG9_CRKEY (0x1u << 0) /**< \brief (LCDC_OVR2CFG9) Blender Chroma Key Enable */\r
+#define LCDC_OVR2CFG9_INV (0x1u << 1) /**< \brief (LCDC_OVR2CFG9) Blender Inverted Blender Output Enable */\r
+#define LCDC_OVR2CFG9_ITER2BL (0x1u << 2) /**< \brief (LCDC_OVR2CFG9) Blender Iterated Color Enable */\r
+#define LCDC_OVR2CFG9_ITER (0x1u << 3) /**< \brief (LCDC_OVR2CFG9) Blender Use Iterated Color */\r
+#define LCDC_OVR2CFG9_REVALPHA (0x1u << 4) /**< \brief (LCDC_OVR2CFG9) Blender Reverse Alpha */\r
+#define LCDC_OVR2CFG9_GAEN (0x1u << 5) /**< \brief (LCDC_OVR2CFG9) Blender Global Alpha Enable */\r
+#define LCDC_OVR2CFG9_LAEN (0x1u << 6) /**< \brief (LCDC_OVR2CFG9) Blender Local Alpha Enable */\r
+#define LCDC_OVR2CFG9_OVR (0x1u << 7) /**< \brief (LCDC_OVR2CFG9) Blender Overlay Layer Enable */\r
+#define LCDC_OVR2CFG9_DMA (0x1u << 8) /**< \brief (LCDC_OVR2CFG9) Blender DMA Layer Enable */\r
+#define LCDC_OVR2CFG9_REP (0x1u << 9) /**< \brief (LCDC_OVR2CFG9) Use Replication logic to expand RGB color to 24 bits */\r
+#define LCDC_OVR2CFG9_DSTKEY (0x1u << 10) /**< \brief (LCDC_OVR2CFG9) Destination Chroma Keying */\r
+#define LCDC_OVR2CFG9_GA_Pos 16\r
+#define LCDC_OVR2CFG9_GA_Msk (0xffu << LCDC_OVR2CFG9_GA_Pos) /**< \brief (LCDC_OVR2CFG9) Blender Global Alpha */\r
+#define LCDC_OVR2CFG9_GA(value) ((LCDC_OVR2CFG9_GA_Msk & ((value) << LCDC_OVR2CFG9_GA_Pos)))\r
+/* -------- LCDC_HEOCHER : (LCDC Offset: 0x00000340) High End Overlay Channel Enable Register -------- */\r
+#define LCDC_HEOCHER_CHEN (0x1u << 0) /**< \brief (LCDC_HEOCHER) Channel Enable Register */\r
+#define LCDC_HEOCHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_HEOCHER) Update Overlay Attributes Enable Register */\r
+#define LCDC_HEOCHER_A2QEN (0x1u << 2) /**< \brief (LCDC_HEOCHER) Add To Queue Enable Register */\r
+/* -------- LCDC_HEOCHDR : (LCDC Offset: 0x00000344) High End Overlay Channel Disable Register -------- */\r
+#define LCDC_HEOCHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_HEOCHDR) Channel Disable Register */\r
+#define LCDC_HEOCHDR_CHRST (0x1u << 8) /**< \brief (LCDC_HEOCHDR) Channel Reset Register */\r
+/* -------- LCDC_HEOCHSR : (LCDC Offset: 0x00000348) High End Overlay Channel Status Register -------- */\r
+#define LCDC_HEOCHSR_CHSR (0x1u << 0) /**< \brief (LCDC_HEOCHSR) Channel Status Register */\r
+#define LCDC_HEOCHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_HEOCHSR) Update Overlay Attributes In Progress Status Register */\r
+#define LCDC_HEOCHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_HEOCHSR) Add To Queue Status Register */\r
+/* -------- LCDC_HEOIER : (LCDC Offset: 0x0000034C) High End Overlay Interrupt Enable Register -------- */\r
+#define LCDC_HEOIER_DMA (0x1u << 2) /**< \brief (LCDC_HEOIER) End of DMA Transfer Interrupt Enable Register */\r
+#define LCDC_HEOIER_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIER) Descriptor Loaded Interrupt Enable Register */\r
+#define LCDC_HEOIER_ADD (0x1u << 4) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded Interrupt Enable Register */\r
+#define LCDC_HEOIER_DONE (0x1u << 5) /**< \brief (LCDC_HEOIER) End of List Interrupt Enable Register */\r
+#define LCDC_HEOIER_OVR (0x1u << 6) /**< \brief (LCDC_HEOIER) Overflow Interrupt Enable Register */\r
+#define LCDC_HEOIER_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIER) End of DMA Transfer for U or UV Chrominance Interrupt Enable Register */\r
+#define LCDC_HEOIER_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIER) Descriptor Loaded for U or UV Chrominance Interrupt Enable Register */\r
+#define LCDC_HEOIER_UADD (0x1u << 12) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded for U or UV Chrominance Interrupt Enable Register */\r
+#define LCDC_HEOIER_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIER) End of List for U or UV Chrominance Interrupt Enable Register */\r
+#define LCDC_HEOIER_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIER) Overflow for U or UV Chrominance Interrupt Enable Register */\r
+#define LCDC_HEOIER_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIER) End of DMA for V Chrominance Transfer Interrupt Enable Register */\r
+#define LCDC_HEOIER_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIER) Descriptor Loaded for V Chrominance Interrupt Enable Register */\r
+#define LCDC_HEOIER_VADD (0x1u << 20) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded for V Chrominance Interrupt Enable Register */\r
+#define LCDC_HEOIER_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIER) End of List for V Chrominance Interrupt Enable Register */\r
+#define LCDC_HEOIER_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIER) Overflow for V Chrominance Interrupt Enable Register */\r
+/* -------- LCDC_HEOIDR : (LCDC Offset: 0x00000350) High End Overlay Interrupt Disable Register -------- */\r
+#define LCDC_HEOIDR_DMA (0x1u << 2) /**< \brief (LCDC_HEOIDR) End of DMA Transfer Interrupt Disable Register */\r
+#define LCDC_HEOIDR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIDR) Descriptor Loaded Interrupt Disable Register */\r
+#define LCDC_HEOIDR_ADD (0x1u << 4) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded Interrupt Disable Register */\r
+#define LCDC_HEOIDR_DONE (0x1u << 5) /**< \brief (LCDC_HEOIDR) End of List Interrupt Disable Register */\r
+#define LCDC_HEOIDR_OVR (0x1u << 6) /**< \brief (LCDC_HEOIDR) Overflow Interrupt Disable Register */\r
+#define LCDC_HEOIDR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIDR) End of DMA Transfer for U or UV Chrominance Component Interrupt Disable Register */\r
+#define LCDC_HEOIDR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIDR) Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register */\r
+#define LCDC_HEOIDR_UADD (0x1u << 12) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register */\r
+#define LCDC_HEOIDR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIDR) End of List Interrupt for U or UV Chrominance Component Disable Register */\r
+#define LCDC_HEOIDR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIDR) Overflow Interrupt for U or UV Chrominance Component Disable Register */\r
+#define LCDC_HEOIDR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIDR) End of DMA Transfer for V Chrominance Component Interrupt Disable Register */\r
+#define LCDC_HEOIDR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIDR) Descriptor Loaded for V Chrominance Component Interrupt Disable Register */\r
+#define LCDC_HEOIDR_VADD (0x1u << 20) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded for V Chrominance Component Interrupt Disable Register */\r
+#define LCDC_HEOIDR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIDR) End of List for V Chrominance Component Interrupt Disable Register */\r
+#define LCDC_HEOIDR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIDR) Overflow for V Chrominance Component Interrupt Disable Register */\r
+/* -------- LCDC_HEOIMR : (LCDC Offset: 0x00000354) High End Overlay Interrupt Mask Register -------- */\r
+#define LCDC_HEOIMR_DMA (0x1u << 2) /**< \brief (LCDC_HEOIMR) End of DMA Transfer Interrupt Mask Register */\r
+#define LCDC_HEOIMR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIMR) Descriptor Loaded Interrupt Mask Register */\r
+#define LCDC_HEOIMR_ADD (0x1u << 4) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded Interrupt Mask Register */\r
+#define LCDC_HEOIMR_DONE (0x1u << 5) /**< \brief (LCDC_HEOIMR) End of List Interrupt Mask Register */\r
+#define LCDC_HEOIMR_OVR (0x1u << 6) /**< \brief (LCDC_HEOIMR) Overflow Interrupt Mask Register */\r
+#define LCDC_HEOIMR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIMR) End of DMA Transfer for U or UV Chrominance Component Interrupt Mask Register */\r
+#define LCDC_HEOIMR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIMR) Descriptor Loaded for U or UV Chrominance Component Interrupt Mask Register */\r
+#define LCDC_HEOIMR_UADD (0x1u << 12) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded for U or UV Chrominance Component Mask Register */\r
+#define LCDC_HEOIMR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIMR) End of List for U or UV Chrominance Component Mask Register */\r
+#define LCDC_HEOIMR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIMR) Overflow for U Chrominance Interrupt Mask Register */\r
+#define LCDC_HEOIMR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIMR) End of DMA Transfer for V Chrominance Component Interrupt Mask Register */\r
+#define LCDC_HEOIMR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIMR) Descriptor Loaded for V Chrominance Component Interrupt Mask Register */\r
+#define LCDC_HEOIMR_VADD (0x1u << 20) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded for V Chrominance Component Mask Register */\r
+#define LCDC_HEOIMR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIMR) End of List for V Chrominance Component Mask Register */\r
+#define LCDC_HEOIMR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIMR) Overflow for V Chrominance Interrupt Mask Register */\r
+/* -------- LCDC_HEOISR : (LCDC Offset: 0x00000358) High End Overlay Interrupt Status Register -------- */\r
+#define LCDC_HEOISR_DMA (0x1u << 2) /**< \brief (LCDC_HEOISR) End of DMA Transfer */\r
+#define LCDC_HEOISR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded */\r
+#define LCDC_HEOISR_ADD (0x1u << 4) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded */\r
+#define LCDC_HEOISR_DONE (0x1u << 5) /**< \brief (LCDC_HEOISR) End of List Detected */\r
+#define LCDC_HEOISR_OVR (0x1u << 6) /**< \brief (LCDC_HEOISR) Overflow Detected */\r
+#define LCDC_HEOISR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOISR) End of DMA Transfer for U Component */\r
+#define LCDC_HEOISR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded for U Component */\r
+#define LCDC_HEOISR_UADD (0x1u << 12) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded for U Component */\r
+#define LCDC_HEOISR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOISR) End of List Detected for U Component */\r
+#define LCDC_HEOISR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOISR) Overflow Detected for U Component */\r
+#define LCDC_HEOISR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOISR) End of DMA Transfer for V Component */\r
+#define LCDC_HEOISR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded for V Component */\r
+#define LCDC_HEOISR_VADD (0x1u << 20) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded for V Component */\r
+#define LCDC_HEOISR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOISR) End of List Detected for V Component */\r
+#define LCDC_HEOISR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOISR) Overflow Detected for V Component */\r
+/* -------- LCDC_HEOHEAD : (LCDC Offset: 0x0000035C) High End Overlay DMA Head Register -------- */\r
+#define LCDC_HEOHEAD_HEAD_Pos 2\r
+#define LCDC_HEOHEAD_HEAD_Msk (0x3fffffffu << LCDC_HEOHEAD_HEAD_Pos) /**< \brief (LCDC_HEOHEAD) DMA Head Pointer */\r
+#define LCDC_HEOHEAD_HEAD(value) ((LCDC_HEOHEAD_HEAD_Msk & ((value) << LCDC_HEOHEAD_HEAD_Pos)))\r
+/* -------- LCDC_HEOADDR : (LCDC Offset: 0x00000360) High End Overlay DMA Address Register -------- */\r
+#define LCDC_HEOADDR_ADDR_Pos 0\r
+#define LCDC_HEOADDR_ADDR_Msk (0xffffffffu << LCDC_HEOADDR_ADDR_Pos) /**< \brief (LCDC_HEOADDR) DMA Transfer start Address */\r
+#define LCDC_HEOADDR_ADDR(value) ((LCDC_HEOADDR_ADDR_Msk & ((value) << LCDC_HEOADDR_ADDR_Pos)))\r
+/* -------- LCDC_HEOCTRL : (LCDC Offset: 0x00000364) High End Overlay DMA Control Register -------- */\r
+#define LCDC_HEOCTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_HEOCTRL) Transfer Descriptor Fetch Enable */\r
+#define LCDC_HEOCTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_HEOCTRL) Lookup Table Fetch Enable */\r
+#define LCDC_HEOCTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_HEOCTRL) End of DMA Transfer Interrupt Enable */\r
+#define LCDC_HEOCTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOCTRL) Descriptor Loaded Interrupt Enable */\r
+#define LCDC_HEOCTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_HEOCTRL) Add Head Descriptor to Queue Interrupt Enable */\r
+#define LCDC_HEOCTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_HEOCTRL) End of List Interrupt Enable */\r
+/* -------- LCDC_HEONEXT : (LCDC Offset: 0x00000368) High End Overlay DMA Next Register -------- */\r
+#define LCDC_HEONEXT_NEXT_Pos 0\r
+#define LCDC_HEONEXT_NEXT_Msk (0xffffffffu << LCDC_HEONEXT_NEXT_Pos) /**< \brief (LCDC_HEONEXT) DMA Descriptor Next Address */\r
+#define LCDC_HEONEXT_NEXT(value) ((LCDC_HEONEXT_NEXT_Msk & ((value) << LCDC_HEONEXT_NEXT_Pos)))\r
+/* -------- LCDC_HEOUHEAD : (LCDC Offset: 0x0000036C) High End Overlay U-UV DMA Head Register -------- */\r
+#define LCDC_HEOUHEAD_UHEAD_Pos 0\r
+#define LCDC_HEOUHEAD_UHEAD_Msk (0xffffffffu << LCDC_HEOUHEAD_UHEAD_Pos) /**< \brief (LCDC_HEOUHEAD) DMA Head Pointer */\r
+#define LCDC_HEOUHEAD_UHEAD(value) ((LCDC_HEOUHEAD_UHEAD_Msk & ((value) << LCDC_HEOUHEAD_UHEAD_Pos)))\r
+/* -------- LCDC_HEOUADDR : (LCDC Offset: 0x00000370) High End Overlay U-UV DMA Address Register -------- */\r
+#define LCDC_HEOUADDR_UADDR_Pos 0\r
+#define LCDC_HEOUADDR_UADDR_Msk (0xffffffffu << LCDC_HEOUADDR_UADDR_Pos) /**< \brief (LCDC_HEOUADDR) DMA Transfer Start Address for U or UV Chrominance */\r
+#define LCDC_HEOUADDR_UADDR(value) ((LCDC_HEOUADDR_UADDR_Msk & ((value) << LCDC_HEOUADDR_UADDR_Pos)))\r
+/* -------- LCDC_HEOUCTRL : (LCDC Offset: 0x00000374) High End Overlay U-UV DMA Control Register -------- */\r
+#define LCDC_HEOUCTRL_UDFETCH (0x1u << 0) /**< \brief (LCDC_HEOUCTRL) Transfer Descriptor Fetch Enable */\r
+#define LCDC_HEOUCTRL_UDMAIEN (0x1u << 2) /**< \brief (LCDC_HEOUCTRL) End of DMA Transfer Interrupt Enable */\r
+#define LCDC_HEOUCTRL_UDSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOUCTRL) Descriptor Loaded Interrupt Enable */\r
+#define LCDC_HEOUCTRL_UADDIEN (0x1u << 4) /**< \brief (LCDC_HEOUCTRL) Add Head Descriptor to Queue Interrupt Enable */\r
+#define LCDC_HEOUCTRL_UDONEIEN (0x1u << 5) /**< \brief (LCDC_HEOUCTRL) End of List Interrupt Enable */\r
+/* -------- LCDC_HEOUNEXT : (LCDC Offset: 0x00000378) High End Overlay U-UV DMA Next Register -------- */\r
+#define LCDC_HEOUNEXT_UNEXT_Pos 0\r
+#define LCDC_HEOUNEXT_UNEXT_Msk (0xffffffffu << LCDC_HEOUNEXT_UNEXT_Pos) /**< \brief (LCDC_HEOUNEXT) DMA Descriptor Next Address */\r
+#define LCDC_HEOUNEXT_UNEXT(value) ((LCDC_HEOUNEXT_UNEXT_Msk & ((value) << LCDC_HEOUNEXT_UNEXT_Pos)))\r
+/* -------- LCDC_HEOVHEAD : (LCDC Offset: 0x0000037C) High End Overlay V DMA Head Register -------- */\r
+#define LCDC_HEOVHEAD_VHEAD_Pos 0\r
+#define LCDC_HEOVHEAD_VHEAD_Msk (0xffffffffu << LCDC_HEOVHEAD_VHEAD_Pos) /**< \brief (LCDC_HEOVHEAD) DMA Head Pointer */\r
+#define LCDC_HEOVHEAD_VHEAD(value) ((LCDC_HEOVHEAD_VHEAD_Msk & ((value) << LCDC_HEOVHEAD_VHEAD_Pos)))\r
+/* -------- LCDC_HEOVADDR : (LCDC Offset: 0x00000380) High End Overlay V DMA Address Register -------- */\r
+#define LCDC_HEOVADDR_VADDR_Pos 0\r
+#define LCDC_HEOVADDR_VADDR_Msk (0xffffffffu << LCDC_HEOVADDR_VADDR_Pos) /**< \brief (LCDC_HEOVADDR) DMA Transfer Start Address for V Chrominance */\r
+#define LCDC_HEOVADDR_VADDR(value) ((LCDC_HEOVADDR_VADDR_Msk & ((value) << LCDC_HEOVADDR_VADDR_Pos)))\r
+/* -------- LCDC_HEOVCTRL : (LCDC Offset: 0x00000384) High End Overlay V DMA Control Register -------- */\r
+#define LCDC_HEOVCTRL_VDFETCH (0x1u << 0) /**< \brief (LCDC_HEOVCTRL) Transfer Descriptor Fetch Enable */\r
+#define LCDC_HEOVCTRL_VDMAIEN (0x1u << 2) /**< \brief (LCDC_HEOVCTRL) End of DMA Transfer Interrupt Enable */\r
+#define LCDC_HEOVCTRL_VDSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOVCTRL) Descriptor Loaded Interrupt Enable */\r
+#define LCDC_HEOVCTRL_VADDIEN (0x1u << 4) /**< \brief (LCDC_HEOVCTRL) Add Head Descriptor to Queue Interrupt Enable */\r
+#define LCDC_HEOVCTRL_VDONEIEN (0x1u << 5) /**< \brief (LCDC_HEOVCTRL) End of List Interrupt Enable */\r
+/* -------- LCDC_HEOVNEXT : (LCDC Offset: 0x00000388) High End Overlay V DMA Next Register -------- */\r
+#define LCDC_HEOVNEXT_VNEXT_Pos 0\r
+#define LCDC_HEOVNEXT_VNEXT_Msk (0xffffffffu << LCDC_HEOVNEXT_VNEXT_Pos) /**< \brief (LCDC_HEOVNEXT) DMA Descriptor Next Address */\r
+#define LCDC_HEOVNEXT_VNEXT(value) ((LCDC_HEOVNEXT_VNEXT_Msk & ((value) << LCDC_HEOVNEXT_VNEXT_Pos)))\r
+/* -------- LCDC_HEOCFG0 : (LCDC Offset: 0x0000038C) High End Overlay Configuration Register 0 -------- */\r
+#define LCDC_HEOCFG0_SIF (0x1u << 0) /**< \brief (LCDC_HEOCFG0) Source Interface */\r
+#define LCDC_HEOCFG0_BLEN_Pos 4\r
+#define LCDC_HEOCFG0_BLEN_Msk (0x3u << LCDC_HEOCFG0_BLEN_Pos) /**< \brief (LCDC_HEOCFG0) AHB Burst Length */\r
+#define LCDC_HEOCFG0_BLEN(value) ((LCDC_HEOCFG0_BLEN_Msk & ((value) << LCDC_HEOCFG0_BLEN_Pos)))\r
+#define LCDC_HEOCFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_HEOCFG0_BLENUV_Pos 6\r
+#define LCDC_HEOCFG0_BLENUV_Msk (0x3u << LCDC_HEOCFG0_BLENUV_Pos) /**< \brief (LCDC_HEOCFG0) AHB Burst Length for U-V channel */\r
+#define LCDC_HEOCFG0_BLENUV(value) ((LCDC_HEOCFG0_BLENUV_Msk & ((value) << LCDC_HEOCFG0_BLENUV_Pos)))\r
+#define LCDC_HEOCFG0_BLENUV_AHB_SINGLE (0x0u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_HEOCFG0_BLENUV_AHB_INCR4 (0x1u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_HEOCFG0_BLENUV_AHB_INCR8 (0x2u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_HEOCFG0_BLENUV_AHB_INCR16 (0x3u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_HEOCFG0_DLBO (0x1u << 8) /**< \brief (LCDC_HEOCFG0) Defined Length Burst Only For Channel Bus Transaction. */\r
+#define LCDC_HEOCFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_HEOCFG0) Hardware Rotation Optimization Disable */\r
+#define LCDC_HEOCFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_HEOCFG0) Hardware Rotation Lock Disable */\r
+/* -------- LCDC_HEOCFG1 : (LCDC Offset: 0x00000390) High End Overlay Configuration Register 1 -------- */\r
+#define LCDC_HEOCFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_HEOCFG1) Color Lookup Table Mode Enable */\r
+#define LCDC_HEOCFG1_YUVEN (0x1u << 1) /**< \brief (LCDC_HEOCFG1) YUV Color Space Enable */\r
+#define LCDC_HEOCFG1_RGBMODE_Pos 4\r
+#define LCDC_HEOCFG1_RGBMODE_Msk (0xfu << LCDC_HEOCFG1_RGBMODE_Pos) /**< \brief (LCDC_HEOCFG1) RGB Mode Input selection */\r
+#define LCDC_HEOCFG1_RGBMODE(value) ((LCDC_HEOCFG1_RGBMODE_Msk & ((value) << LCDC_HEOCFG1_RGBMODE_Pos)))\r
+#define LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_HEOCFG1) 12 bpp RGB 444 */\r
+#define LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp ARGB 4444 */\r
+#define LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp RGBA 4444 */\r
+#define LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp RGB 565 */\r
+#define LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp TRGB 1555 */\r
+#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_HEOCFG1) 18 bpp RGB 666 */\r
+#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_HEOCFG1) 18 bpp RGB 666 PACKED */\r
+#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_HEOCFG1) 19 bpp TRGB 1666 */\r
+#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_HEOCFG1) 19 bpp TRGB 1666 PACKED */\r
+#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_HEOCFG1) 24 bpp RGB 888 */\r
+#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_HEOCFG1) 24 bpp RGB 888 PACKED */\r
+#define LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_HEOCFG1) 25 bpp TRGB 1888 */\r
+#define LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_HEOCFG1) 32 bpp ARGB 8888 */\r
+#define LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_HEOCFG1) 32 bpp RGBA 8888 */\r
+#define LCDC_HEOCFG1_CLUTMODE_Pos 8\r
+#define LCDC_HEOCFG1_CLUTMODE_Msk (0x3u << LCDC_HEOCFG1_CLUTMODE_Pos) /**< \brief (LCDC_HEOCFG1) Color Lookup Table Mode Input Selection */\r
+#define LCDC_HEOCFG1_CLUTMODE(value) ((LCDC_HEOCFG1_CLUTMODE_Msk & ((value) << LCDC_HEOCFG1_CLUTMODE_Pos)))\r
+#define LCDC_HEOCFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_HEOCFG1) Color Lookup Table mode set to 1 bit per pixel */\r
+#define LCDC_HEOCFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_HEOCFG1) Color Lookup Table mode set to 2 bits per pixel */\r
+#define LCDC_HEOCFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_HEOCFG1) Color Lookup Table mode set to 4 bits per pixel */\r
+#define LCDC_HEOCFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_HEOCFG1) Color Lookup Table mode set to 8 bits per pixel */\r
+#define LCDC_HEOCFG1_YUVMODE_Pos 12\r
+#define LCDC_HEOCFG1_YUVMODE_Msk (0xfu << LCDC_HEOCFG1_YUVMODE_Pos) /**< \brief (LCDC_HEOCFG1) YUV Mode Input Selection */\r
+#define LCDC_HEOCFG1_YUVMODE(value) ((LCDC_HEOCFG1_YUVMODE_Msk & ((value) << LCDC_HEOCFG1_YUVMODE_Pos)))\r
+#define LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR (0x0u << 12) /**< \brief (LCDC_HEOCFG1) 32 bpp AYCbCr 444 */\r
+#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0 (0x1u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Cr(n)Y(n+1)Cb(n)Y(n) 422 */\r
+#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1 (0x2u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Y(n+1)Cr(n)Y(n)Cb(n) 422 */\r
+#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2 (0x3u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Cb(n)Y(+1)Cr(n)Y(n) 422 */\r
+#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3 (0x4u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Y(n+1)Cb(n)Y(n)Cr(n) 422 */\r
+#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR (0x5u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Semiplanar 422 YCbCr */\r
+#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR (0x6u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Planar 422 YCbCr */\r
+#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR (0x7u << 12) /**< \brief (LCDC_HEOCFG1) 12 bpp Semiplanar 420 YCbCr */\r
+#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR (0x8u << 12) /**< \brief (LCDC_HEOCFG1) 12 bpp Planar 420 YCbCr */\r
+#define LCDC_HEOCFG1_YUV422ROT (0x1u << 16) /**< \brief (LCDC_HEOCFG1) YUV 4:2:2 Rotation */\r
+#define LCDC_HEOCFG1_YUV422SWP (0x1u << 17) /**< \brief (LCDC_HEOCFG1) YUV 4:2:2 Swap */\r
+#define LCDC_HEOCFG1_DSCALEOPT (0x1u << 20) /**< \brief (LCDC_HEOCFG1) Down Scaling Bandwidth Optimization */\r
+/* -------- LCDC_HEOCFG2 : (LCDC Offset: 0x00000394) High End Overlay Configuration Register 2 -------- */\r
+#define LCDC_HEOCFG2_XPOS_Pos 0\r
+#define LCDC_HEOCFG2_XPOS_Msk (0x7ffu << LCDC_HEOCFG2_XPOS_Pos) /**< \brief (LCDC_HEOCFG2) Horizontal Window Position */\r
+#define LCDC_HEOCFG2_XPOS(value) ((LCDC_HEOCFG2_XPOS_Msk & ((value) << LCDC_HEOCFG2_XPOS_Pos)))\r
+#define LCDC_HEOCFG2_YPOS_Pos 16\r
+#define LCDC_HEOCFG2_YPOS_Msk (0x7ffu << LCDC_HEOCFG2_YPOS_Pos) /**< \brief (LCDC_HEOCFG2) Vertical Window Position */\r
+#define LCDC_HEOCFG2_YPOS(value) ((LCDC_HEOCFG2_YPOS_Msk & ((value) << LCDC_HEOCFG2_YPOS_Pos)))\r
+/* -------- LCDC_HEOCFG3 : (LCDC Offset: 0x00000398) High End Overlay Configuration Register 3 -------- */\r
+#define LCDC_HEOCFG3_XSIZE_Pos 0\r
+#define LCDC_HEOCFG3_XSIZE_Msk (0x7ffu << LCDC_HEOCFG3_XSIZE_Pos) /**< \brief (LCDC_HEOCFG3) Horizontal Window Size */\r
+#define LCDC_HEOCFG3_XSIZE(value) ((LCDC_HEOCFG3_XSIZE_Msk & ((value) << LCDC_HEOCFG3_XSIZE_Pos)))\r
+#define LCDC_HEOCFG3_YSIZE_Pos 16\r
+#define LCDC_HEOCFG3_YSIZE_Msk (0x7ffu << LCDC_HEOCFG3_YSIZE_Pos) /**< \brief (LCDC_HEOCFG3) Vertical Window Size */\r
+#define LCDC_HEOCFG3_YSIZE(value) ((LCDC_HEOCFG3_YSIZE_Msk & ((value) << LCDC_HEOCFG3_YSIZE_Pos)))\r
+/* -------- LCDC_HEOCFG4 : (LCDC Offset: 0x0000039C) High End Overlay Configuration Register 4 -------- */\r
+#define LCDC_HEOCFG4_XMEMSIZE_Pos 0\r
+#define LCDC_HEOCFG4_XMEMSIZE_Msk (0x7ffu << LCDC_HEOCFG4_XMEMSIZE_Pos) /**< \brief (LCDC_HEOCFG4) Horizontal image Size in Memory */\r
+#define LCDC_HEOCFG4_XMEMSIZE(value) ((LCDC_HEOCFG4_XMEMSIZE_Msk & ((value) << LCDC_HEOCFG4_XMEMSIZE_Pos)))\r
+#define LCDC_HEOCFG4_YMEMSIZE_Pos 16\r
+#define LCDC_HEOCFG4_YMEMSIZE_Msk (0x7ffu << LCDC_HEOCFG4_YMEMSIZE_Pos) /**< \brief (LCDC_HEOCFG4) Vertical image Size in Memory */\r
+#define LCDC_HEOCFG4_YMEMSIZE(value) ((LCDC_HEOCFG4_YMEMSIZE_Msk & ((value) << LCDC_HEOCFG4_YMEMSIZE_Pos)))\r
+/* -------- LCDC_HEOCFG5 : (LCDC Offset: 0x000003A0) High End Overlay Configuration Register 5 -------- */\r
+#define LCDC_HEOCFG5_XSTRIDE_Pos 0\r
+#define LCDC_HEOCFG5_XSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG5_XSTRIDE_Pos) /**< \brief (LCDC_HEOCFG5) Horizontal Stride */\r
+#define LCDC_HEOCFG5_XSTRIDE(value) ((LCDC_HEOCFG5_XSTRIDE_Msk & ((value) << LCDC_HEOCFG5_XSTRIDE_Pos)))\r
+/* -------- LCDC_HEOCFG6 : (LCDC Offset: 0x000003A4) High End Overlay Configuration Register 6 -------- */\r
+#define LCDC_HEOCFG6_PSTRIDE_Pos 0\r
+#define LCDC_HEOCFG6_PSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG6_PSTRIDE_Pos) /**< \brief (LCDC_HEOCFG6) Pixel Stride */\r
+#define LCDC_HEOCFG6_PSTRIDE(value) ((LCDC_HEOCFG6_PSTRIDE_Msk & ((value) << LCDC_HEOCFG6_PSTRIDE_Pos)))\r
+/* -------- LCDC_HEOCFG7 : (LCDC Offset: 0x000003A8) High End Overlay Configuration Register 7 -------- */\r
+#define LCDC_HEOCFG7_UVXSTRIDE_Pos 0\r
+#define LCDC_HEOCFG7_UVXSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG7_UVXSTRIDE_Pos) /**< \brief (LCDC_HEOCFG7) UV Horizontal Stride */\r
+#define LCDC_HEOCFG7_UVXSTRIDE(value) ((LCDC_HEOCFG7_UVXSTRIDE_Msk & ((value) << LCDC_HEOCFG7_UVXSTRIDE_Pos)))\r
+/* -------- LCDC_HEOCFG8 : (LCDC Offset: 0x000003AC) High End Overlay Configuration Register 8 -------- */\r
+#define LCDC_HEOCFG8_UVPSTRIDE_Pos 0\r
+#define LCDC_HEOCFG8_UVPSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG8_UVPSTRIDE_Pos) /**< \brief (LCDC_HEOCFG8) UV Pixel Stride */\r
+#define LCDC_HEOCFG8_UVPSTRIDE(value) ((LCDC_HEOCFG8_UVPSTRIDE_Msk & ((value) << LCDC_HEOCFG8_UVPSTRIDE_Pos)))\r
+/* -------- LCDC_HEOCFG9 : (LCDC Offset: 0x000003B0) High End Overlay Configuration Register 9 -------- */\r
+#define LCDC_HEOCFG9_BDEF_Pos 0\r
+#define LCDC_HEOCFG9_BDEF_Msk (0xffu << LCDC_HEOCFG9_BDEF_Pos) /**< \brief (LCDC_HEOCFG9) Blue Default */\r
+#define LCDC_HEOCFG9_BDEF(value) ((LCDC_HEOCFG9_BDEF_Msk & ((value) << LCDC_HEOCFG9_BDEF_Pos)))\r
+#define LCDC_HEOCFG9_GDEF_Pos 8\r
+#define LCDC_HEOCFG9_GDEF_Msk (0xffu << LCDC_HEOCFG9_GDEF_Pos) /**< \brief (LCDC_HEOCFG9) Green Default */\r
+#define LCDC_HEOCFG9_GDEF(value) ((LCDC_HEOCFG9_GDEF_Msk & ((value) << LCDC_HEOCFG9_GDEF_Pos)))\r
+#define LCDC_HEOCFG9_RDEF_Pos 16\r
+#define LCDC_HEOCFG9_RDEF_Msk (0xffu << LCDC_HEOCFG9_RDEF_Pos) /**< \brief (LCDC_HEOCFG9) Red Default */\r
+#define LCDC_HEOCFG9_RDEF(value) ((LCDC_HEOCFG9_RDEF_Msk & ((value) << LCDC_HEOCFG9_RDEF_Pos)))\r
+/* -------- LCDC_HEOCFG10 : (LCDC Offset: 0x000003B4) High End Overlay Configuration Register 10 -------- */\r
+#define LCDC_HEOCFG10_BKEY_Pos 0\r
+#define LCDC_HEOCFG10_BKEY_Msk (0xffu << LCDC_HEOCFG10_BKEY_Pos) /**< \brief (LCDC_HEOCFG10) Blue Color Component Chroma Key */\r
+#define LCDC_HEOCFG10_BKEY(value) ((LCDC_HEOCFG10_BKEY_Msk & ((value) << LCDC_HEOCFG10_BKEY_Pos)))\r
+#define LCDC_HEOCFG10_GKEY_Pos 8\r
+#define LCDC_HEOCFG10_GKEY_Msk (0xffu << LCDC_HEOCFG10_GKEY_Pos) /**< \brief (LCDC_HEOCFG10) Green Color Component Chroma Key */\r
+#define LCDC_HEOCFG10_GKEY(value) ((LCDC_HEOCFG10_GKEY_Msk & ((value) << LCDC_HEOCFG10_GKEY_Pos)))\r
+#define LCDC_HEOCFG10_RKEY_Pos 16\r
+#define LCDC_HEOCFG10_RKEY_Msk (0xffu << LCDC_HEOCFG10_RKEY_Pos) /**< \brief (LCDC_HEOCFG10) Red Color Component Chroma Key */\r
+#define LCDC_HEOCFG10_RKEY(value) ((LCDC_HEOCFG10_RKEY_Msk & ((value) << LCDC_HEOCFG10_RKEY_Pos)))\r
+/* -------- LCDC_HEOCFG11 : (LCDC Offset: 0x000003B8) High End Overlay Configuration Register 11 -------- */\r
+#define LCDC_HEOCFG11_BMASK_Pos 0\r
+#define LCDC_HEOCFG11_BMASK_Msk (0xffu << LCDC_HEOCFG11_BMASK_Pos) /**< \brief (LCDC_HEOCFG11) Blue Color Component Chroma Key Mask */\r
+#define LCDC_HEOCFG11_BMASK(value) ((LCDC_HEOCFG11_BMASK_Msk & ((value) << LCDC_HEOCFG11_BMASK_Pos)))\r
+#define LCDC_HEOCFG11_GMASK_Pos 8\r
+#define LCDC_HEOCFG11_GMASK_Msk (0xffu << LCDC_HEOCFG11_GMASK_Pos) /**< \brief (LCDC_HEOCFG11) Green Color Component Chroma Key Mask */\r
+#define LCDC_HEOCFG11_GMASK(value) ((LCDC_HEOCFG11_GMASK_Msk & ((value) << LCDC_HEOCFG11_GMASK_Pos)))\r
+#define LCDC_HEOCFG11_RMASK_Pos 16\r
+#define LCDC_HEOCFG11_RMASK_Msk (0xffu << LCDC_HEOCFG11_RMASK_Pos) /**< \brief (LCDC_HEOCFG11) Red Color Component Chroma Key Mask */\r
+#define LCDC_HEOCFG11_RMASK(value) ((LCDC_HEOCFG11_RMASK_Msk & ((value) << LCDC_HEOCFG11_RMASK_Pos)))\r
+/* -------- LCDC_HEOCFG12 : (LCDC Offset: 0x000003BC) High End Overlay Configuration Register 12 -------- */\r
+#define LCDC_HEOCFG12_CRKEY (0x1u << 0) /**< \brief (LCDC_HEOCFG12) Blender Chroma Key Enable */\r
+#define LCDC_HEOCFG12_INV (0x1u << 1) /**< \brief (LCDC_HEOCFG12) Blender Inverted Blender Output Enable */\r
+#define LCDC_HEOCFG12_ITER2BL (0x1u << 2) /**< \brief (LCDC_HEOCFG12) Blender Iterated Color Enable */\r
+#define LCDC_HEOCFG12_ITER (0x1u << 3) /**< \brief (LCDC_HEOCFG12) Blender Use Iterated Color */\r
+#define LCDC_HEOCFG12_REVALPHA (0x1u << 4) /**< \brief (LCDC_HEOCFG12) Blender Reverse Alpha */\r
+#define LCDC_HEOCFG12_GAEN (0x1u << 5) /**< \brief (LCDC_HEOCFG12) Blender Global Alpha Enable */\r
+#define LCDC_HEOCFG12_LAEN (0x1u << 6) /**< \brief (LCDC_HEOCFG12) Blender Local Alpha Enable */\r
+#define LCDC_HEOCFG12_OVR (0x1u << 7) /**< \brief (LCDC_HEOCFG12) Blender Overlay Layer Enable */\r
+#define LCDC_HEOCFG12_DMA (0x1u << 8) /**< \brief (LCDC_HEOCFG12) Blender DMA Layer Enable */\r
+#define LCDC_HEOCFG12_REP (0x1u << 9) /**< \brief (LCDC_HEOCFG12) Use Replication logic to expand RGB color to 24 bits */\r
+#define LCDC_HEOCFG12_DSTKEY (0x1u << 10) /**< \brief (LCDC_HEOCFG12) Destination Chroma Keying */\r
+#define LCDC_HEOCFG12_VIDPRI (0x1u << 12) /**< \brief (LCDC_HEOCFG12) Video Priority */\r
+#define LCDC_HEOCFG12_GA_Pos 16\r
+#define LCDC_HEOCFG12_GA_Msk (0xffu << LCDC_HEOCFG12_GA_Pos) /**< \brief (LCDC_HEOCFG12) Blender Global Alpha */\r
+#define LCDC_HEOCFG12_GA(value) ((LCDC_HEOCFG12_GA_Msk & ((value) << LCDC_HEOCFG12_GA_Pos)))\r
+/* -------- LCDC_HEOCFG13 : (LCDC Offset: 0x000003C0) High End Overlay Configuration Register 13 -------- */\r
+#define LCDC_HEOCFG13_XFACTOR_Pos 0\r
+#define LCDC_HEOCFG13_XFACTOR_Msk (0x3fffu << LCDC_HEOCFG13_XFACTOR_Pos) /**< \brief (LCDC_HEOCFG13) Horizontal Scaling Factor */\r
+#define LCDC_HEOCFG13_XFACTOR(value) ((LCDC_HEOCFG13_XFACTOR_Msk & ((value) << LCDC_HEOCFG13_XFACTOR_Pos)))\r
+#define LCDC_HEOCFG13_YFACTOR_Pos 16\r
+#define LCDC_HEOCFG13_YFACTOR_Msk (0x3fffu << LCDC_HEOCFG13_YFACTOR_Pos) /**< \brief (LCDC_HEOCFG13) Vertical Scaling Factor */\r
+#define LCDC_HEOCFG13_YFACTOR(value) ((LCDC_HEOCFG13_YFACTOR_Msk & ((value) << LCDC_HEOCFG13_YFACTOR_Pos)))\r
+#define LCDC_HEOCFG13_SCALEN (0x1u << 31) /**< \brief (LCDC_HEOCFG13) Hardware Scaler Enable */\r
+/* -------- LCDC_HEOCFG14 : (LCDC Offset: 0x000003C4) High End Overlay Configuration Register 14 -------- */\r
+#define LCDC_HEOCFG14_CSCRY_Pos 0\r
+#define LCDC_HEOCFG14_CSCRY_Msk (0x3ffu << LCDC_HEOCFG14_CSCRY_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion Y coefficient for Red Component 1:2:7 format */\r
+#define LCDC_HEOCFG14_CSCRY(value) ((LCDC_HEOCFG14_CSCRY_Msk & ((value) << LCDC_HEOCFG14_CSCRY_Pos)))\r
+#define LCDC_HEOCFG14_CSCRU_Pos 10\r
+#define LCDC_HEOCFG14_CSCRU_Msk (0x3ffu << LCDC_HEOCFG14_CSCRU_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion U coefficient for Red Component 1:2:7 format */\r
+#define LCDC_HEOCFG14_CSCRU(value) ((LCDC_HEOCFG14_CSCRU_Msk & ((value) << LCDC_HEOCFG14_CSCRU_Pos)))\r
+#define LCDC_HEOCFG14_CSCRV_Pos 20\r
+#define LCDC_HEOCFG14_CSCRV_Msk (0x3ffu << LCDC_HEOCFG14_CSCRV_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion V coefficient for Red Component 1:2:7 format */\r
+#define LCDC_HEOCFG14_CSCRV(value) ((LCDC_HEOCFG14_CSCRV_Msk & ((value) << LCDC_HEOCFG14_CSCRV_Pos)))\r
+#define LCDC_HEOCFG14_CSCYOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG14) Color Space Conversion Offset */\r
+/* -------- LCDC_HEOCFG15 : (LCDC Offset: 0x000003C8) High End Overlay Configuration Register 15 -------- */\r
+#define LCDC_HEOCFG15_CSCGY_Pos 0\r
+#define LCDC_HEOCFG15_CSCGY_Msk (0x3ffu << LCDC_HEOCFG15_CSCGY_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion Y coefficient for Green Component 1:2:7 format */\r
+#define LCDC_HEOCFG15_CSCGY(value) ((LCDC_HEOCFG15_CSCGY_Msk & ((value) << LCDC_HEOCFG15_CSCGY_Pos)))\r
+#define LCDC_HEOCFG15_CSCGU_Pos 10\r
+#define LCDC_HEOCFG15_CSCGU_Msk (0x3ffu << LCDC_HEOCFG15_CSCGU_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion U coefficient for Green Component 1:2:7 format */\r
+#define LCDC_HEOCFG15_CSCGU(value) ((LCDC_HEOCFG15_CSCGU_Msk & ((value) << LCDC_HEOCFG15_CSCGU_Pos)))\r
+#define LCDC_HEOCFG15_CSCGV_Pos 20\r
+#define LCDC_HEOCFG15_CSCGV_Msk (0x3ffu << LCDC_HEOCFG15_CSCGV_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion V coefficient for Green Component 1:2:7 format */\r
+#define LCDC_HEOCFG15_CSCGV(value) ((LCDC_HEOCFG15_CSCGV_Msk & ((value) << LCDC_HEOCFG15_CSCGV_Pos)))\r
+#define LCDC_HEOCFG15_CSCUOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG15) Color Space Conversion Offset */\r
+/* -------- LCDC_HEOCFG16 : (LCDC Offset: 0x000003CC) High End Overlay Configuration Register 16 -------- */\r
+#define LCDC_HEOCFG16_CSCBY_Pos 0\r
+#define LCDC_HEOCFG16_CSCBY_Msk (0x3ffu << LCDC_HEOCFG16_CSCBY_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion Y coefficient for Blue Component 1:2:7 format */\r
+#define LCDC_HEOCFG16_CSCBY(value) ((LCDC_HEOCFG16_CSCBY_Msk & ((value) << LCDC_HEOCFG16_CSCBY_Pos)))\r
+#define LCDC_HEOCFG16_CSCBU_Pos 10\r
+#define LCDC_HEOCFG16_CSCBU_Msk (0x3ffu << LCDC_HEOCFG16_CSCBU_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion U coefficient for Blue Component 1:2:7 format */\r
+#define LCDC_HEOCFG16_CSCBU(value) ((LCDC_HEOCFG16_CSCBU_Msk & ((value) << LCDC_HEOCFG16_CSCBU_Pos)))\r
+#define LCDC_HEOCFG16_CSCBV_Pos 20\r
+#define LCDC_HEOCFG16_CSCBV_Msk (0x3ffu << LCDC_HEOCFG16_CSCBV_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion V coefficient for Blue Component 1:2:7 format */\r
+#define LCDC_HEOCFG16_CSCBV(value) ((LCDC_HEOCFG16_CSCBV_Msk & ((value) << LCDC_HEOCFG16_CSCBV_Pos)))\r
+#define LCDC_HEOCFG16_CSCVOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG16) Color Space Conversion Offset */\r
+/* -------- LCDC_HEOCFG17 : (LCDC Offset: 0x000003D0) High End Overlay Configuration Register 17 -------- */\r
+#define LCDC_HEOCFG17_XPHI0COEFF0_Pos 0\r
+#define LCDC_HEOCFG17_XPHI0COEFF0_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF0_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 0 */\r
+#define LCDC_HEOCFG17_XPHI0COEFF0(value) ((LCDC_HEOCFG17_XPHI0COEFF0_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF0_Pos)))\r
+#define LCDC_HEOCFG17_XPHI0COEFF1_Pos 8\r
+#define LCDC_HEOCFG17_XPHI0COEFF1_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF1_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 1 */\r
+#define LCDC_HEOCFG17_XPHI0COEFF1(value) ((LCDC_HEOCFG17_XPHI0COEFF1_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF1_Pos)))\r
+#define LCDC_HEOCFG17_XPHI0COEFF2_Pos 16\r
+#define LCDC_HEOCFG17_XPHI0COEFF2_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF2_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 2 */\r
+#define LCDC_HEOCFG17_XPHI0COEFF2(value) ((LCDC_HEOCFG17_XPHI0COEFF2_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF2_Pos)))\r
+#define LCDC_HEOCFG17_XPHI0COEFF3_Pos 24\r
+#define LCDC_HEOCFG17_XPHI0COEFF3_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF3_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 3 */\r
+#define LCDC_HEOCFG17_XPHI0COEFF3(value) ((LCDC_HEOCFG17_XPHI0COEFF3_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF3_Pos)))\r
+/* -------- LCDC_HEOCFG18 : (LCDC Offset: 0x000003D4) High End Overlay Configuration Register 18 -------- */\r
+#define LCDC_HEOCFG18_XPHI0COEFF4_Pos 0\r
+#define LCDC_HEOCFG18_XPHI0COEFF4_Msk (0xffu << LCDC_HEOCFG18_XPHI0COEFF4_Pos) /**< \brief (LCDC_HEOCFG18) Horizontal Coefficient for phase 0 tap 4 */\r
+#define LCDC_HEOCFG18_XPHI0COEFF4(value) ((LCDC_HEOCFG18_XPHI0COEFF4_Msk & ((value) << LCDC_HEOCFG18_XPHI0COEFF4_Pos)))\r
+/* -------- LCDC_HEOCFG19 : (LCDC Offset: 0x000003D8) High End Overlay Configuration Register 19 -------- */\r
+#define LCDC_HEOCFG19_XPHI1COEFF0_Pos 0\r
+#define LCDC_HEOCFG19_XPHI1COEFF0_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF0_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 0 */\r
+#define LCDC_HEOCFG19_XPHI1COEFF0(value) ((LCDC_HEOCFG19_XPHI1COEFF0_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF0_Pos)))\r
+#define LCDC_HEOCFG19_XPHI1COEFF1_Pos 8\r
+#define LCDC_HEOCFG19_XPHI1COEFF1_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF1_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 1 */\r
+#define LCDC_HEOCFG19_XPHI1COEFF1(value) ((LCDC_HEOCFG19_XPHI1COEFF1_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF1_Pos)))\r
+#define LCDC_HEOCFG19_XPHI1COEFF2_Pos 16\r
+#define LCDC_HEOCFG19_XPHI1COEFF2_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF2_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 2 */\r
+#define LCDC_HEOCFG19_XPHI1COEFF2(value) ((LCDC_HEOCFG19_XPHI1COEFF2_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF2_Pos)))\r
+#define LCDC_HEOCFG19_XPHI1COEFF3_Pos 24\r
+#define LCDC_HEOCFG19_XPHI1COEFF3_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF3_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 3 */\r
+#define LCDC_HEOCFG19_XPHI1COEFF3(value) ((LCDC_HEOCFG19_XPHI1COEFF3_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF3_Pos)))\r
+/* -------- LCDC_HEOCFG20 : (LCDC Offset: 0x000003DC) High End Overlay Configuration Register 20 -------- */\r
+#define LCDC_HEOCFG20_XPHI1COEFF4_Pos 0\r
+#define LCDC_HEOCFG20_XPHI1COEFF4_Msk (0xffu << LCDC_HEOCFG20_XPHI1COEFF4_Pos) /**< \brief (LCDC_HEOCFG20) Horizontal Coefficient for phase 1 tap 4 */\r
+#define LCDC_HEOCFG20_XPHI1COEFF4(value) ((LCDC_HEOCFG20_XPHI1COEFF4_Msk & ((value) << LCDC_HEOCFG20_XPHI1COEFF4_Pos)))\r
+/* -------- LCDC_HEOCFG21 : (LCDC Offset: 0x000003E0) High End Overlay Configuration Register 21 -------- */\r
+#define LCDC_HEOCFG21_XPHI2COEFF0_Pos 0\r
+#define LCDC_HEOCFG21_XPHI2COEFF0_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF0_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 0 */\r
+#define LCDC_HEOCFG21_XPHI2COEFF0(value) ((LCDC_HEOCFG21_XPHI2COEFF0_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF0_Pos)))\r
+#define LCDC_HEOCFG21_XPHI2COEFF1_Pos 8\r
+#define LCDC_HEOCFG21_XPHI2COEFF1_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF1_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 1 */\r
+#define LCDC_HEOCFG21_XPHI2COEFF1(value) ((LCDC_HEOCFG21_XPHI2COEFF1_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF1_Pos)))\r
+#define LCDC_HEOCFG21_XPHI2COEFF2_Pos 16\r
+#define LCDC_HEOCFG21_XPHI2COEFF2_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF2_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 2 */\r
+#define LCDC_HEOCFG21_XPHI2COEFF2(value) ((LCDC_HEOCFG21_XPHI2COEFF2_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF2_Pos)))\r
+#define LCDC_HEOCFG21_XPHI2COEFF3_Pos 24\r
+#define LCDC_HEOCFG21_XPHI2COEFF3_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF3_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 3 */\r
+#define LCDC_HEOCFG21_XPHI2COEFF3(value) ((LCDC_HEOCFG21_XPHI2COEFF3_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF3_Pos)))\r
+/* -------- LCDC_HEOCFG22 : (LCDC Offset: 0x000003E4) High End Overlay Configuration Register 22 -------- */\r
+#define LCDC_HEOCFG22_XPHI2COEFF4_Pos 0\r
+#define LCDC_HEOCFG22_XPHI2COEFF4_Msk (0xffu << LCDC_HEOCFG22_XPHI2COEFF4_Pos) /**< \brief (LCDC_HEOCFG22) Horizontal Coefficient for phase 2 tap 4 */\r
+#define LCDC_HEOCFG22_XPHI2COEFF4(value) ((LCDC_HEOCFG22_XPHI2COEFF4_Msk & ((value) << LCDC_HEOCFG22_XPHI2COEFF4_Pos)))\r
+/* -------- LCDC_HEOCFG23 : (LCDC Offset: 0x000003E8) High End Overlay Configuration Register 23 -------- */\r
+#define LCDC_HEOCFG23_XPHI3COEFF0_Pos 0\r
+#define LCDC_HEOCFG23_XPHI3COEFF0_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF0_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 0 */\r
+#define LCDC_HEOCFG23_XPHI3COEFF0(value) ((LCDC_HEOCFG23_XPHI3COEFF0_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF0_Pos)))\r
+#define LCDC_HEOCFG23_XPHI3COEFF1_Pos 8\r
+#define LCDC_HEOCFG23_XPHI3COEFF1_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF1_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 1 */\r
+#define LCDC_HEOCFG23_XPHI3COEFF1(value) ((LCDC_HEOCFG23_XPHI3COEFF1_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF1_Pos)))\r
+#define LCDC_HEOCFG23_XPHI3COEFF2_Pos 16\r
+#define LCDC_HEOCFG23_XPHI3COEFF2_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF2_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 2 */\r
+#define LCDC_HEOCFG23_XPHI3COEFF2(value) ((LCDC_HEOCFG23_XPHI3COEFF2_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF2_Pos)))\r
+#define LCDC_HEOCFG23_XPHI3COEFF3_Pos 24\r
+#define LCDC_HEOCFG23_XPHI3COEFF3_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF3_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 3 */\r
+#define LCDC_HEOCFG23_XPHI3COEFF3(value) ((LCDC_HEOCFG23_XPHI3COEFF3_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF3_Pos)))\r
+/* -------- LCDC_HEOCFG24 : (LCDC Offset: 0x000003EC) High End Overlay Configuration Register 24 -------- */\r
+#define LCDC_HEOCFG24_XPHI3COEFF4_Pos 0\r
+#define LCDC_HEOCFG24_XPHI3COEFF4_Msk (0xffu << LCDC_HEOCFG24_XPHI3COEFF4_Pos) /**< \brief (LCDC_HEOCFG24) Horizontal Coefficient for phase 3 tap 4 */\r
+#define LCDC_HEOCFG24_XPHI3COEFF4(value) ((LCDC_HEOCFG24_XPHI3COEFF4_Msk & ((value) << LCDC_HEOCFG24_XPHI3COEFF4_Pos)))\r
+/* -------- LCDC_HEOCFG25 : (LCDC Offset: 0x000003F0) High End Overlay Configuration Register 25 -------- */\r
+#define LCDC_HEOCFG25_XPHI4COEFF0_Pos 0\r
+#define LCDC_HEOCFG25_XPHI4COEFF0_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF0_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 0 */\r
+#define LCDC_HEOCFG25_XPHI4COEFF0(value) ((LCDC_HEOCFG25_XPHI4COEFF0_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF0_Pos)))\r
+#define LCDC_HEOCFG25_XPHI4COEFF1_Pos 8\r
+#define LCDC_HEOCFG25_XPHI4COEFF1_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF1_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 1 */\r
+#define LCDC_HEOCFG25_XPHI4COEFF1(value) ((LCDC_HEOCFG25_XPHI4COEFF1_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF1_Pos)))\r
+#define LCDC_HEOCFG25_XPHI4COEFF2_Pos 16\r
+#define LCDC_HEOCFG25_XPHI4COEFF2_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF2_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 2 */\r
+#define LCDC_HEOCFG25_XPHI4COEFF2(value) ((LCDC_HEOCFG25_XPHI4COEFF2_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF2_Pos)))\r
+#define LCDC_HEOCFG25_XPHI4COEFF3_Pos 24\r
+#define LCDC_HEOCFG25_XPHI4COEFF3_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF3_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 3 */\r
+#define LCDC_HEOCFG25_XPHI4COEFF3(value) ((LCDC_HEOCFG25_XPHI4COEFF3_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF3_Pos)))\r
+/* -------- LCDC_HEOCFG26 : (LCDC Offset: 0x000003F4) High End Overlay Configuration Register 26 -------- */\r
+#define LCDC_HEOCFG26_XPHI4COEFF4_Pos 0\r
+#define LCDC_HEOCFG26_XPHI4COEFF4_Msk (0xffu << LCDC_HEOCFG26_XPHI4COEFF4_Pos) /**< \brief (LCDC_HEOCFG26) Horizontal Coefficient for phase 4 tap 4 */\r
+#define LCDC_HEOCFG26_XPHI4COEFF4(value) ((LCDC_HEOCFG26_XPHI4COEFF4_Msk & ((value) << LCDC_HEOCFG26_XPHI4COEFF4_Pos)))\r
+/* -------- LCDC_HEOCFG27 : (LCDC Offset: 0x000003F8) High End Overlay Configuration Register 27 -------- */\r
+#define LCDC_HEOCFG27_XPHI5COEFF0_Pos 0\r
+#define LCDC_HEOCFG27_XPHI5COEFF0_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF0_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 0 */\r
+#define LCDC_HEOCFG27_XPHI5COEFF0(value) ((LCDC_HEOCFG27_XPHI5COEFF0_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF0_Pos)))\r
+#define LCDC_HEOCFG27_XPHI5COEFF1_Pos 8\r
+#define LCDC_HEOCFG27_XPHI5COEFF1_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF1_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 1 */\r
+#define LCDC_HEOCFG27_XPHI5COEFF1(value) ((LCDC_HEOCFG27_XPHI5COEFF1_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF1_Pos)))\r
+#define LCDC_HEOCFG27_XPHI5COEFF2_Pos 16\r
+#define LCDC_HEOCFG27_XPHI5COEFF2_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF2_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 2 */\r
+#define LCDC_HEOCFG27_XPHI5COEFF2(value) ((LCDC_HEOCFG27_XPHI5COEFF2_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF2_Pos)))\r
+#define LCDC_HEOCFG27_XPHI5COEFF3_Pos 24\r
+#define LCDC_HEOCFG27_XPHI5COEFF3_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF3_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 3 */\r
+#define LCDC_HEOCFG27_XPHI5COEFF3(value) ((LCDC_HEOCFG27_XPHI5COEFF3_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF3_Pos)))\r
+/* -------- LCDC_HEOCFG28 : (LCDC Offset: 0x000003FC) High End Overlay Configuration Register 28 -------- */\r
+#define LCDC_HEOCFG28_XPHI5COEFF4_Pos 0\r
+#define LCDC_HEOCFG28_XPHI5COEFF4_Msk (0xffu << LCDC_HEOCFG28_XPHI5COEFF4_Pos) /**< \brief (LCDC_HEOCFG28) Horizontal Coefficient for phase 5 tap 4 */\r
+#define LCDC_HEOCFG28_XPHI5COEFF4(value) ((LCDC_HEOCFG28_XPHI5COEFF4_Msk & ((value) << LCDC_HEOCFG28_XPHI5COEFF4_Pos)))\r
+/* -------- LCDC_HEOCFG29 : (LCDC Offset: 0x00000400) High End Overlay Configuration Register 29 -------- */\r
+#define LCDC_HEOCFG29_XPHI6COEFF0_Pos 0\r
+#define LCDC_HEOCFG29_XPHI6COEFF0_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF0_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 0 */\r
+#define LCDC_HEOCFG29_XPHI6COEFF0(value) ((LCDC_HEOCFG29_XPHI6COEFF0_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF0_Pos)))\r
+#define LCDC_HEOCFG29_XPHI6COEFF1_Pos 8\r
+#define LCDC_HEOCFG29_XPHI6COEFF1_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF1_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 1 */\r
+#define LCDC_HEOCFG29_XPHI6COEFF1(value) ((LCDC_HEOCFG29_XPHI6COEFF1_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF1_Pos)))\r
+#define LCDC_HEOCFG29_XPHI6COEFF2_Pos 16\r
+#define LCDC_HEOCFG29_XPHI6COEFF2_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF2_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 2 */\r
+#define LCDC_HEOCFG29_XPHI6COEFF2(value) ((LCDC_HEOCFG29_XPHI6COEFF2_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF2_Pos)))\r
+#define LCDC_HEOCFG29_XPHI6COEFF3_Pos 24\r
+#define LCDC_HEOCFG29_XPHI6COEFF3_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF3_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 3 */\r
+#define LCDC_HEOCFG29_XPHI6COEFF3(value) ((LCDC_HEOCFG29_XPHI6COEFF3_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF3_Pos)))\r
+/* -------- LCDC_HEOCFG30 : (LCDC Offset: 0x00000404) High End Overlay Configuration Register 30 -------- */\r
+#define LCDC_HEOCFG30_XPHI6COEFF4_Pos 0\r
+#define LCDC_HEOCFG30_XPHI6COEFF4_Msk (0xffu << LCDC_HEOCFG30_XPHI6COEFF4_Pos) /**< \brief (LCDC_HEOCFG30) Horizontal Coefficient for phase 6 tap 4 */\r
+#define LCDC_HEOCFG30_XPHI6COEFF4(value) ((LCDC_HEOCFG30_XPHI6COEFF4_Msk & ((value) << LCDC_HEOCFG30_XPHI6COEFF4_Pos)))\r
+/* -------- LCDC_HEOCFG31 : (LCDC Offset: 0x00000408) High End Overlay Configuration Register 31 -------- */\r
+#define LCDC_HEOCFG31_XPHI7COEFF0_Pos 0\r
+#define LCDC_HEOCFG31_XPHI7COEFF0_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF0_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 0 */\r
+#define LCDC_HEOCFG31_XPHI7COEFF0(value) ((LCDC_HEOCFG31_XPHI7COEFF0_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF0_Pos)))\r
+#define LCDC_HEOCFG31_XPHI7COEFF1_Pos 8\r
+#define LCDC_HEOCFG31_XPHI7COEFF1_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF1_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 1 */\r
+#define LCDC_HEOCFG31_XPHI7COEFF1(value) ((LCDC_HEOCFG31_XPHI7COEFF1_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF1_Pos)))\r
+#define LCDC_HEOCFG31_XPHI7COEFF2_Pos 16\r
+#define LCDC_HEOCFG31_XPHI7COEFF2_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF2_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 2 */\r
+#define LCDC_HEOCFG31_XPHI7COEFF2(value) ((LCDC_HEOCFG31_XPHI7COEFF2_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF2_Pos)))\r
+#define LCDC_HEOCFG31_XPHI7COEFF3_Pos 24\r
+#define LCDC_HEOCFG31_XPHI7COEFF3_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF3_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 3 */\r
+#define LCDC_HEOCFG31_XPHI7COEFF3(value) ((LCDC_HEOCFG31_XPHI7COEFF3_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF3_Pos)))\r
+/* -------- LCDC_HEOCFG32 : (LCDC Offset: 0x0000040C) High End Overlay Configuration Register 32 -------- */\r
+#define LCDC_HEOCFG32_XPHI7COEFF4_Pos 0\r
+#define LCDC_HEOCFG32_XPHI7COEFF4_Msk (0xffu << LCDC_HEOCFG32_XPHI7COEFF4_Pos) /**< \brief (LCDC_HEOCFG32) Horizontal Coefficient for phase 7 tap 4 */\r
+#define LCDC_HEOCFG32_XPHI7COEFF4(value) ((LCDC_HEOCFG32_XPHI7COEFF4_Msk & ((value) << LCDC_HEOCFG32_XPHI7COEFF4_Pos)))\r
+/* -------- LCDC_HEOCFG33 : (LCDC Offset: 0x00000410) High End Overlay Configuration Register 33 -------- */\r
+#define LCDC_HEOCFG33_YPHI0COEFF0_Pos 0\r
+#define LCDC_HEOCFG33_YPHI0COEFF0_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF0_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 0 */\r
+#define LCDC_HEOCFG33_YPHI0COEFF0(value) ((LCDC_HEOCFG33_YPHI0COEFF0_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF0_Pos)))\r
+#define LCDC_HEOCFG33_YPHI0COEFF1_Pos 8\r
+#define LCDC_HEOCFG33_YPHI0COEFF1_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF1_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 1 */\r
+#define LCDC_HEOCFG33_YPHI0COEFF1(value) ((LCDC_HEOCFG33_YPHI0COEFF1_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF1_Pos)))\r
+#define LCDC_HEOCFG33_YPHI0COEFF2_Pos 16\r
+#define LCDC_HEOCFG33_YPHI0COEFF2_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF2_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 2 */\r
+#define LCDC_HEOCFG33_YPHI0COEFF2(value) ((LCDC_HEOCFG33_YPHI0COEFF2_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF2_Pos)))\r
+/* -------- LCDC_HEOCFG34 : (LCDC Offset: 0x00000414) High End Overlay Configuration Register 34 -------- */\r
+#define LCDC_HEOCFG34_YPHI1COEFF0_Pos 0\r
+#define LCDC_HEOCFG34_YPHI1COEFF0_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF0_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 0 */\r
+#define LCDC_HEOCFG34_YPHI1COEFF0(value) ((LCDC_HEOCFG34_YPHI1COEFF0_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF0_Pos)))\r
+#define LCDC_HEOCFG34_YPHI1COEFF1_Pos 8\r
+#define LCDC_HEOCFG34_YPHI1COEFF1_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF1_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 1 */\r
+#define LCDC_HEOCFG34_YPHI1COEFF1(value) ((LCDC_HEOCFG34_YPHI1COEFF1_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF1_Pos)))\r
+#define LCDC_HEOCFG34_YPHI1COEFF2_Pos 16\r
+#define LCDC_HEOCFG34_YPHI1COEFF2_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF2_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 2 */\r
+#define LCDC_HEOCFG34_YPHI1COEFF2(value) ((LCDC_HEOCFG34_YPHI1COEFF2_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF2_Pos)))\r
+/* -------- LCDC_HEOCFG35 : (LCDC Offset: 0x00000418) High End Overlay Configuration Register 35 -------- */\r
+#define LCDC_HEOCFG35_YPHI2COEFF0_Pos 0\r
+#define LCDC_HEOCFG35_YPHI2COEFF0_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF0_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 0 */\r
+#define LCDC_HEOCFG35_YPHI2COEFF0(value) ((LCDC_HEOCFG35_YPHI2COEFF0_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF0_Pos)))\r
+#define LCDC_HEOCFG35_YPHI2COEFF1_Pos 8\r
+#define LCDC_HEOCFG35_YPHI2COEFF1_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF1_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 1 */\r
+#define LCDC_HEOCFG35_YPHI2COEFF1(value) ((LCDC_HEOCFG35_YPHI2COEFF1_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF1_Pos)))\r
+#define LCDC_HEOCFG35_YPHI2COEFF2_Pos 16\r
+#define LCDC_HEOCFG35_YPHI2COEFF2_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF2_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 2 */\r
+#define LCDC_HEOCFG35_YPHI2COEFF2(value) ((LCDC_HEOCFG35_YPHI2COEFF2_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF2_Pos)))\r
+/* -------- LCDC_HEOCFG36 : (LCDC Offset: 0x0000041C) High End Overlay Configuration Register 36 -------- */\r
+#define LCDC_HEOCFG36_YPHI3COEFF0_Pos 0\r
+#define LCDC_HEOCFG36_YPHI3COEFF0_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF0_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 0 */\r
+#define LCDC_HEOCFG36_YPHI3COEFF0(value) ((LCDC_HEOCFG36_YPHI3COEFF0_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF0_Pos)))\r
+#define LCDC_HEOCFG36_YPHI3COEFF1_Pos 8\r
+#define LCDC_HEOCFG36_YPHI3COEFF1_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF1_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 1 */\r
+#define LCDC_HEOCFG36_YPHI3COEFF1(value) ((LCDC_HEOCFG36_YPHI3COEFF1_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF1_Pos)))\r
+#define LCDC_HEOCFG36_YPHI3COEFF2_Pos 16\r
+#define LCDC_HEOCFG36_YPHI3COEFF2_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF2_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 2 */\r
+#define LCDC_HEOCFG36_YPHI3COEFF2(value) ((LCDC_HEOCFG36_YPHI3COEFF2_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF2_Pos)))\r
+/* -------- LCDC_HEOCFG37 : (LCDC Offset: 0x00000420) High End Overlay Configuration Register 37 -------- */\r
+#define LCDC_HEOCFG37_YPHI4COEFF0_Pos 0\r
+#define LCDC_HEOCFG37_YPHI4COEFF0_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF0_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 0 */\r
+#define LCDC_HEOCFG37_YPHI4COEFF0(value) ((LCDC_HEOCFG37_YPHI4COEFF0_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF0_Pos)))\r
+#define LCDC_HEOCFG37_YPHI4COEFF1_Pos 8\r
+#define LCDC_HEOCFG37_YPHI4COEFF1_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF1_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 1 */\r
+#define LCDC_HEOCFG37_YPHI4COEFF1(value) ((LCDC_HEOCFG37_YPHI4COEFF1_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF1_Pos)))\r
+#define LCDC_HEOCFG37_YPHI4COEFF2_Pos 16\r
+#define LCDC_HEOCFG37_YPHI4COEFF2_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF2_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 2 */\r
+#define LCDC_HEOCFG37_YPHI4COEFF2(value) ((LCDC_HEOCFG37_YPHI4COEFF2_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF2_Pos)))\r
+/* -------- LCDC_HEOCFG38 : (LCDC Offset: 0x00000424) High End Overlay Configuration Register 38 -------- */\r
+#define LCDC_HEOCFG38_YPHI5COEFF0_Pos 0\r
+#define LCDC_HEOCFG38_YPHI5COEFF0_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF0_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 0 */\r
+#define LCDC_HEOCFG38_YPHI5COEFF0(value) ((LCDC_HEOCFG38_YPHI5COEFF0_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF0_Pos)))\r
+#define LCDC_HEOCFG38_YPHI5COEFF1_Pos 8\r
+#define LCDC_HEOCFG38_YPHI5COEFF1_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF1_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 1 */\r
+#define LCDC_HEOCFG38_YPHI5COEFF1(value) ((LCDC_HEOCFG38_YPHI5COEFF1_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF1_Pos)))\r
+#define LCDC_HEOCFG38_YPHI5COEFF2_Pos 16\r
+#define LCDC_HEOCFG38_YPHI5COEFF2_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF2_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 2 */\r
+#define LCDC_HEOCFG38_YPHI5COEFF2(value) ((LCDC_HEOCFG38_YPHI5COEFF2_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF2_Pos)))\r
+/* -------- LCDC_HEOCFG39 : (LCDC Offset: 0x00000428) High End Overlay Configuration Register 39 -------- */\r
+#define LCDC_HEOCFG39_YPHI6COEFF0_Pos 0\r
+#define LCDC_HEOCFG39_YPHI6COEFF0_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF0_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 0 */\r
+#define LCDC_HEOCFG39_YPHI6COEFF0(value) ((LCDC_HEOCFG39_YPHI6COEFF0_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF0_Pos)))\r
+#define LCDC_HEOCFG39_YPHI6COEFF1_Pos 8\r
+#define LCDC_HEOCFG39_YPHI6COEFF1_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF1_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 1 */\r
+#define LCDC_HEOCFG39_YPHI6COEFF1(value) ((LCDC_HEOCFG39_YPHI6COEFF1_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF1_Pos)))\r
+#define LCDC_HEOCFG39_YPHI6COEFF2_Pos 16\r
+#define LCDC_HEOCFG39_YPHI6COEFF2_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF2_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 2 */\r
+#define LCDC_HEOCFG39_YPHI6COEFF2(value) ((LCDC_HEOCFG39_YPHI6COEFF2_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF2_Pos)))\r
+/* -------- LCDC_HEOCFG40 : (LCDC Offset: 0x0000042C) High End Overlay Configuration Register 40 -------- */\r
+#define LCDC_HEOCFG40_YPHI7COEFF0_Pos 0\r
+#define LCDC_HEOCFG40_YPHI7COEFF0_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF0_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 0 */\r
+#define LCDC_HEOCFG40_YPHI7COEFF0(value) ((LCDC_HEOCFG40_YPHI7COEFF0_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF0_Pos)))\r
+#define LCDC_HEOCFG40_YPHI7COEFF1_Pos 8\r
+#define LCDC_HEOCFG40_YPHI7COEFF1_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF1_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 1 */\r
+#define LCDC_HEOCFG40_YPHI7COEFF1(value) ((LCDC_HEOCFG40_YPHI7COEFF1_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF1_Pos)))\r
+#define LCDC_HEOCFG40_YPHI7COEFF2_Pos 16\r
+#define LCDC_HEOCFG40_YPHI7COEFF2_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF2_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 2 */\r
+#define LCDC_HEOCFG40_YPHI7COEFF2(value) ((LCDC_HEOCFG40_YPHI7COEFF2_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF2_Pos)))\r
+/* -------- LCDC_HEOCFG41 : (LCDC Offset: 0x00000430) High End Overlay Configuration Register 41 -------- */\r
+#define LCDC_HEOCFG41_XPHIDEF_Pos 0\r
+#define LCDC_HEOCFG41_XPHIDEF_Msk (0x7u << LCDC_HEOCFG41_XPHIDEF_Pos) /**< \brief (LCDC_HEOCFG41) Horizontal Filter Phase Offset */\r
+#define LCDC_HEOCFG41_XPHIDEF(value) ((LCDC_HEOCFG41_XPHIDEF_Msk & ((value) << LCDC_HEOCFG41_XPHIDEF_Pos)))\r
+#define LCDC_HEOCFG41_YPHIDEF_Pos 16\r
+#define LCDC_HEOCFG41_YPHIDEF_Msk (0x7u << LCDC_HEOCFG41_YPHIDEF_Pos) /**< \brief (LCDC_HEOCFG41) Vertical Filter Phase Offset */\r
+#define LCDC_HEOCFG41_YPHIDEF(value) ((LCDC_HEOCFG41_YPHIDEF_Msk & ((value) << LCDC_HEOCFG41_YPHIDEF_Pos)))\r
+/* -------- LCDC_PPCHER : (LCDC Offset: 0x00000540) Post Processing Channel Enable Register -------- */\r
+#define LCDC_PPCHER_CHEN (0x1u << 0) /**< \brief (LCDC_PPCHER) Channel Enable Register */\r
+#define LCDC_PPCHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_PPCHER) Update Overlay Attributes Enable Register */\r
+#define LCDC_PPCHER_A2QEN (0x1u << 2) /**< \brief (LCDC_PPCHER) Add To Queue Enable Register */\r
+/* -------- LCDC_PPCHDR : (LCDC Offset: 0x00000544) Post Processing Channel Disable Register -------- */\r
+#define LCDC_PPCHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_PPCHDR) Channel Disable Register */\r
+#define LCDC_PPCHDR_CHRST (0x1u << 8) /**< \brief (LCDC_PPCHDR) Channel Reset Register */\r
+/* -------- LCDC_PPCHSR : (LCDC Offset: 0x00000548) Post Processing Channel Status Register -------- */\r
+#define LCDC_PPCHSR_CHSR (0x1u << 0) /**< \brief (LCDC_PPCHSR) Channel Status Register */\r
+#define LCDC_PPCHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_PPCHSR) Update Overlay Attributes In Progress Status Register */\r
+#define LCDC_PPCHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_PPCHSR) Add To Queue Status Register */\r
+/* -------- LCDC_PPIER : (LCDC Offset: 0x0000054C) Post Processing Interrupt Enable Register -------- */\r
+#define LCDC_PPIER_DMA (0x1u << 2) /**< \brief (LCDC_PPIER) End of DMA Transfer Interrupt Enable Register */\r
+#define LCDC_PPIER_DSCR (0x1u << 3) /**< \brief (LCDC_PPIER) Descriptor Loaded Interrupt Enable Register */\r
+#define LCDC_PPIER_ADD (0x1u << 4) /**< \brief (LCDC_PPIER) Head Descriptor Loaded Interrupt Enable Register */\r
+#define LCDC_PPIER_DONE (0x1u << 5) /**< \brief (LCDC_PPIER) End of List Interrupt Enable Register */\r
+/* -------- LCDC_PPIDR : (LCDC Offset: 0x00000550) Post Processing Interrupt Disable Register -------- */\r
+#define LCDC_PPIDR_DMA (0x1u << 2) /**< \brief (LCDC_PPIDR) End of DMA Transfer Interrupt Disable Register */\r
+#define LCDC_PPIDR_DSCR (0x1u << 3) /**< \brief (LCDC_PPIDR) Descriptor Loaded Interrupt Disable Register */\r
+#define LCDC_PPIDR_ADD (0x1u << 4) /**< \brief (LCDC_PPIDR) Head Descriptor Loaded Interrupt Disable Register */\r
+#define LCDC_PPIDR_DONE (0x1u << 5) /**< \brief (LCDC_PPIDR) End of List Interrupt Disable Register */\r
+/* -------- LCDC_PPIMR : (LCDC Offset: 0x00000554) Post Processing Interrupt Mask Register -------- */\r
+#define LCDC_PPIMR_DMA (0x1u << 2) /**< \brief (LCDC_PPIMR) End of DMA Transfer Interrupt Mask Register */\r
+#define LCDC_PPIMR_DSCR (0x1u << 3) /**< \brief (LCDC_PPIMR) Descriptor Loaded Interrupt Mask Register */\r
+#define LCDC_PPIMR_ADD (0x1u << 4) /**< \brief (LCDC_PPIMR) Head Descriptor Loaded Interrupt Mask Register */\r
+#define LCDC_PPIMR_DONE (0x1u << 5) /**< \brief (LCDC_PPIMR) End of List Interrupt Mask Register */\r
+/* -------- LCDC_PPISR : (LCDC Offset: 0x00000558) Post Processing Interrupt Status Register -------- */\r
+#define LCDC_PPISR_DMA (0x1u << 2) /**< \brief (LCDC_PPISR) End of DMA Transfer */\r
+#define LCDC_PPISR_DSCR (0x1u << 3) /**< \brief (LCDC_PPISR) DMA Descriptor Loaded */\r
+#define LCDC_PPISR_ADD (0x1u << 4) /**< \brief (LCDC_PPISR) Head Descriptor Loaded */\r
+#define LCDC_PPISR_DONE (0x1u << 5) /**< \brief (LCDC_PPISR) End of List Detected */\r
+/* -------- LCDC_PPHEAD : (LCDC Offset: 0x0000055C) Post Processing Head Register -------- */\r
+#define LCDC_PPHEAD_HEAD_Pos 2\r
+#define LCDC_PPHEAD_HEAD_Msk (0x3fffffffu << LCDC_PPHEAD_HEAD_Pos) /**< \brief (LCDC_PPHEAD) DMA Head Pointer */\r
+#define LCDC_PPHEAD_HEAD(value) ((LCDC_PPHEAD_HEAD_Msk & ((value) << LCDC_PPHEAD_HEAD_Pos)))\r
+/* -------- LCDC_PPADDR : (LCDC Offset: 0x00000560) Post Processing Address Register -------- */\r
+#define LCDC_PPADDR_ADDR_Pos 0\r
+#define LCDC_PPADDR_ADDR_Msk (0xffffffffu << LCDC_PPADDR_ADDR_Pos) /**< \brief (LCDC_PPADDR) DMA Transfer start address */\r
+#define LCDC_PPADDR_ADDR(value) ((LCDC_PPADDR_ADDR_Msk & ((value) << LCDC_PPADDR_ADDR_Pos)))\r
+/* -------- LCDC_PPCTRL : (LCDC Offset: 0x00000564) Post Processing Control Register -------- */\r
+#define LCDC_PPCTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_PPCTRL) Transfer Descriptor Fetch Enable */\r
+#define LCDC_PPCTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_PPCTRL) End of DMA Transfer Interrupt Enable */\r
+#define LCDC_PPCTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_PPCTRL) Descriptor Loaded Interrupt Enable */\r
+#define LCDC_PPCTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_PPCTRL) Add Head Descriptor to Queue Interrupt Enable */\r
+#define LCDC_PPCTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_PPCTRL) End of List Interrupt Enable */\r
+/* -------- LCDC_PPNEXT : (LCDC Offset: 0x00000568) Post Processing Next Register -------- */\r
+#define LCDC_PPNEXT_NEXT_Pos 0\r
+#define LCDC_PPNEXT_NEXT_Msk (0xffffffffu << LCDC_PPNEXT_NEXT_Pos) /**< \brief (LCDC_PPNEXT) DMA Descriptor Next Address */\r
+#define LCDC_PPNEXT_NEXT(value) ((LCDC_PPNEXT_NEXT_Msk & ((value) << LCDC_PPNEXT_NEXT_Pos)))\r
+/* -------- LCDC_PPCFG0 : (LCDC Offset: 0x0000056C) Post Processing Configuration Register 0 -------- */\r
+#define LCDC_PPCFG0_SIF (0x1u << 0) /**< \brief (LCDC_PPCFG0) Source Interface */\r
+#define LCDC_PPCFG0_BLEN_Pos 4\r
+#define LCDC_PPCFG0_BLEN_Msk (0x3u << LCDC_PPCFG0_BLEN_Pos) /**< \brief (LCDC_PPCFG0) AHB Burst Length */\r
+#define LCDC_PPCFG0_BLEN(value) ((LCDC_PPCFG0_BLEN_Msk & ((value) << LCDC_PPCFG0_BLEN_Pos)))\r
+#define LCDC_PPCFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_PPCFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_PPCFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_PPCFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */\r
+#define LCDC_PPCFG0_DLBO (0x1u << 8) /**< \brief (LCDC_PPCFG0) Defined Length Burst Only For Channel Bus Transaction. */\r
+/* -------- LCDC_PPCFG1 : (LCDC Offset: 0x00000570) Post Processing Configuration Register 1 -------- */\r
+#define LCDC_PPCFG1_PPMODE_Pos 0\r
+#define LCDC_PPCFG1_PPMODE_Msk (0x7u << LCDC_PPCFG1_PPMODE_Pos) /**< \brief (LCDC_PPCFG1) Post Processing Output Format selection */\r
+#define LCDC_PPCFG1_PPMODE(value) ((LCDC_PPCFG1_PPMODE_Msk & ((value) << LCDC_PPCFG1_PPMODE_Pos)))\r
+#define LCDC_PPCFG1_PPMODE_PPMODE_RGB_16BPP (0x0u << 0) /**< \brief (LCDC_PPCFG1) RGB 16 bpp */\r
+#define LCDC_PPCFG1_PPMODE_PPMODE_RGB_24BPP_PACKED (0x1u << 0) /**< \brief (LCDC_PPCFG1) RGB 24 bpp PACKED */\r
+#define LCDC_PPCFG1_PPMODE_PPMODE_RGB_24BPP_UNPACKED (0x2u << 0) /**< \brief (LCDC_PPCFG1) RGB 24 bpp UNPACKED */\r
+#define LCDC_PPCFG1_PPMODE_PPMODE_YCBCR_422_MODE0 (0x3u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 0) */\r
+#define LCDC_PPCFG1_PPMODE_PPMODE_YCBCR_422_MODE1 (0x4u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 1) */\r
+#define LCDC_PPCFG1_PPMODE_PPMODE_YCBCR_422_MODE2 (0x5u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 2) */\r
+#define LCDC_PPCFG1_PPMODE_PPMODE_YCBCR_422_MODE3 (0x6u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 3) */\r
+#define LCDC_PPCFG1_ITUBT601 (0x1u << 4) /**< \brief (LCDC_PPCFG1) Color Space Conversion Luminance */\r
+/* -------- LCDC_PPCFG2 : (LCDC Offset: 0x00000574) Post Processing Configuration Register 2 -------- */\r
+#define LCDC_PPCFG2_XSTRIDE_Pos 0\r
+#define LCDC_PPCFG2_XSTRIDE_Msk (0xffffffffu << LCDC_PPCFG2_XSTRIDE_Pos) /**< \brief (LCDC_PPCFG2) Horizontal Stride */\r
+#define LCDC_PPCFG2_XSTRIDE(value) ((LCDC_PPCFG2_XSTRIDE_Msk & ((value) << LCDC_PPCFG2_XSTRIDE_Pos)))\r
+/* -------- LCDC_PPCFG3 : (LCDC Offset: 0x00000578) Post Processing Configuration Register 3 -------- */\r
+#define LCDC_PPCFG3_CSCYR_Pos 0\r
+#define LCDC_PPCFG3_CSCYR_Msk (0x3ffu << LCDC_PPCFG3_CSCYR_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion R coefficient for Luminance component, signed format, step set to 1/1024 */\r
+#define LCDC_PPCFG3_CSCYR(value) ((LCDC_PPCFG3_CSCYR_Msk & ((value) << LCDC_PPCFG3_CSCYR_Pos)))\r
+#define LCDC_PPCFG3_CSCYG_Pos 10\r
+#define LCDC_PPCFG3_CSCYG_Msk (0x3ffu << LCDC_PPCFG3_CSCYG_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion G coefficient for Luminance component, signed format, step set to 1/512 */\r
+#define LCDC_PPCFG3_CSCYG(value) ((LCDC_PPCFG3_CSCYG_Msk & ((value) << LCDC_PPCFG3_CSCYG_Pos)))\r
+#define LCDC_PPCFG3_CSCYB_Pos 20\r
+#define LCDC_PPCFG3_CSCYB_Msk (0x3ffu << LCDC_PPCFG3_CSCYB_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion B coefficient for Luminance component, signed format, step set to 1/1024 */\r
+#define LCDC_PPCFG3_CSCYB(value) ((LCDC_PPCFG3_CSCYB_Msk & ((value) << LCDC_PPCFG3_CSCYB_Pos)))\r
+#define LCDC_PPCFG3_CSCYOFF (0x1u << 30) /**< \brief (LCDC_PPCFG3) Color Space Conversion Luminance Offset */\r
+/* -------- LCDC_PPCFG4 : (LCDC Offset: 0x0000057C) Post Processing Configuration Register 4 -------- */\r
+#define LCDC_PPCFG4_CSCUR_Pos 0\r
+#define LCDC_PPCFG4_CSCUR_Msk (0x3ffu << LCDC_PPCFG4_CSCUR_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion R coefficient for Chrominance B component, signed format. (step 1/1024) */\r
+#define LCDC_PPCFG4_CSCUR(value) ((LCDC_PPCFG4_CSCUR_Msk & ((value) << LCDC_PPCFG4_CSCUR_Pos)))\r
+#define LCDC_PPCFG4_CSCUG_Pos 10\r
+#define LCDC_PPCFG4_CSCUG_Msk (0x3ffu << LCDC_PPCFG4_CSCUG_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion G coefficient for Chrominance B component, signed format. (step 1/512) */\r
+#define LCDC_PPCFG4_CSCUG(value) ((LCDC_PPCFG4_CSCUG_Msk & ((value) << LCDC_PPCFG4_CSCUG_Pos)))\r
+#define LCDC_PPCFG4_CSCUB_Pos 20\r
+#define LCDC_PPCFG4_CSCUB_Msk (0x3ffu << LCDC_PPCFG4_CSCUB_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion B coefficient for Chrominance B component, signed format. (step 1/512) */\r
+#define LCDC_PPCFG4_CSCUB(value) ((LCDC_PPCFG4_CSCUB_Msk & ((value) << LCDC_PPCFG4_CSCUB_Pos)))\r
+#define LCDC_PPCFG4_CSCUOFF (0x1u << 30) /**< \brief (LCDC_PPCFG4) Color Space Conversion Chrominance B Offset */\r
+/* -------- LCDC_PPCFG5 : (LCDC Offset: 0x00000580) Post Processing Configuration Register 5 -------- */\r
+#define LCDC_PPCFG5_CSCVR_Pos 0\r
+#define LCDC_PPCFG5_CSCVR_Msk (0x3ffu << LCDC_PPCFG5_CSCVR_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion R coefficient for Chrominance R component, signed format. (step 1/1024) */\r
+#define LCDC_PPCFG5_CSCVR(value) ((LCDC_PPCFG5_CSCVR_Msk & ((value) << LCDC_PPCFG5_CSCVR_Pos)))\r
+#define LCDC_PPCFG5_CSCVG_Pos 10\r
+#define LCDC_PPCFG5_CSCVG_Msk (0x3ffu << LCDC_PPCFG5_CSCVG_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion G coefficient for Chrominance R component, signed format. (step 1/512) */\r
+#define LCDC_PPCFG5_CSCVG(value) ((LCDC_PPCFG5_CSCVG_Msk & ((value) << LCDC_PPCFG5_CSCVG_Pos)))\r
+#define LCDC_PPCFG5_CSCVB_Pos 20\r
+#define LCDC_PPCFG5_CSCVB_Msk (0x3ffu << LCDC_PPCFG5_CSCVB_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion B coefficient for Chrominance R component, signed format. (step 1/1024) */\r
+#define LCDC_PPCFG5_CSCVB(value) ((LCDC_PPCFG5_CSCVB_Msk & ((value) << LCDC_PPCFG5_CSCVB_Pos)))\r
+#define LCDC_PPCFG5_CSCVOFF (0x1u << 30) /**< \brief (LCDC_PPCFG5) Color Space Conversion Chrominance R Offset */\r
+/* -------- LCDC_BASECLUT[256] : (LCDC Offset: 0x00000600) Base CLUT Register -------- */\r
+#define LCDC_BASECLUT_BCLUT_Pos 0\r
+#define LCDC_BASECLUT_BCLUT_Msk (0xffu << LCDC_BASECLUT_BCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Blue Color entry */\r
+#define LCDC_BASECLUT_BCLUT(value) ((LCDC_BASECLUT_BCLUT_Msk & ((value) << LCDC_BASECLUT_BCLUT_Pos)))\r
+#define LCDC_BASECLUT_GCLUT_Pos 8\r
+#define LCDC_BASECLUT_GCLUT_Msk (0xffu << LCDC_BASECLUT_GCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Green Color entry */\r
+#define LCDC_BASECLUT_GCLUT(value) ((LCDC_BASECLUT_GCLUT_Msk & ((value) << LCDC_BASECLUT_GCLUT_Pos)))\r
+#define LCDC_BASECLUT_RCLUT_Pos 16\r
+#define LCDC_BASECLUT_RCLUT_Msk (0xffu << LCDC_BASECLUT_RCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Red Color entry */\r
+#define LCDC_BASECLUT_RCLUT(value) ((LCDC_BASECLUT_RCLUT_Msk & ((value) << LCDC_BASECLUT_RCLUT_Pos)))\r
+/* -------- LCDC_OVR1CLUT[256] : (LCDC Offset: 0x00000A00) Overlay 1 CLUT Register -------- */\r
+#define LCDC_OVR1CLUT_BCLUT_Pos 0\r
+#define LCDC_OVR1CLUT_BCLUT_Msk (0xffu << LCDC_OVR1CLUT_BCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Blue Color entry */\r
+#define LCDC_OVR1CLUT_BCLUT(value) ((LCDC_OVR1CLUT_BCLUT_Msk & ((value) << LCDC_OVR1CLUT_BCLUT_Pos)))\r
+#define LCDC_OVR1CLUT_GCLUT_Pos 8\r
+#define LCDC_OVR1CLUT_GCLUT_Msk (0xffu << LCDC_OVR1CLUT_GCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Green Color entry */\r
+#define LCDC_OVR1CLUT_GCLUT(value) ((LCDC_OVR1CLUT_GCLUT_Msk & ((value) << LCDC_OVR1CLUT_GCLUT_Pos)))\r
+#define LCDC_OVR1CLUT_RCLUT_Pos 16\r
+#define LCDC_OVR1CLUT_RCLUT_Msk (0xffu << LCDC_OVR1CLUT_RCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Red Color entry */\r
+#define LCDC_OVR1CLUT_RCLUT(value) ((LCDC_OVR1CLUT_RCLUT_Msk & ((value) << LCDC_OVR1CLUT_RCLUT_Pos)))\r
+#define LCDC_OVR1CLUT_ACLUT_Pos 24\r
+#define LCDC_OVR1CLUT_ACLUT_Msk (0xffu << LCDC_OVR1CLUT_ACLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Alpha Color entry */\r
+#define LCDC_OVR1CLUT_ACLUT(value) ((LCDC_OVR1CLUT_ACLUT_Msk & ((value) << LCDC_OVR1CLUT_ACLUT_Pos)))\r
+/* -------- LCDC_OVR2CLUT[256] : (LCDC Offset: 0x00000E00) Overlay 2 CLUT Register -------- */\r
+#define LCDC_OVR2CLUT_BCLUT_Pos 0\r
+#define LCDC_OVR2CLUT_BCLUT_Msk (0xffu << LCDC_OVR2CLUT_BCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Blue Color entry */\r
+#define LCDC_OVR2CLUT_BCLUT(value) ((LCDC_OVR2CLUT_BCLUT_Msk & ((value) << LCDC_OVR2CLUT_BCLUT_Pos)))\r
+#define LCDC_OVR2CLUT_GCLUT_Pos 8\r
+#define LCDC_OVR2CLUT_GCLUT_Msk (0xffu << LCDC_OVR2CLUT_GCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Green Color entry */\r
+#define LCDC_OVR2CLUT_GCLUT(value) ((LCDC_OVR2CLUT_GCLUT_Msk & ((value) << LCDC_OVR2CLUT_GCLUT_Pos)))\r
+#define LCDC_OVR2CLUT_RCLUT_Pos 16\r
+#define LCDC_OVR2CLUT_RCLUT_Msk (0xffu << LCDC_OVR2CLUT_RCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Red Color entry */\r
+#define LCDC_OVR2CLUT_RCLUT(value) ((LCDC_OVR2CLUT_RCLUT_Msk & ((value) << LCDC_OVR2CLUT_RCLUT_Pos)))\r
+#define LCDC_OVR2CLUT_ACLUT_Pos 24\r
+#define LCDC_OVR2CLUT_ACLUT_Msk (0xffu << LCDC_OVR2CLUT_ACLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Alpha Color entry */\r
+#define LCDC_OVR2CLUT_ACLUT(value) ((LCDC_OVR2CLUT_ACLUT_Msk & ((value) << LCDC_OVR2CLUT_ACLUT_Pos)))\r
+/* -------- LCDC_HEOCLUT[256] : (LCDC Offset: 0x00001200) High End Overlay CLUT Register -------- */\r
+#define LCDC_HEOCLUT_BCLUT_Pos 0\r
+#define LCDC_HEOCLUT_BCLUT_Msk (0xffu << LCDC_HEOCLUT_BCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Blue Color entry */\r
+#define LCDC_HEOCLUT_BCLUT(value) ((LCDC_HEOCLUT_BCLUT_Msk & ((value) << LCDC_HEOCLUT_BCLUT_Pos)))\r
+#define LCDC_HEOCLUT_GCLUT_Pos 8\r
+#define LCDC_HEOCLUT_GCLUT_Msk (0xffu << LCDC_HEOCLUT_GCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Green Color entry */\r
+#define LCDC_HEOCLUT_GCLUT(value) ((LCDC_HEOCLUT_GCLUT_Msk & ((value) << LCDC_HEOCLUT_GCLUT_Pos)))\r
+#define LCDC_HEOCLUT_RCLUT_Pos 16\r
+#define LCDC_HEOCLUT_RCLUT_Msk (0xffu << LCDC_HEOCLUT_RCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Red Color entry */\r
+#define LCDC_HEOCLUT_RCLUT(value) ((LCDC_HEOCLUT_RCLUT_Msk & ((value) << LCDC_HEOCLUT_RCLUT_Pos)))\r
+#define LCDC_HEOCLUT_ACLUT_Pos 24\r
+#define LCDC_HEOCLUT_ACLUT_Msk (0xffu << LCDC_HEOCLUT_ACLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Alpha Color entry */\r
+#define LCDC_HEOCLUT_ACLUT(value) ((LCDC_HEOCLUT_ACLUT_Msk & ((value) << LCDC_HEOCLUT_ACLUT_Pos)))\r
+/* -------- LCDC_VERSION : (LCDC Offset: 0x00001FFC) Version Register -------- */\r
+#define LCDC_VERSION_VERSION_Pos 0\r
+#define LCDC_VERSION_VERSION_Msk (0xfffu << LCDC_VERSION_VERSION_Pos) /**< \brief (LCDC_VERSION) Version of the Hardware Module */\r
+#define LCDC_VERSION_MFN_Pos 16\r
+#define LCDC_VERSION_MFN_Msk (0x7u << LCDC_VERSION_MFN_Pos) /**< \brief (LCDC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_LCDC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_MATRIX_COMPONENT_\r
+#define _SAMA5D2_MATRIX_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_MATRIX AHB Bus Matrix */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief MatrixPr hardware registers */\r
+typedef struct {\r
+ __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */\r
+ __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */\r
+} MatrixPr;\r
+/** \brief Matrix hardware registers */\r
+#define MATRIXPR_NUMBER 15\r
+typedef struct {\r
+ __IO uint32_t MATRIX_MCFG0; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 */\r
+ __IO uint32_t MATRIX_MCFG1; /**< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 */\r
+ __IO uint32_t MATRIX_MCFG2; /**< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 */\r
+ __IO uint32_t MATRIX_MCFG3; /**< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 */\r
+ __IO uint32_t MATRIX_MCFG4; /**< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 */\r
+ __IO uint32_t MATRIX_MCFG5; /**< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 */\r
+ __IO uint32_t MATRIX_MCFG6; /**< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 */\r
+ __IO uint32_t MATRIX_MCFG7; /**< \brief (Matrix Offset: 0x001C) Master Configuration Register 7 */\r
+ __IO uint32_t MATRIX_MCFG8; /**< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 */\r
+ __IO uint32_t MATRIX_MCFG9; /**< \brief (Matrix Offset: 0x0024) Master Configuration Register 9 */\r
+ __IO uint32_t MATRIX_MCFG10; /**< \brief (Matrix Offset: 0x0028) Master Configuration Register 10 */\r
+ __IO uint32_t MATRIX_MCFG11; /**< \brief (Matrix Offset: 0x002C) Master Configuration Register 11 */\r
+ __I uint32_t Reserved1[4];\r
+ __IO uint32_t MATRIX_SCFG0; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register 0 */\r
+ __IO uint32_t MATRIX_SCFG1; /**< \brief (Matrix Offset: 0x0044) Slave Configuration Register 1 */\r
+ __IO uint32_t MATRIX_SCFG2; /**< \brief (Matrix Offset: 0x0048) Slave Configuration Register 2 */\r
+ __IO uint32_t MATRIX_SCFG3; /**< \brief (Matrix Offset: 0x004C) Slave Configuration Register 3 */\r
+ __IO uint32_t MATRIX_SCFG4; /**< \brief (Matrix Offset: 0x0050) Slave Configuration Register 4 */\r
+ __IO uint32_t MATRIX_SCFG5; /**< \brief (Matrix Offset: 0x0054) Slave Configuration Register 5 */\r
+ __IO uint32_t MATRIX_SCFG6; /**< \brief (Matrix Offset: 0x0058) Slave Configuration Register 6 */\r
+ __IO uint32_t MATRIX_SCFG7; /**< \brief (Matrix Offset: 0x005C) Slave Configuration Register 7 */\r
+ __IO uint32_t MATRIX_SCFG8; /**< \brief (Matrix Offset: 0x0060) Slave Configuration Register 8 */\r
+ __IO uint32_t MATRIX_SCFG9; /**< \brief (Matrix Offset: 0x0064) Slave Configuration Register 9 */\r
+ __IO uint32_t MATRIX_SCFG10; /**< \brief (Matrix Offset: 0x0068) Slave Configuration Register 10 */\r
+ __IO uint32_t MATRIX_SCFG11; /**< \brief (Matrix Offset: 0x006C) Slave Configuration Register 11 */\r
+ __IO uint32_t MATRIX_SCFG12; /**< \brief (Matrix Offset: 0x0070) Slave Configuration Register 12 */\r
+ __IO uint32_t MATRIX_SCFG13; /**< \brief (Matrix Offset: 0x0074) Slave Configuration Register 13 */\r
+ __IO uint32_t MATRIX_SCFG14; /**< \brief (Matrix Offset: 0x0078) Slave Configuration Register 14 */\r
+ __I uint32_t Reserved2[1];\r
+ MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 14 */\r
+ __I uint32_t Reserved3[22];\r
+ __O uint32_t MATRIX_MEIER; /**< \brief (Matrix Offset: 0x0150) Master Error Interrupt Enable Register */\r
+ __O uint32_t MATRIX_MEIDR; /**< \brief (Matrix Offset: 0x0154) Master Error Interrupt Disable Register */\r
+ __I uint32_t MATRIX_MEIMR; /**< \brief (Matrix Offset: 0x0158) Master Error Interrupt Mask Register */\r
+ __I uint32_t MATRIX_MESR; /**< \brief (Matrix Offset: 0x015C) Master Error Status Register */\r
+ __I uint32_t MATRIX_MEAR0; /**< \brief (Matrix Offset: 0x0160) Master 0 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR1; /**< \brief (Matrix Offset: 0x0164) Master 1 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR2; /**< \brief (Matrix Offset: 0x0168) Master 2 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR3; /**< \brief (Matrix Offset: 0x016C) Master 3 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR4; /**< \brief (Matrix Offset: 0x0170) Master 4 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR5; /**< \brief (Matrix Offset: 0x0174) Master 5 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR6; /**< \brief (Matrix Offset: 0x0178) Master 6 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR7; /**< \brief (Matrix Offset: 0x017C) Master 7 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR8; /**< \brief (Matrix Offset: 0x0180) Master 8 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR9; /**< \brief (Matrix Offset: 0x0184) Master 9 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR10; /**< \brief (Matrix Offset: 0x0188) Master 10 Error Address Register */\r
+ __I uint32_t MATRIX_MEAR11; /**< \brief (Matrix Offset: 0x018C) Master 11 Error Address Register */\r
+ __I uint32_t Reserved4[21];\r
+ __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */\r
+ __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */\r
+ __I uint32_t Reserved5[4];\r
+ __I uint32_t MATRIX_VERSION; /**< \brief (Matrix Offset: 0x01FC) Version Register */\r
+ __IO uint32_t MATRIX_SSR[15]; /**< \brief (Matrix Offset: 0x0200) Security Slave x Register */\r
+ __I uint32_t Reserved6[1];\r
+ __IO uint32_t MATRIX_SASSR[15]; /**< \brief (Matrix Offset: 0x0240) Security Areas Split Slave x Register */\r
+ __I uint32_t Reserved7[1];\r
+ __IO uint32_t MATRIX_SRTSR[15]; /**< \brief (Matrix Offset: 0x0284) Security Region Top Slave x Register */\r
+ __I uint32_t Reserved8[1];\r
+ __IO uint32_t MATRIX_SPSELR[3]; /**< \brief (Matrix Offset: 0x02C0) Security Peripheral Select x Register */\r
+} Matrix;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */\r
+#define MATRIX_MCFG0_ULBT_Pos 0\r
+#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /**< \brief (MATRIX_MCFG0) Undefined Length Burst Type */\r
+#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos)))\r
+#define MATRIX_MCFG0_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */\r
+#define MATRIX_MCFG0_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */\r
+#define MATRIX_MCFG0_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */\r
+#define MATRIX_MCFG0_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */\r
+#define MATRIX_MCFG0_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */\r
+#define MATRIX_MCFG0_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG0) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */\r
+#define MATRIX_MCFG0_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */\r
+#define MATRIX_MCFG0_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */\r
+/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */\r
+#define MATRIX_MCFG1_ULBT_Pos 0\r
+#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /**< \brief (MATRIX_MCFG1) Undefined Length Burst Type */\r
+#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos)))\r
+#define MATRIX_MCFG1_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */\r
+#define MATRIX_MCFG1_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */\r
+#define MATRIX_MCFG1_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */\r
+#define MATRIX_MCFG1_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */\r
+#define MATRIX_MCFG1_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */\r
+#define MATRIX_MCFG1_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG1) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */\r
+#define MATRIX_MCFG1_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */\r
+#define MATRIX_MCFG1_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */\r
+/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */\r
+#define MATRIX_MCFG2_ULBT_Pos 0\r
+#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /**< \brief (MATRIX_MCFG2) Undefined Length Burst Type */\r
+#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos)))\r
+#define MATRIX_MCFG2_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */\r
+#define MATRIX_MCFG2_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */\r
+#define MATRIX_MCFG2_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */\r
+#define MATRIX_MCFG2_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */\r
+#define MATRIX_MCFG2_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */\r
+#define MATRIX_MCFG2_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG2) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */\r
+#define MATRIX_MCFG2_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */\r
+#define MATRIX_MCFG2_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */\r
+/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */\r
+#define MATRIX_MCFG3_ULBT_Pos 0\r
+#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /**< \brief (MATRIX_MCFG3) Undefined Length Burst Type */\r
+#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos)))\r
+#define MATRIX_MCFG3_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */\r
+#define MATRIX_MCFG3_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */\r
+#define MATRIX_MCFG3_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */\r
+#define MATRIX_MCFG3_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */\r
+#define MATRIX_MCFG3_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */\r
+#define MATRIX_MCFG3_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG3) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */\r
+#define MATRIX_MCFG3_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */\r
+#define MATRIX_MCFG3_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */\r
+/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */\r
+#define MATRIX_MCFG4_ULBT_Pos 0\r
+#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /**< \brief (MATRIX_MCFG4) Undefined Length Burst Type */\r
+#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos)))\r
+#define MATRIX_MCFG4_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */\r
+#define MATRIX_MCFG4_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */\r
+#define MATRIX_MCFG4_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */\r
+#define MATRIX_MCFG4_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */\r
+#define MATRIX_MCFG4_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */\r
+#define MATRIX_MCFG4_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG4) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */\r
+#define MATRIX_MCFG4_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */\r
+#define MATRIX_MCFG4_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */\r
+/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */\r
+#define MATRIX_MCFG5_ULBT_Pos 0\r
+#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /**< \brief (MATRIX_MCFG5) Undefined Length Burst Type */\r
+#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos)))\r
+#define MATRIX_MCFG5_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */\r
+#define MATRIX_MCFG5_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */\r
+#define MATRIX_MCFG5_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */\r
+#define MATRIX_MCFG5_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */\r
+#define MATRIX_MCFG5_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */\r
+#define MATRIX_MCFG5_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG5) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */\r
+#define MATRIX_MCFG5_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */\r
+#define MATRIX_MCFG5_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */\r
+/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */\r
+#define MATRIX_MCFG6_ULBT_Pos 0\r
+#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /**< \brief (MATRIX_MCFG6) Undefined Length Burst Type */\r
+#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos)))\r
+#define MATRIX_MCFG6_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */\r
+#define MATRIX_MCFG6_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */\r
+#define MATRIX_MCFG6_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */\r
+#define MATRIX_MCFG6_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */\r
+#define MATRIX_MCFG6_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */\r
+#define MATRIX_MCFG6_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG6) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */\r
+#define MATRIX_MCFG6_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */\r
+#define MATRIX_MCFG6_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */\r
+/* -------- MATRIX_MCFG7 : (MATRIX Offset: 0x001C) Master Configuration Register 7 -------- */\r
+#define MATRIX_MCFG7_ULBT_Pos 0\r
+#define MATRIX_MCFG7_ULBT_Msk (0x7u << MATRIX_MCFG7_ULBT_Pos) /**< \brief (MATRIX_MCFG7) Undefined Length Burst Type */\r
+#define MATRIX_MCFG7_ULBT(value) ((MATRIX_MCFG7_ULBT_Msk & ((value) << MATRIX_MCFG7_ULBT_Pos)))\r
+#define MATRIX_MCFG7_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG7) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */\r
+#define MATRIX_MCFG7_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG7) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */\r
+#define MATRIX_MCFG7_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG7) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */\r
+#define MATRIX_MCFG7_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG7) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */\r
+#define MATRIX_MCFG7_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG7) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */\r
+#define MATRIX_MCFG7_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG7) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */\r
+#define MATRIX_MCFG7_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG7) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */\r
+#define MATRIX_MCFG7_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG7) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */\r
+/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */\r
+#define MATRIX_MCFG8_ULBT_Pos 0\r
+#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /**< \brief (MATRIX_MCFG8) Undefined Length Burst Type */\r
+#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos)))\r
+#define MATRIX_MCFG8_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */\r
+#define MATRIX_MCFG8_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */\r
+#define MATRIX_MCFG8_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */\r
+#define MATRIX_MCFG8_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */\r
+#define MATRIX_MCFG8_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */\r
+#define MATRIX_MCFG8_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG8) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */\r
+#define MATRIX_MCFG8_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */\r
+#define MATRIX_MCFG8_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */\r
+/* -------- MATRIX_MCFG9 : (MATRIX Offset: 0x0024) Master Configuration Register 9 -------- */\r
+#define MATRIX_MCFG9_ULBT_Pos 0\r
+#define MATRIX_MCFG9_ULBT_Msk (0x7u << MATRIX_MCFG9_ULBT_Pos) /**< \brief (MATRIX_MCFG9) Undefined Length Burst Type */\r
+#define MATRIX_MCFG9_ULBT(value) ((MATRIX_MCFG9_ULBT_Msk & ((value) << MATRIX_MCFG9_ULBT_Pos)))\r
+#define MATRIX_MCFG9_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG9) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */\r
+#define MATRIX_MCFG9_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG9) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */\r
+#define MATRIX_MCFG9_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG9) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */\r
+#define MATRIX_MCFG9_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG9) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */\r
+#define MATRIX_MCFG9_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG9) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */\r
+#define MATRIX_MCFG9_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG9) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */\r
+#define MATRIX_MCFG9_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG9) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */\r
+#define MATRIX_MCFG9_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG9) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */\r
+/* -------- MATRIX_SCFG0 : (MATRIX Offset: 0x0040) Slave Configuration Register 0 -------- */\r
+#define MATRIX_SCFG0_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG0_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG0_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG0) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG0_SLOT_CYCLE(value) ((MATRIX_SCFG0_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG0_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG0_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG0_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG0_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG0) Default Master Type */\r
+#define MATRIX_SCFG0_DEFMSTR_TYPE(value) ((MATRIX_SCFG0_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG0_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG0_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG0) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG0_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG0) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG0_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG0) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG0_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG0_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG0_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG0) Fixed Default Master */\r
+#define MATRIX_SCFG0_FIXED_DEFMSTR(value) ((MATRIX_SCFG0_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG0_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG1 : (MATRIX Offset: 0x0044) Slave Configuration Register 1 -------- */\r
+#define MATRIX_SCFG1_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG1_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG1_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG1) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG1_SLOT_CYCLE(value) ((MATRIX_SCFG1_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG1_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG1_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG1_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG1_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG1) Default Master Type */\r
+#define MATRIX_SCFG1_DEFMSTR_TYPE(value) ((MATRIX_SCFG1_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG1_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG1_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG1) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG1_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG1) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG1_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG1) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG1_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG1_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG1_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG1) Fixed Default Master */\r
+#define MATRIX_SCFG1_FIXED_DEFMSTR(value) ((MATRIX_SCFG1_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG1_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG2 : (MATRIX Offset: 0x0048) Slave Configuration Register 2 -------- */\r
+#define MATRIX_SCFG2_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG2_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG2_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG2) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG2_SLOT_CYCLE(value) ((MATRIX_SCFG2_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG2_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG2_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG2_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG2_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG2) Default Master Type */\r
+#define MATRIX_SCFG2_DEFMSTR_TYPE(value) ((MATRIX_SCFG2_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG2_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG2_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG2) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG2_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG2) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG2_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG2) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG2_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG2_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG2_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG2) Fixed Default Master */\r
+#define MATRIX_SCFG2_FIXED_DEFMSTR(value) ((MATRIX_SCFG2_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG2_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG3 : (MATRIX Offset: 0x004C) Slave Configuration Register 3 -------- */\r
+#define MATRIX_SCFG3_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG3_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG3_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG3) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG3_SLOT_CYCLE(value) ((MATRIX_SCFG3_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG3_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG3_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG3_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG3_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG3) Default Master Type */\r
+#define MATRIX_SCFG3_DEFMSTR_TYPE(value) ((MATRIX_SCFG3_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG3_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG3_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG3) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG3_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG3) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG3_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG3) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG3_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG3_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG3_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG3) Fixed Default Master */\r
+#define MATRIX_SCFG3_FIXED_DEFMSTR(value) ((MATRIX_SCFG3_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG3_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG4 : (MATRIX Offset: 0x0050) Slave Configuration Register 4 -------- */\r
+#define MATRIX_SCFG4_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG4_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG4_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG4) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG4_SLOT_CYCLE(value) ((MATRIX_SCFG4_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG4_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG4_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG4_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG4_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG4) Default Master Type */\r
+#define MATRIX_SCFG4_DEFMSTR_TYPE(value) ((MATRIX_SCFG4_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG4_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG4_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG4) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG4_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG4) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG4_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG4) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG4_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG4_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG4_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG4) Fixed Default Master */\r
+#define MATRIX_SCFG4_FIXED_DEFMSTR(value) ((MATRIX_SCFG4_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG4_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG5 : (MATRIX Offset: 0x0054) Slave Configuration Register 5 -------- */\r
+#define MATRIX_SCFG5_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG5_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG5_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG5) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG5_SLOT_CYCLE(value) ((MATRIX_SCFG5_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG5_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG5_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG5_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG5_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG5) Default Master Type */\r
+#define MATRIX_SCFG5_DEFMSTR_TYPE(value) ((MATRIX_SCFG5_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG5_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG5_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG5) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG5_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG5) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG5_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG5) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG5_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG5_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG5_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG5) Fixed Default Master */\r
+#define MATRIX_SCFG5_FIXED_DEFMSTR(value) ((MATRIX_SCFG5_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG5_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG6 : (MATRIX Offset: 0x0058) Slave Configuration Register 6 -------- */\r
+#define MATRIX_SCFG6_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG6_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG6_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG6) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG6_SLOT_CYCLE(value) ((MATRIX_SCFG6_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG6_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG6_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG6_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG6_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG6) Default Master Type */\r
+#define MATRIX_SCFG6_DEFMSTR_TYPE(value) ((MATRIX_SCFG6_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG6_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG6_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG6) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG6_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG6) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG6_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG6) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG6_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG6_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG6_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG6) Fixed Default Master */\r
+#define MATRIX_SCFG6_FIXED_DEFMSTR(value) ((MATRIX_SCFG6_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG6_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG7 : (MATRIX Offset: 0x005C) Slave Configuration Register 7 -------- */\r
+#define MATRIX_SCFG7_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG7_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG7_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG7) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG7_SLOT_CYCLE(value) ((MATRIX_SCFG7_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG7_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG7_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG7_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG7_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG7) Default Master Type */\r
+#define MATRIX_SCFG7_DEFMSTR_TYPE(value) ((MATRIX_SCFG7_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG7_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG7_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG7) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG7_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG7) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG7_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG7) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG7_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG7_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG7_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG7) Fixed Default Master */\r
+#define MATRIX_SCFG7_FIXED_DEFMSTR(value) ((MATRIX_SCFG7_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG7_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG8 : (MATRIX Offset: 0x0060) Slave Configuration Register 8 -------- */\r
+#define MATRIX_SCFG8_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG8_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG8_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG8) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG8_SLOT_CYCLE(value) ((MATRIX_SCFG8_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG8_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG8_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG8_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG8_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG8) Default Master Type */\r
+#define MATRIX_SCFG8_DEFMSTR_TYPE(value) ((MATRIX_SCFG8_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG8_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG8_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG8) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG8_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG8) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG8_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG8) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG8_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG8_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG8_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG8) Fixed Default Master */\r
+#define MATRIX_SCFG8_FIXED_DEFMSTR(value) ((MATRIX_SCFG8_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG8_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG9 : (MATRIX Offset: 0x0064) Slave Configuration Register 9 -------- */\r
+#define MATRIX_SCFG9_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG9_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG9_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG9) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG9_SLOT_CYCLE(value) ((MATRIX_SCFG9_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG9_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG9_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG9_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG9_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG9) Default Master Type */\r
+#define MATRIX_SCFG9_DEFMSTR_TYPE(value) ((MATRIX_SCFG9_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG9_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG9_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG9) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG9_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG9) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG9_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG9) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG9_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG9_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG9_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG9) Fixed Default Master */\r
+#define MATRIX_SCFG9_FIXED_DEFMSTR(value) ((MATRIX_SCFG9_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG9_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG10 : (MATRIX Offset: 0x0068) Slave Configuration Register 10 -------- */\r
+#define MATRIX_SCFG10_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG10_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG10_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG10) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG10_SLOT_CYCLE(value) ((MATRIX_SCFG10_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG10_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG10_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG10_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG10_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG10) Default Master Type */\r
+#define MATRIX_SCFG10_DEFMSTR_TYPE(value) ((MATRIX_SCFG10_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG10_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG10_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG10) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG10_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG10) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG10_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG10) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG10_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG10_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG10_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG10) Fixed Default Master */\r
+#define MATRIX_SCFG10_FIXED_DEFMSTR(value) ((MATRIX_SCFG10_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG10_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG11 : (MATRIX Offset: 0x006C) Slave Configuration Register 11 -------- */\r
+#define MATRIX_SCFG11_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG11_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG11_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG11) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG11_SLOT_CYCLE(value) ((MATRIX_SCFG11_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG11_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG11_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG11_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG11_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG11) Default Master Type */\r
+#define MATRIX_SCFG11_DEFMSTR_TYPE(value) ((MATRIX_SCFG11_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG11_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG11_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG11) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG11_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG11) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG11_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG11) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG11_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG11_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG11_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG11) Fixed Default Master */\r
+#define MATRIX_SCFG11_FIXED_DEFMSTR(value) ((MATRIX_SCFG11_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG11_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_SCFG12 : (MATRIX Offset: 0x0070) Slave Configuration Register 12 -------- */\r
+#define MATRIX_SCFG12_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG12_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG12_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG12) Maximum Bus Grant Duration for Masters */\r
+#define MATRIX_SCFG12_SLOT_CYCLE(value) ((MATRIX_SCFG12_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG12_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG12_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG12_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG12_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG12) Default Master Type */\r
+#define MATRIX_SCFG12_DEFMSTR_TYPE(value) ((MATRIX_SCFG12_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG12_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG12_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG12) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */\r
+#define MATRIX_SCFG12_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG12) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */\r
+#define MATRIX_SCFG12_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG12) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */\r
+#define MATRIX_SCFG12_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG12_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG12_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG12) Fixed Default Master */\r
+#define MATRIX_SCFG12_FIXED_DEFMSTR(value) ((MATRIX_SCFG12_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG12_FIXED_DEFMSTR_Pos)))\r
+/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */\r
+#define MATRIX_PRAS_M0PR_Pos 0\r
+#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */\r
+#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)))\r
+#define MATRIX_PRAS_M1PR_Pos 4\r
+#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */\r
+#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)))\r
+#define MATRIX_PRAS_M2PR_Pos 8\r
+#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */\r
+#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)))\r
+#define MATRIX_PRAS_M3PR_Pos 12\r
+#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */\r
+#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)))\r
+#define MATRIX_PRAS_M4PR_Pos 16\r
+#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */\r
+#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)))\r
+#define MATRIX_PRAS_M5PR_Pos 20\r
+#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */\r
+#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)))\r
+#define MATRIX_PRAS_M6PR_Pos 24\r
+#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */\r
+#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)))\r
+#define MATRIX_PRAS_M7PR_Pos 28\r
+#define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos) /**< \brief (MATRIX_PRAS) Master 7 Priority */\r
+#define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos)))\r
+/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */\r
+#define MATRIX_PRBS_M8PR_Pos 0\r
+#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */\r
+#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)))\r
+#define MATRIX_PRBS_M9PR_Pos 4\r
+#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */\r
+#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)))\r
+#define MATRIX_PRBS_M10PR_Pos 8\r
+#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */\r
+#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)))\r
+#define MATRIX_PRBS_M11PR_Pos 12\r
+#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */\r
+#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)))\r
+/* -------- MATRIX_MEIER : (MATRIX Offset: 0x0150) Master Error Interrupt Enable Register -------- */\r
+#define MATRIX_MEIER_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIER) Master 0 Access Error */\r
+#define MATRIX_MEIER_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIER) Master 1 Access Error */\r
+#define MATRIX_MEIER_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIER) Master 2 Access Error */\r
+#define MATRIX_MEIER_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIER) Master 3 Access Error */\r
+#define MATRIX_MEIER_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIER) Master 4 Access Error */\r
+#define MATRIX_MEIER_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIER) Master 5 Access Error */\r
+#define MATRIX_MEIER_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIER) Master 6 Access Error */\r
+#define MATRIX_MEIER_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIER) Master 7 Access Error */\r
+#define MATRIX_MEIER_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIER) Master 8 Access Error */\r
+#define MATRIX_MEIER_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIER) Master 9 Access Error */\r
+#define MATRIX_MEIER_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIER) Master 10 Access Error */\r
+#define MATRIX_MEIER_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIER) Master 11 Access Error */\r
+/* -------- MATRIX_MEIDR : (MATRIX Offset: 0x0154) Master Error Interrupt Disable Register -------- */\r
+#define MATRIX_MEIDR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIDR) Master 0 Access Error */\r
+#define MATRIX_MEIDR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIDR) Master 1 Access Error */\r
+#define MATRIX_MEIDR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIDR) Master 2 Access Error */\r
+#define MATRIX_MEIDR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIDR) Master 3 Access Error */\r
+#define MATRIX_MEIDR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIDR) Master 4 Access Error */\r
+#define MATRIX_MEIDR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIDR) Master 5 Access Error */\r
+#define MATRIX_MEIDR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIDR) Master 6 Access Error */\r
+#define MATRIX_MEIDR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIDR) Master 7 Access Error */\r
+#define MATRIX_MEIDR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIDR) Master 8 Access Error */\r
+#define MATRIX_MEIDR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIDR) Master 9 Access Error */\r
+#define MATRIX_MEIDR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIDR) Master 10 Access Error */\r
+#define MATRIX_MEIDR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIDR) Master 11 Access Error */\r
+/* -------- MATRIX_MEIMR : (MATRIX Offset: 0x0158) Master Error Interrupt Mask Register -------- */\r
+#define MATRIX_MEIMR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIMR) Master 0 Access Error */\r
+#define MATRIX_MEIMR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIMR) Master 1 Access Error */\r
+#define MATRIX_MEIMR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIMR) Master 2 Access Error */\r
+#define MATRIX_MEIMR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIMR) Master 3 Access Error */\r
+#define MATRIX_MEIMR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIMR) Master 4 Access Error */\r
+#define MATRIX_MEIMR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIMR) Master 5 Access Error */\r
+#define MATRIX_MEIMR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIMR) Master 6 Access Error */\r
+#define MATRIX_MEIMR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIMR) Master 7 Access Error */\r
+#define MATRIX_MEIMR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIMR) Master 8 Access Error */\r
+#define MATRIX_MEIMR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIMR) Master 9 Access Error */\r
+#define MATRIX_MEIMR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIMR) Master 10 Access Error */\r
+#define MATRIX_MEIMR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIMR) Master 11 Access Error */\r
+/* -------- MATRIX_MESR : (MATRIX Offset: 0x015C) Master Error Status Register -------- */\r
+#define MATRIX_MESR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MESR) Master 0 Access Error */\r
+#define MATRIX_MESR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MESR) Master 1 Access Error */\r
+#define MATRIX_MESR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MESR) Master 2 Access Error */\r
+#define MATRIX_MESR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MESR) Master 3 Access Error */\r
+#define MATRIX_MESR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MESR) Master 4 Access Error */\r
+#define MATRIX_MESR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MESR) Master 5 Access Error */\r
+#define MATRIX_MESR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MESR) Master 6 Access Error */\r
+#define MATRIX_MESR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MESR) Master 7 Access Error */\r
+#define MATRIX_MESR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MESR) Master 8 Access Error */\r
+#define MATRIX_MESR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MESR) Master 9 Access Error */\r
+#define MATRIX_MESR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MESR) Master 10 Access Error */\r
+#define MATRIX_MESR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MESR) Master 11 Access Error */\r
+/* -------- MATRIX_MEAR0 : (MATRIX Offset: 0x0160) Master 0 Error Address Register -------- */\r
+#define MATRIX_MEAR0_ERRADD_Pos 0\r
+#define MATRIX_MEAR0_ERRADD_Msk (0xffffffffu << MATRIX_MEAR0_ERRADD_Pos) /**< \brief (MATRIX_MEAR0) Master Error Address */\r
+/* -------- MATRIX_MEAR1 : (MATRIX Offset: 0x0164) Master 1 Error Address Register -------- */\r
+#define MATRIX_MEAR1_ERRADD_Pos 0\r
+#define MATRIX_MEAR1_ERRADD_Msk (0xffffffffu << MATRIX_MEAR1_ERRADD_Pos) /**< \brief (MATRIX_MEAR1) Master Error Address */\r
+/* -------- MATRIX_MEAR2 : (MATRIX Offset: 0x0168) Master 2 Error Address Register -------- */\r
+#define MATRIX_MEAR2_ERRADD_Pos 0\r
+#define MATRIX_MEAR2_ERRADD_Msk (0xffffffffu << MATRIX_MEAR2_ERRADD_Pos) /**< \brief (MATRIX_MEAR2) Master Error Address */\r
+/* -------- MATRIX_MEAR3 : (MATRIX Offset: 0x016C) Master 3 Error Address Register -------- */\r
+#define MATRIX_MEAR3_ERRADD_Pos 0\r
+#define MATRIX_MEAR3_ERRADD_Msk (0xffffffffu << MATRIX_MEAR3_ERRADD_Pos) /**< \brief (MATRIX_MEAR3) Master Error Address */\r
+/* -------- MATRIX_MEAR4 : (MATRIX Offset: 0x0170) Master 4 Error Address Register -------- */\r
+#define MATRIX_MEAR4_ERRADD_Pos 0\r
+#define MATRIX_MEAR4_ERRADD_Msk (0xffffffffu << MATRIX_MEAR4_ERRADD_Pos) /**< \brief (MATRIX_MEAR4) Master Error Address */\r
+/* -------- MATRIX_MEAR5 : (MATRIX Offset: 0x0174) Master 5 Error Address Register -------- */\r
+#define MATRIX_MEAR5_ERRADD_Pos 0\r
+#define MATRIX_MEAR5_ERRADD_Msk (0xffffffffu << MATRIX_MEAR5_ERRADD_Pos) /**< \brief (MATRIX_MEAR5) Master Error Address */\r
+/* -------- MATRIX_MEAR6 : (MATRIX Offset: 0x0178) Master 6 Error Address Register -------- */\r
+#define MATRIX_MEAR6_ERRADD_Pos 0\r
+#define MATRIX_MEAR6_ERRADD_Msk (0xffffffffu << MATRIX_MEAR6_ERRADD_Pos) /**< \brief (MATRIX_MEAR6) Master Error Address */\r
+/* -------- MATRIX_MEAR7 : (MATRIX Offset: 0x017C) Master 7 Error Address Register -------- */\r
+#define MATRIX_MEAR7_ERRADD_Pos 0\r
+#define MATRIX_MEAR7_ERRADD_Msk (0xffffffffu << MATRIX_MEAR7_ERRADD_Pos) /**< \brief (MATRIX_MEAR7) Master Error Address */\r
+/* -------- MATRIX_MEAR8 : (MATRIX Offset: 0x0180) Master 8 Error Address Register -------- */\r
+#define MATRIX_MEAR8_ERRADD_Pos 0\r
+#define MATRIX_MEAR8_ERRADD_Msk (0xffffffffu << MATRIX_MEAR8_ERRADD_Pos) /**< \brief (MATRIX_MEAR8) Master Error Address */\r
+/* -------- MATRIX_MEAR9 : (MATRIX Offset: 0x0184) Master 9 Error Address Register -------- */\r
+#define MATRIX_MEAR9_ERRADD_Pos 0\r
+#define MATRIX_MEAR9_ERRADD_Msk (0xffffffffu << MATRIX_MEAR9_ERRADD_Pos) /**< \brief (MATRIX_MEAR9) Master Error Address */\r
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */\r
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */\r
+#define MATRIX_WPMR_WPKEY_Pos 8\r
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key (Write-only) */\r
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))\r
+#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */\r
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */\r
+#define MATRIX_WPSR_WPVSRC_Pos 8\r
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */\r
+/* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */\r
+#define MATRIX_VERSION_VERSION_Pos 0\r
+#define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos) /**< \brief (MATRIX_VERSION) Version of the Hardware Module */\r
+#define MATRIX_VERSION_MFN_Pos 16\r
+#define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos) /**< \brief (MATRIX_VERSION) Metal Fix Number */\r
+/* -------- MATRIX_SSR0 : (MATRIX Offset: 0x0200) Security Slave 0 Register -------- */\r
+#define MATRIX_SSR0_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR0_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR0_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR0_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR0_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR0_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR0_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR0_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR0_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR0_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR1 : (MATRIX Offset: 0x0204) Security Slave 1 Register -------- */\r
+#define MATRIX_SSR1_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR1_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR1_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR1_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR1_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR1_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR1_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR1_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR1_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR1_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR2 : (MATRIX Offset: 0x0208) Security Slave 2 Register -------- */\r
+#define MATRIX_SSR2_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR2_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR2_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR2_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR2_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR2_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR2_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR2_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR2_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR2_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR3 : (MATRIX Offset: 0x020C) Security Slave 3 Register -------- */\r
+#define MATRIX_SSR3_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR3_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR3_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR3_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR3_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR3_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR3_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR3_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR3_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR3_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR4 : (MATRIX Offset: 0x0210) Security Slave 4 Register -------- */\r
+#define MATRIX_SSR4_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR4_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR4_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR4_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR4_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR4_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR4_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR4_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR4_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR4_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR5 : (MATRIX Offset: 0x0214) Security Slave 5 Register -------- */\r
+#define MATRIX_SSR5_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR5_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR5_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR5_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR5_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR5_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR5_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR5_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR5_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR5_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR6 : (MATRIX Offset: 0x0218) Security Slave 6 Register -------- */\r
+#define MATRIX_SSR6_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR6_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR6_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR6_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR6_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR6_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR6_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR6_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR6_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR6_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR7 : (MATRIX Offset: 0x021C) Security Slave 7 Register -------- */\r
+#define MATRIX_SSR7_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR7_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR7_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR7_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR7_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR7_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR7_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR7_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR7_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR7_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR8 : (MATRIX Offset: 0x0220) Security Slave 8 Register -------- */\r
+#define MATRIX_SSR8_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR8_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR8_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR8_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR8_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR8_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR8_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR8_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR8_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR8_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR9 : (MATRIX Offset: 0x0224) Security Slave 9 Register -------- */\r
+#define MATRIX_SSR9_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR9_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR9_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR9_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR9_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR9_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR9_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR9_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR9_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR9_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR10 : (MATRIX Offset: 0x0228) Security Slave 10 Register -------- */\r
+#define MATRIX_SSR10_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR10_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR10_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR10_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR10_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR10_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR10_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR10_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR10_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR10_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR11 : (MATRIX Offset: 0x022C) Security Slave 11 Register -------- */\r
+#define MATRIX_SSR11_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR11_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR11_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR11_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR11_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR11_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR11_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR11_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR11_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR11_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SSR12 : (MATRIX Offset: 0x0230) Security Slave 12 Register -------- */\r
+#define MATRIX_SSR12_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR12_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR12_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR12_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR12_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR12_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR12_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR12_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */\r
+#define MATRIX_SSR12_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */\r
+#define MATRIX_SSR12_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */\r
+/* -------- MATRIX_SASSR0 : (MATRIX Offset: 0x0240) Security Areas Split Slave 0 Register -------- */\r
+#define MATRIX_SASSR0_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR0_SASPLIT0_Msk (0xfu << MATRIX_SASSR0_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR0_SASPLIT0(value) ((MATRIX_SASSR0_SASPLIT0_Msk & ((value) << MATRIX_SASSR0_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR0_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR0_SASPLIT1_Msk (0xfu << MATRIX_SASSR0_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR0_SASPLIT1(value) ((MATRIX_SASSR0_SASPLIT1_Msk & ((value) << MATRIX_SASSR0_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR0_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR0_SASPLIT2_Msk (0xfu << MATRIX_SASSR0_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR0_SASPLIT2(value) ((MATRIX_SASSR0_SASPLIT2_Msk & ((value) << MATRIX_SASSR0_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR0_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR0_SASPLIT3_Msk (0xfu << MATRIX_SASSR0_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR0_SASPLIT3(value) ((MATRIX_SASSR0_SASPLIT3_Msk & ((value) << MATRIX_SASSR0_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR0_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR0_SASPLIT4_Msk (0xfu << MATRIX_SASSR0_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR0_SASPLIT4(value) ((MATRIX_SASSR0_SASPLIT4_Msk & ((value) << MATRIX_SASSR0_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR0_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR0_SASPLIT5_Msk (0xfu << MATRIX_SASSR0_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR0_SASPLIT5(value) ((MATRIX_SASSR0_SASPLIT5_Msk & ((value) << MATRIX_SASSR0_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR0_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR0_SASPLIT6_Msk (0xfu << MATRIX_SASSR0_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR0_SASPLIT6(value) ((MATRIX_SASSR0_SASPLIT6_Msk & ((value) << MATRIX_SASSR0_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR0_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR0_SASPLIT7_Msk (0xfu << MATRIX_SASSR0_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR0_SASPLIT7(value) ((MATRIX_SASSR0_SASPLIT7_Msk & ((value) << MATRIX_SASSR0_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR1 : (MATRIX Offset: 0x0244) Security Areas Split Slave 1 Register -------- */\r
+#define MATRIX_SASSR1_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR1_SASPLIT0_Msk (0xfu << MATRIX_SASSR1_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR1_SASPLIT0(value) ((MATRIX_SASSR1_SASPLIT0_Msk & ((value) << MATRIX_SASSR1_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR1_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR1_SASPLIT1_Msk (0xfu << MATRIX_SASSR1_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR1_SASPLIT1(value) ((MATRIX_SASSR1_SASPLIT1_Msk & ((value) << MATRIX_SASSR1_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR1_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR1_SASPLIT2_Msk (0xfu << MATRIX_SASSR1_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR1_SASPLIT2(value) ((MATRIX_SASSR1_SASPLIT2_Msk & ((value) << MATRIX_SASSR1_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR1_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR1_SASPLIT3_Msk (0xfu << MATRIX_SASSR1_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR1_SASPLIT3(value) ((MATRIX_SASSR1_SASPLIT3_Msk & ((value) << MATRIX_SASSR1_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR1_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR1_SASPLIT4_Msk (0xfu << MATRIX_SASSR1_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR1_SASPLIT4(value) ((MATRIX_SASSR1_SASPLIT4_Msk & ((value) << MATRIX_SASSR1_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR1_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR1_SASPLIT5_Msk (0xfu << MATRIX_SASSR1_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR1_SASPLIT5(value) ((MATRIX_SASSR1_SASPLIT5_Msk & ((value) << MATRIX_SASSR1_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR1_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR1_SASPLIT6_Msk (0xfu << MATRIX_SASSR1_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR1_SASPLIT6(value) ((MATRIX_SASSR1_SASPLIT6_Msk & ((value) << MATRIX_SASSR1_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR1_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR1_SASPLIT7_Msk (0xfu << MATRIX_SASSR1_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR1_SASPLIT7(value) ((MATRIX_SASSR1_SASPLIT7_Msk & ((value) << MATRIX_SASSR1_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR2 : (MATRIX Offset: 0x0248) Security Areas Split Slave 2 Register -------- */\r
+#define MATRIX_SASSR2_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR2_SASPLIT0_Msk (0xfu << MATRIX_SASSR2_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR2_SASPLIT0(value) ((MATRIX_SASSR2_SASPLIT0_Msk & ((value) << MATRIX_SASSR2_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR2_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR2_SASPLIT1_Msk (0xfu << MATRIX_SASSR2_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR2_SASPLIT1(value) ((MATRIX_SASSR2_SASPLIT1_Msk & ((value) << MATRIX_SASSR2_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR2_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR2_SASPLIT2_Msk (0xfu << MATRIX_SASSR2_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR2_SASPLIT2(value) ((MATRIX_SASSR2_SASPLIT2_Msk & ((value) << MATRIX_SASSR2_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR2_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR2_SASPLIT3_Msk (0xfu << MATRIX_SASSR2_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR2_SASPLIT3(value) ((MATRIX_SASSR2_SASPLIT3_Msk & ((value) << MATRIX_SASSR2_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR2_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR2_SASPLIT4_Msk (0xfu << MATRIX_SASSR2_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR2_SASPLIT4(value) ((MATRIX_SASSR2_SASPLIT4_Msk & ((value) << MATRIX_SASSR2_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR2_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR2_SASPLIT5_Msk (0xfu << MATRIX_SASSR2_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR2_SASPLIT5(value) ((MATRIX_SASSR2_SASPLIT5_Msk & ((value) << MATRIX_SASSR2_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR2_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR2_SASPLIT6_Msk (0xfu << MATRIX_SASSR2_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR2_SASPLIT6(value) ((MATRIX_SASSR2_SASPLIT6_Msk & ((value) << MATRIX_SASSR2_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR2_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR2_SASPLIT7_Msk (0xfu << MATRIX_SASSR2_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR2_SASPLIT7(value) ((MATRIX_SASSR2_SASPLIT7_Msk & ((value) << MATRIX_SASSR2_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR3 : (MATRIX Offset: 0x024C) Security Areas Split Slave 3 Register -------- */\r
+#define MATRIX_SASSR3_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR3_SASPLIT0_Msk (0xfu << MATRIX_SASSR3_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR3_SASPLIT0(value) ((MATRIX_SASSR3_SASPLIT0_Msk & ((value) << MATRIX_SASSR3_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR3_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR3_SASPLIT1_Msk (0xfu << MATRIX_SASSR3_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR3_SASPLIT1(value) ((MATRIX_SASSR3_SASPLIT1_Msk & ((value) << MATRIX_SASSR3_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR3_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR3_SASPLIT2_Msk (0xfu << MATRIX_SASSR3_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR3_SASPLIT2(value) ((MATRIX_SASSR3_SASPLIT2_Msk & ((value) << MATRIX_SASSR3_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR3_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR3_SASPLIT3_Msk (0xfu << MATRIX_SASSR3_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR3_SASPLIT3(value) ((MATRIX_SASSR3_SASPLIT3_Msk & ((value) << MATRIX_SASSR3_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR3_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR3_SASPLIT4_Msk (0xfu << MATRIX_SASSR3_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR3_SASPLIT4(value) ((MATRIX_SASSR3_SASPLIT4_Msk & ((value) << MATRIX_SASSR3_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR3_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR3_SASPLIT5_Msk (0xfu << MATRIX_SASSR3_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR3_SASPLIT5(value) ((MATRIX_SASSR3_SASPLIT5_Msk & ((value) << MATRIX_SASSR3_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR3_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR3_SASPLIT6_Msk (0xfu << MATRIX_SASSR3_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR3_SASPLIT6(value) ((MATRIX_SASSR3_SASPLIT6_Msk & ((value) << MATRIX_SASSR3_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR3_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR3_SASPLIT7_Msk (0xfu << MATRIX_SASSR3_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR3_SASPLIT7(value) ((MATRIX_SASSR3_SASPLIT7_Msk & ((value) << MATRIX_SASSR3_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR4 : (MATRIX Offset: 0x0250) Security Areas Split Slave 4 Register -------- */\r
+#define MATRIX_SASSR4_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR4_SASPLIT0_Msk (0xfu << MATRIX_SASSR4_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR4_SASPLIT0(value) ((MATRIX_SASSR4_SASPLIT0_Msk & ((value) << MATRIX_SASSR4_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR4_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR4_SASPLIT1_Msk (0xfu << MATRIX_SASSR4_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR4_SASPLIT1(value) ((MATRIX_SASSR4_SASPLIT1_Msk & ((value) << MATRIX_SASSR4_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR4_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR4_SASPLIT2_Msk (0xfu << MATRIX_SASSR4_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR4_SASPLIT2(value) ((MATRIX_SASSR4_SASPLIT2_Msk & ((value) << MATRIX_SASSR4_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR4_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR4_SASPLIT3_Msk (0xfu << MATRIX_SASSR4_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR4_SASPLIT3(value) ((MATRIX_SASSR4_SASPLIT3_Msk & ((value) << MATRIX_SASSR4_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR4_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR4_SASPLIT4_Msk (0xfu << MATRIX_SASSR4_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR4_SASPLIT4(value) ((MATRIX_SASSR4_SASPLIT4_Msk & ((value) << MATRIX_SASSR4_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR4_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR4_SASPLIT5_Msk (0xfu << MATRIX_SASSR4_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR4_SASPLIT5(value) ((MATRIX_SASSR4_SASPLIT5_Msk & ((value) << MATRIX_SASSR4_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR4_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR4_SASPLIT6_Msk (0xfu << MATRIX_SASSR4_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR4_SASPLIT6(value) ((MATRIX_SASSR4_SASPLIT6_Msk & ((value) << MATRIX_SASSR4_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR4_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR4_SASPLIT7_Msk (0xfu << MATRIX_SASSR4_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR4_SASPLIT7(value) ((MATRIX_SASSR4_SASPLIT7_Msk & ((value) << MATRIX_SASSR4_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR5 : (MATRIX Offset: 0x0254) Security Areas Split Slave 5 Register -------- */\r
+#define MATRIX_SASSR5_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR5_SASPLIT0_Msk (0xfu << MATRIX_SASSR5_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR5_SASPLIT0(value) ((MATRIX_SASSR5_SASPLIT0_Msk & ((value) << MATRIX_SASSR5_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR5_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR5_SASPLIT1_Msk (0xfu << MATRIX_SASSR5_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR5_SASPLIT1(value) ((MATRIX_SASSR5_SASPLIT1_Msk & ((value) << MATRIX_SASSR5_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR5_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR5_SASPLIT2_Msk (0xfu << MATRIX_SASSR5_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR5_SASPLIT2(value) ((MATRIX_SASSR5_SASPLIT2_Msk & ((value) << MATRIX_SASSR5_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR5_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR5_SASPLIT3_Msk (0xfu << MATRIX_SASSR5_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR5_SASPLIT3(value) ((MATRIX_SASSR5_SASPLIT3_Msk & ((value) << MATRIX_SASSR5_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR5_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR5_SASPLIT4_Msk (0xfu << MATRIX_SASSR5_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR5_SASPLIT4(value) ((MATRIX_SASSR5_SASPLIT4_Msk & ((value) << MATRIX_SASSR5_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR5_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR5_SASPLIT5_Msk (0xfu << MATRIX_SASSR5_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR5_SASPLIT5(value) ((MATRIX_SASSR5_SASPLIT5_Msk & ((value) << MATRIX_SASSR5_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR5_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR5_SASPLIT6_Msk (0xfu << MATRIX_SASSR5_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR5_SASPLIT6(value) ((MATRIX_SASSR5_SASPLIT6_Msk & ((value) << MATRIX_SASSR5_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR5_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR5_SASPLIT7_Msk (0xfu << MATRIX_SASSR5_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR5_SASPLIT7(value) ((MATRIX_SASSR5_SASPLIT7_Msk & ((value) << MATRIX_SASSR5_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR6 : (MATRIX Offset: 0x0258) Security Areas Split Slave 6 Register -------- */\r
+#define MATRIX_SASSR6_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR6_SASPLIT0_Msk (0xfu << MATRIX_SASSR6_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR6_SASPLIT0(value) ((MATRIX_SASSR6_SASPLIT0_Msk & ((value) << MATRIX_SASSR6_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR6_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR6_SASPLIT1_Msk (0xfu << MATRIX_SASSR6_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR6_SASPLIT1(value) ((MATRIX_SASSR6_SASPLIT1_Msk & ((value) << MATRIX_SASSR6_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR6_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR6_SASPLIT2_Msk (0xfu << MATRIX_SASSR6_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR6_SASPLIT2(value) ((MATRIX_SASSR6_SASPLIT2_Msk & ((value) << MATRIX_SASSR6_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR6_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR6_SASPLIT3_Msk (0xfu << MATRIX_SASSR6_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR6_SASPLIT3(value) ((MATRIX_SASSR6_SASPLIT3_Msk & ((value) << MATRIX_SASSR6_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR6_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR6_SASPLIT4_Msk (0xfu << MATRIX_SASSR6_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR6_SASPLIT4(value) ((MATRIX_SASSR6_SASPLIT4_Msk & ((value) << MATRIX_SASSR6_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR6_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR6_SASPLIT5_Msk (0xfu << MATRIX_SASSR6_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR6_SASPLIT5(value) ((MATRIX_SASSR6_SASPLIT5_Msk & ((value) << MATRIX_SASSR6_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR6_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR6_SASPLIT6_Msk (0xfu << MATRIX_SASSR6_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR6_SASPLIT6(value) ((MATRIX_SASSR6_SASPLIT6_Msk & ((value) << MATRIX_SASSR6_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR6_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR6_SASPLIT7_Msk (0xfu << MATRIX_SASSR6_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR6_SASPLIT7(value) ((MATRIX_SASSR6_SASPLIT7_Msk & ((value) << MATRIX_SASSR6_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR7 : (MATRIX Offset: 0x025C) Security Areas Split Slave 7 Register -------- */\r
+#define MATRIX_SASSR7_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR7_SASPLIT0_Msk (0xfu << MATRIX_SASSR7_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR7_SASPLIT0(value) ((MATRIX_SASSR7_SASPLIT0_Msk & ((value) << MATRIX_SASSR7_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR7_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR7_SASPLIT1_Msk (0xfu << MATRIX_SASSR7_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR7_SASPLIT1(value) ((MATRIX_SASSR7_SASPLIT1_Msk & ((value) << MATRIX_SASSR7_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR7_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR7_SASPLIT2_Msk (0xfu << MATRIX_SASSR7_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR7_SASPLIT2(value) ((MATRIX_SASSR7_SASPLIT2_Msk & ((value) << MATRIX_SASSR7_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR7_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR7_SASPLIT3_Msk (0xfu << MATRIX_SASSR7_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR7_SASPLIT3(value) ((MATRIX_SASSR7_SASPLIT3_Msk & ((value) << MATRIX_SASSR7_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR7_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR7_SASPLIT4_Msk (0xfu << MATRIX_SASSR7_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR7_SASPLIT4(value) ((MATRIX_SASSR7_SASPLIT4_Msk & ((value) << MATRIX_SASSR7_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR7_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR7_SASPLIT5_Msk (0xfu << MATRIX_SASSR7_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR7_SASPLIT5(value) ((MATRIX_SASSR7_SASPLIT5_Msk & ((value) << MATRIX_SASSR7_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR7_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR7_SASPLIT6_Msk (0xfu << MATRIX_SASSR7_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR7_SASPLIT6(value) ((MATRIX_SASSR7_SASPLIT6_Msk & ((value) << MATRIX_SASSR7_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR7_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR7_SASPLIT7_Msk (0xfu << MATRIX_SASSR7_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR7_SASPLIT7(value) ((MATRIX_SASSR7_SASPLIT7_Msk & ((value) << MATRIX_SASSR7_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR8 : (MATRIX Offset: 0x0260) Security Areas Split Slave 8 Register -------- */\r
+#define MATRIX_SASSR8_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR8_SASPLIT0_Msk (0xfu << MATRIX_SASSR8_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR8_SASPLIT0(value) ((MATRIX_SASSR8_SASPLIT0_Msk & ((value) << MATRIX_SASSR8_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR8_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR8_SASPLIT1_Msk (0xfu << MATRIX_SASSR8_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR8_SASPLIT1(value) ((MATRIX_SASSR8_SASPLIT1_Msk & ((value) << MATRIX_SASSR8_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR8_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR8_SASPLIT2_Msk (0xfu << MATRIX_SASSR8_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR8_SASPLIT2(value) ((MATRIX_SASSR8_SASPLIT2_Msk & ((value) << MATRIX_SASSR8_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR8_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR8_SASPLIT3_Msk (0xfu << MATRIX_SASSR8_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR8_SASPLIT3(value) ((MATRIX_SASSR8_SASPLIT3_Msk & ((value) << MATRIX_SASSR8_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR8_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR8_SASPLIT4_Msk (0xfu << MATRIX_SASSR8_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR8_SASPLIT4(value) ((MATRIX_SASSR8_SASPLIT4_Msk & ((value) << MATRIX_SASSR8_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR8_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR8_SASPLIT5_Msk (0xfu << MATRIX_SASSR8_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR8_SASPLIT5(value) ((MATRIX_SASSR8_SASPLIT5_Msk & ((value) << MATRIX_SASSR8_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR8_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR8_SASPLIT6_Msk (0xfu << MATRIX_SASSR8_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR8_SASPLIT6(value) ((MATRIX_SASSR8_SASPLIT6_Msk & ((value) << MATRIX_SASSR8_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR8_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR8_SASPLIT7_Msk (0xfu << MATRIX_SASSR8_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR8_SASPLIT7(value) ((MATRIX_SASSR8_SASPLIT7_Msk & ((value) << MATRIX_SASSR8_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR9 : (MATRIX Offset: 0x0264) Security Areas Split Slave 9 Register -------- */\r
+#define MATRIX_SASSR9_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR9_SASPLIT0_Msk (0xfu << MATRIX_SASSR9_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR9_SASPLIT0(value) ((MATRIX_SASSR9_SASPLIT0_Msk & ((value) << MATRIX_SASSR9_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR9_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR9_SASPLIT1_Msk (0xfu << MATRIX_SASSR9_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR9_SASPLIT1(value) ((MATRIX_SASSR9_SASPLIT1_Msk & ((value) << MATRIX_SASSR9_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR9_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR9_SASPLIT2_Msk (0xfu << MATRIX_SASSR9_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR9_SASPLIT2(value) ((MATRIX_SASSR9_SASPLIT2_Msk & ((value) << MATRIX_SASSR9_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR9_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR9_SASPLIT3_Msk (0xfu << MATRIX_SASSR9_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR9_SASPLIT3(value) ((MATRIX_SASSR9_SASPLIT3_Msk & ((value) << MATRIX_SASSR9_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR9_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR9_SASPLIT4_Msk (0xfu << MATRIX_SASSR9_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR9_SASPLIT4(value) ((MATRIX_SASSR9_SASPLIT4_Msk & ((value) << MATRIX_SASSR9_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR9_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR9_SASPLIT5_Msk (0xfu << MATRIX_SASSR9_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR9_SASPLIT5(value) ((MATRIX_SASSR9_SASPLIT5_Msk & ((value) << MATRIX_SASSR9_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR9_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR9_SASPLIT6_Msk (0xfu << MATRIX_SASSR9_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR9_SASPLIT6(value) ((MATRIX_SASSR9_SASPLIT6_Msk & ((value) << MATRIX_SASSR9_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR9_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR9_SASPLIT7_Msk (0xfu << MATRIX_SASSR9_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR9_SASPLIT7(value) ((MATRIX_SASSR9_SASPLIT7_Msk & ((value) << MATRIX_SASSR9_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR10 : (MATRIX Offset: 0x0268) Security Areas Split Slave 10 Register -------- */\r
+#define MATRIX_SASSR10_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR10_SASPLIT0_Msk (0xfu << MATRIX_SASSR10_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR10_SASPLIT0(value) ((MATRIX_SASSR10_SASPLIT0_Msk & ((value) << MATRIX_SASSR10_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR10_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR10_SASPLIT1_Msk (0xfu << MATRIX_SASSR10_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR10_SASPLIT1(value) ((MATRIX_SASSR10_SASPLIT1_Msk & ((value) << MATRIX_SASSR10_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR10_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR10_SASPLIT2_Msk (0xfu << MATRIX_SASSR10_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR10_SASPLIT2(value) ((MATRIX_SASSR10_SASPLIT2_Msk & ((value) << MATRIX_SASSR10_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR10_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR10_SASPLIT3_Msk (0xfu << MATRIX_SASSR10_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR10_SASPLIT3(value) ((MATRIX_SASSR10_SASPLIT3_Msk & ((value) << MATRIX_SASSR10_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR10_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR10_SASPLIT4_Msk (0xfu << MATRIX_SASSR10_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR10_SASPLIT4(value) ((MATRIX_SASSR10_SASPLIT4_Msk & ((value) << MATRIX_SASSR10_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR10_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR10_SASPLIT5_Msk (0xfu << MATRIX_SASSR10_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR10_SASPLIT5(value) ((MATRIX_SASSR10_SASPLIT5_Msk & ((value) << MATRIX_SASSR10_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR10_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR10_SASPLIT6_Msk (0xfu << MATRIX_SASSR10_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR10_SASPLIT6(value) ((MATRIX_SASSR10_SASPLIT6_Msk & ((value) << MATRIX_SASSR10_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR10_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR10_SASPLIT7_Msk (0xfu << MATRIX_SASSR10_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR10_SASPLIT7(value) ((MATRIX_SASSR10_SASPLIT7_Msk & ((value) << MATRIX_SASSR10_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR11 : (MATRIX Offset: 0x026C) Security Areas Split Slave 11 Register -------- */\r
+#define MATRIX_SASSR11_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR11_SASPLIT0_Msk (0xfu << MATRIX_SASSR11_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR11_SASPLIT0(value) ((MATRIX_SASSR11_SASPLIT0_Msk & ((value) << MATRIX_SASSR11_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR11_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR11_SASPLIT1_Msk (0xfu << MATRIX_SASSR11_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR11_SASPLIT1(value) ((MATRIX_SASSR11_SASPLIT1_Msk & ((value) << MATRIX_SASSR11_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR11_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR11_SASPLIT2_Msk (0xfu << MATRIX_SASSR11_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR11_SASPLIT2(value) ((MATRIX_SASSR11_SASPLIT2_Msk & ((value) << MATRIX_SASSR11_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR11_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR11_SASPLIT3_Msk (0xfu << MATRIX_SASSR11_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR11_SASPLIT3(value) ((MATRIX_SASSR11_SASPLIT3_Msk & ((value) << MATRIX_SASSR11_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR11_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR11_SASPLIT4_Msk (0xfu << MATRIX_SASSR11_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR11_SASPLIT4(value) ((MATRIX_SASSR11_SASPLIT4_Msk & ((value) << MATRIX_SASSR11_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR11_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR11_SASPLIT5_Msk (0xfu << MATRIX_SASSR11_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR11_SASPLIT5(value) ((MATRIX_SASSR11_SASPLIT5_Msk & ((value) << MATRIX_SASSR11_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR11_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR11_SASPLIT6_Msk (0xfu << MATRIX_SASSR11_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR11_SASPLIT6(value) ((MATRIX_SASSR11_SASPLIT6_Msk & ((value) << MATRIX_SASSR11_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR11_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR11_SASPLIT7_Msk (0xfu << MATRIX_SASSR11_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR11_SASPLIT7(value) ((MATRIX_SASSR11_SASPLIT7_Msk & ((value) << MATRIX_SASSR11_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SASSR12 : (MATRIX Offset: 0x0270) Security Areas Split Slave 12 Register -------- */\r
+#define MATRIX_SASSR12_SASPLIT0_Pos 0\r
+#define MATRIX_SASSR12_SASPLIT0_Msk (0xfu << MATRIX_SASSR12_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR12_SASPLIT0(value) ((MATRIX_SASSR12_SASPLIT0_Msk & ((value) << MATRIX_SASSR12_SASPLIT0_Pos)))\r
+#define MATRIX_SASSR12_SASPLIT1_Pos 4\r
+#define MATRIX_SASSR12_SASPLIT1_Msk (0xfu << MATRIX_SASSR12_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR12_SASPLIT1(value) ((MATRIX_SASSR12_SASPLIT1_Msk & ((value) << MATRIX_SASSR12_SASPLIT1_Pos)))\r
+#define MATRIX_SASSR12_SASPLIT2_Pos 8\r
+#define MATRIX_SASSR12_SASPLIT2_Msk (0xfu << MATRIX_SASSR12_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR12_SASPLIT2(value) ((MATRIX_SASSR12_SASPLIT2_Msk & ((value) << MATRIX_SASSR12_SASPLIT2_Pos)))\r
+#define MATRIX_SASSR12_SASPLIT3_Pos 12\r
+#define MATRIX_SASSR12_SASPLIT3_Msk (0xfu << MATRIX_SASSR12_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR12_SASPLIT3(value) ((MATRIX_SASSR12_SASPLIT3_Msk & ((value) << MATRIX_SASSR12_SASPLIT3_Pos)))\r
+#define MATRIX_SASSR12_SASPLIT4_Pos 16\r
+#define MATRIX_SASSR12_SASPLIT4_Msk (0xfu << MATRIX_SASSR12_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR12_SASPLIT4(value) ((MATRIX_SASSR12_SASPLIT4_Msk & ((value) << MATRIX_SASSR12_SASPLIT4_Pos)))\r
+#define MATRIX_SASSR12_SASPLIT5_Pos 20\r
+#define MATRIX_SASSR12_SASPLIT5_Msk (0xfu << MATRIX_SASSR12_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR12_SASPLIT5(value) ((MATRIX_SASSR12_SASPLIT5_Msk & ((value) << MATRIX_SASSR12_SASPLIT5_Pos)))\r
+#define MATRIX_SASSR12_SASPLIT6_Pos 24\r
+#define MATRIX_SASSR12_SASPLIT6_Msk (0xfu << MATRIX_SASSR12_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR12_SASPLIT6(value) ((MATRIX_SASSR12_SASPLIT6_Msk & ((value) << MATRIX_SASSR12_SASPLIT6_Pos)))\r
+#define MATRIX_SASSR12_SASPLIT7_Pos 28\r
+#define MATRIX_SASSR12_SASPLIT7_Msk (0xfu << MATRIX_SASSR12_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */\r
+#define MATRIX_SASSR12_SASPLIT7(value) ((MATRIX_SASSR12_SASPLIT7_Msk & ((value) << MATRIX_SASSR12_SASPLIT7_Pos)))\r
+/* -------- MATRIX_SRTSR1 : (MATRIX Offset: 0x0284) Security Region Top Slave 1 Register -------- */\r
+#define MATRIX_SRTSR1_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR1_SRTOP0_Msk (0xfu << MATRIX_SRTSR1_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */\r
+#define MATRIX_SRTSR1_SRTOP0(value) ((MATRIX_SRTSR1_SRTOP0_Msk & ((value) << MATRIX_SRTSR1_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR1_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR1_SRTOP1_Msk (0xfu << MATRIX_SRTSR1_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */\r
+#define MATRIX_SRTSR1_SRTOP1(value) ((MATRIX_SRTSR1_SRTOP1_Msk & ((value) << MATRIX_SRTSR1_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR1_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR1_SRTOP2_Msk (0xfu << MATRIX_SRTSR1_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */\r
+#define MATRIX_SRTSR1_SRTOP2(value) ((MATRIX_SRTSR1_SRTOP2_Msk & ((value) << MATRIX_SRTSR1_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR1_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR1_SRTOP3_Msk (0xfu << MATRIX_SRTSR1_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */\r
+#define MATRIX_SRTSR1_SRTOP3(value) ((MATRIX_SRTSR1_SRTOP3_Msk & ((value) << MATRIX_SRTSR1_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR1_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR1_SRTOP4_Msk (0xfu << MATRIX_SRTSR1_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */\r
+#define MATRIX_SRTSR1_SRTOP4(value) ((MATRIX_SRTSR1_SRTOP4_Msk & ((value) << MATRIX_SRTSR1_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR1_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR1_SRTOP5_Msk (0xfu << MATRIX_SRTSR1_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */\r
+#define MATRIX_SRTSR1_SRTOP5(value) ((MATRIX_SRTSR1_SRTOP5_Msk & ((value) << MATRIX_SRTSR1_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR1_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR1_SRTOP6_Msk (0xfu << MATRIX_SRTSR1_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */\r
+#define MATRIX_SRTSR1_SRTOP6(value) ((MATRIX_SRTSR1_SRTOP6_Msk & ((value) << MATRIX_SRTSR1_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR1_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR1_SRTOP7_Msk (0xfu << MATRIX_SRTSR1_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */\r
+#define MATRIX_SRTSR1_SRTOP7(value) ((MATRIX_SRTSR1_SRTOP7_Msk & ((value) << MATRIX_SRTSR1_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR2 : (MATRIX Offset: 0x0288) Security Region Top Slave 2 Register -------- */\r
+#define MATRIX_SRTSR2_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR2_SRTOP0_Msk (0xfu << MATRIX_SRTSR2_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */\r
+#define MATRIX_SRTSR2_SRTOP0(value) ((MATRIX_SRTSR2_SRTOP0_Msk & ((value) << MATRIX_SRTSR2_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR2_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR2_SRTOP1_Msk (0xfu << MATRIX_SRTSR2_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */\r
+#define MATRIX_SRTSR2_SRTOP1(value) ((MATRIX_SRTSR2_SRTOP1_Msk & ((value) << MATRIX_SRTSR2_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR2_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR2_SRTOP2_Msk (0xfu << MATRIX_SRTSR2_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */\r
+#define MATRIX_SRTSR2_SRTOP2(value) ((MATRIX_SRTSR2_SRTOP2_Msk & ((value) << MATRIX_SRTSR2_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR2_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR2_SRTOP3_Msk (0xfu << MATRIX_SRTSR2_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */\r
+#define MATRIX_SRTSR2_SRTOP3(value) ((MATRIX_SRTSR2_SRTOP3_Msk & ((value) << MATRIX_SRTSR2_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR2_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR2_SRTOP4_Msk (0xfu << MATRIX_SRTSR2_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */\r
+#define MATRIX_SRTSR2_SRTOP4(value) ((MATRIX_SRTSR2_SRTOP4_Msk & ((value) << MATRIX_SRTSR2_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR2_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR2_SRTOP5_Msk (0xfu << MATRIX_SRTSR2_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */\r
+#define MATRIX_SRTSR2_SRTOP5(value) ((MATRIX_SRTSR2_SRTOP5_Msk & ((value) << MATRIX_SRTSR2_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR2_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR2_SRTOP6_Msk (0xfu << MATRIX_SRTSR2_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */\r
+#define MATRIX_SRTSR2_SRTOP6(value) ((MATRIX_SRTSR2_SRTOP6_Msk & ((value) << MATRIX_SRTSR2_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR2_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR2_SRTOP7_Msk (0xfu << MATRIX_SRTSR2_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */\r
+#define MATRIX_SRTSR2_SRTOP7(value) ((MATRIX_SRTSR2_SRTOP7_Msk & ((value) << MATRIX_SRTSR2_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR3 : (MATRIX Offset: 0x028C) Security Region Top Slave 3 Register -------- */\r
+#define MATRIX_SRTSR3_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR3_SRTOP0_Msk (0xfu << MATRIX_SRTSR3_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */\r
+#define MATRIX_SRTSR3_SRTOP0(value) ((MATRIX_SRTSR3_SRTOP0_Msk & ((value) << MATRIX_SRTSR3_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR3_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR3_SRTOP1_Msk (0xfu << MATRIX_SRTSR3_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */\r
+#define MATRIX_SRTSR3_SRTOP1(value) ((MATRIX_SRTSR3_SRTOP1_Msk & ((value) << MATRIX_SRTSR3_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR3_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR3_SRTOP2_Msk (0xfu << MATRIX_SRTSR3_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */\r
+#define MATRIX_SRTSR3_SRTOP2(value) ((MATRIX_SRTSR3_SRTOP2_Msk & ((value) << MATRIX_SRTSR3_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR3_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR3_SRTOP3_Msk (0xfu << MATRIX_SRTSR3_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */\r
+#define MATRIX_SRTSR3_SRTOP3(value) ((MATRIX_SRTSR3_SRTOP3_Msk & ((value) << MATRIX_SRTSR3_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR3_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR3_SRTOP4_Msk (0xfu << MATRIX_SRTSR3_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */\r
+#define MATRIX_SRTSR3_SRTOP4(value) ((MATRIX_SRTSR3_SRTOP4_Msk & ((value) << MATRIX_SRTSR3_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR3_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR3_SRTOP5_Msk (0xfu << MATRIX_SRTSR3_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */\r
+#define MATRIX_SRTSR3_SRTOP5(value) ((MATRIX_SRTSR3_SRTOP5_Msk & ((value) << MATRIX_SRTSR3_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR3_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR3_SRTOP6_Msk (0xfu << MATRIX_SRTSR3_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */\r
+#define MATRIX_SRTSR3_SRTOP6(value) ((MATRIX_SRTSR3_SRTOP6_Msk & ((value) << MATRIX_SRTSR3_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR3_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR3_SRTOP7_Msk (0xfu << MATRIX_SRTSR3_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */\r
+#define MATRIX_SRTSR3_SRTOP7(value) ((MATRIX_SRTSR3_SRTOP7_Msk & ((value) << MATRIX_SRTSR3_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR4 : (MATRIX Offset: 0x0290) Security Region Top Slave 4 Register -------- */\r
+#define MATRIX_SRTSR4_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR4_SRTOP0_Msk (0xfu << MATRIX_SRTSR4_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */\r
+#define MATRIX_SRTSR4_SRTOP0(value) ((MATRIX_SRTSR4_SRTOP0_Msk & ((value) << MATRIX_SRTSR4_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR4_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR4_SRTOP1_Msk (0xfu << MATRIX_SRTSR4_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */\r
+#define MATRIX_SRTSR4_SRTOP1(value) ((MATRIX_SRTSR4_SRTOP1_Msk & ((value) << MATRIX_SRTSR4_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR4_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR4_SRTOP2_Msk (0xfu << MATRIX_SRTSR4_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */\r
+#define MATRIX_SRTSR4_SRTOP2(value) ((MATRIX_SRTSR4_SRTOP2_Msk & ((value) << MATRIX_SRTSR4_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR4_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR4_SRTOP3_Msk (0xfu << MATRIX_SRTSR4_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */\r
+#define MATRIX_SRTSR4_SRTOP3(value) ((MATRIX_SRTSR4_SRTOP3_Msk & ((value) << MATRIX_SRTSR4_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR4_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR4_SRTOP4_Msk (0xfu << MATRIX_SRTSR4_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */\r
+#define MATRIX_SRTSR4_SRTOP4(value) ((MATRIX_SRTSR4_SRTOP4_Msk & ((value) << MATRIX_SRTSR4_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR4_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR4_SRTOP5_Msk (0xfu << MATRIX_SRTSR4_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */\r
+#define MATRIX_SRTSR4_SRTOP5(value) ((MATRIX_SRTSR4_SRTOP5_Msk & ((value) << MATRIX_SRTSR4_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR4_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR4_SRTOP6_Msk (0xfu << MATRIX_SRTSR4_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */\r
+#define MATRIX_SRTSR4_SRTOP6(value) ((MATRIX_SRTSR4_SRTOP6_Msk & ((value) << MATRIX_SRTSR4_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR4_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR4_SRTOP7_Msk (0xfu << MATRIX_SRTSR4_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */\r
+#define MATRIX_SRTSR4_SRTOP7(value) ((MATRIX_SRTSR4_SRTOP7_Msk & ((value) << MATRIX_SRTSR4_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR5 : (MATRIX Offset: 0x0294) Security Region Top Slave 5 Register -------- */\r
+#define MATRIX_SRTSR5_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR5_SRTOP0_Msk (0xfu << MATRIX_SRTSR5_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */\r
+#define MATRIX_SRTSR5_SRTOP0(value) ((MATRIX_SRTSR5_SRTOP0_Msk & ((value) << MATRIX_SRTSR5_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR5_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR5_SRTOP1_Msk (0xfu << MATRIX_SRTSR5_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */\r
+#define MATRIX_SRTSR5_SRTOP1(value) ((MATRIX_SRTSR5_SRTOP1_Msk & ((value) << MATRIX_SRTSR5_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR5_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR5_SRTOP2_Msk (0xfu << MATRIX_SRTSR5_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */\r
+#define MATRIX_SRTSR5_SRTOP2(value) ((MATRIX_SRTSR5_SRTOP2_Msk & ((value) << MATRIX_SRTSR5_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR5_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR5_SRTOP3_Msk (0xfu << MATRIX_SRTSR5_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */\r
+#define MATRIX_SRTSR5_SRTOP3(value) ((MATRIX_SRTSR5_SRTOP3_Msk & ((value) << MATRIX_SRTSR5_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR5_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR5_SRTOP4_Msk (0xfu << MATRIX_SRTSR5_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */\r
+#define MATRIX_SRTSR5_SRTOP4(value) ((MATRIX_SRTSR5_SRTOP4_Msk & ((value) << MATRIX_SRTSR5_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR5_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR5_SRTOP5_Msk (0xfu << MATRIX_SRTSR5_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */\r
+#define MATRIX_SRTSR5_SRTOP5(value) ((MATRIX_SRTSR5_SRTOP5_Msk & ((value) << MATRIX_SRTSR5_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR5_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR5_SRTOP6_Msk (0xfu << MATRIX_SRTSR5_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */\r
+#define MATRIX_SRTSR5_SRTOP6(value) ((MATRIX_SRTSR5_SRTOP6_Msk & ((value) << MATRIX_SRTSR5_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR5_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR5_SRTOP7_Msk (0xfu << MATRIX_SRTSR5_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */\r
+#define MATRIX_SRTSR5_SRTOP7(value) ((MATRIX_SRTSR5_SRTOP7_Msk & ((value) << MATRIX_SRTSR5_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR6 : (MATRIX Offset: 0x0298) Security Region Top Slave 6 Register -------- */\r
+#define MATRIX_SRTSR6_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR6_SRTOP0_Msk (0xfu << MATRIX_SRTSR6_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */\r
+#define MATRIX_SRTSR6_SRTOP0(value) ((MATRIX_SRTSR6_SRTOP0_Msk & ((value) << MATRIX_SRTSR6_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR6_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR6_SRTOP1_Msk (0xfu << MATRIX_SRTSR6_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */\r
+#define MATRIX_SRTSR6_SRTOP1(value) ((MATRIX_SRTSR6_SRTOP1_Msk & ((value) << MATRIX_SRTSR6_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR6_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR6_SRTOP2_Msk (0xfu << MATRIX_SRTSR6_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */\r
+#define MATRIX_SRTSR6_SRTOP2(value) ((MATRIX_SRTSR6_SRTOP2_Msk & ((value) << MATRIX_SRTSR6_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR6_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR6_SRTOP3_Msk (0xfu << MATRIX_SRTSR6_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */\r
+#define MATRIX_SRTSR6_SRTOP3(value) ((MATRIX_SRTSR6_SRTOP3_Msk & ((value) << MATRIX_SRTSR6_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR6_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR6_SRTOP4_Msk (0xfu << MATRIX_SRTSR6_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */\r
+#define MATRIX_SRTSR6_SRTOP4(value) ((MATRIX_SRTSR6_SRTOP4_Msk & ((value) << MATRIX_SRTSR6_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR6_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR6_SRTOP5_Msk (0xfu << MATRIX_SRTSR6_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */\r
+#define MATRIX_SRTSR6_SRTOP5(value) ((MATRIX_SRTSR6_SRTOP5_Msk & ((value) << MATRIX_SRTSR6_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR6_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR6_SRTOP6_Msk (0xfu << MATRIX_SRTSR6_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */\r
+#define MATRIX_SRTSR6_SRTOP6(value) ((MATRIX_SRTSR6_SRTOP6_Msk & ((value) << MATRIX_SRTSR6_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR6_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR6_SRTOP7_Msk (0xfu << MATRIX_SRTSR6_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */\r
+#define MATRIX_SRTSR6_SRTOP7(value) ((MATRIX_SRTSR6_SRTOP7_Msk & ((value) << MATRIX_SRTSR6_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR7 : (MATRIX Offset: 0x029C) Security Region Top Slave 7 Register -------- */\r
+#define MATRIX_SRTSR7_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR7_SRTOP0_Msk (0xfu << MATRIX_SRTSR7_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */\r
+#define MATRIX_SRTSR7_SRTOP0(value) ((MATRIX_SRTSR7_SRTOP0_Msk & ((value) << MATRIX_SRTSR7_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR7_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR7_SRTOP1_Msk (0xfu << MATRIX_SRTSR7_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */\r
+#define MATRIX_SRTSR7_SRTOP1(value) ((MATRIX_SRTSR7_SRTOP1_Msk & ((value) << MATRIX_SRTSR7_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR7_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR7_SRTOP2_Msk (0xfu << MATRIX_SRTSR7_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */\r
+#define MATRIX_SRTSR7_SRTOP2(value) ((MATRIX_SRTSR7_SRTOP2_Msk & ((value) << MATRIX_SRTSR7_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR7_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR7_SRTOP3_Msk (0xfu << MATRIX_SRTSR7_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */\r
+#define MATRIX_SRTSR7_SRTOP3(value) ((MATRIX_SRTSR7_SRTOP3_Msk & ((value) << MATRIX_SRTSR7_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR7_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR7_SRTOP4_Msk (0xfu << MATRIX_SRTSR7_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */\r
+#define MATRIX_SRTSR7_SRTOP4(value) ((MATRIX_SRTSR7_SRTOP4_Msk & ((value) << MATRIX_SRTSR7_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR7_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR7_SRTOP5_Msk (0xfu << MATRIX_SRTSR7_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */\r
+#define MATRIX_SRTSR7_SRTOP5(value) ((MATRIX_SRTSR7_SRTOP5_Msk & ((value) << MATRIX_SRTSR7_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR7_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR7_SRTOP6_Msk (0xfu << MATRIX_SRTSR7_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */\r
+#define MATRIX_SRTSR7_SRTOP6(value) ((MATRIX_SRTSR7_SRTOP6_Msk & ((value) << MATRIX_SRTSR7_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR7_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR7_SRTOP7_Msk (0xfu << MATRIX_SRTSR7_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */\r
+#define MATRIX_SRTSR7_SRTOP7(value) ((MATRIX_SRTSR7_SRTOP7_Msk & ((value) << MATRIX_SRTSR7_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR8 : (MATRIX Offset: 0x02A0) Security Region Top Slave 8 Register -------- */\r
+#define MATRIX_SRTSR8_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR8_SRTOP0_Msk (0xfu << MATRIX_SRTSR8_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */\r
+#define MATRIX_SRTSR8_SRTOP0(value) ((MATRIX_SRTSR8_SRTOP0_Msk & ((value) << MATRIX_SRTSR8_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR8_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR8_SRTOP1_Msk (0xfu << MATRIX_SRTSR8_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */\r
+#define MATRIX_SRTSR8_SRTOP1(value) ((MATRIX_SRTSR8_SRTOP1_Msk & ((value) << MATRIX_SRTSR8_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR8_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR8_SRTOP2_Msk (0xfu << MATRIX_SRTSR8_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */\r
+#define MATRIX_SRTSR8_SRTOP2(value) ((MATRIX_SRTSR8_SRTOP2_Msk & ((value) << MATRIX_SRTSR8_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR8_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR8_SRTOP3_Msk (0xfu << MATRIX_SRTSR8_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */\r
+#define MATRIX_SRTSR8_SRTOP3(value) ((MATRIX_SRTSR8_SRTOP3_Msk & ((value) << MATRIX_SRTSR8_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR8_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR8_SRTOP4_Msk (0xfu << MATRIX_SRTSR8_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */\r
+#define MATRIX_SRTSR8_SRTOP4(value) ((MATRIX_SRTSR8_SRTOP4_Msk & ((value) << MATRIX_SRTSR8_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR8_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR8_SRTOP5_Msk (0xfu << MATRIX_SRTSR8_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */\r
+#define MATRIX_SRTSR8_SRTOP5(value) ((MATRIX_SRTSR8_SRTOP5_Msk & ((value) << MATRIX_SRTSR8_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR8_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR8_SRTOP6_Msk (0xfu << MATRIX_SRTSR8_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */\r
+#define MATRIX_SRTSR8_SRTOP6(value) ((MATRIX_SRTSR8_SRTOP6_Msk & ((value) << MATRIX_SRTSR8_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR8_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR8_SRTOP7_Msk (0xfu << MATRIX_SRTSR8_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */\r
+#define MATRIX_SRTSR8_SRTOP7(value) ((MATRIX_SRTSR8_SRTOP7_Msk & ((value) << MATRIX_SRTSR8_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR9 : (MATRIX Offset: 0x02A4) Security Region Top Slave 9 Register -------- */\r
+#define MATRIX_SRTSR9_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR9_SRTOP0_Msk (0xfu << MATRIX_SRTSR9_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */\r
+#define MATRIX_SRTSR9_SRTOP0(value) ((MATRIX_SRTSR9_SRTOP0_Msk & ((value) << MATRIX_SRTSR9_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR9_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR9_SRTOP1_Msk (0xfu << MATRIX_SRTSR9_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */\r
+#define MATRIX_SRTSR9_SRTOP1(value) ((MATRIX_SRTSR9_SRTOP1_Msk & ((value) << MATRIX_SRTSR9_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR9_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR9_SRTOP2_Msk (0xfu << MATRIX_SRTSR9_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */\r
+#define MATRIX_SRTSR9_SRTOP2(value) ((MATRIX_SRTSR9_SRTOP2_Msk & ((value) << MATRIX_SRTSR9_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR9_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR9_SRTOP3_Msk (0xfu << MATRIX_SRTSR9_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */\r
+#define MATRIX_SRTSR9_SRTOP3(value) ((MATRIX_SRTSR9_SRTOP3_Msk & ((value) << MATRIX_SRTSR9_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR9_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR9_SRTOP4_Msk (0xfu << MATRIX_SRTSR9_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */\r
+#define MATRIX_SRTSR9_SRTOP4(value) ((MATRIX_SRTSR9_SRTOP4_Msk & ((value) << MATRIX_SRTSR9_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR9_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR9_SRTOP5_Msk (0xfu << MATRIX_SRTSR9_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */\r
+#define MATRIX_SRTSR9_SRTOP5(value) ((MATRIX_SRTSR9_SRTOP5_Msk & ((value) << MATRIX_SRTSR9_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR9_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR9_SRTOP6_Msk (0xfu << MATRIX_SRTSR9_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */\r
+#define MATRIX_SRTSR9_SRTOP6(value) ((MATRIX_SRTSR9_SRTOP6_Msk & ((value) << MATRIX_SRTSR9_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR9_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR9_SRTOP7_Msk (0xfu << MATRIX_SRTSR9_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */\r
+#define MATRIX_SRTSR9_SRTOP7(value) ((MATRIX_SRTSR9_SRTOP7_Msk & ((value) << MATRIX_SRTSR9_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR10 : (MATRIX Offset: 0x02A8) Security Region Top Slave 10 Register -------- */\r
+#define MATRIX_SRTSR10_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR10_SRTOP0_Msk (0xfu << MATRIX_SRTSR10_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */\r
+#define MATRIX_SRTSR10_SRTOP0(value) ((MATRIX_SRTSR10_SRTOP0_Msk & ((value) << MATRIX_SRTSR10_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR10_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR10_SRTOP1_Msk (0xfu << MATRIX_SRTSR10_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */\r
+#define MATRIX_SRTSR10_SRTOP1(value) ((MATRIX_SRTSR10_SRTOP1_Msk & ((value) << MATRIX_SRTSR10_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR10_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR10_SRTOP2_Msk (0xfu << MATRIX_SRTSR10_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */\r
+#define MATRIX_SRTSR10_SRTOP2(value) ((MATRIX_SRTSR10_SRTOP2_Msk & ((value) << MATRIX_SRTSR10_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR10_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR10_SRTOP3_Msk (0xfu << MATRIX_SRTSR10_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */\r
+#define MATRIX_SRTSR10_SRTOP3(value) ((MATRIX_SRTSR10_SRTOP3_Msk & ((value) << MATRIX_SRTSR10_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR10_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR10_SRTOP4_Msk (0xfu << MATRIX_SRTSR10_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */\r
+#define MATRIX_SRTSR10_SRTOP4(value) ((MATRIX_SRTSR10_SRTOP4_Msk & ((value) << MATRIX_SRTSR10_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR10_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR10_SRTOP5_Msk (0xfu << MATRIX_SRTSR10_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */\r
+#define MATRIX_SRTSR10_SRTOP5(value) ((MATRIX_SRTSR10_SRTOP5_Msk & ((value) << MATRIX_SRTSR10_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR10_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR10_SRTOP6_Msk (0xfu << MATRIX_SRTSR10_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */\r
+#define MATRIX_SRTSR10_SRTOP6(value) ((MATRIX_SRTSR10_SRTOP6_Msk & ((value) << MATRIX_SRTSR10_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR10_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR10_SRTOP7_Msk (0xfu << MATRIX_SRTSR10_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */\r
+#define MATRIX_SRTSR10_SRTOP7(value) ((MATRIX_SRTSR10_SRTOP7_Msk & ((value) << MATRIX_SRTSR10_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR11 : (MATRIX Offset: 0x02AC) Security Region Top Slave 11 Register -------- */\r
+#define MATRIX_SRTSR11_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR11_SRTOP0_Msk (0xfu << MATRIX_SRTSR11_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */\r
+#define MATRIX_SRTSR11_SRTOP0(value) ((MATRIX_SRTSR11_SRTOP0_Msk & ((value) << MATRIX_SRTSR11_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR11_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR11_SRTOP1_Msk (0xfu << MATRIX_SRTSR11_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */\r
+#define MATRIX_SRTSR11_SRTOP1(value) ((MATRIX_SRTSR11_SRTOP1_Msk & ((value) << MATRIX_SRTSR11_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR11_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR11_SRTOP2_Msk (0xfu << MATRIX_SRTSR11_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */\r
+#define MATRIX_SRTSR11_SRTOP2(value) ((MATRIX_SRTSR11_SRTOP2_Msk & ((value) << MATRIX_SRTSR11_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR11_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR11_SRTOP3_Msk (0xfu << MATRIX_SRTSR11_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */\r
+#define MATRIX_SRTSR11_SRTOP3(value) ((MATRIX_SRTSR11_SRTOP3_Msk & ((value) << MATRIX_SRTSR11_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR11_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR11_SRTOP4_Msk (0xfu << MATRIX_SRTSR11_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */\r
+#define MATRIX_SRTSR11_SRTOP4(value) ((MATRIX_SRTSR11_SRTOP4_Msk & ((value) << MATRIX_SRTSR11_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR11_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR11_SRTOP5_Msk (0xfu << MATRIX_SRTSR11_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */\r
+#define MATRIX_SRTSR11_SRTOP5(value) ((MATRIX_SRTSR11_SRTOP5_Msk & ((value) << MATRIX_SRTSR11_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR11_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR11_SRTOP6_Msk (0xfu << MATRIX_SRTSR11_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */\r
+#define MATRIX_SRTSR11_SRTOP6(value) ((MATRIX_SRTSR11_SRTOP6_Msk & ((value) << MATRIX_SRTSR11_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR11_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR11_SRTOP7_Msk (0xfu << MATRIX_SRTSR11_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */\r
+#define MATRIX_SRTSR11_SRTOP7(value) ((MATRIX_SRTSR11_SRTOP7_Msk & ((value) << MATRIX_SRTSR11_SRTOP7_Pos)))\r
+/* -------- MATRIX_SRTSR12 : (MATRIX Offset: 0x02B0) Security Region Top Slave 12 Register -------- */\r
+#define MATRIX_SRTSR12_SRTOP0_Pos 0\r
+#define MATRIX_SRTSR12_SRTOP0_Msk (0xfu << MATRIX_SRTSR12_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */\r
+#define MATRIX_SRTSR12_SRTOP0(value) ((MATRIX_SRTSR12_SRTOP0_Msk & ((value) << MATRIX_SRTSR12_SRTOP0_Pos)))\r
+#define MATRIX_SRTSR12_SRTOP1_Pos 4\r
+#define MATRIX_SRTSR12_SRTOP1_Msk (0xfu << MATRIX_SRTSR12_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */\r
+#define MATRIX_SRTSR12_SRTOP1(value) ((MATRIX_SRTSR12_SRTOP1_Msk & ((value) << MATRIX_SRTSR12_SRTOP1_Pos)))\r
+#define MATRIX_SRTSR12_SRTOP2_Pos 8\r
+#define MATRIX_SRTSR12_SRTOP2_Msk (0xfu << MATRIX_SRTSR12_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */\r
+#define MATRIX_SRTSR12_SRTOP2(value) ((MATRIX_SRTSR12_SRTOP2_Msk & ((value) << MATRIX_SRTSR12_SRTOP2_Pos)))\r
+#define MATRIX_SRTSR12_SRTOP3_Pos 12\r
+#define MATRIX_SRTSR12_SRTOP3_Msk (0xfu << MATRIX_SRTSR12_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */\r
+#define MATRIX_SRTSR12_SRTOP3(value) ((MATRIX_SRTSR12_SRTOP3_Msk & ((value) << MATRIX_SRTSR12_SRTOP3_Pos)))\r
+#define MATRIX_SRTSR12_SRTOP4_Pos 16\r
+#define MATRIX_SRTSR12_SRTOP4_Msk (0xfu << MATRIX_SRTSR12_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */\r
+#define MATRIX_SRTSR12_SRTOP4(value) ((MATRIX_SRTSR12_SRTOP4_Msk & ((value) << MATRIX_SRTSR12_SRTOP4_Pos)))\r
+#define MATRIX_SRTSR12_SRTOP5_Pos 20\r
+#define MATRIX_SRTSR12_SRTOP5_Msk (0xfu << MATRIX_SRTSR12_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */\r
+#define MATRIX_SRTSR12_SRTOP5(value) ((MATRIX_SRTSR12_SRTOP5_Msk & ((value) << MATRIX_SRTSR12_SRTOP5_Pos)))\r
+#define MATRIX_SRTSR12_SRTOP6_Pos 24\r
+#define MATRIX_SRTSR12_SRTOP6_Msk (0xfu << MATRIX_SRTSR12_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */\r
+#define MATRIX_SRTSR12_SRTOP6(value) ((MATRIX_SRTSR12_SRTOP6_Msk & ((value) << MATRIX_SRTSR12_SRTOP6_Pos)))\r
+#define MATRIX_SRTSR12_SRTOP7_Pos 28\r
+#define MATRIX_SRTSR12_SRTOP7_Msk (0xfu << MATRIX_SRTSR12_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */\r
+#define MATRIX_SRTSR12_SRTOP7(value) ((MATRIX_SRTSR12_SRTOP7_Msk & ((value) << MATRIX_SRTSR12_SRTOP7_Pos)))\r
+/* -------- MATRIX_SPSELR[3] : (MATRIX Offset: 0x02C0) Security Peripheral Select 1 Register -------- */\r
+#define MATRIX_SPSELR_NSECP0 (0x1u << 0) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP1 (0x1u << 1) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP2 (0x1u << 2) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP3 (0x1u << 3) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP4 (0x1u << 4) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP5 (0x1u << 5) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP6 (0x1u << 6) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP7 (0x1u << 7) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP8 (0x1u << 8) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP9 (0x1u << 9) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP10 (0x1u << 10) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP11 (0x1u << 11) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP12 (0x1u << 12) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP13 (0x1u << 13) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP14 (0x1u << 14) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP15 (0x1u << 15) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP16 (0x1u << 16) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP17 (0x1u << 17) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP18 (0x1u << 18) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP19 (0x1u << 19) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP20 (0x1u << 20) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP21 (0x1u << 21) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP22 (0x1u << 22) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP23 (0x1u << 23) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP24 (0x1u << 24) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP25 (0x1u << 25) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP26 (0x1u << 26) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP27 (0x1u << 27) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP28 (0x1u << 28) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP29 (0x1u << 29) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP30 (0x1u << 30) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+#define MATRIX_SPSELR_NSECP31 (0x1u << 31) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_MATRIX_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_MCAN_COMPONENT_\r
+#define _SAMA5D2_MCAN_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Controller Area Network */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_MCAN Controller Area Network */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Mcan hardware registers */\r
+typedef struct {\r
+ __I uint32_t MCAN_CREL; /**< \brief (Mcan Offset: 0x00) Core Release Register */\r
+ __I uint32_t MCAN_ENDN; /**< \brief (Mcan Offset: 0x04) Endian Register */\r
+ __IO uint32_t MCAN_CUST; /**< \brief (Mcan Offset: 0x08) Customer Register */\r
+ __IO uint32_t MCAN_DBTP; /**< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register */\r
+ __IO uint32_t MCAN_TEST; /**< \brief (Mcan Offset: 0x10) Test Register */\r
+ __IO uint32_t MCAN_RWD; /**< \brief (Mcan Offset: 0x14) RAM Watchdog Register */\r
+ __IO uint32_t MCAN_CCCR; /**< \brief (Mcan Offset: 0x18) CC Control Register */\r
+ __IO uint32_t MCAN_NBTP; /**< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register */\r
+ __IO uint32_t MCAN_TSCC; /**< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register */\r
+ __IO uint32_t MCAN_TSCV; /**< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register */\r
+ __IO uint32_t MCAN_TOCC; /**< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register */\r
+ __IO uint32_t MCAN_TOCV; /**< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register */\r
+ __I uint32_t Reserved1[4];\r
+ __I uint32_t MCAN_ECR; /**< \brief (Mcan Offset: 0x40) Error Counter Register */\r
+ __I uint32_t MCAN_PSR; /**< \brief (Mcan Offset: 0x44) Protocol Status Register */\r
+ __IO uint32_t MCAN_TDCR; /**< \brief (Mcan Offset: 0x48) Transmit Delay Compensation Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t MCAN_IR; /**< \brief (Mcan Offset: 0x50) Interrupt Register */\r
+ __IO uint32_t MCAN_IE; /**< \brief (Mcan Offset: 0x54) Interrupt Enable Register */\r
+ __IO uint32_t MCAN_ILS; /**< \brief (Mcan Offset: 0x58) Interrupt Line Select Register */\r
+ __IO uint32_t MCAN_ILE; /**< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register */\r
+ __I uint32_t Reserved3[8];\r
+ __IO uint32_t MCAN_GFC; /**< \brief (Mcan Offset: 0x80) Global Filter Configuration Register */\r
+ __IO uint32_t MCAN_SIDFC; /**< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register */\r
+ __IO uint32_t MCAN_XIDFC; /**< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register */\r
+ __I uint32_t Reserved4[1];\r
+ __IO uint32_t MCAN_XIDAM; /**< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register */\r
+ __I uint32_t MCAN_HPMS; /**< \brief (Mcan Offset: 0x94) High Priority Message Status Register */\r
+ __IO uint32_t MCAN_NDAT1; /**< \brief (Mcan Offset: 0x98) New Data 1 Register */\r
+ __IO uint32_t MCAN_NDAT2; /**< \brief (Mcan Offset: 0x9C) New Data 2 Register */\r
+ __IO uint32_t MCAN_RXF0C; /**< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register */\r
+ __I uint32_t MCAN_RXF0S; /**< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register */\r
+ __IO uint32_t MCAN_RXF0A; /**< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register */\r
+ __IO uint32_t MCAN_RXBC; /**< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register */\r
+ __IO uint32_t MCAN_RXF1C; /**< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register */\r
+ __I uint32_t MCAN_RXF1S; /**< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register */\r
+ __IO uint32_t MCAN_RXF1A; /**< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register */\r
+ __IO uint32_t MCAN_RXESC; /**< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */\r
+ __IO uint32_t MCAN_TXBC; /**< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register */\r
+ __I uint32_t MCAN_TXFQS; /**< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register */\r
+ __IO uint32_t MCAN_TXESC; /**< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register */\r
+ __I uint32_t MCAN_TXBRP; /**< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register */\r
+ __IO uint32_t MCAN_TXBAR; /**< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register */\r
+ __IO uint32_t MCAN_TXBCR; /**< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register */\r
+ __I uint32_t MCAN_TXBTO; /**< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register */\r
+ __I uint32_t MCAN_TXBCF; /**< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register */\r
+ __IO uint32_t MCAN_TXBTIE; /**< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */\r
+ __IO uint32_t MCAN_TXBCIE; /**< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */\r
+ __I uint32_t Reserved5[2];\r
+ __IO uint32_t MCAN_TXEFC; /**< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register */\r
+ __I uint32_t MCAN_TXEFS; /**< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register */\r
+ __IO uint32_t MCAN_TXEFA; /**< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register */\r
+} Mcan;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- MCAN_CREL : (MCAN Offset: 0x00) Core Release Register -------- */\r
+#define MCAN_CREL_DAY_Pos 0\r
+#define MCAN_CREL_DAY_Msk (0xffu << MCAN_CREL_DAY_Pos) /**< \brief (MCAN_CREL) Timestamp Day */\r
+#define MCAN_CREL_MON_Pos 8\r
+#define MCAN_CREL_MON_Msk (0xffu << MCAN_CREL_MON_Pos) /**< \brief (MCAN_CREL) Timestamp Month */\r
+#define MCAN_CREL_YEAR_Pos 16\r
+#define MCAN_CREL_YEAR_Msk (0xfu << MCAN_CREL_YEAR_Pos) /**< \brief (MCAN_CREL) Timestamp Year */\r
+#define MCAN_CREL_SUBSTEP_Pos 20\r
+#define MCAN_CREL_SUBSTEP_Msk (0xfu << MCAN_CREL_SUBSTEP_Pos) /**< \brief (MCAN_CREL) Sub-step of Core Release */\r
+#define MCAN_CREL_STEP_Pos 24\r
+#define MCAN_CREL_STEP_Msk (0xfu << MCAN_CREL_STEP_Pos) /**< \brief (MCAN_CREL) Step of Core Release */\r
+#define MCAN_CREL_REL_Pos 28\r
+#define MCAN_CREL_REL_Msk (0xfu << MCAN_CREL_REL_Pos) /**< \brief (MCAN_CREL) Core Release */\r
+/* -------- MCAN_ENDN : (MCAN Offset: 0x04) Endian Register -------- */\r
+#define MCAN_ENDN_ETV_Pos 0\r
+#define MCAN_ENDN_ETV_Msk (0xffffffffu << MCAN_ENDN_ETV_Pos) /**< \brief (MCAN_ENDN) Endianness Test Value */\r
+/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */\r
+#define MCAN_CUST_CSV_Pos 0\r
+#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /**< \brief (MCAN_CUST) Customer-specific Value */\r
+#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)))\r
+/* -------- MCAN_DBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */\r
+#define MCAN_DBTP_DSJW_Pos 0\r
+#define MCAN_DBTP_DSJW_Msk (0x7u << MCAN_DBTP_DSJW_Pos) /**< \brief (MCAN_DBTP) Fast (Re) Synchronization Jump Width */\r
+#define MCAN_DBTP_DSJW(value) ((MCAN_DBTP_DSJW_Msk & ((value) << MCAN_DBTP_DSJW_Pos)))\r
+#define MCAN_DBTP_DTSEG2_Pos 4\r
+#define MCAN_DBTP_DTSEG2_Msk (0xfu << MCAN_DBTP_DTSEG2_Pos) /**< \brief (MCAN_DBTP) Fast Time Segment After Sample Point */\r
+#define MCAN_DBTP_DTSEG2(value) ((MCAN_DBTP_DTSEG2_Msk & ((value) << MCAN_DBTP_DTSEG2_Pos)))\r
+#define MCAN_DBTP_DTSEG1_Pos 8\r
+#define MCAN_DBTP_DTSEG1_Msk (0x1fu << MCAN_DBTP_DTSEG1_Pos) /**< \brief (MCAN_DBTP) Fast Time Segment Before Sample Point */\r
+#define MCAN_DBTP_DTSEG1(value) ((MCAN_DBTP_DTSEG1_Msk & ((value) << MCAN_DBTP_DTSEG1_Pos)))\r
+#define MCAN_DBTP_FBRP_Pos 16\r
+#define MCAN_DBTP_FBRP_Msk (0x1fu << MCAN_DBTP_FBRP_Pos) /**< \brief (MCAN_DBTP) Fast Baud Rate Prescaler */\r
+#define MCAN_DBTP_FBRP(value) ((MCAN_DBTP_FBRP_Msk & ((value) << MCAN_DBTP_FBRP_Pos)))\r
+#define MCAN_DBTP_TDC (0x1u << 23) /**< \brief (MCAN_DBTP) Transceiver Delay Compensation */\r
+#define MCAN_DBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_DBTP) Transceiver Delay Compensation disabled. */\r
+#define MCAN_DBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_DBTP) Transceiver Delay Compensation enabled. */\r
+/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */\r
+#define MCAN_TEST_LBCK (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back Mode (read/write) */\r
+#define MCAN_TEST_LBCK_DISABLED (0x0u << 4) /**< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. */\r
+#define MCAN_TEST_LBCK_ENABLED (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 1.5.1.9). */\r
+#define MCAN_TEST_TX_Pos 5\r
+#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /**< \brief (MCAN_TEST) Control of Transmit Pin (read/write) */\r
+#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)))\r
+#define MCAN_TEST_TX_RESET (0x0u << 5) /**< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */\r
+#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /**< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. */\r
+#define MCAN_TEST_TX_DOMINANT (0x2u << 5) /**< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. */\r
+#define MCAN_TEST_TX_RECESSIVE (0x3u << 5) /**< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. */\r
+#define MCAN_TEST_RX (0x1u << 7) /**< \brief (MCAN_TEST) Receive Pin (read-only) */\r
+/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */\r
+#define MCAN_RWD_WDC_Pos 0\r
+#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /**< \brief (MCAN_RWD) Watchdog Configuration (read/write) */\r
+#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)))\r
+#define MCAN_RWD_WDV_Pos 8\r
+#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /**< \brief (MCAN_RWD) Watchdog Value (read-only) */\r
+#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)))\r
+/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */\r
+#define MCAN_CCCR_INIT (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization (read/write) */\r
+#define MCAN_CCCR_INIT_DISABLED (0x0u << 0) /**< \brief (MCAN_CCCR) Normal operation. */\r
+#define MCAN_CCCR_INIT_ENABLED (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization is started. */\r
+#define MCAN_CCCR_CCE (0x1u << 1) /**< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) */\r
+#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /**< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. */\r
+#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /**< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */\r
+#define MCAN_CCCR_ASM (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') */\r
+#define MCAN_CCCR_ASM_NORMAL (0x0u << 2) /**< \brief (MCAN_CCCR) Normal CAN operation. */\r
+#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted operation mode active. */\r
+#define MCAN_CCCR_CSA (0x1u << 3) /**< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) */\r
+#define MCAN_CCCR_CSR (0x1u << 4) /**< \brief (MCAN_CCCR) Clock Stop Request (read/write) */\r
+#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /**< \brief (MCAN_CCCR) No clock stop is requested. */\r
+#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /**< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */\r
+#define MCAN_CCCR_MON (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') */\r
+#define MCAN_CCCR_MON_DISABLED (0x0u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. */\r
+#define MCAN_CCCR_MON_ENABLED (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. */\r
+#define MCAN_CCCR_DAR (0x1u << 6) /**< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) */\r
+#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */\r
+#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission disabled. */\r
+#define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */\r
+#define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */\r
+#define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */\r
+#define MCAN_CCCR_FDOE (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD Operation Enable (read/write, write protection) */\r
+#define MCAN_CCCR_FDOE_DISABLED (0x0u << 8) /**< \brief (MCAN_CCCR) Classic CAN frame */\r
+#define MCAN_CCCR_FDOE_ENABLED (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD frame */\r
+#define MCAN_CCCR_BRSE (0x1u << 9) /**< \brief (MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection) */\r
+#define MCAN_CCCR_BRSE_DISABLED (0x0u << 9) /**< \brief (MCAN_CCCR) Frames without bit rate switching */\r
+#define MCAN_CCCR_BRSE_ENABLED (0x1u << 9) /**< \brief (MCAN_CCCR) Frames with bit rate switching */\r
+#define MCAN_CCCR_PXHD (0x1u << 12) /**< \brief (MCAN_CCCR) Protocol Exception Event Handling (read/write, write protection) */\r
+#define MCAN_CCCR_EFBI (0x1u << 13) /**< \brief (MCAN_CCCR) Edge Filtering during Bus Integration (read/write, write protection) */\r
+#define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */\r
+/* -------- MCAN_NBTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */\r
+#define MCAN_NBTP_NTSEG2_Pos 0\r
+#define MCAN_NBTP_NTSEG2_Msk (0x7fu << MCAN_NBTP_NTSEG2_Pos) /**< \brief (MCAN_NBTP) Nominal Time Segment After Sample Point */\r
+#define MCAN_NBTP_NTSEG2(value) ((MCAN_NBTP_NTSEG2_Msk & ((value) << MCAN_NBTP_NTSEG2_Pos)))\r
+#define MCAN_NBTP_NTSEG1_Pos 8\r
+#define MCAN_NBTP_NTSEG1_Msk (0xffu << MCAN_NBTP_NTSEG1_Pos) /**< \brief (MCAN_NBTP) Nominal Time Segment Before Sample Point */\r
+#define MCAN_NBTP_NTSEG1(value) ((MCAN_NBTP_NTSEG1_Msk & ((value) << MCAN_NBTP_NTSEG1_Pos)))\r
+#define MCAN_NBTP_NBRP_Pos 16\r
+#define MCAN_NBTP_NBRP_Msk (0x1ffu << MCAN_NBTP_NBRP_Pos) /**< \brief (MCAN_NBTP) Nominal Baud Rate Prescaler */\r
+#define MCAN_NBTP_NBRP(value) ((MCAN_NBTP_NBRP_Msk & ((value) << MCAN_NBTP_NBRP_Pos)))\r
+#define MCAN_NBTP_NSJW_Pos 25\r
+#define MCAN_NBTP_NSJW_Msk (0x7fu << MCAN_NBTP_NSJW_Pos) /**< \brief (MCAN_NBTP) Nominal (Re) Synchronization Jump Width */\r
+#define MCAN_NBTP_NSJW(value) ((MCAN_NBTP_NSJW_Msk & ((value) << MCAN_NBTP_NSJW_Pos)))\r
+/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */\r
+#define MCAN_TSCC_TSS_Pos 0\r
+#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /**< \brief (MCAN_TSCC) Timestamp Select */\r
+#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)))\r
+#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 */\r
+#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP */\r
+#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /**< \brief (MCAN_TSCC) External timestamp counter value used */\r
+#define MCAN_TSCC_TCP_Pos 16\r
+#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /**< \brief (MCAN_TSCC) Timestamp Counter Prescaler */\r
+#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)))\r
+/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */\r
+#define MCAN_TSCV_TSC_Pos 0\r
+#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /**< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) */\r
+#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)))\r
+/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */\r
+#define MCAN_TOCC_ETOC (0x1u << 0) /**< \brief (MCAN_TOCC) Enable Timeout Counter */\r
+#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /**< \brief (MCAN_TOCC) Timeout Counter disabled. */\r
+#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /**< \brief (MCAN_TOCC) Timeout Counter enabled. */\r
+#define MCAN_TOCC_TOS_Pos 1\r
+#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /**< \brief (MCAN_TOCC) Timeout Select */\r
+#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)))\r
+#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /**< \brief (MCAN_TOCC) Continuous operation */\r
+#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO */\r
+#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */\r
+#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */\r
+#define MCAN_TOCC_TOP_Pos 16\r
+#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /**< \brief (MCAN_TOCC) Timeout Period */\r
+#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)))\r
+/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */\r
+#define MCAN_TOCV_TOC_Pos 0\r
+#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /**< \brief (MCAN_TOCV) Timeout Counter (cleared on write) */\r
+#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)))\r
+/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */\r
+#define MCAN_ECR_TEC_Pos 0\r
+#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /**< \brief (MCAN_ECR) Transmit Error Counter */\r
+#define MCAN_ECR_REC_Pos 8\r
+#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /**< \brief (MCAN_ECR) Receive Error Counter */\r
+#define MCAN_ECR_RP (0x1u << 15) /**< \brief (MCAN_ECR) Receive Error Passive */\r
+#define MCAN_ECR_CEL_Pos 16\r
+#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /**< \brief (MCAN_ECR) CAN Error Logging (cleared on read) */\r
+/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */\r
+#define MCAN_PSR_LEC_Pos 0\r
+#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /**< \brief (MCAN_PSR) Last Error Code (set to 111 on read) */\r
+#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /**< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */\r
+#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /**< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */\r
+#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /**< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. */\r
+#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /**< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */\r
+#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */\r
+#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */\r
+#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /**< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */\r
+#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /**< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */\r
+#define MCAN_PSR_ACT_Pos 3\r
+#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /**< \brief (MCAN_PSR) Activity */\r
+#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /**< \brief (MCAN_PSR) Node is synchronizing on CAN communication */\r
+#define MCAN_PSR_ACT_IDLE (0x1u << 3) /**< \brief (MCAN_PSR) Node is neither receiver nor transmitter */\r
+#define MCAN_PSR_ACT_RECEIVER (0x2u << 3) /**< \brief (MCAN_PSR) Node is operating as receiver */\r
+#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /**< \brief (MCAN_PSR) Node is operating as transmitter */\r
+#define MCAN_PSR_EP (0x1u << 5) /**< \brief (MCAN_PSR) Error Passive */\r
+#define MCAN_PSR_EW (0x1u << 6) /**< \brief (MCAN_PSR) Warning Status */\r
+#define MCAN_PSR_BO (0x1u << 7) /**< \brief (MCAN_PSR) Bus_Off Status */\r
+#define MCAN_PSR_DLEC_Pos 8\r
+#define MCAN_PSR_DLEC_Msk (0x7u << MCAN_PSR_DLEC_Pos) /**< \brief (MCAN_PSR) Data Phase Last Error Code (set to 111 on read) */\r
+#define MCAN_PSR_RESI (0x1u << 11) /**< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) */\r
+#define MCAN_PSR_RBRS (0x1u << 12) /**< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) */\r
+#define MCAN_PSR_RFDF (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */\r
+#define MCAN_PSR_PXE (0x1u << 14) /**< \brief (MCAN_PSR) Protocol Exception Event (cleared on read) */\r
+#define MCAN_PSR_TDCV_Pos 16\r
+#define MCAN_PSR_TDCV_Msk (0x7fu << MCAN_PSR_TDCV_Pos) /**< \brief (MCAN_PSR) Transceiver Delay Compensation Value */\r
+/* -------- MCAN_TDCR : (MCAN Offset: 0x48) Transmit Delay Compensation Register -------- */\r
+#define MCAN_TDCR_TDCF_Pos 0\r
+#define MCAN_TDCR_TDCF_Msk (0x7fu << MCAN_TDCR_TDCF_Pos) /**< \brief (MCAN_TDCR) Transmitter Delay Compensation Filter */\r
+#define MCAN_TDCR_TDCF(value) ((MCAN_TDCR_TDCF_Msk & ((value) << MCAN_TDCR_TDCF_Pos)))\r
+#define MCAN_TDCR_TDCO_Pos 8\r
+#define MCAN_TDCR_TDCO_Msk (0x7fu << MCAN_TDCR_TDCO_Pos) /**< \brief (MCAN_TDCR) Transmitter Delay Compensation Offset */\r
+#define MCAN_TDCR_TDCO(value) ((MCAN_TDCR_TDCO_Msk & ((value) << MCAN_TDCR_TDCO_Pos)))\r
+/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */\r
+#define MCAN_IR_RF0N (0x1u << 0) /**< \brief (MCAN_IR) Receive FIFO 0 New Message */\r
+#define MCAN_IR_RF0W (0x1u << 1) /**< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached */\r
+#define MCAN_IR_RF0F (0x1u << 2) /**< \brief (MCAN_IR) Receive FIFO 0 Full */\r
+#define MCAN_IR_RF0L (0x1u << 3) /**< \brief (MCAN_IR) Receive FIFO 0 Message Lost */\r
+#define MCAN_IR_RF1N (0x1u << 4) /**< \brief (MCAN_IR) Receive FIFO 1 New Message */\r
+#define MCAN_IR_RF1W (0x1u << 5) /**< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached */\r
+#define MCAN_IR_RF1F (0x1u << 6) /**< \brief (MCAN_IR) Receive FIFO 1 Full */\r
+#define MCAN_IR_RF1L (0x1u << 7) /**< \brief (MCAN_IR) Receive FIFO 1 Message Lost */\r
+#define MCAN_IR_HPM (0x1u << 8) /**< \brief (MCAN_IR) High Priority Message */\r
+#define MCAN_IR_TC (0x1u << 9) /**< \brief (MCAN_IR) Transmission Completed */\r
+#define MCAN_IR_TCF (0x1u << 10) /**< \brief (MCAN_IR) Transmission Cancellation Finished */\r
+#define MCAN_IR_TFE (0x1u << 11) /**< \brief (MCAN_IR) Tx FIFO Empty */\r
+#define MCAN_IR_TEFN (0x1u << 12) /**< \brief (MCAN_IR) Tx Event FIFO New Entry */\r
+#define MCAN_IR_TEFW (0x1u << 13) /**< \brief (MCAN_IR) Tx Event FIFO Watermark Reached */\r
+#define MCAN_IR_TEFF (0x1u << 14) /**< \brief (MCAN_IR) Tx Event FIFO Full */\r
+#define MCAN_IR_TEFL (0x1u << 15) /**< \brief (MCAN_IR) Tx Event FIFO Element Lost */\r
+#define MCAN_IR_TSW (0x1u << 16) /**< \brief (MCAN_IR) Timestamp Wraparound */\r
+#define MCAN_IR_MRAF (0x1u << 17) /**< \brief (MCAN_IR) Message RAM Access Failure */\r
+#define MCAN_IR_TOO (0x1u << 18) /**< \brief (MCAN_IR) Timeout Occurred */\r
+#define MCAN_IR_DRX (0x1u << 19) /**< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer */\r
+#define MCAN_IR_BEC (0x1u << 20) /**< \brief (MCAN_IR) Bit Error Corrected */\r
+#define MCAN_IR_BEU (0x1u << 21) /**< \brief (MCAN_IR) Bit Error Uncorrected */\r
+#define MCAN_IR_ELO (0x1u << 22) /**< \brief (MCAN_IR) Error Logging Overflow */\r
+#define MCAN_IR_EP (0x1u << 23) /**< \brief (MCAN_IR) Error Passive */\r
+#define MCAN_IR_EW (0x1u << 24) /**< \brief (MCAN_IR) Warning Status */\r
+#define MCAN_IR_BO (0x1u << 25) /**< \brief (MCAN_IR) Bus_Off Status */\r
+#define MCAN_IR_WDI (0x1u << 26) /**< \brief (MCAN_IR) Watchdog Interrupt */\r
+#define MCAN_IR_PEA (0x1u << 27) /**< \brief (MCAN_IR) Protocol Error in Arbitration Phase */\r
+#define MCAN_IR_PED (0x1u << 28) /**< \brief (MCAN_IR) Protocol Error in Data Phase */\r
+#define MCAN_IR_ARA (0x1u << 29) /**< \brief (MCAN_IR) Access to Reserved Address */\r
+/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */\r
+#define MCAN_IE_RF0NE (0x1u << 0) /**< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable */\r
+#define MCAN_IE_RF0WE (0x1u << 1) /**< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable */\r
+#define MCAN_IE_RF0FE (0x1u << 2) /**< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable */\r
+#define MCAN_IE_RF0LE (0x1u << 3) /**< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable */\r
+#define MCAN_IE_RF1NE (0x1u << 4) /**< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable */\r
+#define MCAN_IE_RF1WE (0x1u << 5) /**< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable */\r
+#define MCAN_IE_RF1FE (0x1u << 6) /**< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable */\r
+#define MCAN_IE_RF1LE (0x1u << 7) /**< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable */\r
+#define MCAN_IE_HPME (0x1u << 8) /**< \brief (MCAN_IE) High Priority Message Interrupt Enable */\r
+#define MCAN_IE_TCE (0x1u << 9) /**< \brief (MCAN_IE) Transmission Completed Interrupt Enable */\r
+#define MCAN_IE_TCFE (0x1u << 10) /**< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable */\r
+#define MCAN_IE_TFEE (0x1u << 11) /**< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable */\r
+#define MCAN_IE_TEFNE (0x1u << 12) /**< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable */\r
+#define MCAN_IE_TEFWE (0x1u << 13) /**< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */\r
+#define MCAN_IE_TEFFE (0x1u << 14) /**< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable */\r
+#define MCAN_IE_TEFLE (0x1u << 15) /**< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable */\r
+#define MCAN_IE_TSWE (0x1u << 16) /**< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable */\r
+#define MCAN_IE_MRAFE (0x1u << 17) /**< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable */\r
+#define MCAN_IE_TOOE (0x1u << 18) /**< \brief (MCAN_IE) Timeout Occurred Interrupt Enable */\r
+#define MCAN_IE_DRXE (0x1u << 19) /**< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable */\r
+#define MCAN_IE_BECE (0x1u << 20) /**< \brief (MCAN_IE) Bit Error Corrected Interrupt Enable */\r
+#define MCAN_IE_BEUE (0x1u << 21) /**< \brief (MCAN_IE) Bit Error Uncorrected Interrupt Enable */\r
+#define MCAN_IE_ELOE (0x1u << 22) /**< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable */\r
+#define MCAN_IE_EPE (0x1u << 23) /**< \brief (MCAN_IE) Error Passive Interrupt Enable */\r
+#define MCAN_IE_EWE (0x1u << 24) /**< \brief (MCAN_IE) Warning Status Interrupt Enable */\r
+#define MCAN_IE_BOE (0x1u << 25) /**< \brief (MCAN_IE) Bus_Off Status Interrupt Enable */\r
+#define MCAN_IE_WDIE (0x1u << 26) /**< \brief (MCAN_IE) Watchdog Interrupt Enable */\r
+#define MCAN_IE_PEAE (0x1u << 27) /**< \brief (MCAN_IE) Protocol Error in Arbitration Phase Enable */\r
+#define MCAN_IE_PEDE (0x1u << 28) /**< \brief (MCAN_IE) Protocol Error in Data Phase Enable */\r
+#define MCAN_IE_ARAE (0x1u << 29) /**< \brief (MCAN_IE) Access to Reserved Address Enable */\r
+/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */\r
+#define MCAN_ILS_RF0NL (0x1u << 0) /**< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line */\r
+#define MCAN_ILS_RF0WL (0x1u << 1) /**< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line */\r
+#define MCAN_ILS_RF0FL (0x1u << 2) /**< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line */\r
+#define MCAN_ILS_RF0LL (0x1u << 3) /**< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line */\r
+#define MCAN_ILS_RF1NL (0x1u << 4) /**< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line */\r
+#define MCAN_ILS_RF1WL (0x1u << 5) /**< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line */\r
+#define MCAN_ILS_RF1FL (0x1u << 6) /**< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line */\r
+#define MCAN_ILS_RF1LL (0x1u << 7) /**< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line */\r
+#define MCAN_ILS_HPML (0x1u << 8) /**< \brief (MCAN_ILS) High Priority Message Interrupt Line */\r
+#define MCAN_ILS_TCL (0x1u << 9) /**< \brief (MCAN_ILS) Transmission Completed Interrupt Line */\r
+#define MCAN_ILS_TCFL (0x1u << 10) /**< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line */\r
+#define MCAN_ILS_TFEL (0x1u << 11) /**< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line */\r
+#define MCAN_ILS_TEFNL (0x1u << 12) /**< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line */\r
+#define MCAN_ILS_TEFWL (0x1u << 13) /**< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */\r
+#define MCAN_ILS_TEFFL (0x1u << 14) /**< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line */\r
+#define MCAN_ILS_TEFLL (0x1u << 15) /**< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line */\r
+#define MCAN_ILS_TSWL (0x1u << 16) /**< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line */\r
+#define MCAN_ILS_MRAFL (0x1u << 17) /**< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line */\r
+#define MCAN_ILS_TOOL (0x1u << 18) /**< \brief (MCAN_ILS) Timeout Occurred Interrupt Line */\r
+#define MCAN_ILS_DRXL (0x1u << 19) /**< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line */\r
+#define MCAN_ILS_BECL (0x1u << 20) /**< \brief (MCAN_ILS) Bit Error Corrected Interrupt Line */\r
+#define MCAN_ILS_BEUL (0x1u << 21) /**< \brief (MCAN_ILS) Bit Error Uncorrected Interrupt Line */\r
+#define MCAN_ILS_ELOL (0x1u << 22) /**< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line */\r
+#define MCAN_ILS_EPL (0x1u << 23) /**< \brief (MCAN_ILS) Error Passive Interrupt Line */\r
+#define MCAN_ILS_EWL (0x1u << 24) /**< \brief (MCAN_ILS) Warning Status Interrupt Line */\r
+#define MCAN_ILS_BOL (0x1u << 25) /**< \brief (MCAN_ILS) Bus_Off Status Interrupt Line */\r
+#define MCAN_ILS_WDIL (0x1u << 26) /**< \brief (MCAN_ILS) Watchdog Interrupt Line */\r
+#define MCAN_ILS_PEAL (0x1u << 27) /**< \brief (MCAN_ILS) Protocol Error in Arbitration Phase Line */\r
+#define MCAN_ILS_PEDL (0x1u << 28) /**< \brief (MCAN_ILS) Protocol Error in Data Phase Line */\r
+#define MCAN_ILS_ARAL (0x1u << 29) /**< \brief (MCAN_ILS) Access to Reserved Address Line */\r
+/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */\r
+#define MCAN_ILE_EINT0 (0x1u << 0) /**< \brief (MCAN_ILE) Enable Interrupt Line 0 */\r
+#define MCAN_ILE_EINT1 (0x1u << 1) /**< \brief (MCAN_ILE) Enable Interrupt Line 1 */\r
+/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */\r
+#define MCAN_GFC_RRFE (0x1u << 0) /**< \brief (MCAN_GFC) Reject Remote Frames Extended */\r
+#define MCAN_GFC_RRFE_FILTER (0x0u << 0) /**< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */\r
+#define MCAN_GFC_RRFE_REJECT (0x1u << 0) /**< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */\r
+#define MCAN_GFC_RRFS (0x1u << 1) /**< \brief (MCAN_GFC) Reject Remote Frames Standard */\r
+#define MCAN_GFC_RRFS_FILTER (0x0u << 1) /**< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */\r
+#define MCAN_GFC_RRFS_REJECT (0x1u << 1) /**< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */\r
+#define MCAN_GFC_ANFE_Pos 2\r
+#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Extended */\r
+#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)))\r
+#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */\r
+#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */\r
+#define MCAN_GFC_ANFS_Pos 4\r
+#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Standard */\r
+#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)))\r
+#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */\r
+#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */\r
+/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */\r
+#define MCAN_SIDFC_FLSSA_Pos 2\r
+#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /**< \brief (MCAN_SIDFC) Filter List Standard Start Address */\r
+#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)))\r
+#define MCAN_SIDFC_LSS_Pos 16\r
+#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /**< \brief (MCAN_SIDFC) List Size Standard */\r
+#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)))\r
+/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */\r
+#define MCAN_XIDFC_FLESA_Pos 2\r
+#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /**< \brief (MCAN_XIDFC) Filter List Extended Start Address */\r
+#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)))\r
+#define MCAN_XIDFC_LSE_Pos 16\r
+#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /**< \brief (MCAN_XIDFC) List Size Extended */\r
+#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)))\r
+/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */\r
+#define MCAN_XIDAM_EIDM_Pos 0\r
+#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /**< \brief (MCAN_XIDAM) Extended ID Mask */\r
+#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)))\r
+/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */\r
+#define MCAN_HPMS_BIDX_Pos 0\r
+#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /**< \brief (MCAN_HPMS) Buffer Index */\r
+#define MCAN_HPMS_MSI_Pos 6\r
+#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /**< \brief (MCAN_HPMS) Message Storage Indicator */\r
+#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /**< \brief (MCAN_HPMS) No FIFO selected. */\r
+#define MCAN_HPMS_MSI_LOST (0x1u << 6) /**< \brief (MCAN_HPMS) FIFO message. */\r
+#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 0. */\r
+#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 1. */\r
+#define MCAN_HPMS_FIDX_Pos 8\r
+#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /**< \brief (MCAN_HPMS) Filter Index */\r
+#define MCAN_HPMS_FLST (0x1u << 15) /**< \brief (MCAN_HPMS) Filter List */\r
+/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */\r
+#define MCAN_NDAT1_ND0 (0x1u << 0) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND1 (0x1u << 1) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND2 (0x1u << 2) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND3 (0x1u << 3) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND4 (0x1u << 4) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND5 (0x1u << 5) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND6 (0x1u << 6) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND7 (0x1u << 7) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND8 (0x1u << 8) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND9 (0x1u << 9) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND10 (0x1u << 10) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND11 (0x1u << 11) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND12 (0x1u << 12) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND13 (0x1u << 13) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND14 (0x1u << 14) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND15 (0x1u << 15) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND16 (0x1u << 16) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND17 (0x1u << 17) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND18 (0x1u << 18) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND19 (0x1u << 19) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND20 (0x1u << 20) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND21 (0x1u << 21) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND22 (0x1u << 22) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND23 (0x1u << 23) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND24 (0x1u << 24) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND25 (0x1u << 25) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND26 (0x1u << 26) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND27 (0x1u << 27) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND28 (0x1u << 28) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND29 (0x1u << 29) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND30 (0x1u << 30) /**< \brief (MCAN_NDAT1) New Data */\r
+#define MCAN_NDAT1_ND31 (0x1u << 31) /**< \brief (MCAN_NDAT1) New Data */\r
+/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */\r
+#define MCAN_NDAT2_ND32 (0x1u << 0) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND33 (0x1u << 1) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND34 (0x1u << 2) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND35 (0x1u << 3) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND36 (0x1u << 4) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND37 (0x1u << 5) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND38 (0x1u << 6) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND39 (0x1u << 7) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND40 (0x1u << 8) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND41 (0x1u << 9) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND42 (0x1u << 10) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND43 (0x1u << 11) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND44 (0x1u << 12) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND45 (0x1u << 13) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND46 (0x1u << 14) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND47 (0x1u << 15) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND48 (0x1u << 16) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND49 (0x1u << 17) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND50 (0x1u << 18) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND51 (0x1u << 19) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND52 (0x1u << 20) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND53 (0x1u << 21) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND54 (0x1u << 22) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND55 (0x1u << 23) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND56 (0x1u << 24) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND57 (0x1u << 25) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND58 (0x1u << 26) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND59 (0x1u << 27) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND60 (0x1u << 28) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND61 (0x1u << 29) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND62 (0x1u << 30) /**< \brief (MCAN_NDAT2) New Data */\r
+#define MCAN_NDAT2_ND63 (0x1u << 31) /**< \brief (MCAN_NDAT2) New Data */\r
+/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */\r
+#define MCAN_RXF0C_F0SA_Pos 2\r
+#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */\r
+#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)))\r
+#define MCAN_RXF0C_F0S_Pos 16\r
+#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */\r
+#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)))\r
+#define MCAN_RXF0C_F0WM_Pos 24\r
+#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark */\r
+#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)))\r
+#define MCAN_RXF0C_F0OM (0x1u << 31) /**< \brief (MCAN_RXF0C) FIFO 0 Operation Mode */\r
+/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */\r
+#define MCAN_RXF0S_F0FL_Pos 0\r
+#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */\r
+#define MCAN_RXF0S_F0GI_Pos 8\r
+#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index */\r
+#define MCAN_RXF0S_F0PI_Pos 16\r
+#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index */\r
+#define MCAN_RXF0S_F0F (0x1u << 24) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */\r
+#define MCAN_RXF0S_RF0L (0x1u << 25) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost */\r
+/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */\r
+#define MCAN_RXF0A_F0AI_Pos 0\r
+#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /**< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index */\r
+#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)))\r
+/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */\r
+#define MCAN_RXBC_RBSA_Pos 2\r
+#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /**< \brief (MCAN_RXBC) Receive Buffer Start Address */\r
+#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)))\r
+/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */\r
+#define MCAN_RXF1C_F1SA_Pos 2\r
+#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */\r
+#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)))\r
+#define MCAN_RXF1C_F1S_Pos 16\r
+#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */\r
+#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)))\r
+#define MCAN_RXF1C_F1WM_Pos 24\r
+#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark */\r
+#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)))\r
+#define MCAN_RXF1C_F1OM (0x1u << 31) /**< \brief (MCAN_RXF1C) FIFO 1 Operation Mode */\r
+/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */\r
+#define MCAN_RXF1S_F1FL_Pos 0\r
+#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */\r
+#define MCAN_RXF1S_F1GI_Pos 8\r
+#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index */\r
+#define MCAN_RXF1S_F1PI_Pos 16\r
+#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index */\r
+#define MCAN_RXF1S_F1F (0x1u << 24) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */\r
+#define MCAN_RXF1S_RF1L (0x1u << 25) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost */\r
+#define MCAN_RXF1S_DMS_Pos 30\r
+#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /**< \brief (MCAN_RXF1S) Debug Message Status */\r
+#define MCAN_RXF1S_DMS_IDLE (0x0u << 30) /**< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */\r
+#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /**< \brief (MCAN_RXF1S) Debug message A received. */\r
+#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B received. */\r
+#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */\r
+/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */\r
+#define MCAN_RXF1A_F1AI_Pos 0\r
+#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /**< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index */\r
+#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)))\r
+/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */\r
+#define MCAN_RXESC_F0DS_Pos 0\r
+#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size */\r
+#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)))\r
+#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /**< \brief (MCAN_RXESC) 8-byte data field */\r
+#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /**< \brief (MCAN_RXESC) 12-byte data field */\r
+#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /**< \brief (MCAN_RXESC) 16-byte data field */\r
+#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /**< \brief (MCAN_RXESC) 20-byte data field */\r
+#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /**< \brief (MCAN_RXESC) 24-byte data field */\r
+#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /**< \brief (MCAN_RXESC) 32-byte data field */\r
+#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /**< \brief (MCAN_RXESC) 48-byte data field */\r
+#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /**< \brief (MCAN_RXESC) 64-byte data field */\r
+#define MCAN_RXESC_F1DS_Pos 4\r
+#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size */\r
+#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)))\r
+#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /**< \brief (MCAN_RXESC) 8-byte data field */\r
+#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /**< \brief (MCAN_RXESC) 12-byte data field */\r
+#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /**< \brief (MCAN_RXESC) 16-byte data field */\r
+#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /**< \brief (MCAN_RXESC) 20-byte data field */\r
+#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /**< \brief (MCAN_RXESC) 24-byte data field */\r
+#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /**< \brief (MCAN_RXESC) 32-byte data field */\r
+#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /**< \brief (MCAN_RXESC) 48-byte data field */\r
+#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /**< \brief (MCAN_RXESC) 64-byte data field */\r
+#define MCAN_RXESC_RBDS_Pos 8\r
+#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /**< \brief (MCAN_RXESC) Receive Buffer Data Field Size */\r
+#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)))\r
+#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /**< \brief (MCAN_RXESC) 8-byte data field */\r
+#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /**< \brief (MCAN_RXESC) 12-byte data field */\r
+#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /**< \brief (MCAN_RXESC) 16-byte data field */\r
+#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /**< \brief (MCAN_RXESC) 20-byte data field */\r
+#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /**< \brief (MCAN_RXESC) 24-byte data field */\r
+#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /**< \brief (MCAN_RXESC) 32-byte data field */\r
+#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /**< \brief (MCAN_RXESC) 48-byte data field */\r
+#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /**< \brief (MCAN_RXESC) 64-byte data field */\r
+/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */\r
+#define MCAN_TXBC_TBSA_Pos 2\r
+#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /**< \brief (MCAN_TXBC) Tx Buffers Start Address */\r
+#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)))\r
+#define MCAN_TXBC_NDTB_Pos 16\r
+#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /**< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers */\r
+#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)))\r
+#define MCAN_TXBC_TFQS_Pos 24\r
+#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /**< \brief (MCAN_TXBC) Transmit FIFO/Queue Size */\r
+#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)))\r
+#define MCAN_TXBC_TFQM (0x1u << 30) /**< \brief (MCAN_TXBC) Tx FIFO/Queue Mode */\r
+/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */\r
+#define MCAN_TXFQS_TFFL_Pos 0\r
+#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Free Level */\r
+#define MCAN_TXFQS_TFGI_Pos 8\r
+#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Get Index */\r
+#define MCAN_TXFQS_TFQPI_Pos 16\r
+#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index */\r
+#define MCAN_TXFQS_TFQF (0x1u << 21) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Full */\r
+/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */\r
+#define MCAN_TXESC_TBDS_Pos 0\r
+#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /**< \brief (MCAN_TXESC) Tx Buffer Data Field Size */\r
+#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)))\r
+#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /**< \brief (MCAN_TXESC) 8-byte data field */\r
+#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /**< \brief (MCAN_TXESC) 12-byte data field */\r
+#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /**< \brief (MCAN_TXESC) 16-byte data field */\r
+#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /**< \brief (MCAN_TXESC) 20-byte data field */\r
+#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /**< \brief (MCAN_TXESC) 24-byte data field */\r
+#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /**< \brief (MCAN_TXESC) 32-byte data field */\r
+#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /**< \brief (MCAN_TXESC) 48-byte data field */\r
+#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /**< \brief (MCAN_TXESC) 64-byte data field */\r
+/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */\r
+#define MCAN_TXBRP_TRP0 (0x1u << 0) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 */\r
+#define MCAN_TXBRP_TRP1 (0x1u << 1) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 */\r
+#define MCAN_TXBRP_TRP2 (0x1u << 2) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 */\r
+#define MCAN_TXBRP_TRP3 (0x1u << 3) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 */\r
+#define MCAN_TXBRP_TRP4 (0x1u << 4) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 */\r
+#define MCAN_TXBRP_TRP5 (0x1u << 5) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 */\r
+#define MCAN_TXBRP_TRP6 (0x1u << 6) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 */\r
+#define MCAN_TXBRP_TRP7 (0x1u << 7) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 */\r
+#define MCAN_TXBRP_TRP8 (0x1u << 8) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 */\r
+#define MCAN_TXBRP_TRP9 (0x1u << 9) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 */\r
+#define MCAN_TXBRP_TRP10 (0x1u << 10) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 */\r
+#define MCAN_TXBRP_TRP11 (0x1u << 11) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 */\r
+#define MCAN_TXBRP_TRP12 (0x1u << 12) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 */\r
+#define MCAN_TXBRP_TRP13 (0x1u << 13) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 */\r
+#define MCAN_TXBRP_TRP14 (0x1u << 14) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 */\r
+#define MCAN_TXBRP_TRP15 (0x1u << 15) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 */\r
+#define MCAN_TXBRP_TRP16 (0x1u << 16) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 */\r
+#define MCAN_TXBRP_TRP17 (0x1u << 17) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 */\r
+#define MCAN_TXBRP_TRP18 (0x1u << 18) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 */\r
+#define MCAN_TXBRP_TRP19 (0x1u << 19) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 */\r
+#define MCAN_TXBRP_TRP20 (0x1u << 20) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 */\r
+#define MCAN_TXBRP_TRP21 (0x1u << 21) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 */\r
+#define MCAN_TXBRP_TRP22 (0x1u << 22) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 */\r
+#define MCAN_TXBRP_TRP23 (0x1u << 23) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 */\r
+#define MCAN_TXBRP_TRP24 (0x1u << 24) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 */\r
+#define MCAN_TXBRP_TRP25 (0x1u << 25) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 */\r
+#define MCAN_TXBRP_TRP26 (0x1u << 26) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 */\r
+#define MCAN_TXBRP_TRP27 (0x1u << 27) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 */\r
+#define MCAN_TXBRP_TRP28 (0x1u << 28) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 */\r
+#define MCAN_TXBRP_TRP29 (0x1u << 29) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 */\r
+#define MCAN_TXBRP_TRP30 (0x1u << 30) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 */\r
+#define MCAN_TXBRP_TRP31 (0x1u << 31) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 */\r
+/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */\r
+#define MCAN_TXBAR_AR0 (0x1u << 0) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 */\r
+#define MCAN_TXBAR_AR1 (0x1u << 1) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 */\r
+#define MCAN_TXBAR_AR2 (0x1u << 2) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 */\r
+#define MCAN_TXBAR_AR3 (0x1u << 3) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 */\r
+#define MCAN_TXBAR_AR4 (0x1u << 4) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 */\r
+#define MCAN_TXBAR_AR5 (0x1u << 5) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 */\r
+#define MCAN_TXBAR_AR6 (0x1u << 6) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 */\r
+#define MCAN_TXBAR_AR7 (0x1u << 7) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 */\r
+#define MCAN_TXBAR_AR8 (0x1u << 8) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 */\r
+#define MCAN_TXBAR_AR9 (0x1u << 9) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 */\r
+#define MCAN_TXBAR_AR10 (0x1u << 10) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 */\r
+#define MCAN_TXBAR_AR11 (0x1u << 11) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 */\r
+#define MCAN_TXBAR_AR12 (0x1u << 12) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 */\r
+#define MCAN_TXBAR_AR13 (0x1u << 13) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 */\r
+#define MCAN_TXBAR_AR14 (0x1u << 14) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 */\r
+#define MCAN_TXBAR_AR15 (0x1u << 15) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 */\r
+#define MCAN_TXBAR_AR16 (0x1u << 16) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 */\r
+#define MCAN_TXBAR_AR17 (0x1u << 17) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 */\r
+#define MCAN_TXBAR_AR18 (0x1u << 18) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 */\r
+#define MCAN_TXBAR_AR19 (0x1u << 19) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 */\r
+#define MCAN_TXBAR_AR20 (0x1u << 20) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 */\r
+#define MCAN_TXBAR_AR21 (0x1u << 21) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 */\r
+#define MCAN_TXBAR_AR22 (0x1u << 22) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 */\r
+#define MCAN_TXBAR_AR23 (0x1u << 23) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 */\r
+#define MCAN_TXBAR_AR24 (0x1u << 24) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 */\r
+#define MCAN_TXBAR_AR25 (0x1u << 25) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 */\r
+#define MCAN_TXBAR_AR26 (0x1u << 26) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 */\r
+#define MCAN_TXBAR_AR27 (0x1u << 27) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 */\r
+#define MCAN_TXBAR_AR28 (0x1u << 28) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 */\r
+#define MCAN_TXBAR_AR29 (0x1u << 29) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 */\r
+#define MCAN_TXBAR_AR30 (0x1u << 30) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 */\r
+#define MCAN_TXBAR_AR31 (0x1u << 31) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 */\r
+/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */\r
+#define MCAN_TXBCR_CR0 (0x1u << 0) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 */\r
+#define MCAN_TXBCR_CR1 (0x1u << 1) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 */\r
+#define MCAN_TXBCR_CR2 (0x1u << 2) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 */\r
+#define MCAN_TXBCR_CR3 (0x1u << 3) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 */\r
+#define MCAN_TXBCR_CR4 (0x1u << 4) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 */\r
+#define MCAN_TXBCR_CR5 (0x1u << 5) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 */\r
+#define MCAN_TXBCR_CR6 (0x1u << 6) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 */\r
+#define MCAN_TXBCR_CR7 (0x1u << 7) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 */\r
+#define MCAN_TXBCR_CR8 (0x1u << 8) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 */\r
+#define MCAN_TXBCR_CR9 (0x1u << 9) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 */\r
+#define MCAN_TXBCR_CR10 (0x1u << 10) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 */\r
+#define MCAN_TXBCR_CR11 (0x1u << 11) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 */\r
+#define MCAN_TXBCR_CR12 (0x1u << 12) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 */\r
+#define MCAN_TXBCR_CR13 (0x1u << 13) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 */\r
+#define MCAN_TXBCR_CR14 (0x1u << 14) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 */\r
+#define MCAN_TXBCR_CR15 (0x1u << 15) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 */\r
+#define MCAN_TXBCR_CR16 (0x1u << 16) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 */\r
+#define MCAN_TXBCR_CR17 (0x1u << 17) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 */\r
+#define MCAN_TXBCR_CR18 (0x1u << 18) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 */\r
+#define MCAN_TXBCR_CR19 (0x1u << 19) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 */\r
+#define MCAN_TXBCR_CR20 (0x1u << 20) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 */\r
+#define MCAN_TXBCR_CR21 (0x1u << 21) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 */\r
+#define MCAN_TXBCR_CR22 (0x1u << 22) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 */\r
+#define MCAN_TXBCR_CR23 (0x1u << 23) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 */\r
+#define MCAN_TXBCR_CR24 (0x1u << 24) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 */\r
+#define MCAN_TXBCR_CR25 (0x1u << 25) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 */\r
+#define MCAN_TXBCR_CR26 (0x1u << 26) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 */\r
+#define MCAN_TXBCR_CR27 (0x1u << 27) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 */\r
+#define MCAN_TXBCR_CR28 (0x1u << 28) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 */\r
+#define MCAN_TXBCR_CR29 (0x1u << 29) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 */\r
+#define MCAN_TXBCR_CR30 (0x1u << 30) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 */\r
+#define MCAN_TXBCR_CR31 (0x1u << 31) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 */\r
+/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */\r
+#define MCAN_TXBTO_TO0 (0x1u << 0) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 */\r
+#define MCAN_TXBTO_TO1 (0x1u << 1) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 */\r
+#define MCAN_TXBTO_TO2 (0x1u << 2) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 */\r
+#define MCAN_TXBTO_TO3 (0x1u << 3) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 */\r
+#define MCAN_TXBTO_TO4 (0x1u << 4) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 */\r
+#define MCAN_TXBTO_TO5 (0x1u << 5) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 */\r
+#define MCAN_TXBTO_TO6 (0x1u << 6) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 */\r
+#define MCAN_TXBTO_TO7 (0x1u << 7) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 */\r
+#define MCAN_TXBTO_TO8 (0x1u << 8) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 */\r
+#define MCAN_TXBTO_TO9 (0x1u << 9) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 */\r
+#define MCAN_TXBTO_TO10 (0x1u << 10) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 */\r
+#define MCAN_TXBTO_TO11 (0x1u << 11) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 */\r
+#define MCAN_TXBTO_TO12 (0x1u << 12) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 */\r
+#define MCAN_TXBTO_TO13 (0x1u << 13) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 */\r
+#define MCAN_TXBTO_TO14 (0x1u << 14) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 */\r
+#define MCAN_TXBTO_TO15 (0x1u << 15) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 */\r
+#define MCAN_TXBTO_TO16 (0x1u << 16) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 */\r
+#define MCAN_TXBTO_TO17 (0x1u << 17) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 */\r
+#define MCAN_TXBTO_TO18 (0x1u << 18) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 */\r
+#define MCAN_TXBTO_TO19 (0x1u << 19) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 */\r
+#define MCAN_TXBTO_TO20 (0x1u << 20) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 */\r
+#define MCAN_TXBTO_TO21 (0x1u << 21) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 */\r
+#define MCAN_TXBTO_TO22 (0x1u << 22) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 */\r
+#define MCAN_TXBTO_TO23 (0x1u << 23) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 */\r
+#define MCAN_TXBTO_TO24 (0x1u << 24) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 */\r
+#define MCAN_TXBTO_TO25 (0x1u << 25) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 */\r
+#define MCAN_TXBTO_TO26 (0x1u << 26) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 */\r
+#define MCAN_TXBTO_TO27 (0x1u << 27) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 */\r
+#define MCAN_TXBTO_TO28 (0x1u << 28) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 */\r
+#define MCAN_TXBTO_TO29 (0x1u << 29) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 */\r
+#define MCAN_TXBTO_TO30 (0x1u << 30) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 */\r
+#define MCAN_TXBTO_TO31 (0x1u << 31) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 */\r
+/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */\r
+#define MCAN_TXBCF_CF0 (0x1u << 0) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 */\r
+#define MCAN_TXBCF_CF1 (0x1u << 1) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 */\r
+#define MCAN_TXBCF_CF2 (0x1u << 2) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 */\r
+#define MCAN_TXBCF_CF3 (0x1u << 3) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 */\r
+#define MCAN_TXBCF_CF4 (0x1u << 4) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 */\r
+#define MCAN_TXBCF_CF5 (0x1u << 5) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 */\r
+#define MCAN_TXBCF_CF6 (0x1u << 6) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 */\r
+#define MCAN_TXBCF_CF7 (0x1u << 7) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 */\r
+#define MCAN_TXBCF_CF8 (0x1u << 8) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 */\r
+#define MCAN_TXBCF_CF9 (0x1u << 9) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 */\r
+#define MCAN_TXBCF_CF10 (0x1u << 10) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 */\r
+#define MCAN_TXBCF_CF11 (0x1u << 11) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 */\r
+#define MCAN_TXBCF_CF12 (0x1u << 12) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 */\r
+#define MCAN_TXBCF_CF13 (0x1u << 13) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 */\r
+#define MCAN_TXBCF_CF14 (0x1u << 14) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 */\r
+#define MCAN_TXBCF_CF15 (0x1u << 15) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 */\r
+#define MCAN_TXBCF_CF16 (0x1u << 16) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 */\r
+#define MCAN_TXBCF_CF17 (0x1u << 17) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 */\r
+#define MCAN_TXBCF_CF18 (0x1u << 18) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 */\r
+#define MCAN_TXBCF_CF19 (0x1u << 19) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 */\r
+#define MCAN_TXBCF_CF20 (0x1u << 20) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 */\r
+#define MCAN_TXBCF_CF21 (0x1u << 21) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 */\r
+#define MCAN_TXBCF_CF22 (0x1u << 22) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 */\r
+#define MCAN_TXBCF_CF23 (0x1u << 23) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 */\r
+#define MCAN_TXBCF_CF24 (0x1u << 24) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 */\r
+#define MCAN_TXBCF_CF25 (0x1u << 25) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 */\r
+#define MCAN_TXBCF_CF26 (0x1u << 26) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 */\r
+#define MCAN_TXBCF_CF27 (0x1u << 27) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 */\r
+#define MCAN_TXBCF_CF28 (0x1u << 28) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 */\r
+#define MCAN_TXBCF_CF29 (0x1u << 29) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 */\r
+#define MCAN_TXBCF_CF30 (0x1u << 30) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 */\r
+#define MCAN_TXBCF_CF31 (0x1u << 31) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 */\r
+/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */\r
+#define MCAN_TXBTIE_TIE0 (0x1u << 0) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 */\r
+#define MCAN_TXBTIE_TIE1 (0x1u << 1) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 */\r
+#define MCAN_TXBTIE_TIE2 (0x1u << 2) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 */\r
+#define MCAN_TXBTIE_TIE3 (0x1u << 3) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 */\r
+#define MCAN_TXBTIE_TIE4 (0x1u << 4) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 */\r
+#define MCAN_TXBTIE_TIE5 (0x1u << 5) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 */\r
+#define MCAN_TXBTIE_TIE6 (0x1u << 6) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 */\r
+#define MCAN_TXBTIE_TIE7 (0x1u << 7) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 */\r
+#define MCAN_TXBTIE_TIE8 (0x1u << 8) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 */\r
+#define MCAN_TXBTIE_TIE9 (0x1u << 9) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 */\r
+#define MCAN_TXBTIE_TIE10 (0x1u << 10) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 */\r
+#define MCAN_TXBTIE_TIE11 (0x1u << 11) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 */\r
+#define MCAN_TXBTIE_TIE12 (0x1u << 12) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 */\r
+#define MCAN_TXBTIE_TIE13 (0x1u << 13) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 */\r
+#define MCAN_TXBTIE_TIE14 (0x1u << 14) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 */\r
+#define MCAN_TXBTIE_TIE15 (0x1u << 15) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 */\r
+#define MCAN_TXBTIE_TIE16 (0x1u << 16) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 */\r
+#define MCAN_TXBTIE_TIE17 (0x1u << 17) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 */\r
+#define MCAN_TXBTIE_TIE18 (0x1u << 18) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 */\r
+#define MCAN_TXBTIE_TIE19 (0x1u << 19) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 */\r
+#define MCAN_TXBTIE_TIE20 (0x1u << 20) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 */\r
+#define MCAN_TXBTIE_TIE21 (0x1u << 21) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 */\r
+#define MCAN_TXBTIE_TIE22 (0x1u << 22) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 */\r
+#define MCAN_TXBTIE_TIE23 (0x1u << 23) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 */\r
+#define MCAN_TXBTIE_TIE24 (0x1u << 24) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 */\r
+#define MCAN_TXBTIE_TIE25 (0x1u << 25) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 */\r
+#define MCAN_TXBTIE_TIE26 (0x1u << 26) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 */\r
+#define MCAN_TXBTIE_TIE27 (0x1u << 27) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 */\r
+#define MCAN_TXBTIE_TIE28 (0x1u << 28) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 */\r
+#define MCAN_TXBTIE_TIE29 (0x1u << 29) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 */\r
+#define MCAN_TXBTIE_TIE30 (0x1u << 30) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 */\r
+#define MCAN_TXBTIE_TIE31 (0x1u << 31) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 */\r
+/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */\r
+#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 */\r
+#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 */\r
+#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 */\r
+#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 */\r
+#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 */\r
+#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 */\r
+#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 */\r
+#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 */\r
+#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 */\r
+#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 */\r
+#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 */\r
+#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 */\r
+#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 */\r
+#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 */\r
+#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 */\r
+#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 */\r
+#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 */\r
+#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 */\r
+#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 */\r
+#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 */\r
+#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 */\r
+#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 */\r
+#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 */\r
+#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 */\r
+#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 */\r
+#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 */\r
+#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 */\r
+#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 */\r
+#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 */\r
+#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 */\r
+#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 */\r
+#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 */\r
+/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */\r
+#define MCAN_TXEFC_EFSA_Pos 2\r
+#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Start Address */\r
+#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)))\r
+#define MCAN_TXEFC_EFS_Pos 16\r
+#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Size */\r
+#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)))\r
+#define MCAN_TXEFC_EFWM_Pos 24\r
+#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Watermark */\r
+#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)))\r
+/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */\r
+#define MCAN_TXEFS_EFFL_Pos 0\r
+#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Fill Level */\r
+#define MCAN_TXEFS_EFGI_Pos 8\r
+#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Get Index */\r
+#define MCAN_TXEFS_EFPI_Pos 16\r
+#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Put Index */\r
+#define MCAN_TXEFS_EFF (0x1u << 24) /**< \brief (MCAN_TXEFS) Event FIFO Full */\r
+#define MCAN_TXEFS_TEFL (0x1u << 25) /**< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost */\r
+/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */\r
+#define MCAN_TXEFA_EFAI_Pos 0\r
+#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /**< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index */\r
+#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)))\r
+/* -------- MCAN Message RAM : Standard Message ID Rx Filter Element -------- */\r
+#define MCAN_RAM_FILT_STD_SIZE (1u) /**< \brief Size of the 11-bit Message ID Rx Filter Element, in words */\r
+#define MCAN_RAM_FILT_SFID2_Pos 0\r
+#define MCAN_RAM_FILT_SFID2_Msk (0x7ffu << MCAN_RAM_FILT_SFID2_Pos) /**< \brief (S0) Standard Filter ID 2 */\r
+#define MCAN_RAM_FILT_SFID2(value) ((MCAN_RAM_FILT_SFID2_Msk & ((value) << MCAN_RAM_FILT_SFID2_Pos)))\r
+#define MCAN_RAM_FILT_SFID2_BUF_IDX_Pos 0\r
+#define MCAN_RAM_FILT_SFID2_BUF_IDX_Msk (0x3fu << MCAN_RAM_FILT_SFID2_BUF_IDX_Pos) /**< \brief (S0) Index of Rx Buffer for storage of a matching message. */\r
+#define MCAN_RAM_FILT_SFID2_BUF_IDX(value) ((MCAN_RAM_FILT_SFID2_BUF_IDX_Msk & ((value) << MCAN_RAM_FILT_SFID2_BUF_IDX_Pos)))\r
+#define MCAN_RAM_FILT_SFID2_FE0 (0x1u << 6) /**< \brief (S0) Generate a pulse at m_can_fe0 filter event pin in case the filter matches. */\r
+#define MCAN_RAM_FILT_SFID2_FE1 (0x1u << 7) /**< \brief (S0) Generate a pulse at m_can_fe1 filter event pin in case the filter matches. */\r
+#define MCAN_RAM_FILT_SFID2_FE2 (0x1u << 8) /**< \brief (S0) Generate a pulse at m_can_fe2 filter event pin in case the filter matches. */\r
+#define MCAN_RAM_FILT_SFID2_BUF (0x0u << 9) /**< \brief (S0) Store message in a Rx buffer. */\r
+#define MCAN_RAM_FILT_SFID2_DBG_A (0x1u << 9) /**< \brief (S0) Debug Message A. */\r
+#define MCAN_RAM_FILT_SFID2_DBG_B (0x2u << 9) /**< \brief (S0) Debug Message B. */\r
+#define MCAN_RAM_FILT_SFID2_DBG_C (0x3u << 9) /**< \brief (S0) Debug Message C. */\r
+#define MCAN_RAM_FILT_SFID1_Pos 16\r
+#define MCAN_RAM_FILT_SFID1_Msk (0x7ffu << MCAN_RAM_FILT_SFID1_Pos) /**< \brief (S0) Standard Filter ID 1 */\r
+#define MCAN_RAM_FILT_SFID1(value) ((MCAN_RAM_FILT_SFID1_Msk & ((value) << MCAN_RAM_FILT_SFID1_Pos)))\r
+#define MCAN_RAM_FILT_SFEC_Pos 27\r
+#define MCAN_RAM_FILT_SFEC_Msk (0x7u << MCAN_RAM_FILT_SFEC_Pos) /**< \brief (S0) Standard Filter Element Configuration */\r
+#define MCAN_RAM_FILT_SFEC(value) ((MCAN_RAM_FILT_SFEC_Msk & ((value) << MCAN_RAM_FILT_SFEC_Pos)))\r
+#define MCAN_RAM_FILT_SFEC_DIS (0x0u << 27) /**< \brief (S0) Disable filter element. */\r
+#define MCAN_RAM_FILT_SFEC_FIFO0 (0x1u << 27) /**< \brief (S0) Store in Rx FIFO 0 if filter matches. */\r
+#define MCAN_RAM_FILT_SFEC_FIFO1 (0x2u << 27) /**< \brief (S0) Store in Rx FIFO 1 if filter matches. */\r
+#define MCAN_RAM_FILT_SFEC_INV (0x3u << 27) /**< \brief (S0) Reject ID if filter matches. */\r
+#define MCAN_RAM_FILT_SFEC_PTY (0x4u << 27) /**< \brief (S0) Set priority if filter matches. */\r
+#define MCAN_RAM_FILT_SFEC_PTY_FIFO0 (0x5u << 27) /**< \brief (S0) Set priority and store in FIFO 0 if filter matches. */\r
+#define MCAN_RAM_FILT_SFEC_PTY_FIFO1 (0x6u << 27) /**< \brief (S0) Set priority and store in FIFO 1 if filter matches. */\r
+#define MCAN_RAM_FILT_SFEC_BUF (0x7u << 27) /**< \brief (S0) Store into Rx Buffer or as debug message. */\r
+#define MCAN_RAM_FILT_SFT_Pos 30\r
+#define MCAN_RAM_FILT_SFT_Msk (0x3u << MCAN_RAM_FILT_SFT_Pos) /**< \brief (S0) Standard Filter Type */\r
+#define MCAN_RAM_FILT_SFT(value) ((MCAN_RAM_FILT_SFT_Msk & ((value) << MCAN_RAM_FILT_SFT_Pos)))\r
+#define MCAN_RAM_FILT_SFT_RANGE (0x0u << 30) /**< \brief (S0) Range filter from SF1ID to SF2ID. */\r
+#define MCAN_RAM_FILT_SFT_DUAL_ID (0x1u << 30) /**< \brief (S0) Dual ID filter for SF1ID or SF2ID. */\r
+#define MCAN_RAM_FILT_SFT_CLASSIC (0x2u << 30) /**< \brief (S0) Classic filter: SF1ID = filter, SF2ID = mask. */\r
+/* -------- MCAN Message RAM : Extended Message ID Rx Filter Element : F0 Word -------- */\r
+#define MCAN_RAM_FILT_EXT_SIZE (2u) /**< \brief Size of the 29-bit Message ID Rx Filter Element, in words */\r
+#define MCAN_RAM_FILT_EFID1_Pos 0\r
+#define MCAN_RAM_FILT_EFID1_Msk (0x1fffffffu << MCAN_RAM_FILT_EFID1_Pos) /**< \brief (F0) Standard Filter ID 1 */\r
+#define MCAN_RAM_FILT_EFID1(value) ((MCAN_RAM_FILT_EFID1_Msk & ((value) << MCAN_RAM_FILT_EFID1_Pos)))\r
+#define MCAN_RAM_FILT_EFEC_Pos 29\r
+#define MCAN_RAM_FILT_EFEC_Msk (0x7u << MCAN_RAM_FILT_EFEC_Pos) /**< \brief (F0) Extended Filter Element Configuration */\r
+#define MCAN_RAM_FILT_EFEC(value) ((MCAN_RAM_FILT_EFEC_Msk & ((value) << MCAN_RAM_FILT_EFEC_Pos)))\r
+#define MCAN_RAM_FILT_EFEC_DIS (0x0u << 29) /**< \brief (F0) Disable filter element. */\r
+#define MCAN_RAM_FILT_EFEC_FIFO0 (0x1u << 29) /**< \brief (F0) Store in Rx FIFO 0 if filter matches. */\r
+#define MCAN_RAM_FILT_EFEC_FIFO1 (0x2u << 29) /**< \brief (F0) Store in Rx FIFO 1 if filter matches. */\r
+#define MCAN_RAM_FILT_EFEC_INV (0x3u << 29) /**< \brief (F0) Reject ID if filter matches. */\r
+#define MCAN_RAM_FILT_EFEC_PTY (0x4u << 29) /**< \brief (F0) Set priority if filter matches. */\r
+#define MCAN_RAM_FILT_EFEC_PTY_FIFO0 (0x5u << 29) /**< \brief (F0) Set priority and store in FIFO 0 if filter matches. */\r
+#define MCAN_RAM_FILT_EFEC_PTY_FIFO1 (0x6u << 29) /**< \brief (F0) Set priority and store in FIFO 1 if filter matches. */\r
+#define MCAN_RAM_FILT_EFEC_BUF (0x7u << 29) /**< \brief (F0) Store into Rx Buffer or as debug message. */\r
+/* -------- MCAN Message RAM : Extended Message ID Rx Filter Element : F1 Word -------- */\r
+#define MCAN_RAM_FILT_EFID2_Pos 0\r
+#define MCAN_RAM_FILT_EFID2_Msk (0x1fffffffu << MCAN_RAM_FILT_EFID2_Pos) /**< \brief (F1) Standard Filter ID 2 */\r
+#define MCAN_RAM_FILT_EFID2(value) ((MCAN_RAM_FILT_EFID2_Msk & ((value) << MCAN_RAM_FILT_EFID2_Pos)))\r
+#define MCAN_RAM_FILT_EFID2_BUF_IDX_Pos 0\r
+#define MCAN_RAM_FILT_EFID2_BUF_IDX_Msk (0x3fu << MCAN_RAM_FILT_EFID2_BUF_IDX_Pos) /**< \brief (F1) Index of Rx Buffer for storage of a matching message. */\r
+#define MCAN_RAM_FILT_EFID2_BUF_IDX(value) ((MCAN_RAM_FILT_EFID2_BUF_IDX_Msk & ((value) << MCAN_RAM_FILT_EFID2_BUF_IDX_Pos)))\r
+#define MCAN_RAM_FILT_EFID2_FE0 (0x1u << 6) /**< \brief (F1) Generate a pulse at m_can_fe0 filter event pin in case the filter matches. */\r
+#define MCAN_RAM_FILT_EFID2_FE1 (0x1u << 7) /**< \brief (F1) Generate a pulse at m_can_fe1 filter event pin in case the filter matches. */\r
+#define MCAN_RAM_FILT_EFID2_FE2 (0x1u << 8) /**< \brief (F1) Generate a pulse at m_can_fe2 filter event pin in case the filter matches. */\r
+#define MCAN_RAM_FILT_EFID2_BUF (0x0u << 9) /**< \brief (F1) Store message in a Rx buffer. */\r
+#define MCAN_RAM_FILT_EFID2_DBG_A (0x1u << 9) /**< \brief (F1) Debug Message A. */\r
+#define MCAN_RAM_FILT_EFID2_DBG_B (0x2u << 9) /**< \brief (F1) Debug Message B. */\r
+#define MCAN_RAM_FILT_EFID2_DBG_C (0x3u << 9) /**< \brief (F1) Debug Message C. */\r
+#define MCAN_RAM_FILT_EFT_Pos 30\r
+#define MCAN_RAM_FILT_EFT_Msk (0x3u << MCAN_RAM_FILT_EFT_Pos) /**< \brief (F1) Extended Filter Type */\r
+#define MCAN_RAM_FILT_EFT(value) ((MCAN_RAM_FILT_EFT_Msk & ((value) << MCAN_RAM_FILT_EFT_Pos)))\r
+#define MCAN_RAM_FILT_EFT_RANGE_EIDM (0x0u << 30) /**< \brief (F1) Range filter from EF1ID to EF2ID (Extended ID Mask applied). */\r
+#define MCAN_RAM_FILT_EFT_DUAL_ID (0x1u << 30) /**< \brief (F1) Dual ID filter for EF1ID or EF2ID. */\r
+#define MCAN_RAM_FILT_EFT_CLASSIC (0x2u << 30) /**< \brief (F1) Classic filter: EF1ID = filter, EF2ID = mask. */\r
+#define MCAN_RAM_FILT_EFT_RANGE (0x3u << 30) /**< \brief (F1) Range filter from EF1ID to EF2ID, Extended ID Mask not applied. */\r
+/* -------- MCAN Message RAM : Tx/Rx Buffer Element : T0/R0 Heading Word -------- */\r
+#define MCAN_RAM_BUF_HDR_SIZE (2u) /**< \brief Size of the header in Rx and Tx Buffer Elements, in words */\r
+#define MCAN_RAM_BUF_ID_XTD_Pos 0\r
+#define MCAN_RAM_BUF_ID_XTD_Msk (0x1fffffffu << MCAN_RAM_BUF_ID_XTD_Pos) /**< \brief (T0, R0) Extended (29-bit) Message identifier */\r
+#define MCAN_RAM_BUF_ID_XTD(value) ((MCAN_RAM_BUF_ID_XTD_Msk & ((value) << MCAN_RAM_BUF_ID_XTD_Pos)))\r
+#define MCAN_RAM_BUF_ID_STD_Pos 18\r
+#define MCAN_RAM_BUF_ID_STD_Msk (0x7ffu << MCAN_RAM_BUF_ID_STD_Pos) /**< \brief (T0, R0) Standard (11-bit) Message identifier */\r
+#define MCAN_RAM_BUF_ID_STD(value) ((MCAN_RAM_BUF_ID_STD_Msk & ((value) << MCAN_RAM_BUF_ID_STD_Pos)))\r
+#define MCAN_RAM_BUF_RTR (0x1u << 29) /**< \brief (T0, R0) Remote Transmission Request */\r
+#define MCAN_RAM_BUF_XTD (0x1u << 30) /**< \brief (T0, R0) Flag that signals an extended Message identifier */\r
+#define MCAN_RAM_BUF_ESI (0x1u << 31) /**< \brief (T0, R0) Error State Indicator */\r
+/* -------- MCAN Message RAM : Tx/Rx Buffer Element : T1/R1 Heading Word -------- */\r
+#define MCAN_RAM_BUF_RXTS_Pos 0\r
+#define MCAN_RAM_BUF_RXTS_Msk (0xffffu << MCAN_RAM_BUF_RXTS_Pos) /**< \brief (R1) Rx Timestamp */\r
+#define MCAN_RAM_BUF_DLC_Pos 16\r
+#define MCAN_RAM_BUF_DLC_Msk (0xfu << MCAN_RAM_BUF_DLC_Pos) /**< \brief (T1, R1) Data Length Code */\r
+#define MCAN_RAM_BUF_DLC(value) ((MCAN_RAM_BUF_DLC_Msk & ((value) << MCAN_RAM_BUF_DLC_Pos)))\r
+#define MCAN_RAM_BUF_BRS (0x1u << 20) /**< \brief (T1, R1) Flag that signals a frame transmitted with bit rate switching */\r
+#define MCAN_RAM_BUF_FDF (0x1u << 21) /**< \brief (T1, R1) Flag that signals a frame in CAN FD format */\r
+#define MCAN_RAM_BUF_EFC (0x1u << 23) /**< \brief (T1) Event FIFO Control */\r
+#define MCAN_RAM_BUF_FIDX_Pos 24\r
+#define MCAN_RAM_BUF_FIDX_Msk (0x7fu << MCAN_RAM_BUF_FIDX_Pos) /**< \brief (R1) Filter Index */\r
+#define MCAN_RAM_BUF_MM_Pos 24\r
+#define MCAN_RAM_BUF_MM_Msk (0xffu << MCAN_RAM_BUF_MM_Pos) /**< \brief (T1) Message Marker */\r
+#define MCAN_RAM_BUF_MM(value) ((MCAN_RAM_BUF_MM_Msk & ((value) << MCAN_RAM_BUF_MM_Pos)))\r
+#define MCAN_RAM_BUF_ANMF (0x1u << 31) /**< \brief (R1) Flag that signals a received frame accepted without matching any Rx Filter Element */\r
+/* -------- MCAN Message RAM : Tx Event Element -------- */\r
+#define MCAN_RAM_TX_EVT_SIZE (2u) /**< \brief Size of the Tx Event Element, in words */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_MCAN_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_MPDDRC_COMPONENT_\r
+#define _SAMA5D2_MPDDRC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR AHB Multi-port DDR-SDRAM Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_MPDDRC AHB Multi-port DDR-SDRAM Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Mpddrc hardware registers */\r
+typedef struct {\r
+ __IO uint32_t MPDDRC_MR; /**< \brief (Mpddrc Offset: 0x00) MPDDRC Mode Register */\r
+ __IO uint32_t MPDDRC_RTR; /**< \brief (Mpddrc Offset: 0x04) MPDDRC Refresh Timer Register */\r
+ __IO uint32_t MPDDRC_CR; /**< \brief (Mpddrc Offset: 0x08) MPDDRC Configuration Register */\r
+ __IO uint32_t MPDDRC_TPR0; /**< \brief (Mpddrc Offset: 0x0C) MPDDRC Timing Parameter 0 Register */\r
+ __IO uint32_t MPDDRC_TPR1; /**< \brief (Mpddrc Offset: 0x10) MPDDRC Timing Parameter 1 Register */\r
+ __IO uint32_t MPDDRC_TPR2; /**< \brief (Mpddrc Offset: 0x14) MPDDRC Timing Parameter 2 Register */\r
+ __I uint32_t Reserved1[1];\r
+ __IO uint32_t MPDDRC_LPR; /**< \brief (Mpddrc Offset: 0x1C) MPDDRC Low-power Register */\r
+ __IO uint32_t MPDDRC_MD; /**< \brief (Mpddrc Offset: 0x20) MPDDRC Memory Device Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t MPDDRC_LPDDR23_LPR; /**< \brief (Mpddrc Offset: 0x28) MPDDRC LPDDR2-LPDDR3 Low-power Register */\r
+ __IO uint32_t MPDDRC_LPDDR23_CAL_MR4; /**< \brief (Mpddrc Offset: 0x2C) MPDDRC LPDDR2-LPDDR3 Calibration and MR4 Register */\r
+ __IO uint32_t MPDDRC_LPDDR23_TIM_CAL; /**< \brief (Mpddrc Offset: 0x30) MPDDRC LPDDR2-LPDDR3 Timing Calibration Register */\r
+ __IO uint32_t MPDDRC_IO_CALIBR; /**< \brief (Mpddrc Offset: 0x34) MPDDRC IO Calibration */\r
+ __IO uint32_t MPDDRC_OCMS; /**< \brief (Mpddrc Offset: 0x38) MPDDRC OCMS Register */\r
+ __O uint32_t MPDDRC_OCMS_KEY1; /**< \brief (Mpddrc Offset: 0x3C) MPDDRC OCMS KEY1 Register */\r
+ __O uint32_t MPDDRC_OCMS_KEY2; /**< \brief (Mpddrc Offset: 0x40) MPDDRC OCMS KEY2 Register */\r
+ __IO uint32_t MPDDRC_CONF_ARBITER; /**< \brief (Mpddrc Offset: 0x44) MPDDRC Configuration Arbiter Register */\r
+ __IO uint32_t MPDDRC_TIMEOUT; /**< \brief (Mpddrc Offset: 0x48) MPDDRC Time-out Port 0/1/2/3 Register */\r
+ __IO uint32_t MPDDRC_REQ_PORT_0123; /**< \brief (Mpddrc Offset: 0x4C) MPDDRC Request Port 0/1/2/3 Register */\r
+ __IO uint32_t MPDDRC_REQ_PORT_4567; /**< \brief (Mpddrc Offset: 0x50) MPDDRC Request Port 4/5/6/7 Register */\r
+ __I uint32_t MPDDRC_BDW_PORT_0123; /**< \brief (Mpddrc Offset: 0x54) MPDDRC Bandwidth Port 0/1/2/3 Register */\r
+ __I uint32_t MPDDRC_BDW_PORT_4567; /**< \brief (Mpddrc Offset: 0x58) MPDDRC Bandwidth Port 4/5/6/7 Register */\r
+ __IO uint32_t MPDDRC_RD_DATA_PATH; /**< \brief (Mpddrc Offset: 0x5C) MPDDRC Read Datapath Register */\r
+ __IO uint32_t MPDDRC_MCFGR; /**< \brief (Mpddrc Offset: 0x60) MPDDRC Monitor Configuration */\r
+ __IO uint32_t MPDDRC_MADDR0; /**< \brief (Mpddrc Offset: 0x64) MPDDRC Monitor Address High/Low port 0 */\r
+ __IO uint32_t MPDDRC_MADDR1; /**< \brief (Mpddrc Offset: 0x68) MPDDRC Monitor Address High/Low port 1 */\r
+ __IO uint32_t MPDDRC_MADDR2; /**< \brief (Mpddrc Offset: 0x6C) MPDDRC Monitor Address High/Low port 2 */\r
+ __IO uint32_t MPDDRC_MADDR3; /**< \brief (Mpddrc Offset: 0x70) MPDDRC Monitor Address High/Low port 3 */\r
+ __IO uint32_t MPDDRC_MADDR4; /**< \brief (Mpddrc Offset: 0x74) MPDDRC Monitor Address High/Low port 4 */\r
+ __IO uint32_t MPDDRC_MADDR5; /**< \brief (Mpddrc Offset: 0x78) MPDDRC Monitor Address High/Low port 5 */\r
+ __IO uint32_t MPDDRC_MADDR6; /**< \brief (Mpddrc Offset: 0x7C) MPDDRC Monitor Address High/Low port 6 */\r
+ __IO uint32_t MPDDRC_MADDR7; /**< \brief (Mpddrc Offset: 0x80) MPDDRC Monitor Address High/Low port 7 */\r
+ __I uint32_t MPDDRC_MINFO0; /**< \brief (Mpddrc Offset: 0x84) MPDDRC Monitor Information port 0 */\r
+ __I uint32_t MPDDRC_MINFO1; /**< \brief (Mpddrc Offset: 0x88) MPDDRC Monitor Information port 1 */\r
+ __I uint32_t MPDDRC_MINFO2; /**< \brief (Mpddrc Offset: 0x8C) MPDDRC Monitor Information port 2 */\r
+ __I uint32_t MPDDRC_MINFO3; /**< \brief (Mpddrc Offset: 0x90) MPDDRC Monitor Information port 3 */\r
+ __I uint32_t MPDDRC_MINFO4; /**< \brief (Mpddrc Offset: 0x94) MPDDRC Monitor Information port 4 */\r
+ __I uint32_t MPDDRC_MINFO5; /**< \brief (Mpddrc Offset: 0x98) MPDDRC Monitor Information port 5 */\r
+ __I uint32_t MPDDRC_MINFO6; /**< \brief (Mpddrc Offset: 0x9C) MPDDRC Monitor Information port 6 */\r
+ __I uint32_t MPDDRC_MINFO7; /**< \brief (Mpddrc Offset: 0xA0) MPDDRC Monitor Information port 7 */\r
+ __I uint32_t Reserved3[16];\r
+ __IO uint32_t MPDDRC_WPMR; /**< \brief (Mpddrc Offset: 0xE4) MPDDRC Write Protection Mode Register */\r
+ __I uint32_t MPDDRC_WPSR; /**< \brief (Mpddrc Offset: 0xE8) MPDDRC Write Protection Status Register */\r
+ __I uint32_t Reserved4[4];\r
+ __I uint32_t MPDDRC_VERSION; /**< \brief (Mpddrc Offset: 0xFC) MPDDRC Version Register */\r
+ __IO uint32_t MPDDRC_DLL_OS; /**< \brief (Mpddrc Offset: 0x100) MPDDRC DLL Offset Selection Register */\r
+ __IO uint32_t MPDDRC_DLL_MAO; /**< \brief (Mpddrc Offset: 0x104) MPDDRC DLL MASTER Offset Register */\r
+ __IO uint32_t MPDDRC_DLL_SO0; /**< \brief (Mpddrc Offset: 0x108) MPDDRC DLL SLAVE Offset 0 Register */\r
+ __IO uint32_t MPDDRC_DLL_SO1; /**< \brief (Mpddrc Offset: 0x10C) MPDDRC DLL SLAVE Offset 1 Register */\r
+ __IO uint32_t MPDDRC_DLL_WRO; /**< \brief (Mpddrc Offset: 0x110) MPDDRC DLL CLKWR Offset Register */\r
+ __IO uint32_t MPDDRC_DLL_ADO; /**< \brief (Mpddrc Offset: 0x114) MPDDRC DLL CLKAD Offset Register */\r
+ __I uint32_t MPDDRC_DLL_SM[4]; /**< \brief (Mpddrc Offset: 0x118) MPDDRC DLL Status MASTER0 Register */\r
+ __I uint32_t MPDDRC_DLL_SSL[8]; /**< \brief (Mpddrc Offset: 0x128) MPDDRC DLL Status SLAVE0 Register */\r
+ __I uint32_t MPDDRC_DLL_SWR[4]; /**< \brief (Mpddrc Offset: 0x148) MPDDRC DLL Status CLKWR0 Register */\r
+ __I uint32_t MPDDRC_DLL_SAD; /**< \brief (Mpddrc Offset: 0x158) MPDDRC DLL Status CLKAD Register */\r
+} Mpddrc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- MPDDRC_MR : (MPDDRC Offset: 0x00) MPDDRC Mode Register -------- */\r
+#define MPDDRC_MR_MODE_Pos 0\r
+#define MPDDRC_MR_MODE_Msk (0x7u << MPDDRC_MR_MODE_Pos) /**< \brief (MPDDRC_MR) MPDDRC Command Mode */\r
+#define MPDDRC_MR_MODE(value) ((MPDDRC_MR_MODE_Msk & ((value) << MPDDRC_MR_MODE_Pos)))\r
+#define MPDDRC_MR_MODE_NORMAL_CMD (0x0u << 0) /**< \brief (MPDDRC_MR) Normal Mode. Any access to the MPDDRC is decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */\r
+#define MPDDRC_MR_MODE_NOP_CMD (0x1u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues a NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */\r
+#define MPDDRC_MR_MODE_PRCGALL_CMD (0x2u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues the All Banks Precharge command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. */\r
+#define MPDDRC_MR_MODE_LMR_CMD (0x3u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues a Load Mode Register command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */\r
+#define MPDDRC_MR_MODE_RFSH_CMD (0x4u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an Auto-Refresh command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an All Banks Precharge command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */\r
+#define MPDDRC_MR_MODE_EXT_LMR_CMD (0x5u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an Extended Load Mode Register command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The write in the DDR-SDRAM must be done in the appropriate bank. */\r
+#define MPDDRC_MR_MODE_DEEP_CALIB_MD (0x6u << 0) /**< \brief (MPDDRC_MR) Deep Power mode: Access to Deep Power-down modeCalibration command: to calibrate RTT and RON values for the Process Voltage Temperature (PVT) (DDR3-SDRAM device) */\r
+#define MPDDRC_MR_MODE_LPDDR2_LPDDR3_CMD (0x7u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an LPDDR2/LPDDR3 Mode Register command when the device is accessed regardless of the cycle. To activate this mode, the Mode Register command must be followed by a write to the low-power DDR2-SDRAM or to the low-power DDR3-SDRAM. */\r
+#define MPDDRC_MR_DAI (0x1u << 4) /**< \brief (MPDDRC_MR) Device Auto-Initialization Status */\r
+#define MPDDRC_MR_DAI_DAI_COMPLETE (0x0u << 4) /**< \brief (MPDDRC_MR) DAI complete */\r
+#define MPDDRC_MR_DAI_DAI_IN_PROGESSS (0x1u << 4) /**< \brief (MPDDRC_MR) DAI still in progress */\r
+#define MPDDRC_MR_MRS_Pos 8\r
+#define MPDDRC_MR_MRS_Msk (0xffu << MPDDRC_MR_MRS_Pos) /**< \brief (MPDDRC_MR) Mode Register Select LPDDR2/LPDDR3 */\r
+#define MPDDRC_MR_MRS(value) ((MPDDRC_MR_MRS_Msk & ((value) << MPDDRC_MR_MRS_Pos)))\r
+/* -------- MPDDRC_RTR : (MPDDRC Offset: 0x04) MPDDRC Refresh Timer Register -------- */\r
+#define MPDDRC_RTR_COUNT_Pos 0\r
+#define MPDDRC_RTR_COUNT_Msk (0xfffu << MPDDRC_RTR_COUNT_Pos) /**< \brief (MPDDRC_RTR) MPDDRC Refresh Timer Count */\r
+#define MPDDRC_RTR_COUNT(value) ((MPDDRC_RTR_COUNT_Msk & ((value) << MPDDRC_RTR_COUNT_Pos)))\r
+#define MPDDRC_RTR_ADJ_REF (0x1u << 16) /**< \brief (MPDDRC_RTR) Adjust Refresh Rate */\r
+#define MPDDRC_RTR_REF_PB (0x1u << 17) /**< \brief (MPDDRC_RTR) Refresh Per Bank */\r
+#define MPDDRC_RTR_MR4_VALUE_Pos 20\r
+#define MPDDRC_RTR_MR4_VALUE_Msk (0x7u << MPDDRC_RTR_MR4_VALUE_Pos) /**< \brief (MPDDRC_RTR) Content of MR4 Register */\r
+#define MPDDRC_RTR_MR4_VALUE(value) ((MPDDRC_RTR_MR4_VALUE_Msk & ((value) << MPDDRC_RTR_MR4_VALUE_Pos)))\r
+/* -------- MPDDRC_CR : (MPDDRC Offset: 0x08) MPDDRC Configuration Register -------- */\r
+#define MPDDRC_CR_NC_Pos 0\r
+#define MPDDRC_CR_NC_Msk (0x3u << MPDDRC_CR_NC_Pos) /**< \brief (MPDDRC_CR) Number of Column Bits */\r
+#define MPDDRC_CR_NC(value) ((MPDDRC_CR_NC_Msk & ((value) << MPDDRC_CR_NC_Pos)))\r
+#define MPDDRC_CR_NC_DDR9_MDDR8_COL_BITS (0x0u << 0) /**< \brief (MPDDRC_CR) 9 bits for DDR, 8-bit for low-power DDR1-SDRAM */\r
+#define MPDDRC_CR_NC_10_COL_BITS (0x1u << 0) /**< \brief (MPDDRC_CR) 10 bits for DDR, 9-bit for low-power DDR1-SDRAM */\r
+#define MPDDRC_CR_NC_DDR11_MDDR10_COL_BITS (0x2u << 0) /**< \brief (MPDDRC_CR) 11 bits for DDR, 10-bit for low-power DDR1-SDRAM */\r
+#define MPDDRC_CR_NC_DDR12_MDDR11_COL_BITS (0x3u << 0) /**< \brief (MPDDRC_CR) 12 bits for DDR, 11-bit for low-power DDR1-SDRAM */\r
+#define MPDDRC_CR_NR_Pos 2\r
+#define MPDDRC_CR_NR_Msk (0x3u << MPDDRC_CR_NR_Pos) /**< \brief (MPDDRC_CR) Number of Row Bits */\r
+#define MPDDRC_CR_NR(value) ((MPDDRC_CR_NR_Msk & ((value) << MPDDRC_CR_NR_Pos)))\r
+#define MPDDRC_CR_NR_11_ROW_BITS (0x0u << 2) /**< \brief (MPDDRC_CR) 11 bits to define the row number, up to 2048 rows */\r
+#define MPDDRC_CR_NR_12_ROW_BITS (0x1u << 2) /**< \brief (MPDDRC_CR) 12 bits to define the row number, up to 4096 rows */\r
+#define MPDDRC_CR_NR_13_ROW_BITS (0x2u << 2) /**< \brief (MPDDRC_CR) 13 bits to define the row number, up to 8192 rows */\r
+#define MPDDRC_CR_NR_14_ROW_BITS (0x3u << 2) /**< \brief (MPDDRC_CR) 14 bits to define the row number, up to 16384 rows */\r
+#define MPDDRC_CR_CAS_Pos 4\r
+#define MPDDRC_CR_CAS_Msk (0x7u << MPDDRC_CR_CAS_Pos) /**< \brief (MPDDRC_CR) CAS Latency */\r
+#define MPDDRC_CR_CAS(value) ((MPDDRC_CR_CAS_Msk & ((value) << MPDDRC_CR_CAS_Pos)))\r
+#define MPDDRC_CR_CAS_DDR_CAS2 (0x2u << 4) /**< \brief (MPDDRC_CR) LPDDR1 CAS Latency 2 */\r
+#define MPDDRC_CR_CAS_DDR_CAS3 (0x3u << 4) /**< \brief (MPDDRC_CR) LPDDR3/DDR2/LPDDR2/LPDDR1 CAS Latency 3 */\r
+#define MPDDRC_CR_CAS_DDR_CAS5 (0x5u << 4) /**< \brief (MPDDRC_CR) DDR3 CAS Latency 5 */\r
+#define MPDDRC_CR_CAS_DDR_CAS6 (0x6u << 4) /**< \brief (MPDDRC_CR) DDR3LPDDR3 CAS Latency 6 */\r
+#define MPDDRC_CR_DLL (0x1u << 7) /**< \brief (MPDDRC_CR) Reset DLL */\r
+#define MPDDRC_CR_DLL_RESET_DISABLED (0x0u << 7) /**< \brief (MPDDRC_CR) Disable DLL reset */\r
+#define MPDDRC_CR_DLL_RESET_ENABLED (0x1u << 7) /**< \brief (MPDDRC_CR) Enable DLL reset */\r
+#define MPDDRC_CR_DIC_DS (0x1u << 8) /**< \brief (MPDDRC_CR) Output Driver Impedance Control (Drive Strength) */\r
+#define MPDDRC_CR_DIC_DS_DDR2_NORMALSTRENGTH_DDR3_RZQ6 (0x0u << 8) /**< \brief (MPDDRC_CR) Normal driver strength (DDR2) - RZQ/6 (40 [NOM], DDR3) */\r
+#define MPDDRC_CR_DIC_DS_DDR2_WEAKSTRENGTH_DDR3_RZQ7 (0x1u << 8) /**< \brief (MPDDRC_CR) Weak driver strength (DDR2) - RZQ/7 (34 [NOM], DDR3) */\r
+#define MPDDRC_CR_DIS_DLL (0x1u << 9) /**< \brief (MPDDRC_CR) DISABLE DLL */\r
+#define MPDDRC_CR_ZQ_Pos 10\r
+#define MPDDRC_CR_ZQ_Msk (0x3u << MPDDRC_CR_ZQ_Pos) /**< \brief (MPDDRC_CR) ZQ Calibration */\r
+#define MPDDRC_CR_ZQ(value) ((MPDDRC_CR_ZQ_Msk & ((value) << MPDDRC_CR_ZQ_Pos)))\r
+#define MPDDRC_CR_ZQ_INIT (0x0u << 10) /**< \brief (MPDDRC_CR) Calibration command after initialization */\r
+#define MPDDRC_CR_ZQ_LONG (0x1u << 10) /**< \brief (MPDDRC_CR) Long calibration */\r
+#define MPDDRC_CR_ZQ_SHORT (0x2u << 10) /**< \brief (MPDDRC_CR) Short calibration */\r
+#define MPDDRC_CR_ZQ_RESET (0x3u << 10) /**< \brief (MPDDRC_CR) ZQ Reset */\r
+#define MPDDRC_CR_OCD_Pos 12\r
+#define MPDDRC_CR_OCD_Msk (0x7u << MPDDRC_CR_OCD_Pos) /**< \brief (MPDDRC_CR) Off-chip Driver */\r
+#define MPDDRC_CR_OCD(value) ((MPDDRC_CR_OCD_Msk & ((value) << MPDDRC_CR_OCD_Pos)))\r
+#define MPDDRC_CR_OCD_DDR2_EXITCALIB (0x0u << 12) /**< \brief (MPDDRC_CR) Exit from OCD Calibration mode and maintain settings */\r
+#define MPDDRC_CR_OCD_DDR2_DEFAULT_CALIB (0x7u << 12) /**< \brief (MPDDRC_CR) OCD calibration default */\r
+#define MPDDRC_CR_DQMS (0x1u << 16) /**< \brief (MPDDRC_CR) Mask Data is Shared */\r
+#define MPDDRC_CR_DQMS_NOT_SHARED (0x0u << 16) /**< \brief (MPDDRC_CR) DQM is not shared with another controller */\r
+#define MPDDRC_CR_DQMS_SHARED (0x1u << 16) /**< \brief (MPDDRC_CR) DQM is shared with another controller */\r
+#define MPDDRC_CR_ENRDM (0x1u << 17) /**< \brief (MPDDRC_CR) Enable Read Measure */\r
+#define MPDDRC_CR_ENRDM_OFF (0x0u << 17) /**< \brief (MPDDRC_CR) DQS/DDR_DATA phase error correction is disabled */\r
+#define MPDDRC_CR_ENRDM_ON (0x1u << 17) /**< \brief (MPDDRC_CR) DQS/DDR_DATA phase error correction is enabled */\r
+#define MPDDRC_CR_LC_LPDDR1 (0x1u << 19) /**< \brief (MPDDRC_CR) Low-cost Low-power DDR1 */\r
+#define MPDDRC_CR_LC_LPDDR1_NOT_2_BANKS (0x0u << 19) /**< \brief (MPDDRC_CR) Any type of memory devices except of low cost, low density Low Power DDR1. */\r
+#define MPDDRC_CR_LC_LPDDR1_2_BANKS_LPDDR1 (0x1u << 19) /**< \brief (MPDDRC_CR) Low-cost and low-density low-power DDR1. These devices have a density of 32 Mbits and are organized as two internal banks. To use this feature, the user has to define the type of memory and the data bus width (see Section 8.8 "MPDDRC Memory Device Register").The 16-bit memory device is organized as 2 banks, 9 columns and 11 rows.The 32-bit memory device is organized as 2 banks, 8 columns and 11 rows.It is impossible to use two 16-bit memory devices (2 x 32 Mbits) for creating one 32-bit memory device (64 Mbits). In this case, it is recommended to use one 32-bit memory device which embeds four internal banks. */\r
+#define MPDDRC_CR_NB (0x1u << 20) /**< \brief (MPDDRC_CR) Number of Banks */\r
+#define MPDDRC_CR_NB_4_BANKS (0x0u << 20) /**< \brief (MPDDRC_CR) 4-bank memory devices */\r
+#define MPDDRC_CR_NB_8_BANKS (0x1u << 20) /**< \brief (MPDDRC_CR) 8 banks. Only possible when using the DDR2-SDRAM and low-power DDR2-SDRAM and DDR3-SDRAM and low-power DDR3-SDRAM devices. */\r
+#define MPDDRC_CR_NDQS (0x1u << 21) /**< \brief (MPDDRC_CR) Not DQS */\r
+#define MPDDRC_CR_NDQS_ENABLED (0x0u << 21) /**< \brief (MPDDRC_CR) Not DQS is enabled */\r
+#define MPDDRC_CR_NDQS_DISABLED (0x1u << 21) /**< \brief (MPDDRC_CR) Not DQS is disabled */\r
+#define MPDDRC_CR_DECOD (0x1u << 22) /**< \brief (MPDDRC_CR) Type of Decoding */\r
+#define MPDDRC_CR_DECOD_SEQUENTIAL (0x0u << 22) /**< \brief (MPDDRC_CR) Method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank. */\r
+#define MPDDRC_CR_DECOD_INTERLEAVED (0x1u << 22) /**< \brief (MPDDRC_CR) Method for address mapping where banks alternate at each SDRAM end page of the current bank. */\r
+#define MPDDRC_CR_UNAL (0x1u << 23) /**< \brief (MPDDRC_CR) Support Unaligned Access */\r
+#define MPDDRC_CR_UNAL_UNSUPPORTED (0x0u << 23) /**< \brief (MPDDRC_CR) Unaligned access is not supported. */\r
+#define MPDDRC_CR_UNAL_SUPPORTED (0x1u << 23) /**< \brief (MPDDRC_CR) Unaligned access is supported. */\r
+/* -------- MPDDRC_TPR0 : (MPDDRC Offset: 0x0C) MPDDRC Timing Parameter 0 Register -------- */\r
+#define MPDDRC_TPR0_TRAS_Pos 0\r
+#define MPDDRC_TPR0_TRAS_Msk (0xfu << MPDDRC_TPR0_TRAS_Pos) /**< \brief (MPDDRC_TPR0) Active to Precharge Delay */\r
+#define MPDDRC_TPR0_TRAS(value) ((MPDDRC_TPR0_TRAS_Msk & ((value) << MPDDRC_TPR0_TRAS_Pos)))\r
+#define MPDDRC_TPR0_TRCD_Pos 4\r
+#define MPDDRC_TPR0_TRCD_Msk (0xfu << MPDDRC_TPR0_TRCD_Pos) /**< \brief (MPDDRC_TPR0) Row to Column Delay */\r
+#define MPDDRC_TPR0_TRCD(value) ((MPDDRC_TPR0_TRCD_Msk & ((value) << MPDDRC_TPR0_TRCD_Pos)))\r
+#define MPDDRC_TPR0_TWR_Pos 8\r
+#define MPDDRC_TPR0_TWR_Msk (0xfu << MPDDRC_TPR0_TWR_Pos) /**< \brief (MPDDRC_TPR0) Write Recovery Delay */\r
+#define MPDDRC_TPR0_TWR(value) ((MPDDRC_TPR0_TWR_Msk & ((value) << MPDDRC_TPR0_TWR_Pos)))\r
+#define MPDDRC_TPR0_TRC_Pos 12\r
+#define MPDDRC_TPR0_TRC_Msk (0xfu << MPDDRC_TPR0_TRC_Pos) /**< \brief (MPDDRC_TPR0) Row Cycle Delay */\r
+#define MPDDRC_TPR0_TRC(value) ((MPDDRC_TPR0_TRC_Msk & ((value) << MPDDRC_TPR0_TRC_Pos)))\r
+#define MPDDRC_TPR0_TRP_Pos 16\r
+#define MPDDRC_TPR0_TRP_Msk (0xfu << MPDDRC_TPR0_TRP_Pos) /**< \brief (MPDDRC_TPR0) Row Precharge Delay */\r
+#define MPDDRC_TPR0_TRP(value) ((MPDDRC_TPR0_TRP_Msk & ((value) << MPDDRC_TPR0_TRP_Pos)))\r
+#define MPDDRC_TPR0_TRRD_Pos 20\r
+#define MPDDRC_TPR0_TRRD_Msk (0xfu << MPDDRC_TPR0_TRRD_Pos) /**< \brief (MPDDRC_TPR0) Active BankA to Active BankB */\r
+#define MPDDRC_TPR0_TRRD(value) ((MPDDRC_TPR0_TRRD_Msk & ((value) << MPDDRC_TPR0_TRRD_Pos)))\r
+#define MPDDRC_TPR0_TWTR_Pos 24\r
+#define MPDDRC_TPR0_TWTR_Msk (0xfu << MPDDRC_TPR0_TWTR_Pos) /**< \brief (MPDDRC_TPR0) Internal Write to Read Delay */\r
+#define MPDDRC_TPR0_TWTR(value) ((MPDDRC_TPR0_TWTR_Msk & ((value) << MPDDRC_TPR0_TWTR_Pos)))\r
+#define MPDDRC_TPR0_TMRD_Pos 28\r
+#define MPDDRC_TPR0_TMRD_Msk (0xfu << MPDDRC_TPR0_TMRD_Pos) /**< \brief (MPDDRC_TPR0) Load Mode Register Command to Activate or Refresh Command */\r
+#define MPDDRC_TPR0_TMRD(value) ((MPDDRC_TPR0_TMRD_Msk & ((value) << MPDDRC_TPR0_TMRD_Pos)))\r
+/* -------- MPDDRC_TPR1 : (MPDDRC Offset: 0x10) MPDDRC Timing Parameter 1 Register -------- */\r
+#define MPDDRC_TPR1_TRFC_Pos 0\r
+#define MPDDRC_TPR1_TRFC_Msk (0x7fu << MPDDRC_TPR1_TRFC_Pos) /**< \brief (MPDDRC_TPR1) Row Cycle Delay */\r
+#define MPDDRC_TPR1_TRFC(value) ((MPDDRC_TPR1_TRFC_Msk & ((value) << MPDDRC_TPR1_TRFC_Pos)))\r
+#define MPDDRC_TPR1_TXSNR_Pos 8\r
+#define MPDDRC_TPR1_TXSNR_Msk (0xffu << MPDDRC_TPR1_TXSNR_Pos) /**< \brief (MPDDRC_TPR1) Exit Self-refresh Delay to Non-Read Command */\r
+#define MPDDRC_TPR1_TXSNR(value) ((MPDDRC_TPR1_TXSNR_Msk & ((value) << MPDDRC_TPR1_TXSNR_Pos)))\r
+#define MPDDRC_TPR1_TXSRD_Pos 16\r
+#define MPDDRC_TPR1_TXSRD_Msk (0xffu << MPDDRC_TPR1_TXSRD_Pos) /**< \brief (MPDDRC_TPR1) Exit Self-refresh Delay to Read Command */\r
+#define MPDDRC_TPR1_TXSRD(value) ((MPDDRC_TPR1_TXSRD_Msk & ((value) << MPDDRC_TPR1_TXSRD_Pos)))\r
+#define MPDDRC_TPR1_TXP_Pos 24\r
+#define MPDDRC_TPR1_TXP_Msk (0xfu << MPDDRC_TPR1_TXP_Pos) /**< \brief (MPDDRC_TPR1) Exit Power-down Delay to First Command */\r
+#define MPDDRC_TPR1_TXP(value) ((MPDDRC_TPR1_TXP_Msk & ((value) << MPDDRC_TPR1_TXP_Pos)))\r
+/* -------- MPDDRC_TPR2 : (MPDDRC Offset: 0x14) MPDDRC Timing Parameter 2 Register -------- */\r
+#define MPDDRC_TPR2_TXARD_Pos 0\r
+#define MPDDRC_TPR2_TXARD_Msk (0xfu << MPDDRC_TPR2_TXARD_Pos) /**< \brief (MPDDRC_TPR2) Exit Active Power Down Delay to Read Command in Mode "Fast Exit" */\r
+#define MPDDRC_TPR2_TXARD(value) ((MPDDRC_TPR2_TXARD_Msk & ((value) << MPDDRC_TPR2_TXARD_Pos)))\r
+#define MPDDRC_TPR2_TXARDS_Pos 4\r
+#define MPDDRC_TPR2_TXARDS_Msk (0xfu << MPDDRC_TPR2_TXARDS_Pos) /**< \brief (MPDDRC_TPR2) Exit Active Power Down Delay to Read Command in Mode "Slow Exit" */\r
+#define MPDDRC_TPR2_TXARDS(value) ((MPDDRC_TPR2_TXARDS_Msk & ((value) << MPDDRC_TPR2_TXARDS_Pos)))\r
+#define MPDDRC_TPR2_TRPA_Pos 8\r
+#define MPDDRC_TPR2_TRPA_Msk (0xfu << MPDDRC_TPR2_TRPA_Pos) /**< \brief (MPDDRC_TPR2) Row Precharge All Delay */\r
+#define MPDDRC_TPR2_TRPA(value) ((MPDDRC_TPR2_TRPA_Msk & ((value) << MPDDRC_TPR2_TRPA_Pos)))\r
+#define MPDDRC_TPR2_TRTP_Pos 12\r
+#define MPDDRC_TPR2_TRTP_Msk (0x7u << MPDDRC_TPR2_TRTP_Pos) /**< \brief (MPDDRC_TPR2) Read to Precharge */\r
+#define MPDDRC_TPR2_TRTP(value) ((MPDDRC_TPR2_TRTP_Msk & ((value) << MPDDRC_TPR2_TRTP_Pos)))\r
+#define MPDDRC_TPR2_TFAW_Pos 16\r
+#define MPDDRC_TPR2_TFAW_Msk (0xfu << MPDDRC_TPR2_TFAW_Pos) /**< \brief (MPDDRC_TPR2) Four Active Windows */\r
+#define MPDDRC_TPR2_TFAW(value) ((MPDDRC_TPR2_TFAW_Msk & ((value) << MPDDRC_TPR2_TFAW_Pos)))\r
+/* -------- MPDDRC_LPR : (MPDDRC Offset: 0x1C) MPDDRC Low-power Register -------- */\r
+#define MPDDRC_LPR_LPCB_Pos 0\r
+#define MPDDRC_LPR_LPCB_Msk (0x3u << MPDDRC_LPR_LPCB_Pos) /**< \brief (MPDDRC_LPR) Low-power Command Bit */\r
+#define MPDDRC_LPR_LPCB(value) ((MPDDRC_LPR_LPCB_Msk & ((value) << MPDDRC_LPR_LPCB_Pos)))\r
+#define MPDDRC_LPR_LPCB_NOLOWPOWER (0x0u << 0) /**< \brief (MPDDRC_LPR) Low-power feature is inhibited. No Power-down, Self-refresh and Deep-power modes are issued to the DDR-SDRAM device. */\r
+#define MPDDRC_LPR_LPCB_SELFREFRESH (0x1u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a self-refresh command to the DDR-SDRAM device, the clock(s) is/are deactivated and the CKE signal is set low. The DDR-SDRAM device leaves the Self-refresh mode when accessed and reenters it after the access. */\r
+#define MPDDRC_LPR_LPCB_POWERDOWN (0x2u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a Power-down command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the Power-down mode when accessed and reenters it after the access. */\r
+#define MPDDRC_LPR_LPCB_DEEPPOWERDOWN (0x3u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a Deep Power-down command to the low-power DDR-SDRAM device. */\r
+#define MPDDRC_LPR_CLK_FR (0x1u << 2) /**< \brief (MPDDRC_LPR) Clock Frozen Command Bit */\r
+#define MPDDRC_LPR_CLK_FR_DISABLED (0x0u << 2) /**< \brief (MPDDRC_LPR) Clock(s) is/are not frozen. */\r
+#define MPDDRC_LPR_CLK_FR_ENABLED (0x1u << 2) /**< \brief (MPDDRC_LPR) Clock(s) is/are frozen. */\r
+#define MPDDRC_LPR_LPDDR2_LPDDR3_PWOFF (0x1u << 3) /**< \brief (MPDDRC_LPR) LPDDR2 - LPDDR3 Power Off Bit */\r
+#define MPDDRC_LPR_LPDDR2_LPDDR3_PWOFF_DISABLED (0x0u << 3) /**< \brief (MPDDRC_LPR) No power-off sequence applied to LPDDR2/LPDDR3. */\r
+#define MPDDRC_LPR_LPDDR2_LPDDR3_PWOFF_ENABLED (0x1u << 3) /**< \brief (MPDDRC_LPR) A power-off sequence is applied to the LPDDR2/LPDDR3 device. CKE is forced low. */\r
+#define MPDDRC_LPR_PASR_Pos 4\r
+#define MPDDRC_LPR_PASR_Msk (0x7u << MPDDRC_LPR_PASR_Pos) /**< \brief (MPDDRC_LPR) Partial Array Self-refresh */\r
+#define MPDDRC_LPR_PASR(value) ((MPDDRC_LPR_PASR_Msk & ((value) << MPDDRC_LPR_PASR_Pos)))\r
+#define MPDDRC_LPR_DS_Pos 8\r
+#define MPDDRC_LPR_DS_Msk (0x7u << MPDDRC_LPR_DS_Pos) /**< \brief (MPDDRC_LPR) Drive Strength */\r
+#define MPDDRC_LPR_DS(value) ((MPDDRC_LPR_DS_Msk & ((value) << MPDDRC_LPR_DS_Pos)))\r
+#define MPDDRC_LPR_TIMEOUT_Pos 12\r
+#define MPDDRC_LPR_TIMEOUT_Msk (0x3u << MPDDRC_LPR_TIMEOUT_Pos) /**< \brief (MPDDRC_LPR) Time Between Last Transfer and Low-Power Mode */\r
+#define MPDDRC_LPR_TIMEOUT(value) ((MPDDRC_LPR_TIMEOUT_Msk & ((value) << MPDDRC_LPR_TIMEOUT_Pos)))\r
+#define MPDDRC_LPR_TIMEOUT_NONE (0x0u << 12) /**< \brief (MPDDRC_LPR) SDRAM Low-power mode is activated immediately after the end of the last transfer. */\r
+#define MPDDRC_LPR_TIMEOUT_DELAY_64_CLK (0x1u << 12) /**< \brief (MPDDRC_LPR) SDRAM Low-power mode is activated 64 clock cycles after the end of the last transfer. */\r
+#define MPDDRC_LPR_TIMEOUT_DELAY_128_CLK (0x2u << 12) /**< \brief (MPDDRC_LPR) SDRAM Low-power mode is activated 128 clock cycles after the end of the last transfer. */\r
+#define MPDDRC_LPR_APDE (0x1u << 16) /**< \brief (MPDDRC_LPR) Active Power Down Exit Time */\r
+#define MPDDRC_LPR_APDE_DDR2_FAST_EXIT (0x0u << 16) /**< \brief (MPDDRC_LPR) Fast Exit from Power Down. DDR2-SDRAM and DDR3-SDRAM devices only. */\r
+#define MPDDRC_LPR_APDE_DDR2_SLOW_EXIT (0x1u << 16) /**< \brief (MPDDRC_LPR) Slow Exit from Power Down. DDR2-SDRAM and DDR3-SDRAM devices only. */\r
+#define MPDDRC_LPR_UPD_MR_Pos 20\r
+#define MPDDRC_LPR_UPD_MR_Msk (0x3u << MPDDRC_LPR_UPD_MR_Pos) /**< \brief (MPDDRC_LPR) Update Load Mode Register and Extended Mode Register */\r
+#define MPDDRC_LPR_UPD_MR(value) ((MPDDRC_LPR_UPD_MR_Msk & ((value) << MPDDRC_LPR_UPD_MR_Pos)))\r
+#define MPDDRC_LPR_UPD_MR_NO_UPDATE (0x0u << 20) /**< \brief (MPDDRC_LPR) Update of Load Mode and Extended Mode registers is disabled. */\r
+#define MPDDRC_LPR_UPD_MR_UPDATE_SHAREDBUS (0x1u << 20) /**< \brief (MPDDRC_LPR) MPDDRC shares an external bus. Automatic update is done during a refresh command and a pending read or write access in the SDRAM device. */\r
+#define MPDDRC_LPR_UPD_MR_UPDATE_NOSHAREDBUS (0x2u << 20) /**< \brief (MPDDRC_LPR) MPDDRC does not share an external bus. Automatic update is done before entering Self-refresh mode. */\r
+#define MPDDRC_LPR_CHG_FRQ (0x1u << 24) /**< \brief (MPDDRC_LPR) Change Clock Frequency During Self-refresh Mode */\r
+#define MPDDRC_LPR_SELF_DONE (0x1u << 25) /**< \brief (MPDDRC_LPR) Self-refresh is done */\r
+/* -------- MPDDRC_MD : (MPDDRC Offset: 0x20) MPDDRC Memory Device Register -------- */\r
+#define MPDDRC_MD_MD_Pos 0\r
+#define MPDDRC_MD_MD_Msk (0x7u << MPDDRC_MD_MD_Pos) /**< \brief (MPDDRC_MD) Memory Device */\r
+#define MPDDRC_MD_MD(value) ((MPDDRC_MD_MD_Msk & ((value) << MPDDRC_MD_MD_Pos)))\r
+#define MPDDRC_MD_MD_LPDDR_SDRAM (0x3u << 0) /**< \brief (MPDDRC_MD) Low-power DDR1-SDRAM */\r
+#define MPDDRC_MD_MD_DDR3_SDRAM (0x4u << 0) /**< \brief (MPDDRC_MD) DDR3-SDRAM */\r
+#define MPDDRC_MD_MD_LPDDR3_SDRAM (0x5u << 0) /**< \brief (MPDDRC_MD) Low-power DDR3-SDRAM */\r
+#define MPDDRC_MD_MD_DDR2_SDRAM (0x6u << 0) /**< \brief (MPDDRC_MD) DDR2-SDRAM */\r
+#define MPDDRC_MD_MD_LPDDR2_SDRAM (0x7u << 0) /**< \brief (MPDDRC_MD) Low-power DDR2-SDRAM */\r
+#define MPDDRC_MD_DBW (0x1u << 4) /**< \brief (MPDDRC_MD) Data Bus Width */\r
+#define MPDDRC_MD_DBW_DBW_32_BITS (0x0u << 4) /**< \brief (MPDDRC_MD) Data bus width is 32 bits */\r
+#define MPDDRC_MD_DBW_DBW_16_BITS (0x1u << 4) /**< \brief (MPDDRC_MD) Data bus width is 16 bits. */\r
+#define MPDDRC_MD_WL (0x1u << 5) /**< \brief (MPDDRC_MD) Write Latency */\r
+#define MPDDRC_MD_WL_WL_SETA (0x0u << 5) /**< \brief (MPDDRC_MD) Write Latency Set A */\r
+#define MPDDRC_MD_WL_WL_SETB (0x1u << 5) /**< \brief (MPDDRC_MD) Write Latency Set B */\r
+#define MPDDRC_MD_RL3 (0x1u << 6) /**< \brief (MPDDRC_MD) Read Latency 3 Option Support */\r
+#define MPDDRC_MD_RL3_RL3_SUPPORT (0x0u << 6) /**< \brief (MPDDRC_MD) Read latency of 3 is supported */\r
+#define MPDDRC_MD_RL3_RL3_NOT_SUPPORTED (0x1u << 6) /**< \brief (MPDDRC_MD) Read latency 0f 3 is not supported */\r
+#define MPDDRC_MD_MANU_ID_Pos 8\r
+#define MPDDRC_MD_MANU_ID_Msk (0xffu << MPDDRC_MD_MANU_ID_Pos) /**< \brief (MPDDRC_MD) Manufacturer Identification */\r
+#define MPDDRC_MD_MANU_ID(value) ((MPDDRC_MD_MANU_ID_Msk & ((value) << MPDDRC_MD_MANU_ID_Pos)))\r
+#define MPDDRC_MD_REV_ID_Pos 16\r
+#define MPDDRC_MD_REV_ID_Msk (0xffu << MPDDRC_MD_REV_ID_Pos) /**< \brief (MPDDRC_MD) Revision Identification */\r
+#define MPDDRC_MD_REV_ID(value) ((MPDDRC_MD_REV_ID_Msk & ((value) << MPDDRC_MD_REV_ID_Pos)))\r
+#define MPDDRC_MD_TYPE_Pos 24\r
+#define MPDDRC_MD_TYPE_Msk (0x3u << MPDDRC_MD_TYPE_Pos) /**< \brief (MPDDRC_MD) DRAM Architecture */\r
+#define MPDDRC_MD_TYPE(value) ((MPDDRC_MD_TYPE_Msk & ((value) << MPDDRC_MD_TYPE_Pos)))\r
+#define MPDDRC_MD_TYPE_S4_SDRAM (0x0u << 24) /**< \brief (MPDDRC_MD) 4n prefetch architecture */\r
+#define MPDDRC_MD_TYPE_S2_SDRAM (0x1u << 24) /**< \brief (MPDDRC_MD) 2n prefetch architecture */\r
+#define MPDDRC_MD_TYPE_NVM (0x2u << 24) /**< \brief (MPDDRC_MD) Non-volatile device */\r
+#define MPDDRC_MD_TYPE_S8_SDRAM (0x3u << 24) /**< \brief (MPDDRC_MD) 8n prefetch architecture */\r
+#define MPDDRC_MD_DENSITY_Pos 26\r
+#define MPDDRC_MD_DENSITY_Msk (0xfu << MPDDRC_MD_DENSITY_Pos) /**< \brief (MPDDRC_MD) Density of Memory */\r
+#define MPDDRC_MD_DENSITY(value) ((MPDDRC_MD_DENSITY_Msk & ((value) << MPDDRC_MD_DENSITY_Pos)))\r
+#define MPDDRC_MD_DENSITY_DENSITY_64MBITS (0x0u << 26) /**< \brief (MPDDRC_MD) The device density is 64 Mbits. */\r
+#define MPDDRC_MD_DENSITY_DENSITY_128MBITS (0x1u << 26) /**< \brief (MPDDRC_MD) The device density is 128 Mbits. */\r
+#define MPDDRC_MD_DENSITY_DENSITY_256MBITS (0x2u << 26) /**< \brief (MPDDRC_MD) The device density is 256 Mbits. */\r
+#define MPDDRC_MD_DENSITY_DENSITY_512MBITS (0x3u << 26) /**< \brief (MPDDRC_MD) The device density is 512 Mbits. */\r
+#define MPDDRC_MD_DENSITY_DENSITY_1GBITS (0x4u << 26) /**< \brief (MPDDRC_MD) The device density is 1 Gbit. */\r
+#define MPDDRC_MD_DENSITY_DENSITY_2GBITS (0x5u << 26) /**< \brief (MPDDRC_MD) The device density is 2 Gbits. */\r
+#define MPDDRC_MD_DENSITY_DENSITY_4GBITS (0x6u << 26) /**< \brief (MPDDRC_MD) The device density is 4 Gbits. */\r
+#define MPDDRC_MD_DENSITY_DENSITY_8GBITS (0x7u << 26) /**< \brief (MPDDRC_MD) The device density is 8 Gbits. */\r
+#define MPDDRC_MD_DENSITY_DENSITY_16GBITS (0x8u << 26) /**< \brief (MPDDRC_MD) The device density is 16 Gbits. */\r
+#define MPDDRC_MD_DENSITY_DENSITY_32GBITS (0x9u << 26) /**< \brief (MPDDRC_MD) The device density is 32 Gbits. */\r
+#define MPDDRC_MD_IO_WIDTH_Pos 30\r
+#define MPDDRC_MD_IO_WIDTH_Msk (0x3u << MPDDRC_MD_IO_WIDTH_Pos) /**< \brief (MPDDRC_MD) Width of Memory */\r
+#define MPDDRC_MD_IO_WIDTH(value) ((MPDDRC_MD_IO_WIDTH_Msk & ((value) << MPDDRC_MD_IO_WIDTH_Pos)))\r
+#define MPDDRC_MD_IO_WIDTH_WIDTH_32 (0x0u << 30) /**< \brief (MPDDRC_MD) The data bus width is 32 bits. */\r
+#define MPDDRC_MD_IO_WIDTH_WIDTH_16 (0x1u << 30) /**< \brief (MPDDRC_MD) The data bus width is 16 bits. */\r
+#define MPDDRC_MD_IO_WIDTH_WIDTH_8 (0x2u << 30) /**< \brief (MPDDRC_MD) The data bus width is 8 bits. */\r
+#define MPDDRC_MD_IO_WIDTH_NOT_USED (0x3u << 30) /**< \brief (MPDDRC_MD) - */\r
+/* -------- MPDDRC_LPDDR23_LPR : (MPDDRC Offset: 0x28) MPDDRC LPDDR2-LPDDR3 Low-power Register -------- */\r
+#define MPDDRC_LPDDR23_LPR_BK_MASK_PASR_Pos 0\r
+#define MPDDRC_LPDDR23_LPR_BK_MASK_PASR_Msk (0xffu << MPDDRC_LPDDR23_LPR_BK_MASK_PASR_Pos) /**< \brief (MPDDRC_LPDDR23_LPR) Bank Mask Bit/PASR */\r
+#define MPDDRC_LPDDR23_LPR_BK_MASK_PASR(value) ((MPDDRC_LPDDR23_LPR_BK_MASK_PASR_Msk & ((value) << MPDDRC_LPDDR23_LPR_BK_MASK_PASR_Pos)))\r
+#define MPDDRC_LPDDR23_LPR_SEG_MASK_Pos 8\r
+#define MPDDRC_LPDDR23_LPR_SEG_MASK_Msk (0xffffu << MPDDRC_LPDDR23_LPR_SEG_MASK_Pos) /**< \brief (MPDDRC_LPDDR23_LPR) Segment Mask Bit */\r
+#define MPDDRC_LPDDR23_LPR_SEG_MASK(value) ((MPDDRC_LPDDR23_LPR_SEG_MASK_Msk & ((value) << MPDDRC_LPDDR23_LPR_SEG_MASK_Pos)))\r
+#define MPDDRC_LPDDR23_LPR_DS_Pos 24\r
+#define MPDDRC_LPDDR23_LPR_DS_Msk (0xfu << MPDDRC_LPDDR23_LPR_DS_Pos) /**< \brief (MPDDRC_LPDDR23_LPR) Drive Strength */\r
+#define MPDDRC_LPDDR23_LPR_DS(value) ((MPDDRC_LPDDR23_LPR_DS_Msk & ((value) << MPDDRC_LPDDR23_LPR_DS_Pos)))\r
+/* -------- MPDDRC_LPDDR23_CAL_MR4 : (MPDDRC Offset: 0x2C) MPDDRC LPDDR2-LPDDR3 Calibration and MR4 Register -------- */\r
+#define MPDDRC_LPDDR23_CAL_MR4_COUNT_CAL_Pos 0\r
+#define MPDDRC_LPDDR23_CAL_MR4_COUNT_CAL_Msk (0xffffu << MPDDRC_LPDDR23_CAL_MR4_COUNT_CAL_Pos) /**< \brief (MPDDRC_LPDDR23_CAL_MR4) LPDDR2 and LPDDR3 Calibration Timer Count */\r
+#define MPDDRC_LPDDR23_CAL_MR4_COUNT_CAL(value) ((MPDDRC_LPDDR23_CAL_MR4_COUNT_CAL_Msk & ((value) << MPDDRC_LPDDR23_CAL_MR4_COUNT_CAL_Pos)))\r
+#define MPDDRC_LPDDR23_CAL_MR4_MR4_READ_Pos 16\r
+#define MPDDRC_LPDDR23_CAL_MR4_MR4_READ_Msk (0xffffu << MPDDRC_LPDDR23_CAL_MR4_MR4_READ_Pos) /**< \brief (MPDDRC_LPDDR23_CAL_MR4) Mode Register 4 Read Interval */\r
+#define MPDDRC_LPDDR23_CAL_MR4_MR4_READ(value) ((MPDDRC_LPDDR23_CAL_MR4_MR4_READ_Msk & ((value) << MPDDRC_LPDDR23_CAL_MR4_MR4_READ_Pos)))\r
+/* -------- MPDDRC_LPDDR23_TIM_CAL : (MPDDRC Offset: 0x30) MPDDRC LPDDR2-LPDDR3 Timing Calibration Register -------- */\r
+#define MPDDRC_LPDDR23_TIM_CAL_ZQCS_Pos 0\r
+#define MPDDRC_LPDDR23_TIM_CAL_ZQCS_Msk (0xffu << MPDDRC_LPDDR23_TIM_CAL_ZQCS_Pos) /**< \brief (MPDDRC_LPDDR23_TIM_CAL) ZQ Calibration Short */\r
+#define MPDDRC_LPDDR23_TIM_CAL_ZQCS(value) ((MPDDRC_LPDDR23_TIM_CAL_ZQCS_Msk & ((value) << MPDDRC_LPDDR23_TIM_CAL_ZQCS_Pos)))\r
+#define MPDDRC_LPDDR23_TIM_CAL_RZQI_Pos 16\r
+#define MPDDRC_LPDDR23_TIM_CAL_RZQI_Msk (0x3u << MPDDRC_LPDDR23_TIM_CAL_RZQI_Pos) /**< \brief (MPDDRC_LPDDR23_TIM_CAL) Built-in Self-Test for RZQ Information */\r
+#define MPDDRC_LPDDR23_TIM_CAL_RZQI(value) ((MPDDRC_LPDDR23_TIM_CAL_RZQI_Msk & ((value) << MPDDRC_LPDDR23_TIM_CAL_RZQI_Pos)))\r
+#define MPDDRC_LPDDR23_TIM_CAL_RZQI_RZQ_NOT_SUPPORTED (0x0u << 16) /**< \brief (MPDDRC_LPDDR23_TIM_CAL) RZQ self test not supported */\r
+#define MPDDRC_LPDDR23_TIM_CAL_RZQI_ZQ_VDDCA_FLOAT (0x1u << 16) /**< \brief (MPDDRC_LPDDR23_TIM_CAL) The ZQ pin can be connected to VDDCA or left floating. */\r
+#define MPDDRC_LPDDR23_TIM_CAL_RZQI_ZQ_SHORTED_GROUND (0x2u << 16) /**< \brief (MPDDRC_LPDDR23_TIM_CAL) The ZQ pin can be shorted to ground. */\r
+#define MPDDRC_LPDDR23_TIM_CAL_RZQI_ZQ_SELF_TEST_OK (0x3u << 16) /**< \brief (MPDDRC_LPDDR23_TIM_CAL) ZQ pin self test complete; no error condition detected */\r
+/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) MPDDRC IO Calibration -------- */\r
+#define MPDDRC_IO_CALIBR_RDIV_Pos 0\r
+#define MPDDRC_IO_CALIBR_RDIV_Msk (0x7u << MPDDRC_IO_CALIBR_RDIV_Pos) /**< \brief (MPDDRC_IO_CALIBR) Resistor Divider, Output Driver Impedance */\r
+#define MPDDRC_IO_CALIBR_RDIV(value) ((MPDDRC_IO_CALIBR_RDIV_Msk & ((value) << MPDDRC_IO_CALIBR_RDIV_Pos)))\r
+#define MPDDRC_IO_CALIBR_RDIV_RZQ_34 (0x1u << 0) /**< \brief (MPDDRC_IO_CALIBR) LP-DDR2 serial impedance line = 34.3 ohms,DDR2/LP-DDR1 serial impedance line: Not applicable */\r
+#define MPDDRC_IO_CALIBR_RDIV_RZQ_40_RZQ_38_RZQ_37_RZQ_35 (0x2u << 0) /**< \brief (MPDDRC_IO_CALIBR) LP-DDR2 serial impedance line = 40 ohms,LP-DDR3 serial impedance line = 38 ohms,DDR3 serial impedance line = 37 ohms,DDR2/LP-DDR1 serial impedance line = 35 ohms */\r
+#define MPDDRC_IO_CALIBR_RDIV_RZQ_48_RZQ_46_RZQ_44_RZQ_43 (0x3u << 0) /**< \brief (MPDDRC_IO_CALIBR) LP-DDR2 serial impedance line = 48 ohms,LP-DDR3 serial impedance line = 46 ohms,DDR3 serial impedance line = 44 ohms,DDR2/LP-DDR1 serial impedance line = 43 ohms */\r
+#define MPDDRC_IO_CALIBR_RDIV_RZQ_60 (0x4u << 0) /**< \brief (MPDDRC_IO_CALIBR) LP-DDR2 serial impedance line = 60 ohms,LP-DDR3 serial impedance line = 57 ohms,DDR3 serial impedance line = 55 ohms,DDR2/LP-DDR1 serial impedance line = 52 ohms */\r
+#define MPDDRC_IO_CALIBR_RDIV_RZQ_80_RZQ_77_RZQ_73_RZQ_70 (0x6u << 0) /**< \brief (MPDDRC_IO_CALIBR) LP-DDR2 serial impedance line = 80 ohms,LP-DDR3 serial impedance line = 77 ohms,DDR3 serial impedance line = 73 ohms,DDR2/LP-DDR1 serial impedance line = 70 ohms */\r
+#define MPDDRC_IO_CALIBR_RDIV_RZQ_120_RZQ_115_RZQ_110_RZQ_105 (0x7u << 0) /**< \brief (MPDDRC_IO_CALIBR) LP-DDR2 serial impedance line = 120 ohms,LP-DDR3 serial impedance line = 115 ohms,DDR3 serial impedance line = 110 ohms,DDR2/LP-DDR1 serial impedance line = 105 ohms */\r
+#define MPDDRC_IO_CALIBR_EN_CALIB (0x1u << 4) /**< \brief (MPDDRC_IO_CALIBR) Enable Calibration */\r
+#define MPDDRC_IO_CALIBR_EN_CALIB_DISABLE_CALIBRATION (0x0u << 4) /**< \brief (MPDDRC_IO_CALIBR) Calibration is disabled. */\r
+#define MPDDRC_IO_CALIBR_EN_CALIB_ENABLE_CALIBRATION (0x1u << 4) /**< \brief (MPDDRC_IO_CALIBR) Calibration is enabled. */\r
+#define MPDDRC_IO_CALIBR_TZQIO_Pos 8\r
+#define MPDDRC_IO_CALIBR_TZQIO_Msk (0x7fu << MPDDRC_IO_CALIBR_TZQIO_Pos) /**< \brief (MPDDRC_IO_CALIBR) IO Calibration */\r
+#define MPDDRC_IO_CALIBR_TZQIO(value) ((MPDDRC_IO_CALIBR_TZQIO_Msk & ((value) << MPDDRC_IO_CALIBR_TZQIO_Pos)))\r
+#define MPDDRC_IO_CALIBR_CALCODEP_Pos 16\r
+#define MPDDRC_IO_CALIBR_CALCODEP_Msk (0xfu << MPDDRC_IO_CALIBR_CALCODEP_Pos) /**< \brief (MPDDRC_IO_CALIBR) Number of Transistor P */\r
+#define MPDDRC_IO_CALIBR_CALCODEP(value) ((MPDDRC_IO_CALIBR_CALCODEP_Msk & ((value) << MPDDRC_IO_CALIBR_CALCODEP_Pos)))\r
+#define MPDDRC_IO_CALIBR_CALCODEN_Pos 20\r
+#define MPDDRC_IO_CALIBR_CALCODEN_Msk (0xfu << MPDDRC_IO_CALIBR_CALCODEN_Pos) /**< \brief (MPDDRC_IO_CALIBR) Number of Transistor N */\r
+#define MPDDRC_IO_CALIBR_CALCODEN(value) ((MPDDRC_IO_CALIBR_CALCODEN_Msk & ((value) << MPDDRC_IO_CALIBR_CALCODEN_Pos)))\r
+/* -------- MPDDRC_OCMS : (MPDDRC Offset: 0x38) MPDDRC OCMS Register -------- */\r
+#define MPDDRC_OCMS_SCR_EN (0x1u << 0) /**< \brief (MPDDRC_OCMS) Scrambling Enable */\r
+/* -------- MPDDRC_OCMS_KEY1 : (MPDDRC Offset: 0x3C) MPDDRC OCMS KEY1 Register -------- */\r
+#define MPDDRC_OCMS_KEY1_KEY1_Pos 0\r
+#define MPDDRC_OCMS_KEY1_KEY1_Msk (0xffffffffu << MPDDRC_OCMS_KEY1_KEY1_Pos) /**< \brief (MPDDRC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */\r
+#define MPDDRC_OCMS_KEY1_KEY1(value) ((MPDDRC_OCMS_KEY1_KEY1_Msk & ((value) << MPDDRC_OCMS_KEY1_KEY1_Pos)))\r
+/* -------- MPDDRC_OCMS_KEY2 : (MPDDRC Offset: 0x40) MPDDRC OCMS KEY2 Register -------- */\r
+#define MPDDRC_OCMS_KEY2_KEY2_Pos 0\r
+#define MPDDRC_OCMS_KEY2_KEY2_Msk (0xffffffffu << MPDDRC_OCMS_KEY2_KEY2_Pos) /**< \brief (MPDDRC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */\r
+#define MPDDRC_OCMS_KEY2_KEY2(value) ((MPDDRC_OCMS_KEY2_KEY2_Msk & ((value) << MPDDRC_OCMS_KEY2_KEY2_Pos)))\r
+/* -------- MPDDRC_CONF_ARBITER : (MPDDRC Offset: 0x44) MPDDRC Configuration Arbiter Register -------- */\r
+#define MPDDRC_CONF_ARBITER_ARB_Pos 0\r
+#define MPDDRC_CONF_ARBITER_ARB_Msk (0x3u << MPDDRC_CONF_ARBITER_ARB_Pos) /**< \brief (MPDDRC_CONF_ARBITER) Type of Arbitration */\r
+#define MPDDRC_CONF_ARBITER_ARB(value) ((MPDDRC_CONF_ARBITER_ARB_Msk & ((value) << MPDDRC_CONF_ARBITER_ARB_Pos)))\r
+#define MPDDRC_CONF_ARBITER_ARB_ROUND (0x0u << 0) /**< \brief (MPDDRC_CONF_ARBITER) Round Robin */\r
+#define MPDDRC_CONF_ARBITER_ARB_NB_REQUEST (0x1u << 0) /**< \brief (MPDDRC_CONF_ARBITER) Request Policy */\r
+#define MPDDRC_CONF_ARBITER_ARB_BANDWIDTH (0x2u << 0) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth Policy */\r
+#define MPDDRC_CONF_ARBITER_BDW_MAX_CUR (0x1u << 3) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth Max or Current */\r
+#define MPDDRC_CONF_ARBITER_RQ_WD_P0 (0x1u << 8) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */\r
+#define MPDDRC_CONF_ARBITER_RQ_WD_P1 (0x1u << 9) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */\r
+#define MPDDRC_CONF_ARBITER_RQ_WD_P2 (0x1u << 10) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */\r
+#define MPDDRC_CONF_ARBITER_RQ_WD_P3 (0x1u << 11) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */\r
+#define MPDDRC_CONF_ARBITER_RQ_WD_P4 (0x1u << 12) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */\r
+#define MPDDRC_CONF_ARBITER_RQ_WD_P5 (0x1u << 13) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */\r
+#define MPDDRC_CONF_ARBITER_RQ_WD_P6 (0x1u << 14) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */\r
+#define MPDDRC_CONF_ARBITER_RQ_WD_P7 (0x1u << 15) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */\r
+#define MPDDRC_CONF_ARBITER_MA_PR_P0 (0x1u << 16) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */\r
+#define MPDDRC_CONF_ARBITER_MA_PR_P1 (0x1u << 17) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */\r
+#define MPDDRC_CONF_ARBITER_MA_PR_P2 (0x1u << 18) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */\r
+#define MPDDRC_CONF_ARBITER_MA_PR_P3 (0x1u << 19) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */\r
+#define MPDDRC_CONF_ARBITER_MA_PR_P4 (0x1u << 20) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */\r
+#define MPDDRC_CONF_ARBITER_MA_PR_P5 (0x1u << 21) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */\r
+#define MPDDRC_CONF_ARBITER_MA_PR_P6 (0x1u << 22) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */\r
+#define MPDDRC_CONF_ARBITER_MA_PR_P7 (0x1u << 23) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */\r
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P0 (0x1u << 24) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */\r
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P1 (0x1u << 25) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */\r
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P2 (0x1u << 26) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */\r
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P3 (0x1u << 27) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */\r
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P4 (0x1u << 28) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */\r
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P5 (0x1u << 29) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */\r
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P6 (0x1u << 30) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */\r
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P7 (0x1u << 31) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */\r
+/* -------- MPDDRC_TIMEOUT : (MPDDRC Offset: 0x48) MPDDRC Time-out Port 0/1/2/3 Register -------- */\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P0_Pos 0\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P0_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P0_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P0(value) ((MPDDRC_TIMEOUT_TIMEOUT_P0_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P0_Pos)))\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P1_Pos 4\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P1_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P1_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P1(value) ((MPDDRC_TIMEOUT_TIMEOUT_P1_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P1_Pos)))\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P2_Pos 8\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P2_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P2_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P2(value) ((MPDDRC_TIMEOUT_TIMEOUT_P2_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P2_Pos)))\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P3_Pos 12\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P3_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P3_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P3(value) ((MPDDRC_TIMEOUT_TIMEOUT_P3_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P3_Pos)))\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P4_Pos 16\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P4_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P4_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P4(value) ((MPDDRC_TIMEOUT_TIMEOUT_P4_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P4_Pos)))\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P5_Pos 20\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P5_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P5_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P5(value) ((MPDDRC_TIMEOUT_TIMEOUT_P5_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P5_Pos)))\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P6_Pos 24\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P6_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P6_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P6(value) ((MPDDRC_TIMEOUT_TIMEOUT_P6_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P6_Pos)))\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P7_Pos 28\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P7_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P7_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */\r
+#define MPDDRC_TIMEOUT_TIMEOUT_P7(value) ((MPDDRC_TIMEOUT_TIMEOUT_P7_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P7_Pos)))\r
+/* -------- MPDDRC_REQ_PORT_0123 : (MPDDRC Offset: 0x4C) MPDDRC Request Port 0/1/2/3 Register -------- */\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_Pos 0\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_Msk (0xffu << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_Pos) /**< \brief (MPDDRC_REQ_PORT_0123) Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 */\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0(value) ((MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_Msk & ((value) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_Pos)))\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_Pos 8\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_Msk (0xffu << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_Pos) /**< \brief (MPDDRC_REQ_PORT_0123) Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 */\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1(value) ((MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_Msk & ((value) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_Pos)))\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_Pos 16\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_Msk (0xffu << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_Pos) /**< \brief (MPDDRC_REQ_PORT_0123) Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 */\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2(value) ((MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_Msk & ((value) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_Pos)))\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_Pos 24\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_Msk (0xffu << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_Pos) /**< \brief (MPDDRC_REQ_PORT_0123) Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 */\r
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3(value) ((MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_Msk & ((value) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_Pos)))\r
+/* -------- MPDDRC_REQ_PORT_4567 : (MPDDRC Offset: 0x50) MPDDRC Request Port 4/5/6/7 Register -------- */\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_Pos 0\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_Msk (0xffu << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_Pos) /**< \brief (MPDDRC_REQ_PORT_4567) Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 */\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4(value) ((MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_Msk & ((value) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_Pos)))\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_Pos 8\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_Msk (0xffu << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_Pos) /**< \brief (MPDDRC_REQ_PORT_4567) Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 */\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5(value) ((MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_Msk & ((value) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_Pos)))\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_Pos 16\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_Msk (0xffu << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_Pos) /**< \brief (MPDDRC_REQ_PORT_4567) Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 */\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6(value) ((MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_Msk & ((value) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_Pos)))\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_Pos 24\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_Msk (0xffu << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_Pos) /**< \brief (MPDDRC_REQ_PORT_4567) Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 */\r
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7(value) ((MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_Msk & ((value) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_Pos)))\r
+/* -------- MPDDRC_BDW_PORT_0123 : (MPDDRC Offset: 0x54) MPDDRC Bandwidth Port 0/1/2/3 Register -------- */\r
+#define MPDDRC_BDW_PORT_0123_BDW_P0_Pos 0\r
+#define MPDDRC_BDW_PORT_0123_BDW_P0_Msk (0x7fu << MPDDRC_BDW_PORT_0123_BDW_P0_Pos) /**< \brief (MPDDRC_BDW_PORT_0123) Current/Maximum Bandwidth from Port 0-1-2-3 */\r
+#define MPDDRC_BDW_PORT_0123_BDW_P1_Pos 8\r
+#define MPDDRC_BDW_PORT_0123_BDW_P1_Msk (0x7fu << MPDDRC_BDW_PORT_0123_BDW_P1_Pos) /**< \brief (MPDDRC_BDW_PORT_0123) Current/Maximum Bandwidth from Port 0-1-2-3 */\r
+#define MPDDRC_BDW_PORT_0123_BDW_P2_Pos 16\r
+#define MPDDRC_BDW_PORT_0123_BDW_P2_Msk (0x7fu << MPDDRC_BDW_PORT_0123_BDW_P2_Pos) /**< \brief (MPDDRC_BDW_PORT_0123) Current/Maximum Bandwidth from Port 0-1-2-3 */\r
+#define MPDDRC_BDW_PORT_0123_BDW_P3_Pos 24\r
+#define MPDDRC_BDW_PORT_0123_BDW_P3_Msk (0x7fu << MPDDRC_BDW_PORT_0123_BDW_P3_Pos) /**< \brief (MPDDRC_BDW_PORT_0123) Current/Maximum Bandwidth from Port 0-1-2-3 */\r
+/* -------- MPDDRC_BDW_PORT_4567 : (MPDDRC Offset: 0x58) MPDDRC Bandwidth Port 4/5/6/7 Register -------- */\r
+#define MPDDRC_BDW_PORT_4567_BDW_P4_Pos 0\r
+#define MPDDRC_BDW_PORT_4567_BDW_P4_Msk (0x7fu << MPDDRC_BDW_PORT_4567_BDW_P4_Pos) /**< \brief (MPDDRC_BDW_PORT_4567) Current/Maximum Bandwidth from Port 4-5-6-7 */\r
+#define MPDDRC_BDW_PORT_4567_BDW_P5_Pos 8\r
+#define MPDDRC_BDW_PORT_4567_BDW_P5_Msk (0x7fu << MPDDRC_BDW_PORT_4567_BDW_P5_Pos) /**< \brief (MPDDRC_BDW_PORT_4567) Current/Maximum Bandwidth from Port 4-5-6-7 */\r
+#define MPDDRC_BDW_PORT_4567_BDW_P6_Pos 16\r
+#define MPDDRC_BDW_PORT_4567_BDW_P6_Msk (0x7fu << MPDDRC_BDW_PORT_4567_BDW_P6_Pos) /**< \brief (MPDDRC_BDW_PORT_4567) Current/Maximum Bandwidth from Port 4-5-6-7 */\r
+#define MPDDRC_BDW_PORT_4567_BDW_P7_Pos 24\r
+#define MPDDRC_BDW_PORT_4567_BDW_P7_Msk (0x7fu << MPDDRC_BDW_PORT_4567_BDW_P7_Pos) /**< \brief (MPDDRC_BDW_PORT_4567) Current/Maximum Bandwidth from Port 4-5-6-7 */\r
+/* -------- MPDDRC_RD_DATA_PATH : (MPDDRC Offset: 0x5C) MPDDRC Read Datapath Register -------- */\r
+#define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_Pos 0\r
+#define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_Msk (0x3u << MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_Pos) /**< \brief (MPDDRC_RD_DATA_PATH) Shift Sampling Point of Data */\r
+#define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING(value) ((MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_Msk & ((value) << MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_Pos)))\r
+#define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_NO_SHIFT (0x0u << 0) /**< \brief (MPDDRC_RD_DATA_PATH) Initial sampling point. */\r
+#define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT_ONE_CYCLE (0x1u << 0) /**< \brief (MPDDRC_RD_DATA_PATH) Sampling point is shifted by one cycle. */\r
+#define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT_TWO_CYCLES (0x2u << 0) /**< \brief (MPDDRC_RD_DATA_PATH) Sampling point is shifted by two cycles. */\r
+#define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT_THREE_CYCLES (0x3u << 0) /**< \brief (MPDDRC_RD_DATA_PATH) Sampling point is shifted by three cycles, unique for LPDDR2 and DDR3 and LPDDR3.Not applicable for DDR2 and LPDDR1 devices. */\r
+/* -------- MPDDRC_MCFGR : (MPDDRC Offset: 0x60) MPDDRC Monitor Configuration -------- */\r
+#define MPDDRC_MCFGR_EN_MONI (0x1u << 0) /**< \brief (MPDDRC_MCFGR) Enable Monitor */\r
+#define MPDDRC_MCFGR_SOFT_RESET (0x1u << 1) /**< \brief (MPDDRC_MCFGR) Soft Reset */\r
+#define MPDDRC_MCFGR_RUN (0x1u << 4) /**< \brief (MPDDRC_MCFGR) Control Monitor */\r
+#define MPDDRC_MCFGR_READ_WRITE_Pos 8\r
+#define MPDDRC_MCFGR_READ_WRITE_Msk (0x3u << MPDDRC_MCFGR_READ_WRITE_Pos) /**< \brief (MPDDRC_MCFGR) Read/Write Access */\r
+#define MPDDRC_MCFGR_READ_WRITE(value) ((MPDDRC_MCFGR_READ_WRITE_Msk & ((value) << MPDDRC_MCFGR_READ_WRITE_Pos)))\r
+#define MPDDRC_MCFGR_READ_WRITE_TRIG_RD_WR (0x0u << 8) /**< \brief (MPDDRC_MCFGR) Read and Write accesses are triggered. */\r
+#define MPDDRC_MCFGR_READ_WRITE_TRIG_WR (0x1u << 8) /**< \brief (MPDDRC_MCFGR) Only Write accesses are triggered. */\r
+#define MPDDRC_MCFGR_READ_WRITE_TRIG_RD (0x2u << 8) /**< \brief (MPDDRC_MCFGR) Only Read accesses are triggered. */\r
+#define MPDDRC_MCFGR_REFR_CALIB (0x1u << 10) /**< \brief (MPDDRC_MCFGR) Refresh Calibration */\r
+#define MPDDRC_MCFGR_INFO_Pos 11\r
+#define MPDDRC_MCFGR_INFO_Msk (0x3u << MPDDRC_MCFGR_INFO_Pos) /**< \brief (MPDDRC_MCFGR) Information Type */\r
+#define MPDDRC_MCFGR_INFO(value) ((MPDDRC_MCFGR_INFO_Msk & ((value) << MPDDRC_MCFGR_INFO_Pos)))\r
+#define MPDDRC_MCFGR_INFO_MAX_WAIT (0x0u << 11) /**< \brief (MPDDRC_MCFGR) Information concerning the transfer with the longest waiting time */\r
+#define MPDDRC_MCFGR_INFO_NB_TRANSFERS (0x1u << 11) /**< \brief (MPDDRC_MCFGR) Number of transfers on the port */\r
+#define MPDDRC_MCFGR_INFO_TOTAL_LATENCY (0x2u << 11) /**< \brief (MPDDRC_MCFGR) Total latency on the port */\r
+/* -------- MPDDRC_MADDR0 : (MPDDRC Offset: 0x64) MPDDRC Monitor Address High/Low port 0 -------- */\r
+#define MPDDRC_MADDR0_ADDR_LOW_PORT0_Pos 0\r
+#define MPDDRC_MADDR0_ADDR_LOW_PORT0_Msk (0xffffu << MPDDRC_MADDR0_ADDR_LOW_PORT0_Pos) /**< \brief (MPDDRC_MADDR0) Address Low on Port x [x =0..7] */\r
+#define MPDDRC_MADDR0_ADDR_LOW_PORT0(value) ((MPDDRC_MADDR0_ADDR_LOW_PORT0_Msk & ((value) << MPDDRC_MADDR0_ADDR_LOW_PORT0_Pos)))\r
+#define MPDDRC_MADDR0_ADDR_HIGH_PORT0_Pos 16\r
+#define MPDDRC_MADDR0_ADDR_HIGH_PORT0_Msk (0xffffu << MPDDRC_MADDR0_ADDR_HIGH_PORT0_Pos) /**< \brief (MPDDRC_MADDR0) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MADDR0_ADDR_HIGH_PORT0(value) ((MPDDRC_MADDR0_ADDR_HIGH_PORT0_Msk & ((value) << MPDDRC_MADDR0_ADDR_HIGH_PORT0_Pos)))\r
+/* -------- MPDDRC_MADDR1 : (MPDDRC Offset: 0x68) MPDDRC Monitor Address High/Low port 1 -------- */\r
+#define MPDDRC_MADDR1_ADDR_LOW_PORT1_Pos 0\r
+#define MPDDRC_MADDR1_ADDR_LOW_PORT1_Msk (0xffffu << MPDDRC_MADDR1_ADDR_LOW_PORT1_Pos) /**< \brief (MPDDRC_MADDR1) Address Low on Port x [x =0..7] */\r
+#define MPDDRC_MADDR1_ADDR_LOW_PORT1(value) ((MPDDRC_MADDR1_ADDR_LOW_PORT1_Msk & ((value) << MPDDRC_MADDR1_ADDR_LOW_PORT1_Pos)))\r
+#define MPDDRC_MADDR1_ADDR_HIGH_PORT1_Pos 16\r
+#define MPDDRC_MADDR1_ADDR_HIGH_PORT1_Msk (0xffffu << MPDDRC_MADDR1_ADDR_HIGH_PORT1_Pos) /**< \brief (MPDDRC_MADDR1) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MADDR1_ADDR_HIGH_PORT1(value) ((MPDDRC_MADDR1_ADDR_HIGH_PORT1_Msk & ((value) << MPDDRC_MADDR1_ADDR_HIGH_PORT1_Pos)))\r
+/* -------- MPDDRC_MADDR2 : (MPDDRC Offset: 0x6C) MPDDRC Monitor Address High/Low port 2 -------- */\r
+#define MPDDRC_MADDR2_ADDR_LOW_PORT2_Pos 0\r
+#define MPDDRC_MADDR2_ADDR_LOW_PORT2_Msk (0xffffu << MPDDRC_MADDR2_ADDR_LOW_PORT2_Pos) /**< \brief (MPDDRC_MADDR2) Address Low on Port x [x =0..7] */\r
+#define MPDDRC_MADDR2_ADDR_LOW_PORT2(value) ((MPDDRC_MADDR2_ADDR_LOW_PORT2_Msk & ((value) << MPDDRC_MADDR2_ADDR_LOW_PORT2_Pos)))\r
+#define MPDDRC_MADDR2_ADDR_HIGH_PORT2_Pos 16\r
+#define MPDDRC_MADDR2_ADDR_HIGH_PORT2_Msk (0xffffu << MPDDRC_MADDR2_ADDR_HIGH_PORT2_Pos) /**< \brief (MPDDRC_MADDR2) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MADDR2_ADDR_HIGH_PORT2(value) ((MPDDRC_MADDR2_ADDR_HIGH_PORT2_Msk & ((value) << MPDDRC_MADDR2_ADDR_HIGH_PORT2_Pos)))\r
+/* -------- MPDDRC_MADDR3 : (MPDDRC Offset: 0x70) MPDDRC Monitor Address High/Low port 3 -------- */\r
+#define MPDDRC_MADDR3_ADDR_LOW_PORT3_Pos 0\r
+#define MPDDRC_MADDR3_ADDR_LOW_PORT3_Msk (0xffffu << MPDDRC_MADDR3_ADDR_LOW_PORT3_Pos) /**< \brief (MPDDRC_MADDR3) Address Low on Port x [x =0..7] */\r
+#define MPDDRC_MADDR3_ADDR_LOW_PORT3(value) ((MPDDRC_MADDR3_ADDR_LOW_PORT3_Msk & ((value) << MPDDRC_MADDR3_ADDR_LOW_PORT3_Pos)))\r
+#define MPDDRC_MADDR3_ADDR_HIGH_PORT3_Pos 16\r
+#define MPDDRC_MADDR3_ADDR_HIGH_PORT3_Msk (0xffffu << MPDDRC_MADDR3_ADDR_HIGH_PORT3_Pos) /**< \brief (MPDDRC_MADDR3) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MADDR3_ADDR_HIGH_PORT3(value) ((MPDDRC_MADDR3_ADDR_HIGH_PORT3_Msk & ((value) << MPDDRC_MADDR3_ADDR_HIGH_PORT3_Pos)))\r
+/* -------- MPDDRC_MADDR4 : (MPDDRC Offset: 0x74) MPDDRC Monitor Address High/Low port 4 -------- */\r
+#define MPDDRC_MADDR4_ADDR_LOW_PORT4_Pos 0\r
+#define MPDDRC_MADDR4_ADDR_LOW_PORT4_Msk (0xffffu << MPDDRC_MADDR4_ADDR_LOW_PORT4_Pos) /**< \brief (MPDDRC_MADDR4) Address Low on Port x [x =0..7] */\r
+#define MPDDRC_MADDR4_ADDR_LOW_PORT4(value) ((MPDDRC_MADDR4_ADDR_LOW_PORT4_Msk & ((value) << MPDDRC_MADDR4_ADDR_LOW_PORT4_Pos)))\r
+#define MPDDRC_MADDR4_ADDR_HIGH_PORT4_Pos 16\r
+#define MPDDRC_MADDR4_ADDR_HIGH_PORT4_Msk (0xffffu << MPDDRC_MADDR4_ADDR_HIGH_PORT4_Pos) /**< \brief (MPDDRC_MADDR4) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MADDR4_ADDR_HIGH_PORT4(value) ((MPDDRC_MADDR4_ADDR_HIGH_PORT4_Msk & ((value) << MPDDRC_MADDR4_ADDR_HIGH_PORT4_Pos)))\r
+/* -------- MPDDRC_MADDR5 : (MPDDRC Offset: 0x78) MPDDRC Monitor Address High/Low port 5 -------- */\r
+#define MPDDRC_MADDR5_ADDR_LOW_PORT5_Pos 0\r
+#define MPDDRC_MADDR5_ADDR_LOW_PORT5_Msk (0xffffu << MPDDRC_MADDR5_ADDR_LOW_PORT5_Pos) /**< \brief (MPDDRC_MADDR5) Address Low on Port x [x =0..7] */\r
+#define MPDDRC_MADDR5_ADDR_LOW_PORT5(value) ((MPDDRC_MADDR5_ADDR_LOW_PORT5_Msk & ((value) << MPDDRC_MADDR5_ADDR_LOW_PORT5_Pos)))\r
+#define MPDDRC_MADDR5_ADDR_HIGH_PORT5_Pos 16\r
+#define MPDDRC_MADDR5_ADDR_HIGH_PORT5_Msk (0xffffu << MPDDRC_MADDR5_ADDR_HIGH_PORT5_Pos) /**< \brief (MPDDRC_MADDR5) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MADDR5_ADDR_HIGH_PORT5(value) ((MPDDRC_MADDR5_ADDR_HIGH_PORT5_Msk & ((value) << MPDDRC_MADDR5_ADDR_HIGH_PORT5_Pos)))\r
+/* -------- MPDDRC_MADDR6 : (MPDDRC Offset: 0x7C) MPDDRC Monitor Address High/Low port 6 -------- */\r
+#define MPDDRC_MADDR6_ADDR_LOW_PORT6_Pos 0\r
+#define MPDDRC_MADDR6_ADDR_LOW_PORT6_Msk (0xffffu << MPDDRC_MADDR6_ADDR_LOW_PORT6_Pos) /**< \brief (MPDDRC_MADDR6) Address Low on Port x [x =0..7] */\r
+#define MPDDRC_MADDR6_ADDR_LOW_PORT6(value) ((MPDDRC_MADDR6_ADDR_LOW_PORT6_Msk & ((value) << MPDDRC_MADDR6_ADDR_LOW_PORT6_Pos)))\r
+#define MPDDRC_MADDR6_ADDR_HIGH_PORT6_Pos 16\r
+#define MPDDRC_MADDR6_ADDR_HIGH_PORT6_Msk (0xffffu << MPDDRC_MADDR6_ADDR_HIGH_PORT6_Pos) /**< \brief (MPDDRC_MADDR6) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MADDR6_ADDR_HIGH_PORT6(value) ((MPDDRC_MADDR6_ADDR_HIGH_PORT6_Msk & ((value) << MPDDRC_MADDR6_ADDR_HIGH_PORT6_Pos)))\r
+/* -------- MPDDRC_MADDR7 : (MPDDRC Offset: 0x80) MPDDRC Monitor Address High/Low port 7 -------- */\r
+#define MPDDRC_MADDR7_ADDR_LOW_PORT7_Pos 0\r
+#define MPDDRC_MADDR7_ADDR_LOW_PORT7_Msk (0xffffu << MPDDRC_MADDR7_ADDR_LOW_PORT7_Pos) /**< \brief (MPDDRC_MADDR7) Address Low on Port x [x =0..7] */\r
+#define MPDDRC_MADDR7_ADDR_LOW_PORT7(value) ((MPDDRC_MADDR7_ADDR_LOW_PORT7_Msk & ((value) << MPDDRC_MADDR7_ADDR_LOW_PORT7_Pos)))\r
+#define MPDDRC_MADDR7_ADDR_HIGH_PORT7_Pos 16\r
+#define MPDDRC_MADDR7_ADDR_HIGH_PORT7_Msk (0xffffu << MPDDRC_MADDR7_ADDR_HIGH_PORT7_Pos) /**< \brief (MPDDRC_MADDR7) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MADDR7_ADDR_HIGH_PORT7(value) ((MPDDRC_MADDR7_ADDR_HIGH_PORT7_Msk & ((value) << MPDDRC_MADDR7_ADDR_HIGH_PORT7_Pos)))\r
+/* -------- MPDDRC_MINFO0 : (MPDDRC Offset: 0x84) MPDDRC Monitor Information port 0 -------- */\r
+#define MPDDRC_MINFO0_MAX_PORT0_WAITING_Pos 0\r
+#define MPDDRC_MINFO0_MAX_PORT0_WAITING_Msk (0xffffu << MPDDRC_MINFO0_MAX_PORT0_WAITING_Pos) /**< \brief (MPDDRC_MINFO0) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MINFO0_BURST_Pos 16\r
+#define MPDDRC_MINFO0_BURST_Msk (0x7u << MPDDRC_MINFO0_BURST_Pos) /**< \brief (MPDDRC_MINFO0) Type of Burst on Port x [x =0..7] */\r
+#define MPDDRC_MINFO0_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO0) Single transfer */\r
+#define MPDDRC_MINFO0_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO0) Incrementing burst of unspecified length */\r
+#define MPDDRC_MINFO0_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO0) 4-beat wrapping burst */\r
+#define MPDDRC_MINFO0_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO0) 4-beat incrementing burst */\r
+#define MPDDRC_MINFO0_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO0) 8-beat wrapping burst */\r
+#define MPDDRC_MINFO0_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO0) 8-beat incrementing burst */\r
+#define MPDDRC_MINFO0_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO0) 16-beat wrapping burst */\r
+#define MPDDRC_MINFO0_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO0) 16-beat incrementing burst */\r
+#define MPDDRC_MINFO0_SIZE_Pos 20\r
+#define MPDDRC_MINFO0_SIZE_Msk (0x7u << MPDDRC_MINFO0_SIZE_Pos) /**< \brief (MPDDRC_MINFO0) Transfer Size on Port x [x =0..7] */\r
+#define MPDDRC_MINFO0_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO0) Byte transfer */\r
+#define MPDDRC_MINFO0_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO0) Halfword transfer */\r
+#define MPDDRC_MINFO0_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO0) Word transfer */\r
+#define MPDDRC_MINFO0_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO0) Dword transfer */\r
+#define MPDDRC_MINFO0_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO0) Read or Write Access on Port x [x =0..7] */\r
+#define MPDDRC_MINFO0_P0_NB_TRANSFERS_Pos 0\r
+#define MPDDRC_MINFO0_P0_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO0_P0_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO0) Number of Transfers on Port x [x =0..7] */\r
+#define MPDDRC_MINFO0_P0_TOTAL_LATENCY_Pos 0\r
+#define MPDDRC_MINFO0_P0_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO0_P0_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO0) Total Latency on Port x [x =0..7] */\r
+/* -------- MPDDRC_MINFO1 : (MPDDRC Offset: 0x88) MPDDRC Monitor Information port 1 -------- */\r
+#define MPDDRC_MINFO1_MAX_PORT1_WAITING_Pos 0\r
+#define MPDDRC_MINFO1_MAX_PORT1_WAITING_Msk (0xffffu << MPDDRC_MINFO1_MAX_PORT1_WAITING_Pos) /**< \brief (MPDDRC_MINFO1) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MINFO1_BURST_Pos 16\r
+#define MPDDRC_MINFO1_BURST_Msk (0x7u << MPDDRC_MINFO1_BURST_Pos) /**< \brief (MPDDRC_MINFO1) Type of Burst on Port x [x =0..7] */\r
+#define MPDDRC_MINFO1_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO1) Single transfer */\r
+#define MPDDRC_MINFO1_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO1) Incrementing burst of unspecified length */\r
+#define MPDDRC_MINFO1_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO1) 4-beat wrapping burst */\r
+#define MPDDRC_MINFO1_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO1) 4-beat incrementing burst */\r
+#define MPDDRC_MINFO1_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO1) 8-beat wrapping burst */\r
+#define MPDDRC_MINFO1_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO1) 8-beat incrementing burst */\r
+#define MPDDRC_MINFO1_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO1) 16-beat wrapping burst */\r
+#define MPDDRC_MINFO1_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO1) 16-beat incrementing burst */\r
+#define MPDDRC_MINFO1_SIZE_Pos 20\r
+#define MPDDRC_MINFO1_SIZE_Msk (0x7u << MPDDRC_MINFO1_SIZE_Pos) /**< \brief (MPDDRC_MINFO1) Transfer Size on Port x [x =0..7] */\r
+#define MPDDRC_MINFO1_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO1) Byte transfer */\r
+#define MPDDRC_MINFO1_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO1) Halfword transfer */\r
+#define MPDDRC_MINFO1_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO1) Word transfer */\r
+#define MPDDRC_MINFO1_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO1) Dword transfer */\r
+#define MPDDRC_MINFO1_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO1) Read or Write Access on Port x [x =0..7] */\r
+#define MPDDRC_MINFO1_P1_NB_TRANSFERS_Pos 0\r
+#define MPDDRC_MINFO1_P1_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO1_P1_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO1) Number of Transfers on Port x [x =0..7] */\r
+#define MPDDRC_MINFO1_P1_TOTAL_LATENCY_Pos 0\r
+#define MPDDRC_MINFO1_P1_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO1_P1_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO1) Total Latency on Port x [x =0..7] */\r
+/* -------- MPDDRC_MINFO2 : (MPDDRC Offset: 0x8C) MPDDRC Monitor Information port 2 -------- */\r
+#define MPDDRC_MINFO2_MAX_PORT2_WAITING_Pos 0\r
+#define MPDDRC_MINFO2_MAX_PORT2_WAITING_Msk (0xffffu << MPDDRC_MINFO2_MAX_PORT2_WAITING_Pos) /**< \brief (MPDDRC_MINFO2) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MINFO2_BURST_Pos 16\r
+#define MPDDRC_MINFO2_BURST_Msk (0x7u << MPDDRC_MINFO2_BURST_Pos) /**< \brief (MPDDRC_MINFO2) Type of Burst on Port x [x =0..7] */\r
+#define MPDDRC_MINFO2_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO2) Single transfer */\r
+#define MPDDRC_MINFO2_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO2) Incrementing burst of unspecified length */\r
+#define MPDDRC_MINFO2_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO2) 4-beat wrapping burst */\r
+#define MPDDRC_MINFO2_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO2) 4-beat incrementing burst */\r
+#define MPDDRC_MINFO2_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO2) 8-beat wrapping burst */\r
+#define MPDDRC_MINFO2_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO2) 8-beat incrementing burst */\r
+#define MPDDRC_MINFO2_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO2) 16-beat wrapping burst */\r
+#define MPDDRC_MINFO2_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO2) 16-beat incrementing burst */\r
+#define MPDDRC_MINFO2_SIZE_Pos 20\r
+#define MPDDRC_MINFO2_SIZE_Msk (0x7u << MPDDRC_MINFO2_SIZE_Pos) /**< \brief (MPDDRC_MINFO2) Transfer Size on Port x [x =0..7] */\r
+#define MPDDRC_MINFO2_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO2) Byte transfer */\r
+#define MPDDRC_MINFO2_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO2) Halfword transfer */\r
+#define MPDDRC_MINFO2_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO2) Word transfer */\r
+#define MPDDRC_MINFO2_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO2) Dword transfer */\r
+#define MPDDRC_MINFO2_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO2) Read or Write Access on Port x [x =0..7] */\r
+#define MPDDRC_MINFO2_P2_NB_TRANSFERS_Pos 0\r
+#define MPDDRC_MINFO2_P2_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO2_P2_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO2) Number of Transfers on Port x [x =0..7] */\r
+#define MPDDRC_MINFO2_P2_TOTAL_LATENCY_Pos 0\r
+#define MPDDRC_MINFO2_P2_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO2_P2_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO2) Total Latency on Port x [x =0..7] */\r
+/* -------- MPDDRC_MINFO3 : (MPDDRC Offset: 0x90) MPDDRC Monitor Information port 3 -------- */\r
+#define MPDDRC_MINFO3_MAX_PORT3_WAITING_Pos 0\r
+#define MPDDRC_MINFO3_MAX_PORT3_WAITING_Msk (0xffffu << MPDDRC_MINFO3_MAX_PORT3_WAITING_Pos) /**< \brief (MPDDRC_MINFO3) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MINFO3_BURST_Pos 16\r
+#define MPDDRC_MINFO3_BURST_Msk (0x7u << MPDDRC_MINFO3_BURST_Pos) /**< \brief (MPDDRC_MINFO3) Type of Burst on Port x [x =0..7] */\r
+#define MPDDRC_MINFO3_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO3) Single transfer */\r
+#define MPDDRC_MINFO3_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO3) Incrementing burst of unspecified length */\r
+#define MPDDRC_MINFO3_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO3) 4-beat wrapping burst */\r
+#define MPDDRC_MINFO3_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO3) 4-beat incrementing burst */\r
+#define MPDDRC_MINFO3_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO3) 8-beat wrapping burst */\r
+#define MPDDRC_MINFO3_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO3) 8-beat incrementing burst */\r
+#define MPDDRC_MINFO3_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO3) 16-beat wrapping burst */\r
+#define MPDDRC_MINFO3_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO3) 16-beat incrementing burst */\r
+#define MPDDRC_MINFO3_SIZE_Pos 20\r
+#define MPDDRC_MINFO3_SIZE_Msk (0x7u << MPDDRC_MINFO3_SIZE_Pos) /**< \brief (MPDDRC_MINFO3) Transfer Size on Port x [x =0..7] */\r
+#define MPDDRC_MINFO3_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO3) Byte transfer */\r
+#define MPDDRC_MINFO3_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO3) Halfword transfer */\r
+#define MPDDRC_MINFO3_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO3) Word transfer */\r
+#define MPDDRC_MINFO3_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO3) Dword transfer */\r
+#define MPDDRC_MINFO3_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO3) Read or Write Access on Port x [x =0..7] */\r
+#define MPDDRC_MINFO3_P3_NB_TRANSFERS_Pos 0\r
+#define MPDDRC_MINFO3_P3_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO3_P3_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO3) Number of Transfers on Port x [x =0..7] */\r
+#define MPDDRC_MINFO3_P3_TOTAL_LATENCY_Pos 0\r
+#define MPDDRC_MINFO3_P3_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO3_P3_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO3) Total Latency on Port x [x =0..7] */\r
+/* -------- MPDDRC_MINFO4 : (MPDDRC Offset: 0x94) MPDDRC Monitor Information port 4 -------- */\r
+#define MPDDRC_MINFO4_MAX_PORT4_WAITING_Pos 0\r
+#define MPDDRC_MINFO4_MAX_PORT4_WAITING_Msk (0xffffu << MPDDRC_MINFO4_MAX_PORT4_WAITING_Pos) /**< \brief (MPDDRC_MINFO4) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MINFO4_BURST_Pos 16\r
+#define MPDDRC_MINFO4_BURST_Msk (0x7u << MPDDRC_MINFO4_BURST_Pos) /**< \brief (MPDDRC_MINFO4) Type of Burst on Port x [x =0..7] */\r
+#define MPDDRC_MINFO4_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO4) Single transfer */\r
+#define MPDDRC_MINFO4_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO4) Incrementing burst of unspecified length */\r
+#define MPDDRC_MINFO4_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO4) 4-beat wrapping burst */\r
+#define MPDDRC_MINFO4_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO4) 4-beat incrementing burst */\r
+#define MPDDRC_MINFO4_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO4) 8-beat wrapping burst */\r
+#define MPDDRC_MINFO4_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO4) 8-beat incrementing burst */\r
+#define MPDDRC_MINFO4_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO4) 16-beat wrapping burst */\r
+#define MPDDRC_MINFO4_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO4) 16-beat incrementing burst */\r
+#define MPDDRC_MINFO4_SIZE_Pos 20\r
+#define MPDDRC_MINFO4_SIZE_Msk (0x7u << MPDDRC_MINFO4_SIZE_Pos) /**< \brief (MPDDRC_MINFO4) Transfer Size on Port x [x =0..7] */\r
+#define MPDDRC_MINFO4_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO4) Byte transfer */\r
+#define MPDDRC_MINFO4_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO4) Halfword transfer */\r
+#define MPDDRC_MINFO4_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO4) Word transfer */\r
+#define MPDDRC_MINFO4_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO4) Dword transfer */\r
+#define MPDDRC_MINFO4_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO4) Read or Write Access on Port x [x =0..7] */\r
+#define MPDDRC_MINFO4_P4_NB_TRANSFERS_Pos 0\r
+#define MPDDRC_MINFO4_P4_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO4_P4_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO4) Number of Transfers on Port x [x =0..7] */\r
+#define MPDDRC_MINFO4_P4_TOTAL_LATENCY_Pos 0\r
+#define MPDDRC_MINFO4_P4_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO4_P4_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO4) Total Latency on Port x [x =0..7] */\r
+/* -------- MPDDRC_MINFO5 : (MPDDRC Offset: 0x98) MPDDRC Monitor Information port 5 -------- */\r
+#define MPDDRC_MINFO5_MAX_PORT5_WAITING_Pos 0\r
+#define MPDDRC_MINFO5_MAX_PORT5_WAITING_Msk (0xffffu << MPDDRC_MINFO5_MAX_PORT5_WAITING_Pos) /**< \brief (MPDDRC_MINFO5) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MINFO5_BURST_Pos 16\r
+#define MPDDRC_MINFO5_BURST_Msk (0x7u << MPDDRC_MINFO5_BURST_Pos) /**< \brief (MPDDRC_MINFO5) Type of Burst on Port x [x =0..7] */\r
+#define MPDDRC_MINFO5_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO5) Single transfer */\r
+#define MPDDRC_MINFO5_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO5) Incrementing burst of unspecified length */\r
+#define MPDDRC_MINFO5_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO5) 4-beat wrapping burst */\r
+#define MPDDRC_MINFO5_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO5) 4-beat incrementing burst */\r
+#define MPDDRC_MINFO5_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO5) 8-beat wrapping burst */\r
+#define MPDDRC_MINFO5_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO5) 8-beat incrementing burst */\r
+#define MPDDRC_MINFO5_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO5) 16-beat wrapping burst */\r
+#define MPDDRC_MINFO5_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO5) 16-beat incrementing burst */\r
+#define MPDDRC_MINFO5_SIZE_Pos 20\r
+#define MPDDRC_MINFO5_SIZE_Msk (0x7u << MPDDRC_MINFO5_SIZE_Pos) /**< \brief (MPDDRC_MINFO5) Transfer Size on Port x [x =0..7] */\r
+#define MPDDRC_MINFO5_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO5) Byte transfer */\r
+#define MPDDRC_MINFO5_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO5) Halfword transfer */\r
+#define MPDDRC_MINFO5_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO5) Word transfer */\r
+#define MPDDRC_MINFO5_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO5) Dword transfer */\r
+#define MPDDRC_MINFO5_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO5) Read or Write Access on Port x [x =0..7] */\r
+#define MPDDRC_MINFO5_P5_NB_TRANSFERS_Pos 0\r
+#define MPDDRC_MINFO5_P5_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO5_P5_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO5) Number of Transfers on Port x [x =0..7] */\r
+#define MPDDRC_MINFO5_P5_TOTAL_LATENCY_Pos 0\r
+#define MPDDRC_MINFO5_P5_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO5_P5_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO5) Total Latency on Port x [x =0..7] */\r
+/* -------- MPDDRC_MINFO6 : (MPDDRC Offset: 0x9C) MPDDRC Monitor Information port 6 -------- */\r
+#define MPDDRC_MINFO6_MAX_PORT6_WAITING_Pos 0\r
+#define MPDDRC_MINFO6_MAX_PORT6_WAITING_Msk (0xffffu << MPDDRC_MINFO6_MAX_PORT6_WAITING_Pos) /**< \brief (MPDDRC_MINFO6) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MINFO6_BURST_Pos 16\r
+#define MPDDRC_MINFO6_BURST_Msk (0x7u << MPDDRC_MINFO6_BURST_Pos) /**< \brief (MPDDRC_MINFO6) Type of Burst on Port x [x =0..7] */\r
+#define MPDDRC_MINFO6_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO6) Single transfer */\r
+#define MPDDRC_MINFO6_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO6) Incrementing burst of unspecified length */\r
+#define MPDDRC_MINFO6_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO6) 4-beat wrapping burst */\r
+#define MPDDRC_MINFO6_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO6) 4-beat incrementing burst */\r
+#define MPDDRC_MINFO6_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO6) 8-beat wrapping burst */\r
+#define MPDDRC_MINFO6_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO6) 8-beat incrementing burst */\r
+#define MPDDRC_MINFO6_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO6) 16-beat wrapping burst */\r
+#define MPDDRC_MINFO6_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO6) 16-beat incrementing burst */\r
+#define MPDDRC_MINFO6_SIZE_Pos 20\r
+#define MPDDRC_MINFO6_SIZE_Msk (0x7u << MPDDRC_MINFO6_SIZE_Pos) /**< \brief (MPDDRC_MINFO6) Transfer Size on Port x [x =0..7] */\r
+#define MPDDRC_MINFO6_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO6) Byte transfer */\r
+#define MPDDRC_MINFO6_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO6) Halfword transfer */\r
+#define MPDDRC_MINFO6_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO6) Word transfer */\r
+#define MPDDRC_MINFO6_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO6) Dword transfer */\r
+#define MPDDRC_MINFO6_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO6) Read or Write Access on Port x [x =0..7] */\r
+#define MPDDRC_MINFO6_P6_NB_TRANSFERS_Pos 0\r
+#define MPDDRC_MINFO6_P6_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO6_P6_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO6) Number of Transfers on Port x [x =0..7] */\r
+#define MPDDRC_MINFO6_P6_TOTAL_LATENCY_Pos 0\r
+#define MPDDRC_MINFO6_P6_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO6_P6_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO6) Total Latency on Port x [x =0..7] */\r
+/* -------- MPDDRC_MINFO7 : (MPDDRC Offset: 0xA0) MPDDRC Monitor Information port 7 -------- */\r
+#define MPDDRC_MINFO7_MAX_PORT7_WAITING_Pos 0\r
+#define MPDDRC_MINFO7_MAX_PORT7_WAITING_Msk (0xffffu << MPDDRC_MINFO7_MAX_PORT7_WAITING_Pos) /**< \brief (MPDDRC_MINFO7) Address High on Port x [x =0..7] */\r
+#define MPDDRC_MINFO7_BURST_Pos 16\r
+#define MPDDRC_MINFO7_BURST_Msk (0x7u << MPDDRC_MINFO7_BURST_Pos) /**< \brief (MPDDRC_MINFO7) Type of Burst on Port x [x =0..7] */\r
+#define MPDDRC_MINFO7_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO7) Single transfer */\r
+#define MPDDRC_MINFO7_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO7) Incrementing burst of unspecified length */\r
+#define MPDDRC_MINFO7_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO7) 4-beat wrapping burst */\r
+#define MPDDRC_MINFO7_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO7) 4-beat incrementing burst */\r
+#define MPDDRC_MINFO7_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO7) 8-beat wrapping burst */\r
+#define MPDDRC_MINFO7_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO7) 8-beat incrementing burst */\r
+#define MPDDRC_MINFO7_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO7) 16-beat wrapping burst */\r
+#define MPDDRC_MINFO7_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO7) 16-beat incrementing burst */\r
+#define MPDDRC_MINFO7_SIZE_Pos 20\r
+#define MPDDRC_MINFO7_SIZE_Msk (0x7u << MPDDRC_MINFO7_SIZE_Pos) /**< \brief (MPDDRC_MINFO7) Transfer Size on Port x [x =0..7] */\r
+#define MPDDRC_MINFO7_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO7) Byte transfer */\r
+#define MPDDRC_MINFO7_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO7) Halfword transfer */\r
+#define MPDDRC_MINFO7_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO7) Word transfer */\r
+#define MPDDRC_MINFO7_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO7) Dword transfer */\r
+#define MPDDRC_MINFO7_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO7) Read or Write Access on Port x [x =0..7] */\r
+#define MPDDRC_MINFO7_P7_NB_TRANSFERS_Pos 0\r
+#define MPDDRC_MINFO7_P7_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO7_P7_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO7) Number of Transfers on Port x [x =0..7] */\r
+#define MPDDRC_MINFO7_P7_TOTAL_LATENCY_Pos 0\r
+#define MPDDRC_MINFO7_P7_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO7_P7_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO7) Total Latency on Port x [x =0..7] */\r
+/* -------- MPDDRC_WPMR : (MPDDRC Offset: 0xE4) MPDDRC Write Protection Mode Register -------- */\r
+#define MPDDRC_WPMR_WPEN (0x1u << 0) /**< \brief (MPDDRC_WPMR) Write Protection Enable */\r
+#define MPDDRC_WPMR_WPKEY_Pos 8\r
+#define MPDDRC_WPMR_WPKEY_Msk (0xffffffu << MPDDRC_WPMR_WPKEY_Pos) /**< \brief (MPDDRC_WPMR) Write Protection Key */\r
+#define MPDDRC_WPMR_WPKEY(value) ((MPDDRC_WPMR_WPKEY_Msk & ((value) << MPDDRC_WPMR_WPKEY_Pos)))\r
+#define MPDDRC_WPMR_WPKEY_PASSWD (0x444452u << 8) /**< \brief (MPDDRC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- MPDDRC_WPSR : (MPDDRC Offset: 0xE8) MPDDRC Write Protection Status Register -------- */\r
+#define MPDDRC_WPSR_WPVS (0x1u << 0) /**< \brief (MPDDRC_WPSR) Write Protection Enable */\r
+#define MPDDRC_WPSR_WPVSRC_Pos 8\r
+#define MPDDRC_WPSR_WPVSRC_Msk (0xffffu << MPDDRC_WPSR_WPVSRC_Pos) /**< \brief (MPDDRC_WPSR) Write Protection Violation Source */\r
+/* -------- MPDDRC_VERSION : (MPDDRC Offset: 0xFC) MPDDRC Version Register -------- */\r
+#define MPDDRC_VERSION_VERSION_Pos 0\r
+#define MPDDRC_VERSION_VERSION_Msk (0xffffu << MPDDRC_VERSION_VERSION_Pos) /**< \brief (MPDDRC_VERSION) Version of the Hardware Module */\r
+#define MPDDRC_VERSION_MFN_Pos 16\r
+#define MPDDRC_VERSION_MFN_Msk (0xfu << MPDDRC_VERSION_MFN_Pos) /**< \brief (MPDDRC_VERSION) Metal Fix Number */\r
+/* -------- MPDDRC_DLL_OS : (MPDDRC Offset: 0x100) MPDDRC DLL Offset Selection Register -------- */\r
+#define MPDDRC_DLL_OS_SELOFF (0x1u << 0) /**< \brief (MPDDRC_DLL_OS) Offset Selection */\r
+/* -------- MPDDRC_DLL_MAO : (MPDDRC Offset: 0x104) MPDDRC DLL MASTER Offset Register -------- */\r
+#define MPDDRC_DLL_MAO_MAOFF_Pos 0\r
+#define MPDDRC_DLL_MAO_MAOFF_Msk (0xffu << MPDDRC_DLL_MAO_MAOFF_Pos) /**< \brief (MPDDRC_DLL_MAO) Master Delay Line Offset */\r
+#define MPDDRC_DLL_MAO_MAOFF(value) ((MPDDRC_DLL_MAO_MAOFF_Msk & ((value) << MPDDRC_DLL_MAO_MAOFF_Pos)))\r
+/* -------- MPDDRC_DLL_SO0 : (MPDDRC Offset: 0x108) MPDDRC DLL SLAVE Offset 0 Register -------- */\r
+#define MPDDRC_DLL_SO0_S0OFF_Pos 0\r
+#define MPDDRC_DLL_SO0_S0OFF_Msk (0xffu << MPDDRC_DLL_SO0_S0OFF_Pos) /**< \brief (MPDDRC_DLL_SO0) SLAVEx Delay Line Offset */\r
+#define MPDDRC_DLL_SO0_S0OFF(value) ((MPDDRC_DLL_SO0_S0OFF_Msk & ((value) << MPDDRC_DLL_SO0_S0OFF_Pos)))\r
+#define MPDDRC_DLL_SO0_S1OFF_Pos 8\r
+#define MPDDRC_DLL_SO0_S1OFF_Msk (0xffu << MPDDRC_DLL_SO0_S1OFF_Pos) /**< \brief (MPDDRC_DLL_SO0) SLAVEx Delay Line Offset */\r
+#define MPDDRC_DLL_SO0_S1OFF(value) ((MPDDRC_DLL_SO0_S1OFF_Msk & ((value) << MPDDRC_DLL_SO0_S1OFF_Pos)))\r
+#define MPDDRC_DLL_SO0_S2OFF_Pos 16\r
+#define MPDDRC_DLL_SO0_S2OFF_Msk (0xffu << MPDDRC_DLL_SO0_S2OFF_Pos) /**< \brief (MPDDRC_DLL_SO0) SLAVEx Delay Line Offset */\r
+#define MPDDRC_DLL_SO0_S2OFF(value) ((MPDDRC_DLL_SO0_S2OFF_Msk & ((value) << MPDDRC_DLL_SO0_S2OFF_Pos)))\r
+#define MPDDRC_DLL_SO0_S3OFF_Pos 24\r
+#define MPDDRC_DLL_SO0_S3OFF_Msk (0xffu << MPDDRC_DLL_SO0_S3OFF_Pos) /**< \brief (MPDDRC_DLL_SO0) SLAVEx Delay Line Offset */\r
+#define MPDDRC_DLL_SO0_S3OFF(value) ((MPDDRC_DLL_SO0_S3OFF_Msk & ((value) << MPDDRC_DLL_SO0_S3OFF_Pos)))\r
+/* -------- MPDDRC_DLL_SO1 : (MPDDRC Offset: 0x10C) MPDDRC DLL SLAVE Offset 1 Register -------- */\r
+#define MPDDRC_DLL_SO1_S4OFF_Pos 0\r
+#define MPDDRC_DLL_SO1_S4OFF_Msk (0xffu << MPDDRC_DLL_SO1_S4OFF_Pos) /**< \brief (MPDDRC_DLL_SO1) SLAVEx Delay Line Offset */\r
+#define MPDDRC_DLL_SO1_S4OFF(value) ((MPDDRC_DLL_SO1_S4OFF_Msk & ((value) << MPDDRC_DLL_SO1_S4OFF_Pos)))\r
+#define MPDDRC_DLL_SO1_S5OFF_Pos 8\r
+#define MPDDRC_DLL_SO1_S5OFF_Msk (0xffu << MPDDRC_DLL_SO1_S5OFF_Pos) /**< \brief (MPDDRC_DLL_SO1) SLAVEx Delay Line Offset */\r
+#define MPDDRC_DLL_SO1_S5OFF(value) ((MPDDRC_DLL_SO1_S5OFF_Msk & ((value) << MPDDRC_DLL_SO1_S5OFF_Pos)))\r
+#define MPDDRC_DLL_SO1_S6OFF_Pos 16\r
+#define MPDDRC_DLL_SO1_S6OFF_Msk (0xffu << MPDDRC_DLL_SO1_S6OFF_Pos) /**< \brief (MPDDRC_DLL_SO1) SLAVEx Delay Line Offset */\r
+#define MPDDRC_DLL_SO1_S6OFF(value) ((MPDDRC_DLL_SO1_S6OFF_Msk & ((value) << MPDDRC_DLL_SO1_S6OFF_Pos)))\r
+#define MPDDRC_DLL_SO1_S7OFF_Pos 24\r
+#define MPDDRC_DLL_SO1_S7OFF_Msk (0xffu << MPDDRC_DLL_SO1_S7OFF_Pos) /**< \brief (MPDDRC_DLL_SO1) SLAVEx Delay Line Offset */\r
+#define MPDDRC_DLL_SO1_S7OFF(value) ((MPDDRC_DLL_SO1_S7OFF_Msk & ((value) << MPDDRC_DLL_SO1_S7OFF_Pos)))\r
+/* -------- MPDDRC_DLL_WRO : (MPDDRC Offset: 0x110) MPDDRC DLL CLKWR Offset Register -------- */\r
+#define MPDDRC_DLL_WRO_WR0OFF_Pos 0\r
+#define MPDDRC_DLL_WRO_WR0OFF_Msk (0xffu << MPDDRC_DLL_WRO_WR0OFF_Pos) /**< \brief (MPDDRC_DLL_WRO) CLKWRx Delay Line Offset */\r
+#define MPDDRC_DLL_WRO_WR0OFF(value) ((MPDDRC_DLL_WRO_WR0OFF_Msk & ((value) << MPDDRC_DLL_WRO_WR0OFF_Pos)))\r
+#define MPDDRC_DLL_WRO_WR1OFF_Pos 8\r
+#define MPDDRC_DLL_WRO_WR1OFF_Msk (0xffu << MPDDRC_DLL_WRO_WR1OFF_Pos) /**< \brief (MPDDRC_DLL_WRO) CLKWRx Delay Line Offset */\r
+#define MPDDRC_DLL_WRO_WR1OFF(value) ((MPDDRC_DLL_WRO_WR1OFF_Msk & ((value) << MPDDRC_DLL_WRO_WR1OFF_Pos)))\r
+#define MPDDRC_DLL_WRO_WR2OFF_Pos 16\r
+#define MPDDRC_DLL_WRO_WR2OFF_Msk (0xffu << MPDDRC_DLL_WRO_WR2OFF_Pos) /**< \brief (MPDDRC_DLL_WRO) CLKWRx Delay Line Offset */\r
+#define MPDDRC_DLL_WRO_WR2OFF(value) ((MPDDRC_DLL_WRO_WR2OFF_Msk & ((value) << MPDDRC_DLL_WRO_WR2OFF_Pos)))\r
+#define MPDDRC_DLL_WRO_WR3OFF_Pos 24\r
+#define MPDDRC_DLL_WRO_WR3OFF_Msk (0xffu << MPDDRC_DLL_WRO_WR3OFF_Pos) /**< \brief (MPDDRC_DLL_WRO) CLKWRx Delay Line Offset */\r
+#define MPDDRC_DLL_WRO_WR3OFF(value) ((MPDDRC_DLL_WRO_WR3OFF_Msk & ((value) << MPDDRC_DLL_WRO_WR3OFF_Pos)))\r
+/* -------- MPDDRC_DLL_ADO : (MPDDRC Offset: 0x114) MPDDRC DLL CLKAD Offset Register -------- */\r
+#define MPDDRC_DLL_ADO_ADOFF_Pos 0\r
+#define MPDDRC_DLL_ADO_ADOFF_Msk (0xffu << MPDDRC_DLL_ADO_ADOFF_Pos) /**< \brief (MPDDRC_DLL_ADO) CLKAD Delay Line Offset */\r
+#define MPDDRC_DLL_ADO_ADOFF(value) ((MPDDRC_DLL_ADO_ADOFF_Msk & ((value) << MPDDRC_DLL_ADO_ADOFF_Pos)))\r
+/* -------- MPDDRC_DLL_SM[4] : (MPDDRC Offset: 0x118) MPDDRC DLL Status MASTER0 Register -------- */\r
+#define MPDDRC_DLL_SM_MDINC (0x1u << 0) /**< \brief (MPDDRC_DLL_SM[4]) MASTERx Delay Increment */\r
+#define MPDDRC_DLL_SM_MDDEC (0x1u << 1) /**< \brief (MPDDRC_DLL_SM[4]) MASTERx Delay Decrement */\r
+#define MPDDRC_DLL_SM_MDOVF (0x1u << 2) /**< \brief (MPDDRC_DLL_SM[4]) MASTERx Delay Overflow Flag */\r
+#define MPDDRC_DLL_SM_MDLVAL_Pos 8\r
+#define MPDDRC_DLL_SM_MDLVAL_Msk (0xffu << MPDDRC_DLL_SM_MDLVAL_Pos) /**< \brief (MPDDRC_DLL_SM[4]) MASTERx Delay Lock Value */\r
+#define MPDDRC_DLL_SM_MDCNT_Pos 20\r
+#define MPDDRC_DLL_SM_MDCNT_Msk (0xffu << MPDDRC_DLL_SM_MDCNT_Pos) /**< \brief (MPDDRC_DLL_SM[4]) MASTERx Delay Counter Value */\r
+/* -------- MPDDRC_DLL_SSL[8] : (MPDDRC Offset: 0x128) MPDDRC DLL Status SLAVE0 Register -------- */\r
+#define MPDDRC_DLL_SSL_SDCOVF (0x1u << 0) /**< \brief (MPDDRC_DLL_SSL[8]) SLAVEx Delay Correction Overflow Flag */\r
+#define MPDDRC_DLL_SSL_SDCUDF (0x1u << 1) /**< \brief (MPDDRC_DLL_SSL[8]) SLAVEx Delay Correction Underflow Flag */\r
+#define MPDDRC_DLL_SSL_SDERF (0x1u << 2) /**< \brief (MPDDRC_DLL_SSL[8]) SLAVEx Delay Correction Error Flag */\r
+#define MPDDRC_DLL_SSL_SDCNT_Pos 8\r
+#define MPDDRC_DLL_SSL_SDCNT_Msk (0xffu << MPDDRC_DLL_SSL_SDCNT_Pos) /**< \brief (MPDDRC_DLL_SSL[8]) SLAVEx Delay Counter Value */\r
+#define MPDDRC_DLL_SSL_SDCVAL_Pos 20\r
+#define MPDDRC_DLL_SSL_SDCVAL_Msk (0xffu << MPDDRC_DLL_SSL_SDCVAL_Pos) /**< \brief (MPDDRC_DLL_SSL[8]) SLAVEx Delay Correction Value */\r
+/* -------- MPDDRC_DLL_SWR[4] : (MPDDRC Offset: 0x148) MPDDRC DLL Status CLKWR0 Register -------- */\r
+#define MPDDRC_DLL_SWR_WRDCNT_Pos 0\r
+#define MPDDRC_DLL_SWR_WRDCNT_Msk (0xffu << MPDDRC_DLL_SWR_WRDCNT_Pos) /**< \brief (MPDDRC_DLL_SWR[4]) CLKWRx Delay Counter Value */\r
+/* -------- MPDDRC_DLL_SAD : (MPDDRC Offset: 0x158) MPDDRC DLL Status CLKAD Register -------- */\r
+#define MPDDRC_DLL_SAD_ADDCNT_Pos 0\r
+#define MPDDRC_DLL_SAD_ADDCNT_Msk (0xffu << MPDDRC_DLL_SAD_ADDCNT_Pos) /**< \brief (MPDDRC_DLL_SAD) CLKAD Delay Counter Value */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_MPDDRC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_PDMIC_COMPONENT_\r
+#define _SAMA5D2_PDMIC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Pulse Density Modulation Interface Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_PDMIC Pulse Density Modulation Interface Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pdmic hardware registers */\r
+typedef struct {\r
+ __IO uint32_t PDMIC_CR; /**< \brief (Pdmic Offset: 0x00) Control Register */\r
+ __IO uint32_t PDMIC_MR; /**< \brief (Pdmic Offset: 0x04) Mode Register */\r
+ __I uint32_t Reserved1[3];\r
+ __I uint32_t PDMIC_CDR; /**< \brief (Pdmic Offset: 0x14) Converted Data Register */\r
+ __O uint32_t PDMIC_IER; /**< \brief (Pdmic Offset: 0x18) Interrupt Enable Register */\r
+ __O uint32_t PDMIC_IDR; /**< \brief (Pdmic Offset: 0x1C) Interrupt Disable Register */\r
+ __I uint32_t PDMIC_IMR; /**< \brief (Pdmic Offset: 0x20) Interrupt Mask Register */\r
+ __I uint32_t PDMIC_ISR; /**< \brief (Pdmic Offset: 0x24) Interrupt Status Register */\r
+ __I uint32_t Reserved2[12];\r
+ __IO uint32_t PDMIC_DSPR0; /**< \brief (Pdmic Offset: 0x58) DSP Configuration Register 0 */\r
+ __IO uint32_t PDMIC_DSPR1; /**< \brief (Pdmic Offset: 0x5C) DSP Configuration Register 1 */\r
+ __I uint32_t Reserved3[33];\r
+ __IO uint32_t PDMIC_WPMR; /**< \brief (Pdmic Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t PDMIC_WPSR; /**< \brief (Pdmic Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved4[4];\r
+ __I uint32_t PDMIC_VERSION; /**< \brief (Pdmic Offset: 0xFC) Version Register */\r
+} Pdmic;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PDMIC_CR : (PDMIC Offset: 0x00) Control Register -------- */\r
+#define PDMIC_CR_SWRST (0x1u << 0) /**< \brief (PDMIC_CR) Software Reset */\r
+#define PDMIC_CR_ENPDM (0x1u << 4) /**< \brief (PDMIC_CR) Enable PDM */\r
+/* -------- PDMIC_MR : (PDMIC Offset: 0x04) Mode Register -------- */\r
+#define PDMIC_MR_PRESCAL_Pos 8\r
+#define PDMIC_MR_PRESCAL_Msk (0x7fu << PDMIC_MR_PRESCAL_Pos) /**< \brief (PDMIC_MR) Prescaler Rate Selection */\r
+#define PDMIC_MR_PRESCAL(value) ((PDMIC_MR_PRESCAL_Msk & ((value) << PDMIC_MR_PRESCAL_Pos)))\r
+/* -------- PDMIC_CDR : (PDMIC Offset: 0x14) Converted Data Register -------- */\r
+#define PDMIC_CDR_DATA_Pos 0\r
+#define PDMIC_CDR_DATA_Msk (0xffffffffu << PDMIC_CDR_DATA_Pos) /**< \brief (PDMIC_CDR) Data Converted */\r
+/* -------- PDMIC_IER : (PDMIC Offset: 0x18) Interrupt Enable Register -------- */\r
+#define PDMIC_IER_DRDY (0x1u << 24) /**< \brief (PDMIC_IER) Data Ready Interrupt Enable */\r
+#define PDMIC_IER_OVRE (0x1u << 25) /**< \brief (PDMIC_IER) Overrun Error Interrupt Enable */\r
+/* -------- PDMIC_IDR : (PDMIC Offset: 0x1C) Interrupt Disable Register -------- */\r
+#define PDMIC_IDR_DRDY (0x1u << 24) /**< \brief (PDMIC_IDR) Data Ready Interrupt Disable */\r
+#define PDMIC_IDR_OVRE (0x1u << 25) /**< \brief (PDMIC_IDR) General Overrun Error Interrupt Disable */\r
+/* -------- PDMIC_IMR : (PDMIC Offset: 0x20) Interrupt Mask Register -------- */\r
+#define PDMIC_IMR_DRDY (0x1u << 24) /**< \brief (PDMIC_IMR) Data Ready Interrupt Mask */\r
+#define PDMIC_IMR_OVRE (0x1u << 25) /**< \brief (PDMIC_IMR) General Overrun Error Interrupt Mask */\r
+/* -------- PDMIC_ISR : (PDMIC Offset: 0x24) Interrupt Status Register -------- */\r
+#define PDMIC_ISR_FIFOCNT_Pos 16\r
+#define PDMIC_ISR_FIFOCNT_Msk (0xffu << PDMIC_ISR_FIFOCNT_Pos) /**< \brief (PDMIC_ISR) FIFO Count */\r
+#define PDMIC_ISR_DRDY (0x1u << 24) /**< \brief (PDMIC_ISR) Data Ready (cleared by reading PDMIC_CDR) */\r
+#define PDMIC_ISR_OVRE (0x1u << 25) /**< \brief (PDMIC_ISR) Overrun Error (cleared on read) */\r
+/* -------- PDMIC_DSPR0 : (PDMIC Offset: 0x58) DSP Configuration Register 0 -------- */\r
+#define PDMIC_DSPR0_HPFBYP (0x1u << 1) /**< \brief (PDMIC_DSPR0) High-Pass Filter Bypass */\r
+#define PDMIC_DSPR0_SINBYP (0x1u << 2) /**< \brief (PDMIC_DSPR0) SINCC Filter Bypass */\r
+#define PDMIC_DSPR0_SIZE (0x1u << 3) /**< \brief (PDMIC_DSPR0) Data Size */\r
+#define PDMIC_DSPR0_OSR_Pos 4\r
+#define PDMIC_DSPR0_OSR_Msk (0x7u << PDMIC_DSPR0_OSR_Pos) /**< \brief (PDMIC_DSPR0) Oversampling Ratio */\r
+#define PDMIC_DSPR0_OSR(value) ((PDMIC_DSPR0_OSR_Msk & ((value) << PDMIC_DSPR0_OSR_Pos)))\r
+#define PDMIC_DSPR0_OSR_128 (0x0u << 4) /**< \brief (PDMIC_DSPR0) Oversampling ratio is 128 */\r
+#define PDMIC_DSPR0_OSR_64 (0x1u << 4) /**< \brief (PDMIC_DSPR0) Oversampling ratio is 64 */\r
+#define PDMIC_DSPR0_SCALE_Pos 8\r
+#define PDMIC_DSPR0_SCALE_Msk (0xfu << PDMIC_DSPR0_SCALE_Pos) /**< \brief (PDMIC_DSPR0) Data Scale */\r
+#define PDMIC_DSPR0_SCALE(value) ((PDMIC_DSPR0_SCALE_Msk & ((value) << PDMIC_DSPR0_SCALE_Pos)))\r
+#define PDMIC_DSPR0_SHIFT_Pos 12\r
+#define PDMIC_DSPR0_SHIFT_Msk (0xfu << PDMIC_DSPR0_SHIFT_Pos) /**< \brief (PDMIC_DSPR0) Data Shift */\r
+#define PDMIC_DSPR0_SHIFT(value) ((PDMIC_DSPR0_SHIFT_Msk & ((value) << PDMIC_DSPR0_SHIFT_Pos)))\r
+/* -------- PDMIC_DSPR1 : (PDMIC Offset: 0x5C) DSP Configuration Register 1 -------- */\r
+#define PDMIC_DSPR1_DGAIN_Pos 0\r
+#define PDMIC_DSPR1_DGAIN_Msk (0x7fffu << PDMIC_DSPR1_DGAIN_Pos) /**< \brief (PDMIC_DSPR1) Gain Correction */\r
+#define PDMIC_DSPR1_DGAIN(value) ((PDMIC_DSPR1_DGAIN_Msk & ((value) << PDMIC_DSPR1_DGAIN_Pos)))\r
+#define PDMIC_DSPR1_OFFSET_Pos 16\r
+#define PDMIC_DSPR1_OFFSET_Msk (0xffffu << PDMIC_DSPR1_OFFSET_Pos) /**< \brief (PDMIC_DSPR1) Offset Correction */\r
+#define PDMIC_DSPR1_OFFSET(value) ((PDMIC_DSPR1_OFFSET_Msk & ((value) << PDMIC_DSPR1_OFFSET_Pos)))\r
+/* -------- PDMIC_WPMR : (PDMIC Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define PDMIC_WPMR_WPEN (0x1u << 0) /**< \brief (PDMIC_WPMR) Write Protection Enable */\r
+#define PDMIC_WPMR_WPKEY_Pos 8\r
+#define PDMIC_WPMR_WPKEY_Msk (0xffffffu << PDMIC_WPMR_WPKEY_Pos) /**< \brief (PDMIC_WPMR) Write Protection Key */\r
+#define PDMIC_WPMR_WPKEY(value) ((PDMIC_WPMR_WPKEY_Msk & ((value) << PDMIC_WPMR_WPKEY_Pos)))\r
+#define PDMIC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (PDMIC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- PDMIC_WPSR : (PDMIC Offset: 0xE8) Write Protection Status Register -------- */\r
+#define PDMIC_WPSR_WPVS (0x1u << 0) /**< \brief (PDMIC_WPSR) Write Protection Violation Status */\r
+#define PDMIC_WPSR_WPVSRC_Pos 8\r
+#define PDMIC_WPSR_WPVSRC_Msk (0xffffu << PDMIC_WPSR_WPVSRC_Pos) /**< \brief (PDMIC_WPSR) Write Protection Violation Source */\r
+/* -------- PDMIC_VERSION : (PDMIC Offset: 0xFC) Version Register -------- */\r
+#define PDMIC_VERSION_VERSION_Pos 0\r
+#define PDMIC_VERSION_VERSION_Msk (0xfffu << PDMIC_VERSION_VERSION_Pos) /**< \brief (PDMIC_VERSION) Version of the Hardware Module */\r
+#define PDMIC_VERSION_MFN_Pos 16\r
+#define PDMIC_VERSION_MFN_Msk (0x7u << PDMIC_VERSION_MFN_Pos) /**< \brief (PDMIC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_PDMIC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_PIO_COMPONENT_\r
+#define _SAMA5D2_PIO_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_PIO Parallel Input/Output Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief PioIo_group hardware registers */\r
+typedef struct {\r
+ __IO uint32_t PIO_MSKR; /**< \brief (PioIo_group Offset: 0x0) PIO Mask Register */\r
+ __IO uint32_t PIO_CFGR; /**< \brief (PioIo_group Offset: 0x4) PIO Configuration Register */\r
+ __I uint32_t PIO_PDSR; /**< \brief (PioIo_group Offset: 0x8) PIO Pin Data Status Register */\r
+ __I uint32_t PIO_LOCKSR; /**< \brief (PioIo_group Offset: 0xC) PIO Lock Status Register */\r
+ __O uint32_t PIO_SODR; /**< \brief (PioIo_group Offset: 0x10) PIO Set Output Data Register */\r
+ __O uint32_t PIO_CODR; /**< \brief (PioIo_group Offset: 0x14) PIO Clear Output Data Register */\r
+ __IO uint32_t PIO_ODSR; /**< \brief (PioIo_group Offset: 0x18) PIO Output Data Status Register */\r
+ __I uint32_t Reserved1[1];\r
+ __O uint32_t PIO_IER; /**< \brief (PioIo_group Offset: 0x20) PIO Interrupt Enable Register */\r
+ __O uint32_t PIO_IDR; /**< \brief (PioIo_group Offset: 0x24) PIO Interrupt Disable Register */\r
+ __I uint32_t PIO_IMR; /**< \brief (PioIo_group Offset: 0x28) PIO Interrupt Mask Register */\r
+ __I uint32_t PIO_ISR; /**< \brief (PioIo_group Offset: 0x2C) PIO Interrupt Status Register */\r
+ __I uint32_t Reserved2[3];\r
+ __O uint32_t PIO_IOFR; /**< \brief (PioIo_group Offset: 0x3C) PIO I/O Freeze Register */\r
+} PioIo_group;\r
+/** \brief PioPio_ hardware registers */\r
+typedef struct {\r
+ __IO uint32_t S_PIO_MSKR; /**< \brief (PioPio_ Offset: 0x0) Secure PIO Mask Register */\r
+ __IO uint32_t S_PIO_CFGR; /**< \brief (PioPio_ Offset: 0x4) Secure PIO Configuration Register */\r
+ __I uint32_t S_PIO_PDSR; /**< \brief (PioPio_ Offset: 0x8) Secure PIO Pin Data Status Register */\r
+ __I uint32_t S_PIO_LOCKSR; /**< \brief (PioPio_ Offset: 0xC) Secure PIO Lock Status Register */\r
+ __O uint32_t S_PIO_SODR; /**< \brief (PioPio_ Offset: 0x10) Secure PIO Set Output Data Register */\r
+ __O uint32_t S_PIO_CODR; /**< \brief (PioPio_ Offset: 0x14) Secure PIO Clear Output Data Register */\r
+ __IO uint32_t S_PIO_ODSR; /**< \brief (PioPio_ Offset: 0x18) Secure PIO Output Data Status Register */\r
+ __I uint32_t Reserved3[1];\r
+ __O uint32_t S_PIO_IER; /**< \brief (PioPio_ Offset: 0x20) Secure PIO Interrupt Enable Register */\r
+ __O uint32_t S_PIO_IDR; /**< \brief (PioPio_ Offset: 0x24) Secure PIO Interrupt Disable Register */\r
+ __I uint32_t S_PIO_IMR; /**< \brief (PioPio_ Offset: 0x28) Secure PIO Interrupt Mask Register */\r
+ __I uint32_t S_PIO_ISR; /**< \brief (PioPio_ Offset: 0x2C) Secure PIO Interrupt Status Register */\r
+ __O uint32_t S_PIO_SIONR; /**< \brief (PioPio_ Offset: 0x30) Secure PIO Set I/O Non-Secure Register */\r
+ __O uint32_t S_PIO_SIOSR; /**< \brief (PioPio_ Offset: 0x34) Secure PIO Set I/O Secure Register */\r
+ __I uint32_t S_PIO_IOSSR; /**< \brief (PioPio_ Offset: 0x38) Secure PIO I/O Security Status Register */\r
+ __O uint32_t S_PIO_IOFR; /**< \brief (PioPio_ Offset: 0x3C) Secure PIO I/O Freeze Register */\r
+} PioPio_;\r
+/** \brief Pio hardware registers */\r
+#define PIOIO_GROUP_NUMBER 4\r
+#define PIOPIO__NUMBER 4\r
+typedef struct {\r
+ PioIo_group PIO_IO_GROUP[PIOIO_GROUP_NUMBER]; /**< \brief (Pio Offset: 0x0) io_group = 0 .. 3 */\r
+ __I uint32_t Reserved1[312];\r
+ __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x5E0) PIO Write Protection Mode Register */\r
+ __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x5E4) PIO Write Protection Status Register */\r
+ __I uint32_t Reserved2[5];\r
+ __I uint32_t PIO_VERSION; /**< \brief (Pio Offset: 0x5FC) Version Register */\r
+ __I uint32_t Reserved3[640];\r
+ PioPio_ PIO_PIO_[PIOPIO__NUMBER]; /**< \brief (Pio Offset: 0x1000) io_group = 0 .. 3 */\r
+ __I uint32_t Reserved4[256];\r
+ __IO uint32_t S_PIO_SCDR; /**< \brief (Pio Offset: 0x1500) Secure PIO Slow Clock Divider Debouncing Register */\r
+ __I uint32_t Reserved5[55];\r
+ __IO uint32_t S_PIO_WPMR; /**< \brief (Pio Offset: 0x15E0) Secure PIO Write Protection Mode Register */\r
+ __I uint32_t S_PIO_WPSR; /**< \brief (Pio Offset: 0x15E4) Secure PIO Write Protection Status Register */\r
+} Pio;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PIO_MSKR : (PIO Offset: N/A) PIO Mask Register -------- */\r
+#define PIO_MSKR_MSK0 (0x1u << 0) /**< \brief (PIO_MSKR) PIO Line 0 Mask */\r
+#define PIO_MSKR_MSK0_DISABLED (0x0u << 0) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK0_ENABLED (0x1u << 0) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK1 (0x1u << 1) /**< \brief (PIO_MSKR) PIO Line 1 Mask */\r
+#define PIO_MSKR_MSK1_DISABLED (0x0u << 1) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK1_ENABLED (0x1u << 1) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK2 (0x1u << 2) /**< \brief (PIO_MSKR) PIO Line 2 Mask */\r
+#define PIO_MSKR_MSK2_DISABLED (0x0u << 2) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK2_ENABLED (0x1u << 2) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK3 (0x1u << 3) /**< \brief (PIO_MSKR) PIO Line 3 Mask */\r
+#define PIO_MSKR_MSK3_DISABLED (0x0u << 3) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK3_ENABLED (0x1u << 3) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK4 (0x1u << 4) /**< \brief (PIO_MSKR) PIO Line 4 Mask */\r
+#define PIO_MSKR_MSK4_DISABLED (0x0u << 4) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK4_ENABLED (0x1u << 4) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK5 (0x1u << 5) /**< \brief (PIO_MSKR) PIO Line 5 Mask */\r
+#define PIO_MSKR_MSK5_DISABLED (0x0u << 5) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK5_ENABLED (0x1u << 5) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK6 (0x1u << 6) /**< \brief (PIO_MSKR) PIO Line 6 Mask */\r
+#define PIO_MSKR_MSK6_DISABLED (0x0u << 6) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK6_ENABLED (0x1u << 6) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK7 (0x1u << 7) /**< \brief (PIO_MSKR) PIO Line 7 Mask */\r
+#define PIO_MSKR_MSK7_DISABLED (0x0u << 7) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK7_ENABLED (0x1u << 7) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK8 (0x1u << 8) /**< \brief (PIO_MSKR) PIO Line 8 Mask */\r
+#define PIO_MSKR_MSK8_DISABLED (0x0u << 8) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK8_ENABLED (0x1u << 8) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK9 (0x1u << 9) /**< \brief (PIO_MSKR) PIO Line 9 Mask */\r
+#define PIO_MSKR_MSK9_DISABLED (0x0u << 9) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK9_ENABLED (0x1u << 9) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK10 (0x1u << 10) /**< \brief (PIO_MSKR) PIO Line 10 Mask */\r
+#define PIO_MSKR_MSK10_DISABLED (0x0u << 10) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK10_ENABLED (0x1u << 10) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK11 (0x1u << 11) /**< \brief (PIO_MSKR) PIO Line 11 Mask */\r
+#define PIO_MSKR_MSK11_DISABLED (0x0u << 11) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK11_ENABLED (0x1u << 11) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK12 (0x1u << 12) /**< \brief (PIO_MSKR) PIO Line 12 Mask */\r
+#define PIO_MSKR_MSK12_DISABLED (0x0u << 12) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK12_ENABLED (0x1u << 12) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK13 (0x1u << 13) /**< \brief (PIO_MSKR) PIO Line 13 Mask */\r
+#define PIO_MSKR_MSK13_DISABLED (0x0u << 13) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK13_ENABLED (0x1u << 13) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK14 (0x1u << 14) /**< \brief (PIO_MSKR) PIO Line 14 Mask */\r
+#define PIO_MSKR_MSK14_DISABLED (0x0u << 14) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK14_ENABLED (0x1u << 14) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK15 (0x1u << 15) /**< \brief (PIO_MSKR) PIO Line 15 Mask */\r
+#define PIO_MSKR_MSK15_DISABLED (0x0u << 15) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK15_ENABLED (0x1u << 15) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK16 (0x1u << 16) /**< \brief (PIO_MSKR) PIO Line 16 Mask */\r
+#define PIO_MSKR_MSK16_DISABLED (0x0u << 16) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK16_ENABLED (0x1u << 16) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK17 (0x1u << 17) /**< \brief (PIO_MSKR) PIO Line 17 Mask */\r
+#define PIO_MSKR_MSK17_DISABLED (0x0u << 17) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK17_ENABLED (0x1u << 17) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK18 (0x1u << 18) /**< \brief (PIO_MSKR) PIO Line 18 Mask */\r
+#define PIO_MSKR_MSK18_DISABLED (0x0u << 18) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK18_ENABLED (0x1u << 18) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK19 (0x1u << 19) /**< \brief (PIO_MSKR) PIO Line 19 Mask */\r
+#define PIO_MSKR_MSK19_DISABLED (0x0u << 19) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK19_ENABLED (0x1u << 19) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK20 (0x1u << 20) /**< \brief (PIO_MSKR) PIO Line 20 Mask */\r
+#define PIO_MSKR_MSK20_DISABLED (0x0u << 20) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK20_ENABLED (0x1u << 20) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK21 (0x1u << 21) /**< \brief (PIO_MSKR) PIO Line 21 Mask */\r
+#define PIO_MSKR_MSK21_DISABLED (0x0u << 21) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK21_ENABLED (0x1u << 21) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK22 (0x1u << 22) /**< \brief (PIO_MSKR) PIO Line 22 Mask */\r
+#define PIO_MSKR_MSK22_DISABLED (0x0u << 22) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK22_ENABLED (0x1u << 22) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK23 (0x1u << 23) /**< \brief (PIO_MSKR) PIO Line 23 Mask */\r
+#define PIO_MSKR_MSK23_DISABLED (0x0u << 23) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK23_ENABLED (0x1u << 23) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK24 (0x1u << 24) /**< \brief (PIO_MSKR) PIO Line 24 Mask */\r
+#define PIO_MSKR_MSK24_DISABLED (0x0u << 24) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK24_ENABLED (0x1u << 24) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK25 (0x1u << 25) /**< \brief (PIO_MSKR) PIO Line 25 Mask */\r
+#define PIO_MSKR_MSK25_DISABLED (0x0u << 25) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK25_ENABLED (0x1u << 25) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK26 (0x1u << 26) /**< \brief (PIO_MSKR) PIO Line 26 Mask */\r
+#define PIO_MSKR_MSK26_DISABLED (0x0u << 26) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK26_ENABLED (0x1u << 26) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK27 (0x1u << 27) /**< \brief (PIO_MSKR) PIO Line 27 Mask */\r
+#define PIO_MSKR_MSK27_DISABLED (0x0u << 27) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK27_ENABLED (0x1u << 27) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK28 (0x1u << 28) /**< \brief (PIO_MSKR) PIO Line 28 Mask */\r
+#define PIO_MSKR_MSK28_DISABLED (0x0u << 28) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK28_ENABLED (0x1u << 28) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK29 (0x1u << 29) /**< \brief (PIO_MSKR) PIO Line 29 Mask */\r
+#define PIO_MSKR_MSK29_DISABLED (0x0u << 29) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK29_ENABLED (0x1u << 29) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK30 (0x1u << 30) /**< \brief (PIO_MSKR) PIO Line 30 Mask */\r
+#define PIO_MSKR_MSK30_DISABLED (0x0u << 30) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK30_ENABLED (0x1u << 30) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK31 (0x1u << 31) /**< \brief (PIO_MSKR) PIO Line 31 Mask */\r
+#define PIO_MSKR_MSK31_DISABLED (0x0u << 31) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define PIO_MSKR_MSK31_ENABLED (0x1u << 31) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */\r
+/* -------- PIO_CFGR : (PIO Offset: N/A) PIO Configuration Register -------- */\r
+#define PIO_CFGR_FUNC_Pos 0\r
+#define PIO_CFGR_FUNC_Msk (0x7u << PIO_CFGR_FUNC_Pos) /**< \brief (PIO_CFGR) I/O Line Function */\r
+#define PIO_CFGR_FUNC(value) ((PIO_CFGR_FUNC_Msk & ((value) << PIO_CFGR_FUNC_Pos)))\r
+#define PIO_CFGR_FUNC_GPIO (0x0u << 0) /**< \brief (PIO_CFGR) Select the PIO mode for the selected I/O lines. */\r
+#define PIO_CFGR_FUNC_PERIPH_A (0x1u << 0) /**< \brief (PIO_CFGR) Select the peripheral A for the selected I/O lines. */\r
+#define PIO_CFGR_FUNC_PERIPH_B (0x2u << 0) /**< \brief (PIO_CFGR) Select the peripheral B for the selected I/O lines. */\r
+#define PIO_CFGR_FUNC_PERIPH_C (0x3u << 0) /**< \brief (PIO_CFGR) Select the peripheral C for the selected I/O lines. */\r
+#define PIO_CFGR_FUNC_PERIPH_D (0x4u << 0) /**< \brief (PIO_CFGR) Select the peripheral D for the selected I/O lines. */\r
+#define PIO_CFGR_FUNC_PERIPH_E (0x5u << 0) /**< \brief (PIO_CFGR) Select the peripheral E for the selected I/O lines. */\r
+#define PIO_CFGR_FUNC_PERIPH_F (0x6u << 0) /**< \brief (PIO_CFGR) Select the peripheral F for the selected I/O lines. */\r
+#define PIO_CFGR_FUNC_PERIPH_G (0x7u << 0) /**< \brief (PIO_CFGR) Select the peripheral G for the selected I/O lines. */\r
+#define PIO_CFGR_DIR (0x1u << 8) /**< \brief (PIO_CFGR) Direction */\r
+#define PIO_CFGR_DIR_INPUT (0x0u << 8) /**< \brief (PIO_CFGR) The selected I/O lines are pure inputs. */\r
+#define PIO_CFGR_DIR_OUTPUT (0x1u << 8) /**< \brief (PIO_CFGR) The selected I/O lines are enabled in output. */\r
+#define PIO_CFGR_PUEN (0x1u << 9) /**< \brief (PIO_CFGR) Pull-Up Enable */\r
+#define PIO_CFGR_PUEN_DISABLED (0x0u << 9) /**< \brief (PIO_CFGR) Pull-Up is disabled for the selected I/O lines. */\r
+#define PIO_CFGR_PUEN_ENABLED (0x1u << 9) /**< \brief (PIO_CFGR) Pull-Up is enabled for the selected I/O lines. */\r
+#define PIO_CFGR_PDEN (0x1u << 10) /**< \brief (PIO_CFGR) Pull-Down Enable */\r
+#define PIO_CFGR_PDEN_DISABLED (0x0u << 10) /**< \brief (PIO_CFGR) Pull-Down is disabled for the selected I/O lines. */\r
+#define PIO_CFGR_PDEN_ENABLED (0x1u << 10) /**< \brief (PIO_CFGR) Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1). */\r
+#define PIO_CFGR_IFEN (0x1u << 12) /**< \brief (PIO_CFGR) Input Filter Enable */\r
+#define PIO_CFGR_IFEN_DISABLED (0x0u << 12) /**< \brief (PIO_CFGR) The input filter is disabled for the selected I/O lines. */\r
+#define PIO_CFGR_IFEN_ENABLED (0x1u << 12) /**< \brief (PIO_CFGR) The input filter is enabled for the selected I/O lines. */\r
+#define PIO_CFGR_IFSCEN (0x1u << 13) /**< \brief (PIO_CFGR) Input Filter Slow Clock Enable */\r
+#define PIO_CFGR_IFSCEN_DISABLED (0x0u << 13) /**< \brief (PIO_CFGR) The glitch filter is able to filter glitches with a duration < tmck/2 for the selected I/O lines. */\r
+#define PIO_CFGR_IFSCEN_ENABLED (0x1u << 13) /**< \brief (PIO_CFGR) The debouncing filter is able to filter pulses with a duration < tdiv_slck/2 for the selected I/O lines. */\r
+#define PIO_CFGR_OPD (0x1u << 14) /**< \brief (PIO_CFGR) Open-Drain */\r
+#define PIO_CFGR_OPD_DISABLED (0x0u << 14) /**< \brief (PIO_CFGR) The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level. */\r
+#define PIO_CFGR_OPD_ENABLED (0x1u << 14) /**< \brief (PIO_CFGR) The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only. */\r
+#define PIO_CFGR_SCHMITT (0x1u << 15) /**< \brief (PIO_CFGR) Schmitt Trigger */\r
+#define PIO_CFGR_SCHMITT_ENABLED (0x0u << 15) /**< \brief (PIO_CFGR) Schmitt trigger is enabled for the selected I/O lines. */\r
+#define PIO_CFGR_SCHMITT_DISABLED (0x1u << 15) /**< \brief (PIO_CFGR) Schmitt trigger is disabled for the selected I/O lines. */\r
+#define PIO_CFGR_DRVSTR_Pos 16\r
+#define PIO_CFGR_DRVSTR_Msk (0x3u << PIO_CFGR_DRVSTR_Pos) /**< \brief (PIO_CFGR) Drive Strength */\r
+#define PIO_CFGR_DRVSTR(value) ((PIO_CFGR_DRVSTR_Msk & ((value) << PIO_CFGR_DRVSTR_Pos)))\r
+#define PIO_CFGR_DRVSTR_LO (0x0u << 16) /**< \brief (PIO_CFGR) Low drive */\r
+#define PIO_CFGR_DRVSTR_ME (0x2u << 16) /**< \brief (PIO_CFGR) Medium drive */\r
+#define PIO_CFGR_DRVSTR_HI (0x3u << 16) /**< \brief (PIO_CFGR) High drive */\r
+#define PIO_CFGR_EVTSEL_Pos 24\r
+#define PIO_CFGR_EVTSEL_Msk (0x7u << PIO_CFGR_EVTSEL_Pos) /**< \brief (PIO_CFGR) Event Selection */\r
+#define PIO_CFGR_EVTSEL(value) ((PIO_CFGR_EVTSEL_Msk & ((value) << PIO_CFGR_EVTSEL_Pos)))\r
+#define PIO_CFGR_EVTSEL_FALLING (0x0u << 24) /**< \brief (PIO_CFGR) Event detection on input falling edge */\r
+#define PIO_CFGR_EVTSEL_RISING (0x1u << 24) /**< \brief (PIO_CFGR) Event detection on input rising edge */\r
+#define PIO_CFGR_EVTSEL_BOTH (0x2u << 24) /**< \brief (PIO_CFGR) Event detection on input both edge */\r
+#define PIO_CFGR_EVTSEL_LOW (0x3u << 24) /**< \brief (PIO_CFGR) Event detection on low level input */\r
+#define PIO_CFGR_EVTSEL_HIGH (0x4u << 24) /**< \brief (PIO_CFGR) Event detection on high level input */\r
+#define PIO_CFGR_PCFS (0x1u << 29) /**< \brief (PIO_CFGR) Physical Configuration Freeze Status */\r
+#define PIO_CFGR_PCFS_NOT_FROZEN (0x0u << 29) /**< \brief (PIO_CFGR) The fields are not frozen and can be written for this I/O line. */\r
+#define PIO_CFGR_PCFS_FROZEN (0x1u << 29) /**< \brief (PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */\r
+#define PIO_CFGR_ICFS (0x1u << 30) /**< \brief (PIO_CFGR) Interrupt Configuration Freeze Status */\r
+#define PIO_CFGR_ICFS_NOT_FROZEN (0x0u << 30) /**< \brief (PIO_CFGR) The fields are not frozen and can be written for this I/O line. */\r
+#define PIO_CFGR_ICFS_FROZEN (0x1u << 30) /**< \brief (PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */\r
+/* -------- PIO_PDSR : (PIO Offset: N/A) PIO Pin Data Status Register -------- */\r
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Input Data Status */\r
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Input Data Status */\r
+/* -------- PIO_LOCKSR : (PIO Offset: N/A) PIO Lock Status Register -------- */\r
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */\r
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */\r
+/* -------- PIO_SODR : (PIO Offset: N/A) PIO Set Output Data Register -------- */\r
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */\r
+/* -------- PIO_CODR : (PIO Offset: N/A) PIO Clear Output Data Register -------- */\r
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */\r
+/* -------- PIO_ODSR : (PIO Offset: N/A) PIO Output Data Status Register -------- */\r
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */\r
+/* -------- PIO_IER : (PIO Offset: N/A) PIO Interrupt Enable Register -------- */\r
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+/* -------- PIO_IDR : (PIO Offset: N/A) PIO Interrupt Disable Register -------- */\r
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+/* -------- PIO_IMR : (PIO Offset: N/A) PIO Interrupt Mask Register -------- */\r
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+/* -------- PIO_ISR : (PIO Offset: N/A) PIO Interrupt Status Register -------- */\r
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+/* -------- PIO_IOFR : (PIO Offset: N/A) PIO I/O Freeze Register -------- */\r
+#define PIO_IOFR_FPHY (0x1u << 0) /**< \brief (PIO_IOFR) Freeze Physical Configuration */\r
+#define PIO_IOFR_FINT (0x1u << 1) /**< \brief (PIO_IOFR) Freeze Interrupt Configuration */\r
+#define PIO_IOFR_FRZKEY_Pos 8\r
+#define PIO_IOFR_FRZKEY_Msk (0xffffffu << PIO_IOFR_FRZKEY_Pos) /**< \brief (PIO_IOFR) Freeze Key */\r
+#define PIO_IOFR_FRZKEY(value) ((PIO_IOFR_FRZKEY_Msk & ((value) << PIO_IOFR_FRZKEY_Pos)))\r
+#define PIO_IOFR_FRZKEY_PASSWD (0x494F46u << 8) /**< \brief (PIO_IOFR) Writing any other value in this field aborts the write operation of the WPEN bit. */\r
+/* -------- PIO_WPMR : (PIO Offset: 0x5E0) PIO Write Protection Mode Register -------- */\r
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */\r
+#define PIO_WPMR_WPKEY_Pos 8\r
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */\r
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))\r
+#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */\r
+/* -------- PIO_WPSR : (PIO Offset: 0x5E4) PIO Write Protection Status Register -------- */\r
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */\r
+#define PIO_WPSR_WPVSRC_Pos 8\r
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */\r
+/* -------- PIO_VERSION : (PIO Offset: 0x5FC) Version Register -------- */\r
+#define PIO_VERSION_VERSION_Pos 0\r
+#define PIO_VERSION_VERSION_Msk (0xfffu << PIO_VERSION_VERSION_Pos) /**< \brief (PIO_VERSION) Hardware Module Version */\r
+#define PIO_VERSION_MFN_Pos 16\r
+#define PIO_VERSION_MFN_Msk (0x7u << PIO_VERSION_MFN_Pos) /**< \brief (PIO_VERSION) Metal Fix Number */\r
+/* -------- S_PIO_MSKR : (PIO Offset: N/A) Secure PIO Mask Register -------- */\r
+#define S_PIO_MSKR_MSK0 (0x1u << 0) /**< \brief (S_PIO_MSKR) PIO Line 0 Mask */\r
+#define S_PIO_MSKR_MSK0_DISABLED (0x0u << 0) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK0_ENABLED (0x1u << 0) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK1 (0x1u << 1) /**< \brief (S_PIO_MSKR) PIO Line 1 Mask */\r
+#define S_PIO_MSKR_MSK1_DISABLED (0x0u << 1) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK1_ENABLED (0x1u << 1) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK2 (0x1u << 2) /**< \brief (S_PIO_MSKR) PIO Line 2 Mask */\r
+#define S_PIO_MSKR_MSK2_DISABLED (0x0u << 2) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK2_ENABLED (0x1u << 2) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK3 (0x1u << 3) /**< \brief (S_PIO_MSKR) PIO Line 3 Mask */\r
+#define S_PIO_MSKR_MSK3_DISABLED (0x0u << 3) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK3_ENABLED (0x1u << 3) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK4 (0x1u << 4) /**< \brief (S_PIO_MSKR) PIO Line 4 Mask */\r
+#define S_PIO_MSKR_MSK4_DISABLED (0x0u << 4) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK4_ENABLED (0x1u << 4) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK5 (0x1u << 5) /**< \brief (S_PIO_MSKR) PIO Line 5 Mask */\r
+#define S_PIO_MSKR_MSK5_DISABLED (0x0u << 5) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK5_ENABLED (0x1u << 5) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK6 (0x1u << 6) /**< \brief (S_PIO_MSKR) PIO Line 6 Mask */\r
+#define S_PIO_MSKR_MSK6_DISABLED (0x0u << 6) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK6_ENABLED (0x1u << 6) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK7 (0x1u << 7) /**< \brief (S_PIO_MSKR) PIO Line 7 Mask */\r
+#define S_PIO_MSKR_MSK7_DISABLED (0x0u << 7) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK7_ENABLED (0x1u << 7) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK8 (0x1u << 8) /**< \brief (S_PIO_MSKR) PIO Line 8 Mask */\r
+#define S_PIO_MSKR_MSK8_DISABLED (0x0u << 8) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK8_ENABLED (0x1u << 8) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK9 (0x1u << 9) /**< \brief (S_PIO_MSKR) PIO Line 9 Mask */\r
+#define S_PIO_MSKR_MSK9_DISABLED (0x0u << 9) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK9_ENABLED (0x1u << 9) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK10 (0x1u << 10) /**< \brief (S_PIO_MSKR) PIO Line 10 Mask */\r
+#define S_PIO_MSKR_MSK10_DISABLED (0x0u << 10) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK10_ENABLED (0x1u << 10) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK11 (0x1u << 11) /**< \brief (S_PIO_MSKR) PIO Line 11 Mask */\r
+#define S_PIO_MSKR_MSK11_DISABLED (0x0u << 11) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK11_ENABLED (0x1u << 11) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK12 (0x1u << 12) /**< \brief (S_PIO_MSKR) PIO Line 12 Mask */\r
+#define S_PIO_MSKR_MSK12_DISABLED (0x0u << 12) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK12_ENABLED (0x1u << 12) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK13 (0x1u << 13) /**< \brief (S_PIO_MSKR) PIO Line 13 Mask */\r
+#define S_PIO_MSKR_MSK13_DISABLED (0x0u << 13) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK13_ENABLED (0x1u << 13) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK14 (0x1u << 14) /**< \brief (S_PIO_MSKR) PIO Line 14 Mask */\r
+#define S_PIO_MSKR_MSK14_DISABLED (0x0u << 14) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK14_ENABLED (0x1u << 14) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK15 (0x1u << 15) /**< \brief (S_PIO_MSKR) PIO Line 15 Mask */\r
+#define S_PIO_MSKR_MSK15_DISABLED (0x0u << 15) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK15_ENABLED (0x1u << 15) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK16 (0x1u << 16) /**< \brief (S_PIO_MSKR) PIO Line 16 Mask */\r
+#define S_PIO_MSKR_MSK16_DISABLED (0x0u << 16) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK16_ENABLED (0x1u << 16) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK17 (0x1u << 17) /**< \brief (S_PIO_MSKR) PIO Line 17 Mask */\r
+#define S_PIO_MSKR_MSK17_DISABLED (0x0u << 17) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK17_ENABLED (0x1u << 17) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK18 (0x1u << 18) /**< \brief (S_PIO_MSKR) PIO Line 18 Mask */\r
+#define S_PIO_MSKR_MSK18_DISABLED (0x0u << 18) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK18_ENABLED (0x1u << 18) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK19 (0x1u << 19) /**< \brief (S_PIO_MSKR) PIO Line 19 Mask */\r
+#define S_PIO_MSKR_MSK19_DISABLED (0x0u << 19) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK19_ENABLED (0x1u << 19) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK20 (0x1u << 20) /**< \brief (S_PIO_MSKR) PIO Line 20 Mask */\r
+#define S_PIO_MSKR_MSK20_DISABLED (0x0u << 20) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK20_ENABLED (0x1u << 20) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK21 (0x1u << 21) /**< \brief (S_PIO_MSKR) PIO Line 21 Mask */\r
+#define S_PIO_MSKR_MSK21_DISABLED (0x0u << 21) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK21_ENABLED (0x1u << 21) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK22 (0x1u << 22) /**< \brief (S_PIO_MSKR) PIO Line 22 Mask */\r
+#define S_PIO_MSKR_MSK22_DISABLED (0x0u << 22) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK22_ENABLED (0x1u << 22) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK23 (0x1u << 23) /**< \brief (S_PIO_MSKR) PIO Line 23 Mask */\r
+#define S_PIO_MSKR_MSK23_DISABLED (0x0u << 23) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK23_ENABLED (0x1u << 23) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK24 (0x1u << 24) /**< \brief (S_PIO_MSKR) PIO Line 24 Mask */\r
+#define S_PIO_MSKR_MSK24_DISABLED (0x0u << 24) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK24_ENABLED (0x1u << 24) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK25 (0x1u << 25) /**< \brief (S_PIO_MSKR) PIO Line 25 Mask */\r
+#define S_PIO_MSKR_MSK25_DISABLED (0x0u << 25) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK25_ENABLED (0x1u << 25) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK26 (0x1u << 26) /**< \brief (S_PIO_MSKR) PIO Line 26 Mask */\r
+#define S_PIO_MSKR_MSK26_DISABLED (0x0u << 26) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK26_ENABLED (0x1u << 26) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK27 (0x1u << 27) /**< \brief (S_PIO_MSKR) PIO Line 27 Mask */\r
+#define S_PIO_MSKR_MSK27_DISABLED (0x0u << 27) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK27_ENABLED (0x1u << 27) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK28 (0x1u << 28) /**< \brief (S_PIO_MSKR) PIO Line 28 Mask */\r
+#define S_PIO_MSKR_MSK28_DISABLED (0x0u << 28) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK28_ENABLED (0x1u << 28) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK29 (0x1u << 29) /**< \brief (S_PIO_MSKR) PIO Line 29 Mask */\r
+#define S_PIO_MSKR_MSK29_DISABLED (0x0u << 29) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK29_ENABLED (0x1u << 29) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK30 (0x1u << 30) /**< \brief (S_PIO_MSKR) PIO Line 30 Mask */\r
+#define S_PIO_MSKR_MSK30_DISABLED (0x0u << 30) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK30_ENABLED (0x1u << 30) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK31 (0x1u << 31) /**< \brief (S_PIO_MSKR) PIO Line 31 Mask */\r
+#define S_PIO_MSKR_MSK31_DISABLED (0x0u << 31) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */\r
+#define S_PIO_MSKR_MSK31_ENABLED (0x1u << 31) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */\r
+/* -------- S_PIO_CFGR : (PIO Offset: N/A) Secure PIO Configuration Register -------- */\r
+#define S_PIO_CFGR_FUNC_Pos 0\r
+#define S_PIO_CFGR_FUNC_Msk (0x7u << S_PIO_CFGR_FUNC_Pos) /**< \brief (S_PIO_CFGR) I/O Line Function */\r
+#define S_PIO_CFGR_FUNC(value) ((S_PIO_CFGR_FUNC_Msk & ((value) << S_PIO_CFGR_FUNC_Pos)))\r
+#define S_PIO_CFGR_FUNC_GPIO (0x0u << 0) /**< \brief (S_PIO_CFGR) Select the PIO mode for the selected I/O lines. */\r
+#define S_PIO_CFGR_FUNC_PERIPH_A (0x1u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral A for the selected I/O lines. */\r
+#define S_PIO_CFGR_FUNC_PERIPH_B (0x2u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral B for the selected I/O lines. */\r
+#define S_PIO_CFGR_FUNC_PERIPH_C (0x3u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral C for the selected I/O lines. */\r
+#define S_PIO_CFGR_FUNC_PERIPH_D (0x4u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral D for the selected I/O lines. */\r
+#define S_PIO_CFGR_FUNC_PERIPH_E (0x5u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral E for the selected I/O lines. */\r
+#define S_PIO_CFGR_FUNC_PERIPH_F (0x6u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral F for the selected I/O lines. */\r
+#define S_PIO_CFGR_FUNC_PERIPH_G (0x7u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral G for the selected I/O lines. */\r
+#define S_PIO_CFGR_DIR (0x1u << 8) /**< \brief (S_PIO_CFGR) Direction */\r
+#define S_PIO_CFGR_DIR_INPUT (0x0u << 8) /**< \brief (S_PIO_CFGR) The selected I/O lines are pure inputs. */\r
+#define S_PIO_CFGR_DIR_OUTPUT (0x1u << 8) /**< \brief (S_PIO_CFGR) The selected I/O lines are enabled in output. */\r
+#define S_PIO_CFGR_PUEN (0x1u << 9) /**< \brief (S_PIO_CFGR) Pull-Up Enable */\r
+#define S_PIO_CFGR_PUEN_DISABLED (0x0u << 9) /**< \brief (S_PIO_CFGR) Pull-Up is disabled for the selected I/O lines. */\r
+#define S_PIO_CFGR_PUEN_ENABLED (0x1u << 9) /**< \brief (S_PIO_CFGR) Pull-Up is enabled for the selected I/O lines. */\r
+#define S_PIO_CFGR_PDEN (0x1u << 10) /**< \brief (S_PIO_CFGR) Pull-Down Enable */\r
+#define S_PIO_CFGR_PDEN_DISABLED (0x0u << 10) /**< \brief (S_PIO_CFGR) Pull-Down is disabled for the selected I/O lines. */\r
+#define S_PIO_CFGR_PDEN_ENABLED (0x1u << 10) /**< \brief (S_PIO_CFGR) Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1). */\r
+#define S_PIO_CFGR_IFEN (0x1u << 12) /**< \brief (S_PIO_CFGR) Input Filter Enable */\r
+#define S_PIO_CFGR_IFEN_DISABLED (0x0u << 12) /**< \brief (S_PIO_CFGR) The input filter is disabled for the selected I/O lines. */\r
+#define S_PIO_CFGR_IFEN_ENABLED (0x1u << 12) /**< \brief (S_PIO_CFGR) The input filter is enabled for the selected I/O lines. */\r
+#define S_PIO_CFGR_IFSCEN (0x1u << 13) /**< \brief (S_PIO_CFGR) Input Filter Slow Clock Enable */\r
+#define S_PIO_CFGR_OPD (0x1u << 14) /**< \brief (S_PIO_CFGR) Open-Drain */\r
+#define S_PIO_CFGR_OPD_DISABLED (0x0u << 14) /**< \brief (S_PIO_CFGR) The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level. */\r
+#define S_PIO_CFGR_OPD_ENABLED (0x1u << 14) /**< \brief (S_PIO_CFGR) The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only. */\r
+#define S_PIO_CFGR_SCHMITT (0x1u << 15) /**< \brief (S_PIO_CFGR) Schmitt Trigger */\r
+#define S_PIO_CFGR_SCHMITT_ENABLED (0x0u << 15) /**< \brief (S_PIO_CFGR) Schmitt trigger is enabled for the selected I/O lines. */\r
+#define S_PIO_CFGR_SCHMITT_DISABLED (0x1u << 15) /**< \brief (S_PIO_CFGR) Schmitt trigger is disabled for the selected I/O lines. */\r
+#define S_PIO_CFGR_DRVSTR_Pos 16\r
+#define S_PIO_CFGR_DRVSTR_Msk (0x3u << S_PIO_CFGR_DRVSTR_Pos) /**< \brief (S_PIO_CFGR) */\r
+#define S_PIO_CFGR_DRVSTR(value) ((S_PIO_CFGR_DRVSTR_Msk & ((value) << S_PIO_CFGR_DRVSTR_Pos)))\r
+#define S_PIO_CFGR_EVTSEL_Pos 24\r
+#define S_PIO_CFGR_EVTSEL_Msk (0x7u << S_PIO_CFGR_EVTSEL_Pos) /**< \brief (S_PIO_CFGR) Event Selection */\r
+#define S_PIO_CFGR_EVTSEL(value) ((S_PIO_CFGR_EVTSEL_Msk & ((value) << S_PIO_CFGR_EVTSEL_Pos)))\r
+#define S_PIO_CFGR_EVTSEL_FALLING (0x0u << 24) /**< \brief (S_PIO_CFGR) Event detection on input falling edge */\r
+#define S_PIO_CFGR_EVTSEL_RISING (0x1u << 24) /**< \brief (S_PIO_CFGR) Event detection on input rising edge */\r
+#define S_PIO_CFGR_EVTSEL_BOTH (0x2u << 24) /**< \brief (S_PIO_CFGR) Event detection on input both edge */\r
+#define S_PIO_CFGR_EVTSEL_LOW (0x3u << 24) /**< \brief (S_PIO_CFGR) Event detection on low level input */\r
+#define S_PIO_CFGR_EVTSEL_HIGH (0x4u << 24) /**< \brief (S_PIO_CFGR) Event detection on high level input */\r
+#define S_PIO_CFGR_PCFS (0x1u << 29) /**< \brief (S_PIO_CFGR) Physical Configuration Freeze Status */\r
+#define S_PIO_CFGR_PCFS_NOT_FROZEN (0x0u << 29) /**< \brief (S_PIO_CFGR) The fields are not frozen and can be written for this I/O line. */\r
+#define S_PIO_CFGR_PCFS_FROZEN (0x1u << 29) /**< \brief (S_PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */\r
+#define S_PIO_CFGR_ICFS (0x1u << 30) /**< \brief (S_PIO_CFGR) Interrupt Configuration Freeze Status */\r
+#define S_PIO_CFGR_ICFS_NOT_FROZEN (0x0u << 30) /**< \brief (S_PIO_CFGR) The fields are not frozen and can be written for this I/O line. */\r
+#define S_PIO_CFGR_ICFS_FROZEN (0x1u << 30) /**< \brief (S_PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */\r
+/* -------- S_PIO_PDSR : (PIO Offset: N/A) Secure PIO Pin Data Status Register -------- */\r
+#define S_PIO_PDSR_P0 (0x1u << 0) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P1 (0x1u << 1) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P2 (0x1u << 2) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P3 (0x1u << 3) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P4 (0x1u << 4) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P5 (0x1u << 5) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P6 (0x1u << 6) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P7 (0x1u << 7) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P8 (0x1u << 8) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P9 (0x1u << 9) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P10 (0x1u << 10) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P11 (0x1u << 11) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P12 (0x1u << 12) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P13 (0x1u << 13) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P14 (0x1u << 14) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P15 (0x1u << 15) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P16 (0x1u << 16) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P17 (0x1u << 17) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P18 (0x1u << 18) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P19 (0x1u << 19) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P20 (0x1u << 20) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P21 (0x1u << 21) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P22 (0x1u << 22) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P23 (0x1u << 23) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P24 (0x1u << 24) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P25 (0x1u << 25) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P26 (0x1u << 26) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P27 (0x1u << 27) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P28 (0x1u << 28) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P29 (0x1u << 29) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P30 (0x1u << 30) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+#define S_PIO_PDSR_P31 (0x1u << 31) /**< \brief (S_PIO_PDSR) Input Data Status */\r
+/* -------- S_PIO_SODR : (PIO Offset: N/A) Secure PIO Set Output Data Register -------- */\r
+#define S_PIO_SODR_P0 (0x1u << 0) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P1 (0x1u << 1) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P2 (0x1u << 2) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P3 (0x1u << 3) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P4 (0x1u << 4) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P5 (0x1u << 5) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P6 (0x1u << 6) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P7 (0x1u << 7) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P8 (0x1u << 8) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P9 (0x1u << 9) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P10 (0x1u << 10) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P11 (0x1u << 11) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P12 (0x1u << 12) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P13 (0x1u << 13) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P14 (0x1u << 14) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P15 (0x1u << 15) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P16 (0x1u << 16) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P17 (0x1u << 17) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P18 (0x1u << 18) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P19 (0x1u << 19) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P20 (0x1u << 20) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P21 (0x1u << 21) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P22 (0x1u << 22) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P23 (0x1u << 23) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P24 (0x1u << 24) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P25 (0x1u << 25) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P26 (0x1u << 26) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P27 (0x1u << 27) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P28 (0x1u << 28) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P29 (0x1u << 29) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P30 (0x1u << 30) /**< \brief (S_PIO_SODR) Set Output Data */\r
+#define S_PIO_SODR_P31 (0x1u << 31) /**< \brief (S_PIO_SODR) Set Output Data */\r
+/* -------- S_PIO_CODR : (PIO Offset: N/A) Secure PIO Clear Output Data Register -------- */\r
+#define S_PIO_CODR_P0 (0x1u << 0) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P1 (0x1u << 1) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P2 (0x1u << 2) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P3 (0x1u << 3) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P4 (0x1u << 4) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P5 (0x1u << 5) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P6 (0x1u << 6) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P7 (0x1u << 7) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P8 (0x1u << 8) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P9 (0x1u << 9) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P10 (0x1u << 10) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P11 (0x1u << 11) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P12 (0x1u << 12) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P13 (0x1u << 13) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P14 (0x1u << 14) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P15 (0x1u << 15) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P16 (0x1u << 16) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P17 (0x1u << 17) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P18 (0x1u << 18) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P19 (0x1u << 19) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P20 (0x1u << 20) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P21 (0x1u << 21) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P22 (0x1u << 22) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P23 (0x1u << 23) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P24 (0x1u << 24) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P25 (0x1u << 25) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P26 (0x1u << 26) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P27 (0x1u << 27) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P28 (0x1u << 28) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P29 (0x1u << 29) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P30 (0x1u << 30) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+#define S_PIO_CODR_P31 (0x1u << 31) /**< \brief (S_PIO_CODR) Clear Output Data */\r
+/* -------- S_PIO_ODSR : (PIO Offset: N/A) Secure PIO Output Data Status Register -------- */\r
+#define S_PIO_ODSR_P0 (0x1u << 0) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P1 (0x1u << 1) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P2 (0x1u << 2) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P3 (0x1u << 3) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P4 (0x1u << 4) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P5 (0x1u << 5) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P6 (0x1u << 6) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P7 (0x1u << 7) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P8 (0x1u << 8) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P9 (0x1u << 9) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P10 (0x1u << 10) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P11 (0x1u << 11) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P12 (0x1u << 12) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P13 (0x1u << 13) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P14 (0x1u << 14) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P15 (0x1u << 15) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P16 (0x1u << 16) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P17 (0x1u << 17) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P18 (0x1u << 18) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P19 (0x1u << 19) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P20 (0x1u << 20) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P21 (0x1u << 21) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P22 (0x1u << 22) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P23 (0x1u << 23) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P24 (0x1u << 24) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P25 (0x1u << 25) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P26 (0x1u << 26) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P27 (0x1u << 27) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P28 (0x1u << 28) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P29 (0x1u << 29) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P30 (0x1u << 30) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+#define S_PIO_ODSR_P31 (0x1u << 31) /**< \brief (S_PIO_ODSR) Output Data Status */\r
+/* -------- S_PIO_IER : (PIO Offset: N/A) Secure PIO Interrupt Enable Register -------- */\r
+#define S_PIO_IER_P0 (0x1u << 0) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P1 (0x1u << 1) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P2 (0x1u << 2) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P3 (0x1u << 3) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P4 (0x1u << 4) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P5 (0x1u << 5) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P6 (0x1u << 6) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P7 (0x1u << 7) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P8 (0x1u << 8) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P9 (0x1u << 9) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P10 (0x1u << 10) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P11 (0x1u << 11) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P12 (0x1u << 12) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P13 (0x1u << 13) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P14 (0x1u << 14) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P15 (0x1u << 15) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P16 (0x1u << 16) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P17 (0x1u << 17) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P18 (0x1u << 18) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P19 (0x1u << 19) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P20 (0x1u << 20) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P21 (0x1u << 21) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P22 (0x1u << 22) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P23 (0x1u << 23) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P24 (0x1u << 24) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P25 (0x1u << 25) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P26 (0x1u << 26) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P27 (0x1u << 27) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P28 (0x1u << 28) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P29 (0x1u << 29) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P30 (0x1u << 30) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+#define S_PIO_IER_P31 (0x1u << 31) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */\r
+/* -------- S_PIO_IDR : (PIO Offset: N/A) Secure PIO Interrupt Disable Register -------- */\r
+#define S_PIO_IDR_P0 (0x1u << 0) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P1 (0x1u << 1) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P2 (0x1u << 2) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P3 (0x1u << 3) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P4 (0x1u << 4) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P5 (0x1u << 5) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P6 (0x1u << 6) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P7 (0x1u << 7) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P8 (0x1u << 8) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P9 (0x1u << 9) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P10 (0x1u << 10) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P11 (0x1u << 11) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P12 (0x1u << 12) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P13 (0x1u << 13) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P14 (0x1u << 14) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P15 (0x1u << 15) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P16 (0x1u << 16) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P17 (0x1u << 17) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P18 (0x1u << 18) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P19 (0x1u << 19) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P20 (0x1u << 20) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P21 (0x1u << 21) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P22 (0x1u << 22) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P23 (0x1u << 23) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P24 (0x1u << 24) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P25 (0x1u << 25) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P26 (0x1u << 26) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P27 (0x1u << 27) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P28 (0x1u << 28) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P29 (0x1u << 29) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P30 (0x1u << 30) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+#define S_PIO_IDR_P31 (0x1u << 31) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */\r
+/* -------- S_PIO_IMR : (PIO Offset: N/A) Secure PIO Interrupt Mask Register -------- */\r
+#define S_PIO_IMR_P0 (0x1u << 0) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P1 (0x1u << 1) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P2 (0x1u << 2) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P3 (0x1u << 3) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P4 (0x1u << 4) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P5 (0x1u << 5) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P6 (0x1u << 6) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P7 (0x1u << 7) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P8 (0x1u << 8) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P9 (0x1u << 9) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P10 (0x1u << 10) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P11 (0x1u << 11) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P12 (0x1u << 12) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P13 (0x1u << 13) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P14 (0x1u << 14) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P15 (0x1u << 15) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P16 (0x1u << 16) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P17 (0x1u << 17) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P18 (0x1u << 18) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P19 (0x1u << 19) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P20 (0x1u << 20) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P21 (0x1u << 21) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P22 (0x1u << 22) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P23 (0x1u << 23) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P24 (0x1u << 24) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P25 (0x1u << 25) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P26 (0x1u << 26) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P27 (0x1u << 27) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P28 (0x1u << 28) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P29 (0x1u << 29) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P30 (0x1u << 30) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+#define S_PIO_IMR_P31 (0x1u << 31) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */\r
+/* -------- S_PIO_ISR : (PIO Offset: N/A) Secure PIO Interrupt Status Register -------- */\r
+#define S_PIO_ISR_P0 (0x1u << 0) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P1 (0x1u << 1) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P2 (0x1u << 2) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P3 (0x1u << 3) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P4 (0x1u << 4) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P5 (0x1u << 5) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P6 (0x1u << 6) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P7 (0x1u << 7) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P8 (0x1u << 8) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P9 (0x1u << 9) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P10 (0x1u << 10) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P11 (0x1u << 11) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P12 (0x1u << 12) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P13 (0x1u << 13) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P14 (0x1u << 14) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P15 (0x1u << 15) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P16 (0x1u << 16) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P17 (0x1u << 17) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P18 (0x1u << 18) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P19 (0x1u << 19) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P20 (0x1u << 20) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P21 (0x1u << 21) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P22 (0x1u << 22) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P23 (0x1u << 23) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P24 (0x1u << 24) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P25 (0x1u << 25) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P26 (0x1u << 26) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P27 (0x1u << 27) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P28 (0x1u << 28) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P29 (0x1u << 29) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P30 (0x1u << 30) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+#define S_PIO_ISR_P31 (0x1u << 31) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */\r
+/* -------- S_PIO_SIONR : (PIO Offset: N/A) Secure PIO Set I/O Non-Secure Register -------- */\r
+#define S_PIO_SIONR_P0 (0x1u << 0) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P1 (0x1u << 1) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P2 (0x1u << 2) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P3 (0x1u << 3) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P4 (0x1u << 4) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P5 (0x1u << 5) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P6 (0x1u << 6) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P7 (0x1u << 7) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P8 (0x1u << 8) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P9 (0x1u << 9) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P10 (0x1u << 10) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P11 (0x1u << 11) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P12 (0x1u << 12) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P13 (0x1u << 13) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P14 (0x1u << 14) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P15 (0x1u << 15) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P16 (0x1u << 16) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P17 (0x1u << 17) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P18 (0x1u << 18) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P19 (0x1u << 19) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P20 (0x1u << 20) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P21 (0x1u << 21) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P22 (0x1u << 22) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P23 (0x1u << 23) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P24 (0x1u << 24) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P25 (0x1u << 25) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P26 (0x1u << 26) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P27 (0x1u << 27) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P28 (0x1u << 28) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P29 (0x1u << 29) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P30 (0x1u << 30) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+#define S_PIO_SIONR_P31 (0x1u << 31) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */\r
+/* -------- S_PIO_SIOSR : (PIO Offset: N/A) Secure PIO Set I/O Secure Register -------- */\r
+#define S_PIO_SIOSR_P0 (0x1u << 0) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P1 (0x1u << 1) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P2 (0x1u << 2) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P3 (0x1u << 3) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P4 (0x1u << 4) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P5 (0x1u << 5) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P6 (0x1u << 6) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P7 (0x1u << 7) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P8 (0x1u << 8) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P9 (0x1u << 9) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P10 (0x1u << 10) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P11 (0x1u << 11) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P12 (0x1u << 12) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P13 (0x1u << 13) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P14 (0x1u << 14) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P15 (0x1u << 15) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P16 (0x1u << 16) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P17 (0x1u << 17) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P18 (0x1u << 18) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P19 (0x1u << 19) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P20 (0x1u << 20) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P21 (0x1u << 21) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P22 (0x1u << 22) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P23 (0x1u << 23) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P24 (0x1u << 24) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P25 (0x1u << 25) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P26 (0x1u << 26) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P27 (0x1u << 27) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P28 (0x1u << 28) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P29 (0x1u << 29) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P30 (0x1u << 30) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+#define S_PIO_SIOSR_P31 (0x1u << 31) /**< \brief (S_PIO_SIOSR) Set I/O Secure */\r
+/* -------- S_PIO_IOSSR : (PIO Offset: N/A) Secure PIO I/O Security Status Register -------- */\r
+#define S_PIO_IOSSR_P0 (0x1u << 0) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P0_SECURE (0x0u << 0) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P0_NON_SECURE (0x1u << 0) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P1 (0x1u << 1) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P1_SECURE (0x0u << 1) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P1_NON_SECURE (0x1u << 1) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P2 (0x1u << 2) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P2_SECURE (0x0u << 2) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P2_NON_SECURE (0x1u << 2) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P3 (0x1u << 3) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P3_SECURE (0x0u << 3) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P3_NON_SECURE (0x1u << 3) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P4 (0x1u << 4) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P4_SECURE (0x0u << 4) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P4_NON_SECURE (0x1u << 4) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P5 (0x1u << 5) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P5_SECURE (0x0u << 5) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P5_NON_SECURE (0x1u << 5) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P6 (0x1u << 6) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P6_SECURE (0x0u << 6) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P6_NON_SECURE (0x1u << 6) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P7 (0x1u << 7) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P7_SECURE (0x0u << 7) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P7_NON_SECURE (0x1u << 7) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P8 (0x1u << 8) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P8_SECURE (0x0u << 8) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P8_NON_SECURE (0x1u << 8) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P9 (0x1u << 9) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P9_SECURE (0x0u << 9) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P9_NON_SECURE (0x1u << 9) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P10 (0x1u << 10) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P10_SECURE (0x0u << 10) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P10_NON_SECURE (0x1u << 10) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P11 (0x1u << 11) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P11_SECURE (0x0u << 11) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P11_NON_SECURE (0x1u << 11) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P12 (0x1u << 12) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P12_SECURE (0x0u << 12) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P12_NON_SECURE (0x1u << 12) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P13 (0x1u << 13) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P13_SECURE (0x0u << 13) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P13_NON_SECURE (0x1u << 13) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P14 (0x1u << 14) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P14_SECURE (0x0u << 14) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P14_NON_SECURE (0x1u << 14) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P15 (0x1u << 15) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P15_SECURE (0x0u << 15) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P15_NON_SECURE (0x1u << 15) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P16 (0x1u << 16) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P16_SECURE (0x0u << 16) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P16_NON_SECURE (0x1u << 16) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P17 (0x1u << 17) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P17_SECURE (0x0u << 17) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P17_NON_SECURE (0x1u << 17) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P18 (0x1u << 18) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P18_SECURE (0x0u << 18) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P18_NON_SECURE (0x1u << 18) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P19 (0x1u << 19) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P19_SECURE (0x0u << 19) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P19_NON_SECURE (0x1u << 19) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P20 (0x1u << 20) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P20_SECURE (0x0u << 20) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P20_NON_SECURE (0x1u << 20) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P21 (0x1u << 21) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P21_SECURE (0x0u << 21) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P21_NON_SECURE (0x1u << 21) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P22 (0x1u << 22) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P22_SECURE (0x0u << 22) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P22_NON_SECURE (0x1u << 22) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P23 (0x1u << 23) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P23_SECURE (0x0u << 23) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P23_NON_SECURE (0x1u << 23) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P24 (0x1u << 24) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P24_SECURE (0x0u << 24) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P24_NON_SECURE (0x1u << 24) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P25 (0x1u << 25) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P25_SECURE (0x0u << 25) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P25_NON_SECURE (0x1u << 25) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P26 (0x1u << 26) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P26_SECURE (0x0u << 26) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P26_NON_SECURE (0x1u << 26) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P27 (0x1u << 27) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P27_SECURE (0x0u << 27) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P27_NON_SECURE (0x1u << 27) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P28 (0x1u << 28) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P28_SECURE (0x0u << 28) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P28_NON_SECURE (0x1u << 28) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P29 (0x1u << 29) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P29_SECURE (0x0u << 29) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P29_NON_SECURE (0x1u << 29) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P30 (0x1u << 30) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P30_SECURE (0x0u << 30) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P30_NON_SECURE (0x1u << 30) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+#define S_PIO_IOSSR_P31 (0x1u << 31) /**< \brief (S_PIO_IOSSR) I/O Security Status */\r
+#define S_PIO_IOSSR_P31_SECURE (0x0u << 31) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */\r
+#define S_PIO_IOSSR_P31_NON_SECURE (0x1u << 31) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */\r
+/* -------- S_PIO_IOFR : (PIO Offset: N/A) Secure PIO I/O Freeze Register -------- */\r
+#define S_PIO_IOFR_FPHY (0x1u << 0) /**< \brief (S_PIO_IOFR) Freeze Physical Configuration */\r
+#define S_PIO_IOFR_FINT (0x1u << 1) /**< \brief (S_PIO_IOFR) Freeze Interrupt Configuration */\r
+#define S_PIO_IOFR_FRZKEY_Pos 8\r
+#define S_PIO_IOFR_FRZKEY_Msk (0xffffffu << S_PIO_IOFR_FRZKEY_Pos) /**< \brief (S_PIO_IOFR) Freeze Key */\r
+#define S_PIO_IOFR_FRZKEY(value) ((S_PIO_IOFR_FRZKEY_Msk & ((value) << S_PIO_IOFR_FRZKEY_Pos)))\r
+#define S_PIO_IOFR_FRZKEY_PASSWD (0x494F46u << 8) /**< \brief (S_PIO_IOFR) Writing any other value in this field aborts the write operation of the WPEN bit. */\r
+/* -------- S_PIO_SCDR : (PIO Offset: 0x1500) Secure PIO Slow Clock Divider Debouncing Register -------- */\r
+#define S_PIO_SCDR_DIV_Pos 0\r
+#define S_PIO_SCDR_DIV_Msk (0x3fffu << S_PIO_SCDR_DIV_Pos) /**< \brief (S_PIO_SCDR) Slow Clock Divider Selection for Debouncing */\r
+#define S_PIO_SCDR_DIV(value) ((S_PIO_SCDR_DIV_Msk & ((value) << S_PIO_SCDR_DIV_Pos)))\r
+/* -------- S_PIO_WPMR : (PIO Offset: 0x15E0) Secure PIO Write Protection Mode Register -------- */\r
+#define S_PIO_WPMR_WPEN (0x1u << 0) /**< \brief (S_PIO_WPMR) Write Protection Enable */\r
+#define S_PIO_WPMR_WPKEY_Pos 8\r
+#define S_PIO_WPMR_WPKEY_Msk (0xffffffu << S_PIO_WPMR_WPKEY_Pos) /**< \brief (S_PIO_WPMR) Write Protection Key */\r
+#define S_PIO_WPMR_WPKEY(value) ((S_PIO_WPMR_WPKEY_Msk & ((value) << S_PIO_WPMR_WPKEY_Pos)))\r
+#define S_PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (S_PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */\r
+/* -------- S_PIO_WPSR : (PIO Offset: 0x15E4) Secure PIO Write Protection Status Register -------- */\r
+#define S_PIO_WPSR_WPVS (0x1u << 0) /**< \brief (S_PIO_WPSR) Write Protection Violation Status */\r
+#define S_PIO_WPSR_WPVSRC_Pos 8\r
+#define S_PIO_WPSR_WPVSRC_Msk (0xffffu << S_PIO_WPSR_WPVSRC_Pos) /**< \brief (S_PIO_WPSR) Write Protection Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_PIO_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_PIT_COMPONENT_\r
+#define _SAMA5D2_PIT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Periodic Interval Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_PIT Periodic Interval Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pit hardware registers */\r
+typedef struct {\r
+ __IO uint32_t PIT_MR; /**< \brief (Pit Offset: 0x00) Mode Register */\r
+ __I uint32_t PIT_SR; /**< \brief (Pit Offset: 0x04) Status Register */\r
+ __I uint32_t PIT_PIVR; /**< \brief (Pit Offset: 0x08) Periodic Interval Value Register */\r
+ __I uint32_t PIT_PIIR; /**< \brief (Pit Offset: 0x0C) Periodic Interval Image Register */\r
+} Pit;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PIT_MR : (PIT Offset: 0x00) Mode Register -------- */\r
+#define PIT_MR_PIV_Pos 0\r
+#define PIT_MR_PIV_Msk (0xfffffu << PIT_MR_PIV_Pos) /**< \brief (PIT_MR) Periodic Interval Value */\r
+#define PIT_MR_PIV(value) ((PIT_MR_PIV_Msk & ((value) << PIT_MR_PIV_Pos)))\r
+#define PIT_MR_PITEN (0x1u << 24) /**< \brief (PIT_MR) Period Interval Timer Enabled */\r
+#define PIT_MR_PITIEN (0x1u << 25) /**< \brief (PIT_MR) Periodic Interval Timer Interrupt Enable */\r
+/* -------- PIT_SR : (PIT Offset: 0x04) Status Register -------- */\r
+#define PIT_SR_PITS (0x1u << 0) /**< \brief (PIT_SR) Periodic Interval Timer Status */\r
+/* -------- PIT_PIVR : (PIT Offset: 0x08) Periodic Interval Value Register -------- */\r
+#define PIT_PIVR_CPIV_Pos 0\r
+#define PIT_PIVR_CPIV_Msk (0xfffffu << PIT_PIVR_CPIV_Pos) /**< \brief (PIT_PIVR) Current Periodic Interval Value */\r
+#define PIT_PIVR_PICNT_Pos 20\r
+#define PIT_PIVR_PICNT_Msk (0xfffu << PIT_PIVR_PICNT_Pos) /**< \brief (PIT_PIVR) Periodic Interval Counter */\r
+/* -------- PIT_PIIR : (PIT Offset: 0x0C) Periodic Interval Image Register -------- */\r
+#define PIT_PIIR_CPIV_Pos 0\r
+#define PIT_PIIR_CPIV_Msk (0xfffffu << PIT_PIIR_CPIV_Pos) /**< \brief (PIT_PIIR) Current Periodic Interval Value */\r
+#define PIT_PIIR_PICNT_Pos 20\r
+#define PIT_PIIR_PICNT_Msk (0xfffu << PIT_PIIR_PICNT_Pos) /**< \brief (PIT_PIIR) Periodic Interval Counter */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_PIT_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_PMC_COMPONENT_\r
+#define _SAMA5D2_PMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Power Management Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_PMC Power Management Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pmc hardware registers */\r
+typedef struct {\r
+ __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */\r
+ __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */\r
+ __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */\r
+ __I uint32_t Reserved1[1];\r
+ __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */\r
+ __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */\r
+ __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */\r
+ __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */\r
+ __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */\r
+ __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */\r
+ __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */\r
+ __I uint32_t Reserved3[1];\r
+ __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */\r
+ __I uint32_t Reserved4[1];\r
+ __IO uint32_t PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */\r
+ __I uint32_t Reserved5[5];\r
+ __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */\r
+ __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */\r
+ __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */\r
+ __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */\r
+ __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) PMC Fast Startup Mode Register */\r
+ __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) PMC Fast Startup Polarity Register */\r
+ __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */\r
+ __I uint32_t Reserved6[1];\r
+ __IO uint32_t PMC_PLLICPR; /**< \brief (Pmc Offset: 0x0080) PLL Charge Pump Current Register */\r
+ __I uint32_t Reserved7[24];\r
+ __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write ProtectIon Mode Register */\r
+ __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */\r
+ __I uint32_t Reserved8[4];\r
+ __I uint32_t PMC_VERSION; /**< \brief (Pmc Offset: 0x00FC) Version Register */\r
+ __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */\r
+ __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */\r
+ __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */\r
+ __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */\r
+ __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */\r
+ __I uint32_t Reserved9[12];\r
+ __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */\r
+ __IO uint32_t PMC_SLPWKCR; /**< \brief (Pmc Offset: 0x0148) SleepWalking Control Register */\r
+ __IO uint32_t PMC_AUDIO_PLL0; /**< \brief (Pmc Offset: 0x014C) Audio PLL Register 0 */\r
+ __IO uint32_t PMC_AUDIO_PLL1; /**< \brief (Pmc Offset: 0x0150) Audio PLL Register 1 */\r
+} Pmc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */\r
+#define PMC_SCER_DDRCK (0x1u << 2) /**< \brief (PMC_SCER) DDR Clock Enable */\r
+#define PMC_SCER_LCDCK (0x1u << 3) /**< \brief (PMC_SCER) LCD2x Clock Enable */\r
+#define PMC_SCER_UHP (0x1u << 6) /**< \brief (PMC_SCER) USB Host OHCI Clocks Enable */\r
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Clock Enable */\r
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */\r
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */\r
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */\r
+#define PMC_SCER_ISCCK (0x1u << 18) /**< \brief (PMC_SCER) ISC Clock Enable */\r
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */\r
+#define PMC_SCDR_PCK (0x1u << 0) /**< \brief (PMC_SCDR) Processor Clock Disable */\r
+#define PMC_SCDR_DDRCK (0x1u << 2) /**< \brief (PMC_SCDR) DDR Clock Disable */\r
+#define PMC_SCDR_LCDCK (0x1u << 3) /**< \brief (PMC_SCDR) LCD2x Clock Disable */\r
+#define PMC_SCDR_UHP (0x1u << 6) /**< \brief (PMC_SCDR) USB Host OHCI Clock Disable */\r
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Clock Enable */\r
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */\r
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */\r
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */\r
+#define PMC_SCDR_ISCCK (0x1u << 18) /**< \brief (PMC_SCDR) ISC Clock Disable */\r
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */\r
+#define PMC_SCSR_PCK (0x1u << 0) /**< \brief (PMC_SCSR) Processor Clock Status */\r
+#define PMC_SCSR_DDRCK (0x1u << 2) /**< \brief (PMC_SCSR) DDR Clock Status */\r
+#define PMC_SCSR_LCDCK (0x1u << 3) /**< \brief (PMC_SCSR) LCD2x Clock Status */\r
+#define PMC_SCSR_UHP (0x1u << 6) /**< \brief (PMC_SCSR) USB Host Port Clock Status */\r
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */\r
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */\r
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */\r
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */\r
+#define PMC_SCSR_ISCCK (0x1u << 18) /**< \brief (PMC_SCSR) ISC Clock Status */\r
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */\r
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */\r
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */\r
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */\r
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */\r
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */\r
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */\r
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */\r
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */\r
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */\r
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */\r
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */\r
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */\r
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */\r
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */\r
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */\r
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */\r
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */\r
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */\r
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */\r
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */\r
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */\r
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */\r
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */\r
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */\r
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */\r
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */\r
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */\r
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */\r
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */\r
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */\r
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */\r
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */\r
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */\r
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */\r
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */\r
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */\r
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */\r
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */\r
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */\r
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */\r
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */\r
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */\r
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */\r
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */\r
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */\r
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */\r
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */\r
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */\r
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */\r
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */\r
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */\r
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */\r
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */\r
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */\r
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */\r
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */\r
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */\r
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */\r
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */\r
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */\r
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */\r
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */\r
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */\r
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */\r
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */\r
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */\r
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */\r
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */\r
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */\r
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */\r
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */\r
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */\r
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */\r
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */\r
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */\r
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */\r
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */\r
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */\r
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */\r
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */\r
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */\r
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */\r
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */\r
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */\r
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */\r
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */\r
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */\r
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */\r
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */\r
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */\r
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */\r
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */\r
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */\r
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */\r
+#define CKGR_UCKR_UPLLCOUNT_Pos 20\r
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */\r
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))\r
+#define CKGR_UCKR_BIASEN (0x1u << 24) /**< \brief (CKGR_UCKR) UTMI BIAS Enable */\r
+#define CKGR_UCKR_BIASCOUNT_Pos 28\r
+#define CKGR_UCKR_BIASCOUNT_Msk (0xfu << CKGR_UCKR_BIASCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI BIAS Start-up Time */\r
+#define CKGR_UCKR_BIASCOUNT(value) ((CKGR_UCKR_BIASCOUNT_Msk & ((value) << CKGR_UCKR_BIASCOUNT_Pos)))\r
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */\r
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) 8 to 24MHz Crystal Oscillator Enable */\r
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) 8 to 24MHz Crystal Oscillator Bypass */\r
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) 12 MHz RC Oscillator Enable */\r
+#define CKGR_MOR_MOSCXTST_Pos 8\r
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) 8 to 24MHz Crystal Oscillator Startup Time */\r
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))\r
+#define CKGR_MOR_KEY_Pos 16\r
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */\r
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))\r
+#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation. */\r
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Clock Oscillator Selection */\r
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */\r
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */\r
+#define CKGR_MCFR_MAINF_Pos 0\r
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */\r
+#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))\r
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */\r
+#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */\r
+#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */\r
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */\r
+#define CKGR_PLLAR_DIVA_Pos 0\r
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider A */\r
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))\r
+#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 */\r
+#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed */\r
+#define CKGR_PLLAR_PLLACOUNT_Pos 8\r
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */\r
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))\r
+#define CKGR_PLLAR_OUTA_Pos 14\r
+#define CKGR_PLLAR_OUTA_Msk (0xfu << CKGR_PLLAR_OUTA_Pos) /**< \brief (CKGR_PLLAR) PLLA Clock Frequency Range */\r
+#define CKGR_PLLAR_OUTA(value) ((CKGR_PLLAR_OUTA_Msk & ((value) << CKGR_PLLAR_OUTA_Pos)))\r
+#define CKGR_PLLAR_MULA_Pos 18\r
+#define CKGR_PLLAR_MULA_Msk (0x7fu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */\r
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))\r
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */\r
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */\r
+#define PMC_MCKR_CSS_Pos 0\r
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master/Processor Clock Source Selection */\r
+#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))\r
+#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow clock is selected */\r
+#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main clock is selected */\r
+#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLACK is selected */\r
+#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */\r
+#define PMC_MCKR_PRES_Pos 4\r
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Master/Processor Clock Prescaler */\r
+#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))\r
+#define PMC_MCKR_PRES_CLOCK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */\r
+#define PMC_MCKR_PRES_CLOCK_DIV2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */\r
+#define PMC_MCKR_PRES_CLOCK_DIV4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */\r
+#define PMC_MCKR_PRES_CLOCK_DIV8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */\r
+#define PMC_MCKR_PRES_CLOCK_DIV16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */\r
+#define PMC_MCKR_PRES_CLOCK_DIV32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */\r
+#define PMC_MCKR_PRES_CLOCK_DIV64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */\r
+#define PMC_MCKR_MDIV_Pos 8\r
+#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */\r
+#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))\r
+#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. WARNING: SysClk DDR and DDRCK are not available. */\r
+#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */\r
+#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */\r
+#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */\r
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */\r
+#define PMC_MCKR_H32MXDIV (0x1u << 24) /**< \brief (PMC_MCKR) AHB 32-bit Matrix Divisor */\r
+#define PMC_MCKR_H32MXDIV_H32MXDIV1 (0x0u << 24) /**< \brief (PMC_MCKR) The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency. It is possible only if the AHB 64-bit Matrix frequency does not exceed 90 MHz. */\r
+#define PMC_MCKR_H32MXDIV_H32MXDIV2 (0x1u << 24) /**< \brief (PMC_MCKR) The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency divided by 2. */\r
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */\r
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB OHCI Input Clock Selection */\r
+#define PMC_USB_USBDIV_Pos 8\r
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB OHCI Clock */\r
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))\r
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */\r
+#define PMC_PCK_CSS_Pos 0\r
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */\r
+#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))\r
+#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow clock is selected */\r
+#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main clock is selected */\r
+#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLACK is selected */\r
+#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */\r
+#define PMC_PCK_CSS_MCK_CLK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */\r
+#define PMC_PCK_CSS_AUDIO_CLK (0x5u << 0) /**< \brief (PMC_PCK[3]) Audio PLL clock is selected */\r
+#define PMC_PCK_PRES_Pos 4\r
+#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */\r
+#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))\r
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */\r
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) 8 to 24MHz Crystal Oscillator Status Interrupt Enable */\r
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */\r
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */\r
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */\r
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */\r
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */\r
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */\r
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable */\r
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */\r
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */\r
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) 8 to 24MHz Crystal Oscillator Status Interrupt Disable */\r
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */\r
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */\r
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Enable */\r
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */\r
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Clock Source Selection Status Interrupt Disable */\r
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */\r
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */\r
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) 8 to 24MHz Crystal Oscillator Status */\r
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */\r
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */\r
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UPLL Clock Status */\r
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */\r
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */\r
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) 12 MHz RC Oscillator Status */\r
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */\r
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */\r
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */\r
+#define PMC_SR_GCKRDY (0x1u << 24) /**< \brief (PMC_SR) Generated Clocks Status */\r
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */\r
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) 8 to 24MHz Crystal Oscillator Status Interrupt Mask */\r
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */\r
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */\r
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */\r
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Clock Source Selection Status Interrupt Mask */\r
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */\r
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) PMC Fast Startup Mode Register -------- */\r
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */\r
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */\r
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */\r
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */\r
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */\r
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */\r
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */\r
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */\r
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */\r
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */\r
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */\r
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */\r
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */\r
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */\r
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */\r
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */\r
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */\r
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */\r
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */\r
+#define PMC_FSMR_RXLPAL (0x1u << 24) /**< \brief (PMC_FSMR) Lower-power Receiver Alarm */\r
+#define PMC_FSMR_ACCAL (0x1u << 25) /**< \brief (PMC_FSMR) Analog Comparator Controller Alarm */\r
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) PMC Fast Startup Polarity Register -------- */\r
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */\r
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */\r
+/* -------- PMC_PLLICPR : (PMC Offset: 0x0080) PLL Charge Pump Current Register -------- */\r
+#define PMC_PLLICPR_ICP_PLLA_Pos 0\r
+#define PMC_PLLICPR_ICP_PLLA_Msk (0x3u << PMC_PLLICPR_ICP_PLLA_Pos) /**< \brief (PMC_PLLICPR) Must Be Written to Zero */\r
+#define PMC_PLLICPR_ICP_PLLA(value) ((PMC_PLLICPR_ICP_PLLA_Msk & ((value) << PMC_PLLICPR_ICP_PLLA_Pos)))\r
+#define PMC_PLLICPR_IPLL_PLLA_Pos 8\r
+#define PMC_PLLICPR_IPLL_PLLA_Msk (0x7u << PMC_PLLICPR_IPLL_PLLA_Pos) /**< \brief (PMC_PLLICPR) Engineering Configuration PLLA */\r
+#define PMC_PLLICPR_IPLL_PLLA(value) ((PMC_PLLICPR_IPLL_PLLA_Msk & ((value) << PMC_PLLICPR_IPLL_PLLA_Pos)))\r
+#define PMC_PLLICPR_ICP_PLLU_Pos 16\r
+#define PMC_PLLICPR_ICP_PLLU_Msk (0x3u << PMC_PLLICPR_ICP_PLLU_Pos) /**< \brief (PMC_PLLICPR) Charge Pump Current PLL UTMI */\r
+#define PMC_PLLICPR_ICP_PLLU(value) ((PMC_PLLICPR_ICP_PLLU_Msk & ((value) << PMC_PLLICPR_ICP_PLLU_Pos)))\r
+#define PMC_PLLICPR_IVCO_PLLU_Pos 24\r
+#define PMC_PLLICPR_IVCO_PLLU_Msk (0x3u << PMC_PLLICPR_IVCO_PLLU_Pos) /**< \brief (PMC_PLLICPR) Voltage Control Output Current PLL UTMI */\r
+#define PMC_PLLICPR_IVCO_PLLU(value) ((PMC_PLLICPR_IVCO_PLLU_Msk & ((value) << PMC_PLLICPR_IVCO_PLLU_Pos)))\r
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write ProtectIon Mode Register -------- */\r
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */\r
+#define PMC_WPMR_WPKEY_Pos 8\r
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */\r
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))\r
+#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */\r
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */\r
+#define PMC_WPSR_WPVSRC_Pos 8\r
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */\r
+/* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */\r
+#define PMC_VERSION_VERSION_Pos 0\r
+#define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) /**< \brief (PMC_VERSION) Version of the Hardware Module */\r
+#define PMC_VERSION_MFN_Pos 16\r
+#define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) /**< \brief (PMC_VERSION) Metal Fix Number */\r
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */\r
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */\r
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */\r
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */\r
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */\r
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */\r
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */\r
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */\r
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */\r
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */\r
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */\r
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */\r
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */\r
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */\r
+#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */\r
+#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */\r
+#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */\r
+#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */\r
+#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */\r
+#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */\r
+#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */\r
+#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */\r
+#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */\r
+#define PMC_PCER1_PID54 (0x1u << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */\r
+#define PMC_PCER1_PID55 (0x1u << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */\r
+#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */\r
+#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */\r
+#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */\r
+#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */\r
+#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */\r
+#define PMC_PCER1_PID61 (0x1u << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */\r
+#define PMC_PCER1_PID62 (0x1u << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */\r
+#define PMC_PCER1_PID63 (0x1u << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */\r
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */\r
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */\r
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */\r
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */\r
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */\r
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */\r
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */\r
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */\r
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */\r
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */\r
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */\r
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */\r
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */\r
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */\r
+#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */\r
+#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */\r
+#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */\r
+#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */\r
+#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */\r
+#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */\r
+#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */\r
+#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */\r
+#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */\r
+#define PMC_PCDR1_PID54 (0x1u << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */\r
+#define PMC_PCDR1_PID55 (0x1u << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */\r
+#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */\r
+#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */\r
+#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */\r
+#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */\r
+#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */\r
+#define PMC_PCDR1_PID61 (0x1u << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */\r
+#define PMC_PCDR1_PID62 (0x1u << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */\r
+#define PMC_PCDR1_PID63 (0x1u << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */\r
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */\r
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */\r
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */\r
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */\r
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */\r
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */\r
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */\r
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */\r
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */\r
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */\r
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */\r
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */\r
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */\r
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */\r
+#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */\r
+#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */\r
+#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */\r
+#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */\r
+#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */\r
+#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */\r
+#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */\r
+#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */\r
+#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */\r
+#define PMC_PCSR1_PID54 (0x1u << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */\r
+#define PMC_PCSR1_PID55 (0x1u << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */\r
+#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */\r
+#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */\r
+#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */\r
+#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */\r
+#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */\r
+#define PMC_PCSR1_PID61 (0x1u << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */\r
+#define PMC_PCSR1_PID62 (0x1u << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */\r
+#define PMC_PCSR1_PID63 (0x1u << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */\r
+/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */\r
+#define PMC_PCR_PID_Pos 0\r
+#define PMC_PCR_PID_Msk (0x7fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */\r
+#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))\r
+#define PMC_PCR_GCKCSS_Pos 8\r
+#define PMC_PCR_GCKCSS_Msk (0x7u << PMC_PCR_GCKCSS_Pos) /**< \brief (PMC_PCR) GCK Clock Source Selection */\r
+#define PMC_PCR_GCKCSS(value) ((PMC_PCR_GCKCSS_Msk & ((value) << PMC_PCR_GCKCSS_Pos)))\r
+#define PMC_PCR_GCKCSS_SLOW_CLK (0x0u << 8) /**< \brief (PMC_PCR) Slow clock is selected */\r
+#define PMC_PCR_GCKCSS_MAIN_CLK (0x1u << 8) /**< \brief (PMC_PCR) Main clock is selected */\r
+#define PMC_PCR_GCKCSS_PLLA_CLK (0x2u << 8) /**< \brief (PMC_PCR) PLLACK is selected */\r
+#define PMC_PCR_GCKCSS_UPLL_CLK (0x3u << 8) /**< \brief (PMC_PCR) UPLL Clock is selected */\r
+#define PMC_PCR_GCKCSS_MCK_CLK (0x4u << 8) /**< \brief (PMC_PCR) Master Clock is selected */\r
+#define PMC_PCR_GCKCSS_AUDIO_CLK (0x5u << 8) /**< \brief (PMC_PCR) Audio PLL clock is selected */\r
+#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */\r
+#define PMC_PCR_DIV_Pos 16\r
+#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */\r
+#define PMC_PCR_DIV(value) ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos)))\r
+#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */\r
+#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */\r
+#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */\r
+#define PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/8 */\r
+#define PMC_PCR_GCKDIV_Pos 20\r
+#define PMC_PCR_GCKDIV_Msk (0xffu << PMC_PCR_GCKDIV_Pos) /**< \brief (PMC_PCR) Generated Clock Division Ratio */\r
+#define PMC_PCR_GCKDIV(value) ((PMC_PCR_GCKDIV_Msk & ((value) << PMC_PCR_GCKDIV_Pos)))\r
+#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */\r
+#define PMC_PCR_GCKEN (0x1u << 29) /**< \brief (PMC_PCR) GCK Enable */\r
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */\r
+#define PMC_OCR_CAL_Pos 0\r
+#define PMC_OCR_CAL_Msk (0x7fu << PMC_OCR_CAL_Pos) /**< \brief (PMC_OCR) 12 MHz RC Oscillator Calibration Bits */\r
+#define PMC_OCR_CAL(value) ((PMC_OCR_CAL_Msk & ((value) << PMC_OCR_CAL_Pos)))\r
+#define PMC_OCR_SEL (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration Bits */\r
+/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */\r
+#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */\r
+/* -------- PMC_SLPWKCR : (PMC Offset: 0x0148) SleepWalking Control Register -------- */\r
+#define PMC_SLPWKCR_PID_Pos 0\r
+#define PMC_SLPWKCR_PID_Msk (0x7fu << PMC_SLPWKCR_PID_Pos) /**< \brief (PMC_SLPWKCR) Peripheral ID */\r
+#define PMC_SLPWKCR_PID(value) ((PMC_SLPWKCR_PID_Msk & ((value) << PMC_SLPWKCR_PID_Pos)))\r
+#define PMC_SLPWKCR_CMD (0x1u << 12) /**< \brief (PMC_SLPWKCR) Command */\r
+#define PMC_SLPWKCR_ASR (0x1u << 16) /**< \brief (PMC_SLPWKCR) Activity Status Register */\r
+#define PMC_SLPWKCR_SLPWKSR (0x1u << 28) /**< \brief (PMC_SLPWKCR) SleepWalking Status Register */\r
+/* -------- PMC_AUDIO_PLL0 : (PMC Offset: 0x014C) Audio PLL Register 0 -------- */\r
+#define PMC_AUDIO_PLL0_PLLEN (0x1u << 0) /**< \brief (PMC_AUDIO_PLL0) PLL Enable */\r
+#define PMC_AUDIO_PLL0_PADEN (0x1u << 1) /**< \brief (PMC_AUDIO_PLL0) Pad Clock Enable */\r
+#define PMC_AUDIO_PLL0_PMCEN (0x1u << 2) /**< \brief (PMC_AUDIO_PLL0) PMC Clock Enable */\r
+#define PMC_AUDIO_PLL0_RESETN (0x1u << 3) /**< \brief (PMC_AUDIO_PLL0) Audio PLL Reset */\r
+#define PMC_AUDIO_PLL0_ND_Pos 8\r
+#define PMC_AUDIO_PLL0_ND_Msk (0x7fu << PMC_AUDIO_PLL0_ND_Pos) /**< \brief (PMC_AUDIO_PLL0) Loop Divider Ratio */\r
+#define PMC_AUDIO_PLL0_ND(value) ((PMC_AUDIO_PLL0_ND_Msk & ((value) << PMC_AUDIO_PLL0_ND_Pos)))\r
+#define PMC_AUDIO_PLL0_QDPMC_Pos 16\r
+#define PMC_AUDIO_PLL0_QDPMC_Msk (0x7fu << PMC_AUDIO_PLL0_QDPMC_Pos) /**< \brief (PMC_AUDIO_PLL0) Output Divider Ratio for PMC Clock */\r
+#define PMC_AUDIO_PLL0_QDPMC(value) ((PMC_AUDIO_PLL0_QDPMC_Msk & ((value) << PMC_AUDIO_PLL0_QDPMC_Pos)))\r
+/* -------- PMC_AUDIO_PLL1 : (PMC Offset: 0x0150) Audio PLL Register 1 -------- */\r
+#define PMC_AUDIO_PLL1_FRACR_Pos 0\r
+#define PMC_AUDIO_PLL1_FRACR_Msk (0x3fffffu << PMC_AUDIO_PLL1_FRACR_Pos) /**< \brief (PMC_AUDIO_PLL1) Fractional Loop Divider Setting */\r
+#define PMC_AUDIO_PLL1_FRACR(value) ((PMC_AUDIO_PLL1_FRACR_Msk & ((value) << PMC_AUDIO_PLL1_FRACR_Pos)))\r
+#define PMC_AUDIO_PLL1_DIV_Pos 24\r
+#define PMC_AUDIO_PLL1_DIV_Msk (0x3u << PMC_AUDIO_PLL1_DIV_Pos) /**< \brief (PMC_AUDIO_PLL1) Divider Value */\r
+#define PMC_AUDIO_PLL1_DIV(value) ((PMC_AUDIO_PLL1_DIV_Msk & ((value) << PMC_AUDIO_PLL1_DIV_Pos)))\r
+#define PMC_AUDIO_PLL1_QDAUDIO_Pos 26\r
+#define PMC_AUDIO_PLL1_QDAUDIO_Msk (0x1fu << PMC_AUDIO_PLL1_QDAUDIO_Pos) /**< \brief (PMC_AUDIO_PLL1) Output Divider Ratio for Pad Clock */\r
+#define PMC_AUDIO_PLL1_QDAUDIO(value) ((PMC_AUDIO_PLL1_QDAUDIO_Msk & ((value) << PMC_AUDIO_PLL1_QDAUDIO_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_PMC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_PWM_COMPONENT_\r
+#define _SAMA5D2_PWM_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_PWM Pulse Width Modulation Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief PwmCh_num hardware registers */\r
+typedef struct {\r
+ __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */\r
+ __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */\r
+ __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */\r
+ __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */\r
+ __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */\r
+ __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */\r
+ __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */\r
+ __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */\r
+} PwmCh_num;\r
+/** \brief PwmCmp hardware registers */\r
+typedef struct {\r
+ __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */\r
+ __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */\r
+ __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */\r
+ __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */\r
+} PwmCmp;\r
+/** \brief Pwm hardware registers */\r
+#define PWMCMP_NUMBER 8\r
+#define PWMCH_NUM_NUMBER 4\r
+typedef struct {\r
+ __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */\r
+ __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */\r
+ __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */\r
+ __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */\r
+ __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */\r
+ __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */\r
+ __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */\r
+ __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */\r
+ __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */\r
+ __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */\r
+ __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */\r
+ __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */\r
+ __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */\r
+ __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */\r
+ __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */\r
+ __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */\r
+ __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */\r
+ __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */\r
+ __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */\r
+ __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */\r
+ __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */\r
+ __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */\r
+ __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */\r
+ __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */\r
+ __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */\r
+ __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */\r
+ __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */\r
+ __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */\r
+ __I uint32_t Reserved1[3];\r
+ __IO uint32_t PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */\r
+ __I uint32_t Reserved2[7];\r
+ __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */\r
+ __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */\r
+ __I uint32_t Reserved3[2];\r
+ __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */\r
+ __I uint32_t Reserved4[3];\r
+ __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */\r
+ __I uint32_t Reserved5[8];\r
+ __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */\r
+ __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */\r
+ __I uint32_t Reserved6[4];\r
+ __I uint32_t PWM_VERSION; /**< \brief (Pwm Offset: 0xFC) Version Register */\r
+ __I uint32_t Reserved7[12];\r
+ PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */\r
+ __I uint32_t Reserved8[20];\r
+ PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */\r
+ __I uint32_t Reserved9[96];\r
+ __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */\r
+ __I uint32_t Reserved10[7];\r
+ __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */\r
+ __I uint32_t Reserved11[2];\r
+ __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */\r
+ __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */\r
+ __I uint32_t Reserved12[3];\r
+ __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */\r
+ __I uint32_t Reserved13[2];\r
+ __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */\r
+ __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */\r
+ __I uint32_t Reserved14[3];\r
+ __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */\r
+} Pwm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */\r
+#define PWM_CLK_DIVA_Pos 0\r
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */\r
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))\r
+#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */\r
+#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */\r
+#define PWM_CLK_PREA_Pos 8\r
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */\r
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))\r
+#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */\r
+#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */\r
+#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */\r
+#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */\r
+#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */\r
+#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */\r
+#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */\r
+#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */\r
+#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */\r
+#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */\r
+#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */\r
+#define PWM_CLK_DIVB_Pos 16\r
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */\r
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))\r
+#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */\r
+#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */\r
+#define PWM_CLK_PREB_Pos 24\r
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */\r
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))\r
+#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */\r
+#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */\r
+#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */\r
+#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */\r
+#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */\r
+#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */\r
+#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */\r
+#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */\r
+#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */\r
+#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */\r
+#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */\r
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */\r
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */\r
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */\r
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */\r
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */\r
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */\r
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */\r
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */\r
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */\r
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */\r
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */\r
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */\r
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */\r
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */\r
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */\r
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */\r
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */\r
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */\r
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */\r
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */\r
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */\r
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */\r
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */\r
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */\r
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */\r
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */\r
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */\r
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */\r
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */\r
+#define PWM_SCM_UPDM_Pos 16\r
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */\r
+#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)))\r
+#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */\r
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Controller Transfer Request Mode */\r
+#define PWM_SCM_PTRCS_Pos 21\r
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Controller Transfer Request Comparison Selection */\r
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))\r
+/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */\r
+#define PWM_DMAR_DMADUTY_Pos 0\r
+#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */\r
+#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)))\r
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */\r
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */\r
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */\r
+#define PWM_SCUP_UPR_Pos 0\r
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */\r
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))\r
+#define PWM_SCUP_UPRCNT_Pos 4\r
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */\r
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))\r
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */\r
+#define PWM_SCUPUPD_UPRUPD_Pos 0\r
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */\r
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))\r
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */\r
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */\r
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */\r
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */\r
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */\r
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */\r
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */\r
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */\r
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */\r
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */\r
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */\r
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */\r
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */\r
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */\r
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */\r
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */\r
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */\r
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */\r
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */\r
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */\r
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */\r
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */\r
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */\r
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */\r
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */\r
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */\r
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */\r
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */\r
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */\r
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */\r
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */\r
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */\r
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */\r
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */\r
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */\r
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */\r
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */\r
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */\r
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */\r
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */\r
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */\r
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */\r
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */\r
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */\r
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */\r
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */\r
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */\r
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */\r
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */\r
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */\r
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */\r
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */\r
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */\r
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */\r
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */\r
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */\r
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */\r
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */\r
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */\r
+#define PWM_FMR_FPOL_Pos 0\r
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */\r
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))\r
+#define PWM_FMR_FMOD_Pos 8\r
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */\r
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))\r
+#define PWM_FMR_FFIL_Pos 16\r
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */\r
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))\r
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */\r
+#define PWM_FSR_FIV_Pos 0\r
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */\r
+#define PWM_FSR_FS_Pos 8\r
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */\r
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */\r
+#define PWM_FCR_FCLR_Pos 0\r
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */\r
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))\r
+/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */\r
+#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */\r
+#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */\r
+#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */\r
+#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */\r
+#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */\r
+#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */\r
+#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */\r
+#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */\r
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */\r
+#define PWM_FPE_FPE0_Pos 0\r
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */\r
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))\r
+#define PWM_FPE_FPE1_Pos 8\r
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */\r
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))\r
+#define PWM_FPE_FPE2_Pos 16\r
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */\r
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))\r
+#define PWM_FPE_FPE3_Pos 24\r
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */\r
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))\r
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */\r
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */\r
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */\r
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */\r
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */\r
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */\r
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */\r
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */\r
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */\r
+/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */\r
+#define PWM_SSPR_SPRD_Pos 0\r
+#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */\r
+#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)))\r
+#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */\r
+/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */\r
+#define PWM_SSPUP_SPRDUP_Pos 0\r
+#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */\r
+#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)))\r
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */\r
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */\r
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */\r
+/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */\r
+#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */\r
+#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */\r
+#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */\r
+#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */\r
+#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */\r
+#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */\r
+#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */\r
+#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */\r
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */\r
+#define PWM_WPCR_WPCMD_Pos 0\r
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */\r
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))\r
+#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */\r
+#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */\r
+#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */\r
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */\r
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */\r
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */\r
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */\r
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */\r
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */\r
+#define PWM_WPCR_WPKEY_Pos 8\r
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */\r
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))\r
+#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */\r
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */\r
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */\r
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPVSRC_Pos 16\r
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */\r
+/* -------- PWM_VERSION : (PWM Offset: 0xFC) Version Register -------- */\r
+#define PWM_VERSION_VERSION_Pos 0\r
+#define PWM_VERSION_VERSION_Msk (0xfffu << PWM_VERSION_VERSION_Pos) /**< \brief (PWM_VERSION) Version of the Hardware Module */\r
+#define PWM_VERSION_MFN_Pos 16\r
+#define PWM_VERSION_MFN_Msk (0x7u << PWM_VERSION_MFN_Pos) /**< \brief (PWM_VERSION) Metal Fix Number */\r
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */\r
+#define PWM_CMPV_CV_Pos 0\r
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */\r
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))\r
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */\r
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */\r
+#define PWM_CMPVUPD_CVUPD_Pos 0\r
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */\r
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))\r
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */\r
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */\r
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */\r
+#define PWM_CMPM_CTR_Pos 4\r
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */\r
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))\r
+#define PWM_CMPM_CPR_Pos 8\r
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */\r
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))\r
+#define PWM_CMPM_CPRCNT_Pos 12\r
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */\r
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))\r
+#define PWM_CMPM_CUPR_Pos 16\r
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */\r
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))\r
+#define PWM_CMPM_CUPRCNT_Pos 20\r
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */\r
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))\r
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */\r
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */\r
+#define PWM_CMPMUPD_CTRUPD_Pos 4\r
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */\r
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))\r
+#define PWM_CMPMUPD_CPRUPD_Pos 8\r
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */\r
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))\r
+#define PWM_CMPMUPD_CUPRUPD_Pos 16\r
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */\r
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))\r
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */\r
+#define PWM_CMR_CPRE_Pos 0\r
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */\r
+#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)))\r
+#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */\r
+#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */\r
+#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */\r
+#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */\r
+#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */\r
+#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */\r
+#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */\r
+#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */\r
+#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */\r
+#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */\r
+#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */\r
+#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */\r
+#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */\r
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */\r
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */\r
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */\r
+#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */\r
+#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */\r
+#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */\r
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */\r
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */\r
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */\r
+#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */\r
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */\r
+#define PWM_CDTY_CDTY_Pos 0\r
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */\r
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))\r
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */\r
+#define PWM_CDTYUPD_CDTYUPD_Pos 0\r
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */\r
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))\r
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */\r
+#define PWM_CPRD_CPRD_Pos 0\r
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */\r
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))\r
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */\r
+#define PWM_CPRDUPD_CPRDUPD_Pos 0\r
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */\r
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))\r
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */\r
+#define PWM_CCNT_CNT_Pos 0\r
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */\r
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */\r
+#define PWM_DT_DTH_Pos 0\r
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */\r
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))\r
+#define PWM_DT_DTL_Pos 16\r
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */\r
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))\r
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */\r
+#define PWM_DTUPD_DTHUPD_Pos 0\r
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */\r
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))\r
+#define PWM_DTUPD_DTLUPD_Pos 16\r
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */\r
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))\r
+/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */\r
+#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */\r
+#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */\r
+/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */\r
+#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */\r
+#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */\r
+/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */\r
+#define PWM_ETRG1_MAXCNT_Pos 0\r
+#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */\r
+#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)))\r
+#define PWM_ETRG1_TRGMODE_Pos 24\r
+#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */\r
+#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)))\r
+#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */\r
+#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */\r
+#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */\r
+#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */\r
+#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */\r
+#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */\r
+#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */\r
+#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */\r
+#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */\r
+#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */\r
+/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */\r
+#define PWM_LEBR1_LEBDELAY_Pos 0\r
+#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */\r
+#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)))\r
+#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */\r
+#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */\r
+#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */\r
+#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */\r
+/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */\r
+#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */\r
+#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */\r
+/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */\r
+#define PWM_ETRG2_MAXCNT_Pos 0\r
+#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */\r
+#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)))\r
+#define PWM_ETRG2_TRGMODE_Pos 24\r
+#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */\r
+#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)))\r
+#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */\r
+#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */\r
+#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */\r
+#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */\r
+#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */\r
+#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */\r
+#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */\r
+#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */\r
+#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */\r
+#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */\r
+/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */\r
+#define PWM_LEBR2_LEBDELAY_Pos 0\r
+#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */\r
+#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)))\r
+#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */\r
+#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */\r
+#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */\r
+#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */\r
+/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */\r
+#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */\r
+#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_PWM_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_QSPI_COMPONENT_\r
+#define _SAMA5D2_QSPI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_QSPI Quad Serial Peripheral Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Qspi hardware registers */\r
+typedef struct {\r
+ __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */\r
+ __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */\r
+ __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */\r
+ __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */\r
+ __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */\r
+ __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */\r
+ __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */\r
+ __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */\r
+ __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */\r
+ __I uint32_t Reserved1[3];\r
+ __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */\r
+ __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */\r
+ __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */\r
+ __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */\r
+ __I uint32_t Reserved3[39];\r
+ __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved4[4];\r
+ __I uint32_t QSPI_VERSION; /**< \brief (Qspi Offset: 0x00FC) Version Register */\r
+} Qspi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */\r
+#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */\r
+#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */\r
+#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */\r
+#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */\r
+/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */\r
+#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */\r
+#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */\r
+#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */\r
+#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */\r
+#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */\r
+#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */\r
+#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */\r
+#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */\r
+#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */\r
+#define QSPI_MR_SMRM (0x1u << 3) /**< \brief (QSPI_MR) Serial Memory Register Mode */\r
+#define QSPI_MR_CSMODE_Pos 4\r
+#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */\r
+#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)))\r
+#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */\r
+#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */\r
+#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */\r
+#define QSPI_MR_NBBITS_Pos 8\r
+#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */\r
+#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)))\r
+#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */\r
+#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */\r
+#define QSPI_MR_DLYBCT_Pos 16\r
+#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */\r
+#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)))\r
+#define QSPI_MR_DLYCS_Pos 24\r
+#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */\r
+#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)))\r
+/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */\r
+#define QSPI_RDR_RD_Pos 0\r
+#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */\r
+/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */\r
+#define QSPI_TDR_TD_Pos 0\r
+#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */\r
+#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)))\r
+/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */\r
+#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */\r
+#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */\r
+#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */\r
+#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */\r
+#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */\r
+#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */\r
+#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */\r
+#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */\r
+/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */\r
+#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */\r
+#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */\r
+#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */\r
+#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */\r
+#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */\r
+#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */\r
+#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */\r
+/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */\r
+#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */\r
+#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */\r
+#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */\r
+#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */\r
+#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */\r
+#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */\r
+#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */\r
+/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */\r
+#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */\r
+#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */\r
+#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */\r
+#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */\r
+#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */\r
+#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */\r
+/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */\r
+#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */\r
+#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */\r
+#define QSPI_SCR_SCBR_Pos 8\r
+#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */\r
+#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)))\r
+#define QSPI_SCR_DLYBS_Pos 16\r
+#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */\r
+#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)))\r
+/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */\r
+#define QSPI_IAR_ADDR_Pos 0\r
+#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */\r
+#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)))\r
+/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */\r
+#define QSPI_ICR_INST_Pos 0\r
+#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */\r
+#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)))\r
+#define QSPI_ICR_OPT_Pos 16\r
+#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */\r
+#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)))\r
+/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */\r
+#define QSPI_IFR_WIDTH_Pos 0\r
+#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */\r
+#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)))\r
+#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */\r
+#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */\r
+#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */\r
+#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */\r
+#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */\r
+#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */\r
+#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */\r
+#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */\r
+#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */\r
+#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */\r
+#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */\r
+#define QSPI_IFR_OPTL_Pos 8\r
+#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */\r
+#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)))\r
+#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */\r
+#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */\r
+#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */\r
+#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */\r
+#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */\r
+#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */\r
+#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */\r
+#define QSPI_IFR_TFRTYP_Pos 12\r
+#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */\r
+#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)))\r
+#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */\r
+#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */\r
+#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */\r
+#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */\r
+#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */\r
+#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */\r
+#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */\r
+#define QSPI_IFR_NBDUM_Pos 16\r
+#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */\r
+#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)))\r
+/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */\r
+#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */\r
+#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */\r
+#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */\r
+#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */\r
+/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */\r
+#define QSPI_SKR_USRK_Pos 0\r
+#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */\r
+#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)))\r
+/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */\r
+#define QSPI_WPMR_WPKEY_Pos 8\r
+#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */\r
+#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)))\r
+#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */\r
+/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */\r
+#define QSPI_WPSR_WPVSRC_Pos 8\r
+#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */\r
+/* -------- QSPI_VERSION : (QSPI Offset: 0x00FC) Version Register -------- */\r
+#define QSPI_VERSION_VERSION_Pos 0\r
+#define QSPI_VERSION_VERSION_Msk (0xfffu << QSPI_VERSION_VERSION_Pos) /**< \brief (QSPI_VERSION) Hardware Module Version */\r
+#define QSPI_VERSION_MFN_Pos 16\r
+#define QSPI_VERSION_MFN_Msk (0x7u << QSPI_VERSION_MFN_Pos) /**< \brief (QSPI_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_QSPI_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_RSTC_COMPONENT_\r
+#define _SAMA5D2_RSTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Reset Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_RSTC Reset Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rstc hardware registers */\r
+typedef struct {\r
+ __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */\r
+ __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */\r
+ __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */\r
+} Rstc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */\r
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */\r
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */\r
+#define RSTC_CR_KEY_Pos 24\r
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Write Access Password */\r
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))\r
+#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation.Always reads as 0. */\r
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */\r
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */\r
+#define RSTC_SR_RSTTYP_Pos 8\r
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */\r
+#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) Both VDDCORE and VDDBU rising */\r
+#define RSTC_SR_RSTTYP_WKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) VDDCORE rising */\r
+#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */\r
+#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */\r
+#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */\r
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */\r
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */\r
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */\r
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */\r
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */\r
+#define RSTC_MR_KEY_Pos 24\r
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */\r
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))\r
+#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_RSTC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_RTC_COMPONENT_\r
+#define _SAMA5D2_RTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Clock */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_RTC Real-time Clock */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief RtcTs hardware registers */\r
+typedef struct {\r
+ __I uint32_t RTC_TSTR; /**< \brief (RtcTs Offset: 0x0) TimeStamp Time Register 0 */\r
+ __I uint32_t RTC_TSDR; /**< \brief (RtcTs Offset: 0x4) TimeStamp Date Register 0 */\r
+ __I uint32_t RTC_TSSR; /**< \brief (RtcTs Offset: 0x8) TimeStamp Source Register 0 */\r
+} RtcTs;\r
+/** \brief Rtc hardware registers */\r
+#define RTCTS_NUMBER 2\r
+typedef struct {\r
+ __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */\r
+ __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */\r
+ __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */\r
+ __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */\r
+ __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */\r
+ __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */\r
+ __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */\r
+ __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */\r
+ __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */\r
+ __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */\r
+ __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */\r
+ __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */\r
+ __I uint32_t Reserved1[32];\r
+ RtcTs RTC_TS[RTCTS_NUMBER]; /**< \brief (Rtc Offset: 0xB0) 0 .. 1 */\r
+ __I uint32_t Reserved2[2];\r
+ __I uint32_t RTC_MSR; /**< \brief (Rtc Offset: 0xD0) Milliseconds Register */\r
+ __I uint32_t Reserved3[4];\r
+ __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t Reserved4[5];\r
+ __I uint32_t RTC_VERSION; /**< \brief (Rtc Offset: 0xFC) Version Register */\r
+} Rtc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */\r
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */\r
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */\r
+#define RTC_CR_TIMEVSEL_Pos 8\r
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */\r
+#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)))\r
+#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */\r
+#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */\r
+#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */\r
+#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */\r
+#define RTC_CR_CALEVSEL_Pos 16\r
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */\r
+#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)))\r
+#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */\r
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */\r
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */\r
+#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */\r
+#define RTC_MR_UTC (0x1u << 2) /**< \brief (RTC_MR) UTC Time Format */\r
+#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */\r
+#define RTC_MR_CORRECTION_Pos 8\r
+#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */\r
+#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))\r
+#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */\r
+#define RTC_MR_OUT0_Pos 16\r
+#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) All ADC Channel Trigger Event Source Selection */\r
+#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)))\r
+#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */\r
+#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */\r
+#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */\r
+#define RTC_MR_OUT1_Pos 20\r
+#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) ADC Last Channel Trigger Event Source Selection */\r
+#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)))\r
+#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */\r
+#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */\r
+#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */\r
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */\r
+#define RTC_TIMR_SEC_Pos 0\r
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */\r
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))\r
+#define RTC_TIMR_MIN_Pos 8\r
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */\r
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))\r
+#define RTC_TIMR_HOUR_Pos 16\r
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */\r
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))\r
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */\r
+#define RTC_TIMR_UTC_TIME_Pos 0\r
+#define RTC_TIMR_UTC_TIME_Msk (0xffffffffu << RTC_TIMR_UTC_TIME_Pos) /**< \brief (RTC_TIMR) Current UTC Time */\r
+#define RTC_TIMR_UTC_TIME(value) ((RTC_TIMR_UTC_TIME_Msk & ((value) << RTC_TIMR_UTC_TIME_Pos)))\r
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */\r
+#define RTC_CALR_CENT_Pos 0\r
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */\r
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))\r
+#define RTC_CALR_YEAR_Pos 8\r
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */\r
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))\r
+#define RTC_CALR_MONTH_Pos 16\r
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */\r
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))\r
+#define RTC_CALR_DAY_Pos 21\r
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */\r
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))\r
+#define RTC_CALR_DATE_Pos 24\r
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */\r
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))\r
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */\r
+#define RTC_TIMALR_SEC_Pos 0\r
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */\r
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))\r
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */\r
+#define RTC_TIMALR_MIN_Pos 8\r
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */\r
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))\r
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */\r
+#define RTC_TIMALR_HOUR_Pos 16\r
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */\r
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))\r
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */\r
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */\r
+#define RTC_TIMALR_UTC_TIME_Pos 0\r
+#define RTC_TIMALR_UTC_TIME_Msk (0xffffffffu << RTC_TIMALR_UTC_TIME_Pos) /**< \brief (RTC_TIMALR) UTC_TIME Alarm */\r
+#define RTC_TIMALR_UTC_TIME(value) ((RTC_TIMALR_UTC_TIME_Msk & ((value) << RTC_TIMALR_UTC_TIME_Pos)))\r
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */\r
+#define RTC_CALALR_MONTH_Pos 16\r
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */\r
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))\r
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */\r
+#define RTC_CALALR_DATE_Pos 24\r
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */\r
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))\r
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */\r
+#define RTC_CALALR_UTCEN (0x1u << 0) /**< \brief (RTC_CALALR) UTC Alarm Enable */\r
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */\r
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */\r
+#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */\r
+#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */\r
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */\r
+#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */\r
+#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */\r
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */\r
+#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */\r
+#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */\r
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */\r
+#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */\r
+#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */\r
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */\r
+#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */\r
+#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */\r
+#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */\r
+#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */\r
+#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */\r
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */\r
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */\r
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */\r
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */\r
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */\r
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */\r
+#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */\r
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */\r
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */\r
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */\r
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */\r
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */\r
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */\r
+#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */\r
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */\r
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */\r
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */\r
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */\r
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */\r
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */\r
+#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */\r
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */\r
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */\r
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */\r
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */\r
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */\r
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */\r
+#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */\r
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */\r
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */\r
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */\r
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */\r
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */\r
+/* -------- RTC_TSTR : (RTC Offset: N/A) TimeStamp Time Register 0 -------- */\r
+#define RTC_TSTR_SEC_Pos 0\r
+#define RTC_TSTR_SEC_Msk (0x7fu << RTC_TSTR_SEC_Pos) /**< \brief (RTC_TSTR) Seconds of the Tamper */\r
+#define RTC_TSTR_MIN_Pos 8\r
+#define RTC_TSTR_MIN_Msk (0x7fu << RTC_TSTR_MIN_Pos) /**< \brief (RTC_TSTR) Minutes of the Tamper */\r
+#define RTC_TSTR_HOUR_Pos 16\r
+#define RTC_TSTR_HOUR_Msk (0x3fu << RTC_TSTR_HOUR_Pos) /**< \brief (RTC_TSTR) Hours of the Tamper */\r
+#define RTC_TSTR_AMPM (0x1u << 22) /**< \brief (RTC_TSTR) AM/PM Indicator of the Tamper */\r
+#define RTC_TSTR_TEVCNT_Pos 24\r
+#define RTC_TSTR_TEVCNT_Msk (0xfu << RTC_TSTR_TEVCNT_Pos) /**< \brief (RTC_TSTR) Tamper Events Counter */\r
+#define RTC_TSTR_BACKUP (0x1u << 31) /**< \brief (RTC_TSTR) System Mode of the Tamper */\r
+/* -------- RTC_TSDR : (RTC Offset: N/A) TimeStamp Date Register 0 -------- */\r
+#define RTC_TSDR_CENT_Pos 0\r
+#define RTC_TSDR_CENT_Msk (0x7fu << RTC_TSDR_CENT_Pos) /**< \brief (RTC_TSDR) Century of the Tamper */\r
+#define RTC_TSDR_YEAR_Pos 8\r
+#define RTC_TSDR_YEAR_Msk (0xffu << RTC_TSDR_YEAR_Pos) /**< \brief (RTC_TSDR) Year of the Tamper */\r
+#define RTC_TSDR_MONTH_Pos 16\r
+#define RTC_TSDR_MONTH_Msk (0x1fu << RTC_TSDR_MONTH_Pos) /**< \brief (RTC_TSDR) Month of the Tamper */\r
+#define RTC_TSDR_DAY_Pos 21\r
+#define RTC_TSDR_DAY_Msk (0x7u << RTC_TSDR_DAY_Pos) /**< \brief (RTC_TSDR) Day of the Tamper */\r
+#define RTC_TSDR_DATE_Pos 24\r
+#define RTC_TSDR_DATE_Msk (0x3fu << RTC_TSDR_DATE_Pos) /**< \brief (RTC_TSDR) Date of the Tamper */\r
+#define RTC_TSDR_UTC_TIME_Pos 0\r
+#define RTC_TSDR_UTC_TIME_Msk (0xffffffffu << RTC_TSDR_UTC_TIME_Pos) /**< \brief (RTC_TSDR) Time of the Tamper (UTC format) */\r
+/* -------- RTC_TSSR : (RTC Offset: N/A) TimeStamp Source Register 0 -------- */\r
+#define RTC_TSSR_SHLDM (0x1u << 0) /**< \brief (RTC_TSSR) Shield Monitor */\r
+#define RTC_TSSR_DBLFM (0x1u << 1) /**< \brief (RTC_TSSR) Double Frequency Monitor */\r
+#define RTC_TSSR_TST (0x1u << 2) /**< \brief (RTC_TSSR) Test Pin Monitor */\r
+#define RTC_TSSR_JTAG (0x1u << 3) /**< \brief (RTC_TSSR) JTAG Pins Monitor */\r
+#define RTC_TSSR_REGUL (0x1u << 4) /**< \brief (RTC_TSSR) Core Regulator Disconnection Monitor */\r
+#define RTC_TSSR_MCKM (0x1u << 5) /**< \brief (RTC_TSSR) Master Clock Monitor */\r
+#define RTC_TSSR_TPML (0x1u << 6) /**< \brief (RTC_TSSR) Low Temperature Monitor */\r
+#define RTC_TSSR_TPMH (0x1u << 7) /**< \brief (RTC_TSSR) High Temperature Monitor */\r
+#define RTC_TSSR_VDDRL (0x1u << 8) /**< \brief (RTC_TSSR) Low VDDDDR Voltage Monitor */\r
+#define RTC_TSSR_VDDRH (0x1u << 9) /**< \brief (RTC_TSSR) High VDDDDR Voltage Monitor */\r
+#define RTC_TSSR_VDDBUL (0x1u << 10) /**< \brief (RTC_TSSR) Low VDDBU Voltage Monitor */\r
+#define RTC_TSSR_VDDBUH (0x1u << 11) /**< \brief (RTC_TSSR) High VDDBU Voltage Monitor */\r
+#define RTC_TSSR_VDDCOREL (0x1u << 12) /**< \brief (RTC_TSSR) Low VDDCORE Voltage Monitor */\r
+#define RTC_TSSR_VDDCOREH (0x1u << 13) /**< \brief (RTC_TSSR) High VDDCORE Voltage Monitor */\r
+#define RTC_TSSR_VDDIOL (0x1u << 14) /**< \brief (RTC_TSSR) Low VDDIO Voltage Monitor */\r
+#define RTC_TSSR_VDDIOH (0x1u << 15) /**< \brief (RTC_TSSR) High VDDIO Voltage Monitor */\r
+#define RTC_TSSR_DET0 (0x1u << 16) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */\r
+#define RTC_TSSR_DET1 (0x1u << 17) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */\r
+#define RTC_TSSR_DET2 (0x1u << 18) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */\r
+#define RTC_TSSR_DET3 (0x1u << 19) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */\r
+#define RTC_TSSR_DET4 (0x1u << 20) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */\r
+#define RTC_TSSR_DET5 (0x1u << 21) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */\r
+#define RTC_TSSR_DET6 (0x1u << 22) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */\r
+#define RTC_TSSR_DET7 (0x1u << 23) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */\r
+/* -------- RTC_MSR : (RTC Offset: 0xD0) Milliseconds Register -------- */\r
+#define RTC_MSR_MS_Pos 0\r
+#define RTC_MSR_MS_Msk (0x3ffu << RTC_MSR_MS_Pos) /**< \brief (RTC_MSR) Number of 1/1024 seconds elapsed within 1 second */\r
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */\r
+#define RTC_WPMR_WPKEY_Pos 8\r
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */\r
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))\r
+#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- RTC_VERSION : (RTC Offset: 0xFC) Version Register -------- */\r
+#define RTC_VERSION_VERSION_Pos 0\r
+#define RTC_VERSION_VERSION_Msk (0xfffu << RTC_VERSION_VERSION_Pos) /**< \brief (RTC_VERSION) Version of the Hardware Module */\r
+#define RTC_VERSION_MFN_Pos 16\r
+#define RTC_VERSION_MFN_Msk (0x7u << RTC_VERSION_MFN_Pos) /**< \brief (RTC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_RTC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_RXLP_COMPONENT_\r
+#define _SAMA5D2_RXLP_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Low Power Asynchronous Receiver */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_RXLP Low Power Asynchronous Receiver */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rxlp hardware registers */\r
+typedef struct {\r
+ __O uint32_t RXLP_CR; /**< \brief (Rxlp Offset: 0x0000) Control Register */\r
+ __IO uint32_t RXLP_MR; /**< \brief (Rxlp Offset: 0x0004) Mode Register */\r
+ __I uint32_t Reserved1[4];\r
+ __I uint32_t RXLP_RHR; /**< \brief (Rxlp Offset: 0x0018) Receive Holding Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t RXLP_BRGR; /**< \brief (Rxlp Offset: 0x0020) Baud Rate Generator Register */\r
+ __IO uint32_t RXLP_CMPR; /**< \brief (Rxlp Offset: 0x0024) Comparison Register */\r
+ __I uint32_t Reserved3[47];\r
+ __IO uint32_t RXLP_WPMR; /**< \brief (Rxlp Offset: 0x00E4) Write Protection Mode Register */\r
+ __I uint32_t Reserved4[5];\r
+ __I uint32_t RXLP_VERSION; /**< \brief (Rxlp Offset: 0x00FC) Version Register */\r
+} Rxlp;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RXLP_CR : (RXLP Offset: 0x0000) Control Register -------- */\r
+#define RXLP_CR_RSTRX (0x1u << 2) /**< \brief (RXLP_CR) Reset Receiver */\r
+#define RXLP_CR_RXEN (0x1u << 4) /**< \brief (RXLP_CR) Receiver Enable */\r
+#define RXLP_CR_RXDIS (0x1u << 5) /**< \brief (RXLP_CR) Receiver Disable */\r
+/* -------- RXLP_MR : (RXLP Offset: 0x0004) Mode Register -------- */\r
+#define RXLP_MR_FILTER (0x1u << 4) /**< \brief (RXLP_MR) Receiver Digital Filter */\r
+#define RXLP_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (RXLP_MR) RXLP does not filter the receive line. */\r
+#define RXLP_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (RXLP_MR) RXLP filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */\r
+#define RXLP_MR_PAR_Pos 9\r
+#define RXLP_MR_PAR_Msk (0x7u << RXLP_MR_PAR_Pos) /**< \brief (RXLP_MR) Parity Type */\r
+#define RXLP_MR_PAR(value) ((RXLP_MR_PAR_Msk & ((value) << RXLP_MR_PAR_Pos)))\r
+#define RXLP_MR_PAR_EVEN (0x0u << 9) /**< \brief (RXLP_MR) Even Parity */\r
+#define RXLP_MR_PAR_ODD (0x1u << 9) /**< \brief (RXLP_MR) Odd Parity */\r
+#define RXLP_MR_PAR_SPACE (0x2u << 9) /**< \brief (RXLP_MR) Parity forced to 0 */\r
+#define RXLP_MR_PAR_MARK (0x3u << 9) /**< \brief (RXLP_MR) Parity forced to 1 */\r
+#define RXLP_MR_PAR_NO (0x4u << 9) /**< \brief (RXLP_MR) No parity */\r
+/* -------- RXLP_RHR : (RXLP Offset: 0x0018) Receive Holding Register -------- */\r
+#define RXLP_RHR_RXCHR_Pos 0\r
+#define RXLP_RHR_RXCHR_Msk (0xffu << RXLP_RHR_RXCHR_Pos) /**< \brief (RXLP_RHR) Received Character */\r
+/* -------- RXLP_BRGR : (RXLP Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define RXLP_BRGR_CD_Pos 0\r
+#define RXLP_BRGR_CD_Msk (0x3u << RXLP_BRGR_CD_Pos) /**< \brief (RXLP_BRGR) Clock Divisor */\r
+#define RXLP_BRGR_CD(value) ((RXLP_BRGR_CD_Msk & ((value) << RXLP_BRGR_CD_Pos)))\r
+/* -------- RXLP_CMPR : (RXLP Offset: 0x0024) Comparison Register -------- */\r
+#define RXLP_CMPR_VAL1_Pos 0\r
+#define RXLP_CMPR_VAL1_Msk (0xffu << RXLP_CMPR_VAL1_Pos) /**< \brief (RXLP_CMPR) First Comparison Value for Received Character */\r
+#define RXLP_CMPR_VAL1(value) ((RXLP_CMPR_VAL1_Msk & ((value) << RXLP_CMPR_VAL1_Pos)))\r
+#define RXLP_CMPR_VAL2_Pos 16\r
+#define RXLP_CMPR_VAL2_Msk (0xffu << RXLP_CMPR_VAL2_Pos) /**< \brief (RXLP_CMPR) Second Comparison Value for Received Character */\r
+#define RXLP_CMPR_VAL2(value) ((RXLP_CMPR_VAL2_Msk & ((value) << RXLP_CMPR_VAL2_Pos)))\r
+/* -------- RXLP_WPMR : (RXLP Offset: 0x00E4) Write Protection Mode Register -------- */\r
+#define RXLP_WPMR_WPEN (0x1u << 0) /**< \brief (RXLP_WPMR) Write Protection Enable */\r
+#define RXLP_WPMR_WPKEY_Pos 8\r
+#define RXLP_WPMR_WPKEY_Msk (0xffffffu << RXLP_WPMR_WPKEY_Pos) /**< \brief (RXLP_WPMR) Write Protection Key */\r
+#define RXLP_WPMR_WPKEY(value) ((RXLP_WPMR_WPKEY_Msk & ((value) << RXLP_WPMR_WPKEY_Pos)))\r
+#define RXLP_WPMR_WPKEY_PASSWD (0x52584Cu << 8) /**< \brief (RXLP_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */\r
+/* -------- RXLP_VERSION : (RXLP Offset: 0x00FC) Version Register -------- */\r
+#define RXLP_VERSION_VERSION_Pos 0\r
+#define RXLP_VERSION_VERSION_Msk (0xfffu << RXLP_VERSION_VERSION_Pos) /**< \brief (RXLP_VERSION) Hardware Module Version */\r
+#define RXLP_VERSION_MFN_Pos 16\r
+#define RXLP_VERSION_MFN_Msk (0x7u << RXLP_VERSION_MFN_Pos) /**< \brief (RXLP_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_RXLP_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SCKC_COMPONENT_\r
+#define _SAMA5D2_SCKC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Slow Clock Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SCKC Slow Clock Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Sckc hardware registers */\r
+typedef struct {\r
+ __IO uint32_t SCKC_CR; /**< \brief (Sckc Offset: 0x0) Slow Clock Controller Configuration Register */\r
+} Sckc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SCKC_CR : (SCKC Offset: 0x0) Slow Clock Controller Configuration Register -------- */\r
+#define SCKC_CR_OSCSEL (0x1u << 3) /**< \brief (SCKC_CR) Slow Clock Selector */\r
+#define SCKC_CR_OSCSEL_RC (0x0u << 3) /**< \brief (SCKC_CR) Slow clock is the embedded 64 kHz (typical) RC oscillator. */\r
+#define SCKC_CR_OSCSEL_XTAL (0x1u << 3) /**< \brief (SCKC_CR) Slow clock is the 32.768 kHz crystal oscillator. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_SCKC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SDMMC_COMPONENT_\r
+#define _SAMA5D2_SDMMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Secure Digital MultiMedia Card Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SDMMC Secure Digital MultiMedia Card Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief SDMMC hardware registers */\r
+typedef struct {\r
+ __IO uint32_t SDMMC_SSAR; /**< \brief (SDMMC Offset: 0x000) SDMA System Address - Argument 2 Register */\r
+ __IO uint16_t SDMMC_BSR; /**< \brief (SDMMC Offset: 0x004) Block Size Register */\r
+ __IO uint16_t SDMMC_BCR; /**< \brief (SDMMC Offset: 0x006) Block Count Register */\r
+ __IO uint32_t SDMMC_ARG1R; /**< \brief (SDMMC Offset: 0x008) Argument 1 Register */\r
+ __IO uint16_t SDMMC_TMR; /**< \brief (SDMMC Offset: 0x00C) Transfer Mode Register */\r
+ __IO uint16_t SDMMC_CR; /**< \brief (SDMMC Offset: 0x00E) Command Register */\r
+ __I uint32_t SDMMC_RR[4]; /**< \brief (SDMMC Offset: 0x010) Response Register */\r
+ __IO uint32_t SDMMC_BDPR; /**< \brief (SDMMC Offset: 0x020) Buffer Data Port Register */\r
+ __I uint32_t SDMMC_PSR; /**< \brief (SDMMC Offset: 0x024) Present State Register */\r
+ __IO uint8_t SDMMC_HC1R; /**< \brief (SDMMC Offset: 0x028) Host Control 1 Register */\r
+ __IO uint8_t SDMMC_PCR; /**< \brief (SDMMC Offset: 0x029) Power Control Register */\r
+ __IO uint8_t SDMMC_BGCR; /**< \brief (SDMMC Offset: 0x02A) Block Gap Control Register */\r
+ __IO uint8_t SDMMC_WCR; /**< \brief (SDMMC Offset: 0x02B) Wakeup Control Register */\r
+ __IO uint16_t SDMMC_CCR; /**< \brief (SDMMC Offset: 0x02C) Clock Control Register */\r
+ __IO uint8_t SDMMC_TCR; /**< \brief (SDMMC Offset: 0x02E) Timeout Control Register */\r
+ __IO uint8_t SDMMC_SRR; /**< \brief (SDMMC Offset: 0x02F) Software Reset Register */\r
+ __IO uint16_t SDMMC_NISTR; /**< \brief (SDMMC Offset: 0x030) Normal Interrupt Status Register */\r
+ __IO uint16_t SDMMC_EISTR; /**< \brief (SDMMC Offset: 0x032) Error Interrupt Status Register */\r
+ __IO uint16_t SDMMC_NISTER; /**< \brief (SDMMC Offset: 0x034) Normal Interrupt Status Enable Register */\r
+ __IO uint16_t SDMMC_EISTER; /**< \brief (SDMMC Offset: 0x036) Error Interrupt Status Enable Register */\r
+ __IO uint16_t SDMMC_NISIER; /**< \brief (SDMMC Offset: 0x038) Normal Interrupt Signal Enable Register */\r
+ __IO uint16_t SDMMC_EISIER; /**< \brief (SDMMC Offset: 0x03A) Error Interrupt Signal Enable Register */\r
+ __I uint16_t SDMMC_ACESR; /**< \brief (SDMMC Offset: 0x03C) Auto CMD Error Status Register */\r
+ __IO uint16_t SDMMC_HC2R; /**< \brief (SDMMC Offset: 0x03E) Host Control 2 Register */\r
+ __IO uint32_t SDMMC_CA0R; /**< \brief (SDMMC Offset: 0x040) Capabilities Register */\r
+ __IO uint32_t SDMMC_CA1R; /**< \brief (SDMMC Offset: 0x044) Capabilities Register */\r
+ __IO uint32_t SDMMC_MCCAR; /**< \brief (SDMMC Offset: 0x048) Maximum Current Capabilities Register */\r
+ __I uint32_t SDMMC_RSVD1; /**< \brief (SDMMC Offset: 0x04C) Reserved */\r
+ __O uint16_t SDMMC_FERACES; /**< \brief (SDMMC Offset: 0x050) Force Event Register for Auto CMD Error Status */\r
+ __O uint16_t SDMMC_FEREIS; /**< \brief (SDMMC Offset: 0x052) Force Event Register for Error Interrupt Status */\r
+ __I uint8_t SDMMC_AESR; /**< \brief (SDMMC Offset: 0x054) ADMA Error Status Register */\r
+ __I uint8_t SDMMC_RSVD2[3]; /**< \brief (SDMMC Offset: 0x055 - 0x57) Reserved */\r
+ __IO uint32_t SDMMC_ASA0R; /**< \brief (SDMMC Offset: 0x058) ADMA System Address Register */\r
+ __I uint32_t SDMMC_RSVD3[1]; /**< \brief (SDMMC Offset: 0x05C) Reserved */\r
+ __IO uint16_t SDMMC_PVR[8]; /**< \brief (SDMMC Offset: 0x060) Preset Value Register */\r
+ __I uint32_t SDMMC_RSVD4[35]; /**< \brief (SDMMC Offset: 0x070 - 0xF8) Reserved */\r
+ __I uint16_t SDMMC_SISR; /**< \brief (SDMMC Offset: 0x0FC) Slot Interrupt Status Register */\r
+ __I uint16_t SDMMC_HCVR; /**< \brief (SDMMC Offset: 0x0FE) Host Controller Version Register */\r
+\r
+ __I uint32_t SDMMC_RSVD5[64]; /**< \brief (SDMMC Offset: 0x100 - 0x1FC) Reserved */\r
+\r
+ __I uint32_t SDMMC_APSR; /**< \brief (SDMMC Offset: 0x200) Additionnal Present State Register */\r
+ __IO uint8_t SDMMC_MC1R; /**< \brief (SDMMC Offset: 0x204) MMC Control 1 Register */\r
+ __O uint8_t SDMMC_MC2R; /**< \brief (SDMMC Offset: 0x205) MMC Control 2 Register */\r
+ __I uint8_t SDMMC_RSVD6[2]; /**< \brief (SDMMC Offset: 0x206 - 0x207) Reserved */\r
+ __IO uint32_t SDMMC_ACR; /**< \brief (SDMMC Offset: 0x208) AHB Control Register */\r
+ __IO uint32_t SDMMC_CC2R; /**< \brief (SDMMC Offset: 0x20C) Clock Control 2 Register */\r
+ __IO uint8_t SDMMC_RTC1R; /**< \brief (SDMMC Offset: 0x210) Retuning Timer Control 1 Register */\r
+ __O uint8_t SDMMC_RTC2R; /**< \brief (SDMMC Offset: 0x211) Retuning Timer Control 2 Register */\r
+ __I uint8_t SDMMC_RSVD7[2]; /**< \brief (SDMMC Offset: 0x212 - 0x213) Reserved */\r
+ __IO uint32_t SDMMC_RTCVR; /**< \brief (SDMMC Offset: 0x214) Retuning Timer Counter Value Register */\r
+ __IO uint8_t SDMMC_RTISTER; /**< \brief (SDMMC Offset: 0x218) Retuning Timer Interrupt Status Enable Register */\r
+ __IO uint8_t SDMMC_RTISIER; /**< \brief (SDMMC Offset: 0x219) Retuning Timer Interrupt Signal Enable Register */\r
+ __I uint8_t SDMMC_RSVD11[2]; /**< \brief (SDMMC Offset: 0x21A - 0x21B) Reserved */\r
+ __IO uint8_t SDMMC_RTISTR; /**< \brief (SDMMC Offset: 0x21C) Retuning Timer Interrupt Status Register */\r
+ __I uint8_t SDMMC_RTSSR; /**< \brief (SDMMC Offset: 0x21D) Retuning Timer Status Slots Register */\r
+ __I uint8_t SDMMC_RSVD12[2]; /**< \brief (SDMMC Offset: 0x21E - 0x21F) Reserved */\r
+ __IO uint32_t SDMMC_TUNCR; /**< \brief (SDMMC Offset: 0x220) Tuning Control Register */\r
+ __I uint32_t SDMMC_RSVD8[3]; /**< \brief (SDMMC Offset: 0x224 - 0x22C) Reserved */\r
+ __IO uint32_t SDMMC_CACR; /**< \brief (SDMMC Offset: 0x230) Capabilities Control Register */\r
+ __I uint32_t SDMMC_RSVD9[3]; /**< \brief (SDMMC Offset: 0x234 - 0x23C) Reserved */\r
+ __IO uint32_t SDMMC_CALCR; /**< \brief (SDMMC Offset: 0x240) Calibration Control Register */\r
+ __I uint32_t SDMMC_RSVD10[47]; /**< \brief (SDMMC Offset: 0x244 - 0x2FC) Reserved */\r
+} Sdmmc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* -------- SDMMC_SSAR (SDMMC Offset: 0x000) SDMA System Address - Argument 2 Register */\r
+#define SDMMC_SSAR_ADDR_Pos 0\r
+#define SDMMC_SSAR_ADDR_Msk (0xFFFFFFFFu << SDMMC_SSAR_ADDR_Pos)\r
+#define SDMMC_SSAR_ADDR(value) ((SDMMC_SSAR_ADDR_Msk & ((value) << SDMMC_SSAR_ADDR_Pos)))\r
+#define SDMMC_SSAR_ARG2_Pos 0\r
+#define SDMMC_SSAR_ARG2_Msk (0xFFFFFFFFu << SDMMC_SSAR_ARG2_Pos)\r
+#define SDMMC_SSAR_ARG2(value) ((SDMMC_SSAR_ARG2_Msk & ((value) << SDMMC_SSAR_ARG2_Pos)))\r
+/* -------- SDMMC_BSR (SDMMC Offset: 0x004) Block Size Register */\r
+#define SDMMC_BSR_BLKSIZE_Pos 0\r
+#define SDMMC_BSR_BLKSIZE_Msk (0xFFFu << SDMMC_BSR_BLKSIZE_Pos)\r
+#define SDMMC_BSR_BLKSIZE(value) ((SDMMC_BSR_BLKSIZE_Msk & ((value) << SDMMC_BSR_BLKSIZE_Pos)))\r
+#define SDMMC_BSR_BOUNDARY_Pos 12\r
+#define SDMMC_BSR_BOUNDARY_Msk (0x7u << SDMMC_BSR_BOUNDARY_Pos)\r
+#define SDMMC_BSR_BOUNDARY(value) ((SDMMC_BSR_BOUNDARY_Msk & ((value) << SDMMC_BSR_BOUNDARY_Pos)))\r
+/* -------- SDMMC_BCR (SDMMC Offset: 0x006) Block Count Register */\r
+#define SDMMC_BCR_BLKCNT_Pos 0\r
+#define SDMMC_BCR_BLKCNT_Msk (0xFFFFu << SDMMC_BCR_BLKCNT_Pos)\r
+#define SDMMC_BCR_BLKCNT(value) ((SDMMC_BCR_BLKCNT_Msk & ((value) << SDMMC_BCR_BLKCNT_Pos)))\r
+/* -------- SDMMC_ARG1R (SDMMC Offset: 0x008) Argument 1 Register */\r
+#define SDMMC_ARG1R_ARG1_Pos 0\r
+#define SDMMC_ARG1R_ARG1_Msk (0xFFFFFFFFu << SDMMC_ARG1R_ARG1_Pos)\r
+#define SDMMC_ARG1R_ARG1(value) ((SDMMC_ARG1R_ARG1_Msk & ((value) << SDMMC_ARG1R_ARG1_Pos)))\r
+/* -------- SDMMC_TMR (SDMMC Offset: 0x00C) Transfer Mode Register */\r
+#define SDMMC_TMR_DMAEN (0x1u << 0)\r
+#define SDMMC_TMR_BCEN (0x1u << 1)\r
+#define SDMMC_TMR_ACMDEN_Pos 2\r
+#define SDMMC_TMR_ACMDEN_Msk (0x3u << SDMMC_TMR_ACMDEN_Pos)\r
+#define SDMMC_TMR_ACMDEN_DIS (0x0u << 2)\r
+#define SDMMC_TMR_ACMDEN_ACMD12 (0x1u << 2)\r
+#define SDMMC_TMR_ACMDEN_ACMD23 (0x2u << 2)\r
+#define SDMMC_TMR_DTDSEL (0x1u << 4)\r
+#define SDMMC_TMR_DTDSEL_WR (0x0u << 4)\r
+#define SDMMC_TMR_DTDSEL_RD (0x1u << 4)\r
+#define SDMMC_TMR_MSBSEL (0x1u << 5)\r
+/* -------- SDMMC_CR (SDMMC Offset: 0x00E) Command Register */\r
+#define SDMMC_CR_RESPTYP_Pos 0\r
+#define SDMMC_CR_RESPTYP_Msk (0x3u << SDMMC_CR_RESPTYP_Pos)\r
+#define SDMMC_CR_RESPTYP_NORESP (0x0u << 0)\r
+#define SDMMC_CR_RESPTYP_RL136 (0x1u << 0)\r
+#define SDMMC_CR_RESPTYP_RL48 (0x2u << 0)\r
+#define SDMMC_CR_RESPTYP_RL48BUSY (0x3u << 0)\r
+#define SDMMC_CR_CMDCCEN (0x1u << 3)\r
+#define SDMMC_CR_CMDICEN (0x1u << 4)\r
+#define SDMMC_CR_DPSEL (0x1u << 5)\r
+#define SDMMC_CR_CMDTYP_Pos 6\r
+#define SDMMC_CR_CMDTYP_Msk (0x3u << SDMMC_CR_CMDTYP_Pos)\r
+#define SDMMC_CR_CMDTYP_NORMAL (0x0u << 6)\r
+#define SDMMC_CR_CMDTYP_SUSPEND (0x1u << 6)\r
+#define SDMMC_CR_CMDTYP_RESUME (0x2u << 6)\r
+#define SDMMC_CR_CMDTYP_ABORT (0x3u << 6)\r
+#define SDMMC_CR_CMDIDX_Pos 8\r
+#define SDMMC_CR_CMDIDX_Msk (0x3F << SDMMC_CR_CMDIDX_Pos)\r
+#define SDMMC_CR_CMDIDX(value) ((SDMMC_CR_CMDIDX_Msk & ((value) << SDMMC_CR_CMDIDX_Pos)))\r
+/* -------- SDMMC_RR[4] (SDMMC Offset: 0x010) Response Register */\r
+#define SDMMC_RR_CMDRESP_Pos 0\r
+#define SDMMC_RR_CMDRESP_Msk (0xFFFFFFFFu << SDMMC_RR_CMDRESP_Pos)\r
+/* -------- SDMMC_BDPR Buffer Data Port Register */\r
+#define SDMMC_BDPR_BUFDATA_Pos 0\r
+#define SDMMC_BDPR_BUFDATA_Msk (0xFFFFFFFFu << SDMMC_BDPR_BUFDATA_Pos)\r
+#define SDMMC_BDPR_BUFDATA(value) ((SDMMC_BDPR_BUFDATA_Msk & ((value) << SDMMC_BDPR_BUFDATA_Pos)))\r
+/* -------- SDMMC_PSR (SDMMC Offset: 0x024) Present State Register */\r
+#define SDMMC_PSR_CMDINHC (0x1u << 0)\r
+#define SDMMC_PSR_CMDINHD (0x1u << 1)\r
+#define SDMMC_PSR_DLACT (0x1u << 2)\r
+#define SDMMC_PSR_RTREQ (0x1u << 3)\r
+#define SDMMC_PSR_WTACT (0x1u << 8)\r
+#define SDMMC_PSR_RTACT (0x1u << 9)\r
+#define SDMMC_PSR_BUFWREN (0x1u << 10)\r
+#define SDMMC_PSR_BUFRDEN (0x1u << 11)\r
+#define SDMMC_PSR_CARDINS (0x1u << 16)\r
+#define SDMMC_PSR_CARDSS (0x1u << 17)\r
+#define SDMMC_PSR_CARDDPL (0x1u << 18)\r
+#define SDMMC_PSR_WRPPL (0x1u << 19)\r
+#define SDMMC_PSR_DATLL_Pos 20\r
+#define SDMMC_PSR_DATLL_Msk (0xFu << SDMMC_PSR_DATLL_Pos)\r
+#define SDMMC_PSR_CMDLL (0x1u << 24)\r
+/* -------- SDMMC_HC1R (SDMMC Offset: 0x028) Host Control 1 Register */\r
+#define SDMMC_HC1R_LEDCTRL (0x1u << 0)\r
+#define SDMMC_HC1R_DW (0x1u << 1)\r
+#define SDMMC_HC1R_HSEN (0x1u << 2)\r
+#define SDMMC_HC1R_DMASEL_Pos 3\r
+#define SDMMC_HC1R_DMASEL_Msk (0x3u << SDMMC_HC1R_DMASEL_Pos)\r
+#define SDMMC_HC1R_DMASEL_SDMA (0x0u << 3)\r
+#define SDMMC_HC1R_DMASEL_ADMA32 (0x2u << 3)\r
+#define SDMMC_HC1R_DMASEL_ADMA64 (0x3u << 3)\r
+#define SDMMC_HC1R_EXTDW (0x1u << 5)\r
+#define SDMMC_HC1R_CARDDTL (0x1u << 6)\r
+#define SDMMC_HC1R_CARDDSSEL (0x1u << 7)\r
+/* -------- SDMMC_PCR (SDMMC Offset: 0x029) Power Control Register */\r
+#define SDMMC_PCR_SDBPWR (0x1u << 0)\r
+#define SDMMC_PCR_SDBVSEL_Pos 1\r
+#define SDMMC_PCR_SDBVSEL_Msk (0x7u << SDMMC_PCR_SDBVSEL_Pos)\r
+#define SDMMC_PCR_SDBVSEL(value) ((SDMMC_PCR_SDBVSEL_Msk & ((value) << SDMMC_PCR_SDBVSEL_Pos)))\r
+/* -------- SDMMC_BGCR (SDMMC Offset: 0x02A) Block Gap Control Register */\r
+#define SDMMC_BGCR_STPBGR (0x1u << 0)\r
+#define SDMMC_BGCR_CONTR (0x1u << 1)\r
+#define SDMMC_BGCR_RWCTRL (0x1u << 2)\r
+#define SDMMC_BGCR_INTBG (0x1u << 3)\r
+/* -------- SDMMC_WCR (SDMMC Offset: 0x02B) Wakeup Control Register */\r
+#define SDMMC_WCR_WKENCINT (0x1u << 0)\r
+#define SDMMC_WCR_WKENCINS (0x1u << 1)\r
+#define SDMMC_WCR_WKENCREM (0x1u << 2)\r
+/* -------- SDMMC_CCR (SDMMC Offset: 0x02C) Clock Control Register */\r
+#define SDMMC_CCR_INTCLKEN (0x1u << 0)\r
+#define SDMMC_CCR_INTCLKS (0x1u << 1)\r
+#define SDMMC_CCR_SDCLKEN (0x1u << 2)\r
+#define SDMMC_CCR_CLKGSEL (0x1u << 5)\r
+#define SDMMC_CCR_USDCLKFSEL_Pos 6\r
+#define SDMMC_CCR_USDCLKFSEL_Msk (0x3u << SDMMC_CCR_USDCLKFSEL_Pos)\r
+#define SDMMC_CCR_USDCLKFSEL(value) ((SDMMC_CCR_USDCLKFSEL_Msk & ((value) << SDMMC_CCR_USDCLKFSEL_Pos)))\r
+#define SDMMC_CCR_SDCLKFSEL_Pos 8\r
+#define SDMMC_CCR_SDCLKFSEL_Msk (0xFFu << SDMMC_CCR_SDCLKFSEL_Pos)\r
+#define SDMMC_CCR_SDCLKFSEL(value) ((SDMMC_CCR_SDCLKFSEL_Msk & ((value) << SDMMC_CCR_SDCLKFSEL_Pos)))\r
+/* -------- SDMMC_TCR (SDMMC Offset: 0x02E) Timeout Control Register */\r
+#define SDMMC_TCR_DTCVAL_Pos 0\r
+#define SDMMC_TCR_DTCVAL_Msk (0xFu << SDMMC_TCR_DTCVAL_Pos)\r
+#define SDMMC_TCR_DTCVAL(value) ((SDMMC_TCR_DTCVAL_Msk & ((value) << SDMMC_TCR_DTCVAL_Pos)))\r
+/* -------- SDMMC_SRR (SDMMC Offset: 0x02F) Software Reset Register */\r
+#define SDMMC_SRR_SWRSTALL (0x1u << 0)\r
+#define SDMMC_SRR_SWRSTCMD (0x1u << 1)\r
+#define SDMMC_SRR_SWRSTDAT (0x1u << 2)\r
+/* -------- SDMMC_NISTR (SDMMC Offset: 0x030) Normal Interrupt Status Register */\r
+#define SDMMC_NISTR_CMDC (0x1u << 0)\r
+#define SDMMC_NISTR_TRFC (0x1u << 1)\r
+#define SDMMC_NISTR_BLKGE (0x1u << 2)\r
+#define SDMMC_NISTR_DMAINT (0x1u << 3)\r
+#define SDMMC_NISTR_BWRRDY (0x1u << 4)\r
+#define SDMMC_NISTR_BRDRDY (0x1u << 5)\r
+#define SDMMC_NISTR_CINS (0x1u << 6)\r
+#define SDMMC_NISTR_CREM (0x1u << 7)\r
+#define SDMMC_NISTR_CINT (0x1u << 8)\r
+#define SDMMC_NISTR_INTA (0x1u << 9)\r
+#define SDMMC_NISTR_INTB (0x1u << 10)\r
+#define SDMMC_NISTR_INTC (0x1u << 11)\r
+#define SDMMC_NISTR_RTEVT (0x1u << 12)\r
+#define SDMMC_NISTR_BOOTAR (0x1u << 14)\r
+#define SDMMC_NISTR_ERRINT (0x1u << 15)\r
+/* -------- SDMMC_EISTR (SDMMC Offset: 0x032) Error Interrupt Status Register */\r
+#define SDMMC_EISTR_CMDTEO (0x1u << 0)\r
+#define SDMMC_EISTR_CMDCRC (0x1u << 1)\r
+#define SDMMC_EISTR_CMDEND (0x1u << 2)\r
+#define SDMMC_EISTR_CMDIDX (0x1u << 3)\r
+#define SDMMC_EISTR_DATTEO (0x1u << 4)\r
+#define SDMMC_EISTR_DATCRC (0x1u << 5)\r
+#define SDMMC_EISTR_DATEND (0x1u << 6)\r
+#define SDMMC_EISTR_CURLIM (0x1u << 7)\r
+#define SDMMC_EISTR_ACMD (0x1u << 8)\r
+#define SDMMC_EISTR_ADMA (0x1u << 9)\r
+#define SDMMC_EISTR_TUNING (0x1u << 10)\r
+#define SDMMC_EISTR_BOOTAE (0x1u << 12)\r
+/* -------- SDMMC_NISTER (SDMMC Offset: 0x034) Normal Interrupt Status Enable Register */\r
+#define SDMMC_NISTER_CMDC (0x1u << 0)\r
+#define SDMMC_NISTER_TRFC (0x1u << 1)\r
+#define SDMMC_NISTER_BLKGE (0x1u << 2)\r
+#define SDMMC_NISTER_DMAINT (0x1u << 3)\r
+#define SDMMC_NISTER_BWRRDY (0x1u << 4)\r
+#define SDMMC_NISTER_BRDRDY (0x1u << 5)\r
+#define SDMMC_NISTER_CINS (0x1u << 6)\r
+#define SDMMC_NISTER_CREM (0x1u << 7)\r
+#define SDMMC_NISTER_CINT (0x1u << 8)\r
+#define SDMMC_NISTER_INTA (0x1u << 9)\r
+#define SDMMC_NISTER_INTB (0x1u << 10)\r
+#define SDMMC_NISTER_INTC (0x1u << 11)\r
+#define SDMMC_NISTER_RTEVT (0x1u << 12)\r
+#define SDMMC_NISTER_BOOTAR (0x1u << 14)\r
+/* -------- SDMMC_EISTER (SDMMC Offset: 0x036) Error Interrupt Status Enable Register */\r
+#define SDMMC_EISTER_CMDTEO (0x1u << 0)\r
+#define SDMMC_EISTER_CMDCRC (0x1u << 1)\r
+#define SDMMC_EISTER_CMDEND (0x1u << 2)\r
+#define SDMMC_EISTER_CMDIDX (0x1u << 3)\r
+#define SDMMC_EISTER_DATTEO (0x1u << 4)\r
+#define SDMMC_EISTER_DATCRC (0x1u << 5)\r
+#define SDMMC_EISTER_DATEND (0x1u << 6)\r
+#define SDMMC_EISTER_CURLIM (0x1u << 7)\r
+#define SDMMC_EISTER_ACMD (0x1u << 8)\r
+#define SDMMC_EISTER_ADMA (0x1u << 9)\r
+#define SDMMC_EISTER_TUNING (0x1u << 10)\r
+#define SDMMC_EISTER_BOOTAE (0x1u << 12)\r
+/* -------- SDMMC_NISIER (SDMMC Offset: 0x038) Normal Interrupt Signal Enable Register */\r
+#define SDMMC_NISIER_CMDC (0x1u << 0)\r
+#define SDMMC_NISIER_TRFC (0x1u << 1)\r
+#define SDMMC_NISIER_BLKGE (0x1u << 2)\r
+#define SDMMC_NISIER_DMAINT (0x1u << 3)\r
+#define SDMMC_NISIER_BWRRDY (0x1u << 4)\r
+#define SDMMC_NISIER_BRDRDY (0x1u << 5)\r
+#define SDMMC_NISIER_CINS (0x1u << 6)\r
+#define SDMMC_NISIER_CREM (0x1u << 7)\r
+#define SDMMC_NISIER_CINT (0x1u << 8)\r
+#define SDMMC_NISIER_INTA (0x1u << 9)\r
+#define SDMMC_NISIER_INTB (0x1u << 10)\r
+#define SDMMC_NISIER_INTC (0x1u << 11)\r
+#define SDMMC_NISIER_RTEVT (0x1u << 12)\r
+#define SDMMC_NISIER_BOOTAR (0x1u << 14)\r
+/* -------- SDMMC_EISIER (SDMMC Offset: 0x03A) Error Interrupt Signal Enable Register */\r
+#define SDMMC_EISIER_CMDTEO (0x1u << 0)\r
+#define SDMMC_EISIER_CMDCRC (0x1u << 1)\r
+#define SDMMC_EISIER_CMDEND (0x1u << 2)\r
+#define SDMMC_EISIER_CMDIDX (0x1u << 3)\r
+#define SDMMC_EISIER_DATTEO (0x1u << 4)\r
+#define SDMMC_EISIER_DATCRC (0x1u << 5)\r
+#define SDMMC_EISIER_DATEND (0x1u << 6)\r
+#define SDMMC_EISIER_CURLIM (0x1u << 7)\r
+#define SDMMC_EISIER_ACMD (0x1u << 8)\r
+#define SDMMC_EISIER_ADMA (0x1u << 9)\r
+#define SDMMC_EISIER_TUNING (0x1u << 10)\r
+#define SDMMC_EISIER_BOOTAE (0x1u << 12)\r
+/* -------- SDMMC_ACESR (SDMMC Offset: 0x03C) Auto CMD Error Status Register */\r
+#define SDMMC_ACESR_ACMD12NE (0x1u << 0)\r
+#define SDMMC_ACESR_ACMDTEO (0x1u << 1)\r
+#define SDMMC_ACESR_ACMDCRC (0x1u << 2)\r
+#define SDMMC_ACESR_ACMDEND (0x1u << 3)\r
+#define SDMMC_ACESR_ACMDIDX (0x1u << 4)\r
+#define SDMMC_ACESR_CMDNI (0x1u << 7)\r
+/* -------- SDMMC_HC2R (SDMMC Offset: 0x03E) Host Control 2 Register */\r
+#define SDMMC_HC2R_UHSMS_Pos 0\r
+#define SDMMC_HC2R_UHSMS_Msk (0x7u << SDMMC_HC2R_UHSMS_Pos)\r
+#define SDMMC_HC2R_UHSMS_SDR12 (0x0u << 0)\r
+#define SDMMC_HC2R_UHSMS_SDR25 (0x1u << 0)\r
+#define SDMMC_HC2R_UHSMS_SDR50 (0x2u << 0)\r
+#define SDMMC_HC2R_UHSMS_SDR104 (0x3u << 0)\r
+#define SDMMC_HC2R_UHSMS_DDR50 (0x4u << 0)\r
+#define SDMMC_HC2R_VS18EN (0x1u << 3)\r
+#define SDMMC_HC2R_DRVSEL_Pos 4\r
+#define SDMMC_HC2R_DRVSEL_Msk (0x3u << SDMMC_HC2R_DRVSEL_Pos)\r
+#define SDMMC_HC2R_DRVSEL_TYPEB (0x0u << 4)\r
+#define SDMMC_HC2R_DRVSEL_TYPEA (0x1u << 4)\r
+#define SDMMC_HC2R_DRVSEL_TYPEC (0x2u << 4)\r
+#define SDMMC_HC2R_DRVSEL_TYPED (0x3u << 4)\r
+#define SDMMC_HC2R_EXTUN (0x1u << 6)\r
+#define SDMMC_HC2R_SCLKSEL (0x1u << 7)\r
+#define SDMMC_HC2R_ASINTEN (0x1u << 14)\r
+#define SDMMC_HC2R_PVALEN (0x1u << 15)\r
+/* -------- SDMMC_CA0R (SDMMC Offset: 0x040) Capabilities Register */\r
+#define SDMMC_CA0R_TEOCLKF_Pos 0\r
+#define SDMMC_CA0R_TEOCLKF_Msk (0x3Fu << SDMMC_CA0R_TEOCLKF_Pos)\r
+#define SDMMC_CA0R_TEOCLKF(value) ((SDMMC_CA0R_TEOCLKF_Msk & ((value) << SDMMC_CA0R_TEOCLKF_Pos)))\r
+#define SDMMC_CA0R_TEOCLKU (0x1u << 7)\r
+#define SDMMC_CA0R_BASECLKF_Pos 8\r
+#define SDMMC_CA0R_BASECLKF_Msk (0xFFu << SDMMC_CA0R_BASECLKF_Pos)\r
+#define SDMMC_CA0R_BASECLKF(value) ((SDMMC_CA0R_BASECLKF_Msk & ((value) << SDMMC_CA0R_BASECLKF_Pos)))\r
+#define SDMMC_CA0R_MAXBLKL_Pos 16\r
+#define SDMMC_CA0R_MAXBLKL_Msk (0x3u << SDMMC_CA0R_MAXBLKL_Pos)\r
+#define SDMMC_CA0R_MAXBLKL(value) ((SDMMC_CA0R_MAXBLKL_Msk & ((value) << SDMMC_CA0R_MAXBLKL_Pos)))\r
+#define SDMMC_CA0R_ED8SUP (0x1u << 18)\r
+#define SDMMC_CA0R_ADMA2SUP (0x1u << 19)\r
+#define SDMMC_CA0R_HSSUP (0x1u << 21)\r
+#define SDMMC_CA0R_SDMASUP (0x1u << 22)\r
+#define SDMMC_CA0R_SRSUP (0x1u << 23)\r
+#define SDMMC_CA0R_V33VSUP (0x1u << 24)\r
+#define SDMMC_CA0R_V30VSUP (0x1u << 25)\r
+#define SDMMC_CA0R_V18VSUP (0x1u << 26)\r
+#define SDMMC_CA0R_SB64SUP (0x1u << 28)\r
+#define SDMMC_CA0R_ASINTSUP (0x1u << 29)\r
+#define SDMMC_CA0R_SLTYPE_Pos 30\r
+#define SDMMC_CA0R_SLTYPE_Msk (0x3u << SDMMC_CA0R_SLTYPE_Pos)\r
+#define SDMMC_CA0R_SLTYPE_REMOVABLECARD (0x0u << 30)\r
+#define SDMMC_CA0R_SLTYPE_EMBEDDED (0x1u << 30)\r
+#define SDMMC_CA0R_SLTYPE_SHAREDBUS (0x2u << 30)\r
+/* -------- SDMMC_CA1R (SDMMC Offset: 0x044) Capabilities Register */\r
+#define SDMMC_CA1R_SDR50SUP (0x1u << 0)\r
+#define SDMMC_CA1R_SDR104SUP (0x1u << 1)\r
+#define SDMMC_CA1R_DDR50SUP (0x1u << 2)\r
+#define SDMMC_CA1R_DRVASUP (0x1u << 4)\r
+#define SDMMC_CA1R_DRVCSUP (0x1u << 5)\r
+#define SDMMC_CA1R_DRVDSUP (0x1u << 6)\r
+#define SDMMC_CA1R_TCNTRT_Pos 8\r
+#define SDMMC_CA1R_TCNTRT_Msk (0xFu << SDMMC_CA1R_TCNTRT_Pos)\r
+#define SDMMC_CA1R_TSDR50 (0x1u << 13)\r
+#define SDMMC_CA1R_RTMOD_Pos 14\r
+#define SDMMC_CA1R_RTMOD_Msk (0x3u << SDMMC_CA1R_RTMOD_Pos)\r
+#define SDMMC_CA1R_RTMOD_MODE1 (0x0u << 14)\r
+#define SDMMC_CA1R_RTMOD_MODE2 (0x1u << 14)\r
+#define SDMMC_CA1R_RTMOD_MODE3 (0x2u << 14)\r
+#define SDMMC_CA1R_CLKMULT_Pos 16\r
+#define SDMMC_CA1R_CLKMULT_Msk (0xFFu << SDMMC_CA1R_CLKMULT_Pos)\r
+/* -------- SDMMC_MCCAR (SDMMC Offset: 0x048) Maximum Current Capabilities Register */\r
+#define SDMMC_MCCAR_MAXCUR33V_Pos 0\r
+#define SDMMC_MCCAR_MAXCUR33V_Msk (0xFFu << SDMMC_MCCAR_MAXCUR33V_Pos)\r
+#define SDMMC_MCCAR_MAXCUR30V_Pos 8\r
+#define SDMMC_MCCAR_MAXCUR30V_Msk (0xFFu << SDMMC_MCCAR_MAXCUR30V_Pos)\r
+#define SDMMC_MCCAR_MAXCUR18V_Pos 16\r
+#define SDMMC_MCCAR_MAXCUR18V_Msk (0xFFu << SDMMC_MCCAR_MAXCUR18V_Pos)\r
+/* -------- SDMMC_FERACES (SDMMC Offset: 0x050) Force Event Register for Auto CMD Error Status */\r
+#define SDMMC_FERACES_ACMD12NE (0x1u << 0)\r
+#define SDMMC_FERACES_ACMDTEO (0x1u << 1)\r
+#define SDMMC_FERACES_ACMDCRC (0x1u << 2)\r
+#define SDMMC_FERACES_ACMDEND (0x1u << 3)\r
+#define SDMMC_FERACES_ACMDIDX (0x1u << 4)\r
+#define SDMMC_FERACES_CMDNI (0x1u << 7)\r
+/* -------- SDMMC_FEREIS (SDMMC Offset: 0x052) Force Event Register for Error Interrupt Status */\r
+#define SDMMC_FEREIS_CMDTEO (0x1u << 0)\r
+#define SDMMC_FEREIS_CMDCRC (0x1u << 1)\r
+#define SDMMC_FEREIS_CMDEND (0x1u << 2)\r
+#define SDMMC_FEREIS_CMDIDX (0x1u << 3)\r
+#define SDMMC_FEREIS_DATTEO (0x1u << 4)\r
+#define SDMMC_FEREIS_DATCRC (0x1u << 5)\r
+#define SDMMC_FEREIS_DATEND (0x1u << 6)\r
+#define SDMMC_FEREIS_CURLIM (0x1u << 7)\r
+#define SDMMC_FEREIS_ACMD (0x1u << 8)\r
+#define SDMMC_FEREIS_ADMA (0x1u << 9)\r
+/* -------- SDMMC_AESR (SDMMC Offset: 0x054) ADMA Error Status Register */\r
+#define SDMMC_AESR_ERRST_Pos 0\r
+#define SDMMC_AESR_ERRST_Msk (0x3u << SDMMC_AESR_ERRST_Pos)\r
+#define SDMMC_AESR_ERRST_STOP (0x0u << 0)\r
+#define SDMMC_AESR_ERRST_FDS (0x1u << 0)\r
+#define SDMMC_AESR_ERRST_TFR (0x3u << 0)\r
+#define SDMMC_AESR_LMIS (0x1u << 2)\r
+/* -------- SDMMC_ASA0R (SDMMC Offset: 0x058) ADMA System Address Register */\r
+#define SDMMC_ASA0R_ADMASA_Pos 0\r
+#define SDMMC_ASA0R_ADMASA_Msk (0xFFFFFFFFu << SDMMC_ASA0R_ADMASA_Pos)\r
+#define SDMMC_ASA0R_ADMASA(value) ((SDMMC_ASA0R_ADMASA_Msk & ((value) << SDMMC_ASA0R_ADMASA_Pos)))\r
+/* -------- SDMMC_PVR[8] (SDMMC Offset: 0x060) Preset Value Register */\r
+#define SDMMC_PVR_SDCLKFSEL_Pos 0\r
+#define SDMMC_PVR_SDCLKFSEL_Msk (0x3FFu << SDMMC_PVR_SDCLKFSEL_Pos)\r
+#define SDMMC_PVR_SDCLKFSEL(value) ((SDMMC_PVR_SDCLKFSEL_Msk & ((value) << SDMMC_PVR_SDCLKFSEL_Pos)))\r
+#define SDMMC_PVR_CLKGSEL (0x1u << 10)\r
+#define SDMMC_PVR_DRVSEL_Pos 14\r
+#define SDMMC_PVR_DRVSEL_Msk (0x3u << SDMMC_PVR_DRVSEL_Pos)\r
+#define SDMMC_PVR_DRVSEL(value) ((SDMMC_PVR_DRVSEL_Msk & ((value) << SDMMC_PVR_DRVSEL_Pos)))\r
+/* -------- SDMMC_SISR (SDMMC Offset: 0x0FC) Slot Interrupt Status Register */\r
+#define SDMMC_SISR_INTSSL_Pos 0\r
+#define SDMMC_SISR_INTSSL_Msk (0xFFu << SDMMC_SISR_INTSIGSLOT_Pos)\r
+/* -------- SDMMC_HCVR (SDMMC Offset: 0x0FE) Host Controller Version Register */\r
+#define SDMMC_HCVR_SVER_Pos 0\r
+#define SDMMC_HCVR_SVER_Msk (0xFFu << SDMMC_HCVR_SVER_Pos)\r
+#define SDMMC_HCVR_VVER_Pos 8\r
+#define SDMMC_HCVR_VVER_Msk (0xFFu << SDMMC_HCVR_VVER_Pos)\r
+/* -------- SDMMC_APSR (SDMMC Offset: 0x200) Additionnal Present State Register */\r
+#define SDMMC_APSR_HDATLL_Pos 0\r
+#define SDMMC_APSR_HDATLL_Msk (0xFu << SDMMC_APSR_HDATLL_Pos)\r
+/* -------- SDMMC_MC1R (SDMMC Offset: 0x204) MMC Control 1 Register */\r
+#define SDMMC_MC1R_CMDTYP_Pos 0\r
+#define SDMMC_MC1R_CMDTYP_Msk (0x3u << SDMMC_MC1R_CMDTYP_Pos)\r
+#define SDMMC_MC1R_CMDTYP_NORMAL (0x0u << 0)\r
+#define SDMMC_MC1R_CMDTYP_WAITIRQ (0x1u << 0)\r
+#define SDMMC_MC1R_CMDTYP_STREAM (0x2u << 0)\r
+#define SDMMC_MC1R_CMDTYP_BOOT (0x3u << 0)\r
+#define SDMMC_MC1R_DDR (0x1u << 3)\r
+#define SDMMC_MC1R_OPD (0x1u << 4)\r
+#define SDMMC_MC1R_BOOTA (0x1u << 5)\r
+#define SDMMC_MC1R_RSTN (0x1u << 6)\r
+#define SDMMC_MC1R_FCD (0x1u << 7)\r
+/* -------- SDMMC_MC2R (SDMMC Offset: 0x205) MMC Control 2 Register */\r
+#define SDMMC_MC2R_SRESP (0x1u << 0)\r
+#define SDMMC_MC2R_ABOOT (0x1u << 1)\r
+/* -------- SDMMC_ACR (SDMMC Offset: 0x208) AHB Control Register */\r
+#define SDMMC_ACR_BMAX_Pos 0\r
+#define SDMMC_ACR_BMAX_Msk (0x3u << SDMMC_ACR_BMAX_Pos)\r
+#define SDMMC_ACR_BMAX_INCR16 (0x0u << 0)\r
+#define SDMMC_ACR_BMAX_INCR8 (0x1u << 0)\r
+#define SDMMC_ACR_BMAX_INCR4 (0x2u << 0)\r
+#define SDMMC_ACR_BMAX_SINGLE (0x3u << 0)\r
+#define SDMMC_ACR_HNBRDIS (0x1u << 4)\r
+#define SDMMC_ACR_B1KBDIS (0x1u << 5)\r
+/* -------- SDMMC_CC2R (SDMMC Offset: 0x20C) Clock Control 2 Register */\r
+#define SDMMC_CC2R_FSDCLKD (0x1u << 0)\r
+/* -------- SDMMC_RTC1R (SDMMC Offset: 0x210) Retuning Timer Control 1 Register */\r
+#define SDMMC_RTC1R_TMREN (0x1u << 0)\r
+/* -------- SDMMC_RTC2R (SDMMC Offset: 0x211) Retuning Timer Control 2 Register */\r
+#define SDMMC_RTC2R_RLD (0x1u << 0)\r
+/* -------- SDMMC_RTCVR (SDMMC Offset: 0x214) Retuning Timer Counter Value Register */\r
+#define SDMMC_RTCVR_TCVAL_Pos 0\r
+#define SDMMC_RTCVR_TCVAL_Msk (0xFu << SDMMC_RTCVR_TCVAL_Pos)\r
+#define SDMMC_RTCVR_TCVAL(value) ((SDMMC_RTCVR_TCVAL_Msk & ((value) << SDMMC_RTCVR_TCVAL_Pos)))\r
+/* -------- SDMMC_RTISTER (SDMMC Offset: 0x218) Retuning Timer Interrupt Status Enable Register */\r
+#define SDMMC_RTISTER_TEVT (0x1u << 0)\r
+/* -------- SDMMC_RTISIER (SDMMC Offset: 0x219) Retuning Timer Interrupt Signal Enable Register */\r
+#define SDMMC_RTISIER_TEVT (0x1u << 0)\r
+/* -------- SDMMC_RTISTR (SDMMC Offset: 0x21C) Retuning Timer Interrupt Status Register */\r
+#define SDMMC_RTISTR_TEVT (0x1u << 0)\r
+/* -------- SDMMC_RTSSR (SDMMC Offset: 0x21D) Retuning Timer Status Slots Register */\r
+#define SDMMC_RTSSR_TEVTSLOT (0x1u << 0)\r
+/* -------- SDMMC_TUNCR (SDMMC Offset: 0x220) Tuning Control Register */\r
+#define SDMMC_TUNCR_SMPLPT (0x1u << 0)\r
+/* -------- SDMMC_CACR (SDMMC Offset: 0x230) Capabilities Control Register */\r
+#define SDMMC_CACR_CAPWREN (0x1u << 0)\r
+#define SDMMC_CACR_KEY_Pos 8\r
+#define SDMMC_CACR_KEY_Msk (0xFFu << SDMMC_CACR_KEY_Pos)\r
+#define SDMMC_CACR_KEY(value) ((SDMMC_CACR_KEY_Msk & ((value) << SDMMC_CACR_KEY_Pos)))\r
+/* -------- SDMMC_CALCR (SDMMC Offset: 0x240) Calibration Control Register */\r
+#define SDMMC_CALCR_EN (0x1u << 0)\r
+#define SDMMC_CALCR_ALWYSON (0x1u << 4)\r
+#define SDMMC_CALCR_TUNDIS (0x1u << 5)\r
+#define SDMMC_CALCR_CNTVAL_Pos 8\r
+#define SDMMC_CALCR_CNTVAL_Msk (0xFFu << SDMMC_CALCR_CNTVAL_Pos)\r
+#define SDMMC_CALCR_CNTVAL(value) ((SDMMC_CALCR_CNTVAL_Msk & ((value) << SDMMC_CALCR_CNTVAL_Pos)))\r
+#define SDMMC_CALCR_CALN_Pos 16\r
+#define SDMMC_CALCR_CALN_Msk (0xFu << SDMMC_CALCR_CALN_Pos)\r
+#define SDMMC_CALCR_CALP_Pos 24\r
+#define SDMMC_CALCR_CALP_Msk (0xFu << SDMMC_CALCR_CALP_Pos)\r
+/* -------- SDMMC Descriptor Table for Advanced DMA 2 as pointed by SDMMC_ASA0R */\r
+#define SDMMC_DMADL_SIZE (2u) /**< \brief Size of a Descriptor Line in the ADMA2 Descriptor Table, in words */\r
+#define SDMMC_DMADL_TRAN_LEN_MIN (1u) /**< \brief Minimum data length per ADMA2 Descriptor Line, in bytes */\r
+#define SDMMC_DMADL_TRAN_LEN_MAX (65536ul) /**< \brief Maximum data length per ADMA2 Descriptor Line, in bytes */\r
+/* -------- SDMMC_DMADL[0] (Descriptor Line Offset: 0x0) ADMA2 Descriptor Line */\r
+#define SDMMC_DMA0DL_ATTR_VALID (0x1u << 0)\r
+#define SDMMC_DMA0DL_ATTR_END (0x1u << 1)\r
+#define SDMMC_DMA0DL_ATTR_INT (0x1u << 2)\r
+#define SDMMC_DMA0DL_ATTR_ACT_Pos 4\r
+#define SDMMC_DMA0DL_ATTR_ACT_Msk (0x3u << SDMMC_DMA0DL_ATTR_ACT_Pos)\r
+#define SDMMC_DMA0DL_ATTR_ACT_NOP (0x0u << 4)\r
+#define SDMMC_DMA0DL_ATTR_ACT_TRAN (0x2u << 4)\r
+#define SDMMC_DMA0DL_ATTR_ACT_LINK (0x3u << 4)\r
+#define SDMMC_DMA0DL_LEN_Pos 16\r
+#define SDMMC_DMA0DL_LEN_Msk (0xFFFFu << SDMMC_DMA0DL_LEN_Pos)\r
+#define SDMMC_DMA0DL_LEN_MAX (0x0u << 16)\r
+#define SDMMC_DMA0DL_LEN(value) ((SDMMC_DMA0DL_LEN_Msk & ((value) << SDMMC_DMA0DL_LEN_Pos)))\r
+/* -------- SDMMC_DMADL[1] (Descriptor Line Offset: 0x4) ADMA2 Descriptor Line */\r
+#define SDMMC_DMA1DL_ADDR_Pos 0\r
+#define SDMMC_DMA1DL_ADDR_Msk (0xFFFFFFFFu << SDMMC_DMA1DL_ADDR_Pos)\r
+#define SDMMC_DMA1DL_ADDR(value) ((SDMMC_DMA1DL_ADDR_Msk & ((value) << SDMMC_DMA1DL_ADDR_Pos)))\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D2_SDMMC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SFC_COMPONENT_\r
+#define _SAMA5D2_SFC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Secure Fuse Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SFC Secure Fuse Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Sfc hardware registers */\r
+typedef struct {\r
+ __O uint32_t SFC_KR; /**< \brief (Sfc Offset: 0x00) SFC Key Register */\r
+ __IO uint32_t SFC_MR; /**< \brief (Sfc Offset: 0X04) SFC Mode Register */\r
+ __I uint32_t Reserved1[2];\r
+ __IO uint32_t SFC_IER; /**< \brief (Sfc Offset: 0x10) SFC Interrupt Enable Register */\r
+ __IO uint32_t SFC_IDR; /**< \brief (Sfc Offset: 0x14) SFC Interrupt Disable Register */\r
+ __I uint32_t SFC_IMR; /**< \brief (Sfc Offset: 0x18) SFC Interrupt Mask Register */\r
+ __I uint32_t SFC_SR; /**< \brief (Sfc Offset: 0x1C) SFC Status Register */\r
+ __IO uint32_t SFC_DR[24]; /**< \brief (Sfc Offset: 0x20) SFC Data Register */\r
+ __I uint32_t Reserved2[31];\r
+ __I uint32_t SFC_VERSION; /**< \brief (Sfc Offset: 0xFC) Version Register */\r
+} Sfc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SFC_KR : (SFC Offset: 0x00) SFC Key Register -------- */\r
+#define SFC_KR_KEY_Pos 0\r
+#define SFC_KR_KEY_Msk (0xffu << SFC_KR_KEY_Pos) /**< \brief (SFC_KR) Key Code */\r
+#define SFC_KR_KEY(value) ((SFC_KR_KEY_Msk & ((value) << SFC_KR_KEY_Pos)))\r
+/* -------- SFC_MR : (SFC Offset: 0X04) SFC Mode Register -------- */\r
+#define SFC_MR_MSK (0x1u << 0) /**< \brief (SFC_MR) Mask Data Registers */\r
+#define SFC_MR_SASEL (0x1u << 4) /**< \brief (SFC_MR) Sense Amplifier Selection */\r
+/* -------- SFC_IER : (SFC Offset: 0x10) SFC Interrupt Enable Register -------- */\r
+#define SFC_IER_PGMC (0x1u << 0) /**< \brief (SFC_IER) Programming Sequence Completed Interrupt Enable */\r
+#define SFC_IER_PGMF (0x1u << 1) /**< \brief (SFC_IER) Programming Sequence Failed Interrupt Enable */\r
+#define SFC_IER_LCHECK (0x1u << 4) /**< \brief (SFC_IER) Live Integrity Check Error Interrupt Enable */\r
+#define SFC_IER_APLE (0x1u << 16) /**< \brief (SFC_IER) Atmel Programming Lock Error Interrupt Enable */\r
+#define SFC_IER_ACE (0x1u << 17) /**< \brief (SFC_IER) Atmel Check Error Interrupt Enable */\r
+/* -------- SFC_IDR : (SFC Offset: 0x14) SFC Interrupt Disable Register -------- */\r
+#define SFC_IDR_PGMC (0x1u << 0) /**< \brief (SFC_IDR) Programming Sequence Completed Interrupt Disable */\r
+#define SFC_IDR_PGMF (0x1u << 1) /**< \brief (SFC_IDR) Programming Sequence Failed Interrupt Disable */\r
+#define SFC_IDR_LCHECK (0x1u << 4) /**< \brief (SFC_IDR) Live Integrity Check Error Interrupt Disable */\r
+#define SFC_IDR_APLE (0x1u << 16) /**< \brief (SFC_IDR) Atmel Programming Lock Error Interrupt Disable */\r
+#define SFC_IDR_ACE (0x1u << 17) /**< \brief (SFC_IDR) Atmel Check Error Interrupt Disable */\r
+/* -------- SFC_IMR : (SFC Offset: 0x18) SFC Interrupt Mask Register -------- */\r
+#define SFC_IMR_PGMC (0x1u << 0) /**< \brief (SFC_IMR) Programming Sequence Completed Interrupt Mask */\r
+#define SFC_IMR_PGMF (0x1u << 1) /**< \brief (SFC_IMR) Programming Sequence Failed Interrupt Mask */\r
+#define SFC_IMR_LCHECK (0x1u << 4) /**< \brief (SFC_IMR) Live Integrity Checking Error Interrupt Mask */\r
+#define SFC_IMR_APLE (0x1u << 16) /**< \brief (SFC_IMR) Atmel Programming Lock Error Interrupt Mask */\r
+#define SFC_IMR_ACE (0x1u << 17) /**< \brief (SFC_IMR) Atmel Check Error Interrupt Mask */\r
+/* -------- SFC_SR : (SFC Offset: 0x1C) SFC Status Register -------- */\r
+#define SFC_SR_PGMC (0x1u << 0) /**< \brief (SFC_SR) Programming Sequence Completed (cleared on read) */\r
+#define SFC_SR_PGMF (0x1u << 1) /**< \brief (SFC_SR) Programming Sequence Failed (cleared on read) */\r
+#define SFC_SR_LCHECK (0x1u << 4) /**< \brief (SFC_SR) Live Integrity Checking Error (cleared on read) */\r
+#define SFC_SR_APLE (0x1u << 16) /**< \brief (SFC_SR) Atmel Programming Lock Error (cleared on read) */\r
+#define SFC_SR_ACE (0x1u << 17) /**< \brief (SFC_SR) Atmel Check Error (cleared on read) */\r
+/* -------- SFC_DR[24] : (SFC Offset: 0x20) SFC Data Register -------- */\r
+#define SFC_DR_DATA_Pos 0\r
+#define SFC_DR_DATA_Msk (0xffffffffu << SFC_DR_DATA_Pos) /**< \brief (SFC_DR[24]) Fuse Data */\r
+#define SFC_DR_DATA(value) ((SFC_DR_DATA_Msk & ((value) << SFC_DR_DATA_Pos)))\r
+/* -------- SFC_VERSION : (SFC Offset: 0xFC) Version Register -------- */\r
+#define SFC_VERSION_VERSION_Pos 0\r
+#define SFC_VERSION_VERSION_Msk (0xfffu << SFC_VERSION_VERSION_Pos) /**< \brief (SFC_VERSION) Hardware Module Version */\r
+#define SFC_VERSION_MFN_Pos 16\r
+#define SFC_VERSION_MFN_Msk (0x7u << SFC_VERSION_MFN_Pos) /**< \brief (SFC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_SFC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SFR_COMPONENT_\r
+#define _SAMA5D2_SFR_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Special Function Registers */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SFR Special Function Registers */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Sfr hardware registers */\r
+typedef struct {\r
+ __I uint32_t Reserved0[1];\r
+ __IO uint32_t SFR_DDRCFG; /**< \brief (Sfr Offset: 0x04) DDR Configuration Register */\r
+ __I uint32_t Reserved1[2];\r
+ __IO uint32_t SFR_OHCIICR; /**< \brief (Sfr Offset: 0x10) OHCI Interrupt Configuration Register */\r
+ __I uint32_t SFR_OHCIISR; /**< \brief (Sfr Offset: 0x14) OHCI Interrupt Status Register */\r
+ __I uint32_t Reserved2[4];\r
+ __IO uint32_t SFR_SECURE; /**< \brief (Sfr Offset: 0x28) Security Configuration Register */\r
+ __I uint32_t Reserved3[1];\r
+ __IO uint32_t SFR_UTMICKTRIM; /**< \brief (Sfr Offset: 0x30) UTMI Clock Trimming Register */\r
+ __IO uint32_t SFR_UTMIHSTRIM; /**< \brief (Sfr Offset: 0x34) UTMI High Speed Trimming Register */\r
+ __IO uint32_t SFR_UTMIFSTRIM; /**< \brief (Sfr Offset: 0x38) UTMI Full Speed Trimming Register */\r
+ __IO uint32_t SFR_UTMISWAP; /**< \brief (Sfr Offset: 0x3C) UTMI DP/DM Pin Swapping Register */\r
+ __IO uint32_t SFR_EBICFG; /**< \brief (Sfr Offset: 0x40) EBI Configuration Register */\r
+ __I uint32_t Reserved4[1];\r
+ __IO uint32_t SFR_CAN; /**< \brief (Sfr Offset: 0x48) CAN Memories Address-based Register */\r
+ __I uint32_t SFR_SN0; /**< \brief (Sfr Offset: 0x4C) Serial Number 0 Register */\r
+ __I uint32_t SFR_SN1; /**< \brief (Sfr Offset: 0x50) Serial Number 1 Register */\r
+ __IO uint32_t SFR_AICREDIR; /**< \brief (Sfr Offset: 0x54) AIC interrupt Redirection Register */\r
+ __IO uint32_t SFR_L2CC_HRAMC; /**< \brief (Sfr Offset: 0x58) L2CC_HRAMC1 */\r
+ __I uint32_t Reserved5[13];\r
+ __IO uint32_t SFR_I2SCLKSEL; /**< \brief (Sfr Offset: 0x90) I2SC Register */\r
+ __IO uint32_t QSPICLK_REG; /**< \brief (Sfr Offset: 0x94) QSPI Clock Pad Supply Select Register */\r
+} Sfr;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SFR_DDRCFG : (SFR Offset: 0x04) DDR Configuration Register -------- */\r
+#define SFR_DDRCFG_FDQIEN (0x1u << 16) /**< \brief (SFR_DDRCFG) Force DDR_DQ Input Buffer Always On */\r
+#define SFR_DDRCFG_FDQSIEN (0x1u << 17) /**< \brief (SFR_DDRCFG) Force DDR_DQS Input Buffer Always On */\r
+/* -------- SFR_OHCIICR : (SFR Offset: 0x10) OHCI Interrupt Configuration Register -------- */\r
+#define SFR_OHCIICR_RES0 (0x1u << 0) /**< \brief (SFR_OHCIICR) USB PORTx RESET */\r
+#define SFR_OHCIICR_RES1 (0x1u << 1) /**< \brief (SFR_OHCIICR) USB PORTx RESET */\r
+#define SFR_OHCIICR_RES2 (0x1u << 2) /**< \brief (SFR_OHCIICR) USB PORTx RESET */\r
+#define SFR_OHCIICR_ARIE (0x1u << 4) /**< \brief (SFR_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */\r
+#define SFR_OHCIICR_APPSTART (0x1u << 5) /**< \brief (SFR_OHCIICR) Reserved */\r
+#define SFR_OHCIICR_SUSPEND_A (0x1u << 8) /**< \brief (SFR_OHCIICR) USB PORT A */\r
+#define SFR_OHCIICR_SUSPEND_B (0x1u << 9) /**< \brief (SFR_OHCIICR) USB PORT B */\r
+#define SFR_OHCIICR_SUSPEND_C (0x1u << 10) /**< \brief (SFR_OHCIICR) USB PORT C */\r
+#define SFR_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (SFR_OHCIICR) USB DEVICE PULL-UP DISABLE */\r
+#define SFR_OHCIICR_HSIC_SEL (0x1u << 27) /**< \brief (SFR_OHCIICR) Reserved */\r
+/* -------- SFR_OHCIISR : (SFR Offset: 0x14) OHCI Interrupt Status Register -------- */\r
+#define SFR_OHCIISR_RIS0 (0x1u << 0) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 0 */\r
+#define SFR_OHCIISR_RIS1 (0x1u << 1) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 1 */\r
+#define SFR_OHCIISR_RIS2 (0x1u << 2) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 2 */\r
+/* -------- SFR_SECURE : (SFR Offset: 0x28) Security Configuration Register -------- */\r
+#define SFR_SECURE_ROM (0x1u << 0) /**< \brief (SFR_SECURE) Disable Access to ROM Code */\r
+#define SFR_SECURE_FUSE (0x1u << 8) /**< \brief (SFR_SECURE) Disable Access to Fuse Controller */\r
+/* -------- SFR_UTMICKTRIM : (SFR Offset: 0x30) UTMI Clock Trimming Register -------- */\r
+#define SFR_UTMICKTRIM_FREQ_Pos 0\r
+#define SFR_UTMICKTRIM_FREQ_Msk (0x3u << SFR_UTMICKTRIM_FREQ_Pos) /**< \brief (SFR_UTMICKTRIM) UTMI Reference Clock Frequency */\r
+#define SFR_UTMICKTRIM_FREQ(value) ((SFR_UTMICKTRIM_FREQ_Msk & ((value) << SFR_UTMICKTRIM_FREQ_Pos)))\r
+#define SFR_UTMICKTRIM_FREQ_12 (0x0u << 0) /**< \brief (SFR_UTMICKTRIM) 12 MHz reference clock */\r
+#define SFR_UTMICKTRIM_FREQ_16 (0x1u << 0) /**< \brief (SFR_UTMICKTRIM) 16 MHz reference clock */\r
+#define SFR_UTMICKTRIM_FREQ_24 (0x2u << 0) /**< \brief (SFR_UTMICKTRIM) 24 MHz reference clock */\r
+#define SFR_UTMICKTRIM_VBG_Pos 16\r
+#define SFR_UTMICKTRIM_VBG_Msk (0xfu << SFR_UTMICKTRIM_VBG_Pos) /**< \brief (SFR_UTMICKTRIM) UTMI Band Gap Voltage Trimming */\r
+#define SFR_UTMICKTRIM_VBG(value) ((SFR_UTMICKTRIM_VBG_Msk & ((value) << SFR_UTMICKTRIM_VBG_Pos)))\r
+/* -------- SFR_UTMIHSTRIM : (SFR Offset: 0x34) UTMI High Speed Trimming Register -------- */\r
+#define SFR_UTMIHSTRIM_SQUELCH_Pos 0\r
+#define SFR_UTMIHSTRIM_SQUELCH_Msk (0x7u << SFR_UTMIHSTRIM_SQUELCH_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS SQUELCH Voltage Trimming */\r
+#define SFR_UTMIHSTRIM_SQUELCH(value) ((SFR_UTMIHSTRIM_SQUELCH_Msk & ((value) << SFR_UTMIHSTRIM_SQUELCH_Pos)))\r
+#define SFR_UTMIHSTRIM_DISC_Pos 4\r
+#define SFR_UTMIHSTRIM_DISC_Msk (0x7u << SFR_UTMIHSTRIM_DISC_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI Disconnect Voltage Trimming */\r
+#define SFR_UTMIHSTRIM_DISC(value) ((SFR_UTMIHSTRIM_DISC_Msk & ((value) << SFR_UTMIHSTRIM_DISC_Pos)))\r
+#define SFR_UTMIHSTRIM_SLOPE0_Pos 8\r
+#define SFR_UTMIHSTRIM_SLOPE0_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE0_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */\r
+#define SFR_UTMIHSTRIM_SLOPE0(value) ((SFR_UTMIHSTRIM_SLOPE0_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE0_Pos)))\r
+#define SFR_UTMIHSTRIM_SLOPE1_Pos 12\r
+#define SFR_UTMIHSTRIM_SLOPE1_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE1_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */\r
+#define SFR_UTMIHSTRIM_SLOPE1(value) ((SFR_UTMIHSTRIM_SLOPE1_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE1_Pos)))\r
+#define SFR_UTMIHSTRIM_SLOPE2_Pos 16\r
+#define SFR_UTMIHSTRIM_SLOPE2_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE2_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */\r
+#define SFR_UTMIHSTRIM_SLOPE2(value) ((SFR_UTMIHSTRIM_SLOPE2_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE2_Pos)))\r
+/* -------- SFR_UTMIFSTRIM : (SFR Offset: 0x38) UTMI Full Speed Trimming Register -------- */\r
+#define SFR_UTMIFSTRIM_RISE_Pos 0\r
+#define SFR_UTMIFSTRIM_RISE_Msk (0x7u << SFR_UTMIFSTRIM_RISE_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver Output Rising Slope Trimming */\r
+#define SFR_UTMIFSTRIM_RISE(value) ((SFR_UTMIFSTRIM_RISE_Msk & ((value) << SFR_UTMIFSTRIM_RISE_Pos)))\r
+#define SFR_UTMIFSTRIM_FALL_Pos 4\r
+#define SFR_UTMIFSTRIM_FALL_Msk (0x7u << SFR_UTMIFSTRIM_FALL_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver Output Falling Slope Trimming */\r
+#define SFR_UTMIFSTRIM_FALL(value) ((SFR_UTMIFSTRIM_FALL_Msk & ((value) << SFR_UTMIFSTRIM_FALL_Pos)))\r
+#define SFR_UTMIFSTRIM_XCVR_Pos 8\r
+#define SFR_UTMIFSTRIM_XCVR_Msk (0x3u << SFR_UTMIFSTRIM_XCVR_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver Crossover Voltage Trimming */\r
+#define SFR_UTMIFSTRIM_XCVR(value) ((SFR_UTMIFSTRIM_XCVR_Msk & ((value) << SFR_UTMIFSTRIM_XCVR_Pos)))\r
+#define SFR_UTMIFSTRIM_ZN_Pos 16\r
+#define SFR_UTMIFSTRIM_ZN_Msk (0x7u << SFR_UTMIFSTRIM_ZN_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver NMOS Impedance Trimming */\r
+#define SFR_UTMIFSTRIM_ZN(value) ((SFR_UTMIFSTRIM_ZN_Msk & ((value) << SFR_UTMIFSTRIM_ZN_Pos)))\r
+#define SFR_UTMIFSTRIM_ZP_Pos 20\r
+#define SFR_UTMIFSTRIM_ZP_Msk (0x7u << SFR_UTMIFSTRIM_ZP_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver PMOS Impedance Trimming */\r
+#define SFR_UTMIFSTRIM_ZP(value) ((SFR_UTMIFSTRIM_ZP_Msk & ((value) << SFR_UTMIFSTRIM_ZP_Pos)))\r
+/* -------- SFR_UTMISWAP : (SFR Offset: 0x3C) UTMI DP/DM Pin Swapping Register -------- */\r
+#define SFR_UTMISWAP_PORT0 (0x1u << 0) /**< \brief (SFR_UTMISWAP) PORT 0 DP/DM Pin Swapping */\r
+#define SFR_UTMISWAP_PORT0_NORMAL (0x0u << 0) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */\r
+#define SFR_UTMISWAP_PORT0_SWAPPED (0x1u << 0) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */\r
+#define SFR_UTMISWAP_PORT1 (0x1u << 1) /**< \brief (SFR_UTMISWAP) PORT 1 DP/DM Pin Swapping */\r
+#define SFR_UTMISWAP_PORT1_NORMAL (0x0u << 1) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */\r
+#define SFR_UTMISWAP_PORT1_SWAPPED (0x1u << 1) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */\r
+#define SFR_UTMISWAP_PORT2 (0x1u << 2) /**< \brief (SFR_UTMISWAP) PORT 2 DP/DM Pin Swapping */\r
+#define SFR_UTMISWAP_PORT2_NORMAL (0x0u << 2) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */\r
+#define SFR_UTMISWAP_PORT2_SWAPPED (0x1u << 2) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */\r
+/* -------- SFR_EBICFG : (SFR Offset: 0x40) EBI Configuration Register -------- */\r
+#define SFR_EBICFG_DRIVE0_Pos 0\r
+#define SFR_EBICFG_DRIVE0_Msk (0x3u << SFR_EBICFG_DRIVE0_Pos) /**< \brief (SFR_EBICFG) EBI Pins Drive Level */\r
+#define SFR_EBICFG_DRIVE0(value) ((SFR_EBICFG_DRIVE0_Msk & ((value) << SFR_EBICFG_DRIVE0_Pos)))\r
+#define SFR_EBICFG_DRIVE0_LOW (0x0u << 0) /**< \brief (SFR_EBICFG) Low drive level */\r
+#define SFR_EBICFG_DRIVE0_MEDIUM (0x2u << 0) /**< \brief (SFR_EBICFG) Medium drive level */\r
+#define SFR_EBICFG_DRIVE0_HIGH (0x3u << 0) /**< \brief (SFR_EBICFG) High drive level */\r
+#define SFR_EBICFG_PULL0_Pos 2\r
+#define SFR_EBICFG_PULL0_Msk (0x3u << SFR_EBICFG_PULL0_Pos) /**< \brief (SFR_EBICFG) EBI Pins Pull Value */\r
+#define SFR_EBICFG_PULL0(value) ((SFR_EBICFG_PULL0_Msk & ((value) << SFR_EBICFG_PULL0_Pos)))\r
+#define SFR_EBICFG_PULL0_UP (0x0u << 2) /**< \brief (SFR_EBICFG) Pull-up */\r
+#define SFR_EBICFG_PULL0_NONE (0x1u << 2) /**< \brief (SFR_EBICFG) No Pull */\r
+#define SFR_EBICFG_PULL0_DOWN (0x3u << 2) /**< \brief (SFR_EBICFG) Pull-down */\r
+#define SFR_EBICFG_SCH0 (0x1u << 4) /**< \brief (SFR_EBICFG) EBI Pins Schmitt Trigger */\r
+#define SFR_EBICFG_DRIVE1_Pos 8\r
+#define SFR_EBICFG_DRIVE1_Msk (0x3u << SFR_EBICFG_DRIVE1_Pos) /**< \brief (SFR_EBICFG) EBI Pins Drive Level */\r
+#define SFR_EBICFG_DRIVE1(value) ((SFR_EBICFG_DRIVE1_Msk & ((value) << SFR_EBICFG_DRIVE1_Pos)))\r
+#define SFR_EBICFG_DRIVE1_LOW (0x0u << 8) /**< \brief (SFR_EBICFG) Low drive level */\r
+#define SFR_EBICFG_DRIVE1_MEDIUM (0x2u << 8) /**< \brief (SFR_EBICFG) Medium drive level */\r
+#define SFR_EBICFG_DRIVE1_HIGH (0x3u << 8) /**< \brief (SFR_EBICFG) High drive level */\r
+#define SFR_EBICFG_PULL1_Pos 10\r
+#define SFR_EBICFG_PULL1_Msk (0x3u << SFR_EBICFG_PULL1_Pos) /**< \brief (SFR_EBICFG) EBI Pins Pull Value */\r
+#define SFR_EBICFG_PULL1(value) ((SFR_EBICFG_PULL1_Msk & ((value) << SFR_EBICFG_PULL1_Pos)))\r
+#define SFR_EBICFG_PULL1_UP (0x0u << 10) /**< \brief (SFR_EBICFG) Pull-up */\r
+#define SFR_EBICFG_PULL1_NONE (0x1u << 10) /**< \brief (SFR_EBICFG) No Pull */\r
+#define SFR_EBICFG_PULL1_DOWN (0x3u << 10) /**< \brief (SFR_EBICFG) Pull-down */\r
+#define SFR_EBICFG_SCH1 (0x1u << 12) /**< \brief (SFR_EBICFG) EBI Pins Schmitt Trigger */\r
+/* -------- SFR_CAN : (SFR Offset: 0x48) CAN Memories Address-based Register -------- */\r
+#define SFR_CAN_EXT_MEM_CAN0_ADDR_Pos 0\r
+#define SFR_CAN_EXT_MEM_CAN0_ADDR_Msk (0xffffu << SFR_CAN_EXT_MEM_CAN0_ADDR_Pos) /**< \brief (SFR_CAN) MSB CAN0 DMA Base Address */\r
+#define SFR_CAN_EXT_MEM_CAN0_ADDR(value) ((SFR_CAN_EXT_MEM_CAN0_ADDR_Msk & ((value) << SFR_CAN_EXT_MEM_CAN0_ADDR_Pos)))\r
+#define SFR_CAN_EXT_MEM_CAN1_ADDR_Pos 16\r
+#define SFR_CAN_EXT_MEM_CAN1_ADDR_Msk (0xffffu << SFR_CAN_EXT_MEM_CAN1_ADDR_Pos) /**< \brief (SFR_CAN) MSB CAN1 DMA Base Address */\r
+#define SFR_CAN_EXT_MEM_CAN1_ADDR(value) ((SFR_CAN_EXT_MEM_CAN1_ADDR_Msk & ((value) << SFR_CAN_EXT_MEM_CAN1_ADDR_Pos)))\r
+/* -------- SFR_SN0 : (SFR Offset: 0x4C) Serial Number 0 Register -------- */\r
+#define SFR_SN0_SN0_Pos 0\r
+#define SFR_SN0_SN0_Msk (0xffffffffu << SFR_SN0_SN0_Pos) /**< \brief (SFR_SN0) Serial Number 0 */\r
+/* -------- SFR_SN1 : (SFR Offset: 0x50) Serial Number 1 Register -------- */\r
+#define SFR_SN1_SN1_Pos 0\r
+#define SFR_SN1_SN1_Msk (0xffffffffu << SFR_SN1_SN1_Pos) /**< \brief (SFR_SN1) Serial Number 1 */\r
+/* -------- SFR_AICREDIR : (SFR Offset: 0x54) AIC interrupt Redirection Register -------- */\r
+#define SFR_AICREDIR_NSAIC (0x1u << 0) /**< \brief (SFR_AICREDIR) Interrupt redirection to Non-Secure AIC */\r
+#define SFR_AICREDIR_AICREDIRKEY_Pos 1\r
+#define SFR_AICREDIR_AICREDIRKEY_Msk (0x7fffffffu << SFR_AICREDIR_AICREDIRKEY_Pos) /**< \brief (SFR_AICREDIR) Unlock Key */\r
+#define SFR_AICREDIR_AICREDIRKEY(value) ((SFR_AICREDIR_AICREDIRKEY_Msk & ((value) << SFR_AICREDIR_AICREDIRKEY_Pos)))\r
+/* -------- SFR_L2CC_HRAMC : (SFR Offset: 0x58) L2CC_HRAMC1 -------- */\r
+#define SFR_L2CC_HRAMC_SRAM_SEL (0x1u << 0) /**< \brief (SFR_L2CC_HRAMC) SRAM Selector */\r
+/* -------- SFR_I2SCLKSEL : (SFR Offset: 0x90) I2SC Register -------- */\r
+#define SFR_I2SCLKSEL_CLKSEL0 (0x1u << 0) /**< \brief (SFR_I2SCLKSEL) Clock Selection 0 */\r
+#define SFR_I2SCLKSEL_CLKSEL1 (0x1u << 1) /**< \brief (SFR_I2SCLKSEL) Clock Selection 1 */\r
+/* -------- QSPICLK_REG : (SFR Offset: 0x94) QSPI Clock Pad Supply Select Register -------- */\r
+#define QSPICLK_REG_SUP_SEL (0x1u << 0) /**< \brief (QSPICLK_REG) Supply Selection */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_SFR_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SFRBU_COMPONENT_\r
+#define _SAMA5D2_SFRBU_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Special Function Registers */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SFRBU Special Function Registers */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Sfrbu hardware registers */\r
+typedef struct {\r
+ __IO uint32_t SFRBU_PSWBUCTRL; /**< \brief (Sfrbu Offset: 0x00) Power Switch BU Control Register */\r
+ __IO uint32_t SFRBU_TSRANGECFG;/**< \brief (Sfrbu Offset: 0x04) TS Range Configuration Register */\r
+ __I uint32_t Reserved1[2];\r
+ __IO uint32_t SFRBU_DDRBUMCR; /**< \brief (Sfrbu Offset: 0x10) DDR BU Mode Control Register */\r
+ __IO uint32_t SFRBU_RXLPPUCR; /**< \brief (Sfrbu Offset: 0x14) RXLP Pull-Up Control Register */\r
+} Sfrbu;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+/* -------- SFRBU_DDRBUMCR : (Sfrbu Offset: 0x10) DDR BU Mode Control Register -------- */\r
+/* This bit is used to isolate the DDR Pads from the CPU domain (VCCCORE).\r
+ * It has to be set after enabling the Self-refresh mode on the DDR memory\r
+ * and before doing power-down on VCCCORE\r
+ */\r
+#define SFRBU_DDRBUMCR_BUMEN (0x1<<0) /**< \brief (SFRBU_DDRBUMCR) DDR BU Mode Enable */\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D2_SFRBU_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SHA_COMPONENT_\r
+#define _SAMA5D2_SHA_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Secure Hash Algorithm */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SHA Secure Hash Algorithm */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Sha hardware registers */\r
+typedef struct {\r
+ __O uint32_t SHA_CR; /**< \brief (Sha Offset: 0x00) Control Register */\r
+ __IO uint32_t SHA_MR; /**< \brief (Sha Offset: 0x04) Mode Register */\r
+ __I uint32_t Reserved1[2];\r
+ __O uint32_t SHA_IER; /**< \brief (Sha Offset: 0x10) Interrupt Enable Register */\r
+ __O uint32_t SHA_IDR; /**< \brief (Sha Offset: 0x14) Interrupt Disable Register */\r
+ __I uint32_t SHA_IMR; /**< \brief (Sha Offset: 0x18) Interrupt Mask Register */\r
+ __I uint32_t SHA_ISR; /**< \brief (Sha Offset: 0x1C) Interrupt Status Register */\r
+ __IO uint32_t SHA_MSR; /**< \brief (Sha Offset: 0x20) Message Size Register */\r
+ __I uint32_t Reserved2[3];\r
+ __IO uint32_t SHA_BCR; /**< \brief (Sha Offset: 0x30) Bytes Count Register */\r
+ __I uint32_t Reserved3[3];\r
+ __O uint32_t SHA_IDATAR[16]; /**< \brief (Sha Offset: 0x40) Input Data 0 Register */\r
+ __IO uint32_t SHA_IODATAR[16]; /**< \brief (Sha Offset: 0x80) Input/Output Data 0 Register */\r
+ __I uint32_t SHA_VERSION; /**< \brief (Sha Offset: 0xFC) Version Register */\r
+} Sha;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SHA_CR : (SHA Offset: 0x00) Control Register -------- */\r
+#define SHA_CR_START (0x1u << 0) /**< \brief (SHA_CR) Start Processing */\r
+#define SHA_CR_FIRST (0x1u << 4) /**< \brief (SHA_CR) First Block of a Message */\r
+#define SHA_CR_SWRST (0x1u << 8) /**< \brief (SHA_CR) Software Reset */\r
+#define SHA_CR_WUIHV (0x1u << 12) /**< \brief (SHA_CR) Write User Initial Hash Values */\r
+#define SHA_CR_WUIEHV (0x1u << 13) /**< \brief (SHA_CR) Write User Initial or Expected Hash Values */\r
+/* -------- SHA_MR : (SHA Offset: 0x04) Mode Register -------- */\r
+#define SHA_MR_SMOD_Pos 0\r
+#define SHA_MR_SMOD_Msk (0x3u << SHA_MR_SMOD_Pos) /**< \brief (SHA_MR) Start Mode */\r
+#define SHA_MR_SMOD(value) ((SHA_MR_SMOD_Msk & ((value) << SHA_MR_SMOD_Pos)))\r
+#define SHA_MR_SMOD_MANUAL_START (0x0u << 0) /**< \brief (SHA_MR) Manual Mode */\r
+#define SHA_MR_SMOD_AUTO_START (0x1u << 0) /**< \brief (SHA_MR) Auto Mode */\r
+#define SHA_MR_SMOD_IDATAR0_START (0x2u << 0) /**< \brief (SHA_MR) SHA_IDATAR0 access only Auto Mode */\r
+#define SHA_MR_PROCDLY (0x1u << 4) /**< \brief (SHA_MR) Processing Delay */\r
+#define SHA_MR_PROCDLY_SHORTEST (0x0u << 4) /**< \brief (SHA_MR) SHA processing runtime is the shortest one */\r
+#define SHA_MR_PROCDLY_LONGEST (0x1u << 4) /**< \brief (SHA_MR) SHA processing runtime is the longest one (reduces the SHA bandwidth requirement, reduces the system bus overload) */\r
+#define SHA_MR_UIHV (0x1u << 5) /**< \brief (SHA_MR) User Initial Hash Value Registers */\r
+#define SHA_MR_UIEHV (0x1u << 6) /**< \brief (SHA_MR) User Initial or Expected Hash Value Registers */\r
+#define SHA_MR_ALGO_Pos 8\r
+#define SHA_MR_ALGO_Msk (0xfu << SHA_MR_ALGO_Pos) /**< \brief (SHA_MR) SHA Algorithm */\r
+#define SHA_MR_ALGO(value) ((SHA_MR_ALGO_Msk & ((value) << SHA_MR_ALGO_Pos)))\r
+#define SHA_MR_ALGO_SHA1 (0x0u << 8) /**< \brief (SHA_MR) SHA1 algorithm processed */\r
+#define SHA_MR_ALGO_SHA256 (0x1u << 8) /**< \brief (SHA_MR) SHA256 algorithm processed */\r
+#define SHA_MR_ALGO_SHA384 (0x2u << 8) /**< \brief (SHA_MR) SHA384 algorithm processed */\r
+#define SHA_MR_ALGO_SHA512 (0x3u << 8) /**< \brief (SHA_MR) SHA512 algorithm processed */\r
+#define SHA_MR_ALGO_SHA224 (0x4u << 8) /**< \brief (SHA_MR) SHA224 algorithm processed */\r
+#define SHA_MR_ALGO_HMAC_SHA1 (0x8u << 8) /**< \brief (SHA_MR) HMAC algorithm with SHA1 Hash processed */\r
+#define SHA_MR_ALGO_HMAC_SHA256 (0x9u << 8) /**< \brief (SHA_MR) HMAC algorithm with SHA256 Hash processed */\r
+#define SHA_MR_ALGO_HMAC_SHA384 (0xAu << 8) /**< \brief (SHA_MR) HMAC algorithm with SHA384 Hash processed */\r
+#define SHA_MR_ALGO_HMAC_SHA512 (0xBu << 8) /**< \brief (SHA_MR) HMAC algorithm with SHA512 Hash processed */\r
+#define SHA_MR_ALGO_HMAC_SHA224 (0xCu << 8) /**< \brief (SHA_MR) HMAC algorithm with SHA224 Hash processed */\r
+#define SHA_MR_DUALBUFF (0x1u << 16) /**< \brief (SHA_MR) Dual Input Buffer */\r
+#define SHA_MR_DUALBUFF_INACTIVE (0x0u << 16) /**< \brief (SHA_MR) SHA_IDATARx and SHA_IODATARx cannot be written during processing of previous block. */\r
+#define SHA_MR_DUALBUFF_ACTIVE (0x1u << 16) /**< \brief (SHA_MR) SHA_IDATARx and SHA_IODATARx can be written during processing of previous block when SMOD value = 2. It speeds up the overall runtime of large files. */\r
+#define SHA_MR_CHECK_Pos 24\r
+#define SHA_MR_CHECK_Msk (0x3u << SHA_MR_CHECK_Pos) /**< \brief (SHA_MR) Hash Check */\r
+#define SHA_MR_CHECK(value) ((SHA_MR_CHECK_Msk & ((value) << SHA_MR_CHECK_Pos)))\r
+#define SHA_MR_CHECK_NO_CHECK (0x0u << 24) /**< \brief (SHA_MR) No check is performed */\r
+#define SHA_MR_CHECK_CHECK_EHV (0x1u << 24) /**< \brief (SHA_MR) Check is performed with expected hash stored in internal expected hash value registers. */\r
+#define SHA_MR_CHECK_CHECK_MESSAGE (0x2u << 24) /**< \brief (SHA_MR) Check is performed with expected hash provided after the message. */\r
+#define SHA_MR_CHKCNT_Pos 28\r
+#define SHA_MR_CHKCNT_Msk (0xfu << SHA_MR_CHKCNT_Pos) /**< \brief (SHA_MR) Check Counter */\r
+#define SHA_MR_CHKCNT(value) ((SHA_MR_CHKCNT_Msk & ((value) << SHA_MR_CHKCNT_Pos)))\r
+/* -------- SHA_IER : (SHA Offset: 0x10) Interrupt Enable Register -------- */\r
+#define SHA_IER_DATRDY (0x1u << 0) /**< \brief (SHA_IER) Data Ready Interrupt Enable */\r
+#define SHA_IER_URAD (0x1u << 8) /**< \brief (SHA_IER) Unspecified Register Access Detection Interrupt Enable */\r
+#define SHA_IER_CHECKF (0x1u << 16) /**< \brief (SHA_IER) Check Done Interrupt Enable */\r
+/* -------- SHA_IDR : (SHA Offset: 0x14) Interrupt Disable Register -------- */\r
+#define SHA_IDR_DATRDY (0x1u << 0) /**< \brief (SHA_IDR) Data Ready Interrupt Disable */\r
+#define SHA_IDR_URAD (0x1u << 8) /**< \brief (SHA_IDR) Unspecified Register Access Detection Interrupt Disable */\r
+#define SHA_IDR_CHECKF (0x1u << 16) /**< \brief (SHA_IDR) Check Done Interrupt Disable */\r
+/* -------- SHA_IMR : (SHA Offset: 0x18) Interrupt Mask Register -------- */\r
+#define SHA_IMR_DATRDY (0x1u << 0) /**< \brief (SHA_IMR) Data Ready Interrupt Mask */\r
+#define SHA_IMR_URAD (0x1u << 8) /**< \brief (SHA_IMR) Unspecified Register Access Detection Interrupt Mask */\r
+#define SHA_IMR_CHECKF (0x1u << 16) /**< \brief (SHA_IMR) Check Done Interrupt Mask */\r
+/* -------- SHA_ISR : (SHA Offset: 0x1C) Interrupt Status Register -------- */\r
+#define SHA_ISR_DATRDY (0x1u << 0) /**< \brief (SHA_ISR) Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR, or by reading SHA_IODATARx) */\r
+#define SHA_ISR_WRDY (0x1u << 4) /**< \brief (SHA_ISR) Input Data Register Write Ready */\r
+#define SHA_ISR_URAD (0x1u << 8) /**< \brief (SHA_ISR) Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR) */\r
+#define SHA_ISR_URAT_Pos 12\r
+#define SHA_ISR_URAT_Msk (0x7u << SHA_ISR_URAT_Pos) /**< \brief (SHA_ISR) Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR) */\r
+#define SHA_ISR_CHECKF (0x1u << 16) /**< \brief (SHA_ISR) Check Done Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx) */\r
+#define SHA_ISR_CHKST_Pos 20\r
+#define SHA_ISR_CHKST_Msk (0xfu << SHA_ISR_CHKST_Pos) /**< \brief (SHA_ISR) Check Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx) */\r
+/* -------- SHA_MSR : (SHA Offset: 0x20) Message Size Register -------- */\r
+#define SHA_MSR_MSGSIZE_Pos 0\r
+#define SHA_MSR_MSGSIZE_Msk (0xffffffffu << SHA_MSR_MSGSIZE_Pos) /**< \brief (SHA_MSR) Message Size */\r
+#define SHA_MSR_MSGSIZE(value) ((SHA_MSR_MSGSIZE_Msk & ((value) << SHA_MSR_MSGSIZE_Pos)))\r
+/* -------- SHA_BCR : (SHA Offset: 0x30) Bytes Count Register -------- */\r
+#define SHA_BCR_BYTCNT_Pos 0\r
+#define SHA_BCR_BYTCNT_Msk (0xffffffffu << SHA_BCR_BYTCNT_Pos) /**< \brief (SHA_BCR) Remaining Byte Count Before Auto Padding */\r
+#define SHA_BCR_BYTCNT(value) ((SHA_BCR_BYTCNT_Msk & ((value) << SHA_BCR_BYTCNT_Pos)))\r
+/* -------- SHA_IDATAR[16] : (SHA Offset: 0x40) Input Data 0 Register -------- */\r
+#define SHA_IDATAR_IDATA_Pos 0\r
+#define SHA_IDATAR_IDATA_Msk (0xffffffffu << SHA_IDATAR_IDATA_Pos) /**< \brief (SHA_IDATAR[16]) Input Data */\r
+#define SHA_IDATAR_IDATA(value) ((SHA_IDATAR_IDATA_Msk & ((value) << SHA_IDATAR_IDATA_Pos)))\r
+/* -------- SHA_IODATAR[16] : (SHA Offset: 0x80) Input/Output Data 0 Register -------- */\r
+#define SHA_IODATAR_IODATA_Pos 0\r
+#define SHA_IODATAR_IODATA_Msk (0xffffffffu << SHA_IODATAR_IODATA_Pos) /**< \brief (SHA_IODATAR[16]) Input/Output Data */\r
+#define SHA_IODATAR_IODATA(value) ((SHA_IODATAR_IODATA_Msk & ((value) << SHA_IODATAR_IODATA_Pos)))\r
+/* -------- SHA_VERSION : (SHA Offset: 0xFC) Version Register -------- */\r
+#define SHA_VERSION_VERSION_Pos 0\r
+#define SHA_VERSION_VERSION_Msk (0xfffu << SHA_VERSION_VERSION_Pos) /**< \brief (SHA_VERSION) Version of the Hardware Module */\r
+#define SHA_VERSION_MFN_Pos 16\r
+#define SHA_VERSION_MFN_Msk (0x7u << SHA_VERSION_MFN_Pos) /**< \brief (SHA_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_SHA_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SHDWC_COMPONENT_\r
+#define _SAMA5D2_SHDWC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Shutdown Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SHDWC Shutdown Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Shdwc hardware registers */\r
+typedef struct {\r
+ __O uint32_t SHDW_CR; /**< \brief (Shdwc Offset: 0x00) Shutdown Control Register */\r
+ __IO uint32_t SHDW_MR; /**< \brief (Shdwc Offset: 0x04) Shutdown Mode Register */\r
+ __I uint32_t SHDW_SR; /**< \brief (Shdwc Offset: 0x08) Shutdown Status Register */\r
+ __IO uint32_t SHDW_WUIR; /**< \brief (Shdwc Offset: 0x0C) Shutdown Wake-up Inputs Register */\r
+} Shdwc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SHDW_CR : (SHDWC Offset: 0x00) Shutdown Control Register -------- */\r
+#define SHDW_CR_SHDW (0x1u << 0) /**< \brief (SHDW_CR) Shutdown Command */\r
+#define SHDW_CR_KEY_Pos 24\r
+#define SHDW_CR_KEY_Msk (0xffu << SHDW_CR_KEY_Pos) /**< \brief (SHDW_CR) Password */\r
+#define SHDW_CR_KEY(value) ((SHDW_CR_KEY_Msk & ((value) << SHDW_CR_KEY_Pos)))\r
+#define SHDW_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SHDW_CR) Writing any other value in this field aborts the write operation. */\r
+/* -------- SHDW_MR : (SHDWC Offset: 0x04) Shutdown Mode Register -------- */\r
+#define SHDW_MR_LPDBCEN0 (0x1u << 0) /**< \brief (SHDW_MR) Low-Power Debouncer Enable WKUP0 */\r
+#define SHDW_MR_LPDBCEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SHDW_MR) The WKUP0 input pin is not connected to the low-power debouncer. */\r
+#define SHDW_MR_LPDBCEN0_ENABLE (0x1u << 0) /**< \brief (SHDW_MR) The WKUP0 input pin is connected to the low-power debouncer and can force a system wake-up. */\r
+#define SHDW_MR_LPDBCEN1 (0x1u << 1) /**< \brief (SHDW_MR) Low-Power Debouncer Enable WKUP1 */\r
+#define SHDW_MR_LPDBCEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SHDW_MR) The WKUP1 input pin is not connected to the low-power debouncer. */\r
+#define SHDW_MR_LPDBCEN1_ENABLE (0x1u << 1) /**< \brief (SHDW_MR) The WKUP1 input pin is connected to the low-power debouncer and can force a system wake-up. */\r
+#define SHDW_MR_LPDBC_Pos 8\r
+#define SHDW_MR_LPDBC_Msk (0x7u << SHDW_MR_LPDBC_Pos) /**< \brief (SHDW_MR) Low Power Debouncer Period */\r
+#define SHDW_MR_LPDBC(value) ((SHDW_MR_LPDBC_Msk & ((value) << SHDW_MR_LPDBC_Pos)))\r
+#define SHDW_MR_LPDBC_DISABLE (0x0u << 8) /**< \brief (SHDW_MR) Disable the low-power debouncers */\r
+#define SHDW_MR_LPDBC_2_RTCOUT0 (0x1u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 2 RTCOUT0 periods */\r
+#define SHDW_MR_LPDBC_3_RTCOUT0 (0x2u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 3 RTCOUT0 periods */\r
+#define SHDW_MR_LPDBC_4_RTCOUT0 (0x3u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 4 RTCOUT0 periods */\r
+#define SHDW_MR_LPDBC_5_RTCOUT0 (0x4u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 5 RTCOUT0 periods */\r
+#define SHDW_MR_LPDBC_6_RTCOUT0 (0x5u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 6 RTCOUT0 periods */\r
+#define SHDW_MR_LPDBC_7_RTCOUT0 (0x6u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 7 RTCOUT0 periods */\r
+#define SHDW_MR_LPDBC_8_RTCOUT0 (0x7u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 8 RTCOUT0 periods */\r
+#define SHDW_MR_RTTWKEN (0x1u << 16) /**< \brief (SHDW_MR) */\r
+#define SHDW_MR_RTCWKEN (0x1u << 17) /**< \brief (SHDW_MR) Analog Comparator Controller Wake-up Enable */\r
+#define SHDW_MR_ACCWKEN (0x1u << 18) /**< \brief (SHDW_MR) Analog Comparator Controller Wake-up Enable */\r
+#define SHDW_MR_RXLPWKEN (0x1u << 19) /**< \brief (SHDW_MR) Debug Unit Wake-up Enable */\r
+#define SHDW_MR_WKUPDBC_Pos 24\r
+#define SHDW_MR_WKUPDBC_Msk (0x7u << SHDW_MR_WKUPDBC_Pos) /**< \brief (SHDW_MR) Wake-up Inputs Debouncer Period */\r
+#define SHDW_MR_WKUPDBC(value) ((SHDW_MR_WKUPDBC_Msk & ((value) << SHDW_MR_WKUPDBC_Pos)))\r
+#define SHDW_MR_WKUPDBC_IMMEDIATE (0x0u << 24) /**< \brief (SHDW_MR) Immediate, no debouncing, detected active at least on one Slow Clock edge */\r
+#define SHDW_MR_WKUPDBC_3_SLCK (0x1u << 24) /**< \brief (SHDW_MR) WKUPx shall be in its active state for at least 3 SLCK periods */\r
+#define SHDW_MR_WKUPDBC_32_SLCK (0x2u << 24) /**< \brief (SHDW_MR) WKUPx shall be in its active state for at least 32 SLCK periods */\r
+#define SHDW_MR_WKUPDBC_512_SLCK (0x3u << 24) /**< \brief (SHDW_MR) WKUPx shall be in its active state for at least 512 SLCK periods */\r
+#define SHDW_MR_WKUPDBC_4096_SLCK (0x4u << 24) /**< \brief (SHDW_MR) WKUPx shall be in its active state for at least 4,096 SLCK periods */\r
+#define SHDW_MR_WKUPDBC_32768_SLCK (0x5u << 24) /**< \brief (SHDW_MR) WKUPx shall be in its active state for at least 32,768 SLCK periods */\r
+/* -------- SHDW_SR : (SHDWC Offset: 0x08) Shutdown Status Register -------- */\r
+#define SHDW_SR_WKUPS (0x1u << 0) /**< \brief (SHDW_SR) WKUP Wake-up Status */\r
+#define SHDW_SR_WKUPS_NO (0x0u << 0) /**< \brief (SHDW_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SHDW_SR_WKUPS_PRESENT (0x1u << 0) /**< \brief (SHDW_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SHDW_SR_ACCWK (0x1u << 6) /**< \brief (SHDW_SR) Analog Comparator Controller Wake-up */\r
+#define SHDW_SR_RXLPWK (0x1u << 7) /**< \brief (SHDW_SR) Debug Unit Wake-up */\r
+#define SHDW_SR_WKUPIS0 (0x1u << 16) /**< \brief (SHDW_SR) Wake-up 0 Input Status */\r
+#define SHDW_SR_WKUPIS0_DISABLE (0x0u << 16) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS0_ENABLE (0x1u << 16) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS1 (0x1u << 17) /**< \brief (SHDW_SR) Wake-up 1 Input Status */\r
+#define SHDW_SR_WKUPIS1_DISABLE (0x0u << 17) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS1_ENABLE (0x1u << 17) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS2 (0x1u << 18) /**< \brief (SHDW_SR) Wake-up 2 Input Status */\r
+#define SHDW_SR_WKUPIS2_DISABLE (0x0u << 18) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS2_ENABLE (0x1u << 18) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS3 (0x1u << 19) /**< \brief (SHDW_SR) Wake-up 3 Input Status */\r
+#define SHDW_SR_WKUPIS3_DISABLE (0x0u << 19) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS3_ENABLE (0x1u << 19) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS4 (0x1u << 20) /**< \brief (SHDW_SR) Wake-up 4 Input Status */\r
+#define SHDW_SR_WKUPIS4_DISABLE (0x0u << 20) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS4_ENABLE (0x1u << 20) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS5 (0x1u << 21) /**< \brief (SHDW_SR) Wake-up 5 Input Status */\r
+#define SHDW_SR_WKUPIS5_DISABLE (0x0u << 21) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS5_ENABLE (0x1u << 21) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS6 (0x1u << 22) /**< \brief (SHDW_SR) Wake-up 6 Input Status */\r
+#define SHDW_SR_WKUPIS6_DISABLE (0x0u << 22) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS6_ENABLE (0x1u << 22) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS7 (0x1u << 23) /**< \brief (SHDW_SR) Wake-up 7 Input Status */\r
+#define SHDW_SR_WKUPIS7_DISABLE (0x0u << 23) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS7_ENABLE (0x1u << 23) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS8 (0x1u << 24) /**< \brief (SHDW_SR) Wake-up 8 Input Status */\r
+#define SHDW_SR_WKUPIS8_DISABLE (0x0u << 24) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */\r
+#define SHDW_SR_WKUPIS8_ENABLE (0x1u << 24) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */\r
+/* -------- SHDW_WUIR : (SHDWC Offset: 0x0C) Shutdown Wake-up Inputs Register -------- */\r
+#define SHDW_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SHDW_WUIR) Wake-up 0 Input Enable */\r
+#define SHDW_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SHDW_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SHDW_WUIR) Wake-up 1 Input Enable */\r
+#define SHDW_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SHDW_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SHDW_WUIR) Wake-up 2 Input Enable */\r
+#define SHDW_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SHDW_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SHDW_WUIR) Wake-up 3 Input Enable */\r
+#define SHDW_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SHDW_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SHDW_WUIR) Wake-up 4 Input Enable */\r
+#define SHDW_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SHDW_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SHDW_WUIR) Wake-up 5 Input Enable */\r
+#define SHDW_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SHDW_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SHDW_WUIR) Wake-up 6 Input Enable */\r
+#define SHDW_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SHDW_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SHDW_WUIR) Wake-up 7 Input Enable */\r
+#define SHDW_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SHDW_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SHDW_WUIR) Wake-up 8 Input Enable */\r
+#define SHDW_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */\r
+#define SHDW_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SHDW_WUIR) Wake-up 0 Input Type */\r
+#define SHDW_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SHDW_WUIR) Wake-up 1 Input Type */\r
+#define SHDW_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SHDW_WUIR) Wake-up 2 Input Type */\r
+#define SHDW_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SHDW_WUIR) Wake-up 3 Input Type */\r
+#define SHDW_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SHDW_WUIR) Wake-up 4 Input Type */\r
+#define SHDW_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SHDW_WUIR) Wake-up 5 Input Type */\r
+#define SHDW_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SHDW_WUIR) Wake-up 6 Input Type */\r
+#define SHDW_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SHDW_WUIR) Wake-up 7 Input Type */\r
+#define SHDW_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SHDW_WUIR) Wake-up 8 Input Type */\r
+#define SHDW_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+#define SHDW_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_SHDWC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SMC_COMPONENT_\r
+#define _SAMA5D2_SMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Static Memory Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SMC Static Memory Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief SmcCs_number hardware registers */\r
+typedef struct {\r
+ __IO uint32_t HSMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) HSMC Setup Register */\r
+ __IO uint32_t HSMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) HSMC Pulse Register */\r
+ __IO uint32_t HSMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) HSMC Cycle Register */\r
+ __IO uint32_t HSMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) HSMC Timings Register */\r
+ __IO uint32_t HSMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) HSMC Mode Register */\r
+} SmcCs_number;\r
+/** \brief SmcPmecc hardware registers */\r
+typedef struct {\r
+ __I uint32_t HSMC_PMECC[14]; /**< \brief (SmcPmecc Offset: 0x0) PMECC Redundancy x Register */\r
+ __I uint32_t Reserved1[2];\r
+} SmcPmecc;\r
+/** \brief SmcRem hardware registers */\r
+typedef struct {\r
+ __I uint32_t HSMC_REM0_; /**< \brief (SmcRem Offset: 0x0) PMECC Remainder 0 Register */\r
+ __I uint32_t HSMC_REM1_; /**< \brief (SmcRem Offset: 0x4) PMECC Remainder 1 Register */\r
+ __I uint32_t HSMC_REM2_; /**< \brief (SmcRem Offset: 0x8) PMECC Remainder 2 Register */\r
+ __I uint32_t HSMC_REM3_; /**< \brief (SmcRem Offset: 0xC) PMECC Remainder 3 Register */\r
+ __I uint32_t HSMC_REM4_; /**< \brief (SmcRem Offset: 0x10) PMECC Remainder 4 Register */\r
+ __I uint32_t HSMC_REM5_; /**< \brief (SmcRem Offset: 0x14) PMECC Remainder 5 Register */\r
+ __I uint32_t HSMC_REM6_; /**< \brief (SmcRem Offset: 0x18) PMECC Remainder 6 Register */\r
+ __I uint32_t HSMC_REM7_; /**< \brief (SmcRem Offset: 0x1C) PMECC Remainder 7 Register */\r
+ __I uint32_t HSMC_REM8_; /**< \brief (SmcRem Offset: 0x20) PMECC Remainder 8 Register */\r
+ __I uint32_t HSMC_REM9_; /**< \brief (SmcRem Offset: 0x24) PMECC Remainder 9 Register */\r
+ __I uint32_t HSMC_REM10_; /**< \brief (SmcRem Offset: 0x28) PMECC Remainder 10 Register */\r
+ __I uint32_t HSMC_REM11_; /**< \brief (SmcRem Offset: 0x2C) PMECC Remainder 11 Register */\r
+ __I uint32_t HSMC_REM12_; /**< \brief (SmcRem Offset: 0x30) PMECC Remainder 12 Register */\r
+ __I uint32_t HSMC_REM13_; /**< \brief (SmcRem Offset: 0x34) PMECC Remainder 13 Register */\r
+ __I uint32_t HSMC_REM14_; /**< \brief (SmcRem Offset: 0x38) PMECC Remainder 14 Register */\r
+ __I uint32_t HSMC_REM15_; /**< \brief (SmcRem Offset: 0x3C) PMECC Remainder 15 Register */\r
+} SmcRem;\r
+/** \brief Smc hardware registers */\r
+#define SMCPMECC_NUMBER 8\r
+#define SMCREM_NUMBER 8\r
+#define SMCCS_NUMBER_NUMBER 4\r
+typedef struct {\r
+ __IO uint32_t HSMC_CFG; /**< \brief (Smc Offset: 0x000) HSMC NFC Configuration Register */\r
+ __O uint32_t HSMC_CTRL; /**< \brief (Smc Offset: 0x004) HSMC NFC Control Register */\r
+ __I uint32_t HSMC_SR; /**< \brief (Smc Offset: 0x008) HSMC NFC Status Register */\r
+ __O uint32_t HSMC_IER; /**< \brief (Smc Offset: 0x00C) HSMC NFC Interrupt Enable Register */\r
+ __O uint32_t HSMC_IDR; /**< \brief (Smc Offset: 0x010) HSMC NFC Interrupt Disable Register */\r
+ __I uint32_t HSMC_IMR; /**< \brief (Smc Offset: 0x014) HSMC NFC Interrupt Mask Register */\r
+ __IO uint32_t HSMC_ADDR; /**< \brief (Smc Offset: 0x018) HSMC NFC Address Cycle Zero Register */\r
+ __IO uint32_t HSMC_BANK; /**< \brief (Smc Offset: 0x01C) HSMC Bank Address Register */\r
+ __I uint32_t Reserved1[20];\r
+ __IO uint32_t HSMC_PMECCFG; /**< \brief (Smc Offset: 0x070) PMECC Configuration Register */\r
+ __IO uint32_t HSMC_PMECCSAREA; /**< \brief (Smc Offset: 0x074) PMECC Spare Area Size Register */\r
+ __IO uint32_t HSMC_PMECCSADDR; /**< \brief (Smc Offset: 0x078) PMECC Start Address Register */\r
+ __IO uint32_t HSMC_PMECCEADDR; /**< \brief (Smc Offset: 0x07C) PMECC End Address Register */\r
+ __I uint32_t Reserved2[1];\r
+ __O uint32_t HSMC_PMECCTRL; /**< \brief (Smc Offset: 0x084) PMECC Control Register */\r
+ __I uint32_t HSMC_PMECCSR; /**< \brief (Smc Offset: 0x088) PMECC Status Register */\r
+ __O uint32_t HSMC_PMECCIER; /**< \brief (Smc Offset: 0x08C) PMECC Interrupt Enable register */\r
+ __O uint32_t HSMC_PMECCIDR; /**< \brief (Smc Offset: 0x090) PMECC Interrupt Disable Register */\r
+ __I uint32_t HSMC_PMECCIMR; /**< \brief (Smc Offset: 0x094) PMECC Interrupt Mask Register */\r
+ __I uint32_t HSMC_PMECCISR; /**< \brief (Smc Offset: 0x098) PMECC Interrupt Status Register */\r
+ __I uint32_t Reserved3[5];\r
+ SmcPmecc SMC_PMECC[SMCPMECC_NUMBER]; /**< \brief (Smc Offset: 0xB0) sec_num = 0 .. 7 */\r
+ SmcRem SMC_REM[SMCREM_NUMBER]; /**< \brief (Smc Offset: 0x2B0) sec_num = 0 .. 7 */\r
+ __I uint32_t Reserved4[20];\r
+ __IO uint32_t HSMC_ELCFG; /**< \brief (Smc Offset: 0x500) PMECC Error Location Configuration Register */\r
+ __I uint32_t HSMC_ELPRIM; /**< \brief (Smc Offset: 0x504) PMECC Error Location Primitive Register */\r
+ __O uint32_t HSMC_ELEN; /**< \brief (Smc Offset: 0x508) PMECC Error Location Enable Register */\r
+ __O uint32_t HSMC_ELDIS; /**< \brief (Smc Offset: 0x50C) PMECC Error Location Disable Register */\r
+ __I uint32_t HSMC_ELSR; /**< \brief (Smc Offset: 0x510) PMECC Error Location Status Register */\r
+ __O uint32_t HSMC_ELIER; /**< \brief (Smc Offset: 0x514) PMECC Error Location Interrupt Enable register */\r
+ __O uint32_t HSMC_ELIDR; /**< \brief (Smc Offset: 0x518) PMECC Error Location Interrupt Disable Register */\r
+ __I uint32_t HSMC_ELIMR; /**< \brief (Smc Offset: 0x51C) PMECC Error Location Interrupt Mask Register */\r
+ __I uint32_t HSMC_ELISR; /**< \brief (Smc Offset: 0x520) PMECC Error Location Interrupt Status Register */\r
+ __I uint32_t Reserved5[1];\r
+ __I uint32_t HSMC_SIGMA0; /**< \brief (Smc Offset: 0x528) PMECC Error Location SIGMA 0 Register */\r
+ __IO uint32_t HSMC_SIGMA1; /**< \brief (Smc Offset: 0x52C) PMECC Error Location SIGMA 1 Register */\r
+ __IO uint32_t HSMC_SIGMA2; /**< \brief (Smc Offset: 0x530) PMECC Error Location SIGMA 2 Register */\r
+ __IO uint32_t HSMC_SIGMA3; /**< \brief (Smc Offset: 0x534) PMECC Error Location SIGMA 3 Register */\r
+ __IO uint32_t HSMC_SIGMA4; /**< \brief (Smc Offset: 0x538) PMECC Error Location SIGMA 4 Register */\r
+ __IO uint32_t HSMC_SIGMA5; /**< \brief (Smc Offset: 0x53C) PMECC Error Location SIGMA 5 Register */\r
+ __IO uint32_t HSMC_SIGMA6; /**< \brief (Smc Offset: 0x540) PMECC Error Location SIGMA 6 Register */\r
+ __IO uint32_t HSMC_SIGMA7; /**< \brief (Smc Offset: 0x544) PMECC Error Location SIGMA 7 Register */\r
+ __IO uint32_t HSMC_SIGMA8; /**< \brief (Smc Offset: 0x548) PMECC Error Location SIGMA 8 Register */\r
+ __IO uint32_t HSMC_SIGMA9; /**< \brief (Smc Offset: 0x54C) PMECC Error Location SIGMA 9 Register */\r
+ __IO uint32_t HSMC_SIGMA10; /**< \brief (Smc Offset: 0x550) PMECC Error Location SIGMA 10 Register */\r
+ __IO uint32_t HSMC_SIGMA11; /**< \brief (Smc Offset: 0x554) PMECC Error Location SIGMA 11 Register */\r
+ __IO uint32_t HSMC_SIGMA12; /**< \brief (Smc Offset: 0x558) PMECC Error Location SIGMA 12 Register */\r
+ __IO uint32_t HSMC_SIGMA13; /**< \brief (Smc Offset: 0x55C) PMECC Error Location SIGMA 13 Register */\r
+ __IO uint32_t HSMC_SIGMA14; /**< \brief (Smc Offset: 0x560) PMECC Error Location SIGMA 14 Register */\r
+ __IO uint32_t HSMC_SIGMA15; /**< \brief (Smc Offset: 0x564) PMECC Error Location SIGMA 15 Register */\r
+ __IO uint32_t HSMC_SIGMA16; /**< \brief (Smc Offset: 0x568) PMECC Error Location SIGMA 16 Register */\r
+ __IO uint32_t HSMC_SIGMA17; /**< \brief (Smc Offset: 0x56C) PMECC Error Location SIGMA 17 Register */\r
+ __IO uint32_t HSMC_SIGMA18; /**< \brief (Smc Offset: 0x570) PMECC Error Location SIGMA 18 Register */\r
+ __IO uint32_t HSMC_SIGMA19; /**< \brief (Smc Offset: 0x574) PMECC Error Location SIGMA 19 Register */\r
+ __IO uint32_t HSMC_SIGMA20; /**< \brief (Smc Offset: 0x578) PMECC Error Location SIGMA 20 Register */\r
+ __IO uint32_t HSMC_SIGMA21; /**< \brief (Smc Offset: 0x57C) PMECC Error Location SIGMA 21 Register */\r
+ __IO uint32_t HSMC_SIGMA22; /**< \brief (Smc Offset: 0x580) PMECC Error Location SIGMA 22 Register */\r
+ __IO uint32_t HSMC_SIGMA23; /**< \brief (Smc Offset: 0x584) PMECC Error Location SIGMA 23 Register */\r
+ __IO uint32_t HSMC_SIGMA24; /**< \brief (Smc Offset: 0x588) PMECC Error Location SIGMA 24 Register */\r
+ __IO uint32_t HSMC_SIGMA25; /**< \brief (Smc Offset: 0x58C) PMECC Error Location SIGMA 25 Register */\r
+ __IO uint32_t HSMC_SIGMA26; /**< \brief (Smc Offset: 0x590) PMECC Error Location SIGMA 26 Register */\r
+ __IO uint32_t HSMC_SIGMA27; /**< \brief (Smc Offset: 0x594) PMECC Error Location SIGMA 27 Register */\r
+ __IO uint32_t HSMC_SIGMA28; /**< \brief (Smc Offset: 0x598) PMECC Error Location SIGMA 28 Register */\r
+ __IO uint32_t HSMC_SIGMA29; /**< \brief (Smc Offset: 0x59C) PMECC Error Location SIGMA 29 Register */\r
+ __IO uint32_t HSMC_SIGMA30; /**< \brief (Smc Offset: 0x5A0) PMECC Error Location SIGMA 30 Register */\r
+ __IO uint32_t HSMC_SIGMA31; /**< \brief (Smc Offset: 0x5A4) PMECC Error Location SIGMA 31 Register */\r
+ __IO uint32_t HSMC_SIGMA32; /**< \brief (Smc Offset: 0x5A8) PMECC Error Location SIGMA 32 Register */\r
+ __I uint32_t HSMC_ERRLOC0; /**< \brief (Smc Offset: 0x5AC) PMECC Error Location 0 Register */\r
+ __I uint32_t HSMC_ERRLOC1; /**< \brief (Smc Offset: 0x5B0) PMECC Error Location 1 Register */\r
+ __I uint32_t HSMC_ERRLOC2; /**< \brief (Smc Offset: 0x5B4) PMECC Error Location 2 Register */\r
+ __I uint32_t HSMC_ERRLOC3; /**< \brief (Smc Offset: 0x5B8) PMECC Error Location 3 Register */\r
+ __I uint32_t HSMC_ERRLOC4; /**< \brief (Smc Offset: 0x5BC) PMECC Error Location 4 Register */\r
+ __I uint32_t HSMC_ERRLOC5; /**< \brief (Smc Offset: 0x5C0) PMECC Error Location 5 Register */\r
+ __I uint32_t HSMC_ERRLOC6; /**< \brief (Smc Offset: 0x5C4) PMECC Error Location 6 Register */\r
+ __I uint32_t HSMC_ERRLOC7; /**< \brief (Smc Offset: 0x5C8) PMECC Error Location 7 Register */\r
+ __I uint32_t HSMC_ERRLOC8; /**< \brief (Smc Offset: 0x5CC) PMECC Error Location 8 Register */\r
+ __I uint32_t HSMC_ERRLOC9; /**< \brief (Smc Offset: 0x5D0) PMECC Error Location 9 Register */\r
+ __I uint32_t HSMC_ERRLOC10; /**< \brief (Smc Offset: 0x5D4) PMECC Error Location 10 Register */\r
+ __I uint32_t HSMC_ERRLOC11; /**< \brief (Smc Offset: 0x5D8) PMECC Error Location 11 Register */\r
+ __I uint32_t HSMC_ERRLOC12; /**< \brief (Smc Offset: 0x5DC) PMECC Error Location 12 Register */\r
+ __I uint32_t HSMC_ERRLOC13; /**< \brief (Smc Offset: 0x5E0) PMECC Error Location 13 Register */\r
+ __I uint32_t HSMC_ERRLOC14; /**< \brief (Smc Offset: 0x5E4) PMECC Error Location 14 Register */\r
+ __I uint32_t HSMC_ERRLOC15; /**< \brief (Smc Offset: 0x5E8) PMECC Error Location 15 Register */\r
+ __I uint32_t HSMC_ERRLOC16; /**< \brief (Smc Offset: 0x5EC) PMECC Error Location 16 Register */\r
+ __I uint32_t HSMC_ERRLOC17; /**< \brief (Smc Offset: 0x5F0) PMECC Error Location 17 Register */\r
+ __I uint32_t HSMC_ERRLOC18; /**< \brief (Smc Offset: 0x5F4) PMECC Error Location 18 Register */\r
+ __I uint32_t HSMC_ERRLOC19; /**< \brief (Smc Offset: 0x5F8) PMECC Error Location 19 Register */\r
+ __I uint32_t HSMC_ERRLOC20; /**< \brief (Smc Offset: 0x5FC) PMECC Error Location 20 Register */\r
+ __I uint32_t HSMC_ERRLOC21; /**< \brief (Smc Offset: 0x600) PMECC Error Location 21 Register */\r
+ __I uint32_t HSMC_ERRLOC22; /**< \brief (Smc Offset: 0x604) PMECC Error Location 22 Register */\r
+ __I uint32_t HSMC_ERRLOC23; /**< \brief (Smc Offset: 0x608) PMECC Error Location 23 Register */\r
+ __I uint32_t HSMC_ERRLOC24; /**< \brief (Smc Offset: 0x60C) PMECC Error Location 24 Register */\r
+ __I uint32_t HSMC_ERRLOC25; /**< \brief (Smc Offset: 0x610) PMECC Error Location 25 Register */\r
+ __I uint32_t HSMC_ERRLOC26; /**< \brief (Smc Offset: 0x614) PMECC Error Location 26 Register */\r
+ __I uint32_t HSMC_ERRLOC27; /**< \brief (Smc Offset: 0x618) PMECC Error Location 27 Register */\r
+ __I uint32_t HSMC_ERRLOC28; /**< \brief (Smc Offset: 0x61C) PMECC Error Location 28 Register */\r
+ __I uint32_t HSMC_ERRLOC29; /**< \brief (Smc Offset: 0x620) PMECC Error Location 29 Register */\r
+ __I uint32_t HSMC_ERRLOC30; /**< \brief (Smc Offset: 0x624) PMECC Error Location 30 Register */\r
+ __I uint32_t HSMC_ERRLOC31; /**< \brief (Smc Offset: 0x628) PMECC Error Location 31 Register */\r
+ __I uint32_t Reserved6[53];\r
+ SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x700) CS_number = 0 .. 3 */\r
+ __I uint32_t Reserved7[20];\r
+ __IO uint32_t HSMC_OCMS; /**< \brief (Smc Offset: 0x7A0) HSMC Off Chip Memory Scrambling Register */\r
+ __O uint32_t HSMC_KEY1; /**< \brief (Smc Offset: 0x7A4) HSMC Off Chip Memory Scrambling KEY1 Register */\r
+ __O uint32_t HSMC_KEY2; /**< \brief (Smc Offset: 0x7A8) HSMC Off Chip Memory Scrambling KEY2 Register */\r
+ __I uint32_t Reserved8[14];\r
+ __IO uint32_t HSMC_WPMR; /**< \brief (Smc Offset: 0x7E4) HSMC Write Protection Mode Register */\r
+ __I uint32_t HSMC_WPSR; /**< \brief (Smc Offset: 0x7E8) HSMC Write Protection Status Register */\r
+ __I uint32_t Reserved9[4];\r
+ __I uint32_t HSMC_VERSION; /**< \brief (Smc Offset: 0x7FC) HSMC Version Register */\r
+} Smc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- HSMC_CFG : (SMC Offset: 0x000) HSMC NFC Configuration Register -------- */\r
+#define HSMC_CFG_PAGESIZE_Pos 0\r
+#define HSMC_CFG_PAGESIZE_Msk (0x7u << HSMC_CFG_PAGESIZE_Pos) /**< \brief (HSMC_CFG) Page Size of the NAND Flash Device */\r
+#define HSMC_CFG_PAGESIZE(value) ((HSMC_CFG_PAGESIZE_Msk & ((value) << HSMC_CFG_PAGESIZE_Pos)))\r
+#define HSMC_CFG_PAGESIZE_PS512 (0x0u << 0) /**< \brief (HSMC_CFG) Main area 512 bytes */\r
+#define HSMC_CFG_PAGESIZE_PS1024 (0x1u << 0) /**< \brief (HSMC_CFG) Main area 1024 bytes */\r
+#define HSMC_CFG_PAGESIZE_PS2048 (0x2u << 0) /**< \brief (HSMC_CFG) Main area 2048 bytes */\r
+#define HSMC_CFG_PAGESIZE_PS4096 (0x3u << 0) /**< \brief (HSMC_CFG) Main area 4096 bytes */\r
+#define HSMC_CFG_PAGESIZE_PS8192 (0x4u << 0) /**< \brief (HSMC_CFG) Main area 8192 bytes */\r
+#define HSMC_CFG_WSPARE (0x1u << 8) /**< \brief (HSMC_CFG) Write Spare Area */\r
+#define HSMC_CFG_RSPARE (0x1u << 9) /**< \brief (HSMC_CFG) Read Spare Area */\r
+#define HSMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (HSMC_CFG) Rising/Falling Edge Detection Control */\r
+#define HSMC_CFG_RBEDGE (0x1u << 13) /**< \brief (HSMC_CFG) Ready/Busy Signal Edge Detection */\r
+#define HSMC_CFG_DTOCYC_Pos 16\r
+#define HSMC_CFG_DTOCYC_Msk (0xfu << HSMC_CFG_DTOCYC_Pos) /**< \brief (HSMC_CFG) Data Timeout Cycle Number */\r
+#define HSMC_CFG_DTOCYC(value) ((HSMC_CFG_DTOCYC_Msk & ((value) << HSMC_CFG_DTOCYC_Pos)))\r
+#define HSMC_CFG_DTOMUL_Pos 20\r
+#define HSMC_CFG_DTOMUL_Msk (0x7u << HSMC_CFG_DTOMUL_Pos) /**< \brief (HSMC_CFG) Data Timeout Multiplier */\r
+#define HSMC_CFG_DTOMUL(value) ((HSMC_CFG_DTOMUL_Msk & ((value) << HSMC_CFG_DTOMUL_Pos)))\r
+#define HSMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (HSMC_CFG) DTOCYC */\r
+#define HSMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (HSMC_CFG) DTOCYC x 16 */\r
+#define HSMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (HSMC_CFG) DTOCYC x 128 */\r
+#define HSMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (HSMC_CFG) DTOCYC x 256 */\r
+#define HSMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (HSMC_CFG) DTOCYC x 1024 */\r
+#define HSMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (HSMC_CFG) DTOCYC x 4096 */\r
+#define HSMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (HSMC_CFG) DTOCYC x 65536 */\r
+#define HSMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (HSMC_CFG) DTOCYC x 1048576 */\r
+#define HSMC_CFG_NFCSPARESIZE_Pos 24\r
+#define HSMC_CFG_NFCSPARESIZE_Msk (0x7fu << HSMC_CFG_NFCSPARESIZE_Pos) /**< \brief (HSMC_CFG) NAND Flash Spare Area Size Retrieved by the Host Controller */\r
+#define HSMC_CFG_NFCSPARESIZE(value) ((HSMC_CFG_NFCSPARESIZE_Msk & ((value) << HSMC_CFG_NFCSPARESIZE_Pos)))\r
+/* -------- HSMC_CTRL : (SMC Offset: 0x004) HSMC NFC Control Register -------- */\r
+#define HSMC_CTRL_NFCEN (0x1u << 0) /**< \brief (HSMC_CTRL) NAND Flash Controller Enable */\r
+#define HSMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (HSMC_CTRL) NAND Flash Controller Disable */\r
+/* -------- HSMC_SR : (SMC Offset: 0x008) HSMC NFC Status Register -------- */\r
+#define HSMC_SR_SMCSTS (0x1u << 0) /**< \brief (HSMC_SR) NAND Flash Controller Status (this field cannot be reset) */\r
+#define HSMC_SR_RB_RISE (0x1u << 4) /**< \brief (HSMC_SR) Selected Ready Busy Rising Edge Detected */\r
+#define HSMC_SR_RB_FALL (0x1u << 5) /**< \brief (HSMC_SR) Selected Ready Busy Falling Edge Detected */\r
+#define HSMC_SR_NFCBUSY (0x1u << 8) /**< \brief (HSMC_SR) NFC Busy (this field cannot be reset) */\r
+#define HSMC_SR_NFCWR (0x1u << 11) /**< \brief (HSMC_SR) NFC Write/Read Operation (this field cannot be reset) */\r
+#define HSMC_SR_NFCSID_Pos 12\r
+#define HSMC_SR_NFCSID_Msk (0x7u << HSMC_SR_NFCSID_Pos) /**< \brief (HSMC_SR) NFC Chip Select ID (this field cannot be reset) */\r
+#define HSMC_SR_XFRDONE (0x1u << 16) /**< \brief (HSMC_SR) NFC Data Transfer Terminated */\r
+#define HSMC_SR_CMDDONE (0x1u << 17) /**< \brief (HSMC_SR) Command Done */\r
+#define HSMC_SR_DTOE (0x1u << 20) /**< \brief (HSMC_SR) Data Timeout Error */\r
+#define HSMC_SR_UNDEF (0x1u << 21) /**< \brief (HSMC_SR) Undefined Area Error */\r
+#define HSMC_SR_AWB (0x1u << 22) /**< \brief (HSMC_SR) Accessing While Busy */\r
+#define HSMC_SR_NFCASE (0x1u << 23) /**< \brief (HSMC_SR) NFC Access Size Error */\r
+#define HSMC_SR_RB_EDGE3 (0x1u << 27) /**< \brief (HSMC_SR) Ready/Busy Line 3 Edge Detected */\r
+/* -------- HSMC_IER : (SMC Offset: 0x00C) HSMC NFC Interrupt Enable Register -------- */\r
+#define HSMC_IER_RB_RISE (0x1u << 4) /**< \brief (HSMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */\r
+#define HSMC_IER_RB_FALL (0x1u << 5) /**< \brief (HSMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */\r
+#define HSMC_IER_XFRDONE (0x1u << 16) /**< \brief (HSMC_IER) Transfer Done Interrupt Enable */\r
+#define HSMC_IER_CMDDONE (0x1u << 17) /**< \brief (HSMC_IER) Command Done Interrupt Enable */\r
+#define HSMC_IER_DTOE (0x1u << 20) /**< \brief (HSMC_IER) Data Timeout Error Interrupt Enable */\r
+#define HSMC_IER_UNDEF (0x1u << 21) /**< \brief (HSMC_IER) Undefined Area Access Interrupt Enable */\r
+#define HSMC_IER_AWB (0x1u << 22) /**< \brief (HSMC_IER) Accessing While Busy Interrupt Enable */\r
+#define HSMC_IER_NFCASE (0x1u << 23) /**< \brief (HSMC_IER) NFC Access Size Error Interrupt Enable */\r
+#define HSMC_IER_RB_EDGE3 (0x1u << 27) /**< \brief (HSMC_IER) Ready/Busy Line 3 Interrupt Enable */\r
+/* -------- HSMC_IDR : (SMC Offset: 0x010) HSMC NFC Interrupt Disable Register -------- */\r
+#define HSMC_IDR_RB_RISE (0x1u << 4) /**< \brief (HSMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */\r
+#define HSMC_IDR_RB_FALL (0x1u << 5) /**< \brief (HSMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */\r
+#define HSMC_IDR_XFRDONE (0x1u << 16) /**< \brief (HSMC_IDR) Transfer Done Interrupt Disable */\r
+#define HSMC_IDR_CMDDONE (0x1u << 17) /**< \brief (HSMC_IDR) Command Done Interrupt Disable */\r
+#define HSMC_IDR_DTOE (0x1u << 20) /**< \brief (HSMC_IDR) Data Timeout Error Interrupt Disable */\r
+#define HSMC_IDR_UNDEF (0x1u << 21) /**< \brief (HSMC_IDR) Undefined Area Access Interrupt Disable */\r
+#define HSMC_IDR_AWB (0x1u << 22) /**< \brief (HSMC_IDR) Accessing While Busy Interrupt Disable */\r
+#define HSMC_IDR_NFCASE (0x1u << 23) /**< \brief (HSMC_IDR) NFC Access Size Error Interrupt Disable */\r
+#define HSMC_IDR_RB_EDGE3 (0x1u << 27) /**< \brief (HSMC_IDR) Ready/Busy Line 3 Interrupt Disable */\r
+/* -------- HSMC_IMR : (SMC Offset: 0x014) HSMC NFC Interrupt Mask Register -------- */\r
+#define HSMC_IMR_RB_RISE (0x1u << 4) /**< \brief (HSMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */\r
+#define HSMC_IMR_RB_FALL (0x1u << 5) /**< \brief (HSMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */\r
+#define HSMC_IMR_XFRDONE (0x1u << 16) /**< \brief (HSMC_IMR) Transfer Done Interrupt Mask */\r
+#define HSMC_IMR_CMDDONE (0x1u << 17) /**< \brief (HSMC_IMR) Command Done Interrupt Mask */\r
+#define HSMC_IMR_DTOE (0x1u << 20) /**< \brief (HSMC_IMR) Data Timeout Error Interrupt Mask */\r
+#define HSMC_IMR_UNDEF (0x1u << 21) /**< \brief (HSMC_IMR) Undefined Area Access Interrupt Mask5 */\r
+#define HSMC_IMR_AWB (0x1u << 22) /**< \brief (HSMC_IMR) Accessing While Busy Interrupt Mask */\r
+#define HSMC_IMR_NFCASE (0x1u << 23) /**< \brief (HSMC_IMR) NFC Access Size Error Interrupt Mask */\r
+#define HSMC_IMR_RB_EDGE3 (0x1u << 27) /**< \brief (HSMC_IMR) Ready/Busy Line 3 Interrupt Mask */\r
+/* -------- HSMC_ADDR : (SMC Offset: 0x018) HSMC NFC Address Cycle Zero Register -------- */\r
+#define HSMC_ADDR_ADDR_CYCLE0_Pos 0\r
+#define HSMC_ADDR_ADDR_CYCLE0_Msk (0xffu << HSMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (HSMC_ADDR) NAND Flash Array Address Cycle 0 */\r
+#define HSMC_ADDR_ADDR_CYCLE0(value) ((HSMC_ADDR_ADDR_CYCLE0_Msk & ((value) << HSMC_ADDR_ADDR_CYCLE0_Pos)))\r
+/* -------- HSMC_BANK : (SMC Offset: 0x01C) HSMC Bank Address Register -------- */\r
+#define HSMC_BANK_BANK (0x1u << 0) /**< \brief (HSMC_BANK) Bank Identifier */\r
+/* -------- HSMC_PMECCFG : (SMC Offset: 0x070) PMECC Configuration Register -------- */\r
+#define HSMC_PMECCFG_BCH_ERR_Pos 0\r
+#define HSMC_PMECCFG_BCH_ERR_Msk (0x7u << HSMC_PMECCFG_BCH_ERR_Pos) /**< \brief (HSMC_PMECCFG) Error Correcting Capability */\r
+#define HSMC_PMECCFG_BCH_ERR(value) ((HSMC_PMECCFG_BCH_ERR_Msk & ((value) << HSMC_PMECCFG_BCH_ERR_Pos)))\r
+#define HSMC_PMECCFG_BCH_ERR_BCH_ERR2 (0x0u << 0) /**< \brief (HSMC_PMECCFG) 2 errors */\r
+#define HSMC_PMECCFG_BCH_ERR_BCH_ERR4 (0x1u << 0) /**< \brief (HSMC_PMECCFG) 4 errors */\r
+#define HSMC_PMECCFG_BCH_ERR_BCH_ERR8 (0x2u << 0) /**< \brief (HSMC_PMECCFG) 8 errors */\r
+#define HSMC_PMECCFG_BCH_ERR_BCH_ERR12 (0x3u << 0) /**< \brief (HSMC_PMECCFG) 12 errors */\r
+#define HSMC_PMECCFG_BCH_ERR_BCH_ERR24 (0x4u << 0) /**< \brief (HSMC_PMECCFG) 24 errors */\r
+#define HSMC_PMECCFG_BCH_ERR_BCH_ERR32 (0x5u << 0) /**< \brief (HSMC_PMECCFG) 32 errors */\r
+#define HSMC_PMECCFG_SECTORSZ (0x1u << 4) /**< \brief (HSMC_PMECCFG) Sector Size */\r
+#define HSMC_PMECCFG_PAGESIZE_Pos 8\r
+#define HSMC_PMECCFG_PAGESIZE_Msk (0x3u << HSMC_PMECCFG_PAGESIZE_Pos) /**< \brief (HSMC_PMECCFG) Number of Sectors in the Page */\r
+#define HSMC_PMECCFG_PAGESIZE(value) ((HSMC_PMECCFG_PAGESIZE_Msk & ((value) << HSMC_PMECCFG_PAGESIZE_Pos)))\r
+#define HSMC_PMECCFG_PAGESIZE_PAGESIZE_1SEC (0x0u << 8) /**< \brief (HSMC_PMECCFG) 1 sector for main area (512 or 1024 bytes) */\r
+#define HSMC_PMECCFG_PAGESIZE_PAGESIZE_2SEC (0x1u << 8) /**< \brief (HSMC_PMECCFG) 2 sectors for main area (1024 or 2048 bytes) */\r
+#define HSMC_PMECCFG_PAGESIZE_PAGESIZE_4SEC (0x2u << 8) /**< \brief (HSMC_PMECCFG) 4 sectors for main area (2048 or 4096 bytes) */\r
+#define HSMC_PMECCFG_PAGESIZE_PAGESIZE_8SEC (0x3u << 8) /**< \brief (HSMC_PMECCFG) 8 sectors for main area (4096 or 8192 bytes) */\r
+#define HSMC_PMECCFG_NANDWR (0x1u << 12) /**< \brief (HSMC_PMECCFG) NAND Write Access */\r
+#define HSMC_PMECCFG_SPAREEN (0x1u << 16) /**< \brief (HSMC_PMECCFG) Spare Enable */\r
+#define HSMC_PMECCFG_AUTO (0x1u << 20) /**< \brief (HSMC_PMECCFG) Automatic Mode Enable */\r
+/* -------- HSMC_PMECCSAREA : (SMC Offset: 0x074) PMECC Spare Area Size Register -------- */\r
+#define HSMC_PMECCSAREA_SPARESIZE_Pos 0\r
+#define HSMC_PMECCSAREA_SPARESIZE_Msk (0x1ffu << HSMC_PMECCSAREA_SPARESIZE_Pos) /**< \brief (HSMC_PMECCSAREA) Spare Area Size */\r
+#define HSMC_PMECCSAREA_SPARESIZE(value) ((HSMC_PMECCSAREA_SPARESIZE_Msk & ((value) << HSMC_PMECCSAREA_SPARESIZE_Pos)))\r
+/* -------- HSMC_PMECCSADDR : (SMC Offset: 0x078) PMECC Start Address Register -------- */\r
+#define HSMC_PMECCSADDR_STARTADDR_Pos 0\r
+#define HSMC_PMECCSADDR_STARTADDR_Msk (0x1ffu << HSMC_PMECCSADDR_STARTADDR_Pos) /**< \brief (HSMC_PMECCSADDR) ECC Area Start Address */\r
+#define HSMC_PMECCSADDR_STARTADDR(value) ((HSMC_PMECCSADDR_STARTADDR_Msk & ((value) << HSMC_PMECCSADDR_STARTADDR_Pos)))\r
+/* -------- HSMC_PMECCEADDR : (SMC Offset: 0x07C) PMECC End Address Register -------- */\r
+#define HSMC_PMECCEADDR_ENDADDR_Pos 0\r
+#define HSMC_PMECCEADDR_ENDADDR_Msk (0x1ffu << HSMC_PMECCEADDR_ENDADDR_Pos) /**< \brief (HSMC_PMECCEADDR) ECC Area End Address */\r
+#define HSMC_PMECCEADDR_ENDADDR(value) ((HSMC_PMECCEADDR_ENDADDR_Msk & ((value) << HSMC_PMECCEADDR_ENDADDR_Pos)))\r
+/* -------- HSMC_PMECCTRL : (SMC Offset: 0x084) PMECC Control Register -------- */\r
+#define HSMC_PMECCTRL_RST (0x1u << 0) /**< \brief (HSMC_PMECCTRL) Reset the PMECC Module */\r
+#define HSMC_PMECCTRL_DATA (0x1u << 1) /**< \brief (HSMC_PMECCTRL) Start a Data Phase */\r
+#define HSMC_PMECCTRL_USER (0x1u << 2) /**< \brief (HSMC_PMECCTRL) Start a User Mode Phase */\r
+#define HSMC_PMECCTRL_ENABLE (0x1u << 4) /**< \brief (HSMC_PMECCTRL) PMECC Enable */\r
+#define HSMC_PMECCTRL_DISABLE (0x1u << 5) /**< \brief (HSMC_PMECCTRL) PMECC Enable */\r
+/* -------- HSMC_PMECCSR : (SMC Offset: 0x088) PMECC Status Register -------- */\r
+#define HSMC_PMECCSR_BUSY (0x1u << 0) /**< \brief (HSMC_PMECCSR) The kernel of the PMECC is busy */\r
+#define HSMC_PMECCSR_ENABLE (0x1u << 4) /**< \brief (HSMC_PMECCSR) PMECC Enable bit */\r
+/* -------- HSMC_PMECCIER : (SMC Offset: 0x08C) PMECC Interrupt Enable register -------- */\r
+#define HSMC_PMECCIER_ERRIE (0x1u << 0) /**< \brief (HSMC_PMECCIER) Error Interrupt Enable */\r
+/* -------- HSMC_PMECCIDR : (SMC Offset: 0x090) PMECC Interrupt Disable Register -------- */\r
+#define HSMC_PMECCIDR_ERRID (0x1u << 0) /**< \brief (HSMC_PMECCIDR) Error Interrupt Disable */\r
+/* -------- HSMC_PMECCIMR : (SMC Offset: 0x094) PMECC Interrupt Mask Register -------- */\r
+#define HSMC_PMECCIMR_ERRIM (0x1u << 0) /**< \brief (HSMC_PMECCIMR) Error Interrupt Mask */\r
+/* -------- HSMC_PMECCISR : (SMC Offset: 0x098) PMECC Interrupt Status Register -------- */\r
+#define HSMC_PMECCISR_ERRIS_Pos 0\r
+#define HSMC_PMECCISR_ERRIS_Msk (0xffu << HSMC_PMECCISR_ERRIS_Pos) /**< \brief (HSMC_PMECCISR) Error Interrupt Status Register */\r
+/* -------- HSMC_PMECC[14] : (SMC Offset: N/A) PMECC Redundancy x Register -------- */\r
+#define HSMC_PMECC_ECC_Pos 0\r
+#define HSMC_PMECC_ECC_Msk (0xffffffffu << HSMC_PMECC_ECC_Pos) /**< \brief (HSMC_PMECC[14]) BCH Redundancy */\r
+/* -------- HSMC_REM0_ : (SMC Offset: N/A) PMECC Remainder 0 Register -------- */\r
+#define HSMC_REM0__REM2NP1_Pos 0\r
+#define HSMC_REM0__REM2NP1_Msk (0x3fffu << HSMC_REM0__REM2NP1_Pos) /**< \brief (HSMC_REM0_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM0__REM2NP3_Pos 16\r
+#define HSMC_REM0__REM2NP3_Msk (0x3fffu << HSMC_REM0__REM2NP3_Pos) /**< \brief (HSMC_REM0_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM1_ : (SMC Offset: N/A) PMECC Remainder 1 Register -------- */\r
+#define HSMC_REM1__REM2NP1_Pos 0\r
+#define HSMC_REM1__REM2NP1_Msk (0x3fffu << HSMC_REM1__REM2NP1_Pos) /**< \brief (HSMC_REM1_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM1__REM2NP3_Pos 16\r
+#define HSMC_REM1__REM2NP3_Msk (0x3fffu << HSMC_REM1__REM2NP3_Pos) /**< \brief (HSMC_REM1_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM2_ : (SMC Offset: N/A) PMECC Remainder 2 Register -------- */\r
+#define HSMC_REM2__REM2NP1_Pos 0\r
+#define HSMC_REM2__REM2NP1_Msk (0x3fffu << HSMC_REM2__REM2NP1_Pos) /**< \brief (HSMC_REM2_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM2__REM2NP3_Pos 16\r
+#define HSMC_REM2__REM2NP3_Msk (0x3fffu << HSMC_REM2__REM2NP3_Pos) /**< \brief (HSMC_REM2_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM3_ : (SMC Offset: N/A) PMECC Remainder 3 Register -------- */\r
+#define HSMC_REM3__REM2NP1_Pos 0\r
+#define HSMC_REM3__REM2NP1_Msk (0x3fffu << HSMC_REM3__REM2NP1_Pos) /**< \brief (HSMC_REM3_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM3__REM2NP3_Pos 16\r
+#define HSMC_REM3__REM2NP3_Msk (0x3fffu << HSMC_REM3__REM2NP3_Pos) /**< \brief (HSMC_REM3_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM4_ : (SMC Offset: N/A) PMECC Remainder 4 Register -------- */\r
+#define HSMC_REM4__REM2NP1_Pos 0\r
+#define HSMC_REM4__REM2NP1_Msk (0x3fffu << HSMC_REM4__REM2NP1_Pos) /**< \brief (HSMC_REM4_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM4__REM2NP3_Pos 16\r
+#define HSMC_REM4__REM2NP3_Msk (0x3fffu << HSMC_REM4__REM2NP3_Pos) /**< \brief (HSMC_REM4_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM5_ : (SMC Offset: N/A) PMECC Remainder 5 Register -------- */\r
+#define HSMC_REM5__REM2NP1_Pos 0\r
+#define HSMC_REM5__REM2NP1_Msk (0x3fffu << HSMC_REM5__REM2NP1_Pos) /**< \brief (HSMC_REM5_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM5__REM2NP3_Pos 16\r
+#define HSMC_REM5__REM2NP3_Msk (0x3fffu << HSMC_REM5__REM2NP3_Pos) /**< \brief (HSMC_REM5_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM6_ : (SMC Offset: N/A) PMECC Remainder 6 Register -------- */\r
+#define HSMC_REM6__REM2NP1_Pos 0\r
+#define HSMC_REM6__REM2NP1_Msk (0x3fffu << HSMC_REM6__REM2NP1_Pos) /**< \brief (HSMC_REM6_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM6__REM2NP3_Pos 16\r
+#define HSMC_REM6__REM2NP3_Msk (0x3fffu << HSMC_REM6__REM2NP3_Pos) /**< \brief (HSMC_REM6_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM7_ : (SMC Offset: N/A) PMECC Remainder 7 Register -------- */\r
+#define HSMC_REM7__REM2NP1_Pos 0\r
+#define HSMC_REM7__REM2NP1_Msk (0x3fffu << HSMC_REM7__REM2NP1_Pos) /**< \brief (HSMC_REM7_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM7__REM2NP3_Pos 16\r
+#define HSMC_REM7__REM2NP3_Msk (0x3fffu << HSMC_REM7__REM2NP3_Pos) /**< \brief (HSMC_REM7_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM8_ : (SMC Offset: N/A) PMECC Remainder 8 Register -------- */\r
+#define HSMC_REM8__REM2NP1_Pos 0\r
+#define HSMC_REM8__REM2NP1_Msk (0x3fffu << HSMC_REM8__REM2NP1_Pos) /**< \brief (HSMC_REM8_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM8__REM2NP3_Pos 16\r
+#define HSMC_REM8__REM2NP3_Msk (0x3fffu << HSMC_REM8__REM2NP3_Pos) /**< \brief (HSMC_REM8_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM9_ : (SMC Offset: N/A) PMECC Remainder 9 Register -------- */\r
+#define HSMC_REM9__REM2NP1_Pos 0\r
+#define HSMC_REM9__REM2NP1_Msk (0x3fffu << HSMC_REM9__REM2NP1_Pos) /**< \brief (HSMC_REM9_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM9__REM2NP3_Pos 16\r
+#define HSMC_REM9__REM2NP3_Msk (0x3fffu << HSMC_REM9__REM2NP3_Pos) /**< \brief (HSMC_REM9_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM10_ : (SMC Offset: N/A) PMECC Remainder 10 Register -------- */\r
+#define HSMC_REM10__REM2NP1_Pos 0\r
+#define HSMC_REM10__REM2NP1_Msk (0x3fffu << HSMC_REM10__REM2NP1_Pos) /**< \brief (HSMC_REM10_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM10__REM2NP3_Pos 16\r
+#define HSMC_REM10__REM2NP3_Msk (0x3fffu << HSMC_REM10__REM2NP3_Pos) /**< \brief (HSMC_REM10_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM11_ : (SMC Offset: N/A) PMECC Remainder 11 Register -------- */\r
+#define HSMC_REM11__REM2NP1_Pos 0\r
+#define HSMC_REM11__REM2NP1_Msk (0x3fffu << HSMC_REM11__REM2NP1_Pos) /**< \brief (HSMC_REM11_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM11__REM2NP3_Pos 16\r
+#define HSMC_REM11__REM2NP3_Msk (0x3fffu << HSMC_REM11__REM2NP3_Pos) /**< \brief (HSMC_REM11_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM12_ : (SMC Offset: N/A) PMECC Remainder 12 Register -------- */\r
+#define HSMC_REM12__REM2NP1_Pos 0\r
+#define HSMC_REM12__REM2NP1_Msk (0x3fffu << HSMC_REM12__REM2NP1_Pos) /**< \brief (HSMC_REM12_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM12__REM2NP3_Pos 16\r
+#define HSMC_REM12__REM2NP3_Msk (0x3fffu << HSMC_REM12__REM2NP3_Pos) /**< \brief (HSMC_REM12_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM13_ : (SMC Offset: N/A) PMECC Remainder 13 Register -------- */\r
+#define HSMC_REM13__REM2NP1_Pos 0\r
+#define HSMC_REM13__REM2NP1_Msk (0x3fffu << HSMC_REM13__REM2NP1_Pos) /**< \brief (HSMC_REM13_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM13__REM2NP3_Pos 16\r
+#define HSMC_REM13__REM2NP3_Msk (0x3fffu << HSMC_REM13__REM2NP3_Pos) /**< \brief (HSMC_REM13_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM14_ : (SMC Offset: N/A) PMECC Remainder 14 Register -------- */\r
+#define HSMC_REM14__REM2NP1_Pos 0\r
+#define HSMC_REM14__REM2NP1_Msk (0x3fffu << HSMC_REM14__REM2NP1_Pos) /**< \brief (HSMC_REM14_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM14__REM2NP3_Pos 16\r
+#define HSMC_REM14__REM2NP3_Msk (0x3fffu << HSMC_REM14__REM2NP3_Pos) /**< \brief (HSMC_REM14_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_REM15_ : (SMC Offset: N/A) PMECC Remainder 15 Register -------- */\r
+#define HSMC_REM15__REM2NP1_Pos 0\r
+#define HSMC_REM15__REM2NP1_Msk (0x3fffu << HSMC_REM15__REM2NP1_Pos) /**< \brief (HSMC_REM15_) BCH Remainder 2 * N + 1 */\r
+#define HSMC_REM15__REM2NP3_Pos 16\r
+#define HSMC_REM15__REM2NP3_Msk (0x3fffu << HSMC_REM15__REM2NP3_Pos) /**< \brief (HSMC_REM15_) BCH Remainder 2 * N + 3 */\r
+/* -------- HSMC_ELCFG : (SMC Offset: 0x500) PMECC Error Location Configuration Register -------- */\r
+#define HSMC_ELCFG_SECTORSZ (0x1u << 0) /**< \brief (HSMC_ELCFG) Sector Size */\r
+#define HSMC_ELCFG_ERRNUM_Pos 16\r
+#define HSMC_ELCFG_ERRNUM_Msk (0x1fu << HSMC_ELCFG_ERRNUM_Pos) /**< \brief (HSMC_ELCFG) Number of Errors */\r
+#define HSMC_ELCFG_ERRNUM(value) ((HSMC_ELCFG_ERRNUM_Msk & ((value) << HSMC_ELCFG_ERRNUM_Pos)))\r
+/* -------- HSMC_ELPRIM : (SMC Offset: 0x504) PMECC Error Location Primitive Register -------- */\r
+#define HSMC_ELPRIM_PRIMITIV_Pos 0\r
+#define HSMC_ELPRIM_PRIMITIV_Msk (0xffffu << HSMC_ELPRIM_PRIMITIV_Pos) /**< \brief (HSMC_ELPRIM) Primitive Polynomial */\r
+/* -------- HSMC_ELEN : (SMC Offset: 0x508) PMECC Error Location Enable Register -------- */\r
+#define HSMC_ELEN_ENINIT_Pos 0\r
+#define HSMC_ELEN_ENINIT_Msk (0x3fffu << HSMC_ELEN_ENINIT_Pos) /**< \brief (HSMC_ELEN) Error Location Enable */\r
+#define HSMC_ELEN_ENINIT(value) ((HSMC_ELEN_ENINIT_Msk & ((value) << HSMC_ELEN_ENINIT_Pos)))\r
+/* -------- HSMC_ELDIS : (SMC Offset: 0x50C) PMECC Error Location Disable Register -------- */\r
+#define HSMC_ELDIS_DIS (0x1u << 0) /**< \brief (HSMC_ELDIS) Disable Error Location Engine */\r
+/* -------- HSMC_ELSR : (SMC Offset: 0x510) PMECC Error Location Status Register -------- */\r
+#define HSMC_ELSR_BUSY (0x1u << 0) /**< \brief (HSMC_ELSR) Error Location Engine Busy */\r
+/* -------- HSMC_ELIER : (SMC Offset: 0x514) PMECC Error Location Interrupt Enable register -------- */\r
+#define HSMC_ELIER_DONE (0x1u << 0) /**< \brief (HSMC_ELIER) Computation Terminated Interrupt Enable */\r
+/* -------- HSMC_ELIDR : (SMC Offset: 0x518) PMECC Error Location Interrupt Disable Register -------- */\r
+#define HSMC_ELIDR_DONE (0x1u << 0) /**< \brief (HSMC_ELIDR) Computation Terminated Interrupt Disable */\r
+/* -------- HSMC_ELIMR : (SMC Offset: 0x51C) PMECC Error Location Interrupt Mask Register -------- */\r
+#define HSMC_ELIMR_DONE (0x1u << 0) /**< \brief (HSMC_ELIMR) Computation Terminated Interrupt Mask */\r
+/* -------- HSMC_ELISR : (SMC Offset: 0x520) PMECC Error Location Interrupt Status Register -------- */\r
+#define HSMC_ELISR_DONE (0x1u << 0) /**< \brief (HSMC_ELISR) Computation Terminated Interrupt Status */\r
+#define HSMC_ELISR_ERR_CNT_Pos 8\r
+#define HSMC_ELISR_ERR_CNT_Msk (0x3fu << HSMC_ELISR_ERR_CNT_Pos) /**< \brief (HSMC_ELISR) Error Counter value */\r
+/* -------- HSMC_SIGMA0 : (SMC Offset: 0x528) PMECC Error Location SIGMA 0 Register -------- */\r
+#define HSMC_SIGMA0_SIGMA0_Pos 0\r
+#define HSMC_SIGMA0_SIGMA0_Msk (0x3fffu << HSMC_SIGMA0_SIGMA0_Pos) /**< \brief (HSMC_SIGMA0) Coefficient of degree 0 in the SIGMA polynomial */\r
+/* -------- HSMC_SIGMA1 : (SMC Offset: 0x52C) PMECC Error Location SIGMA 1 Register -------- */\r
+#define HSMC_SIGMA1_SIGMA1_Pos 0\r
+#define HSMC_SIGMA1_SIGMA1_Msk (0x3fffu << HSMC_SIGMA1_SIGMA1_Pos) /**< \brief (HSMC_SIGMA1) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA1_SIGMA1(value) ((HSMC_SIGMA1_SIGMA1_Msk & ((value) << HSMC_SIGMA1_SIGMA1_Pos)))\r
+/* -------- HSMC_SIGMA2 : (SMC Offset: 0x530) PMECC Error Location SIGMA 2 Register -------- */\r
+#define HSMC_SIGMA2_SIGMA2_Pos 0\r
+#define HSMC_SIGMA2_SIGMA2_Msk (0x3fffu << HSMC_SIGMA2_SIGMA2_Pos) /**< \brief (HSMC_SIGMA2) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA2_SIGMA2(value) ((HSMC_SIGMA2_SIGMA2_Msk & ((value) << HSMC_SIGMA2_SIGMA2_Pos)))\r
+/* -------- HSMC_SIGMA3 : (SMC Offset: 0x534) PMECC Error Location SIGMA 3 Register -------- */\r
+#define HSMC_SIGMA3_SIGMA3_Pos 0\r
+#define HSMC_SIGMA3_SIGMA3_Msk (0x3fffu << HSMC_SIGMA3_SIGMA3_Pos) /**< \brief (HSMC_SIGMA3) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA3_SIGMA3(value) ((HSMC_SIGMA3_SIGMA3_Msk & ((value) << HSMC_SIGMA3_SIGMA3_Pos)))\r
+/* -------- HSMC_SIGMA4 : (SMC Offset: 0x538) PMECC Error Location SIGMA 4 Register -------- */\r
+#define HSMC_SIGMA4_SIGMA4_Pos 0\r
+#define HSMC_SIGMA4_SIGMA4_Msk (0x3fffu << HSMC_SIGMA4_SIGMA4_Pos) /**< \brief (HSMC_SIGMA4) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA4_SIGMA4(value) ((HSMC_SIGMA4_SIGMA4_Msk & ((value) << HSMC_SIGMA4_SIGMA4_Pos)))\r
+/* -------- HSMC_SIGMA5 : (SMC Offset: 0x53C) PMECC Error Location SIGMA 5 Register -------- */\r
+#define HSMC_SIGMA5_SIGMA5_Pos 0\r
+#define HSMC_SIGMA5_SIGMA5_Msk (0x3fffu << HSMC_SIGMA5_SIGMA5_Pos) /**< \brief (HSMC_SIGMA5) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA5_SIGMA5(value) ((HSMC_SIGMA5_SIGMA5_Msk & ((value) << HSMC_SIGMA5_SIGMA5_Pos)))\r
+/* -------- HSMC_SIGMA6 : (SMC Offset: 0x540) PMECC Error Location SIGMA 6 Register -------- */\r
+#define HSMC_SIGMA6_SIGMA6_Pos 0\r
+#define HSMC_SIGMA6_SIGMA6_Msk (0x3fffu << HSMC_SIGMA6_SIGMA6_Pos) /**< \brief (HSMC_SIGMA6) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA6_SIGMA6(value) ((HSMC_SIGMA6_SIGMA6_Msk & ((value) << HSMC_SIGMA6_SIGMA6_Pos)))\r
+/* -------- HSMC_SIGMA7 : (SMC Offset: 0x544) PMECC Error Location SIGMA 7 Register -------- */\r
+#define HSMC_SIGMA7_SIGMA7_Pos 0\r
+#define HSMC_SIGMA7_SIGMA7_Msk (0x3fffu << HSMC_SIGMA7_SIGMA7_Pos) /**< \brief (HSMC_SIGMA7) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA7_SIGMA7(value) ((HSMC_SIGMA7_SIGMA7_Msk & ((value) << HSMC_SIGMA7_SIGMA7_Pos)))\r
+/* -------- HSMC_SIGMA8 : (SMC Offset: 0x548) PMECC Error Location SIGMA 8 Register -------- */\r
+#define HSMC_SIGMA8_SIGMA8_Pos 0\r
+#define HSMC_SIGMA8_SIGMA8_Msk (0x3fffu << HSMC_SIGMA8_SIGMA8_Pos) /**< \brief (HSMC_SIGMA8) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA8_SIGMA8(value) ((HSMC_SIGMA8_SIGMA8_Msk & ((value) << HSMC_SIGMA8_SIGMA8_Pos)))\r
+/* -------- HSMC_SIGMA9 : (SMC Offset: 0x54C) PMECC Error Location SIGMA 9 Register -------- */\r
+#define HSMC_SIGMA9_SIGMA9_Pos 0\r
+#define HSMC_SIGMA9_SIGMA9_Msk (0x3fffu << HSMC_SIGMA9_SIGMA9_Pos) /**< \brief (HSMC_SIGMA9) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA9_SIGMA9(value) ((HSMC_SIGMA9_SIGMA9_Msk & ((value) << HSMC_SIGMA9_SIGMA9_Pos)))\r
+/* -------- HSMC_SIGMA10 : (SMC Offset: 0x550) PMECC Error Location SIGMA 10 Register -------- */\r
+#define HSMC_SIGMA10_SIGMA10_Pos 0\r
+#define HSMC_SIGMA10_SIGMA10_Msk (0x3fffu << HSMC_SIGMA10_SIGMA10_Pos) /**< \brief (HSMC_SIGMA10) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA10_SIGMA10(value) ((HSMC_SIGMA10_SIGMA10_Msk & ((value) << HSMC_SIGMA10_SIGMA10_Pos)))\r
+/* -------- HSMC_SIGMA11 : (SMC Offset: 0x554) PMECC Error Location SIGMA 11 Register -------- */\r
+#define HSMC_SIGMA11_SIGMA11_Pos 0\r
+#define HSMC_SIGMA11_SIGMA11_Msk (0x3fffu << HSMC_SIGMA11_SIGMA11_Pos) /**< \brief (HSMC_SIGMA11) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA11_SIGMA11(value) ((HSMC_SIGMA11_SIGMA11_Msk & ((value) << HSMC_SIGMA11_SIGMA11_Pos)))\r
+/* -------- HSMC_SIGMA12 : (SMC Offset: 0x558) PMECC Error Location SIGMA 12 Register -------- */\r
+#define HSMC_SIGMA12_SIGMA12_Pos 0\r
+#define HSMC_SIGMA12_SIGMA12_Msk (0x3fffu << HSMC_SIGMA12_SIGMA12_Pos) /**< \brief (HSMC_SIGMA12) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA12_SIGMA12(value) ((HSMC_SIGMA12_SIGMA12_Msk & ((value) << HSMC_SIGMA12_SIGMA12_Pos)))\r
+/* -------- HSMC_SIGMA13 : (SMC Offset: 0x55C) PMECC Error Location SIGMA 13 Register -------- */\r
+#define HSMC_SIGMA13_SIGMA13_Pos 0\r
+#define HSMC_SIGMA13_SIGMA13_Msk (0x3fffu << HSMC_SIGMA13_SIGMA13_Pos) /**< \brief (HSMC_SIGMA13) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA13_SIGMA13(value) ((HSMC_SIGMA13_SIGMA13_Msk & ((value) << HSMC_SIGMA13_SIGMA13_Pos)))\r
+/* -------- HSMC_SIGMA14 : (SMC Offset: 0x560) PMECC Error Location SIGMA 14 Register -------- */\r
+#define HSMC_SIGMA14_SIGMA14_Pos 0\r
+#define HSMC_SIGMA14_SIGMA14_Msk (0x3fffu << HSMC_SIGMA14_SIGMA14_Pos) /**< \brief (HSMC_SIGMA14) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA14_SIGMA14(value) ((HSMC_SIGMA14_SIGMA14_Msk & ((value) << HSMC_SIGMA14_SIGMA14_Pos)))\r
+/* -------- HSMC_SIGMA15 : (SMC Offset: 0x564) PMECC Error Location SIGMA 15 Register -------- */\r
+#define HSMC_SIGMA15_SIGMA15_Pos 0\r
+#define HSMC_SIGMA15_SIGMA15_Msk (0x3fffu << HSMC_SIGMA15_SIGMA15_Pos) /**< \brief (HSMC_SIGMA15) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA15_SIGMA15(value) ((HSMC_SIGMA15_SIGMA15_Msk & ((value) << HSMC_SIGMA15_SIGMA15_Pos)))\r
+/* -------- HSMC_SIGMA16 : (SMC Offset: 0x568) PMECC Error Location SIGMA 16 Register -------- */\r
+#define HSMC_SIGMA16_SIGMA16_Pos 0\r
+#define HSMC_SIGMA16_SIGMA16_Msk (0x3fffu << HSMC_SIGMA16_SIGMA16_Pos) /**< \brief (HSMC_SIGMA16) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA16_SIGMA16(value) ((HSMC_SIGMA16_SIGMA16_Msk & ((value) << HSMC_SIGMA16_SIGMA16_Pos)))\r
+/* -------- HSMC_SIGMA17 : (SMC Offset: 0x56C) PMECC Error Location SIGMA 17 Register -------- */\r
+#define HSMC_SIGMA17_SIGMA17_Pos 0\r
+#define HSMC_SIGMA17_SIGMA17_Msk (0x3fffu << HSMC_SIGMA17_SIGMA17_Pos) /**< \brief (HSMC_SIGMA17) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA17_SIGMA17(value) ((HSMC_SIGMA17_SIGMA17_Msk & ((value) << HSMC_SIGMA17_SIGMA17_Pos)))\r
+/* -------- HSMC_SIGMA18 : (SMC Offset: 0x570) PMECC Error Location SIGMA 18 Register -------- */\r
+#define HSMC_SIGMA18_SIGMA18_Pos 0\r
+#define HSMC_SIGMA18_SIGMA18_Msk (0x3fffu << HSMC_SIGMA18_SIGMA18_Pos) /**< \brief (HSMC_SIGMA18) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA18_SIGMA18(value) ((HSMC_SIGMA18_SIGMA18_Msk & ((value) << HSMC_SIGMA18_SIGMA18_Pos)))\r
+/* -------- HSMC_SIGMA19 : (SMC Offset: 0x574) PMECC Error Location SIGMA 19 Register -------- */\r
+#define HSMC_SIGMA19_SIGMA19_Pos 0\r
+#define HSMC_SIGMA19_SIGMA19_Msk (0x3fffu << HSMC_SIGMA19_SIGMA19_Pos) /**< \brief (HSMC_SIGMA19) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA19_SIGMA19(value) ((HSMC_SIGMA19_SIGMA19_Msk & ((value) << HSMC_SIGMA19_SIGMA19_Pos)))\r
+/* -------- HSMC_SIGMA20 : (SMC Offset: 0x578) PMECC Error Location SIGMA 20 Register -------- */\r
+#define HSMC_SIGMA20_SIGMA20_Pos 0\r
+#define HSMC_SIGMA20_SIGMA20_Msk (0x3fffu << HSMC_SIGMA20_SIGMA20_Pos) /**< \brief (HSMC_SIGMA20) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA20_SIGMA20(value) ((HSMC_SIGMA20_SIGMA20_Msk & ((value) << HSMC_SIGMA20_SIGMA20_Pos)))\r
+/* -------- HSMC_SIGMA21 : (SMC Offset: 0x57C) PMECC Error Location SIGMA 21 Register -------- */\r
+#define HSMC_SIGMA21_SIGMA21_Pos 0\r
+#define HSMC_SIGMA21_SIGMA21_Msk (0x3fffu << HSMC_SIGMA21_SIGMA21_Pos) /**< \brief (HSMC_SIGMA21) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA21_SIGMA21(value) ((HSMC_SIGMA21_SIGMA21_Msk & ((value) << HSMC_SIGMA21_SIGMA21_Pos)))\r
+/* -------- HSMC_SIGMA22 : (SMC Offset: 0x580) PMECC Error Location SIGMA 22 Register -------- */\r
+#define HSMC_SIGMA22_SIGMA22_Pos 0\r
+#define HSMC_SIGMA22_SIGMA22_Msk (0x3fffu << HSMC_SIGMA22_SIGMA22_Pos) /**< \brief (HSMC_SIGMA22) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA22_SIGMA22(value) ((HSMC_SIGMA22_SIGMA22_Msk & ((value) << HSMC_SIGMA22_SIGMA22_Pos)))\r
+/* -------- HSMC_SIGMA23 : (SMC Offset: 0x584) PMECC Error Location SIGMA 23 Register -------- */\r
+#define HSMC_SIGMA23_SIGMA23_Pos 0\r
+#define HSMC_SIGMA23_SIGMA23_Msk (0x3fffu << HSMC_SIGMA23_SIGMA23_Pos) /**< \brief (HSMC_SIGMA23) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA23_SIGMA23(value) ((HSMC_SIGMA23_SIGMA23_Msk & ((value) << HSMC_SIGMA23_SIGMA23_Pos)))\r
+/* -------- HSMC_SIGMA24 : (SMC Offset: 0x588) PMECC Error Location SIGMA 24 Register -------- */\r
+#define HSMC_SIGMA24_SIGMA24_Pos 0\r
+#define HSMC_SIGMA24_SIGMA24_Msk (0x3fffu << HSMC_SIGMA24_SIGMA24_Pos) /**< \brief (HSMC_SIGMA24) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA24_SIGMA24(value) ((HSMC_SIGMA24_SIGMA24_Msk & ((value) << HSMC_SIGMA24_SIGMA24_Pos)))\r
+/* -------- HSMC_SIGMA25 : (SMC Offset: 0x58C) PMECC Error Location SIGMA 25 Register -------- */\r
+#define HSMC_SIGMA25_SIGMA25_Pos 0\r
+#define HSMC_SIGMA25_SIGMA25_Msk (0x3fffu << HSMC_SIGMA25_SIGMA25_Pos) /**< \brief (HSMC_SIGMA25) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA25_SIGMA25(value) ((HSMC_SIGMA25_SIGMA25_Msk & ((value) << HSMC_SIGMA25_SIGMA25_Pos)))\r
+/* -------- HSMC_SIGMA26 : (SMC Offset: 0x590) PMECC Error Location SIGMA 26 Register -------- */\r
+#define HSMC_SIGMA26_SIGMA26_Pos 0\r
+#define HSMC_SIGMA26_SIGMA26_Msk (0x3fffu << HSMC_SIGMA26_SIGMA26_Pos) /**< \brief (HSMC_SIGMA26) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA26_SIGMA26(value) ((HSMC_SIGMA26_SIGMA26_Msk & ((value) << HSMC_SIGMA26_SIGMA26_Pos)))\r
+/* -------- HSMC_SIGMA27 : (SMC Offset: 0x594) PMECC Error Location SIGMA 27 Register -------- */\r
+#define HSMC_SIGMA27_SIGMA27_Pos 0\r
+#define HSMC_SIGMA27_SIGMA27_Msk (0x3fffu << HSMC_SIGMA27_SIGMA27_Pos) /**< \brief (HSMC_SIGMA27) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA27_SIGMA27(value) ((HSMC_SIGMA27_SIGMA27_Msk & ((value) << HSMC_SIGMA27_SIGMA27_Pos)))\r
+/* -------- HSMC_SIGMA28 : (SMC Offset: 0x598) PMECC Error Location SIGMA 28 Register -------- */\r
+#define HSMC_SIGMA28_SIGMA28_Pos 0\r
+#define HSMC_SIGMA28_SIGMA28_Msk (0x3fffu << HSMC_SIGMA28_SIGMA28_Pos) /**< \brief (HSMC_SIGMA28) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA28_SIGMA28(value) ((HSMC_SIGMA28_SIGMA28_Msk & ((value) << HSMC_SIGMA28_SIGMA28_Pos)))\r
+/* -------- HSMC_SIGMA29 : (SMC Offset: 0x59C) PMECC Error Location SIGMA 29 Register -------- */\r
+#define HSMC_SIGMA29_SIGMA29_Pos 0\r
+#define HSMC_SIGMA29_SIGMA29_Msk (0x3fffu << HSMC_SIGMA29_SIGMA29_Pos) /**< \brief (HSMC_SIGMA29) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA29_SIGMA29(value) ((HSMC_SIGMA29_SIGMA29_Msk & ((value) << HSMC_SIGMA29_SIGMA29_Pos)))\r
+/* -------- HSMC_SIGMA30 : (SMC Offset: 0x5A0) PMECC Error Location SIGMA 30 Register -------- */\r
+#define HSMC_SIGMA30_SIGMA30_Pos 0\r
+#define HSMC_SIGMA30_SIGMA30_Msk (0x3fffu << HSMC_SIGMA30_SIGMA30_Pos) /**< \brief (HSMC_SIGMA30) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA30_SIGMA30(value) ((HSMC_SIGMA30_SIGMA30_Msk & ((value) << HSMC_SIGMA30_SIGMA30_Pos)))\r
+/* -------- HSMC_SIGMA31 : (SMC Offset: 0x5A4) PMECC Error Location SIGMA 31 Register -------- */\r
+#define HSMC_SIGMA31_SIGMA31_Pos 0\r
+#define HSMC_SIGMA31_SIGMA31_Msk (0x3fffu << HSMC_SIGMA31_SIGMA31_Pos) /**< \brief (HSMC_SIGMA31) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA31_SIGMA31(value) ((HSMC_SIGMA31_SIGMA31_Msk & ((value) << HSMC_SIGMA31_SIGMA31_Pos)))\r
+/* -------- HSMC_SIGMA32 : (SMC Offset: 0x5A8) PMECC Error Location SIGMA 32 Register -------- */\r
+#define HSMC_SIGMA32_SIGMA32_Pos 0\r
+#define HSMC_SIGMA32_SIGMA32_Msk (0x3fffu << HSMC_SIGMA32_SIGMA32_Pos) /**< \brief (HSMC_SIGMA32) Coefficient of degree x in the SIGMA polynomial */\r
+#define HSMC_SIGMA32_SIGMA32(value) ((HSMC_SIGMA32_SIGMA32_Msk & ((value) << HSMC_SIGMA32_SIGMA32_Pos)))\r
+/* -------- HSMC_ERRLOC0 : (SMC Offset: 0x5AC) PMECC Error Location 0 Register -------- */\r
+#define HSMC_ERRLOC0_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC0_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC0_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC0) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC1 : (SMC Offset: 0x5B0) PMECC Error Location 1 Register -------- */\r
+#define HSMC_ERRLOC1_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC1_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC1_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC1) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC2 : (SMC Offset: 0x5B4) PMECC Error Location 2 Register -------- */\r
+#define HSMC_ERRLOC2_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC2_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC2_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC2) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC3 : (SMC Offset: 0x5B8) PMECC Error Location 3 Register -------- */\r
+#define HSMC_ERRLOC3_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC3_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC3_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC3) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC4 : (SMC Offset: 0x5BC) PMECC Error Location 4 Register -------- */\r
+#define HSMC_ERRLOC4_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC4_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC4_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC4) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC5 : (SMC Offset: 0x5C0) PMECC Error Location 5 Register -------- */\r
+#define HSMC_ERRLOC5_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC5_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC5_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC5) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC6 : (SMC Offset: 0x5C4) PMECC Error Location 6 Register -------- */\r
+#define HSMC_ERRLOC6_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC6_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC6_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC6) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC7 : (SMC Offset: 0x5C8) PMECC Error Location 7 Register -------- */\r
+#define HSMC_ERRLOC7_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC7_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC7_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC7) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC8 : (SMC Offset: 0x5CC) PMECC Error Location 8 Register -------- */\r
+#define HSMC_ERRLOC8_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC8_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC8_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC8) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC9 : (SMC Offset: 0x5D0) PMECC Error Location 9 Register -------- */\r
+#define HSMC_ERRLOC9_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC9_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC9_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC9) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC10 : (SMC Offset: 0x5D4) PMECC Error Location 10 Register -------- */\r
+#define HSMC_ERRLOC10_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC10_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC10_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC10) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC11 : (SMC Offset: 0x5D8) PMECC Error Location 11 Register -------- */\r
+#define HSMC_ERRLOC11_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC11_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC11_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC11) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC12 : (SMC Offset: 0x5DC) PMECC Error Location 12 Register -------- */\r
+#define HSMC_ERRLOC12_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC12_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC12_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC12) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC13 : (SMC Offset: 0x5E0) PMECC Error Location 13 Register -------- */\r
+#define HSMC_ERRLOC13_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC13_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC13_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC13) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC14 : (SMC Offset: 0x5E4) PMECC Error Location 14 Register -------- */\r
+#define HSMC_ERRLOC14_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC14_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC14_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC14) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC15 : (SMC Offset: 0x5E8) PMECC Error Location 15 Register -------- */\r
+#define HSMC_ERRLOC15_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC15_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC15_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC15) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC16 : (SMC Offset: 0x5EC) PMECC Error Location 16 Register -------- */\r
+#define HSMC_ERRLOC16_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC16_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC16_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC16) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC17 : (SMC Offset: 0x5F0) PMECC Error Location 17 Register -------- */\r
+#define HSMC_ERRLOC17_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC17_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC17_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC17) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC18 : (SMC Offset: 0x5F4) PMECC Error Location 18 Register -------- */\r
+#define HSMC_ERRLOC18_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC18_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC18_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC18) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC19 : (SMC Offset: 0x5F8) PMECC Error Location 19 Register -------- */\r
+#define HSMC_ERRLOC19_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC19_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC19_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC19) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC20 : (SMC Offset: 0x5FC) PMECC Error Location 20 Register -------- */\r
+#define HSMC_ERRLOC20_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC20_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC20_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC20) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC21 : (SMC Offset: 0x600) PMECC Error Location 21 Register -------- */\r
+#define HSMC_ERRLOC21_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC21_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC21_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC21) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC22 : (SMC Offset: 0x604) PMECC Error Location 22 Register -------- */\r
+#define HSMC_ERRLOC22_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC22_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC22_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC22) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_ERRLOC23 : (SMC Offset: 0x608) PMECC Error Location 23 Register -------- */\r
+#define HSMC_ERRLOC23_ERRLOCN_Pos 0\r
+#define HSMC_ERRLOC23_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC23_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC23) Error Position within the Set {sector area, spare area} */\r
+/* -------- HSMC_SETUP : (SMC Offset: N/A) HSMC Setup Register -------- */\r
+#define HSMC_SETUP_NWE_SETUP_Pos 0\r
+#define HSMC_SETUP_NWE_SETUP_Msk (0x3fu << HSMC_SETUP_NWE_SETUP_Pos) /**< \brief (HSMC_SETUP) NWE Setup Length */\r
+#define HSMC_SETUP_NWE_SETUP(value) ((HSMC_SETUP_NWE_SETUP_Msk & ((value) << HSMC_SETUP_NWE_SETUP_Pos)))\r
+#define HSMC_SETUP_NCS_WR_SETUP_Pos 8\r
+#define HSMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << HSMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (HSMC_SETUP) NCS Setup Length in Write Access */\r
+#define HSMC_SETUP_NCS_WR_SETUP(value) ((HSMC_SETUP_NCS_WR_SETUP_Msk & ((value) << HSMC_SETUP_NCS_WR_SETUP_Pos)))\r
+#define HSMC_SETUP_NRD_SETUP_Pos 16\r
+#define HSMC_SETUP_NRD_SETUP_Msk (0x3fu << HSMC_SETUP_NRD_SETUP_Pos) /**< \brief (HSMC_SETUP) NRD Setup Length */\r
+#define HSMC_SETUP_NRD_SETUP(value) ((HSMC_SETUP_NRD_SETUP_Msk & ((value) << HSMC_SETUP_NRD_SETUP_Pos)))\r
+#define HSMC_SETUP_NCS_RD_SETUP_Pos 24\r
+#define HSMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << HSMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (HSMC_SETUP) NCS Setup Length in Read Access */\r
+#define HSMC_SETUP_NCS_RD_SETUP(value) ((HSMC_SETUP_NCS_RD_SETUP_Msk & ((value) << HSMC_SETUP_NCS_RD_SETUP_Pos)))\r
+/* -------- HSMC_PULSE : (SMC Offset: N/A) HSMC Pulse Register -------- */\r
+#define HSMC_PULSE_NWE_PULSE_Pos 0\r
+#define HSMC_PULSE_NWE_PULSE_Msk (0x7fu << HSMC_PULSE_NWE_PULSE_Pos) /**< \brief (HSMC_PULSE) NWE Pulse Length */\r
+#define HSMC_PULSE_NWE_PULSE(value) ((HSMC_PULSE_NWE_PULSE_Msk & ((value) << HSMC_PULSE_NWE_PULSE_Pos)))\r
+#define HSMC_PULSE_NCS_WR_PULSE_Pos 8\r
+#define HSMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << HSMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (HSMC_PULSE) NCS Pulse Length in WRITE Access */\r
+#define HSMC_PULSE_NCS_WR_PULSE(value) ((HSMC_PULSE_NCS_WR_PULSE_Msk & ((value) << HSMC_PULSE_NCS_WR_PULSE_Pos)))\r
+#define HSMC_PULSE_NRD_PULSE_Pos 16\r
+#define HSMC_PULSE_NRD_PULSE_Msk (0x7fu << HSMC_PULSE_NRD_PULSE_Pos) /**< \brief (HSMC_PULSE) NRD Pulse Length */\r
+#define HSMC_PULSE_NRD_PULSE(value) ((HSMC_PULSE_NRD_PULSE_Msk & ((value) << HSMC_PULSE_NRD_PULSE_Pos)))\r
+#define HSMC_PULSE_NCS_RD_PULSE_Pos 24\r
+#define HSMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << HSMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (HSMC_PULSE) NCS Pulse Length in READ Access */\r
+#define HSMC_PULSE_NCS_RD_PULSE(value) ((HSMC_PULSE_NCS_RD_PULSE_Msk & ((value) << HSMC_PULSE_NCS_RD_PULSE_Pos)))\r
+/* -------- HSMC_CYCLE : (SMC Offset: N/A) HSMC Cycle Register -------- */\r
+#define HSMC_CYCLE_NWE_CYCLE_Pos 0\r
+#define HSMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << HSMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (HSMC_CYCLE) Total Write Cycle Length */\r
+#define HSMC_CYCLE_NWE_CYCLE(value) ((HSMC_CYCLE_NWE_CYCLE_Msk & ((value) << HSMC_CYCLE_NWE_CYCLE_Pos)))\r
+#define HSMC_CYCLE_NRD_CYCLE_Pos 16\r
+#define HSMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << HSMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (HSMC_CYCLE) Total Read Cycle Length */\r
+#define HSMC_CYCLE_NRD_CYCLE(value) ((HSMC_CYCLE_NRD_CYCLE_Msk & ((value) << HSMC_CYCLE_NRD_CYCLE_Pos)))\r
+/* -------- HSMC_TIMINGS : (SMC Offset: N/A) HSMC Timings Register -------- */\r
+#define HSMC_TIMINGS_TCLR_Pos 0\r
+#define HSMC_TIMINGS_TCLR_Msk (0xfu << HSMC_TIMINGS_TCLR_Pos) /**< \brief (HSMC_TIMINGS) CLE to REN Low Delay */\r
+#define HSMC_TIMINGS_TCLR(value) ((HSMC_TIMINGS_TCLR_Msk & ((value) << HSMC_TIMINGS_TCLR_Pos)))\r
+#define HSMC_TIMINGS_TADL_Pos 4\r
+#define HSMC_TIMINGS_TADL_Msk (0xfu << HSMC_TIMINGS_TADL_Pos) /**< \brief (HSMC_TIMINGS) ALE to Data Start */\r
+#define HSMC_TIMINGS_TADL(value) ((HSMC_TIMINGS_TADL_Msk & ((value) << HSMC_TIMINGS_TADL_Pos)))\r
+#define HSMC_TIMINGS_TAR_Pos 8\r
+#define HSMC_TIMINGS_TAR_Msk (0xfu << HSMC_TIMINGS_TAR_Pos) /**< \brief (HSMC_TIMINGS) ALE to REN Low Delay */\r
+#define HSMC_TIMINGS_TAR(value) ((HSMC_TIMINGS_TAR_Msk & ((value) << HSMC_TIMINGS_TAR_Pos)))\r
+#define HSMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (HSMC_TIMINGS) Off Chip Memory Scrambling Enable */\r
+#define HSMC_TIMINGS_TRR_Pos 16\r
+#define HSMC_TIMINGS_TRR_Msk (0xfu << HSMC_TIMINGS_TRR_Pos) /**< \brief (HSMC_TIMINGS) Ready to REN Low Delay */\r
+#define HSMC_TIMINGS_TRR(value) ((HSMC_TIMINGS_TRR_Msk & ((value) << HSMC_TIMINGS_TRR_Pos)))\r
+#define HSMC_TIMINGS_TWB_Pos 24\r
+#define HSMC_TIMINGS_TWB_Msk (0xfu << HSMC_TIMINGS_TWB_Pos) /**< \brief (HSMC_TIMINGS) WEN High to REN to Busy */\r
+#define HSMC_TIMINGS_TWB(value) ((HSMC_TIMINGS_TWB_Msk & ((value) << HSMC_TIMINGS_TWB_Pos)))\r
+#define HSMC_TIMINGS_RBNSEL_Pos 28\r
+#define HSMC_TIMINGS_RBNSEL_Msk (0x7u << HSMC_TIMINGS_RBNSEL_Pos) /**< \brief (HSMC_TIMINGS) Ready/Busy Line Selection */\r
+#define HSMC_TIMINGS_RBNSEL(value) ((HSMC_TIMINGS_RBNSEL_Msk & ((value) << HSMC_TIMINGS_RBNSEL_Pos)))\r
+#define HSMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (HSMC_TIMINGS) NAND Flash Selection */\r
+/* -------- HSMC_MODE : (SMC Offset: N/A) HSMC Mode Register -------- */\r
+#define HSMC_MODE_READ_MODE (0x1u << 0) /**< \brief (HSMC_MODE) Selection of the Control Signal for Read Operation */\r
+#define HSMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (HSMC_MODE) The Read operation is controlled by the NCS signal. */\r
+#define HSMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (HSMC_MODE) The Read operation is controlled by the NRD signal. */\r
+#define HSMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (HSMC_MODE) Selection of the Control Signal for Write Operation */\r
+#define HSMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (HSMC_MODE) The Write operation is controller by the NCS signal. */\r
+#define HSMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (HSMC_MODE) The Write operation is controlled by the NWE signal */\r
+#define HSMC_MODE_EXNW_MODE_Pos 4\r
+#define HSMC_MODE_EXNW_MODE_Msk (0x3u << HSMC_MODE_EXNW_MODE_Pos) /**< \brief (HSMC_MODE) NWAIT Mode */\r
+#define HSMC_MODE_EXNW_MODE(value) ((HSMC_MODE_EXNW_MODE_Msk & ((value) << HSMC_MODE_EXNW_MODE_Pos)))\r
+#define HSMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (HSMC_MODE) Disabled-The NWAIT input signal is ignored on the corresponding Chip Select. */\r
+#define HSMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (HSMC_MODE) Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. */\r
+#define HSMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (HSMC_MODE) Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. */\r
+#define HSMC_MODE_BAT (0x1u << 8) /**< \brief (HSMC_MODE) Byte Access Type */\r
+#define HSMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (HSMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */\r
+#define HSMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (HSMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */\r
+#define HSMC_MODE_DBW (0x1u << 12) /**< \brief (HSMC_MODE) Data Bus Width */\r
+#define HSMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (HSMC_MODE) 8-bit bus */\r
+#define HSMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (HSMC_MODE) 16-bit bus */\r
+#define HSMC_MODE_TDF_CYCLES_Pos 16\r
+#define HSMC_MODE_TDF_CYCLES_Msk (0xfu << HSMC_MODE_TDF_CYCLES_Pos) /**< \brief (HSMC_MODE) Data Float Time */\r
+#define HSMC_MODE_TDF_CYCLES(value) ((HSMC_MODE_TDF_CYCLES_Msk & ((value) << HSMC_MODE_TDF_CYCLES_Pos)))\r
+#define HSMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (HSMC_MODE) TDF Optimization */\r
+/* -------- HSMC_OCMS : (SMC Offset: 0x7A0) HSMC Off Chip Memory Scrambling Register -------- */\r
+#define HSMC_OCMS_SMSE (0x1u << 0) /**< \brief (HSMC_OCMS) Static Memory Controller Scrambling Enable */\r
+#define HSMC_OCMS_SRSE (0x1u << 1) /**< \brief (HSMC_OCMS) NFC Internal SRAM Scrambling Enable */\r
+/* -------- HSMC_KEY1 : (SMC Offset: 0x7A4) HSMC Off Chip Memory Scrambling KEY1 Register -------- */\r
+#define HSMC_KEY1_KEY1_Pos 0\r
+#define HSMC_KEY1_KEY1_Msk (0xffffffffu << HSMC_KEY1_KEY1_Pos) /**< \brief (HSMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */\r
+#define HSMC_KEY1_KEY1(value) ((HSMC_KEY1_KEY1_Msk & ((value) << HSMC_KEY1_KEY1_Pos)))\r
+/* -------- HSMC_KEY2 : (SMC Offset: 0x7A8) HSMC Off Chip Memory Scrambling KEY2 Register -------- */\r
+#define HSMC_KEY2_KEY2_Pos 0\r
+#define HSMC_KEY2_KEY2_Msk (0xffffffffu << HSMC_KEY2_KEY2_Pos) /**< \brief (HSMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */\r
+#define HSMC_KEY2_KEY2(value) ((HSMC_KEY2_KEY2_Msk & ((value) << HSMC_KEY2_KEY2_Pos)))\r
+/* -------- HSMC_WPMR : (SMC Offset: 0x7E4) HSMC Write Protection Mode Register -------- */\r
+#define HSMC_WPMR_WPEN (0x1u << 0) /**< \brief (HSMC_WPMR) Write Protection Enable */\r
+#define HSMC_WPMR_WPKEY_Pos 8\r
+#define HSMC_WPMR_WPKEY_Msk (0xffffffu << HSMC_WPMR_WPKEY_Pos) /**< \brief (HSMC_WPMR) Write Protection Key */\r
+#define HSMC_WPMR_WPKEY(value) ((HSMC_WPMR_WPKEY_Msk & ((value) << HSMC_WPMR_WPKEY_Pos)))\r
+#define HSMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (HSMC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */\r
+/* -------- HSMC_WPSR : (SMC Offset: 0x7E8) HSMC Write Protection Status Register -------- */\r
+#define HSMC_WPSR_WPVS (0x1u << 0) /**< \brief (HSMC_WPSR) Write Protection Violation Status */\r
+#define HSMC_WPSR_WPVSRC_Pos 8\r
+#define HSMC_WPSR_WPVSRC_Msk (0xffffu << HSMC_WPSR_WPVSRC_Pos) /**< \brief (HSMC_WPSR) Write Protection Violation Source */\r
+/* -------- HSMC_VERSION : (SMC Offset: 0x7FC) HSMC Version Register -------- */\r
+#define HSMC_VERSION_VERSION_Pos 0\r
+#define HSMC_VERSION_VERSION_Msk (0xfffu << HSMC_VERSION_VERSION_Pos) /**< \brief (HSMC_VERSION) Hardware Version Number */\r
+#define HSMC_VERSION_MFN_Pos 16\r
+#define HSMC_VERSION_MFN_Msk (0x7u << HSMC_VERSION_MFN_Pos) /**< \brief (HSMC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_SMC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SPI_COMPONENT_\r
+#define _SAMA5D2_SPI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SPI Serial Peripheral Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Spi hardware registers */\r
+typedef struct {\r
+ __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */\r
+ __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */\r
+ __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */\r
+ __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */\r
+ __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */\r
+ __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */\r
+ __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */\r
+ __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */\r
+ __I uint32_t Reserved1[4];\r
+ __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */\r
+ __IO uint32_t SPI_FMR; /**< \brief (Spi Offset: 0x40) FIFO Mode Register */\r
+ __I uint32_t SPI_FLR; /**< \brief (Spi Offset: 0x44) FIFO Level Register */\r
+ __I uint32_t SPI_CMPR; /**< \brief (Spi Offset: 0x48) Comparison Register */\r
+ __I uint32_t Reserved2[38];\r
+ __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved3[4];\r
+ __I uint32_t SPI_VERSION; /**< \brief (Spi Offset: 0xFC) Version Register */\r
+} Spi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */\r
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */\r
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */\r
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */\r
+#define SPI_CR_REQCLR (0x1u << 12) /**< \brief (SPI_CR) Request to Clear the Comparison Trigger */\r
+#define SPI_CR_TXFCLR (0x1u << 16) /**< \brief (SPI_CR) Transmit FIFO Clear */\r
+#define SPI_CR_RXFCLR (0x1u << 17) /**< \brief (SPI_CR) Receive FIFO Clear */\r
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */\r
+#define SPI_CR_FIFOEN (0x1u << 30) /**< \brief (SPI_CR) FIFO Enable */\r
+#define SPI_CR_FIFODIS (0x1u << 31) /**< \brief (SPI_CR) FIFO Disable */\r
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */\r
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */\r
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */\r
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */\r
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */\r
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */\r
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */\r
+#define SPI_MR_CMPMODE (0x1u << 12) /**< \brief (SPI_MR) Comparison Mode */\r
+#define SPI_MR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (SPI_MR) Any character is received and comparison function drives CMP flag. */\r
+#define SPI_MR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (SPI_MR) Comparison condition must be met to start reception of all incoming characters until REQCLR is set. */\r
+#define SPI_MR_PCS_Pos 16\r
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */\r
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))\r
+#define SPI_MR_DLYBCS_Pos 24\r
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */\r
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))\r
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */\r
+#define SPI_RDR_RD_Pos 0\r
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_PCS_Pos 16\r
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */\r
+#define SPI_RDR_RD0_Pos 0\r
+#define SPI_RDR_RD0_Msk (0xffu << SPI_RDR_RD0_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD1_Pos 8\r
+#define SPI_RDR_RD1_Msk (0xffu << SPI_RDR_RD1_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD2_Pos 16\r
+#define SPI_RDR_RD2_Msk (0xffu << SPI_RDR_RD2_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD3_Pos 24\r
+#define SPI_RDR_RD3_Msk (0xffu << SPI_RDR_RD3_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD0_FIFO_MULTI_DATA_16_Pos 0\r
+#define SPI_RDR_RD0_FIFO_MULTI_DATA_16_Msk (0xffffu << SPI_RDR_RD0_FIFO_MULTI_DATA_16_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_RD1_FIFO_MULTI_DATA_16_Pos 16\r
+#define SPI_RDR_RD1_FIFO_MULTI_DATA_16_Msk (0xffffu << SPI_RDR_RD1_FIFO_MULTI_DATA_16_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */\r
+#define SPI_TDR_TD_Pos 0\r
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))\r
+#define SPI_TDR_PCS_Pos 16\r
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */\r
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))\r
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */\r
+#define SPI_TDR_TD0_Pos 0\r
+#define SPI_TDR_TD0_Msk (0xffffu << SPI_TDR_TD0_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD0(value) ((SPI_TDR_TD0_Msk & ((value) << SPI_TDR_TD0_Pos)))\r
+#define SPI_TDR_TD1_Pos 16\r
+#define SPI_TDR_TD1_Msk (0xffffu << SPI_TDR_TD1_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD1(value) ((SPI_TDR_TD1_Msk & ((value) << SPI_TDR_TD1_Pos)))\r
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */\r
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */\r
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */\r
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */\r
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */\r
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */\r
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */\r
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */\r
+#define SPI_SR_CMP (0x1u << 11) /**< \brief (SPI_SR) Comparison Status (cleared on read) */\r
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */\r
+#define SPI_SR_TXFEF (0x1u << 24) /**< \brief (SPI_SR) Transmit FIFO Empty Flag (cleared on read) */\r
+#define SPI_SR_TXFFF (0x1u << 25) /**< \brief (SPI_SR) Transmit FIFO Full Flag (cleared on read) */\r
+#define SPI_SR_TXFTHF (0x1u << 26) /**< \brief (SPI_SR) Transmit FIFO Threshold Flag (cleared on read) */\r
+#define SPI_SR_RXFEF (0x1u << 27) /**< \brief (SPI_SR) Receive FIFO Empty Flag */\r
+#define SPI_SR_RXFFF (0x1u << 28) /**< \brief (SPI_SR) Receive FIFO Full Flag */\r
+#define SPI_SR_RXFTHF (0x1u << 29) /**< \brief (SPI_SR) Receive FIFO Threshold Flag */\r
+#define SPI_SR_TXFPTEF (0x1u << 30) /**< \brief (SPI_SR) Transmit FIFO Pointer Error Flag */\r
+#define SPI_SR_RXFPTEF (0x1u << 31) /**< \brief (SPI_SR) Receive FIFO Pointer Error Flag */\r
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */\r
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */\r
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */\r
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */\r
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */\r
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */\r
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */\r
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */\r
+#define SPI_IER_CMP (0x1u << 11) /**< \brief (SPI_IER) Comparison Interrupt Enable */\r
+#define SPI_IER_TXFEF (0x1u << 24) /**< \brief (SPI_IER) TXFEF Interrupt Enable */\r
+#define SPI_IER_TXFFF (0x1u << 25) /**< \brief (SPI_IER) TXFFF Interrupt Enable */\r
+#define SPI_IER_TXFTHF (0x1u << 26) /**< \brief (SPI_IER) TXFTHF Interrupt Enable */\r
+#define SPI_IER_RXFEF (0x1u << 27) /**< \brief (SPI_IER) RXFEF Interrupt Enable */\r
+#define SPI_IER_RXFFF (0x1u << 28) /**< \brief (SPI_IER) RXFFF Interrupt Enable */\r
+#define SPI_IER_RXFTHF (0x1u << 29) /**< \brief (SPI_IER) RXFTHF Interrupt Enable */\r
+#define SPI_IER_TXFPTEF (0x1u << 30) /**< \brief (SPI_IER) TXFPTEF Interrupt Enable */\r
+#define SPI_IER_RXFPTEF (0x1u << 31) /**< \brief (SPI_IER) RXFPTEF Interrupt Enable */\r
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */\r
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */\r
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */\r
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */\r
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */\r
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */\r
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */\r
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */\r
+#define SPI_IDR_CMP (0x1u << 11) /**< \brief (SPI_IDR) Comparison Interrupt Disable */\r
+#define SPI_IDR_TXFEF (0x1u << 24) /**< \brief (SPI_IDR) TXFEF Interrupt Disable */\r
+#define SPI_IDR_TXFFF (0x1u << 25) /**< \brief (SPI_IDR) TXFFF Interrupt Disable */\r
+#define SPI_IDR_TXFTHF (0x1u << 26) /**< \brief (SPI_IDR) TXFTHF Interrupt Disable */\r
+#define SPI_IDR_RXFEF (0x1u << 27) /**< \brief (SPI_IDR) RXFEF Interrupt Disable */\r
+#define SPI_IDR_RXFFF (0x1u << 28) /**< \brief (SPI_IDR) RXFFF Interrupt Disable */\r
+#define SPI_IDR_RXFTHF (0x1u << 29) /**< \brief (SPI_IDR) RXFTHF Interrupt Disable */\r
+#define SPI_IDR_TXFPTEF (0x1u << 30) /**< \brief (SPI_IDR) TXFPTEF Interrupt Disable */\r
+#define SPI_IDR_RXFPTEF (0x1u << 31) /**< \brief (SPI_IDR) RXFPTEF Interrupt Disable */\r
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */\r
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */\r
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */\r
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */\r
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */\r
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */\r
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */\r
+#define SPI_IMR_CMP (0x1u << 11) /**< \brief (SPI_IMR) Comparison Interrupt Mask */\r
+#define SPI_IMR_TXFEF (0x1u << 24) /**< \brief (SPI_IMR) TXFEF Interrupt Mask */\r
+#define SPI_IMR_TXFFF (0x1u << 25) /**< \brief (SPI_IMR) TXFFF Interrupt Mask */\r
+#define SPI_IMR_TXFTHF (0x1u << 26) /**< \brief (SPI_IMR) TXFTHF Interrupt Mask */\r
+#define SPI_IMR_RXFEF (0x1u << 27) /**< \brief (SPI_IMR) RXFEF Interrupt Mask */\r
+#define SPI_IMR_RXFFF (0x1u << 28) /**< \brief (SPI_IMR) RXFFF Interrupt Mask */\r
+#define SPI_IMR_RXFTHF (0x1u << 29) /**< \brief (SPI_IMR) RXFTHF Interrupt Mask */\r
+#define SPI_IMR_TXFPTEF (0x1u << 30) /**< \brief (SPI_IMR) TXFPTEF Interrupt Mask */\r
+#define SPI_IMR_RXFPTEF (0x1u << 31) /**< \brief (SPI_IMR) RXFPTEF Interrupt Mask */\r
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */\r
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */\r
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */\r
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */\r
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */\r
+#define SPI_CSR_BITS_Pos 4\r
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */\r
+#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)))\r
+#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */\r
+#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */\r
+#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */\r
+#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */\r
+#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */\r
+#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */\r
+#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */\r
+#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */\r
+#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */\r
+#define SPI_CSR_SCBR_Pos 8\r
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */\r
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))\r
+#define SPI_CSR_DLYBS_Pos 16\r
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */\r
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))\r
+#define SPI_CSR_DLYBCT_Pos 24\r
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */\r
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))\r
+/* -------- SPI_FMR : (SPI Offset: 0x40) FIFO Mode Register -------- */\r
+#define SPI_FMR_TXRDYM_Pos 0\r
+#define SPI_FMR_TXRDYM_Msk (0x3u << SPI_FMR_TXRDYM_Pos) /**< \brief (SPI_FMR) Transmitter Data Register Empty Mode */\r
+#define SPI_FMR_TXRDYM(value) ((SPI_FMR_TXRDYM_Msk & ((value) << SPI_FMR_TXRDYM_Pos)))\r
+#define SPI_FMR_TXRDYM_ONE_DATA (0x0u << 0) /**< \brief (SPI_FMR) TDRE will be at level '1' when at least one data can be written in the Transmit FIFO. */\r
+#define SPI_FMR_TXRDYM_TWO_DATA (0x1u << 0) /**< \brief (SPI_FMR) TDRE will be at level '1' when at least two data can be written in the Transmit FIFO. */\r
+#define SPI_FMR_TXRDYM_FOUR_DATA (0x2u << 0) /**< \brief (SPI_FMR) TDRE will be at level '1' when at least four data can be written in the Transmit FIFO. */\r
+#define SPI_FMR_RXRDYM_Pos 4\r
+#define SPI_FMR_RXRDYM_Msk (0x3u << SPI_FMR_RXRDYM_Pos) /**< \brief (SPI_FMR) Receiver Data Register Full Mode */\r
+#define SPI_FMR_RXRDYM(value) ((SPI_FMR_RXRDYM_Msk & ((value) << SPI_FMR_RXRDYM_Pos)))\r
+#define SPI_FMR_RXRDYM_ONE_DATA (0x0u << 4) /**< \brief (SPI_FMR) RDRF will be at level '1' when at least one unread data is in the Receive FIFO. */\r
+#define SPI_FMR_RXRDYM_TWO_DATA (0x1u << 4) /**< \brief (SPI_FMR) RDRF will be at level '1' when at least two unread data are in the Receive FIFO. */\r
+#define SPI_FMR_RXRDYM_FOUR_DATA (0x2u << 4) /**< \brief (SPI_FMR) RDRF will be at level '1' when at least four unread data are in the Receive FIFO. */\r
+#define SPI_FMR_TXFTHRES_Pos 16\r
+#define SPI_FMR_TXFTHRES_Msk (0x3fu << SPI_FMR_TXFTHRES_Pos) /**< \brief (SPI_FMR) Transmit FIFO Threshold */\r
+#define SPI_FMR_TXFTHRES(value) ((SPI_FMR_TXFTHRES_Msk & ((value) << SPI_FMR_TXFTHRES_Pos)))\r
+#define SPI_FMR_RXFTHRES_Pos 24\r
+#define SPI_FMR_RXFTHRES_Msk (0x3fu << SPI_FMR_RXFTHRES_Pos) /**< \brief (SPI_FMR) Receive FIFO Threshold */\r
+#define SPI_FMR_RXFTHRES(value) ((SPI_FMR_RXFTHRES_Msk & ((value) << SPI_FMR_RXFTHRES_Pos)))\r
+/* -------- SPI_FLR : (SPI Offset: 0x44) FIFO Level Register -------- */\r
+#define SPI_FLR_TXFL_Pos 0\r
+#define SPI_FLR_TXFL_Msk (0x3fu << SPI_FLR_TXFL_Pos) /**< \brief (SPI_FLR) Transmit FIFO Level */\r
+#define SPI_FLR_RXFL_Pos 16\r
+#define SPI_FLR_RXFL_Msk (0x3fu << SPI_FLR_RXFL_Pos) /**< \brief (SPI_FLR) Receive FIFO Level */\r
+/* -------- SPI_CMPR : (SPI Offset: 0x48) Comparison Register -------- */\r
+#define SPI_CMPR_VAL1_Pos 0\r
+#define SPI_CMPR_VAL1_Msk (0xffffu << SPI_CMPR_VAL1_Pos) /**< \brief (SPI_CMPR) First Comparison Value for Received Character */\r
+#define SPI_CMPR_VAL2_Pos 16\r
+#define SPI_CMPR_VAL2_Msk (0xffffu << SPI_CMPR_VAL2_Pos) /**< \brief (SPI_CMPR) Second Comparison Value for Received Character */\r
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */\r
+#define SPI_WPMR_WPKEY_Pos 8\r
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */\r
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))\r
+#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */\r
+#define SPI_WPSR_WPVSRC_Pos 8\r
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */\r
+/* -------- SPI_VERSION : (SPI Offset: 0xFC) Version Register -------- */\r
+#define SPI_VERSION_VERSION_Pos 0\r
+#define SPI_VERSION_VERSION_Msk (0xfffu << SPI_VERSION_VERSION_Pos) /**< \brief (SPI_VERSION) Version of the Hardware Module */\r
+#define SPI_VERSION_MFN_Pos 16\r
+#define SPI_VERSION_MFN_Msk (0x7u << SPI_VERSION_MFN_Pos) /**< \brief (SPI_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_SPI_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_SSC_COMPONENT_\r
+#define _SAMA5D2_SSC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_SSC Synchronous Serial Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Ssc hardware registers */\r
+typedef struct {\r
+ __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */\r
+ __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */\r
+ __I uint32_t Reserved1[2];\r
+ __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */\r
+ __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */\r
+ __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */\r
+ __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */\r
+ __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */\r
+ __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */\r
+ __I uint32_t Reserved2[2];\r
+ __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */\r
+ __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */\r
+ __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */\r
+ __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */\r
+ __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */\r
+ __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */\r
+ __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */\r
+ __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */\r
+ __I uint32_t Reserved3[37];\r
+ __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved4[4];\r
+ __I uint32_t SSC_VERSION; /**< \brief (Ssc Offset: 0xFC) Version Register */\r
+} Ssc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */\r
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */\r
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */\r
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */\r
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */\r
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */\r
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */\r
+#define SSC_CMR_DIV_Pos 0\r
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */\r
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))\r
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */\r
+#define SSC_RCMR_CKS_Pos 0\r
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */\r
+#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)))\r
+#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */\r
+#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */\r
+#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */\r
+#define SSC_RCMR_CKO_Pos 2\r
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */\r
+#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)))\r
+#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */\r
+#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */\r
+#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */\r
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */\r
+#define SSC_RCMR_CKG_Pos 6\r
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */\r
+#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)))\r
+#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */\r
+#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */\r
+#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */\r
+#define SSC_RCMR_START_Pos 8\r
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */\r
+#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)))\r
+#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */\r
+#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */\r
+#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */\r
+#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */\r
+#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */\r
+#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */\r
+#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */\r
+#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */\r
+#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */\r
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */\r
+#define SSC_RCMR_STTDLY_Pos 16\r
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */\r
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))\r
+#define SSC_RCMR_PERIOD_Pos 24\r
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */\r
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))\r
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */\r
+#define SSC_RFMR_DATLEN_Pos 0\r
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */\r
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))\r
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */\r
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */\r
+#define SSC_RFMR_DATNB_Pos 8\r
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */\r
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))\r
+#define SSC_RFMR_FSLEN_Pos 16\r
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */\r
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))\r
+#define SSC_RFMR_FSOS_Pos 20\r
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */\r
+#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)))\r
+#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */\r
+#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */\r
+#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */\r
+#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */\r
+#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */\r
+#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */\r
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */\r
+#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */\r
+#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */\r
+#define SSC_RFMR_FSLEN_EXT_Pos 28\r
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */\r
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))\r
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */\r
+#define SSC_TCMR_CKS_Pos 0\r
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */\r
+#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)))\r
+#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */\r
+#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */\r
+#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */\r
+#define SSC_TCMR_CKO_Pos 2\r
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */\r
+#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)))\r
+#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */\r
+#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */\r
+#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */\r
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */\r
+#define SSC_TCMR_CKG_Pos 6\r
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */\r
+#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)))\r
+#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */\r
+#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */\r
+#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */\r
+#define SSC_TCMR_START_Pos 8\r
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */\r
+#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)))\r
+#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */\r
+#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */\r
+#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */\r
+#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */\r
+#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */\r
+#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */\r
+#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */\r
+#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */\r
+#define SSC_TCMR_STTDLY_Pos 16\r
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */\r
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))\r
+#define SSC_TCMR_PERIOD_Pos 24\r
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */\r
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))\r
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */\r
+#define SSC_TFMR_DATLEN_Pos 0\r
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */\r
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))\r
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */\r
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */\r
+#define SSC_TFMR_DATNB_Pos 8\r
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */\r
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))\r
+#define SSC_TFMR_FSLEN_Pos 16\r
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */\r
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))\r
+#define SSC_TFMR_FSOS_Pos 20\r
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */\r
+#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)))\r
+#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */\r
+#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */\r
+#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */\r
+#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */\r
+#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */\r
+#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */\r
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */\r
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */\r
+#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */\r
+#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */\r
+#define SSC_TFMR_FSLEN_EXT_Pos 28\r
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */\r
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))\r
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */\r
+#define SSC_RHR_RDAT_Pos 0\r
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */\r
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */\r
+#define SSC_THR_TDAT_Pos 0\r
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */\r
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))\r
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */\r
+#define SSC_RSHR_RSDAT_Pos 0\r
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */\r
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */\r
+#define SSC_TSHR_TSDAT_Pos 0\r
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */\r
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))\r
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */\r
+#define SSC_RC0R_CP0_Pos 0\r
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */\r
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))\r
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */\r
+#define SSC_RC1R_CP1_Pos 0\r
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */\r
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))\r
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */\r
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */\r
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */\r
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */\r
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */\r
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */\r
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */\r
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */\r
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */\r
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */\r
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */\r
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */\r
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */\r
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */\r
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */\r
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */\r
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */\r
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */\r
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */\r
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */\r
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */\r
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */\r
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */\r
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */\r
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */\r
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */\r
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */\r
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */\r
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */\r
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */\r
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */\r
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */\r
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */\r
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */\r
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */\r
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */\r
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */\r
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */\r
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */\r
+#define SSC_WPMR_WPKEY_Pos 8\r
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */\r
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))\r
+#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */\r
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */\r
+#define SSC_WPSR_WPVSRC_Pos 8\r
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */\r
+/* -------- SSC_VERSION : (SSC Offset: 0xFC) Version Register -------- */\r
+#define SSC_VERSION_VERSION_Pos 0\r
+#define SSC_VERSION_VERSION_Msk (0xffffu << SSC_VERSION_VERSION_Pos) /**< \brief (SSC_VERSION) Version of the Hardware Module */\r
+#define SSC_VERSION_MFN_Pos 16\r
+#define SSC_VERSION_MFN_Msk (0x7u << SSC_VERSION_MFN_Pos) /**< \brief (SSC_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_SSC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_TC_COMPONENT_\r
+#define _SAMA5D2_TC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Timer Counter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_TC Timer Counter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief TcChannel hardware registers */\r
+typedef struct {\r
+ __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */\r
+ __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */\r
+ __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */\r
+ __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */\r
+ __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */\r
+ __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */\r
+ __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */\r
+ __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */\r
+ __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */\r
+ __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */\r
+ __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */\r
+ __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */\r
+ __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */\r
+ __I uint32_t Reserved1[3];\r
+} TcChannel;\r
+/** \brief Tc hardware registers */\r
+#define TCCHANNEL_NUMBER 3\r
+typedef struct {\r
+ TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */\r
+ __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */\r
+ __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */\r
+ __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */\r
+ __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */\r
+ __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */\r
+ __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */\r
+ __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */\r
+ __I uint32_t Reserved1[2];\r
+ __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t Reserved2[5];\r
+ __I uint32_t TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */\r
+} Tc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */\r
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */\r
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */\r
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */\r
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */\r
+#define TC_CMR_TCCLKS_Pos 0\r
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */\r
+#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)))\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal GCLK [TC_ID] clock signal (from PMC) */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal div8 clock signal (from PMC) */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal div32 clock signal (from PMC) */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal div128 clock signal (from PMC) */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal slow_clock clock signal (from PMC) */\r
+#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */\r
+#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */\r
+#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */\r
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */\r
+#define TC_CMR_BURST_Pos 4\r
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */\r
+#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)))\r
+#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */\r
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */\r
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */\r
+#define TC_CMR_ETRGEDG_Pos 8\r
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */\r
+#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)))\r
+#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */\r
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */\r
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */\r
+#define TC_CMR_LDRA_Pos 16\r
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */\r
+#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)))\r
+#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_LDRB_Pos 18\r
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */\r
+#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)))\r
+#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_SBSMPLR_Pos 20\r
+#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */\r
+#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)))\r
+#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */\r
+#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */\r
+#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */\r
+#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */\r
+#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */\r
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */\r
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */\r
+#define TC_CMR_EEVTEDG_Pos 8\r
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */\r
+#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos)))\r
+#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_EEVT_Pos 10\r
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */\r
+#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos)))\r
+#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */\r
+#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */\r
+#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */\r
+#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */\r
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */\r
+#define TC_CMR_WAVSEL_Pos 13\r
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */\r
+#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos)))\r
+#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */\r
+#define TC_CMR_ACPA_Pos 16\r
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */\r
+#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos)))\r
+#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ACPC_Pos 18\r
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */\r
+#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos)))\r
+#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_AEEVT_Pos 20\r
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */\r
+#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos)))\r
+#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ASWTRG_Pos 22\r
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */\r
+#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos)))\r
+#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPB_Pos 24\r
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */\r
+#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos)))\r
+#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPC_Pos 26\r
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */\r
+#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos)))\r
+#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BEEVT_Pos 28\r
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */\r
+#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos)))\r
+#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BSWTRG_Pos 30\r
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */\r
+#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos)))\r
+#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */\r
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */\r
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */\r
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */\r
+/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */\r
+#define TC_RAB_RAB_Pos 0\r
+#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */\r
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */\r
+#define TC_CV_CV_Pos 0\r
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */\r
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */\r
+#define TC_RA_RA_Pos 0\r
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */\r
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))\r
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */\r
+#define TC_RB_RB_Pos 0\r
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */\r
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))\r
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */\r
+#define TC_RC_RC_Pos 0\r
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */\r
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))\r
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */\r
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */\r
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */\r
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */\r
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */\r
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */\r
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */\r
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */\r
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */\r
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */\r
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */\r
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */\r
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */\r
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */\r
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */\r
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */\r
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */\r
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */\r
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */\r
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */\r
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */\r
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */\r
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */\r
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */\r
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */\r
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */\r
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */\r
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */\r
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */\r
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */\r
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */\r
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */\r
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */\r
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */\r
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */\r
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */\r
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */\r
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */\r
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */\r
+/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */\r
+#define TC_EMR_TRIGSRCA_Pos 0\r
+#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */\r
+#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)))\r
+#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */\r
+#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */\r
+#define TC_EMR_TRIGSRCB_Pos 4\r
+#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */\r
+#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)))\r
+#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */\r
+#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */\r
+#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */\r
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */\r
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */\r
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */\r
+#define TC_BMR_TC0XC0S_Pos 0\r
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */\r
+#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)))\r
+#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */\r
+#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */\r
+#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */\r
+#define TC_BMR_TC1XC1S_Pos 2\r
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */\r
+#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)))\r
+#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */\r
+#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */\r
+#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */\r
+#define TC_BMR_TC2XC2S_Pos 4\r
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */\r
+#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)))\r
+#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */\r
+#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */\r
+#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */\r
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */\r
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */\r
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */\r
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */\r
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */\r
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */\r
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */\r
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */\r
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */\r
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */\r
+#define TC_BMR_AUTOC (0x1u << 18) /**< \brief (TC_BMR) Auto-Correction of missing pulses */\r
+#define TC_BMR_AUTOC_DISABLED (0x0u << 18) /**< \brief (TC_BMR) The detection and auto-correction function is disabled. */\r
+#define TC_BMR_AUTOC_ENABLED (0x1u << 18) /**< \brief (TC_BMR) The detection and auto-correction function is enabled. */\r
+#define TC_BMR_MAXFILT_Pos 20\r
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */\r
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))\r
+#define TC_BMR_MAXCMP_Pos 26\r
+#define TC_BMR_MAXCMP_Msk (0xfu << TC_BMR_MAXCMP_Pos) /**< \brief (TC_BMR) Maximum Consecutive Missing Pulses */\r
+#define TC_BMR_MAXCMP(value) ((TC_BMR_MAXCMP_Msk & ((value) << TC_BMR_MAXCMP_Pos)))\r
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */\r
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */\r
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */\r
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */\r
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */\r
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */\r
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */\r
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */\r
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */\r
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */\r
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */\r
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */\r
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */\r
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */\r
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */\r
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */\r
+#define TC_QISR_MPE (0x1u << 3) /**< \brief (TC_QISR) Consecutive Missing Pulse Error */\r
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */\r
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */\r
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */\r
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */\r
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */\r
+#define TC_WPMR_WPKEY_Pos 8\r
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */\r
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))\r
+#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */\r
+/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */\r
+#define TC_VER_VERSION_Pos 0\r
+#define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos) /**< \brief (TC_VER) Version of the Hardware Module */\r
+#define TC_VER_MFN_Pos 16\r
+#define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos) /**< \brief (TC_VER) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_TC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_TDES_COMPONENT_\r
+#define _SAMA5D2_TDES_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_TDES Triple Data Encryption Standard */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Tdes hardware registers */\r
+typedef struct {\r
+ __O uint32_t TDES_CR; /**< \brief (Tdes Offset: 0x00) Control Register */\r
+ __IO uint32_t TDES_MR; /**< \brief (Tdes Offset: 0x04) Mode Register */\r
+ __I uint32_t Reserved1[2];\r
+ __O uint32_t TDES_IER; /**< \brief (Tdes Offset: 0x10) Interrupt Enable Register */\r
+ __O uint32_t TDES_IDR; /**< \brief (Tdes Offset: 0x14) Interrupt Disable Register */\r
+ __I uint32_t TDES_IMR; /**< \brief (Tdes Offset: 0x18) Interrupt Mask Register */\r
+ __I uint32_t TDES_ISR; /**< \brief (Tdes Offset: 0x1C) Interrupt Status Register */\r
+ __O uint32_t TDES_KEY1WR[2]; /**< \brief (Tdes Offset: 0x20) Key 1 Word Register */\r
+ __O uint32_t TDES_KEY2WR[2]; /**< \brief (Tdes Offset: 0x28) Key 2 Word Register */\r
+ __O uint32_t TDES_KEY3WR[2]; /**< \brief (Tdes Offset: 0x30) Key 3 Word Register */\r
+ __I uint32_t Reserved2[2];\r
+ __O uint32_t TDES_IDATAR[2]; /**< \brief (Tdes Offset: 0x40) Input Data Register */\r
+ __I uint32_t Reserved3[2];\r
+ __I uint32_t TDES_ODATAR[2]; /**< \brief (Tdes Offset: 0x50) Output Data Register */\r
+ __I uint32_t Reserved4[2];\r
+ __O uint32_t TDES_IVR[2]; /**< \brief (Tdes Offset: 0x60) Initialization Vector Register */\r
+ __I uint32_t Reserved5[2];\r
+ __IO uint32_t TDES_XTEA_RNDR; /**< \brief (Tdes Offset: 0x70) XTEA Rounds Register */\r
+ __I uint32_t Reserved6[34];\r
+ __I uint32_t TDES_VERSION; /**< \brief (Tdes Offset: 0xFC) Version Register */\r
+} Tdes;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TDES_CR : (TDES Offset: 0x00) Control Register -------- */\r
+#define TDES_CR_START (0x1u << 0) /**< \brief (TDES_CR) Start Processing */\r
+#define TDES_CR_SWRST (0x1u << 8) /**< \brief (TDES_CR) Software Reset */\r
+#define TDES_CR_LOADSEED (0x1u << 16) /**< \brief (TDES_CR) Load Seed */\r
+/* -------- TDES_MR : (TDES Offset: 0x04) Mode Register -------- */\r
+#define TDES_MR_CIPHER (0x1u << 0) /**< \brief (TDES_MR) Processing Mode */\r
+#define TDES_MR_CIPHER_DECRYPT (0x0u << 0) /**< \brief (TDES_MR) Decrypts data. */\r
+#define TDES_MR_CIPHER_ENCRYPT (0x1u << 0) /**< \brief (TDES_MR) Encrypts data. */\r
+#define TDES_MR_TDESMOD_Pos 1\r
+#define TDES_MR_TDESMOD_Msk (0x3u << TDES_MR_TDESMOD_Pos) /**< \brief (TDES_MR) ALGORITHM Mode */\r
+#define TDES_MR_TDESMOD(value) ((TDES_MR_TDESMOD_Msk & ((value) << TDES_MR_TDESMOD_Pos)))\r
+#define TDES_MR_TDESMOD_SINGLE_DES (0x0u << 1) /**< \brief (TDES_MR) Single DES processing using TDES_KEY1WRx registers */\r
+#define TDES_MR_TDESMOD_TRIPLE_DES (0x1u << 1) /**< \brief (TDES_MR) Triple DES processing using TDES_KEY1WRx, TDES_KEY2WRx and TDES_KEY3WRx registers */\r
+#define TDES_MR_TDESMOD_XTEA (0x2u << 1) /**< \brief (TDES_MR) XTEA processing using TDES_KEY1WRx, TDES_KEY2WRx */\r
+#define TDES_MR_KEYMOD (0x1u << 4) /**< \brief (TDES_MR) Key Mode */\r
+#define TDES_MR_SMOD_Pos 8\r
+#define TDES_MR_SMOD_Msk (0x3u << TDES_MR_SMOD_Pos) /**< \brief (TDES_MR) Start Mode */\r
+#define TDES_MR_SMOD(value) ((TDES_MR_SMOD_Msk & ((value) << TDES_MR_SMOD_Pos)))\r
+#define TDES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (TDES_MR) Manual Mode */\r
+#define TDES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (TDES_MR) Auto Mode */\r
+#define TDES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (TDES_MR) TDES_IDATAR0 access only Auto Mode */\r
+#define TDES_MR_OPMOD_Pos 12\r
+#define TDES_MR_OPMOD_Msk (0x3u << TDES_MR_OPMOD_Pos) /**< \brief (TDES_MR) Operation Mode */\r
+#define TDES_MR_OPMOD(value) ((TDES_MR_OPMOD_Msk & ((value) << TDES_MR_OPMOD_Pos)))\r
+#define TDES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (TDES_MR) Electronic Code Book mode */\r
+#define TDES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (TDES_MR) Cipher Block Chaining mode */\r
+#define TDES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (TDES_MR) Output Feedback mode */\r
+#define TDES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (TDES_MR) Cipher Feedback mode */\r
+#define TDES_MR_LOD (0x1u << 15) /**< \brief (TDES_MR) Last Output Data Mode */\r
+#define TDES_MR_CFBS_Pos 16\r
+#define TDES_MR_CFBS_Msk (0x3u << TDES_MR_CFBS_Pos) /**< \brief (TDES_MR) Cipher Feedback Data Size */\r
+#define TDES_MR_CFBS(value) ((TDES_MR_CFBS_Msk & ((value) << TDES_MR_CFBS_Pos)))\r
+#define TDES_MR_CFBS_SIZE_64BIT (0x0u << 16) /**< \brief (TDES_MR) 64-bit */\r
+#define TDES_MR_CFBS_SIZE_32BIT (0x1u << 16) /**< \brief (TDES_MR) 32-bit */\r
+#define TDES_MR_CFBS_SIZE_16BIT (0x2u << 16) /**< \brief (TDES_MR) 16-bit */\r
+#define TDES_MR_CFBS_SIZE_8BIT (0x3u << 16) /**< \brief (TDES_MR) 8-bit */\r
+#define TDES_MR_CKEY_Pos 20\r
+#define TDES_MR_CKEY_Msk (0xfu << TDES_MR_CKEY_Pos) /**< \brief (TDES_MR) Countermeasure Key */\r
+#define TDES_MR_CKEY(value) ((TDES_MR_CKEY_Msk & ((value) << TDES_MR_CKEY_Pos)))\r
+#define TDES_MR_CMTYP1 (0x1u << 24) /**< \brief (TDES_MR) Countermeasure Type 1 */\r
+#define TDES_MR_CMTYP1_NO_PAUSE (0x0u << 24) /**< \brief (TDES_MR) Countermeasure type 1 is disabled */\r
+#define TDES_MR_CMTYP1_PAUSE (0x1u << 24) /**< \brief (TDES_MR) Countermeasure type 1 is enabled */\r
+#define TDES_MR_CMTYP2 (0x1u << 25) /**< \brief (TDES_MR) Countermeasure Type 2 */\r
+#define TDES_MR_CMTYP2_NO_DUMMY (0x0u << 25) /**< \brief (TDES_MR) Countermeasure type 2 is disabled */\r
+#define TDES_MR_CMTYP2_DUMMY (0x1u << 25) /**< \brief (TDES_MR) Countermeasure type 2 is enabled */\r
+#define TDES_MR_CMTYP3 (0x1u << 26) /**< \brief (TDES_MR) Countermeasure Type 3 */\r
+#define TDES_MR_CMTYP3_NO_RESTART (0x0u << 26) /**< \brief (TDES_MR) Countermeasure type 3 is disabled */\r
+#define TDES_MR_CMTYP3_RESTART (0x1u << 26) /**< \brief (TDES_MR) Countermeasure type 3 is enabled */\r
+#define TDES_MR_CMTYP4 (0x1u << 27) /**< \brief (TDES_MR) Countermeasure Type 4 */\r
+#define TDES_MR_CMTYP4_NO_IDLECURRENT (0x0u << 27) /**< \brief (TDES_MR) Countermeasure type 4 is disabled */\r
+#define TDES_MR_CMTYP4_IDLECURRENT (0x1u << 27) /**< \brief (TDES_MR) Countermeasure type 4 is enabled */\r
+#define TDES_MR_CMTYP5 (0x1u << 28) /**< \brief (TDES_MR) Countermeasure Type 5 */\r
+#define TDES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (TDES_MR) Countermeasure type 5 is disabled */\r
+#define TDES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (TDES_MR) Countermeasure type 5 is enabled */\r
+#define TDES_MR_CMTYP6 (0x1u << 29) /**< \brief (TDES_MR) Countermeasure Type 6 */\r
+#define TDES_MR_CMTYP6_NO_UNIFORM (0x0u << 29) /**< \brief (TDES_MR) Countermeasure type 6 is disabled */\r
+#define TDES_MR_CMTYP6_UNIFORM (0x1u << 29) /**< \brief (TDES_MR) Countermeasure type 6 is enabled */\r
+/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */\r
+#define TDES_IER_DATRDY (0x1u << 0) /**< \brief (TDES_IER) Data Ready Interrupt Enable */\r
+#define TDES_IER_URAD (0x1u << 8) /**< \brief (TDES_IER) Unspecified Register Access Detection Interrupt Enable */\r
+/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */\r
+#define TDES_IDR_DATRDY (0x1u << 0) /**< \brief (TDES_IDR) Data Ready Interrupt Disable */\r
+#define TDES_IDR_URAD (0x1u << 8) /**< \brief (TDES_IDR) Unspecified Register Access Detection Interrupt Disable */\r
+/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */\r
+#define TDES_IMR_DATRDY (0x1u << 0) /**< \brief (TDES_IMR) Data Ready Interrupt Mask */\r
+#define TDES_IMR_URAD (0x1u << 8) /**< \brief (TDES_IMR) Unspecified Register Access Detection Interrupt Mask */\r
+/* -------- TDES_ISR : (TDES Offset: 0x1C) Interrupt Status Register -------- */\r
+#define TDES_ISR_DATRDY (0x1u << 0) /**< \brief (TDES_ISR) Data Ready (cleared by setting bit START or bit SWRST in TDES_CR or by reading TDES_ODATARx) */\r
+#define TDES_ISR_URAD (0x1u << 8) /**< \brief (TDES_ISR) Unspecified Register Access Detection Status (cleared by setting bit TDES_CR.SWRST) */\r
+#define TDES_ISR_URAT_Pos 12\r
+#define TDES_ISR_URAT_Msk (0x3u << TDES_ISR_URAT_Pos) /**< \brief (TDES_ISR) Unspecified Register Access (cleared by setting bit TDES_CR.SWRST) */\r
+#define TDES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (TDES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */\r
+#define TDES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (TDES_ISR) Output Data Register read during the data processing. */\r
+#define TDES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (TDES_ISR) Mode Register written during the data processing. */\r
+#define TDES_ISR_URAT_WOR_RD_ACCESS (0x3u << 12) /**< \brief (TDES_ISR) Write-only register read access. */\r
+/* -------- TDES_KEY1WR[2] : (TDES Offset: 0x20) Key 1 Word Register -------- */\r
+#define TDES_KEY1WR_KEY1W_Pos 0\r
+#define TDES_KEY1WR_KEY1W_Msk (0xffffffffu << TDES_KEY1WR_KEY1W_Pos) /**< \brief (TDES_KEY1WR[2]) Key 1 Word */\r
+#define TDES_KEY1WR_KEY1W(value) ((TDES_KEY1WR_KEY1W_Msk & ((value) << TDES_KEY1WR_KEY1W_Pos)))\r
+/* -------- TDES_KEY2WR[2] : (TDES Offset: 0x28) Key 2 Word Register -------- */\r
+#define TDES_KEY2WR_KEY2W_Pos 0\r
+#define TDES_KEY2WR_KEY2W_Msk (0xffffffffu << TDES_KEY2WR_KEY2W_Pos) /**< \brief (TDES_KEY2WR[2]) Key 2 Word */\r
+#define TDES_KEY2WR_KEY2W(value) ((TDES_KEY2WR_KEY2W_Msk & ((value) << TDES_KEY2WR_KEY2W_Pos)))\r
+/* -------- TDES_KEY3WR[2] : (TDES Offset: 0x30) Key 3 Word Register -------- */\r
+#define TDES_KEY3WR_KEY3W_Pos 0\r
+#define TDES_KEY3WR_KEY3W_Msk (0xffffffffu << TDES_KEY3WR_KEY3W_Pos) /**< \brief (TDES_KEY3WR[2]) Key 3 Word */\r
+#define TDES_KEY3WR_KEY3W(value) ((TDES_KEY3WR_KEY3W_Msk & ((value) << TDES_KEY3WR_KEY3W_Pos)))\r
+/* -------- TDES_IDATAR[2] : (TDES Offset: 0x40) Input Data Register -------- */\r
+#define TDES_IDATAR_IDATA_Pos 0\r
+#define TDES_IDATAR_IDATA_Msk (0xffffffffu << TDES_IDATAR_IDATA_Pos) /**< \brief (TDES_IDATAR[2]) Input Data */\r
+#define TDES_IDATAR_IDATA(value) ((TDES_IDATAR_IDATA_Msk & ((value) << TDES_IDATAR_IDATA_Pos)))\r
+/* -------- TDES_ODATAR[2] : (TDES Offset: 0x50) Output Data Register -------- */\r
+#define TDES_ODATAR_ODATA_Pos 0\r
+#define TDES_ODATAR_ODATA_Msk (0xffffffffu << TDES_ODATAR_ODATA_Pos) /**< \brief (TDES_ODATAR[2]) Output Data */\r
+/* -------- TDES_IVR[2] : (TDES Offset: 0x60) Initialization Vector Register -------- */\r
+#define TDES_IVR_IV_Pos 0\r
+#define TDES_IVR_IV_Msk (0xffffffffu << TDES_IVR_IV_Pos) /**< \brief (TDES_IVR[2]) Initialization Vector */\r
+#define TDES_IVR_IV(value) ((TDES_IVR_IV_Msk & ((value) << TDES_IVR_IV_Pos)))\r
+/* -------- TDES_XTEA_RNDR : (TDES Offset: 0x70) XTEA Rounds Register -------- */\r
+#define TDES_XTEA_RNDR_XTEA_RNDS_Pos 0\r
+#define TDES_XTEA_RNDR_XTEA_RNDS_Msk (0x3fu << TDES_XTEA_RNDR_XTEA_RNDS_Pos) /**< \brief (TDES_XTEA_RNDR) Number of Rounds */\r
+#define TDES_XTEA_RNDR_XTEA_RNDS(value) ((TDES_XTEA_RNDR_XTEA_RNDS_Msk & ((value) << TDES_XTEA_RNDR_XTEA_RNDS_Pos)))\r
+/* -------- TDES_VERSION : (TDES Offset: 0xFC) Version Register -------- */\r
+#define TDES_VERSION_VERSION_Pos 0\r
+#define TDES_VERSION_VERSION_Msk (0xfffu << TDES_VERSION_VERSION_Pos) /**< \brief (TDES_VERSION) Version of the Hardware Module */\r
+#define TDES_VERSION_MFN_Pos 16\r
+#define TDES_VERSION_MFN_Msk (0x7u << TDES_VERSION_MFN_Pos) /**< \brief (TDES_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_TDES_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_TRNG_COMPONENT_\r
+#define _SAMA5D2_TRNG_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR True Random Number Generator */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_TRNG True Random Number Generator */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Trng hardware registers */\r
+typedef struct {\r
+ __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */\r
+ __I uint32_t Reserved1[3];\r
+ __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */\r
+ __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */\r
+ __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */\r
+ __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */\r
+ __I uint32_t Reserved2[12];\r
+ __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */\r
+ __I uint32_t Reserved3[42];\r
+ __I uint32_t TRNG_VERSION; /**< \brief (Trng Offset: 0xFC) Version Register */\r
+} Trng;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */\r
+#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to Provide Random Values */\r
+#define TRNG_CR_KEY_Pos 8\r
+#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */\r
+#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))\r
+#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */\r
+/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */\r
+#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */\r
+/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */\r
+#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */\r
+/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */\r
+#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */\r
+/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */\r
+#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */\r
+/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */\r
+#define TRNG_ODATA_ODATA_Pos 0\r
+#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */\r
+/* -------- TRNG_VERSION : (TRNG Offset: 0xFC) Version Register -------- */\r
+#define TRNG_VERSION_VERSION_Pos 0\r
+#define TRNG_VERSION_VERSION_Msk (0xfffu << TRNG_VERSION_VERSION_Pos) /**< \brief (TRNG_VERSION) Version of the Hardware Module */\r
+#define TRNG_VERSION_MFN_Pos 16\r
+#define TRNG_VERSION_MFN_Msk (0x7u << TRNG_VERSION_MFN_Pos) /**< \brief (TRNG_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_TRNG_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_TWIHS_COMPONENT_\r
+#define _SAMA5D2_TWIHS_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_TWIHS Two-wire Interface High Speed */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Twihs hardware registers */\r
+typedef struct {\r
+ __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */\r
+ __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */\r
+ __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */\r
+ __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */\r
+ __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */\r
+ __I uint32_t Reserved1[3];\r
+ __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */\r
+ __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */\r
+ __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */\r
+ __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */\r
+ __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */\r
+ __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */\r
+ __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */\r
+ __I uint32_t Reserved2[1];\r
+ __IO uint32_t TWIHS_ACR; /**< \brief (Twihs Offset: 0x40) Alternative Command Register */\r
+ __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */\r
+ __I uint32_t Reserved3[1];\r
+ __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */\r
+ __IO uint32_t TWIHS_FMR; /**< \brief (Twihs Offset: 0x50) FIFO Mode Register */\r
+ __I uint32_t TWIHS_FLR; /**< \brief (Twihs Offset: 0x54) FIFO Level Register */\r
+ __I uint32_t Reserved4[2];\r
+ __I uint32_t TWIHS_FSR; /**< \brief (Twihs Offset: 0x60) FIFO Status Register */\r
+ __O uint32_t TWIHS_FIER; /**< \brief (Twihs Offset: 0x64) FIFO Interrupt Enable Register */\r
+ __O uint32_t TWIHS_FIDR; /**< \brief (Twihs Offset: 0x68) FIFO Interrupt Disable Register */\r
+ __I uint32_t TWIHS_FIMR; /**< \brief (Twihs Offset: 0x6C) FIFO Interrupt Mask Register */\r
+ __I uint32_t Reserved5[24];\r
+ __I uint32_t TWIHS_DR; /**< \brief (Twihs Offset: 0xD0) Debug Register */\r
+ __I uint32_t Reserved6[4];\r
+ __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */\r
+ __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */\r
+ __I uint32_t Reserved7[4];\r
+ __I uint32_t TWIHS_VER; /**< \brief (Twihs Offset: 0xFC) Version Register */\r
+} Twihs;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */\r
+#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */\r
+#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */\r
+#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */\r
+#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */\r
+#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */\r
+#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */\r
+#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */\r
+#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */\r
+#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */\r
+#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */\r
+#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */\r
+#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */\r
+#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */\r
+#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */\r
+#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */\r
+#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */\r
+#define TWIHS_CR_ACMEN (0x1u << 16) /**< \brief (TWIHS_CR) Alternative Command Mode Enable */\r
+#define TWIHS_CR_ACMDIS (0x1u << 17) /**< \brief (TWIHS_CR) Alternative Command Mode Disable */\r
+#define TWIHS_CR_THRCLR (0x1u << 24) /**< \brief (TWIHS_CR) Transmit Holding Register Clear */\r
+#define TWIHS_CR_LOCKCLR (0x1u << 26) /**< \brief (TWIHS_CR) Lock Clear */\r
+#define TWIHS_CR_FIFOEN (0x1u << 28) /**< \brief (TWIHS_CR) FIFO Enable */\r
+#define TWIHS_CR_FIFODIS (0x1u << 29) /**< \brief (TWIHS_CR) FIFO Disable */\r
+/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */\r
+#define TWIHS_MMR_IADRSZ_Pos 8\r
+#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */\r
+#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)))\r
+#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */\r
+#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */\r
+#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */\r
+#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */\r
+#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */\r
+#define TWIHS_MMR_DADR_Pos 16\r
+#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */\r
+#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)))\r
+/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */\r
+#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */\r
+#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */\r
+#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */\r
+#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */\r
+#define TWIHS_SMR_MASK_Pos 8\r
+#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */\r
+#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)))\r
+#define TWIHS_SMR_SADR_Pos 16\r
+#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */\r
+#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)))\r
+#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */\r
+#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */\r
+#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */\r
+#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */\r
+/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */\r
+#define TWIHS_IADR_IADR_Pos 0\r
+#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */\r
+#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)))\r
+/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */\r
+#define TWIHS_CWGR_CLDIV_Pos 0\r
+#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */\r
+#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)))\r
+#define TWIHS_CWGR_CHDIV_Pos 8\r
+#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */\r
+#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)))\r
+#define TWIHS_CWGR_CKDIV_Pos 16\r
+#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */\r
+#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)))\r
+#define TWIHS_CWGR_CKSRC (0x1u << 20) /**< \brief (TWIHS_CWGR) Transfer Rate Clock Source */\r
+#define TWIHS_CWGR_CKSRC_PERIPH_CK (0x0u << 20) /**< \brief (TWIHS_CWGR) Peripheral clock is used to generate the TWIHS baud rate. */\r
+#define TWIHS_CWGR_CKSRC_PMC_PCK (0x1u << 20) /**< \brief (TWIHS_CWGR) PMC PCKx is used to generate the TWIHS baud rate. */\r
+#define TWIHS_CWGR_HOLD_Pos 24\r
+#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */\r
+#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)))\r
+/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */\r
+#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */\r
+#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */\r
+#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */\r
+#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */\r
+#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */\r
+#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */\r
+#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */\r
+#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */\r
+#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */\r
+#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */\r
+#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */\r
+#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */\r
+#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */\r
+#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */\r
+#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */\r
+#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */\r
+#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */\r
+#define TWIHS_SR_LOCK (0x1u << 23) /**< \brief (TWIHS_SR) TWIHS Lock due to Frame Errors (cleared by writing a one to bit LOCKCLR in TWIHS_CR) */\r
+#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL Line Value */\r
+#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA Line Value */\r
+/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */\r
+#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */\r
+#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */\r
+#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */\r
+#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */\r
+#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */\r
+#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */\r
+#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */\r
+#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */\r
+#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */\r
+#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */\r
+#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */\r
+#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */\r
+#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */\r
+#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */\r
+#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */\r
+#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */\r
+/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */\r
+#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */\r
+#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */\r
+#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */\r
+#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */\r
+#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */\r
+#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */\r
+#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */\r
+#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */\r
+#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */\r
+#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */\r
+#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */\r
+#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */\r
+#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */\r
+#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */\r
+#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */\r
+#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */\r
+/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */\r
+#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */\r
+#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */\r
+#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */\r
+#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */\r
+#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */\r
+#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */\r
+#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */\r
+#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */\r
+#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */\r
+#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */\r
+#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */\r
+#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */\r
+#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */\r
+#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */\r
+#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */\r
+/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */\r
+#define TWIHS_RHR_RXDATA_Pos 0\r
+#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */\r
+#define TWIHS_RHR_RXDATA0_Pos 0\r
+#define TWIHS_RHR_RXDATA0_Msk (0xffu << TWIHS_RHR_RXDATA0_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data 0 */\r
+#define TWIHS_RHR_RXDATA1_Pos 8\r
+#define TWIHS_RHR_RXDATA1_Msk (0xffu << TWIHS_RHR_RXDATA1_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data 1 */\r
+#define TWIHS_RHR_RXDATA2_Pos 16\r
+#define TWIHS_RHR_RXDATA2_Msk (0xffu << TWIHS_RHR_RXDATA2_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data 2 */\r
+#define TWIHS_RHR_RXDATA3_Pos 24\r
+#define TWIHS_RHR_RXDATA3_Msk (0xffu << TWIHS_RHR_RXDATA3_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data 3 */\r
+/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */\r
+#define TWIHS_THR_TXDATA_Pos 0\r
+#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */\r
+#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)))\r
+#define TWIHS_THR_TXDATA0_Pos 0\r
+#define TWIHS_THR_TXDATA0_Msk (0xffu << TWIHS_THR_TXDATA0_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data 0 */\r
+#define TWIHS_THR_TXDATA0(value) ((TWIHS_THR_TXDATA0_Msk & ((value) << TWIHS_THR_TXDATA0_Pos)))\r
+#define TWIHS_THR_TXDATA1_Pos 8\r
+#define TWIHS_THR_TXDATA1_Msk (0xffu << TWIHS_THR_TXDATA1_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data 1 */\r
+#define TWIHS_THR_TXDATA1(value) ((TWIHS_THR_TXDATA1_Msk & ((value) << TWIHS_THR_TXDATA1_Pos)))\r
+#define TWIHS_THR_TXDATA2_Pos 16\r
+#define TWIHS_THR_TXDATA2_Msk (0xffu << TWIHS_THR_TXDATA2_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data 2 */\r
+#define TWIHS_THR_TXDATA2(value) ((TWIHS_THR_TXDATA2_Msk & ((value) << TWIHS_THR_TXDATA2_Pos)))\r
+#define TWIHS_THR_TXDATA3_Pos 24\r
+#define TWIHS_THR_TXDATA3_Msk (0xffu << TWIHS_THR_TXDATA3_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data 3 */\r
+#define TWIHS_THR_TXDATA3(value) ((TWIHS_THR_TXDATA3_Msk & ((value) << TWIHS_THR_TXDATA3_Pos)))\r
+/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */\r
+#define TWIHS_SMBTR_PRESC_Pos 0\r
+#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */\r
+#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)))\r
+#define TWIHS_SMBTR_TLOWS_Pos 8\r
+#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */\r
+#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)))\r
+#define TWIHS_SMBTR_TLOWM_Pos 16\r
+#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */\r
+#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)))\r
+#define TWIHS_SMBTR_THMAX_Pos 24\r
+#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */\r
+#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)))\r
+/* -------- TWIHS_ACR : (TWIHS Offset: 0x40) Alternative Command Register -------- */\r
+#define TWIHS_ACR_DATAL_Pos 0\r
+#define TWIHS_ACR_DATAL_Msk (0xffu << TWIHS_ACR_DATAL_Pos) /**< \brief (TWIHS_ACR) Data Length */\r
+#define TWIHS_ACR_DATAL(value) ((TWIHS_ACR_DATAL_Msk & ((value) << TWIHS_ACR_DATAL_Pos)))\r
+#define TWIHS_ACR_DIR (0x1u << 8) /**< \brief (TWIHS_ACR) Transfer Direction */\r
+#define TWIHS_ACR_PEC (0x1u << 9) /**< \brief (TWIHS_ACR) PEC Request (SMBus Mode only) */\r
+#define TWIHS_ACR_NDATAL_Pos 16\r
+#define TWIHS_ACR_NDATAL_Msk (0xffu << TWIHS_ACR_NDATAL_Pos) /**< \brief (TWIHS_ACR) Next Data Length */\r
+#define TWIHS_ACR_NDATAL(value) ((TWIHS_ACR_NDATAL_Msk & ((value) << TWIHS_ACR_NDATAL_Pos)))\r
+#define TWIHS_ACR_NDIR (0x1u << 24) /**< \brief (TWIHS_ACR) Next Transfer Direction */\r
+#define TWIHS_ACR_NPEC (0x1u << 25) /**< \brief (TWIHS_ACR) Next PEC Request (SMBus Mode only) */\r
+/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */\r
+#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */\r
+#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */\r
+#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */\r
+#define TWIHS_FILTR_THRES_Pos 8\r
+#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */\r
+#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)))\r
+/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */\r
+#define TWIHS_SWMR_SADR1_Pos 0\r
+#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */\r
+#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)))\r
+#define TWIHS_SWMR_SADR2_Pos 8\r
+#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */\r
+#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)))\r
+#define TWIHS_SWMR_SADR3_Pos 16\r
+#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */\r
+#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)))\r
+#define TWIHS_SWMR_DATAM_Pos 24\r
+#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */\r
+#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)))\r
+/* -------- TWIHS_FMR : (TWIHS Offset: 0x50) FIFO Mode Register -------- */\r
+#define TWIHS_FMR_TXRDYM_Pos 0\r
+#define TWIHS_FMR_TXRDYM_Msk (0x3u << TWIHS_FMR_TXRDYM_Pos) /**< \brief (TWIHS_FMR) Transmitter Ready Mode */\r
+#define TWIHS_FMR_TXRDYM(value) ((TWIHS_FMR_TXRDYM_Msk & ((value) << TWIHS_FMR_TXRDYM_Pos)))\r
+#define TWIHS_FMR_TXRDYM_ONE_DATA (0x0u << 0) /**< \brief (TWIHS_FMR) TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO */\r
+#define TWIHS_FMR_TXRDYM_TWO_DATA (0x1u << 0) /**< \brief (TWIHS_FMR) TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO */\r
+#define TWIHS_FMR_TXRDYM_FOUR_DATA (0x2u << 0) /**< \brief (TWIHS_FMR) TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO */\r
+#define TWIHS_FMR_RXRDYM_Pos 4\r
+#define TWIHS_FMR_RXRDYM_Msk (0x3u << TWIHS_FMR_RXRDYM_Pos) /**< \brief (TWIHS_FMR) Receiver Ready Mode */\r
+#define TWIHS_FMR_RXRDYM(value) ((TWIHS_FMR_RXRDYM_Msk & ((value) << TWIHS_FMR_RXRDYM_Pos)))\r
+#define TWIHS_FMR_RXRDYM_ONE_DATA (0x0u << 4) /**< \brief (TWIHS_FMR) RXRDY will be at level '1' when at least one unread data is in the Receive FIFO */\r
+#define TWIHS_FMR_RXRDYM_TWO_DATA (0x1u << 4) /**< \brief (TWIHS_FMR) RXRDY will be at level '1' when at least two unread data are in the Receive FIFO */\r
+#define TWIHS_FMR_RXRDYM_FOUR_DATA (0x2u << 4) /**< \brief (TWIHS_FMR) RXRDY will be at level '1' when at least four unread data are in the Receive FIFO */\r
+#define TWIHS_FMR_TXFTHRES_Pos 16\r
+#define TWIHS_FMR_TXFTHRES_Msk (0x3fu << TWIHS_FMR_TXFTHRES_Pos) /**< \brief (TWIHS_FMR) Transmit FIFO Threshold */\r
+#define TWIHS_FMR_TXFTHRES(value) ((TWIHS_FMR_TXFTHRES_Msk & ((value) << TWIHS_FMR_TXFTHRES_Pos)))\r
+#define TWIHS_FMR_RXFTHRES_Pos 24\r
+#define TWIHS_FMR_RXFTHRES_Msk (0x3fu << TWIHS_FMR_RXFTHRES_Pos) /**< \brief (TWIHS_FMR) Receive FIFO Threshold */\r
+#define TWIHS_FMR_RXFTHRES(value) ((TWIHS_FMR_RXFTHRES_Msk & ((value) << TWIHS_FMR_RXFTHRES_Pos)))\r
+/* -------- TWIHS_FLR : (TWIHS Offset: 0x54) FIFO Level Register -------- */\r
+#define TWIHS_FLR_TXFL_Pos 0\r
+#define TWIHS_FLR_TXFL_Msk (0x3fu << TWIHS_FLR_TXFL_Pos) /**< \brief (TWIHS_FLR) Transmit FIFO Level */\r
+#define TWIHS_FLR_RXFL_Pos 16\r
+#define TWIHS_FLR_RXFL_Msk (0x3fu << TWIHS_FLR_RXFL_Pos) /**< \brief (TWIHS_FLR) Receive FIFO Level */\r
+/* -------- TWIHS_FSR : (TWIHS Offset: 0x60) FIFO Status Register -------- */\r
+#define TWIHS_FSR_TXFEF (0x1u << 0) /**< \brief (TWIHS_FSR) Transmit FIFO Empty Flag (cleared on read) */\r
+#define TWIHS_FSR_TXFFF (0x1u << 1) /**< \brief (TWIHS_FSR) Transmit FIFO Full Flag (cleared on read) */\r
+#define TWIHS_FSR_TXFTHF (0x1u << 2) /**< \brief (TWIHS_FSR) Transmit FIFO Threshold Flag (cleared on read) */\r
+#define TWIHS_FSR_RXFEF (0x1u << 3) /**< \brief (TWIHS_FSR) Receive FIFO Empty Flag */\r
+#define TWIHS_FSR_RXFFF (0x1u << 4) /**< \brief (TWIHS_FSR) Receive FIFO Full Flag */\r
+#define TWIHS_FSR_RXFTHF (0x1u << 5) /**< \brief (TWIHS_FSR) Receive FIFO Threshold Flag */\r
+#define TWIHS_FSR_TXFPTEF (0x1u << 6) /**< \brief (TWIHS_FSR) Transmit FIFO Pointer Error Flag */\r
+#define TWIHS_FSR_RXFPTEF (0x1u << 7) /**< \brief (TWIHS_FSR) Receive FIFO Pointer Error Flag */\r
+/* -------- TWIHS_FIER : (TWIHS Offset: 0x64) FIFO Interrupt Enable Register -------- */\r
+#define TWIHS_FIER_TXFEF (0x1u << 0) /**< \brief (TWIHS_FIER) TXFEF Interrupt Enable */\r
+#define TWIHS_FIER_TXFFF (0x1u << 1) /**< \brief (TWIHS_FIER) TXFFF Interrupt Enable */\r
+#define TWIHS_FIER_TXFTHF (0x1u << 2) /**< \brief (TWIHS_FIER) TXFTHF Interrupt Enable */\r
+#define TWIHS_FIER_RXFEF (0x1u << 3) /**< \brief (TWIHS_FIER) RXFEF Interrupt Enable */\r
+#define TWIHS_FIER_RXFFF (0x1u << 4) /**< \brief (TWIHS_FIER) RXFFF Interrupt Enable */\r
+#define TWIHS_FIER_RXFTHF (0x1u << 5) /**< \brief (TWIHS_FIER) RXFTHF Interrupt Enable */\r
+#define TWIHS_FIER_TXFPTEF (0x1u << 6) /**< \brief (TWIHS_FIER) TXFPTEF Interrupt Enable */\r
+#define TWIHS_FIER_RXFPTEF (0x1u << 7) /**< \brief (TWIHS_FIER) RXFPTEF Interrupt Enable */\r
+/* -------- TWIHS_FIDR : (TWIHS Offset: 0x68) FIFO Interrupt Disable Register -------- */\r
+#define TWIHS_FIDR_TXFEF (0x1u << 0) /**< \brief (TWIHS_FIDR) TXFEF Interrupt Disable */\r
+#define TWIHS_FIDR_TXFFF (0x1u << 1) /**< \brief (TWIHS_FIDR) TXFFF Interrupt Disable */\r
+#define TWIHS_FIDR_TXFTHF (0x1u << 2) /**< \brief (TWIHS_FIDR) TXFTHF Interrupt Disable */\r
+#define TWIHS_FIDR_RXFEF (0x1u << 3) /**< \brief (TWIHS_FIDR) RXFEF Interrupt Disable */\r
+#define TWIHS_FIDR_RXFFF (0x1u << 4) /**< \brief (TWIHS_FIDR) RXFFF Interrupt Disable */\r
+#define TWIHS_FIDR_RXFTHF (0x1u << 5) /**< \brief (TWIHS_FIDR) RXFTHF Interrupt Disable */\r
+#define TWIHS_FIDR_TXFPTEF (0x1u << 6) /**< \brief (TWIHS_FIDR) TXFPTEF Interrupt Disable */\r
+#define TWIHS_FIDR_RXFPTEF (0x1u << 7) /**< \brief (TWIHS_FIDR) RXFPTEF Interrupt Disable */\r
+/* -------- TWIHS_FIMR : (TWIHS Offset: 0x6C) FIFO Interrupt Mask Register -------- */\r
+#define TWIHS_FIMR_TXFEF (0x1u << 0) /**< \brief (TWIHS_FIMR) TXFEF Interrupt Mask */\r
+#define TWIHS_FIMR_TXFFF (0x1u << 1) /**< \brief (TWIHS_FIMR) TXFFF Interrupt Mask */\r
+#define TWIHS_FIMR_TXFTHF (0x1u << 2) /**< \brief (TWIHS_FIMR) TXFTHF Interrupt Mask */\r
+#define TWIHS_FIMR_RXFEF (0x1u << 3) /**< \brief (TWIHS_FIMR) RXFEF Interrupt Mask */\r
+#define TWIHS_FIMR_RXFFF (0x1u << 4) /**< \brief (TWIHS_FIMR) RXFFF Interrupt Mask */\r
+#define TWIHS_FIMR_RXFTHF (0x1u << 5) /**< \brief (TWIHS_FIMR) RXFTHF Interrupt Mask */\r
+#define TWIHS_FIMR_TXFPTEF (0x1u << 6) /**< \brief (TWIHS_FIMR) TXFPTEF Interrupt Mask */\r
+#define TWIHS_FIMR_RXFPTEF (0x1u << 7) /**< \brief (TWIHS_FIMR) RXFPTEF Interrupt Mask */\r
+/* -------- TWIHS_DR : (TWIHS Offset: 0xD0) Debug Register -------- */\r
+#define TWIHS_DR_SWEN (0x1u << 0) /**< \brief (TWIHS_DR) SleepWalking Enable */\r
+#define TWIHS_DR_CLKRQ (0x1u << 1) /**< \brief (TWIHS_DR) Clock Request */\r
+#define TWIHS_DR_SWMATCH (0x1u << 2) /**< \brief (TWIHS_DR) SleepWalking Match */\r
+#define TWIHS_DR_TRP (0x1u << 3) /**< \brief (TWIHS_DR) Transfer Pending */\r
+/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */\r
+#define TWIHS_WPMR_WPKEY_Pos 8\r
+#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */\r
+#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)))\r
+#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */\r
+/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */\r
+#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */\r
+#define TWIHS_WPSR_WPVSRC_Pos 8\r
+#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */\r
+/* -------- TWIHS_VER : (TWIHS Offset: 0xFC) Version Register -------- */\r
+#define TWIHS_VER_VERSION_Pos 0\r
+#define TWIHS_VER_VERSION_Msk (0xfffu << TWIHS_VER_VERSION_Pos) /**< \brief (TWIHS_VER) Version of the Hardware Module */\r
+#define TWIHS_VER_MFN_Pos 16\r
+#define TWIHS_VER_MFN_Msk (0x7u << TWIHS_VER_MFN_Pos) /**< \brief (TWIHS_VER) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_TWIHS_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_UART_COMPONENT_\r
+#define _SAMA5D2_UART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_UART Universal Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Uart hardware registers */\r
+typedef struct {\r
+ __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */\r
+ __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */\r
+ __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */\r
+ __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */\r
+ __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */\r
+ __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */\r
+ __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */\r
+ __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */\r
+ __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */\r
+ __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */\r
+ __IO uint32_t UART_RTOR; /**< \brief (Uart Offset: 0x0028) Receiver Time-out Register */\r
+ __I uint32_t Reserved1[46];\r
+ __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */\r
+ __I uint32_t Reserved2[5];\r
+ __I uint32_t UART_VERSION; /**< \brief (Uart Offset: 0x00FC) Version Register */\r
+} Uart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */\r
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */\r
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */\r
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */\r
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */\r
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */\r
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */\r
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */\r
+#define UART_CR_RETTO (0x1u << 10) /**< \brief (UART_CR) Rearm Time-out */\r
+#define UART_CR_STTTO (0x1u << 11) /**< \brief (UART_CR) Start Time-out */\r
+#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */\r
+#define UART_CR_DBGE (0x1u << 15) /**< \brief (UART_CR) Debug Enable */\r
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */\r
+#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */\r
+#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */\r
+#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */\r
+#define UART_MR_PAR_Pos 9\r
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */\r
+#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)))\r
+#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */\r
+#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */\r
+#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */\r
+#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */\r
+#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */\r
+#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */\r
+#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */\r
+#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */\r
+#define UART_MR_CHMODE_Pos 14\r
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */\r
+#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)))\r
+#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */\r
+#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */\r
+#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */\r
+#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */\r
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */\r
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */\r
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */\r
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */\r
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */\r
+#define UART_IER_TIMEOUT (0x1u << 8) /**< \brief (UART_IER) Enable Time-out Interrupt */\r
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */\r
+#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */\r
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */\r
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */\r
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */\r
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */\r
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */\r
+#define UART_IDR_TIMEOUT (0x1u << 8) /**< \brief (UART_IDR) Disable Time-out Interrupt */\r
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */\r
+#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */\r
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */\r
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */\r
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */\r
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */\r
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */\r
+#define UART_IMR_TIMEOUT (0x1u << 8) /**< \brief (UART_IMR) Mask Time-out Interrupt */\r
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */\r
+#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */\r
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */\r
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */\r
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */\r
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */\r
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */\r
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */\r
+#define UART_SR_TIMEOUT (0x1u << 8) /**< \brief (UART_SR) Receiver Time-out */\r
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */\r
+#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */\r
+#define UART_SR_SWES (0x1u << 21) /**< \brief (UART_SR) SleepWalking Enable Status */\r
+#define UART_SR_CLKREQ (0x1u << 22) /**< \brief (UART_SR) Clock Request */\r
+#define UART_SR_WKUPREQ (0x1u << 23) /**< \brief (UART_SR) Wake-Up Request */\r
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */\r
+#define UART_RHR_RXCHR_Pos 0\r
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */\r
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */\r
+#define UART_THR_TXCHR_Pos 0\r
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */\r
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))\r
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define UART_BRGR_CD_Pos 0\r
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */\r
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))\r
+/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */\r
+#define UART_CMPR_VAL1_Pos 0\r
+#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */\r
+#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)))\r
+#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */\r
+#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */\r
+#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */\r
+#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */\r
+#define UART_CMPR_VAL2_Pos 16\r
+#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */\r
+#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)))\r
+/* -------- UART_RTOR : (UART Offset: 0x0028) Receiver Time-out Register -------- */\r
+#define UART_RTOR_TO_Pos 0\r
+#define UART_RTOR_TO_Msk (0xffu << UART_RTOR_TO_Pos) /**< \brief (UART_RTOR) Time-out Value */\r
+#define UART_RTOR_TO(value) ((UART_RTOR_TO_Msk & ((value) << UART_RTOR_TO_Pos)))\r
+/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */\r
+#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */\r
+#define UART_WPMR_WPKEY_Pos 8\r
+#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */\r
+#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)))\r
+#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */\r
+/* -------- UART_VERSION : (UART Offset: 0x00FC) Version Register -------- */\r
+#define UART_VERSION_VERSION_Pos 0\r
+#define UART_VERSION_VERSION_Msk (0xfffu << UART_VERSION_VERSION_Pos) /**< \brief (UART_VERSION) Hardware Module Version */\r
+#define UART_VERSION_MFN_Pos 16\r
+#define UART_VERSION_MFN_Msk (0x7u << UART_VERSION_MFN_Pos) /**< \brief (UART_VERSION) Metal Fix Number */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_UART_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_UDPHS_COMPONENT_\r
+#define _SAMA5D2_UDPHS_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR USB High Speed Device Port */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_UDPHS USB High Speed Device Port */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief UdphsDma hardware registers */\r
+typedef struct {\r
+ __IO uint32_t UDPHS_DMANXTDSC; /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */\r
+ __IO uint32_t UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */\r
+ __IO uint32_t UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */\r
+ __IO uint32_t UDPHS_DMASTATUS; /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */\r
+} UdphsDma;\r
+/** \brief UdphsEpt hardware registers */\r
+typedef struct {\r
+ __IO uint32_t UDPHS_EPTCFG; /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */\r
+ __O uint32_t UDPHS_EPTCTLENB; /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */\r
+ __O uint32_t UDPHS_EPTCTLDIS; /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */\r
+ __I uint32_t UDPHS_EPTCTL; /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */\r
+ __I uint32_t Reserved1[1];\r
+ __O uint32_t UDPHS_EPTSETSTA; /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */\r
+ __O uint32_t UDPHS_EPTCLRSTA; /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */\r
+ __I uint32_t UDPHS_EPTSTA; /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */\r
+} UdphsEpt;\r
+/** \brief Udphs hardware registers */\r
+#define UDPHSEPT_NUMBER 16\r
+#define UDPHSDMA_NUMBER 7\r
+typedef struct {\r
+ __IO uint32_t UDPHS_CTRL; /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */\r
+ __I uint32_t UDPHS_FNUM; /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */\r
+ __I uint32_t Reserved1[2];\r
+ __IO uint32_t UDPHS_IEN; /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */\r
+ __I uint32_t UDPHS_INTSTA; /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */\r
+ __O uint32_t UDPHS_CLRINT; /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */\r
+ __O uint32_t UDPHS_EPTRST; /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */\r
+ __I uint32_t Reserved2[44];\r
+ __IO uint32_t UDPHS_TSTSOFCNT; /**< \brief (Udphs Offset: 0xD0) UDPHS Test SOF Counter Register */\r
+ __IO uint32_t UDPHS_TSTCNTA; /**< \brief (Udphs Offset: 0xD4) UDPHS Test A Counter Register */\r
+ __IO uint32_t UDPHS_TSTCNTB; /**< \brief (Udphs Offset: 0xD8) UDPHS Test B Counter Register */\r
+ __IO uint32_t UDPHS_TSTMODEREG; /**< \brief (Udphs Offset: 0xDC) UDPHS Test Mode Register */\r
+ __IO uint32_t UDPHS_TST; /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */\r
+ __I uint32_t Reserved3[6];\r
+ __I uint32_t UDPHS_VERSION; /**< \brief (Udphs Offset: 0xFC) UDPHS Version Register */\r
+ UdphsEpt UDPHS_EPT[UDPHSEPT_NUMBER]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 15 */\r
+ UdphsDma UDPHS_DMA[UDPHSDMA_NUMBER]; /**< \brief (Udphs Offset: 0x300) channel = 0 .. 6 */\r
+} Udphs;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */\r
+#define UDPHS_CTRL_DEV_ADDR_Pos 0\r
+#define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) /**< \brief (UDPHS_CTRL) UDPHS Address (cleared upon USB reset) */\r
+#define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos)))\r
+#define UDPHS_CTRL_FADDR_EN (0x1u << 7) /**< \brief (UDPHS_CTRL) Function Address Enable (cleared upon USB reset) */\r
+#define UDPHS_CTRL_EN_UDPHS (0x1u << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */\r
+#define UDPHS_CTRL_DETACH (0x1u << 9) /**< \brief (UDPHS_CTRL) Detach Command */\r
+#define UDPHS_CTRL_REWAKEUP (0x1u << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up (cleared upon USB reset) */\r
+#define UDPHS_CTRL_PULLD_DIS (0x1u << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable (cleared upon USB reset) */\r
+/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */\r
+#define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0\r
+#define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) /**< \brief (UDPHS_FNUM) Microframe Number (cleared upon USB reset) */\r
+#define UDPHS_FNUM_FRAME_NUMBER_Pos 3\r
+#define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats (cleared upon USB reset) */\r
+#define UDPHS_FNUM_FNUM_ERR (0x1u << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error (cleared upon USB reset) */\r
+/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */\r
+#define UDPHS_IEN_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_INT_SOF (0x1u << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_ENDRESET (0x1u << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_0 (0x1u << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_1 (0x1u << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_2 (0x1u << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_3 (0x1u << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_4 (0x1u << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_5 (0x1u << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_6 (0x1u << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_7 (0x1u << 15) /**< \brief (UDPHS_IEN) Endpoint 7 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_8 (0x1u << 16) /**< \brief (UDPHS_IEN) Endpoint 8 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_9 (0x1u << 17) /**< \brief (UDPHS_IEN) Endpoint 9 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_10 (0x1u << 18) /**< \brief (UDPHS_IEN) Endpoint 10 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_11 (0x1u << 19) /**< \brief (UDPHS_IEN) Endpoint 11 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_12 (0x1u << 20) /**< \brief (UDPHS_IEN) Endpoint 12 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_13 (0x1u << 21) /**< \brief (UDPHS_IEN) Endpoint 13 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_14 (0x1u << 22) /**< \brief (UDPHS_IEN) Endpoint 14 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_EPT_15 (0x1u << 23) /**< \brief (UDPHS_IEN) Endpoint 15 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_DMA_1 (0x1u << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_DMA_2 (0x1u << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_DMA_3 (0x1u << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_DMA_4 (0x1u << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_DMA_5 (0x1u << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_DMA_6 (0x1u << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable (cleared upon USB reset) */\r
+#define UDPHS_IEN_DMA_7 (0x1u << 31) /**< \brief (UDPHS_IEN) DMA Channel 7 Interrupt Enable (cleared upon USB reset) */\r
+/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */\r
+#define UDPHS_INTSTA_SPEED (0x1u << 0) /**< \brief (UDPHS_INTSTA) Speed Status */\r
+#define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */\r
+#define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */\r
+#define UDPHS_INTSTA_INT_SOF (0x1u << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */\r
+#define UDPHS_INTSTA_ENDRESET (0x1u << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */\r
+#define UDPHS_INTSTA_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */\r
+#define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */\r
+#define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */\r
+#define UDPHS_INTSTA_EPT_0 (0x1u << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_1 (0x1u << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_2 (0x1u << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_3 (0x1u << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_4 (0x1u << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_5 (0x1u << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_6 (0x1u << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_7 (0x1u << 15) /**< \brief (UDPHS_INTSTA) Endpoint 7 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_8 (0x1u << 16) /**< \brief (UDPHS_INTSTA) Endpoint 8 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_9 (0x1u << 17) /**< \brief (UDPHS_INTSTA) Endpoint 9 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_10 (0x1u << 18) /**< \brief (UDPHS_INTSTA) Endpoint 10 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_11 (0x1u << 19) /**< \brief (UDPHS_INTSTA) Endpoint 11 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_12 (0x1u << 20) /**< \brief (UDPHS_INTSTA) Endpoint 12 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_13 (0x1u << 21) /**< \brief (UDPHS_INTSTA) Endpoint 13 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_14 (0x1u << 22) /**< \brief (UDPHS_INTSTA) Endpoint 14 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_EPT_15 (0x1u << 23) /**< \brief (UDPHS_INTSTA) Endpoint 15 Interrupt (cleared upon USB reset) */\r
+#define UDPHS_INTSTA_DMA_1 (0x1u << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */\r
+#define UDPHS_INTSTA_DMA_2 (0x1u << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */\r
+#define UDPHS_INTSTA_DMA_3 (0x1u << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */\r
+#define UDPHS_INTSTA_DMA_4 (0x1u << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */\r
+#define UDPHS_INTSTA_DMA_5 (0x1u << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */\r
+#define UDPHS_INTSTA_DMA_6 (0x1u << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */\r
+#define UDPHS_INTSTA_DMA_7 (0x1u << 31) /**< \brief (UDPHS_INTSTA) DMA Channel 7 Interrupt */\r
+/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */\r
+#define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */\r
+#define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */\r
+#define UDPHS_CLRINT_INT_SOF (0x1u << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */\r
+#define UDPHS_CLRINT_ENDRESET (0x1u << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */\r
+#define UDPHS_CLRINT_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */\r
+#define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */\r
+#define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */\r
+/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */\r
+#define UDPHS_EPTRST_EPT_0 (0x1u << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */\r
+#define UDPHS_EPTRST_EPT_1 (0x1u << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */\r
+#define UDPHS_EPTRST_EPT_2 (0x1u << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */\r
+#define UDPHS_EPTRST_EPT_3 (0x1u << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */\r
+#define UDPHS_EPTRST_EPT_4 (0x1u << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */\r
+#define UDPHS_EPTRST_EPT_5 (0x1u << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */\r
+#define UDPHS_EPTRST_EPT_6 (0x1u << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */\r
+#define UDPHS_EPTRST_EPT_7 (0x1u << 7) /**< \brief (UDPHS_EPTRST) Endpoint 7 Reset */\r
+#define UDPHS_EPTRST_EPT_8 (0x1u << 8) /**< \brief (UDPHS_EPTRST) Endpoint 8 Reset */\r
+#define UDPHS_EPTRST_EPT_9 (0x1u << 9) /**< \brief (UDPHS_EPTRST) Endpoint 9 Reset */\r
+#define UDPHS_EPTRST_EPT_10 (0x1u << 10) /**< \brief (UDPHS_EPTRST) Endpoint 10 Reset */\r
+#define UDPHS_EPTRST_EPT_11 (0x1u << 11) /**< \brief (UDPHS_EPTRST) Endpoint 11 Reset */\r
+#define UDPHS_EPTRST_EPT_12 (0x1u << 12) /**< \brief (UDPHS_EPTRST) Endpoint 12 Reset */\r
+#define UDPHS_EPTRST_EPT_13 (0x1u << 13) /**< \brief (UDPHS_EPTRST) Endpoint 13 Reset */\r
+#define UDPHS_EPTRST_EPT_14 (0x1u << 14) /**< \brief (UDPHS_EPTRST) Endpoint 14 Reset */\r
+#define UDPHS_EPTRST_EPT_15 (0x1u << 15) /**< \brief (UDPHS_EPTRST) Endpoint 15 Reset */\r
+/* -------- UDPHS_TSTSOFCNT : (UDPHS Offset: 0xD0) UDPHS Test SOF Counter Register -------- */\r
+#define UDPHS_TSTSOFCNT_SOFCNTMAX_Pos 0\r
+#define UDPHS_TSTSOFCNT_SOFCNTMAX_Msk (0x7fu << UDPHS_TSTSOFCNT_SOFCNTMAX_Pos) /**< \brief (UDPHS_TSTSOFCNT) SOF Counter Max Value */\r
+#define UDPHS_TSTSOFCNT_SOFCNTMAX(value) ((UDPHS_TSTSOFCNT_SOFCNTMAX_Msk & ((value) << UDPHS_TSTSOFCNT_SOFCNTMAX_Pos)))\r
+#define UDPHS_TSTSOFCNT_SOFCTLOAD (0x1u << 7) /**< \brief (UDPHS_TSTSOFCNT) SOF Counter Load */\r
+/* -------- UDPHS_TSTCNTA : (UDPHS Offset: 0xD4) UDPHS Test A Counter Register -------- */\r
+#define UDPHS_TSTCNTA_CNTAMAX_Pos 0\r
+#define UDPHS_TSTCNTA_CNTAMAX_Msk (0x7fffu << UDPHS_TSTCNTA_CNTAMAX_Pos) /**< \brief (UDPHS_TSTCNTA) A Counter Max Value */\r
+#define UDPHS_TSTCNTA_CNTAMAX(value) ((UDPHS_TSTCNTA_CNTAMAX_Msk & ((value) << UDPHS_TSTCNTA_CNTAMAX_Pos)))\r
+#define UDPHS_TSTCNTA_CNTALOAD (0x1u << 15) /**< \brief (UDPHS_TSTCNTA) A Counter Load */\r
+/* -------- UDPHS_TSTCNTB : (UDPHS Offset: 0xD8) UDPHS Test B Counter Register -------- */\r
+#define UDPHS_TSTCNTB_CNTBMAX_Pos 0\r
+#define UDPHS_TSTCNTB_CNTBMAX_Msk (0x7fffu << UDPHS_TSTCNTB_CNTBMAX_Pos) /**< \brief (UDPHS_TSTCNTB) B Counter Max Value */\r
+#define UDPHS_TSTCNTB_CNTBMAX(value) ((UDPHS_TSTCNTB_CNTBMAX_Msk & ((value) << UDPHS_TSTCNTB_CNTBMAX_Pos)))\r
+#define UDPHS_TSTCNTB_CNTBLOAD (0x1u << 15) /**< \brief (UDPHS_TSTCNTB) B Counter Load */\r
+/* -------- UDPHS_TSTMODEREG : (UDPHS Offset: 0xDC) UDPHS Test Mode Register -------- */\r
+#define UDPHS_TSTMODEREG_TSTMODE_Pos 1\r
+#define UDPHS_TSTMODEREG_TSTMODE_Msk (0x1fu << UDPHS_TSTMODEREG_TSTMODE_Pos) /**< \brief (UDPHS_TSTMODEREG) UDPHS Core TestModeReg */\r
+#define UDPHS_TSTMODEREG_TSTMODE(value) ((UDPHS_TSTMODEREG_TSTMODE_Msk & ((value) << UDPHS_TSTMODEREG_TSTMODE_Pos)))\r
+/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */\r
+#define UDPHS_TST_SPEED_CFG_Pos 0\r
+#define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) /**< \brief (UDPHS_TST) Speed Configuration */\r
+#define UDPHS_TST_SPEED_CFG(value) ((UDPHS_TST_SPEED_CFG_Msk & ((value) << UDPHS_TST_SPEED_CFG_Pos)))\r
+#define UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) /**< \brief (UDPHS_TST) Normal mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode. */\r
+#define UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) /**< \brief (UDPHS_TST) Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. */\r
+#define UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) /**< \brief (UDPHS_TST) Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. */\r
+#define UDPHS_TST_TST_J (0x1u << 2) /**< \brief (UDPHS_TST) Test J Mode */\r
+#define UDPHS_TST_TST_K (0x1u << 3) /**< \brief (UDPHS_TST) Test K Mode */\r
+#define UDPHS_TST_TST_PKT (0x1u << 4) /**< \brief (UDPHS_TST) Test Packet Mode */\r
+#define UDPHS_TST_OPMODE2 (0x1u << 5) /**< \brief (UDPHS_TST) OpMode2 */\r
+/* -------- UDPHS_VERSION : (UDPHS Offset: 0xFC) UDPHS Version Register -------- */\r
+#define UDPHS_VERSION_VERSION_Pos 0\r
+#define UDPHS_VERSION_VERSION_Msk (0xffffu << UDPHS_VERSION_VERSION_Pos) /**< \brief (UDPHS_VERSION) Version of the Hardware Module */\r
+#define UDPHS_VERSION_MFN_Pos 16\r
+#define UDPHS_VERSION_MFN_Msk (0x7u << UDPHS_VERSION_MFN_Pos) /**< \brief (UDPHS_VERSION) Metal Fix Number */\r
+/* -------- UDPHS_EPTCFG : (UDPHS Offset: N/A) UDPHS Endpoint Configuration Register -------- */\r
+#define UDPHS_EPTCFG_EPT_SIZE_Pos 0\r
+#define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Size (cleared upon USB reset) */\r
+#define UDPHS_EPTCFG_EPT_SIZE(value) ((UDPHS_EPTCFG_EPT_SIZE_Msk & ((value) << UDPHS_EPTCFG_EPT_SIZE_Pos)))\r
+#define UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) /**< \brief (UDPHS_EPTCFG) 8 bytes */\r
+#define UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) /**< \brief (UDPHS_EPTCFG) 16 bytes */\r
+#define UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) /**< \brief (UDPHS_EPTCFG) 32 bytes */\r
+#define UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) /**< \brief (UDPHS_EPTCFG) 64 bytes */\r
+#define UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) /**< \brief (UDPHS_EPTCFG) 128 bytes */\r
+#define UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) /**< \brief (UDPHS_EPTCFG) 256 bytes */\r
+#define UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) /**< \brief (UDPHS_EPTCFG) 512 bytes */\r
+#define UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) /**< \brief (UDPHS_EPTCFG) 1024 bytes */\r
+#define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) /**< \brief (UDPHS_EPTCFG) Endpoint Direction (cleared upon USB reset) */\r
+#define UDPHS_EPTCFG_EPT_TYPE_Pos 4\r
+#define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Type (cleared upon USB reset) */\r
+#define UDPHS_EPTCFG_EPT_TYPE(value) ((UDPHS_EPTCFG_EPT_TYPE_Msk & ((value) << UDPHS_EPTCFG_EPT_TYPE_Pos)))\r
+#define UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) /**< \brief (UDPHS_EPTCFG) Control endpoint */\r
+#define UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) /**< \brief (UDPHS_EPTCFG) Isochronous endpoint */\r
+#define UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) /**< \brief (UDPHS_EPTCFG) Bulk endpoint */\r
+#define UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) /**< \brief (UDPHS_EPTCFG) Interrupt endpoint */\r
+#define UDPHS_EPTCFG_BK_NUMBER_Pos 6\r
+#define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) /**< \brief (UDPHS_EPTCFG) Number of Banks (cleared upon USB reset) */\r
+#define UDPHS_EPTCFG_BK_NUMBER(value) ((UDPHS_EPTCFG_BK_NUMBER_Msk & ((value) << UDPHS_EPTCFG_BK_NUMBER_Pos)))\r
+#define UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) /**< \brief (UDPHS_EPTCFG) Zero bank, the endpoint is not mapped in memory */\r
+#define UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) /**< \brief (UDPHS_EPTCFG) One bank (bank 0) */\r
+#define UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) /**< \brief (UDPHS_EPTCFG) Double bank (Ping-Pong: bank0/bank1) */\r
+#define UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) /**< \brief (UDPHS_EPTCFG) Triple bank (bank0/bank1/bank2) */\r
+#define UDPHS_EPTCFG_NB_TRANS_Pos 8\r
+#define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) /**< \brief (UDPHS_EPTCFG) Number Of Transaction per Microframe (cleared upon USB reset) */\r
+#define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos)))\r
+#define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) /**< \brief (UDPHS_EPTCFG) Endpoint Mapped (cleared upon USB reset) */\r
+/* -------- UDPHS_EPTCTLENB : (UDPHS Offset: N/A) UDPHS Endpoint Control Enable Register -------- */\r
+#define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLENB) Endpoint Enable */\r
+#define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLENB) Packet Auto-Valid Enable */\r
+#define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLENB) Interrupts Disable DMA */\r
+#define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLENB) NYET Disable (Only for High Speed Bulk OUT endpoints) */\r
+#define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLENB) Overflow Error Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTLENB) Received OUT Data Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLENB) Transmitted IN Data Complete Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP */\r
+#define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLENB) NAKOUT Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLENB) Busy Bank Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLENB) Short Packet Send/Short Packet Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLENB) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */\r
+#define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLENB) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */\r
+#define UDPHS_EPTCTLENB_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Error Flow Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) ISO CRC Error/Number of Transaction Error Interrupt Enable */\r
+#define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) Bank Flush Error Interrupt Enable */\r
+/* -------- UDPHS_EPTCTLDIS : (UDPHS Offset: N/A) UDPHS Endpoint Control Disable Register -------- */\r
+#define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLDIS) Endpoint Disable */\r
+#define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLDIS) Packet Auto-Valid Disable */\r
+#define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLDIS) Interrupts Disable DMA */\r
+#define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLDIS) NYET Enable (Only for High Speed Bulk OUT endpoints) */\r
+#define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLDIS) Overflow Error Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTLDIS) Received OUT Data Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLDIS) Transmitted IN Data Complete Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLDIS) NAKOUT Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLDIS) Busy Bank Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLDIS) Short Packet Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLDIS) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */\r
+#define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLDIS) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */\r
+#define UDPHS_EPTCTLDIS_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Error Flow Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) ISO CRC Error/Number of Transaction Error Interrupt Disable */\r
+#define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) bank flush error Interrupt Disable */\r
+/* -------- UDPHS_EPTCTL : (UDPHS Offset: N/A) UDPHS Endpoint Control Register -------- */\r
+#define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTL) Endpoint Enable (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTL) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTL) Interrupt Disables DMA (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTL) NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTL) Overflow Error Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTL) Received OUT Data Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTL) Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTL) NAKOUT Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTL) Busy Bank Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTL) Short Packet Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTL) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTL) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Error Flow Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTL) ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) */\r
+#define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTL) Bank Flush Error Interrupt Enabled (cleared upon USB reset) */\r
+/* -------- UDPHS_EPTSETSTA : (UDPHS Offset: N/A) UDPHS Endpoint Set Status Register -------- */\r
+#define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSETSTA) Stall Handshake Request Set */\r
+#define UDPHS_EPTSETSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTSETSTA) KILL Bank Set (for IN Endpoint) */\r
+#define UDPHS_EPTSETSTA_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */\r
+#define UDPHS_EPTSETSTA_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */\r
+/* -------- UDPHS_EPTCLRSTA : (UDPHS Offset: N/A) UDPHS Endpoint Clear Status Register -------- */\r
+#define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTCLRSTA) Stall Handshake Request Clear */\r
+#define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) /**< \brief (UDPHS_EPTCLRSTA) Data Toggle Clear */\r
+#define UDPHS_EPTCLRSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCLRSTA) Received OUT Data Clear */\r
+#define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCLRSTA) Transmitted IN Data Complete Clear */\r
+#define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP Clear */\r
+#define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent Clear */\r
+#define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN Clear */\r
+#define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCLRSTA) NAKOUT Clear */\r
+#define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Error Flow Clear */\r
+#define UDPHS_EPTCLRSTA_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Number of Transaction Error Clear */\r
+#define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) Bank Flush Error Clear */\r
+/* -------- UDPHS_EPTSTA : (UDPHS Offset: N/A) UDPHS Endpoint Status Register -------- */\r
+#define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSTA) Stall Handshake Request (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6\r
+#define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) /**< \brief (UDPHS_EPTSTA) Toggle Sequencing (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) /**< \brief (UDPHS_EPTSTA) DATA0 */\r
+#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) /**< \brief (UDPHS_EPTSTA) DATA1 */\r
+#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) /**< \brief (UDPHS_EPTSTA) Reserved for High Bandwidth Isochronous Endpoint */\r
+#define UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) /**< \brief (UDPHS_EPTSTA) Reserved for High Bandwidth Isochronous Endpoint */\r
+#define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTSTA) Overflow Error (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTSTA) Transmitted IN Data Complete (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTSTA) NAK OUT (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_CURBK_CTLDIR_Pos 16\r
+#define UDPHS_EPTSTA_CURBK_CTLDIR_Msk (0x3u << UDPHS_EPTSTA_CURBK_CTLDIR_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18\r
+#define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) /**< \brief (UDPHS_EPTSTA) Busy Bank Number (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_BUSY_BANK_STA_0BUSYBANK (0x0u << 18) /**< \brief (UDPHS_EPTSTA) All banks are free */\r
+#define UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x1u << 18) /**< \brief (UDPHS_EPTSTA) 1 busy bank */\r
+#define UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x2u << 18) /**< \brief (UDPHS_EPTSTA) 2 busy banks */\r
+#define UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x3u << 18) /**< \brief (UDPHS_EPTSTA) 3 busy banks */\r
+#define UDPHS_EPTSTA_BYTE_COUNT_Pos 20\r
+#define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) /**< \brief (UDPHS_EPTSTA) UDPHS Byte Count (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTSTA) Short Packet (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Error Flow (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTSTA) CRC ISO Error/Number of Transaction Error (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTSTA) Bank Flush Error (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_CURBK_Pos 16\r
+#define UDPHS_EPTSTA_CURBK_Msk (0x3u << UDPHS_EPTSTA_CURBK_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank (cleared upon USB reset) */\r
+#define UDPHS_EPTSTA_CURBK_BANK0 (0x0u << 16) /**< \brief (UDPHS_EPTSTA) Bank 0 (or single bank) */\r
+#define UDPHS_EPTSTA_CURBK_BANK1 (0x1u << 16) /**< \brief (UDPHS_EPTSTA) Bank 1 */\r
+#define UDPHS_EPTSTA_CURBK_BANK2 (0x2u << 16) /**< \brief (UDPHS_EPTSTA) Bank 2 */\r
+/* -------- UDPHS_DMANXTDSC : (UDPHS Offset: N/A) UDPHS DMA Next Descriptor Address Register -------- */\r
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0\r
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UDPHS_DMANXTDSC) Next Descriptor Address */\r
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos)))\r
+/* -------- UDPHS_DMAADDRESS : (UDPHS Offset: N/A) UDPHS DMA Channel Address Register -------- */\r
+#define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0\r
+#define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) /**< \brief (UDPHS_DMAADDRESS) Buffer Address */\r
+#define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos)))\r
+/* -------- UDPHS_DMACONTROL : (UDPHS Offset: N/A) UDPHS DMA Channel Control Register -------- */\r
+#define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMACONTROL) (Channel Enable Command) */\r
+#define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UDPHS_DMACONTROL) Load Next Channel Transfer Descriptor Enable (Command) */\r
+#define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UDPHS_DMACONTROL) End of Transfer Enable (Control) */\r
+#define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UDPHS_DMACONTROL) End of Buffer Enable (Control) */\r
+#define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UDPHS_DMACONTROL) End of Transfer Interrupt Enable */\r
+#define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UDPHS_DMACONTROL) End of Buffer Interrupt Enable */\r
+#define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UDPHS_DMACONTROL) Descriptor Loaded Interrupt Enable */\r
+#define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UDPHS_DMACONTROL) Burst Lock Enable */\r
+#define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16\r
+#define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UDPHS_DMACONTROL) Buffer Byte Length (Write-only) */\r
+#define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos)))\r
+/* -------- UDPHS_DMASTATUS : (UDPHS Offset: N/A) UDPHS DMA Channel Status Register -------- */\r
+#define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMASTATUS) Channel Enable Status */\r
+#define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UDPHS_DMASTATUS) Channel Active Status */\r
+#define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UDPHS_DMASTATUS) End of Channel Transfer Status */\r
+#define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UDPHS_DMASTATUS) End of Channel Buffer Status */\r
+#define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UDPHS_DMASTATUS) Descriptor Loaded Status */\r
+#define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16\r
+#define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) /**< \brief (UDPHS_DMASTATUS) Buffer Byte Count */\r
+#define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_UDPHS_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_WDT_COMPONENT_\r
+#define _SAMA5D2_WDT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Watchdog Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_WDT Watchdog Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Wdt hardware registers */\r
+typedef struct {\r
+ __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */\r
+ __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */\r
+ __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */\r
+} Wdt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */\r
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */\r
+#define WDT_CR_LOCKMR (0x1u << 4) /**< \brief (WDT_CR) Lock Mode Register Write Access */\r
+#define WDT_CR_KEY_Pos 24\r
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */\r
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))\r
+#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */\r
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */\r
+#define WDT_MR_WDV_Pos 0\r
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */\r
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))\r
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */\r
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */\r
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */\r
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */\r
+#define WDT_MR_WDD_Pos 16\r
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */\r
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))\r
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */\r
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */\r
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */\r
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */\r
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_WDT_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D2_XDMAC_COMPONENT_\r
+#define _SAMA5D2_XDMAC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAMA5D2_XDMAC Extensible DMA Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief XdmacChid hardware registers */\r
+typedef struct {\r
+ __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */\r
+ __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */\r
+ __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */\r
+ __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */\r
+ __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */\r
+ __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */\r
+ __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */\r
+ __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */\r
+ __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */\r
+ __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */\r
+ __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */\r
+ __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */\r
+ __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */\r
+ __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */\r
+ __I uint32_t Reserved1[2];\r
+} XdmacChid;\r
+/** \brief Xdmac hardware registers */\r
+#define XDMACCHID_NUMBER 16\r
+typedef struct {\r
+ __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */\r
+ __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */\r
+ __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */\r
+ __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */\r
+ __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */\r
+ __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */\r
+ __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */\r
+ __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */\r
+ __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */\r
+ __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */\r
+ __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */\r
+ __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */\r
+ __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */\r
+ __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */\r
+ __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */\r
+ __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */\r
+ __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */\r
+ __I uint32_t Reserved1[3];\r
+ XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 15 */\r
+ __I uint32_t Reserved2[747];\r
+ __IO uint32_t XDMAC_VERSION; /**< \brief (Xdmac Offset: 0xFFC) XDMAC Version Register */\r
+} Xdmac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */\r
+#define XDMAC_GTYPE_NB_CH_Pos 0\r
+#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */\r
+#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)))\r
+#define XDMAC_GTYPE_FIFO_SZ_Pos 5\r
+#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */\r
+#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)))\r
+#define XDMAC_GTYPE_NB_REQ_Pos 16\r
+#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */\r
+#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)))\r
+/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */\r
+#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */\r
+#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */\r
+#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */\r
+#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */\r
+#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilobyte Enable */\r
+/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */\r
+#define XDMAC_GWAC_PW0_Pos 0\r
+#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */\r
+#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)))\r
+#define XDMAC_GWAC_PW1_Pos 4\r
+#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */\r
+#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)))\r
+#define XDMAC_GWAC_PW2_Pos 8\r
+#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */\r
+#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)))\r
+#define XDMAC_GWAC_PW3_Pos 12\r
+#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */\r
+#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)))\r
+/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */\r
+#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */\r
+#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */\r
+/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */\r
+#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */\r
+#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */\r
+/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */\r
+#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */\r
+#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */\r
+/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */\r
+#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */\r
+#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */\r
+/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */\r
+#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */\r
+#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */\r
+#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */\r
+#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */\r
+#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */\r
+#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */\r
+#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */\r
+#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */\r
+#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */\r
+#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */\r
+#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */\r
+#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */\r
+#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */\r
+#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */\r
+/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */\r
+#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */\r
+#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */\r
+#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */\r
+#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */\r
+#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */\r
+#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */\r
+#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */\r
+#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */\r
+#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */\r
+#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */\r
+#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */\r
+#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */\r
+#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */\r
+#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */\r
+/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */\r
+#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */\r
+#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */\r
+#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */\r
+#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */\r
+#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */\r
+#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */\r
+#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */\r
+#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */\r
+#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */\r
+#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */\r
+#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */\r
+#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */\r
+#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */\r
+#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */\r
+/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */\r
+#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */\r
+#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */\r
+#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */\r
+#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */\r
+#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */\r
+#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */\r
+#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */\r
+#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */\r
+#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */\r
+#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */\r
+#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */\r
+#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */\r
+#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */\r
+#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */\r
+/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */\r
+#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */\r
+#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */\r
+#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */\r
+#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */\r
+#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */\r
+#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */\r
+#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */\r
+#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */\r
+#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */\r
+#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */\r
+#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */\r
+#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */\r
+#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */\r
+#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */\r
+/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */\r
+#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */\r
+#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */\r
+/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */\r
+#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */\r
+#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */\r
+/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */\r
+#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */\r
+#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */\r
+/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */\r
+#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */\r
+#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */\r
+/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */\r
+#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */\r
+#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */\r
+/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */\r
+#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */\r
+#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */\r
+#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */\r
+#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */\r
+#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */\r
+#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */\r
+#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */\r
+/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */\r
+#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */\r
+#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */\r
+#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */\r
+#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */\r
+#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */\r
+#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */\r
+#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */\r
+/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */\r
+#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */\r
+#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */\r
+#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */\r
+#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */\r
+#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */\r
+#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */\r
+#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */\r
+/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */\r
+#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */\r
+#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */\r
+#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */\r
+#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */\r
+#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */\r
+#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */\r
+#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */\r
+/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */\r
+#define XDMAC_CSA_SA_Pos 0\r
+#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */\r
+#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)))\r
+/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */\r
+#define XDMAC_CDA_DA_Pos 0\r
+#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */\r
+#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)))\r
+/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */\r
+#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */\r
+#define XDMAC_CNDA_NDA_Pos 2\r
+#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */\r
+#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)))\r
+/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */\r
+#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */\r
+#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled. */\r
+#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled. */\r
+#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */\r
+#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */\r
+#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */\r
+#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */\r
+#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */\r
+#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */\r
+#define XDMAC_CNDC_NDVIEW_Pos 3\r
+#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */\r
+#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)))\r
+#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */\r
+#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */\r
+#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */\r
+#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */\r
+/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */\r
+#define XDMAC_CUBC_UBLEN_Pos 0\r
+#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */\r
+#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)))\r
+/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */\r
+#define XDMAC_CBC_BLEN_Pos 0\r
+#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */\r
+#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)))\r
+/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */\r
+#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */\r
+#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */\r
+#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */\r
+#define XDMAC_CC_MBSIZE_Pos 1\r
+#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */\r
+#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)))\r
+#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */\r
+#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */\r
+#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */\r
+#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */\r
+#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */\r
+#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer. */\r
+#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer. */\r
+#define XDMAC_CC_PROT (0x1u << 5) /**< \brief (XDMAC_CC) Channel x Protection */\r
+#define XDMAC_CC_PROT_SEC (0x0u << 5) /**< \brief (XDMAC_CC) Channel is secured. */\r
+#define XDMAC_CC_PROT_UNSEC (0x1u << 5) /**< \brief (XDMAC_CC) Channel is unsecured. */\r
+#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */\r
+#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */\r
+#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */\r
+#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */\r
+#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated. */\r
+#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */\r
+#define XDMAC_CC_CSIZE_Pos 8\r
+#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */\r
+#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)))\r
+#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */\r
+#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */\r
+#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */\r
+#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */\r
+#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */\r
+#define XDMAC_CC_DWIDTH_Pos 11\r
+#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */\r
+#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)))\r
+#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */\r
+#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */\r
+#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */\r
+#define XDMAC_CC_DWIDTH_DWORD (0x3u << 11) /**< \brief (XDMAC_CC) The data size is set to 64 bits */\r
+#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */\r
+#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0. */\r
+#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1. */\r
+#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */\r
+#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0. */\r
+#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1. */\r
+#define XDMAC_CC_SAM_Pos 16\r
+#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */\r
+#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)))\r
+#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */\r
+#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */\r
+#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */\r
+#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */\r
+#define XDMAC_CC_DAM_Pos 18\r
+#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */\r
+#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)))\r
+#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */\r
+#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */\r
+#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */\r
+#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */\r
+#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */\r
+#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */\r
+#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */\r
+#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */\r
+#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */\r
+#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */\r
+#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */\r
+#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */\r
+#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */\r
+#define XDMAC_CC_PERID_Pos 24\r
+#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Identifier */\r
+#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)))\r
+/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */\r
+#define XDMAC_CDS_MSP_SDS_MSP_Pos 0\r
+#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */\r
+#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)))\r
+#define XDMAC_CDS_MSP_DDS_MSP_Pos 16\r
+#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */\r
+#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)))\r
+/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */\r
+#define XDMAC_CSUS_SUBS_Pos 0\r
+#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */\r
+#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)))\r
+/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */\r
+#define XDMAC_CDUS_DUBS_Pos 0\r
+#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */\r
+#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)))\r
+/* -------- XDMAC_VERSION : (XDMAC Offset: 0xFFC) XDMAC Version Register -------- */\r
+#define XDMAC_VERSION_VERSION_Pos 0\r
+#define XDMAC_VERSION_VERSION_Msk (0xfffu << XDMAC_VERSION_VERSION_Pos) /**< \brief (XDMAC_VERSION) Version of the Hardware Module */\r
+#define XDMAC_VERSION_VERSION(value) ((XDMAC_VERSION_VERSION_Msk & ((value) << XDMAC_VERSION_VERSION_Pos)))\r
+#define XDMAC_VERSION_MFN_Pos 16\r
+#define XDMAC_VERSION_MFN_Msk (0x7u << XDMAC_VERSION_MFN_Pos) /**< \brief (XDMAC_VERSION) Metal Fix Number */\r
+#define XDMAC_VERSION_MFN(value) ((XDMAC_VERSION_MFN_Msk & ((value) << XDMAC_VERSION_MFN_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAMA5D2_XDMAC_COMPONENT_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D21_PIO_\r
+#define _SAMA5D21_PIO_\r
+\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PD19X1_AD0 (1u << 19) /**< \brief Adc signal: AD0 */\r
+#define PIO_PD20X1_AD1 (1u << 20) /**< \brief Adc signal: AD1 */\r
+#define PIO_PD29X1_AD10 (1u << 29) /**< \brief Adc signal: AD10 */\r
+#define PIO_PD30X1_AD11 (1u << 30) /**< \brief Adc signal: AD11 */\r
+#define PIO_PD21X1_AD2 (1u << 21) /**< \brief Adc signal: AD2 */\r
+#define PIO_PD22X1_AD3 (1u << 22) /**< \brief Adc signal: AD3 */\r
+#define PIO_PD23X1_AD4 (1u << 23) /**< \brief Adc signal: AD4 */\r
+#define PIO_PD24X1_AD5 (1u << 24) /**< \brief Adc signal: AD5 */\r
+#define PIO_PD25X1_AD6 (1u << 25) /**< \brief Adc signal: AD6 */\r
+#define PIO_PD26X1_AD7 (1u << 26) /**< \brief Adc signal: AD7 */\r
+#define PIO_PD27X1_AD8 (1u << 27) /**< \brief Adc signal: AD8 */\r
+#define PIO_PD28X1_AD9 (1u << 28) /**< \brief Adc signal: AD9 */\r
+#define PIO_PD31A_ADTRG (1u << 31) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for AIC peripheral ========== */\r
+#define PIO_PB4C_FIQ (1u << 4) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC8C_FIQ (1u << 8) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC9A_FIQ (1u << 9) /**< \brief Aic signal: FIQ */\r
+#define PIO_PD3B_FIQ (1u << 3) /**< \brief Aic signal: FIQ */\r
+#define PIO_PA12B_IRQ (1u << 12) /**< \brief Aic signal: IRQ */\r
+#define PIO_PA21A_IRQ (1u << 21) /**< \brief Aic signal: IRQ */\r
+#define PIO_PB3C_IRQ (1u << 3) /**< \brief Aic signal: IRQ */\r
+#define PIO_PD31C_IRQ (1u << 31) /**< \brief Aic signal: IRQ */\r
+/* ========== Pio definition for ARM peripheral ========== */\r
+#define PIO_PA26C_NTRST (1u << 26) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD10A_NTRST (1u << 10) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD18A_NTRST (1u << 18) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD31B_NTRST (1u << 31) /**< \brief Arm signal: NTRST */\r
+#define PIO_PA22C_TCK (1u << 22) /**< \brief Arm signal: TCK */\r
+#define PIO_PD6A_TCK (1u << 6) /**< \brief Arm signal: TCK */\r
+#define PIO_PD14A_TCK (1u << 14) /**< \brief Arm signal: TCK */\r
+#define PIO_PD27B_TCK (1u << 27) /**< \brief Arm signal: TCK */\r
+#define PIO_PA23C_TDI (1u << 23) /**< \brief Arm signal: TDI */\r
+#define PIO_PD7A_TDI (1u << 7) /**< \brief Arm signal: TDI */\r
+#define PIO_PD15A_TDI (1u << 15) /**< \brief Arm signal: TDI */\r
+#define PIO_PD28B_TDI (1u << 28) /**< \brief Arm signal: TDI */\r
+#define PIO_PA24C_TDO (1u << 24) /**< \brief Arm signal: TDO */\r
+#define PIO_PD8A_TDO (1u << 8) /**< \brief Arm signal: TDO */\r
+#define PIO_PD16A_TDO (1u << 16) /**< \brief Arm signal: TDO */\r
+#define PIO_PD29B_TDO (1u << 29) /**< \brief Arm signal: TDO */\r
+#define PIO_PA25C_TMS (1u << 25) /**< \brief Arm signal: TMS */\r
+#define PIO_PD9A_TMS (1u << 9) /**< \brief Arm signal: TMS */\r
+#define PIO_PD17A_TMS (1u << 17) /**< \brief Arm signal: TMS */\r
+#define PIO_PD30B_TMS (1u << 30) /**< \brief Arm signal: TMS */\r
+/* ========== Pio definition for CLASSD peripheral ========== */\r
+#define PIO_PA28F_CLASSD_L0 (1u << 28) /**< \brief Classd signal: CLASSD_L0 */\r
+#define PIO_PA29F_CLASSD_L1 (1u << 29) /**< \brief Classd signal: CLASSD_L1 */\r
+#define PIO_PA30F_CLASSD_L2 (1u << 30) /**< \brief Classd signal: CLASSD_L2 */\r
+#define PIO_PA31F_CLASSD_L3 (1u << 31) /**< \brief Classd signal: CLASSD_L3 */\r
+#define PIO_PB1F_CLASSD_R0 (1u << 1) /**< \brief Classd signal: CLASSD_R0 */\r
+#define PIO_PB2F_CLASSD_R1 (1u << 2) /**< \brief Classd signal: CLASSD_R1 */\r
+#define PIO_PB3F_CLASSD_R2 (1u << 3) /**< \brief Classd signal: CLASSD_R2 */\r
+#define PIO_PB4F_CLASSD_R3 (1u << 4) /**< \brief Classd signal: CLASSD_R3 */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PB11B_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB11B_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB12B_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC12F_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PB21B_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC21F_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PB22B_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC22F_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PB23B_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC23F_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PB24B_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PC24F_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PB25B_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PC25F_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PB26B_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PC26F_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PB27B_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PC27F_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PB28B_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PC28F_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PB29B_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PC29F_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PB30B_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC30F_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PB13B_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PC13F_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PB31B_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC31F_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PA10F_A21 (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA10F_NANDALE (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_A21 (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_NANDALE (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA11F_A22 (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA11F_NANDCLE (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_A22 (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_NANDCLE (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC0B_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PD0F_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC1B_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PD1F_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PC2B_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PD2F_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PB14B_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC14F_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PB15B_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC15F_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PB16B_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC16F_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PB17B_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC17F_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PB18B_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC18F_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PB19B_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC19F_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PB20B_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC20F_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PA0F_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA22B_D0 (1u << 22) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA1F_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA23B_D1 (1u << 23) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA15F_D10 (1u << 15) /**< \brief Ebi signal: D10 */\r
+#define PIO_PB5B_D10 (1u << 5) /**< \brief Ebi signal: D10 */\r
+#define PIO_PA16F_D11 (1u << 16) /**< \brief Ebi signal: D11 */\r
+#define PIO_PB6B_D11 (1u << 6) /**< \brief Ebi signal: D11 */\r
+#define PIO_PA17F_D12 (1u << 17) /**< \brief Ebi signal: D12 */\r
+#define PIO_PB7B_D12 (1u << 7) /**< \brief Ebi signal: D12 */\r
+#define PIO_PA18F_D13 (1u << 18) /**< \brief Ebi signal: D13 */\r
+#define PIO_PB8B_D13 (1u << 8) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA19F_D14 (1u << 19) /**< \brief Ebi signal: D14 */\r
+#define PIO_PB9B_D14 (1u << 9) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA20F_D15 (1u << 20) /**< \brief Ebi signal: D15 */\r
+#define PIO_PB10B_D15 (1u << 10) /**< \brief Ebi signal: D15 */\r
+#define PIO_PA2F_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA24B_D2 (1u << 24) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA3F_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA25B_D3 (1u << 25) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA4F_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA26B_D4 (1u << 26) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA5F_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA27B_D5 (1u << 27) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA6F_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA28B_D6 (1u << 28) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA7F_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA29B_D7 (1u << 29) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA13F_D8 (1u << 13) /**< \brief Ebi signal: D8 */\r
+#define PIO_PB3B_D8 (1u << 3) /**< \brief Ebi signal: D8 */\r
+#define PIO_PA14F_D9 (1u << 14) /**< \brief Ebi signal: D9 */\r
+#define PIO_PB4B_D9 (1u << 4) /**< \brief Ebi signal: D9 */\r
+#define PIO_PA21F_NANDRDY (1u << 21) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC8B_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PD8F_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC5B_NCS0 (1u << 5) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PD4F_NCS0 (1u << 4) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC6B_NCS1 (1u << 6) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PD5F_NCS1 (1u << 5) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PC7B_NCS2 (1u << 7) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PD6F_NCS2 (1u << 6) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PA9F_NCS3 (1u << 9) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA31B_NCS3 (1u << 31) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA12F_NRD (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PA12F_NANDOE (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NRD (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NANDOE (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PC3B_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PD3F_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PA8F_NWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA8F_NANDWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NANDWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PC4B_NWR1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PC4B_NBS1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NWR1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NBS1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+/* ========== Pio definition for FLEXCOM0 peripheral ========== */\r
+#define PIO_PB28C_FLEXCOM0_IO0 (1u << 28) /**< \brief Flexcom0 signal: FLEXCOM0_IO0 */\r
+#define PIO_PB29C_FLEXCOM0_IO1 (1u << 29) /**< \brief Flexcom0 signal: FLEXCOM0_IO1 */\r
+#define PIO_PB30C_FLEXCOM0_IO2 (1u << 30) /**< \brief Flexcom0 signal: FLEXCOM0_IO2 */\r
+#define PIO_PB31C_FLEXCOM0_IO3 (1u << 31) /**< \brief Flexcom0 signal: FLEXCOM0_IO3 */\r
+#define PIO_PC0C_FLEXCOM0_IO4 (1u << 0) /**< \brief Flexcom0 signal: FLEXCOM0_IO4 */\r
+/* ========== Pio definition for FLEXCOM1 peripheral ========== */\r
+#define PIO_PA24A_FLEXCOM1_IO0 (1u << 24) /**< \brief Flexcom1 signal: FLEXCOM1_IO0 */\r
+#define PIO_PA23A_FLEXCOM1_IO1 (1u << 23) /**< \brief Flexcom1 signal: FLEXCOM1_IO1 */\r
+#define PIO_PA22A_FLEXCOM1_IO2 (1u << 22) /**< \brief Flexcom1 signal: FLEXCOM1_IO2 */\r
+#define PIO_PA25A_FLEXCOM1_IO3 (1u << 25) /**< \brief Flexcom1 signal: FLEXCOM1_IO3 */\r
+#define PIO_PA26A_FLEXCOM1_IO4 (1u << 26) /**< \brief Flexcom1 signal: FLEXCOM1_IO4 */\r
+/* ========== Pio definition for FLEXCOM3 peripheral ========== */\r
+#define PIO_PA15E_FLEXCOM3_IO0 (1u << 15) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PB23E_FLEXCOM3_IO0 (1u << 23) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PC20E_FLEXCOM3_IO0 (1u << 20) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PA13E_FLEXCOM3_IO1 (1u << 13) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PB22E_FLEXCOM3_IO1 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PC19E_FLEXCOM3_IO1 (1u << 19) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PA14E_FLEXCOM3_IO2 (1u << 14) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PB21E_FLEXCOM3_IO2 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PC18E_FLEXCOM3_IO2 (1u << 18) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PA16E_FLEXCOM3_IO3 (1u << 16) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PB24E_FLEXCOM3_IO3 (1u << 24) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PC21E_FLEXCOM3_IO3 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PA17E_FLEXCOM3_IO4 (1u << 17) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PB25E_FLEXCOM3_IO4 (1u << 25) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PC22E_FLEXCOM3_IO4 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+/* ========== Pio definition for FLEXCOM4 peripheral ========== */\r
+#define PIO_PC28B_FLEXCOM4_IO0 (1u << 28) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD12B_FLEXCOM4_IO0 (1u << 12) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD21C_FLEXCOM4_IO0 (1u << 21) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PC29B_FLEXCOM4_IO1 (1u << 29) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD13B_FLEXCOM4_IO1 (1u << 13) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD22C_FLEXCOM4_IO1 (1u << 22) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PC30B_FLEXCOM4_IO2 (1u << 30) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD14B_FLEXCOM4_IO2 (1u << 14) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD23C_FLEXCOM4_IO2 (1u << 23) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PC31B_FLEXCOM4_IO3 (1u << 31) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD15B_FLEXCOM4_IO3 (1u << 15) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD24C_FLEXCOM4_IO3 (1u << 24) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD0B_FLEXCOM4_IO4 (1u << 0) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD16B_FLEXCOM4_IO4 (1u << 16) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD25C_FLEXCOM4_IO4 (1u << 25) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PB9F_GCOL (1u << 9) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PC23B_GCOL (1u << 23) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD4D_GCOL (1u << 4) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PB8F_GCRS (1u << 8) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PC22B_GCRS (1u << 22) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD3D_GCRS (1u << 3) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PB22F_GMDC (1u << 22) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PC18B_GMDC (1u << 18) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD17D_GMDC (1u << 17) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PB23F_GMDIO (1u << 23) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PC19B_GMDIO (1u << 19) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD18D_GMDIO (1u << 18) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PB18F_GRX0 (1u << 18) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PC14B_GRX0 (1u << 14) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD13D_GRX0 (1u << 13) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PB19F_GRX1 (1u << 19) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PC15B_GRX1 (1u << 15) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD14D_GRX1 (1u << 14) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PB10F_GRX2 (1u << 10) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PC24B_GRX2 (1u << 24) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD5D_GRX2 (1u << 5) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PB11F_GRX3 (1u << 11) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PC25B_GRX3 (1u << 25) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD6D_GRX3 (1u << 6) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PB7F_GRXCK (1u << 7) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PC20B_GRXCK (1u << 20) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD1D_GRXCK (1u << 1) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PB16F_GRXDV (1u << 16) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PC12B_GRXDV (1u << 12) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD11D_GRXDV (1u << 11) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PB17F_GRXER (1u << 17) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PC13B_GRXER (1u << 13) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD12D_GRXER (1u << 12) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB5F_GTSUCOMP (1u << 5) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PC9B_GTSUCOMP (1u << 9) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD0D_GTSUCOMP (1u << 0) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB20F_GTX0 (1u << 20) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PC16B_GTX0 (1u << 16) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD15D_GTX0 (1u << 15) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PB21F_GTX1 (1u << 21) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PC17B_GTX1 (1u << 17) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD16D_GTX1 (1u << 16) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PB12F_GTX2 (1u << 12) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PC26B_GTX2 (1u << 26) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD7D_GTX2 (1u << 7) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PB13F_GTX3 (1u << 13) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PC27B_GTX3 (1u << 27) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD8D_GTX3 (1u << 8) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PB14F_GTXCK (1u << 14) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PC10B_GTXCK (1u << 10) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD9D_GTXCK (1u << 9) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PB15F_GTXEN (1u << 15) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PC11B_GTXEN (1u << 11) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD10D_GTXEN (1u << 10) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PB6F_GTXER (1u << 6) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PC21B_GTXER (1u << 21) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PD2D_GTXER (1u << 2) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for I2SC0 peripheral ========== */\r
+#define PIO_PC1E_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PD19E_I2SC0_CK (1u << 19) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PC4E_I2SC0_DI0 (1u << 4) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PD22E_I2SC0_DI0 (1u << 22) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PC5E_I2SC0_DO0 (1u << 5) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PD23E_I2SC0_DO0 (1u << 23) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PC2E_I2SC0_MCK (1u << 2) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PD20E_I2SC0_MCK (1u << 20) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PC3E_I2SC0_WS (1u << 3) /**< \brief I2sc0 signal: I2SC0_WS */\r
+#define PIO_PD21E_I2SC0_WS (1u << 21) /**< \brief I2sc0 signal: I2SC0_WS */\r
+/* ========== Pio definition for I2SC1 peripheral ========== */\r
+#define PIO_PA15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PB15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PA17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PB17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PA18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PB18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PA14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PB14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PA16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+#define PIO_PB16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+/* ========== Pio definition for ISC peripheral ========== */\r
+#define PIO_PB26F_ISC_D0 (1u << 26) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PC9C_ISC_D0 (1u << 9) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PD7E_ISC_D0 (1u << 7) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PB27F_ISC_D1 (1u << 27) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PC10C_ISC_D1 (1u << 10) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PD8E_ISC_D1 (1u << 8) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PB24F_ISC_D10 (1u << 24) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PC19C_ISC_D10 (1u << 19) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD4E_ISC_D10 (1u << 4) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD18F_ISC_D10 (1u << 18) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PB25F_ISC_D11 (1u << 25) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PC20C_ISC_D11 (1u << 20) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD3E_ISC_D11 (1u << 3) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD19F_ISC_D11 (1u << 19) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PB28F_ISC_D2 (1u << 28) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PC11C_ISC_D2 (1u << 11) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PD9E_ISC_D2 (1u << 9) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PB29F_ISC_D3 (1u << 29) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PC12C_ISC_D3 (1u << 12) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PD10E_ISC_D3 (1u << 10) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PB30F_ISC_D4 (1u << 30) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PC13C_ISC_D4 (1u << 13) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD11E_ISC_D4 (1u << 11) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD12F_ISC_D4 (1u << 12) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PB31F_ISC_D5 (1u << 31) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC14C_ISC_D5 (1u << 14) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD12E_ISC_D5 (1u << 12) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD13F_ISC_D5 (1u << 13) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC0F_ISC_D6 (1u << 0) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC15C_ISC_D6 (1u << 15) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD13E_ISC_D6 (1u << 13) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD14F_ISC_D6 (1u << 14) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC1F_ISC_D7 (1u << 1) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC16C_ISC_D7 (1u << 16) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD14E_ISC_D7 (1u << 14) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD15F_ISC_D7 (1u << 15) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC2F_ISC_D8 (1u << 2) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC17C_ISC_D8 (1u << 17) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD6E_ISC_D8 (1u << 6) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD16F_ISC_D8 (1u << 16) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC3F_ISC_D9 (1u << 3) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC18C_ISC_D9 (1u << 18) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD5E_ISC_D9 (1u << 5) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD17F_ISC_D9 (1u << 17) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC8F_ISC_FIELD (1u << 8) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC25C_ISC_FIELD (1u << 25) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD18E_ISC_FIELD (1u << 18) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD23F_ISC_FIELD (1u << 23) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC6F_ISC_HSYNC (1u << 6) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC23C_ISC_HSYNC (1u << 23) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD17E_ISC_HSYNC (1u << 17) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD22F_ISC_HSYNC (1u << 22) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC7F_ISC_MCK (1u << 7) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC24C_ISC_MCK (1u << 24) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD2E_ISC_MCK (1u << 2) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD11F_ISC_MCK (1u << 11) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC4F_ISC_PCK (1u << 4) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC21C_ISC_PCK (1u << 21) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD15E_ISC_PCK (1u << 15) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD20F_ISC_PCK (1u << 20) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC5F_ISC_VSYNC (1u << 5) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PC22C_ISC_VSYNC (1u << 22) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD16E_ISC_VSYNC (1u << 16) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD21F_ISC_VSYNC (1u << 21) /**< \brief Isc signal: ISC_VSYNC */\r
+/* ========== Pio definition for LCDC peripheral ========== */\r
+#define PIO_PB11A_LCDDAT0 (1u << 11) /**< \brief Lcdc signal: LCDDAT0 */\r
+#define PIO_PB12A_LCDDAT1 (1u << 12) /**< \brief Lcdc signal: LCDDAT1 */\r
+#define PIO_PB21A_LCDDAT10 (1u << 21) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PC16A_LCDDAT10 (1u << 16) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PB22A_LCDDAT11 (1u << 22) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PC17A_LCDDAT11 (1u << 17) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PB23A_LCDDAT12 (1u << 23) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PC18A_LCDDAT12 (1u << 18) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PB24A_LCDDAT13 (1u << 24) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PC19A_LCDDAT13 (1u << 19) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PB25A_LCDDAT14 (1u << 25) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PC20A_LCDDAT14 (1u << 20) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PB26A_LCDDAT15 (1u << 26) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PC21A_LCDDAT15 (1u << 21) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PB27A_LCDDAT16 (1u << 27) /**< \brief Lcdc signal: LCDDAT16 */\r
+#define PIO_PB28A_LCDDAT17 (1u << 28) /**< \brief Lcdc signal: LCDDAT17 */\r
+#define PIO_PB29A_LCDDAT18 (1u << 29) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PC22A_LCDDAT18 (1u << 22) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PB30A_LCDDAT19 (1u << 30) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PC23A_LCDDAT19 (1u << 23) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PB13A_LCDDAT2 (1u << 13) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PC10A_LCDDAT2 (1u << 10) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PB31A_LCDDAT20 (1u << 31) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC24A_LCDDAT20 (1u << 24) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC0A_LCDDAT21 (1u << 0) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC25A_LCDDAT21 (1u << 25) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC1A_LCDDAT22 (1u << 1) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC26A_LCDDAT22 (1u << 26) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC2A_LCDDAT23 (1u << 2) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PC27A_LCDDAT23 (1u << 27) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PB14A_LCDDAT3 (1u << 14) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PC11A_LCDDAT3 (1u << 11) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PB15A_LCDDAT4 (1u << 15) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PC12A_LCDDAT4 (1u << 12) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PB16A_LCDDAT5 (1u << 16) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PC13A_LCDDAT5 (1u << 13) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PB17A_LCDDAT6 (1u << 17) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PC14A_LCDDAT6 (1u << 14) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PB18A_LCDDAT7 (1u << 18) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PC15A_LCDDAT7 (1u << 15) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PB19A_LCDDAT8 (1u << 19) /**< \brief Lcdc signal: LCDDAT8 */\r
+#define PIO_PB20A_LCDDAT9 (1u << 20) /**< \brief Lcdc signal: LCDDAT9 */\r
+#define PIO_PC8A_LCDDEN (1u << 8) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PD1A_LCDDEN (1u << 1) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PC4A_LCDDISP (1u << 4) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC29A_LCDDISP (1u << 29) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC6A_LCDHSYNC (1u << 6) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC31A_LCDHSYNC (1u << 31) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC7A_LCDPCK (1u << 7) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PD0A_LCDPCK (1u << 0) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PC3A_LCDPWM (1u << 3) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC28A_LCDPWM (1u << 28) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC5A_LCDVSYNC (1u << 5) /**< \brief Lcdc signal: LCDVSYNC */\r
+#define PIO_PC30A_LCDVSYNC (1u << 30) /**< \brief Lcdc signal: LCDVSYNC */\r
+/* ========== Pio definition for PDMIC peripheral ========== */\r
+#define PIO_PB12D_PDMIC_CLK (1u << 12) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB27D_PDMIC_CLK (1u << 27) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB11D_PDMIC_DAT (1u << 11) /**< \brief Pdmic signal: PDMIC_DAT */\r
+#define PIO_PB26D_PDMIC_DAT (1u << 26) /**< \brief Pdmic signal: PDMIC_DAT */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PC8D_PCK0 (1u << 8) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD19A_PCK0 (1u << 19) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD31E_PCK0 (1u << 31) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13C_PCK1 (1u << 13) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PB20E_PCK1 (1u << 20) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PC27C_PCK1 (1u << 27) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PD6B_PCK1 (1u << 6) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK2 (1u << 21) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PC28C_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD11B_PCK2 (1u << 11) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PB3D_PWMEXTRG0 (1u << 3) /**< \brief Pwm signal: PWMEXTRG0 */\r
+#define PIO_PB10C_PWMEXTRG1 (1u << 10) /**< \brief Pwm signal: PWMEXTRG1 */\r
+#define PIO_PB2D_PWMFI0 (1u << 2) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PB9C_PWMFI1 (1u << 9) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PA30D_PWMH0 (1u << 30) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0D_PWMH1 (1u << 0) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB5C_PWMH2 (1u << 5) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB7C_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA31D_PWML0 (1u << 31) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB1D_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB6C_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB8C_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for QSPI0 peripheral ========== */\r
+#define PIO_PA1B_QSPI0_CS (1u << 1) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA15C_QSPI0_CS (1u << 15) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA23F_QSPI0_CS (1u << 23) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA2B_QSPI0_IO0 (1u << 2) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA16C_QSPI0_IO0 (1u << 16) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA24F_QSPI0_IO0 (1u << 24) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA3B_QSPI0_IO1 (1u << 3) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA17C_QSPI0_IO1 (1u << 17) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA25F_QSPI0_IO1 (1u << 25) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA4B_QSPI0_IO2 (1u << 4) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA18C_QSPI0_IO2 (1u << 18) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA26F_QSPI0_IO2 (1u << 26) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA5B_QSPI0_IO3 (1u << 5) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA19C_QSPI0_IO3 (1u << 19) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA27F_QSPI0_IO3 (1u << 27) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA0B_QSPI0_SCK (1u << 0) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA14C_QSPI0_SCK (1u << 14) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA22F_QSPI0_SCK (1u << 22) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+/* ========== Pio definition for QSPI1 peripheral ========== */\r
+#define PIO_PA11B_QSPI1_CS (1u << 11) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB6D_QSPI1_CS (1u << 6) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB15E_QSPI1_CS (1u << 15) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PA7B_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB7D_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB16E_QSPI1_IO0 (1u << 16) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PA8B_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB8D_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB17E_QSPI1_IO1 (1u << 17) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PA9B_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB9D_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB18E_QSPI1_IO2 (1u << 18) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PA10B_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB10D_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB19E_QSPI1_IO3 (1u << 19) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PA6B_QSPI1_SCK (1u << 6) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB5D_QSPI1_SCK (1u << 5) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB14E_QSPI1_SCK (1u << 14) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+/* ========== Pio definition for SDMMC0 peripheral ========== */\r
+#define PIO_PA30E_SDMMC0_CD (1u << 30) /**< \brief Sdmmc0 signal: SDMMC0_CD */\r
+#define PIO_PA27E_SDMMC0_RSTN (1u << 27) /**< \brief Sdmmc0 signal: SDMMC0_RSTN */\r
+#define PIO_PA22E_SDMMC0_CK (1u << 22) /**< \brief Sdmmc0 signal: SDMMC0_CK */\r
+#define PIO_PA28E_SDMMC0_CMD (1u << 28) /**< \brief Sdmmc0 signal: SDMMC0_CMD */\r
+#define PIO_PA29E_SDMMC0_WP (1u << 29) /**< \brief Sdmmc0 signal: SDMMC0_WP */\r
+#define PIO_PA18E_SDMMC0_DAT0 (1u << 18) /**< \brief Sdmmc0 signal: SDMMC0_DAT0 */\r
+#define PIO_PA19E_SDMMC0_DAT1 (1u << 19) /**< \brief Sdmmc0 signal: SDMMC0_DAT1 */\r
+#define PIO_PA20E_SDMMC0_DAT2 (1u << 20) /**< \brief Sdmmc0 signal: SDMMC0_DAT2 */\r
+#define PIO_PA21E_SDMMC0_DAT3 (1u << 21) /**< \brief Sdmmc0 signal: SDMMC0_DAT3 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA16A_SPI0_MISO (1u << 16) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA31C_SPI0_MISO (1u << 31) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA15A_SPI0_MOSI (1u << 15) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB0C_SPI0_MOSI (1u << 0) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA17A_SPI0_NPCS0 (1u << 17) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA30C_SPI0_NPCS0 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA18A_SPI0_NPCS1 (1u << 18) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA29C_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA19A_SPI0_NPCS2 (1u << 19) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA27C_SPI0_NPCS2 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA20A_SPI0_NPCS3 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA28C_SPI0_NPCS3 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA14A_SPI0_SPCK (1u << 14) /**< \brief Spi0 signal: SPI0_SPCK */\r
+#define PIO_PB1C_SPI0_SPCK (1u << 1) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PA24D_SPI1_MISO (1u << 24) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC3D_SPI1_MISO (1u << 3) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PD27A_SPI1_MISO (1u << 27) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PA23D_SPI1_MOSI (1u << 23) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC2D_SPI1_MOSI (1u << 2) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PD26A_SPI1_MOSI (1u << 26) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PA25D_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC4D_SPI1_NPCS0 (1u << 4) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PD28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PA26D_SPI1_NPCS1 (1u << 26) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC5D_SPI1_NPCS1 (1u << 5) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PA27D_SPI1_NPCS2 (1u << 27) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC6D_SPI1_NPCS2 (1u << 6) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD30A_SPI1_NPCS2 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PA28D_SPI1_NPCS3 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC7D_SPI1_NPCS3 (1u << 7) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PA22D_SPI1_SPCK (1u << 22) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PC1D_SPI1_SPCK (1u << 1) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PD25A_SPI1_SPCK (1u << 25) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC0 peripheral ========== */\r
+#define PIO_PB23C_RD0 (1u << 23) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PC15E_RD0 (1u << 15) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PB25C_RF0 (1u << 25) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PC17E_RF0 (1u << 17) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PB24C_RK0 (1u << 24) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PC16E_RK0 (1u << 16) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PB22C_TD0 (1u << 22) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PC14E_TD0 (1u << 14) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PB21C_TF0 (1u << 21) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PC13E_TF0 (1u << 13) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PB20C_TK0 (1u << 20) /**< \brief Ssc0 signal: TK0 */\r
+#define PIO_PC12E_TK0 (1u << 12) /**< \brief Ssc0 signal: TK0 */\r
+/* ========== Pio definition for SSC1 peripheral ========== */\r
+#define PIO_PA17B_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PB17C_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PA19B_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PB19C_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PA18B_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PB18C_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PA16B_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PB16C_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PA15B_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PB15C_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PA14B_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+#define PIO_PB14C_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA21D_TCLK0 (1u << 21) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA29A_TCLK1 (1u << 29) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PC5C_TCLK1 (1u << 5) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PD13A_TCLK1 (1u << 13) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PB5A_TCLK2 (1u << 5) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB24D_TCLK2 (1u << 24) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PD22A_TCLK2 (1u << 22) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA19D_TIOA0 (1u << 19) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA27A_TIOA1 (1u << 27) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PC3C_TIOA1 (1u << 3) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PD11A_TIOA1 (1u << 11) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PB6A_TIOA2 (1u << 6) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB22D_TIOA2 (1u << 22) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PD20A_TIOA2 (1u << 20) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA20D_TIOB0 (1u << 20) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA28A_TIOB1 (1u << 28) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PC4C_TIOB1 (1u << 4) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PD12A_TIOB1 (1u << 12) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PB7A_TIOB2 (1u << 7) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PB23D_TIOB2 (1u << 23) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PD21A_TIOB2 (1u << 21) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PB8A_TCLK3 (1u << 8) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PB21D_TCLK3 (1u << 21) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PD31D_TCLK3 (1u << 31) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PA8D_TCLK5 (1u << 8) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB30D_TCLK5 (1u << 30) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB19D_TIOA3 (1u << 19) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PD29D_TIOA3 (1u << 29) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PA9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PA6D_TIOA5 (1u << 6) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB28D_TIOA5 (1u << 28) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB20D_TIOB3 (1u << 20) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PD30D_TIOB3 (1u << 30) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PA10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PA7D_TIOB5 (1u << 7) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PB29D_TIOB5 (1u << 29) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWIHS0 peripheral ========== */\r
+#define PIO_PC0D_TWCK0 (1u << 0) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PC28E_TWCK0 (1u << 28) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD22B_TWCK0 (1u << 22) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD30E_TWCK0 (1u << 30) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PB31D_TWD0 (1u << 31) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PC27E_TWD0 (1u << 27) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD21B_TWD0 (1u << 21) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD29E_TWD0 (1u << 29) /**< \brief Twihs0 signal: TWD0 */\r
+/* ========== Pio definition for TWIHS1 peripheral ========== */\r
+#define PIO_PC7C_TWCK1 (1u << 7) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD20B_TWCK1 (1u << 20) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PC6C_TWD1 (1u << 6) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD19B_TWD1 (1u << 19) /**< \brief Twihs1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PB26C_URXD0 (1u << 26) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PB27C_UTXD0 (1u << 27) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PC7E_URXD1 (1u << 7) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PD2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PC8E_UTXD1 (1u << 8) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD4B_URXD2 (1u << 4) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD19C_URXD2 (1u << 19) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD23A_URXD2 (1u << 23) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD5B_UTXD2 (1u << 5) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD20C_UTXD2 (1u << 20) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD24A_UTXD2 (1u << 24) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PB11C_URXD3 (1u << 11) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC12D_URXD3 (1u << 12) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC31C_URXD3 (1u << 31) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PB12C_UTXD3 (1u << 12) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PC13D_UTXD3 (1u << 13) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD0C_UTXD3 (1u << 0) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PB3A_URXD4 (1u << 3) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PB4A_UTXD4 (1u << 4) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+\r
+#endif /* _SAMA5D21_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D22_PIO_\r
+#define _SAMA5D22_PIO_\r
+\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PD19X1_AD0 (1u << 19) /**< \brief Adc signal: AD0 */\r
+#define PIO_PD20X1_AD1 (1u << 20) /**< \brief Adc signal: AD1 */\r
+#define PIO_PD29X1_AD10 (1u << 29) /**< \brief Adc signal: AD10 */\r
+#define PIO_PD30X1_AD11 (1u << 30) /**< \brief Adc signal: AD11 */\r
+#define PIO_PD21X1_AD2 (1u << 21) /**< \brief Adc signal: AD2 */\r
+#define PIO_PD22X1_AD3 (1u << 22) /**< \brief Adc signal: AD3 */\r
+#define PIO_PD23X1_AD4 (1u << 23) /**< \brief Adc signal: AD4 */\r
+#define PIO_PD24X1_AD5 (1u << 24) /**< \brief Adc signal: AD5 */\r
+#define PIO_PD25X1_AD6 (1u << 25) /**< \brief Adc signal: AD6 */\r
+#define PIO_PD26X1_AD7 (1u << 26) /**< \brief Adc signal: AD7 */\r
+#define PIO_PD27X1_AD8 (1u << 27) /**< \brief Adc signal: AD8 */\r
+#define PIO_PD28X1_AD9 (1u << 28) /**< \brief Adc signal: AD9 */\r
+#define PIO_PD31A_ADTRG (1u << 31) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for AIC peripheral ========== */\r
+#define PIO_PB4C_FIQ (1u << 4) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC8C_FIQ (1u << 8) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC9A_FIQ (1u << 9) /**< \brief Aic signal: FIQ */\r
+#define PIO_PD3B_FIQ (1u << 3) /**< \brief Aic signal: FIQ */\r
+#define PIO_PA12B_IRQ (1u << 12) /**< \brief Aic signal: IRQ */\r
+#define PIO_PA21A_IRQ (1u << 21) /**< \brief Aic signal: IRQ */\r
+#define PIO_PB3C_IRQ (1u << 3) /**< \brief Aic signal: IRQ */\r
+#define PIO_PD31C_IRQ (1u << 31) /**< \brief Aic signal: IRQ */\r
+/* ========== Pio definition for ARM peripheral ========== */\r
+#define PIO_PA26C_NTRST (1u << 26) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD10A_NTRST (1u << 10) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD18A_NTRST (1u << 18) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD31B_NTRST (1u << 31) /**< \brief Arm signal: NTRST */\r
+#define PIO_PA22C_TCK (1u << 22) /**< \brief Arm signal: TCK */\r
+#define PIO_PD6A_TCK (1u << 6) /**< \brief Arm signal: TCK */\r
+#define PIO_PD14A_TCK (1u << 14) /**< \brief Arm signal: TCK */\r
+#define PIO_PD27B_TCK (1u << 27) /**< \brief Arm signal: TCK */\r
+#define PIO_PA23C_TDI (1u << 23) /**< \brief Arm signal: TDI */\r
+#define PIO_PD7A_TDI (1u << 7) /**< \brief Arm signal: TDI */\r
+#define PIO_PD15A_TDI (1u << 15) /**< \brief Arm signal: TDI */\r
+#define PIO_PD28B_TDI (1u << 28) /**< \brief Arm signal: TDI */\r
+#define PIO_PA24C_TDO (1u << 24) /**< \brief Arm signal: TDO */\r
+#define PIO_PD8A_TDO (1u << 8) /**< \brief Arm signal: TDO */\r
+#define PIO_PD16A_TDO (1u << 16) /**< \brief Arm signal: TDO */\r
+#define PIO_PD29B_TDO (1u << 29) /**< \brief Arm signal: TDO */\r
+#define PIO_PA25C_TMS (1u << 25) /**< \brief Arm signal: TMS */\r
+#define PIO_PD9A_TMS (1u << 9) /**< \brief Arm signal: TMS */\r
+#define PIO_PD17A_TMS (1u << 17) /**< \brief Arm signal: TMS */\r
+#define PIO_PD30B_TMS (1u << 30) /**< \brief Arm signal: TMS */\r
+/* ========== Pio definition for CLASSD peripheral ========== */\r
+#define PIO_PA28F_CLASSD_L0 (1u << 28) /**< \brief Classd signal: CLASSD_L0 */\r
+#define PIO_PA29F_CLASSD_L1 (1u << 29) /**< \brief Classd signal: CLASSD_L1 */\r
+#define PIO_PA30F_CLASSD_L2 (1u << 30) /**< \brief Classd signal: CLASSD_L2 */\r
+#define PIO_PA31F_CLASSD_L3 (1u << 31) /**< \brief Classd signal: CLASSD_L3 */\r
+#define PIO_PB1F_CLASSD_R0 (1u << 1) /**< \brief Classd signal: CLASSD_R0 */\r
+#define PIO_PB2F_CLASSD_R1 (1u << 2) /**< \brief Classd signal: CLASSD_R1 */\r
+#define PIO_PB3F_CLASSD_R2 (1u << 3) /**< \brief Classd signal: CLASSD_R2 */\r
+#define PIO_PB4F_CLASSD_R3 (1u << 4) /**< \brief Classd signal: CLASSD_R3 */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PB11B_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB11B_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB12B_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC12F_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PB21B_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC21F_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PB22B_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC22F_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PB23B_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC23F_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PB24B_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PC24F_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PB25B_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PC25F_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PB26B_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PC26F_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PB27B_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PC27F_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PB28B_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PC28F_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PB29B_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PC29F_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PB30B_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC30F_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PB13B_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PC13F_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PB31B_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC31F_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PA10F_A21 (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA10F_NANDALE (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_A21 (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_NANDALE (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA11F_A22 (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA11F_NANDCLE (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_A22 (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_NANDCLE (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC0B_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PD0F_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC1B_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PD1F_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PC2B_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PD2F_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PB14B_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC14F_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PB15B_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC15F_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PB16B_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC16F_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PB17B_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC17F_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PB18B_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC18F_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PB19B_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC19F_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PB20B_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC20F_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PA0F_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA22B_D0 (1u << 22) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA1F_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA23B_D1 (1u << 23) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA15F_D10 (1u << 15) /**< \brief Ebi signal: D10 */\r
+#define PIO_PB5B_D10 (1u << 5) /**< \brief Ebi signal: D10 */\r
+#define PIO_PA16F_D11 (1u << 16) /**< \brief Ebi signal: D11 */\r
+#define PIO_PB6B_D11 (1u << 6) /**< \brief Ebi signal: D11 */\r
+#define PIO_PA17F_D12 (1u << 17) /**< \brief Ebi signal: D12 */\r
+#define PIO_PB7B_D12 (1u << 7) /**< \brief Ebi signal: D12 */\r
+#define PIO_PA18F_D13 (1u << 18) /**< \brief Ebi signal: D13 */\r
+#define PIO_PB8B_D13 (1u << 8) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA19F_D14 (1u << 19) /**< \brief Ebi signal: D14 */\r
+#define PIO_PB9B_D14 (1u << 9) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA20F_D15 (1u << 20) /**< \brief Ebi signal: D15 */\r
+#define PIO_PB10B_D15 (1u << 10) /**< \brief Ebi signal: D15 */\r
+#define PIO_PA2F_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA24B_D2 (1u << 24) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA3F_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA25B_D3 (1u << 25) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA4F_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA26B_D4 (1u << 26) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA5F_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA27B_D5 (1u << 27) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA6F_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA28B_D6 (1u << 28) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA7F_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA29B_D7 (1u << 29) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA13F_D8 (1u << 13) /**< \brief Ebi signal: D8 */\r
+#define PIO_PB3B_D8 (1u << 3) /**< \brief Ebi signal: D8 */\r
+#define PIO_PA14F_D9 (1u << 14) /**< \brief Ebi signal: D9 */\r
+#define PIO_PB4B_D9 (1u << 4) /**< \brief Ebi signal: D9 */\r
+#define PIO_PA21F_NANDRDY (1u << 21) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC8B_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PD8F_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC5B_NCS0 (1u << 5) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PD4F_NCS0 (1u << 4) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC6B_NCS1 (1u << 6) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PD5F_NCS1 (1u << 5) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PC7B_NCS2 (1u << 7) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PD6F_NCS2 (1u << 6) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PA9F_NCS3 (1u << 9) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA31B_NCS3 (1u << 31) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA12F_NRD (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PA12F_NANDOE (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NRD (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NANDOE (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PC3B_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PD3F_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PA8F_NWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA8F_NANDWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NANDWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PC4B_NWR1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PC4B_NBS1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NWR1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NBS1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+/* ========== Pio definition for FLEXCOM0 peripheral ========== */\r
+#define PIO_PB28C_FLEXCOM0_IO0 (1u << 28) /**< \brief Flexcom0 signal: FLEXCOM0_IO0 */\r
+#define PIO_PB29C_FLEXCOM0_IO1 (1u << 29) /**< \brief Flexcom0 signal: FLEXCOM0_IO1 */\r
+#define PIO_PB30C_FLEXCOM0_IO2 (1u << 30) /**< \brief Flexcom0 signal: FLEXCOM0_IO2 */\r
+#define PIO_PB31C_FLEXCOM0_IO3 (1u << 31) /**< \brief Flexcom0 signal: FLEXCOM0_IO3 */\r
+#define PIO_PC0C_FLEXCOM0_IO4 (1u << 0) /**< \brief Flexcom0 signal: FLEXCOM0_IO4 */\r
+/* ========== Pio definition for FLEXCOM1 peripheral ========== */\r
+#define PIO_PA24A_FLEXCOM1_IO0 (1u << 24) /**< \brief Flexcom1 signal: FLEXCOM1_IO0 */\r
+#define PIO_PA23A_FLEXCOM1_IO1 (1u << 23) /**< \brief Flexcom1 signal: FLEXCOM1_IO1 */\r
+#define PIO_PA22A_FLEXCOM1_IO2 (1u << 22) /**< \brief Flexcom1 signal: FLEXCOM1_IO2 */\r
+#define PIO_PA25A_FLEXCOM1_IO3 (1u << 25) /**< \brief Flexcom1 signal: FLEXCOM1_IO3 */\r
+#define PIO_PA26A_FLEXCOM1_IO4 (1u << 26) /**< \brief Flexcom1 signal: FLEXCOM1_IO4 */\r
+/* ========== Pio definition for FLEXCOM3 peripheral ========== */\r
+#define PIO_PA15E_FLEXCOM3_IO0 (1u << 15) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PB23E_FLEXCOM3_IO0 (1u << 23) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PC20E_FLEXCOM3_IO0 (1u << 20) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PA13E_FLEXCOM3_IO1 (1u << 13) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PB22E_FLEXCOM3_IO1 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PC19E_FLEXCOM3_IO1 (1u << 19) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PA14E_FLEXCOM3_IO2 (1u << 14) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PB21E_FLEXCOM3_IO2 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PC18E_FLEXCOM3_IO2 (1u << 18) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PA16E_FLEXCOM3_IO3 (1u << 16) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PB24E_FLEXCOM3_IO3 (1u << 24) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PC21E_FLEXCOM3_IO3 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PA17E_FLEXCOM3_IO4 (1u << 17) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PB25E_FLEXCOM3_IO4 (1u << 25) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PC22E_FLEXCOM3_IO4 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+/* ========== Pio definition for FLEXCOM4 peripheral ========== */\r
+#define PIO_PC28B_FLEXCOM4_IO0 (1u << 28) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD12B_FLEXCOM4_IO0 (1u << 12) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD21C_FLEXCOM4_IO0 (1u << 21) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PC29B_FLEXCOM4_IO1 (1u << 29) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD13B_FLEXCOM4_IO1 (1u << 13) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD22C_FLEXCOM4_IO1 (1u << 22) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PC30B_FLEXCOM4_IO2 (1u << 30) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD14B_FLEXCOM4_IO2 (1u << 14) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD23C_FLEXCOM4_IO2 (1u << 23) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PC31B_FLEXCOM4_IO3 (1u << 31) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD15B_FLEXCOM4_IO3 (1u << 15) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD24C_FLEXCOM4_IO3 (1u << 24) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD0B_FLEXCOM4_IO4 (1u << 0) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD16B_FLEXCOM4_IO4 (1u << 16) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD25C_FLEXCOM4_IO4 (1u << 25) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PB9F_GCOL (1u << 9) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PC23B_GCOL (1u << 23) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD4D_GCOL (1u << 4) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PB8F_GCRS (1u << 8) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PC22B_GCRS (1u << 22) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD3D_GCRS (1u << 3) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PB22F_GMDC (1u << 22) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PC18B_GMDC (1u << 18) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD17D_GMDC (1u << 17) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PB23F_GMDIO (1u << 23) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PC19B_GMDIO (1u << 19) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD18D_GMDIO (1u << 18) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PB18F_GRX0 (1u << 18) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PC14B_GRX0 (1u << 14) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD13D_GRX0 (1u << 13) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PB19F_GRX1 (1u << 19) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PC15B_GRX1 (1u << 15) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD14D_GRX1 (1u << 14) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PB10F_GRX2 (1u << 10) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PC24B_GRX2 (1u << 24) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD5D_GRX2 (1u << 5) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PB11F_GRX3 (1u << 11) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PC25B_GRX3 (1u << 25) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD6D_GRX3 (1u << 6) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PB7F_GRXCK (1u << 7) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PC20B_GRXCK (1u << 20) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD1D_GRXCK (1u << 1) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PB16F_GRXDV (1u << 16) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PC12B_GRXDV (1u << 12) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD11D_GRXDV (1u << 11) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PB17F_GRXER (1u << 17) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PC13B_GRXER (1u << 13) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD12D_GRXER (1u << 12) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB5F_GTSUCOMP (1u << 5) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PC9B_GTSUCOMP (1u << 9) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD0D_GTSUCOMP (1u << 0) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB20F_GTX0 (1u << 20) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PC16B_GTX0 (1u << 16) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD15D_GTX0 (1u << 15) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PB21F_GTX1 (1u << 21) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PC17B_GTX1 (1u << 17) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD16D_GTX1 (1u << 16) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PB12F_GTX2 (1u << 12) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PC26B_GTX2 (1u << 26) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD7D_GTX2 (1u << 7) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PB13F_GTX3 (1u << 13) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PC27B_GTX3 (1u << 27) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD8D_GTX3 (1u << 8) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PB14F_GTXCK (1u << 14) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PC10B_GTXCK (1u << 10) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD9D_GTXCK (1u << 9) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PB15F_GTXEN (1u << 15) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PC11B_GTXEN (1u << 11) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD10D_GTXEN (1u << 10) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PB6F_GTXER (1u << 6) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PC21B_GTXER (1u << 21) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PD2D_GTXER (1u << 2) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for I2SC0 peripheral ========== */\r
+#define PIO_PC1E_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PD19E_I2SC0_CK (1u << 19) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PC4E_I2SC0_DI0 (1u << 4) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PD22E_I2SC0_DI0 (1u << 22) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PC5E_I2SC0_DO0 (1u << 5) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PD23E_I2SC0_DO0 (1u << 23) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PC2E_I2SC0_MCK (1u << 2) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PD20E_I2SC0_MCK (1u << 20) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PC3E_I2SC0_WS (1u << 3) /**< \brief I2sc0 signal: I2SC0_WS */\r
+#define PIO_PD21E_I2SC0_WS (1u << 21) /**< \brief I2sc0 signal: I2SC0_WS */\r
+/* ========== Pio definition for I2SC1 peripheral ========== */\r
+#define PIO_PA15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PB15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PA17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PB17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PA18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PB18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PA14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PB14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PA16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+#define PIO_PB16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+/* ========== Pio definition for ISC peripheral ========== */\r
+#define PIO_PB26F_ISC_D0 (1u << 26) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PC9C_ISC_D0 (1u << 9) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PD7E_ISC_D0 (1u << 7) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PB27F_ISC_D1 (1u << 27) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PC10C_ISC_D1 (1u << 10) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PD8E_ISC_D1 (1u << 8) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PB24F_ISC_D10 (1u << 24) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PC19C_ISC_D10 (1u << 19) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD4E_ISC_D10 (1u << 4) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD18F_ISC_D10 (1u << 18) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PB25F_ISC_D11 (1u << 25) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PC20C_ISC_D11 (1u << 20) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD3E_ISC_D11 (1u << 3) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD19F_ISC_D11 (1u << 19) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PB28F_ISC_D2 (1u << 28) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PC11C_ISC_D2 (1u << 11) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PD9E_ISC_D2 (1u << 9) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PB29F_ISC_D3 (1u << 29) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PC12C_ISC_D3 (1u << 12) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PD10E_ISC_D3 (1u << 10) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PB30F_ISC_D4 (1u << 30) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PC13C_ISC_D4 (1u << 13) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD11E_ISC_D4 (1u << 11) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD12F_ISC_D4 (1u << 12) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PB31F_ISC_D5 (1u << 31) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC14C_ISC_D5 (1u << 14) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD12E_ISC_D5 (1u << 12) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD13F_ISC_D5 (1u << 13) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC0F_ISC_D6 (1u << 0) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC15C_ISC_D6 (1u << 15) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD13E_ISC_D6 (1u << 13) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD14F_ISC_D6 (1u << 14) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC1F_ISC_D7 (1u << 1) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC16C_ISC_D7 (1u << 16) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD14E_ISC_D7 (1u << 14) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD15F_ISC_D7 (1u << 15) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC2F_ISC_D8 (1u << 2) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC17C_ISC_D8 (1u << 17) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD6E_ISC_D8 (1u << 6) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD16F_ISC_D8 (1u << 16) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC3F_ISC_D9 (1u << 3) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC18C_ISC_D9 (1u << 18) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD5E_ISC_D9 (1u << 5) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD17F_ISC_D9 (1u << 17) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC8F_ISC_FIELD (1u << 8) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC25C_ISC_FIELD (1u << 25) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD18E_ISC_FIELD (1u << 18) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD23F_ISC_FIELD (1u << 23) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC6F_ISC_HSYNC (1u << 6) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC23C_ISC_HSYNC (1u << 23) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD17E_ISC_HSYNC (1u << 17) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD22F_ISC_HSYNC (1u << 22) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC7F_ISC_MCK (1u << 7) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC24C_ISC_MCK (1u << 24) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD2E_ISC_MCK (1u << 2) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD11F_ISC_MCK (1u << 11) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC4F_ISC_PCK (1u << 4) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC21C_ISC_PCK (1u << 21) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD15E_ISC_PCK (1u << 15) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD20F_ISC_PCK (1u << 20) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC5F_ISC_VSYNC (1u << 5) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PC22C_ISC_VSYNC (1u << 22) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD16E_ISC_VSYNC (1u << 16) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD21F_ISC_VSYNC (1u << 21) /**< \brief Isc signal: ISC_VSYNC */\r
+/* ========== Pio definition for LCDC peripheral ========== */\r
+#define PIO_PB11A_LCDDAT0 (1u << 11) /**< \brief Lcdc signal: LCDDAT0 */\r
+#define PIO_PB12A_LCDDAT1 (1u << 12) /**< \brief Lcdc signal: LCDDAT1 */\r
+#define PIO_PB21A_LCDDAT10 (1u << 21) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PC16A_LCDDAT10 (1u << 16) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PB22A_LCDDAT11 (1u << 22) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PC17A_LCDDAT11 (1u << 17) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PB23A_LCDDAT12 (1u << 23) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PC18A_LCDDAT12 (1u << 18) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PB24A_LCDDAT13 (1u << 24) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PC19A_LCDDAT13 (1u << 19) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PB25A_LCDDAT14 (1u << 25) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PC20A_LCDDAT14 (1u << 20) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PB26A_LCDDAT15 (1u << 26) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PC21A_LCDDAT15 (1u << 21) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PB27A_LCDDAT16 (1u << 27) /**< \brief Lcdc signal: LCDDAT16 */\r
+#define PIO_PB28A_LCDDAT17 (1u << 28) /**< \brief Lcdc signal: LCDDAT17 */\r
+#define PIO_PB29A_LCDDAT18 (1u << 29) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PC22A_LCDDAT18 (1u << 22) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PB30A_LCDDAT19 (1u << 30) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PC23A_LCDDAT19 (1u << 23) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PB13A_LCDDAT2 (1u << 13) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PC10A_LCDDAT2 (1u << 10) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PB31A_LCDDAT20 (1u << 31) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC24A_LCDDAT20 (1u << 24) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC0A_LCDDAT21 (1u << 0) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC25A_LCDDAT21 (1u << 25) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC1A_LCDDAT22 (1u << 1) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC26A_LCDDAT22 (1u << 26) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC2A_LCDDAT23 (1u << 2) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PC27A_LCDDAT23 (1u << 27) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PB14A_LCDDAT3 (1u << 14) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PC11A_LCDDAT3 (1u << 11) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PB15A_LCDDAT4 (1u << 15) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PC12A_LCDDAT4 (1u << 12) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PB16A_LCDDAT5 (1u << 16) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PC13A_LCDDAT5 (1u << 13) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PB17A_LCDDAT6 (1u << 17) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PC14A_LCDDAT6 (1u << 14) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PB18A_LCDDAT7 (1u << 18) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PC15A_LCDDAT7 (1u << 15) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PB19A_LCDDAT8 (1u << 19) /**< \brief Lcdc signal: LCDDAT8 */\r
+#define PIO_PB20A_LCDDAT9 (1u << 20) /**< \brief Lcdc signal: LCDDAT9 */\r
+#define PIO_PC8A_LCDDEN (1u << 8) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PD1A_LCDDEN (1u << 1) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PC4A_LCDDISP (1u << 4) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC29A_LCDDISP (1u << 29) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC6A_LCDHSYNC (1u << 6) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC31A_LCDHSYNC (1u << 31) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC7A_LCDPCK (1u << 7) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PD0A_LCDPCK (1u << 0) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PC3A_LCDPWM (1u << 3) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC28A_LCDPWM (1u << 28) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC5A_LCDVSYNC (1u << 5) /**< \brief Lcdc signal: LCDVSYNC */\r
+#define PIO_PC30A_LCDVSYNC (1u << 30) /**< \brief Lcdc signal: LCDVSYNC */\r
+/* ========== Pio definition for MCAN0 peripheral ========== */\r
+#define PIO_PC2C_CANRX0 (1u << 2) /**< \brief Mcan0 signal: CANRX0 */\r
+#define PIO_PC1C_CANTX0 (1u << 1) /**< \brief Mcan0 signal: CANTX0 */\r
+/* ========== Pio definition for PDMIC peripheral ========== */\r
+#define PIO_PB12D_PDMIC_CLK (1u << 12) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB27D_PDMIC_CLK (1u << 27) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB11D_PDMIC_DAT (1u << 11) /**< \brief Pdmic signal: PDMIC_DAT */\r
+#define PIO_PB26D_PDMIC_DAT (1u << 26) /**< \brief Pdmic signal: PDMIC_DAT */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PC8D_PCK0 (1u << 8) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD19A_PCK0 (1u << 19) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD31E_PCK0 (1u << 31) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13C_PCK1 (1u << 13) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PB20E_PCK1 (1u << 20) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PC27C_PCK1 (1u << 27) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PD6B_PCK1 (1u << 6) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK2 (1u << 21) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PC28C_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD11B_PCK2 (1u << 11) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PB3D_PWMEXTRG0 (1u << 3) /**< \brief Pwm signal: PWMEXTRG0 */\r
+#define PIO_PB10C_PWMEXTRG1 (1u << 10) /**< \brief Pwm signal: PWMEXTRG1 */\r
+#define PIO_PB2D_PWMFI0 (1u << 2) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PB9C_PWMFI1 (1u << 9) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PA30D_PWMH0 (1u << 30) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0D_PWMH1 (1u << 0) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB5C_PWMH2 (1u << 5) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB7C_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA31D_PWML0 (1u << 31) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB1D_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB6C_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB8C_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for QSPI0 peripheral ========== */\r
+#define PIO_PA1B_QSPI0_CS (1u << 1) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA15C_QSPI0_CS (1u << 15) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA23F_QSPI0_CS (1u << 23) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA2B_QSPI0_IO0 (1u << 2) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA16C_QSPI0_IO0 (1u << 16) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA24F_QSPI0_IO0 (1u << 24) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA3B_QSPI0_IO1 (1u << 3) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA17C_QSPI0_IO1 (1u << 17) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA25F_QSPI0_IO1 (1u << 25) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA4B_QSPI0_IO2 (1u << 4) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA18C_QSPI0_IO2 (1u << 18) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA26F_QSPI0_IO2 (1u << 26) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA5B_QSPI0_IO3 (1u << 5) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA19C_QSPI0_IO3 (1u << 19) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA27F_QSPI0_IO3 (1u << 27) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA0B_QSPI0_SCK (1u << 0) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA14C_QSPI0_SCK (1u << 14) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA22F_QSPI0_SCK (1u << 22) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+/* ========== Pio definition for QSPI1 peripheral ========== */\r
+#define PIO_PA11B_QSPI1_CS (1u << 11) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB6D_QSPI1_CS (1u << 6) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB15E_QSPI1_CS (1u << 15) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PA7B_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB7D_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB16E_QSPI1_IO0 (1u << 16) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PA8B_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB8D_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB17E_QSPI1_IO1 (1u << 17) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PA9B_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB9D_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB18E_QSPI1_IO2 (1u << 18) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PA10B_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB10D_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB19E_QSPI1_IO3 (1u << 19) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PA6B_QSPI1_SCK (1u << 6) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB5D_QSPI1_SCK (1u << 5) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB14E_QSPI1_SCK (1u << 14) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+/* ========== Pio definition for SDMMC0 peripheral ========== */\r
+#define PIO_PA30E_SDMMC0_CD (1u << 30) /**< \brief Sdmmc0 signal: SDMMC0_CD */\r
+#define PIO_PA27E_SDMMC0_RSTN (1u << 27) /**< \brief Sdmmc0 signal: SDMMC0_RSTN */\r
+#define PIO_PA22E_SDMMC0_CK (1u << 22) /**< \brief Sdmmc0 signal: SDMMC0_CK */\r
+#define PIO_PA28E_SDMMC0_CMD (1u << 28) /**< \brief Sdmmc0 signal: SDMMC0_CMD */\r
+#define PIO_PA29E_SDMMC0_WP (1u << 29) /**< \brief Sdmmc0 signal: SDMMC0_WP */\r
+#define PIO_PA18E_SDMMC0_DAT0 (1u << 18) /**< \brief Sdmmc0 signal: SDMMC0_DAT0 */\r
+#define PIO_PA19E_SDMMC0_DAT1 (1u << 19) /**< \brief Sdmmc0 signal: SDMMC0_DAT1 */\r
+#define PIO_PA20E_SDMMC0_DAT2 (1u << 20) /**< \brief Sdmmc0 signal: SDMMC0_DAT2 */\r
+#define PIO_PA21E_SDMMC0_DAT3 (1u << 21) /**< \brief Sdmmc0 signal: SDMMC0_DAT3 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA16A_SPI0_MISO (1u << 16) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA31C_SPI0_MISO (1u << 31) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA15A_SPI0_MOSI (1u << 15) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB0C_SPI0_MOSI (1u << 0) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA17A_SPI0_NPCS0 (1u << 17) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA30C_SPI0_NPCS0 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA18A_SPI0_NPCS1 (1u << 18) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA29C_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA19A_SPI0_NPCS2 (1u << 19) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA27C_SPI0_NPCS2 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA20A_SPI0_NPCS3 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA28C_SPI0_NPCS3 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA14A_SPI0_SPCK (1u << 14) /**< \brief Spi0 signal: SPI0_SPCK */\r
+#define PIO_PB1C_SPI0_SPCK (1u << 1) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PA24D_SPI1_MISO (1u << 24) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC3D_SPI1_MISO (1u << 3) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PD27A_SPI1_MISO (1u << 27) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PA23D_SPI1_MOSI (1u << 23) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC2D_SPI1_MOSI (1u << 2) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PD26A_SPI1_MOSI (1u << 26) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PA25D_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC4D_SPI1_NPCS0 (1u << 4) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PD28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PA26D_SPI1_NPCS1 (1u << 26) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC5D_SPI1_NPCS1 (1u << 5) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PA27D_SPI1_NPCS2 (1u << 27) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC6D_SPI1_NPCS2 (1u << 6) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD30A_SPI1_NPCS2 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PA28D_SPI1_NPCS3 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC7D_SPI1_NPCS3 (1u << 7) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PA22D_SPI1_SPCK (1u << 22) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PC1D_SPI1_SPCK (1u << 1) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PD25A_SPI1_SPCK (1u << 25) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC0 peripheral ========== */\r
+#define PIO_PB23C_RD0 (1u << 23) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PC15E_RD0 (1u << 15) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PB25C_RF0 (1u << 25) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PC17E_RF0 (1u << 17) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PB24C_RK0 (1u << 24) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PC16E_RK0 (1u << 16) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PB22C_TD0 (1u << 22) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PC14E_TD0 (1u << 14) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PB21C_TF0 (1u << 21) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PC13E_TF0 (1u << 13) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PB20C_TK0 (1u << 20) /**< \brief Ssc0 signal: TK0 */\r
+#define PIO_PC12E_TK0 (1u << 12) /**< \brief Ssc0 signal: TK0 */\r
+/* ========== Pio definition for SSC1 peripheral ========== */\r
+#define PIO_PA17B_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PB17C_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PA19B_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PB19C_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PA18B_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PB18C_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PA16B_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PB16C_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PA15B_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PB15C_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PA14B_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+#define PIO_PB14C_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA21D_TCLK0 (1u << 21) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA29A_TCLK1 (1u << 29) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PC5C_TCLK1 (1u << 5) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PD13A_TCLK1 (1u << 13) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PB5A_TCLK2 (1u << 5) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB24D_TCLK2 (1u << 24) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PD22A_TCLK2 (1u << 22) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA19D_TIOA0 (1u << 19) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA27A_TIOA1 (1u << 27) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PC3C_TIOA1 (1u << 3) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PD11A_TIOA1 (1u << 11) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PB6A_TIOA2 (1u << 6) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB22D_TIOA2 (1u << 22) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PD20A_TIOA2 (1u << 20) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA20D_TIOB0 (1u << 20) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA28A_TIOB1 (1u << 28) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PC4C_TIOB1 (1u << 4) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PD12A_TIOB1 (1u << 12) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PB7A_TIOB2 (1u << 7) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PB23D_TIOB2 (1u << 23) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PD21A_TIOB2 (1u << 21) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PB8A_TCLK3 (1u << 8) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PB21D_TCLK3 (1u << 21) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PD31D_TCLK3 (1u << 31) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PA8D_TCLK5 (1u << 8) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB30D_TCLK5 (1u << 30) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB19D_TIOA3 (1u << 19) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PD29D_TIOA3 (1u << 29) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PA9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PA6D_TIOA5 (1u << 6) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB28D_TIOA5 (1u << 28) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB20D_TIOB3 (1u << 20) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PD30D_TIOB3 (1u << 30) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PA10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PA7D_TIOB5 (1u << 7) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PB29D_TIOB5 (1u << 29) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWIHS0 peripheral ========== */\r
+#define PIO_PC0D_TWCK0 (1u << 0) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PC28E_TWCK0 (1u << 28) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD22B_TWCK0 (1u << 22) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD30E_TWCK0 (1u << 30) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PB31D_TWD0 (1u << 31) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PC27E_TWD0 (1u << 27) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD21B_TWD0 (1u << 21) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD29E_TWD0 (1u << 29) /**< \brief Twihs0 signal: TWD0 */\r
+/* ========== Pio definition for TWIHS1 peripheral ========== */\r
+#define PIO_PC7C_TWCK1 (1u << 7) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD20B_TWCK1 (1u << 20) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PC6C_TWD1 (1u << 6) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD19B_TWD1 (1u << 19) /**< \brief Twihs1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PB26C_URXD0 (1u << 26) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PB27C_UTXD0 (1u << 27) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PC7E_URXD1 (1u << 7) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PD2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PC8E_UTXD1 (1u << 8) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD4B_URXD2 (1u << 4) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD19C_URXD2 (1u << 19) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD23A_URXD2 (1u << 23) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD5B_UTXD2 (1u << 5) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD20C_UTXD2 (1u << 20) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD24A_UTXD2 (1u << 24) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PB11C_URXD3 (1u << 11) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC12D_URXD3 (1u << 12) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC31C_URXD3 (1u << 31) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PB12C_UTXD3 (1u << 12) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PC13D_UTXD3 (1u << 13) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD0C_UTXD3 (1u << 0) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PB3A_URXD4 (1u << 3) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PB4A_UTXD4 (1u << 4) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+\r
+#endif /* _SAMA5D22_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D23_PIO_\r
+#define _SAMA5D23_PIO_\r
+\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PD19X1_AD0 (1u << 19) /**< \brief Adc signal: AD0 */\r
+#define PIO_PD20X1_AD1 (1u << 20) /**< \brief Adc signal: AD1 */\r
+#define PIO_PD29X1_AD10 (1u << 29) /**< \brief Adc signal: AD10 */\r
+#define PIO_PD30X1_AD11 (1u << 30) /**< \brief Adc signal: AD11 */\r
+#define PIO_PD21X1_AD2 (1u << 21) /**< \brief Adc signal: AD2 */\r
+#define PIO_PD22X1_AD3 (1u << 22) /**< \brief Adc signal: AD3 */\r
+#define PIO_PD23X1_AD4 (1u << 23) /**< \brief Adc signal: AD4 */\r
+#define PIO_PD24X1_AD5 (1u << 24) /**< \brief Adc signal: AD5 */\r
+#define PIO_PD25X1_AD6 (1u << 25) /**< \brief Adc signal: AD6 */\r
+#define PIO_PD26X1_AD7 (1u << 26) /**< \brief Adc signal: AD7 */\r
+#define PIO_PD27X1_AD8 (1u << 27) /**< \brief Adc signal: AD8 */\r
+#define PIO_PD28X1_AD9 (1u << 28) /**< \brief Adc signal: AD9 */\r
+#define PIO_PD31A_ADTRG (1u << 31) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for AIC peripheral ========== */\r
+#define PIO_PB4C_FIQ (1u << 4) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC8C_FIQ (1u << 8) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC9A_FIQ (1u << 9) /**< \brief Aic signal: FIQ */\r
+#define PIO_PD3B_FIQ (1u << 3) /**< \brief Aic signal: FIQ */\r
+#define PIO_PA12B_IRQ (1u << 12) /**< \brief Aic signal: IRQ */\r
+#define PIO_PA21A_IRQ (1u << 21) /**< \brief Aic signal: IRQ */\r
+#define PIO_PB3C_IRQ (1u << 3) /**< \brief Aic signal: IRQ */\r
+#define PIO_PD31C_IRQ (1u << 31) /**< \brief Aic signal: IRQ */\r
+/* ========== Pio definition for ARM peripheral ========== */\r
+#define PIO_PA26C_NTRST (1u << 26) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD10A_NTRST (1u << 10) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD18A_NTRST (1u << 18) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD31B_NTRST (1u << 31) /**< \brief Arm signal: NTRST */\r
+#define PIO_PA22C_TCK (1u << 22) /**< \brief Arm signal: TCK */\r
+#define PIO_PD6A_TCK (1u << 6) /**< \brief Arm signal: TCK */\r
+#define PIO_PD14A_TCK (1u << 14) /**< \brief Arm signal: TCK */\r
+#define PIO_PD27B_TCK (1u << 27) /**< \brief Arm signal: TCK */\r
+#define PIO_PA23C_TDI (1u << 23) /**< \brief Arm signal: TDI */\r
+#define PIO_PD7A_TDI (1u << 7) /**< \brief Arm signal: TDI */\r
+#define PIO_PD15A_TDI (1u << 15) /**< \brief Arm signal: TDI */\r
+#define PIO_PD28B_TDI (1u << 28) /**< \brief Arm signal: TDI */\r
+#define PIO_PA24C_TDO (1u << 24) /**< \brief Arm signal: TDO */\r
+#define PIO_PD8A_TDO (1u << 8) /**< \brief Arm signal: TDO */\r
+#define PIO_PD16A_TDO (1u << 16) /**< \brief Arm signal: TDO */\r
+#define PIO_PD29B_TDO (1u << 29) /**< \brief Arm signal: TDO */\r
+#define PIO_PA25C_TMS (1u << 25) /**< \brief Arm signal: TMS */\r
+#define PIO_PD9A_TMS (1u << 9) /**< \brief Arm signal: TMS */\r
+#define PIO_PD17A_TMS (1u << 17) /**< \brief Arm signal: TMS */\r
+#define PIO_PD30B_TMS (1u << 30) /**< \brief Arm signal: TMS */\r
+/* ========== Pio definition for CLASSD peripheral ========== */\r
+#define PIO_PA28F_CLASSD_L0 (1u << 28) /**< \brief Classd signal: CLASSD_L0 */\r
+#define PIO_PA29F_CLASSD_L1 (1u << 29) /**< \brief Classd signal: CLASSD_L1 */\r
+#define PIO_PA30F_CLASSD_L2 (1u << 30) /**< \brief Classd signal: CLASSD_L2 */\r
+#define PIO_PA31F_CLASSD_L3 (1u << 31) /**< \brief Classd signal: CLASSD_L3 */\r
+#define PIO_PB1F_CLASSD_R0 (1u << 1) /**< \brief Classd signal: CLASSD_R0 */\r
+#define PIO_PB2F_CLASSD_R1 (1u << 2) /**< \brief Classd signal: CLASSD_R1 */\r
+#define PIO_PB3F_CLASSD_R2 (1u << 3) /**< \brief Classd signal: CLASSD_R2 */\r
+#define PIO_PB4F_CLASSD_R3 (1u << 4) /**< \brief Classd signal: CLASSD_R3 */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PB11B_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB11B_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB12B_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC12F_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PB21B_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC21F_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PB22B_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC22F_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PB23B_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC23F_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PB24B_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PC24F_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PB25B_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PC25F_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PB26B_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PC26F_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PB27B_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PC27F_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PB28B_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PC28F_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PB29B_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PC29F_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PB30B_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC30F_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PB13B_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PC13F_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PB31B_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC31F_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PA10F_A21 (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA10F_NANDALE (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_A21 (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_NANDALE (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA11F_A22 (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA11F_NANDCLE (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_A22 (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_NANDCLE (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC0B_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PD0F_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC1B_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PD1F_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PC2B_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PD2F_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PB14B_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC14F_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PB15B_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC15F_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PB16B_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC16F_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PB17B_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC17F_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PB18B_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC18F_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PB19B_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC19F_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PB20B_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC20F_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PA0F_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA22B_D0 (1u << 22) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA1F_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA23B_D1 (1u << 23) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA15F_D10 (1u << 15) /**< \brief Ebi signal: D10 */\r
+#define PIO_PB5B_D10 (1u << 5) /**< \brief Ebi signal: D10 */\r
+#define PIO_PA16F_D11 (1u << 16) /**< \brief Ebi signal: D11 */\r
+#define PIO_PB6B_D11 (1u << 6) /**< \brief Ebi signal: D11 */\r
+#define PIO_PA17F_D12 (1u << 17) /**< \brief Ebi signal: D12 */\r
+#define PIO_PB7B_D12 (1u << 7) /**< \brief Ebi signal: D12 */\r
+#define PIO_PA18F_D13 (1u << 18) /**< \brief Ebi signal: D13 */\r
+#define PIO_PB8B_D13 (1u << 8) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA19F_D14 (1u << 19) /**< \brief Ebi signal: D14 */\r
+#define PIO_PB9B_D14 (1u << 9) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA20F_D15 (1u << 20) /**< \brief Ebi signal: D15 */\r
+#define PIO_PB10B_D15 (1u << 10) /**< \brief Ebi signal: D15 */\r
+#define PIO_PA2F_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA24B_D2 (1u << 24) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA3F_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA25B_D3 (1u << 25) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA4F_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA26B_D4 (1u << 26) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA5F_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA27B_D5 (1u << 27) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA6F_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA28B_D6 (1u << 28) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA7F_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA29B_D7 (1u << 29) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA13F_D8 (1u << 13) /**< \brief Ebi signal: D8 */\r
+#define PIO_PB3B_D8 (1u << 3) /**< \brief Ebi signal: D8 */\r
+#define PIO_PA14F_D9 (1u << 14) /**< \brief Ebi signal: D9 */\r
+#define PIO_PB4B_D9 (1u << 4) /**< \brief Ebi signal: D9 */\r
+#define PIO_PA21F_NANDRDY (1u << 21) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC8B_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PD8F_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC5B_NCS0 (1u << 5) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PD4F_NCS0 (1u << 4) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC6B_NCS1 (1u << 6) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PD5F_NCS1 (1u << 5) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PC7B_NCS2 (1u << 7) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PD6F_NCS2 (1u << 6) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PA9F_NCS3 (1u << 9) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA31B_NCS3 (1u << 31) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA12F_NRD (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PA12F_NANDOE (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NRD (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NANDOE (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PC3B_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PD3F_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PA8F_NWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA8F_NANDWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NANDWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PC4B_NWR1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PC4B_NBS1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NWR1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NBS1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+/* ========== Pio definition for FLEXCOM0 peripheral ========== */\r
+#define PIO_PB28C_FLEXCOM0_IO0 (1u << 28) /**< \brief Flexcom0 signal: FLEXCOM0_IO0 */\r
+#define PIO_PB29C_FLEXCOM0_IO1 (1u << 29) /**< \brief Flexcom0 signal: FLEXCOM0_IO1 */\r
+#define PIO_PB30C_FLEXCOM0_IO2 (1u << 30) /**< \brief Flexcom0 signal: FLEXCOM0_IO2 */\r
+#define PIO_PB31C_FLEXCOM0_IO3 (1u << 31) /**< \brief Flexcom0 signal: FLEXCOM0_IO3 */\r
+#define PIO_PC0C_FLEXCOM0_IO4 (1u << 0) /**< \brief Flexcom0 signal: FLEXCOM0_IO4 */\r
+/* ========== Pio definition for FLEXCOM1 peripheral ========== */\r
+#define PIO_PA24A_FLEXCOM1_IO0 (1u << 24) /**< \brief Flexcom1 signal: FLEXCOM1_IO0 */\r
+#define PIO_PA23A_FLEXCOM1_IO1 (1u << 23) /**< \brief Flexcom1 signal: FLEXCOM1_IO1 */\r
+#define PIO_PA22A_FLEXCOM1_IO2 (1u << 22) /**< \brief Flexcom1 signal: FLEXCOM1_IO2 */\r
+#define PIO_PA25A_FLEXCOM1_IO3 (1u << 25) /**< \brief Flexcom1 signal: FLEXCOM1_IO3 */\r
+#define PIO_PA26A_FLEXCOM1_IO4 (1u << 26) /**< \brief Flexcom1 signal: FLEXCOM1_IO4 */\r
+/* ========== Pio definition for FLEXCOM3 peripheral ========== */\r
+#define PIO_PA15E_FLEXCOM3_IO0 (1u << 15) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PB23E_FLEXCOM3_IO0 (1u << 23) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PC20E_FLEXCOM3_IO0 (1u << 20) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PA13E_FLEXCOM3_IO1 (1u << 13) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PB22E_FLEXCOM3_IO1 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PC19E_FLEXCOM3_IO1 (1u << 19) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PA14E_FLEXCOM3_IO2 (1u << 14) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PB21E_FLEXCOM3_IO2 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PC18E_FLEXCOM3_IO2 (1u << 18) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PA16E_FLEXCOM3_IO3 (1u << 16) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PB24E_FLEXCOM3_IO3 (1u << 24) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PC21E_FLEXCOM3_IO3 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PA17E_FLEXCOM3_IO4 (1u << 17) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PB25E_FLEXCOM3_IO4 (1u << 25) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PC22E_FLEXCOM3_IO4 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+/* ========== Pio definition for FLEXCOM4 peripheral ========== */\r
+#define PIO_PC28B_FLEXCOM4_IO0 (1u << 28) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD12B_FLEXCOM4_IO0 (1u << 12) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD21C_FLEXCOM4_IO0 (1u << 21) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PC29B_FLEXCOM4_IO1 (1u << 29) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD13B_FLEXCOM4_IO1 (1u << 13) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD22C_FLEXCOM4_IO1 (1u << 22) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PC30B_FLEXCOM4_IO2 (1u << 30) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD14B_FLEXCOM4_IO2 (1u << 14) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD23C_FLEXCOM4_IO2 (1u << 23) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PC31B_FLEXCOM4_IO3 (1u << 31) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD15B_FLEXCOM4_IO3 (1u << 15) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD24C_FLEXCOM4_IO3 (1u << 24) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD0B_FLEXCOM4_IO4 (1u << 0) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD16B_FLEXCOM4_IO4 (1u << 16) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD25C_FLEXCOM4_IO4 (1u << 25) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PB9F_GCOL (1u << 9) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PC23B_GCOL (1u << 23) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD4D_GCOL (1u << 4) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PB8F_GCRS (1u << 8) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PC22B_GCRS (1u << 22) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD3D_GCRS (1u << 3) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PB22F_GMDC (1u << 22) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PC18B_GMDC (1u << 18) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD17D_GMDC (1u << 17) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PB23F_GMDIO (1u << 23) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PC19B_GMDIO (1u << 19) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD18D_GMDIO (1u << 18) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PB18F_GRX0 (1u << 18) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PC14B_GRX0 (1u << 14) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD13D_GRX0 (1u << 13) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PB19F_GRX1 (1u << 19) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PC15B_GRX1 (1u << 15) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD14D_GRX1 (1u << 14) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PB10F_GRX2 (1u << 10) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PC24B_GRX2 (1u << 24) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD5D_GRX2 (1u << 5) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PB11F_GRX3 (1u << 11) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PC25B_GRX3 (1u << 25) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD6D_GRX3 (1u << 6) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PB7F_GRXCK (1u << 7) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PC20B_GRXCK (1u << 20) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD1D_GRXCK (1u << 1) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PB16F_GRXDV (1u << 16) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PC12B_GRXDV (1u << 12) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD11D_GRXDV (1u << 11) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PB17F_GRXER (1u << 17) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PC13B_GRXER (1u << 13) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD12D_GRXER (1u << 12) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB5F_GTSUCOMP (1u << 5) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PC9B_GTSUCOMP (1u << 9) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD0D_GTSUCOMP (1u << 0) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB20F_GTX0 (1u << 20) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PC16B_GTX0 (1u << 16) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD15D_GTX0 (1u << 15) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PB21F_GTX1 (1u << 21) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PC17B_GTX1 (1u << 17) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD16D_GTX1 (1u << 16) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PB12F_GTX2 (1u << 12) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PC26B_GTX2 (1u << 26) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD7D_GTX2 (1u << 7) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PB13F_GTX3 (1u << 13) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PC27B_GTX3 (1u << 27) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD8D_GTX3 (1u << 8) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PB14F_GTXCK (1u << 14) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PC10B_GTXCK (1u << 10) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD9D_GTXCK (1u << 9) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PB15F_GTXEN (1u << 15) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PC11B_GTXEN (1u << 11) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD10D_GTXEN (1u << 10) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PB6F_GTXER (1u << 6) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PC21B_GTXER (1u << 21) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PD2D_GTXER (1u << 2) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for I2SC0 peripheral ========== */\r
+#define PIO_PC1E_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PD19E_I2SC0_CK (1u << 19) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PC4E_I2SC0_DI0 (1u << 4) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PD22E_I2SC0_DI0 (1u << 22) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PC5E_I2SC0_DO0 (1u << 5) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PD23E_I2SC0_DO0 (1u << 23) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PC2E_I2SC0_MCK (1u << 2) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PD20E_I2SC0_MCK (1u << 20) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PC3E_I2SC0_WS (1u << 3) /**< \brief I2sc0 signal: I2SC0_WS */\r
+#define PIO_PD21E_I2SC0_WS (1u << 21) /**< \brief I2sc0 signal: I2SC0_WS */\r
+/* ========== Pio definition for I2SC1 peripheral ========== */\r
+#define PIO_PA15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PB15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PA17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PB17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PA18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PB18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PA14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PB14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PA16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+#define PIO_PB16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+/* ========== Pio definition for ISC peripheral ========== */\r
+#define PIO_PB26F_ISC_D0 (1u << 26) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PC9C_ISC_D0 (1u << 9) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PD7E_ISC_D0 (1u << 7) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PB27F_ISC_D1 (1u << 27) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PC10C_ISC_D1 (1u << 10) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PD8E_ISC_D1 (1u << 8) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PB24F_ISC_D10 (1u << 24) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PC19C_ISC_D10 (1u << 19) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD4E_ISC_D10 (1u << 4) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD18F_ISC_D10 (1u << 18) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PB25F_ISC_D11 (1u << 25) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PC20C_ISC_D11 (1u << 20) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD3E_ISC_D11 (1u << 3) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD19F_ISC_D11 (1u << 19) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PB28F_ISC_D2 (1u << 28) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PC11C_ISC_D2 (1u << 11) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PD9E_ISC_D2 (1u << 9) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PB29F_ISC_D3 (1u << 29) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PC12C_ISC_D3 (1u << 12) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PD10E_ISC_D3 (1u << 10) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PB30F_ISC_D4 (1u << 30) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PC13C_ISC_D4 (1u << 13) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD11E_ISC_D4 (1u << 11) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD12F_ISC_D4 (1u << 12) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PB31F_ISC_D5 (1u << 31) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC14C_ISC_D5 (1u << 14) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD12E_ISC_D5 (1u << 12) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD13F_ISC_D5 (1u << 13) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC0F_ISC_D6 (1u << 0) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC15C_ISC_D6 (1u << 15) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD13E_ISC_D6 (1u << 13) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD14F_ISC_D6 (1u << 14) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC1F_ISC_D7 (1u << 1) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC16C_ISC_D7 (1u << 16) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD14E_ISC_D7 (1u << 14) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD15F_ISC_D7 (1u << 15) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC2F_ISC_D8 (1u << 2) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC17C_ISC_D8 (1u << 17) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD6E_ISC_D8 (1u << 6) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD16F_ISC_D8 (1u << 16) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC3F_ISC_D9 (1u << 3) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC18C_ISC_D9 (1u << 18) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD5E_ISC_D9 (1u << 5) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD17F_ISC_D9 (1u << 17) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC8F_ISC_FIELD (1u << 8) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC25C_ISC_FIELD (1u << 25) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD18E_ISC_FIELD (1u << 18) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD23F_ISC_FIELD (1u << 23) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC6F_ISC_HSYNC (1u << 6) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC23C_ISC_HSYNC (1u << 23) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD17E_ISC_HSYNC (1u << 17) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD22F_ISC_HSYNC (1u << 22) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC7F_ISC_MCK (1u << 7) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC24C_ISC_MCK (1u << 24) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD2E_ISC_MCK (1u << 2) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD11F_ISC_MCK (1u << 11) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC4F_ISC_PCK (1u << 4) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC21C_ISC_PCK (1u << 21) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD15E_ISC_PCK (1u << 15) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD20F_ISC_PCK (1u << 20) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC5F_ISC_VSYNC (1u << 5) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PC22C_ISC_VSYNC (1u << 22) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD16E_ISC_VSYNC (1u << 16) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD21F_ISC_VSYNC (1u << 21) /**< \brief Isc signal: ISC_VSYNC */\r
+/* ========== Pio definition for LCDC peripheral ========== */\r
+#define PIO_PB11A_LCDDAT0 (1u << 11) /**< \brief Lcdc signal: LCDDAT0 */\r
+#define PIO_PB12A_LCDDAT1 (1u << 12) /**< \brief Lcdc signal: LCDDAT1 */\r
+#define PIO_PB21A_LCDDAT10 (1u << 21) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PC16A_LCDDAT10 (1u << 16) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PB22A_LCDDAT11 (1u << 22) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PC17A_LCDDAT11 (1u << 17) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PB23A_LCDDAT12 (1u << 23) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PC18A_LCDDAT12 (1u << 18) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PB24A_LCDDAT13 (1u << 24) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PC19A_LCDDAT13 (1u << 19) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PB25A_LCDDAT14 (1u << 25) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PC20A_LCDDAT14 (1u << 20) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PB26A_LCDDAT15 (1u << 26) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PC21A_LCDDAT15 (1u << 21) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PB27A_LCDDAT16 (1u << 27) /**< \brief Lcdc signal: LCDDAT16 */\r
+#define PIO_PB28A_LCDDAT17 (1u << 28) /**< \brief Lcdc signal: LCDDAT17 */\r
+#define PIO_PB29A_LCDDAT18 (1u << 29) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PC22A_LCDDAT18 (1u << 22) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PB30A_LCDDAT19 (1u << 30) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PC23A_LCDDAT19 (1u << 23) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PB13A_LCDDAT2 (1u << 13) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PC10A_LCDDAT2 (1u << 10) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PB31A_LCDDAT20 (1u << 31) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC24A_LCDDAT20 (1u << 24) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC0A_LCDDAT21 (1u << 0) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC25A_LCDDAT21 (1u << 25) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC1A_LCDDAT22 (1u << 1) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC26A_LCDDAT22 (1u << 26) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC2A_LCDDAT23 (1u << 2) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PC27A_LCDDAT23 (1u << 27) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PB14A_LCDDAT3 (1u << 14) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PC11A_LCDDAT3 (1u << 11) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PB15A_LCDDAT4 (1u << 15) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PC12A_LCDDAT4 (1u << 12) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PB16A_LCDDAT5 (1u << 16) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PC13A_LCDDAT5 (1u << 13) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PB17A_LCDDAT6 (1u << 17) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PC14A_LCDDAT6 (1u << 14) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PB18A_LCDDAT7 (1u << 18) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PC15A_LCDDAT7 (1u << 15) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PB19A_LCDDAT8 (1u << 19) /**< \brief Lcdc signal: LCDDAT8 */\r
+#define PIO_PB20A_LCDDAT9 (1u << 20) /**< \brief Lcdc signal: LCDDAT9 */\r
+#define PIO_PC8A_LCDDEN (1u << 8) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PD1A_LCDDEN (1u << 1) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PC4A_LCDDISP (1u << 4) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC29A_LCDDISP (1u << 29) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC6A_LCDHSYNC (1u << 6) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC31A_LCDHSYNC (1u << 31) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC7A_LCDPCK (1u << 7) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PD0A_LCDPCK (1u << 0) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PC3A_LCDPWM (1u << 3) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC28A_LCDPWM (1u << 28) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC5A_LCDVSYNC (1u << 5) /**< \brief Lcdc signal: LCDVSYNC */\r
+#define PIO_PC30A_LCDVSYNC (1u << 30) /**< \brief Lcdc signal: LCDVSYNC */\r
+/* ========== Pio definition for MCAN0 peripheral ========== */\r
+#define PIO_PC2C_CANRX0 (1u << 2) /**< \brief Mcan0 signal: CANRX0 */\r
+#define PIO_PC1C_CANTX0 (1u << 1) /**< \brief Mcan0 signal: CANTX0 */\r
+/* ========== Pio definition for PDMIC peripheral ========== */\r
+#define PIO_PB12D_PDMIC_CLK (1u << 12) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB27D_PDMIC_CLK (1u << 27) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB11D_PDMIC_DAT (1u << 11) /**< \brief Pdmic signal: PDMIC_DAT */\r
+#define PIO_PB26D_PDMIC_DAT (1u << 26) /**< \brief Pdmic signal: PDMIC_DAT */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PC8D_PCK0 (1u << 8) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD19A_PCK0 (1u << 19) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD31E_PCK0 (1u << 31) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13C_PCK1 (1u << 13) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PB20E_PCK1 (1u << 20) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PC27C_PCK1 (1u << 27) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PD6B_PCK1 (1u << 6) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK2 (1u << 21) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PC28C_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD11B_PCK2 (1u << 11) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PB3D_PWMEXTRG0 (1u << 3) /**< \brief Pwm signal: PWMEXTRG0 */\r
+#define PIO_PB10C_PWMEXTRG1 (1u << 10) /**< \brief Pwm signal: PWMEXTRG1 */\r
+#define PIO_PB2D_PWMFI0 (1u << 2) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PB9C_PWMFI1 (1u << 9) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PA30D_PWMH0 (1u << 30) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0D_PWMH1 (1u << 0) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB5C_PWMH2 (1u << 5) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB7C_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA31D_PWML0 (1u << 31) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB1D_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB6C_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB8C_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for QSPI0 peripheral ========== */\r
+#define PIO_PA1B_QSPI0_CS (1u << 1) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA15C_QSPI0_CS (1u << 15) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA23F_QSPI0_CS (1u << 23) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA2B_QSPI0_IO0 (1u << 2) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA16C_QSPI0_IO0 (1u << 16) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA24F_QSPI0_IO0 (1u << 24) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA3B_QSPI0_IO1 (1u << 3) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA17C_QSPI0_IO1 (1u << 17) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA25F_QSPI0_IO1 (1u << 25) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA4B_QSPI0_IO2 (1u << 4) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA18C_QSPI0_IO2 (1u << 18) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA26F_QSPI0_IO2 (1u << 26) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA5B_QSPI0_IO3 (1u << 5) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA19C_QSPI0_IO3 (1u << 19) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA27F_QSPI0_IO3 (1u << 27) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA0B_QSPI0_SCK (1u << 0) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA14C_QSPI0_SCK (1u << 14) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA22F_QSPI0_SCK (1u << 22) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+/* ========== Pio definition for QSPI1 peripheral ========== */\r
+#define PIO_PA11B_QSPI1_CS (1u << 11) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB6D_QSPI1_CS (1u << 6) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB15E_QSPI1_CS (1u << 15) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PA7B_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB7D_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB16E_QSPI1_IO0 (1u << 16) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PA8B_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB8D_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB17E_QSPI1_IO1 (1u << 17) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PA9B_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB9D_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB18E_QSPI1_IO2 (1u << 18) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PA10B_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB10D_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB19E_QSPI1_IO3 (1u << 19) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PA6B_QSPI1_SCK (1u << 6) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB5D_QSPI1_SCK (1u << 5) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB14E_QSPI1_SCK (1u << 14) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+/* ========== Pio definition for SDMMC0 peripheral ========== */\r
+#define PIO_PA30E_SDMMC0_CD (1u << 30) /**< \brief Sdmmc0 signal: SDMMC0_CD */\r
+#define PIO_PA27E_SDMMC0_RSTN (1u << 27) /**< \brief Sdmmc0 signal: SDMMC0_RSTN */\r
+#define PIO_PA22E_SDMMC0_CK (1u << 22) /**< \brief Sdmmc0 signal: SDMMC0_CK */\r
+#define PIO_PA28E_SDMMC0_CMD (1u << 28) /**< \brief Sdmmc0 signal: SDMMC0_CMD */\r
+#define PIO_PA29E_SDMMC0_WP (1u << 29) /**< \brief Sdmmc0 signal: SDMMC0_WP */\r
+#define PIO_PA18E_SDMMC0_DAT0 (1u << 18) /**< \brief Sdmmc0 signal: SDMMC0_DAT0 */\r
+#define PIO_PA19E_SDMMC0_DAT1 (1u << 19) /**< \brief Sdmmc0 signal: SDMMC0_DAT1 */\r
+#define PIO_PA20E_SDMMC0_DAT2 (1u << 20) /**< \brief Sdmmc0 signal: SDMMC0_DAT2 */\r
+#define PIO_PA21E_SDMMC0_DAT3 (1u << 21) /**< \brief Sdmmc0 signal: SDMMC0_DAT3 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA16A_SPI0_MISO (1u << 16) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA31C_SPI0_MISO (1u << 31) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA15A_SPI0_MOSI (1u << 15) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB0C_SPI0_MOSI (1u << 0) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA17A_SPI0_NPCS0 (1u << 17) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA30C_SPI0_NPCS0 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA18A_SPI0_NPCS1 (1u << 18) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA29C_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA19A_SPI0_NPCS2 (1u << 19) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA27C_SPI0_NPCS2 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA20A_SPI0_NPCS3 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA28C_SPI0_NPCS3 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA14A_SPI0_SPCK (1u << 14) /**< \brief Spi0 signal: SPI0_SPCK */\r
+#define PIO_PB1C_SPI0_SPCK (1u << 1) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PA24D_SPI1_MISO (1u << 24) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC3D_SPI1_MISO (1u << 3) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PD27A_SPI1_MISO (1u << 27) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PA23D_SPI1_MOSI (1u << 23) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC2D_SPI1_MOSI (1u << 2) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PD26A_SPI1_MOSI (1u << 26) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PA25D_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC4D_SPI1_NPCS0 (1u << 4) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PD28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PA26D_SPI1_NPCS1 (1u << 26) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC5D_SPI1_NPCS1 (1u << 5) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PA27D_SPI1_NPCS2 (1u << 27) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC6D_SPI1_NPCS2 (1u << 6) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD30A_SPI1_NPCS2 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PA28D_SPI1_NPCS3 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC7D_SPI1_NPCS3 (1u << 7) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PA22D_SPI1_SPCK (1u << 22) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PC1D_SPI1_SPCK (1u << 1) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PD25A_SPI1_SPCK (1u << 25) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC0 peripheral ========== */\r
+#define PIO_PB23C_RD0 (1u << 23) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PC15E_RD0 (1u << 15) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PB25C_RF0 (1u << 25) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PC17E_RF0 (1u << 17) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PB24C_RK0 (1u << 24) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PC16E_RK0 (1u << 16) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PB22C_TD0 (1u << 22) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PC14E_TD0 (1u << 14) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PB21C_TF0 (1u << 21) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PC13E_TF0 (1u << 13) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PB20C_TK0 (1u << 20) /**< \brief Ssc0 signal: TK0 */\r
+#define PIO_PC12E_TK0 (1u << 12) /**< \brief Ssc0 signal: TK0 */\r
+/* ========== Pio definition for SSC1 peripheral ========== */\r
+#define PIO_PA17B_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PB17C_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PA19B_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PB19C_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PA18B_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PB18C_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PA16B_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PB16C_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PA15B_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PB15C_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PA14B_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+#define PIO_PB14C_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA21D_TCLK0 (1u << 21) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA29A_TCLK1 (1u << 29) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PC5C_TCLK1 (1u << 5) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PD13A_TCLK1 (1u << 13) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PB5A_TCLK2 (1u << 5) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB24D_TCLK2 (1u << 24) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PD22A_TCLK2 (1u << 22) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA19D_TIOA0 (1u << 19) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA27A_TIOA1 (1u << 27) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PC3C_TIOA1 (1u << 3) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PD11A_TIOA1 (1u << 11) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PB6A_TIOA2 (1u << 6) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB22D_TIOA2 (1u << 22) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PD20A_TIOA2 (1u << 20) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA20D_TIOB0 (1u << 20) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA28A_TIOB1 (1u << 28) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PC4C_TIOB1 (1u << 4) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PD12A_TIOB1 (1u << 12) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PB7A_TIOB2 (1u << 7) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PB23D_TIOB2 (1u << 23) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PD21A_TIOB2 (1u << 21) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PB8A_TCLK3 (1u << 8) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PB21D_TCLK3 (1u << 21) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PD31D_TCLK3 (1u << 31) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PA8D_TCLK5 (1u << 8) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB30D_TCLK5 (1u << 30) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB19D_TIOA3 (1u << 19) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PD29D_TIOA3 (1u << 29) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PA9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PA6D_TIOA5 (1u << 6) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB28D_TIOA5 (1u << 28) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB20D_TIOB3 (1u << 20) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PD30D_TIOB3 (1u << 30) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PA10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PA7D_TIOB5 (1u << 7) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PB29D_TIOB5 (1u << 29) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWIHS0 peripheral ========== */\r
+#define PIO_PC0D_TWCK0 (1u << 0) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PC28E_TWCK0 (1u << 28) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD22B_TWCK0 (1u << 22) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD30E_TWCK0 (1u << 30) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PB31D_TWD0 (1u << 31) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PC27E_TWD0 (1u << 27) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD21B_TWD0 (1u << 21) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD29E_TWD0 (1u << 29) /**< \brief Twihs0 signal: TWD0 */\r
+/* ========== Pio definition for TWIHS1 peripheral ========== */\r
+#define PIO_PC7C_TWCK1 (1u << 7) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD20B_TWCK1 (1u << 20) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PC6C_TWD1 (1u << 6) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD19B_TWD1 (1u << 19) /**< \brief Twihs1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PB26C_URXD0 (1u << 26) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PB27C_UTXD0 (1u << 27) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PC7E_URXD1 (1u << 7) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PD2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PC8E_UTXD1 (1u << 8) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD4B_URXD2 (1u << 4) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD19C_URXD2 (1u << 19) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD23A_URXD2 (1u << 23) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD5B_UTXD2 (1u << 5) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD20C_UTXD2 (1u << 20) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD24A_UTXD2 (1u << 24) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PB11C_URXD3 (1u << 11) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC12D_URXD3 (1u << 12) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC31C_URXD3 (1u << 31) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PB12C_UTXD3 (1u << 12) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PC13D_UTXD3 (1u << 13) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD0C_UTXD3 (1u << 0) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PB3A_URXD4 (1u << 3) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PB4A_UTXD4 (1u << 4) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+\r
+#endif /* _SAMA5D23_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D24_PIO_\r
+#define _SAMA5D24_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PD19X1_AD0 (1u << 19) /**< \brief Adc signal: AD0 */\r
+#define PIO_PD20X1_AD1 (1u << 20) /**< \brief Adc signal: AD1 */\r
+#define PIO_PD29X1_AD10 (1u << 29) /**< \brief Adc signal: AD10 */\r
+#define PIO_PD30X1_AD11 (1u << 30) /**< \brief Adc signal: AD11 */\r
+#define PIO_PD21X1_AD2 (1u << 21) /**< \brief Adc signal: AD2 */\r
+#define PIO_PD22X1_AD3 (1u << 22) /**< \brief Adc signal: AD3 */\r
+#define PIO_PD23X1_AD4 (1u << 23) /**< \brief Adc signal: AD4 */\r
+#define PIO_PD24X1_AD5 (1u << 24) /**< \brief Adc signal: AD5 */\r
+#define PIO_PD25X1_AD6 (1u << 25) /**< \brief Adc signal: AD6 */\r
+#define PIO_PD26X1_AD7 (1u << 26) /**< \brief Adc signal: AD7 */\r
+#define PIO_PD27X1_AD8 (1u << 27) /**< \brief Adc signal: AD8 */\r
+#define PIO_PD28X1_AD9 (1u << 28) /**< \brief Adc signal: AD9 */\r
+#define PIO_PD31A_ADTRG (1u << 31) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for AIC peripheral ========== */\r
+#define PIO_PB4C_FIQ (1u << 4) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC8C_FIQ (1u << 8) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC9A_FIQ (1u << 9) /**< \brief Aic signal: FIQ */\r
+#define PIO_PD3B_FIQ (1u << 3) /**< \brief Aic signal: FIQ */\r
+#define PIO_PA12B_IRQ (1u << 12) /**< \brief Aic signal: IRQ */\r
+#define PIO_PA21A_IRQ (1u << 21) /**< \brief Aic signal: IRQ */\r
+#define PIO_PB3C_IRQ (1u << 3) /**< \brief Aic signal: IRQ */\r
+#define PIO_PD31C_IRQ (1u << 31) /**< \brief Aic signal: IRQ */\r
+/* ========== Pio definition for ARM peripheral ========== */\r
+#define PIO_PA26C_NTRST (1u << 26) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD10A_NTRST (1u << 10) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD18A_NTRST (1u << 18) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD31B_NTRST (1u << 31) /**< \brief Arm signal: NTRST */\r
+#define PIO_PA22C_TCK (1u << 22) /**< \brief Arm signal: TCK */\r
+#define PIO_PD6A_TCK (1u << 6) /**< \brief Arm signal: TCK */\r
+#define PIO_PD14A_TCK (1u << 14) /**< \brief Arm signal: TCK */\r
+#define PIO_PD27B_TCK (1u << 27) /**< \brief Arm signal: TCK */\r
+#define PIO_PA23C_TDI (1u << 23) /**< \brief Arm signal: TDI */\r
+#define PIO_PD7A_TDI (1u << 7) /**< \brief Arm signal: TDI */\r
+#define PIO_PD15A_TDI (1u << 15) /**< \brief Arm signal: TDI */\r
+#define PIO_PD28B_TDI (1u << 28) /**< \brief Arm signal: TDI */\r
+#define PIO_PA24C_TDO (1u << 24) /**< \brief Arm signal: TDO */\r
+#define PIO_PD8A_TDO (1u << 8) /**< \brief Arm signal: TDO */\r
+#define PIO_PD16A_TDO (1u << 16) /**< \brief Arm signal: TDO */\r
+#define PIO_PD29B_TDO (1u << 29) /**< \brief Arm signal: TDO */\r
+#define PIO_PA25C_TMS (1u << 25) /**< \brief Arm signal: TMS */\r
+#define PIO_PD9A_TMS (1u << 9) /**< \brief Arm signal: TMS */\r
+#define PIO_PD17A_TMS (1u << 17) /**< \brief Arm signal: TMS */\r
+#define PIO_PD30B_TMS (1u << 30) /**< \brief Arm signal: TMS */\r
+/* ========== Pio definition for CLASSD peripheral ========== */\r
+#define PIO_PA28F_CLASSD_L0 (1u << 28) /**< \brief Classd signal: CLASSD_L0 */\r
+#define PIO_PA29F_CLASSD_L1 (1u << 29) /**< \brief Classd signal: CLASSD_L1 */\r
+#define PIO_PA30F_CLASSD_L2 (1u << 30) /**< \brief Classd signal: CLASSD_L2 */\r
+#define PIO_PA31F_CLASSD_L3 (1u << 31) /**< \brief Classd signal: CLASSD_L3 */\r
+#define PIO_PB1F_CLASSD_R0 (1u << 1) /**< \brief Classd signal: CLASSD_R0 */\r
+#define PIO_PB2F_CLASSD_R1 (1u << 2) /**< \brief Classd signal: CLASSD_R1 */\r
+#define PIO_PB3F_CLASSD_R2 (1u << 3) /**< \brief Classd signal: CLASSD_R2 */\r
+#define PIO_PB4F_CLASSD_R3 (1u << 4) /**< \brief Classd signal: CLASSD_R3 */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PB11B_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB11B_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB12B_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC12F_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PB21B_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC21F_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PB22B_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC22F_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PB23B_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC23F_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PB24B_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PC24F_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PB25B_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PC25F_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PB26B_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PC26F_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PB27B_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PC27F_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PB28B_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PC28F_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PB29B_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PC29F_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PB30B_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC30F_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PB13B_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PC13F_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PB31B_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC31F_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PA10F_A21 (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA10F_NANDALE (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_A21 (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_NANDALE (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA11F_A22 (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA11F_NANDCLE (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_A22 (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_NANDCLE (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC0B_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PD0F_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC1B_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PD1F_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PC2B_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PD2F_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PB14B_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC14F_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PB15B_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC15F_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PB16B_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC16F_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PB17B_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC17F_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PB18B_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC18F_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PB19B_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC19F_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PB20B_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC20F_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PA0F_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA22B_D0 (1u << 22) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA1F_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA23B_D1 (1u << 23) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA15F_D10 (1u << 15) /**< \brief Ebi signal: D10 */\r
+#define PIO_PB5B_D10 (1u << 5) /**< \brief Ebi signal: D10 */\r
+#define PIO_PA16F_D11 (1u << 16) /**< \brief Ebi signal: D11 */\r
+#define PIO_PB6B_D11 (1u << 6) /**< \brief Ebi signal: D11 */\r
+#define PIO_PA17F_D12 (1u << 17) /**< \brief Ebi signal: D12 */\r
+#define PIO_PB7B_D12 (1u << 7) /**< \brief Ebi signal: D12 */\r
+#define PIO_PA18F_D13 (1u << 18) /**< \brief Ebi signal: D13 */\r
+#define PIO_PB8B_D13 (1u << 8) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA19F_D14 (1u << 19) /**< \brief Ebi signal: D14 */\r
+#define PIO_PB9B_D14 (1u << 9) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA20F_D15 (1u << 20) /**< \brief Ebi signal: D15 */\r
+#define PIO_PB10B_D15 (1u << 10) /**< \brief Ebi signal: D15 */\r
+#define PIO_PA2F_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA24B_D2 (1u << 24) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA3F_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA25B_D3 (1u << 25) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA4F_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA26B_D4 (1u << 26) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA5F_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA27B_D5 (1u << 27) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA6F_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA28B_D6 (1u << 28) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA7F_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA29B_D7 (1u << 29) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA13F_D8 (1u << 13) /**< \brief Ebi signal: D8 */\r
+#define PIO_PB3B_D8 (1u << 3) /**< \brief Ebi signal: D8 */\r
+#define PIO_PA14F_D9 (1u << 14) /**< \brief Ebi signal: D9 */\r
+#define PIO_PB4B_D9 (1u << 4) /**< \brief Ebi signal: D9 */\r
+#define PIO_PA21F_NANDRDY (1u << 21) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC8B_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PD8F_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC5B_NCS0 (1u << 5) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PD4F_NCS0 (1u << 4) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC6B_NCS1 (1u << 6) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PD5F_NCS1 (1u << 5) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PC7B_NCS2 (1u << 7) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PD6F_NCS2 (1u << 6) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PA9F_NCS3 (1u << 9) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA31B_NCS3 (1u << 31) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA12F_NRD (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PA12F_NANDOE (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NRD (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NANDOE (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PC3B_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PD3F_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PA8F_NWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA8F_NANDWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NANDWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PC4B_NWR1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PC4B_NBS1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NWR1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NBS1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+/* ========== Pio definition for FLEXCOM0 peripheral ========== */\r
+#define PIO_PB28C_FLEXCOM0_IO0 (1u << 28) /**< \brief Flexcom0 signal: FLEXCOM0_IO0 */\r
+#define PIO_PB29C_FLEXCOM0_IO1 (1u << 29) /**< \brief Flexcom0 signal: FLEXCOM0_IO1 */\r
+#define PIO_PB30C_FLEXCOM0_IO2 (1u << 30) /**< \brief Flexcom0 signal: FLEXCOM0_IO2 */\r
+#define PIO_PB31C_FLEXCOM0_IO3 (1u << 31) /**< \brief Flexcom0 signal: FLEXCOM0_IO3 */\r
+#define PIO_PC0C_FLEXCOM0_IO4 (1u << 0) /**< \brief Flexcom0 signal: FLEXCOM0_IO4 */\r
+/* ========== Pio definition for FLEXCOM1 peripheral ========== */\r
+#define PIO_PA24A_FLEXCOM1_IO0 (1u << 24) /**< \brief Flexcom1 signal: FLEXCOM1_IO0 */\r
+#define PIO_PA23A_FLEXCOM1_IO1 (1u << 23) /**< \brief Flexcom1 signal: FLEXCOM1_IO1 */\r
+#define PIO_PA22A_FLEXCOM1_IO2 (1u << 22) /**< \brief Flexcom1 signal: FLEXCOM1_IO2 */\r
+#define PIO_PA25A_FLEXCOM1_IO3 (1u << 25) /**< \brief Flexcom1 signal: FLEXCOM1_IO3 */\r
+#define PIO_PA26A_FLEXCOM1_IO4 (1u << 26) /**< \brief Flexcom1 signal: FLEXCOM1_IO4 */\r
+/* ========== Pio definition for FLEXCOM2 peripheral ========== */\r
+#define PIO_PA6E_FLEXCOM2_IO0 (1u << 6) /**< \brief Flexcom2 signal: FLEXCOM2_IO0 */\r
+#define PIO_PD26C_FLEXCOM2_IO0 (1u << 26) /**< \brief Flexcom2 signal: FLEXCOM2_IO0 */\r
+#define PIO_PA7E_FLEXCOM2_IO1 (1u << 7) /**< \brief Flexcom2 signal: FLEXCOM2_IO1 */\r
+#define PIO_PD27C_FLEXCOM2_IO1 (1u << 27) /**< \brief Flexcom2 signal: FLEXCOM2_IO1 */\r
+#define PIO_PA8E_FLEXCOM2_IO2 (1u << 8) /**< \brief Flexcom2 signal: FLEXCOM2_IO2 */\r
+#define PIO_PD28C_FLEXCOM2_IO2 (1u << 28) /**< \brief Flexcom2 signal: FLEXCOM2_IO2 */\r
+#define PIO_PA9E_FLEXCOM2_IO3 (1u << 9) /**< \brief Flexcom2 signal: FLEXCOM2_IO3 */\r
+#define PIO_PD29C_FLEXCOM2_IO3 (1u << 29) /**< \brief Flexcom2 signal: FLEXCOM2_IO3 */\r
+#define PIO_PA10E_FLEXCOM2_IO4 (1u << 10) /**< \brief Flexcom2 signal: FLEXCOM2_IO4 */\r
+#define PIO_PD30C_FLEXCOM2_IO4 (1u << 30) /**< \brief Flexcom2 signal: FLEXCOM2_IO4 */\r
+/* ========== Pio definition for FLEXCOM3 peripheral ========== */\r
+#define PIO_PA15E_FLEXCOM3_IO0 (1u << 15) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PB23E_FLEXCOM3_IO0 (1u << 23) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PC20E_FLEXCOM3_IO0 (1u << 20) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PA13E_FLEXCOM3_IO1 (1u << 13) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PB22E_FLEXCOM3_IO1 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PC19E_FLEXCOM3_IO1 (1u << 19) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PA14E_FLEXCOM3_IO2 (1u << 14) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PB21E_FLEXCOM3_IO2 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PC18E_FLEXCOM3_IO2 (1u << 18) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PA16E_FLEXCOM3_IO3 (1u << 16) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PB24E_FLEXCOM3_IO3 (1u << 24) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PC21E_FLEXCOM3_IO3 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PA17E_FLEXCOM3_IO4 (1u << 17) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PB25E_FLEXCOM3_IO4 (1u << 25) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PC22E_FLEXCOM3_IO4 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+/* ========== Pio definition for FLEXCOM4 peripheral ========== */\r
+#define PIO_PC28B_FLEXCOM4_IO0 (1u << 28) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD12B_FLEXCOM4_IO0 (1u << 12) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD21C_FLEXCOM4_IO0 (1u << 21) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PC29B_FLEXCOM4_IO1 (1u << 29) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD13B_FLEXCOM4_IO1 (1u << 13) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD22C_FLEXCOM4_IO1 (1u << 22) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PC30B_FLEXCOM4_IO2 (1u << 30) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD14B_FLEXCOM4_IO2 (1u << 14) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD23C_FLEXCOM4_IO2 (1u << 23) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PC31B_FLEXCOM4_IO3 (1u << 31) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD15B_FLEXCOM4_IO3 (1u << 15) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD24C_FLEXCOM4_IO3 (1u << 24) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD0B_FLEXCOM4_IO4 (1u << 0) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD16B_FLEXCOM4_IO4 (1u << 16) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD25C_FLEXCOM4_IO4 (1u << 25) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PB9F_GCOL (1u << 9) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PC23B_GCOL (1u << 23) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD4D_GCOL (1u << 4) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PB8F_GCRS (1u << 8) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PC22B_GCRS (1u << 22) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD3D_GCRS (1u << 3) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PB22F_GMDC (1u << 22) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PC18B_GMDC (1u << 18) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD17D_GMDC (1u << 17) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PB23F_GMDIO (1u << 23) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PC19B_GMDIO (1u << 19) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD18D_GMDIO (1u << 18) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PB18F_GRX0 (1u << 18) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PC14B_GRX0 (1u << 14) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD13D_GRX0 (1u << 13) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PB19F_GRX1 (1u << 19) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PC15B_GRX1 (1u << 15) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD14D_GRX1 (1u << 14) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PB10F_GRX2 (1u << 10) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PC24B_GRX2 (1u << 24) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD5D_GRX2 (1u << 5) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PB11F_GRX3 (1u << 11) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PC25B_GRX3 (1u << 25) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD6D_GRX3 (1u << 6) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PB7F_GRXCK (1u << 7) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PC20B_GRXCK (1u << 20) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD1D_GRXCK (1u << 1) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PB16F_GRXDV (1u << 16) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PC12B_GRXDV (1u << 12) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD11D_GRXDV (1u << 11) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PB17F_GRXER (1u << 17) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PC13B_GRXER (1u << 13) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD12D_GRXER (1u << 12) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB5F_GTSUCOMP (1u << 5) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PC9B_GTSUCOMP (1u << 9) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD0D_GTSUCOMP (1u << 0) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB20F_GTX0 (1u << 20) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PC16B_GTX0 (1u << 16) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD15D_GTX0 (1u << 15) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PB21F_GTX1 (1u << 21) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PC17B_GTX1 (1u << 17) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD16D_GTX1 (1u << 16) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PB12F_GTX2 (1u << 12) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PC26B_GTX2 (1u << 26) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD7D_GTX2 (1u << 7) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PB13F_GTX3 (1u << 13) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PC27B_GTX3 (1u << 27) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD8D_GTX3 (1u << 8) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PB14F_GTXCK (1u << 14) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PC10B_GTXCK (1u << 10) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD9D_GTXCK (1u << 9) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PB15F_GTXEN (1u << 15) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PC11B_GTXEN (1u << 11) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD10D_GTXEN (1u << 10) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PB6F_GTXER (1u << 6) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PC21B_GTXER (1u << 21) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PD2D_GTXER (1u << 2) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for I2SC0 peripheral ========== */\r
+#define PIO_PC1E_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PD19E_I2SC0_CK (1u << 19) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PC4E_I2SC0_DI0 (1u << 4) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PD22E_I2SC0_DI0 (1u << 22) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PC5E_I2SC0_DO0 (1u << 5) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PD23E_I2SC0_DO0 (1u << 23) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PC2E_I2SC0_MCK (1u << 2) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PD20E_I2SC0_MCK (1u << 20) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PC3E_I2SC0_WS (1u << 3) /**< \brief I2sc0 signal: I2SC0_WS */\r
+#define PIO_PD21E_I2SC0_WS (1u << 21) /**< \brief I2sc0 signal: I2SC0_WS */\r
+/* ========== Pio definition for I2SC1 peripheral ========== */\r
+#define PIO_PA15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PB15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PA17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PB17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PA18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PB18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PA14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PB14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PA16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+#define PIO_PB16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+/* ========== Pio definition for ISC peripheral ========== */\r
+#define PIO_PB26F_ISC_D0 (1u << 26) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PC9C_ISC_D0 (1u << 9) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PD7E_ISC_D0 (1u << 7) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PB27F_ISC_D1 (1u << 27) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PC10C_ISC_D1 (1u << 10) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PD8E_ISC_D1 (1u << 8) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PB24F_ISC_D10 (1u << 24) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PC19C_ISC_D10 (1u << 19) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD4E_ISC_D10 (1u << 4) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD18F_ISC_D10 (1u << 18) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PB25F_ISC_D11 (1u << 25) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PC20C_ISC_D11 (1u << 20) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD3E_ISC_D11 (1u << 3) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD19F_ISC_D11 (1u << 19) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PB28F_ISC_D2 (1u << 28) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PC11C_ISC_D2 (1u << 11) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PD9E_ISC_D2 (1u << 9) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PB29F_ISC_D3 (1u << 29) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PC12C_ISC_D3 (1u << 12) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PD10E_ISC_D3 (1u << 10) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PB30F_ISC_D4 (1u << 30) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PC13C_ISC_D4 (1u << 13) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD11E_ISC_D4 (1u << 11) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD12F_ISC_D4 (1u << 12) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PB31F_ISC_D5 (1u << 31) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC14C_ISC_D5 (1u << 14) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD12E_ISC_D5 (1u << 12) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD13F_ISC_D5 (1u << 13) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC0F_ISC_D6 (1u << 0) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC15C_ISC_D6 (1u << 15) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD13E_ISC_D6 (1u << 13) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD14F_ISC_D6 (1u << 14) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC1F_ISC_D7 (1u << 1) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC16C_ISC_D7 (1u << 16) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD14E_ISC_D7 (1u << 14) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD15F_ISC_D7 (1u << 15) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC2F_ISC_D8 (1u << 2) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC17C_ISC_D8 (1u << 17) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD6E_ISC_D8 (1u << 6) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD16F_ISC_D8 (1u << 16) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC3F_ISC_D9 (1u << 3) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC18C_ISC_D9 (1u << 18) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD5E_ISC_D9 (1u << 5) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD17F_ISC_D9 (1u << 17) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC8F_ISC_FIELD (1u << 8) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC25C_ISC_FIELD (1u << 25) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD18E_ISC_FIELD (1u << 18) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD23F_ISC_FIELD (1u << 23) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC6F_ISC_HSYNC (1u << 6) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC23C_ISC_HSYNC (1u << 23) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD17E_ISC_HSYNC (1u << 17) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD22F_ISC_HSYNC (1u << 22) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC7F_ISC_MCK (1u << 7) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC24C_ISC_MCK (1u << 24) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD2E_ISC_MCK (1u << 2) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD11F_ISC_MCK (1u << 11) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC4F_ISC_PCK (1u << 4) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC21C_ISC_PCK (1u << 21) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD15E_ISC_PCK (1u << 15) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD20F_ISC_PCK (1u << 20) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC5F_ISC_VSYNC (1u << 5) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PC22C_ISC_VSYNC (1u << 22) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD16E_ISC_VSYNC (1u << 16) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD21F_ISC_VSYNC (1u << 21) /**< \brief Isc signal: ISC_VSYNC */\r
+/* ========== Pio definition for LCDC peripheral ========== */\r
+#define PIO_PB11A_LCDDAT0 (1u << 11) /**< \brief Lcdc signal: LCDDAT0 */\r
+#define PIO_PB12A_LCDDAT1 (1u << 12) /**< \brief Lcdc signal: LCDDAT1 */\r
+#define PIO_PB21A_LCDDAT10 (1u << 21) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PC16A_LCDDAT10 (1u << 16) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PB22A_LCDDAT11 (1u << 22) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PC17A_LCDDAT11 (1u << 17) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PB23A_LCDDAT12 (1u << 23) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PC18A_LCDDAT12 (1u << 18) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PB24A_LCDDAT13 (1u << 24) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PC19A_LCDDAT13 (1u << 19) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PB25A_LCDDAT14 (1u << 25) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PC20A_LCDDAT14 (1u << 20) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PB26A_LCDDAT15 (1u << 26) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PC21A_LCDDAT15 (1u << 21) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PB27A_LCDDAT16 (1u << 27) /**< \brief Lcdc signal: LCDDAT16 */\r
+#define PIO_PB28A_LCDDAT17 (1u << 28) /**< \brief Lcdc signal: LCDDAT17 */\r
+#define PIO_PB29A_LCDDAT18 (1u << 29) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PC22A_LCDDAT18 (1u << 22) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PB30A_LCDDAT19 (1u << 30) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PC23A_LCDDAT19 (1u << 23) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PB13A_LCDDAT2 (1u << 13) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PC10A_LCDDAT2 (1u << 10) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PB31A_LCDDAT20 (1u << 31) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC24A_LCDDAT20 (1u << 24) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC0A_LCDDAT21 (1u << 0) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC25A_LCDDAT21 (1u << 25) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC1A_LCDDAT22 (1u << 1) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC26A_LCDDAT22 (1u << 26) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC2A_LCDDAT23 (1u << 2) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PC27A_LCDDAT23 (1u << 27) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PB14A_LCDDAT3 (1u << 14) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PC11A_LCDDAT3 (1u << 11) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PB15A_LCDDAT4 (1u << 15) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PC12A_LCDDAT4 (1u << 12) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PB16A_LCDDAT5 (1u << 16) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PC13A_LCDDAT5 (1u << 13) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PB17A_LCDDAT6 (1u << 17) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PC14A_LCDDAT6 (1u << 14) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PB18A_LCDDAT7 (1u << 18) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PC15A_LCDDAT7 (1u << 15) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PB19A_LCDDAT8 (1u << 19) /**< \brief Lcdc signal: LCDDAT8 */\r
+#define PIO_PB20A_LCDDAT9 (1u << 20) /**< \brief Lcdc signal: LCDDAT9 */\r
+#define PIO_PC8A_LCDDEN (1u << 8) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PD1A_LCDDEN (1u << 1) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PC4A_LCDDISP (1u << 4) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC29A_LCDDISP (1u << 29) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC6A_LCDHSYNC (1u << 6) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC31A_LCDHSYNC (1u << 31) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC7A_LCDPCK (1u << 7) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PD0A_LCDPCK (1u << 0) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PC3A_LCDPWM (1u << 3) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC28A_LCDPWM (1u << 28) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC5A_LCDVSYNC (1u << 5) /**< \brief Lcdc signal: LCDVSYNC */\r
+#define PIO_PC30A_LCDVSYNC (1u << 30) /**< \brief Lcdc signal: LCDVSYNC */\r
+/* ========== Pio definition for PDMIC peripheral ========== */\r
+#define PIO_PB12D_PDMIC_CLK (1u << 12) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB27D_PDMIC_CLK (1u << 27) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB11D_PDMIC_DAT (1u << 11) /**< \brief Pdmic signal: PDMIC_DAT */\r
+#define PIO_PB26D_PDMIC_DAT (1u << 26) /**< \brief Pdmic signal: PDMIC_DAT */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PC8D_PCK0 (1u << 8) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD19A_PCK0 (1u << 19) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD31E_PCK0 (1u << 31) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13C_PCK1 (1u << 13) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PB20E_PCK1 (1u << 20) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PC27C_PCK1 (1u << 27) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PD6B_PCK1 (1u << 6) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK2 (1u << 21) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PC28C_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD11B_PCK2 (1u << 11) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PB3D_PWMEXTRG0 (1u << 3) /**< \brief Pwm signal: PWMEXTRG0 */\r
+#define PIO_PB10C_PWMEXTRG1 (1u << 10) /**< \brief Pwm signal: PWMEXTRG1 */\r
+#define PIO_PB2D_PWMFI0 (1u << 2) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PB9C_PWMFI1 (1u << 9) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PA30D_PWMH0 (1u << 30) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0D_PWMH1 (1u << 0) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB5C_PWMH2 (1u << 5) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB7C_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA31D_PWML0 (1u << 31) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB1D_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB6C_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB8C_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for QSPI0 peripheral ========== */\r
+#define PIO_PA1B_QSPI0_CS (1u << 1) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA15C_QSPI0_CS (1u << 15) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA23F_QSPI0_CS (1u << 23) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA2B_QSPI0_IO0 (1u << 2) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA16C_QSPI0_IO0 (1u << 16) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA24F_QSPI0_IO0 (1u << 24) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA3B_QSPI0_IO1 (1u << 3) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA17C_QSPI0_IO1 (1u << 17) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA25F_QSPI0_IO1 (1u << 25) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA4B_QSPI0_IO2 (1u << 4) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA18C_QSPI0_IO2 (1u << 18) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA26F_QSPI0_IO2 (1u << 26) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA5B_QSPI0_IO3 (1u << 5) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA19C_QSPI0_IO3 (1u << 19) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA27F_QSPI0_IO3 (1u << 27) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA0B_QSPI0_SCK (1u << 0) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA14C_QSPI0_SCK (1u << 14) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA22F_QSPI0_SCK (1u << 22) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+/* ========== Pio definition for QSPI1 peripheral ========== */\r
+#define PIO_PA11B_QSPI1_CS (1u << 11) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB6D_QSPI1_CS (1u << 6) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB15E_QSPI1_CS (1u << 15) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PA7B_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB7D_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB16E_QSPI1_IO0 (1u << 16) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PA8B_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB8D_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB17E_QSPI1_IO1 (1u << 17) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PA9B_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB9D_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB18E_QSPI1_IO2 (1u << 18) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PA10B_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB10D_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB19E_QSPI1_IO3 (1u << 19) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PA6B_QSPI1_SCK (1u << 6) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB5D_QSPI1_SCK (1u << 5) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB14E_QSPI1_SCK (1u << 14) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+/* ========== Pio definition for SDMMC0 peripheral ========== */\r
+#define PIO_PA13A_SDMMC0_CD (1u << 13) /**< \brief Sdmmc0 signal: SDMMC0_CD */\r
+#define PIO_PA11A_SDMMC0_VDDSEL (1u << 11)/**< \brief Sdmmc0 signal: SDMMC0_VDDSEL */\r
+#define PIO_PA10A_SDMMC0_RSTN (1u << 10) /**< \brief Sdmmc0 signal: SDMMC0_RSTN */\r
+#define PIO_PA0A_SDMMC0_CK (1u << 0) /**< \brief Sdmmc0 signal: SDMMC0_CK */\r
+#define PIO_PA1A_SDMMC0_CMD (1u << 1) /**< \brief Sdmmc0 signal: SDMMC0_CMD */\r
+#define PIO_PA12A_SDMMC0_WP (1u << 12) /**< \brief Sdmmc0 signal: SDMMC0_WP */\r
+#define PIO_PA2A_SDMMC0_DAT0 (1u << 2) /**< \brief Sdmmc0 signal: SDMMC0_DAT0 */\r
+#define PIO_PA3A_SDMMC0_DAT1 (1u << 3) /**< \brief Sdmmc0 signal: SDMMC0_DAT1 */\r
+#define PIO_PA4A_SDMMC0_DAT2 (1u << 4) /**< \brief Sdmmc0 signal: SDMMC0_DAT2 */\r
+#define PIO_PA5A_SDMMC0_DAT3 (1u << 5) /**< \brief Sdmmc0 signal: SDMMC0_DAT3 */\r
+#define PIO_PA6A_SDMMC0_DAT4 (1u << 6) /**< \brief Sdmmc0 signal: SDMMC0_DAT4 */\r
+#define PIO_PA7A_SDMMC0_DAT5 (1u << 7) /**< \brief Sdmmc0 signal: SDMMC0_DAT5 */\r
+#define PIO_PA8A_SDMMC0_DAT6 (1u << 8) /**< \brief Sdmmc0 signal: SDMMC0_DAT6 */\r
+#define PIO_PA9A_SDMMC0_DAT7 (1u << 9) /**< \brief Sdmmc0 signal: SDMMC0_DAT7 */\r
+/* ========== Pio definition for SDMMC1 peripheral ========== */\r
+#define PIO_PA30E_SDMMC1_CD (1u << 30) /**< \brief Sdmmc1 signal: SDMMC1_CD */\r
+#define PIO_PA27E_SDMMC1_RSTN (1u << 27) /**< \brief Sdmmc1 signal: SDMMC1_RSTN */\r
+#define PIO_PA22E_SDMMC1_CK (1u << 22) /**< \brief Sdmmc1 signal: SDMMC1_CK */\r
+#define PIO_PA28E_SDMMC1_CMD (1u << 28) /**< \brief Sdmmc1 signal: SDMMC1_CMD */\r
+#define PIO_PA29E_SDMMC1_WP (1u << 29) /**< \brief Sdmmc1 signal: SDMMC1_WP */\r
+#define PIO_PA18E_SDMMC1_DAT0 (1u << 18) /**< \brief Sdmmc1 signal: SDMMC1_DAT0 */\r
+#define PIO_PA19E_SDMMC1_DAT1 (1u << 19) /**< \brief Sdmmc1 signal: SDMMC1_DAT1 */\r
+#define PIO_PA20E_SDMMC1_DAT2 (1u << 20) /**< \brief Sdmmc1 signal: SDMMC1_DAT2 */\r
+#define PIO_PA21E_SDMMC1_DAT3 (1u << 21) /**< \brief Sdmmc1 signal: SDMMC1_DAT3 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA16A_SPI0_MISO (1u << 16) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA31C_SPI0_MISO (1u << 31) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA15A_SPI0_MOSI (1u << 15) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB0C_SPI0_MOSI (1u << 0) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA17A_SPI0_NPCS0 (1u << 17) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA30C_SPI0_NPCS0 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA18A_SPI0_NPCS1 (1u << 18) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA29C_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA19A_SPI0_NPCS2 (1u << 19) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA27C_SPI0_NPCS2 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA20A_SPI0_NPCS3 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA28C_SPI0_NPCS3 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA14A_SPI0_SPCK (1u << 14) /**< \brief Spi0 signal: SPI0_SPCK */\r
+#define PIO_PB1C_SPI0_SPCK (1u << 1) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PA24D_SPI1_MISO (1u << 24) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC3D_SPI1_MISO (1u << 3) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PD27A_SPI1_MISO (1u << 27) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PA23D_SPI1_MOSI (1u << 23) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC2D_SPI1_MOSI (1u << 2) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PD26A_SPI1_MOSI (1u << 26) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PA25D_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC4D_SPI1_NPCS0 (1u << 4) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PD28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PA26D_SPI1_NPCS1 (1u << 26) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC5D_SPI1_NPCS1 (1u << 5) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PA27D_SPI1_NPCS2 (1u << 27) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC6D_SPI1_NPCS2 (1u << 6) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD30A_SPI1_NPCS2 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PA28D_SPI1_NPCS3 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC7D_SPI1_NPCS3 (1u << 7) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PA22D_SPI1_SPCK (1u << 22) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PC1D_SPI1_SPCK (1u << 1) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PD25A_SPI1_SPCK (1u << 25) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC0 peripheral ========== */\r
+#define PIO_PB23C_RD0 (1u << 23) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PC15E_RD0 (1u << 15) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PB25C_RF0 (1u << 25) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PC17E_RF0 (1u << 17) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PB24C_RK0 (1u << 24) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PC16E_RK0 (1u << 16) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PB22C_TD0 (1u << 22) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PC14E_TD0 (1u << 14) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PB21C_TF0 (1u << 21) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PC13E_TF0 (1u << 13) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PB20C_TK0 (1u << 20) /**< \brief Ssc0 signal: TK0 */\r
+#define PIO_PC12E_TK0 (1u << 12) /**< \brief Ssc0 signal: TK0 */\r
+/* ========== Pio definition for SSC1 peripheral ========== */\r
+#define PIO_PA17B_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PB17C_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PA19B_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PB19C_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PA18B_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PB18C_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PA16B_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PB16C_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PA15B_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PB15C_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PA14B_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+#define PIO_PB14C_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA21D_TCLK0 (1u << 21) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA29A_TCLK1 (1u << 29) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PC5C_TCLK1 (1u << 5) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PD13A_TCLK1 (1u << 13) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PB5A_TCLK2 (1u << 5) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB24D_TCLK2 (1u << 24) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PD22A_TCLK2 (1u << 22) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA19D_TIOA0 (1u << 19) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA27A_TIOA1 (1u << 27) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PC3C_TIOA1 (1u << 3) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PD11A_TIOA1 (1u << 11) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PB6A_TIOA2 (1u << 6) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB22D_TIOA2 (1u << 22) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PD20A_TIOA2 (1u << 20) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA20D_TIOB0 (1u << 20) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA28A_TIOB1 (1u << 28) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PC4C_TIOB1 (1u << 4) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PD12A_TIOB1 (1u << 12) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PB7A_TIOB2 (1u << 7) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PB23D_TIOB2 (1u << 23) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PD21A_TIOB2 (1u << 21) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PB8A_TCLK3 (1u << 8) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PB21D_TCLK3 (1u << 21) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PD31D_TCLK3 (1u << 31) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PA8D_TCLK5 (1u << 8) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB30D_TCLK5 (1u << 30) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB19D_TIOA3 (1u << 19) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PD29D_TIOA3 (1u << 29) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PA9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PA6D_TIOA5 (1u << 6) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB28D_TIOA5 (1u << 28) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB20D_TIOB3 (1u << 20) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PD30D_TIOB3 (1u << 30) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PA10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PA7D_TIOB5 (1u << 7) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PB29D_TIOB5 (1u << 29) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWIHS0 peripheral ========== */\r
+#define PIO_PC0D_TWCK0 (1u << 0) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PC28E_TWCK0 (1u << 28) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD22B_TWCK0 (1u << 22) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD30E_TWCK0 (1u << 30) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PB31D_TWD0 (1u << 31) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PC27E_TWD0 (1u << 27) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD21B_TWD0 (1u << 21) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD29E_TWD0 (1u << 29) /**< \brief Twihs0 signal: TWD0 */\r
+/* ========== Pio definition for TWIHS1 peripheral ========== */\r
+#define PIO_PC7C_TWCK1 (1u << 7) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD20B_TWCK1 (1u << 20) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PC6C_TWD1 (1u << 6) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD19B_TWD1 (1u << 19) /**< \brief Twihs1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PB26C_URXD0 (1u << 26) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PB27C_UTXD0 (1u << 27) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PC7E_URXD1 (1u << 7) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PD2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PC8E_UTXD1 (1u << 8) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD4B_URXD2 (1u << 4) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD19C_URXD2 (1u << 19) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD23A_URXD2 (1u << 23) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD5B_UTXD2 (1u << 5) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD20C_UTXD2 (1u << 20) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD24A_UTXD2 (1u << 24) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PB11C_URXD3 (1u << 11) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC12D_URXD3 (1u << 12) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC31C_URXD3 (1u << 31) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PB12C_UTXD3 (1u << 12) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PC13D_UTXD3 (1u << 13) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD0C_UTXD3 (1u << 0) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PB3A_URXD4 (1u << 3) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PB4A_UTXD4 (1u << 4) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+#define PIO_PD24_IDX 120\r
+#define PIO_PD25_IDX 121\r
+#define PIO_PD26_IDX 122\r
+#define PIO_PD27_IDX 123\r
+#define PIO_PD28_IDX 124\r
+#define PIO_PD29_IDX 125\r
+#define PIO_PD30_IDX 126\r
+#define PIO_PD31_IDX 127\r
+\r
+#endif /* _SAMA5D24_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D26_PIO_\r
+#define _SAMA5D26_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PD19X1_AD0 (1u << 19) /**< \brief Adc signal: AD0 */\r
+#define PIO_PD20X1_AD1 (1u << 20) /**< \brief Adc signal: AD1 */\r
+#define PIO_PD29X1_AD10 (1u << 29) /**< \brief Adc signal: AD10 */\r
+#define PIO_PD30X1_AD11 (1u << 30) /**< \brief Adc signal: AD11 */\r
+#define PIO_PD21X1_AD2 (1u << 21) /**< \brief Adc signal: AD2 */\r
+#define PIO_PD22X1_AD3 (1u << 22) /**< \brief Adc signal: AD3 */\r
+#define PIO_PD23X1_AD4 (1u << 23) /**< \brief Adc signal: AD4 */\r
+#define PIO_PD24X1_AD5 (1u << 24) /**< \brief Adc signal: AD5 */\r
+#define PIO_PD25X1_AD6 (1u << 25) /**< \brief Adc signal: AD6 */\r
+#define PIO_PD26X1_AD7 (1u << 26) /**< \brief Adc signal: AD7 */\r
+#define PIO_PD27X1_AD8 (1u << 27) /**< \brief Adc signal: AD8 */\r
+#define PIO_PD28X1_AD9 (1u << 28) /**< \brief Adc signal: AD9 */\r
+#define PIO_PD31A_ADTRG (1u << 31) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for AIC peripheral ========== */\r
+#define PIO_PB4C_FIQ (1u << 4) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC8C_FIQ (1u << 8) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC9A_FIQ (1u << 9) /**< \brief Aic signal: FIQ */\r
+#define PIO_PD3B_FIQ (1u << 3) /**< \brief Aic signal: FIQ */\r
+#define PIO_PA12B_IRQ (1u << 12) /**< \brief Aic signal: IRQ */\r
+#define PIO_PA21A_IRQ (1u << 21) /**< \brief Aic signal: IRQ */\r
+#define PIO_PB3C_IRQ (1u << 3) /**< \brief Aic signal: IRQ */\r
+#define PIO_PD31C_IRQ (1u << 31) /**< \brief Aic signal: IRQ */\r
+/* ========== Pio definition for ARM peripheral ========== */\r
+#define PIO_PA26C_NTRST (1u << 26) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD10A_NTRST (1u << 10) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD18A_NTRST (1u << 18) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD31B_NTRST (1u << 31) /**< \brief Arm signal: NTRST */\r
+#define PIO_PA22C_TCK (1u << 22) /**< \brief Arm signal: TCK */\r
+#define PIO_PD6A_TCK (1u << 6) /**< \brief Arm signal: TCK */\r
+#define PIO_PD14A_TCK (1u << 14) /**< \brief Arm signal: TCK */\r
+#define PIO_PD27B_TCK (1u << 27) /**< \brief Arm signal: TCK */\r
+#define PIO_PA23C_TDI (1u << 23) /**< \brief Arm signal: TDI */\r
+#define PIO_PD7A_TDI (1u << 7) /**< \brief Arm signal: TDI */\r
+#define PIO_PD15A_TDI (1u << 15) /**< \brief Arm signal: TDI */\r
+#define PIO_PD28B_TDI (1u << 28) /**< \brief Arm signal: TDI */\r
+#define PIO_PA24C_TDO (1u << 24) /**< \brief Arm signal: TDO */\r
+#define PIO_PD8A_TDO (1u << 8) /**< \brief Arm signal: TDO */\r
+#define PIO_PD16A_TDO (1u << 16) /**< \brief Arm signal: TDO */\r
+#define PIO_PD29B_TDO (1u << 29) /**< \brief Arm signal: TDO */\r
+#define PIO_PA25C_TMS (1u << 25) /**< \brief Arm signal: TMS */\r
+#define PIO_PD9A_TMS (1u << 9) /**< \brief Arm signal: TMS */\r
+#define PIO_PD17A_TMS (1u << 17) /**< \brief Arm signal: TMS */\r
+#define PIO_PD30B_TMS (1u << 30) /**< \brief Arm signal: TMS */\r
+/* ========== Pio definition for CLASSD peripheral ========== */\r
+#define PIO_PA28F_CLASSD_L0 (1u << 28) /**< \brief Classd signal: CLASSD_L0 */\r
+#define PIO_PA29F_CLASSD_L1 (1u << 29) /**< \brief Classd signal: CLASSD_L1 */\r
+#define PIO_PA30F_CLASSD_L2 (1u << 30) /**< \brief Classd signal: CLASSD_L2 */\r
+#define PIO_PA31F_CLASSD_L3 (1u << 31) /**< \brief Classd signal: CLASSD_L3 */\r
+#define PIO_PB1F_CLASSD_R0 (1u << 1) /**< \brief Classd signal: CLASSD_R0 */\r
+#define PIO_PB2F_CLASSD_R1 (1u << 2) /**< \brief Classd signal: CLASSD_R1 */\r
+#define PIO_PB3F_CLASSD_R2 (1u << 3) /**< \brief Classd signal: CLASSD_R2 */\r
+#define PIO_PB4F_CLASSD_R3 (1u << 4) /**< \brief Classd signal: CLASSD_R3 */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PB11B_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB11B_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB12B_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC12F_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PB21B_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC21F_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PB22B_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC22F_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PB23B_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC23F_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PB24B_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PC24F_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PB25B_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PC25F_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PB26B_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PC26F_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PB27B_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PC27F_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PB28B_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PC28F_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PB29B_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PC29F_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PB30B_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC30F_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PB13B_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PC13F_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PB31B_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC31F_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PA10F_A21 (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA10F_NANDALE (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_A21 (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_NANDALE (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA11F_A22 (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA11F_NANDCLE (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_A22 (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_NANDCLE (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC0B_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PD0F_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC1B_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PD1F_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PC2B_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PD2F_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PB14B_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC14F_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PB15B_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC15F_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PB16B_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC16F_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PB17B_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC17F_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PB18B_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC18F_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PB19B_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC19F_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PB20B_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC20F_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PA0F_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA22B_D0 (1u << 22) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA1F_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA23B_D1 (1u << 23) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA15F_D10 (1u << 15) /**< \brief Ebi signal: D10 */\r
+#define PIO_PB5B_D10 (1u << 5) /**< \brief Ebi signal: D10 */\r
+#define PIO_PA16F_D11 (1u << 16) /**< \brief Ebi signal: D11 */\r
+#define PIO_PB6B_D11 (1u << 6) /**< \brief Ebi signal: D11 */\r
+#define PIO_PA17F_D12 (1u << 17) /**< \brief Ebi signal: D12 */\r
+#define PIO_PB7B_D12 (1u << 7) /**< \brief Ebi signal: D12 */\r
+#define PIO_PA18F_D13 (1u << 18) /**< \brief Ebi signal: D13 */\r
+#define PIO_PB8B_D13 (1u << 8) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA19F_D14 (1u << 19) /**< \brief Ebi signal: D14 */\r
+#define PIO_PB9B_D14 (1u << 9) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA20F_D15 (1u << 20) /**< \brief Ebi signal: D15 */\r
+#define PIO_PB10B_D15 (1u << 10) /**< \brief Ebi signal: D15 */\r
+#define PIO_PA2F_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA24B_D2 (1u << 24) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA3F_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA25B_D3 (1u << 25) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA4F_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA26B_D4 (1u << 26) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA5F_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA27B_D5 (1u << 27) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA6F_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA28B_D6 (1u << 28) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA7F_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA29B_D7 (1u << 29) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA13F_D8 (1u << 13) /**< \brief Ebi signal: D8 */\r
+#define PIO_PB3B_D8 (1u << 3) /**< \brief Ebi signal: D8 */\r
+#define PIO_PA14F_D9 (1u << 14) /**< \brief Ebi signal: D9 */\r
+#define PIO_PB4B_D9 (1u << 4) /**< \brief Ebi signal: D9 */\r
+#define PIO_PA21F_NANDRDY (1u << 21) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC8B_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PD8F_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC5B_NCS0 (1u << 5) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PD4F_NCS0 (1u << 4) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC6B_NCS1 (1u << 6) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PD5F_NCS1 (1u << 5) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PC7B_NCS2 (1u << 7) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PD6F_NCS2 (1u << 6) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PA9F_NCS3 (1u << 9) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA31B_NCS3 (1u << 31) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA12F_NRD (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PA12F_NANDOE (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NRD (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NANDOE (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PC3B_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PD3F_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PA8F_NWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA8F_NANDWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NANDWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PC4B_NWR1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PC4B_NBS1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NWR1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NBS1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+/* ========== Pio definition for FLEXCOM0 peripheral ========== */\r
+#define PIO_PB28C_FLEXCOM0_IO0 (1u << 28) /**< \brief Flexcom0 signal: FLEXCOM0_IO0 */\r
+#define PIO_PB29C_FLEXCOM0_IO1 (1u << 29) /**< \brief Flexcom0 signal: FLEXCOM0_IO1 */\r
+#define PIO_PB30C_FLEXCOM0_IO2 (1u << 30) /**< \brief Flexcom0 signal: FLEXCOM0_IO2 */\r
+#define PIO_PB31C_FLEXCOM0_IO3 (1u << 31) /**< \brief Flexcom0 signal: FLEXCOM0_IO3 */\r
+#define PIO_PC0C_FLEXCOM0_IO4 (1u << 0) /**< \brief Flexcom0 signal: FLEXCOM0_IO4 */\r
+/* ========== Pio definition for FLEXCOM1 peripheral ========== */\r
+#define PIO_PA24A_FLEXCOM1_IO0 (1u << 24) /**< \brief Flexcom1 signal: FLEXCOM1_IO0 */\r
+#define PIO_PA23A_FLEXCOM1_IO1 (1u << 23) /**< \brief Flexcom1 signal: FLEXCOM1_IO1 */\r
+#define PIO_PA22A_FLEXCOM1_IO2 (1u << 22) /**< \brief Flexcom1 signal: FLEXCOM1_IO2 */\r
+#define PIO_PA25A_FLEXCOM1_IO3 (1u << 25) /**< \brief Flexcom1 signal: FLEXCOM1_IO3 */\r
+#define PIO_PA26A_FLEXCOM1_IO4 (1u << 26) /**< \brief Flexcom1 signal: FLEXCOM1_IO4 */\r
+/* ========== Pio definition for FLEXCOM2 peripheral ========== */\r
+#define PIO_PA6E_FLEXCOM2_IO0 (1u << 6) /**< \brief Flexcom2 signal: FLEXCOM2_IO0 */\r
+#define PIO_PD26C_FLEXCOM2_IO0 (1u << 26) /**< \brief Flexcom2 signal: FLEXCOM2_IO0 */\r
+#define PIO_PA7E_FLEXCOM2_IO1 (1u << 7) /**< \brief Flexcom2 signal: FLEXCOM2_IO1 */\r
+#define PIO_PD27C_FLEXCOM2_IO1 (1u << 27) /**< \brief Flexcom2 signal: FLEXCOM2_IO1 */\r
+#define PIO_PA8E_FLEXCOM2_IO2 (1u << 8) /**< \brief Flexcom2 signal: FLEXCOM2_IO2 */\r
+#define PIO_PD28C_FLEXCOM2_IO2 (1u << 28) /**< \brief Flexcom2 signal: FLEXCOM2_IO2 */\r
+#define PIO_PA9E_FLEXCOM2_IO3 (1u << 9) /**< \brief Flexcom2 signal: FLEXCOM2_IO3 */\r
+#define PIO_PD29C_FLEXCOM2_IO3 (1u << 29) /**< \brief Flexcom2 signal: FLEXCOM2_IO3 */\r
+#define PIO_PA10E_FLEXCOM2_IO4 (1u << 10) /**< \brief Flexcom2 signal: FLEXCOM2_IO4 */\r
+#define PIO_PD30C_FLEXCOM2_IO4 (1u << 30) /**< \brief Flexcom2 signal: FLEXCOM2_IO4 */\r
+/* ========== Pio definition for FLEXCOM3 peripheral ========== */\r
+#define PIO_PA15E_FLEXCOM3_IO0 (1u << 15) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PB23E_FLEXCOM3_IO0 (1u << 23) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PC20E_FLEXCOM3_IO0 (1u << 20) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PA13E_FLEXCOM3_IO1 (1u << 13) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PB22E_FLEXCOM3_IO1 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PC19E_FLEXCOM3_IO1 (1u << 19) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PA14E_FLEXCOM3_IO2 (1u << 14) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PB21E_FLEXCOM3_IO2 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PC18E_FLEXCOM3_IO2 (1u << 18) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PA16E_FLEXCOM3_IO3 (1u << 16) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PB24E_FLEXCOM3_IO3 (1u << 24) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PC21E_FLEXCOM3_IO3 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PA17E_FLEXCOM3_IO4 (1u << 17) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PB25E_FLEXCOM3_IO4 (1u << 25) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PC22E_FLEXCOM3_IO4 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+/* ========== Pio definition for FLEXCOM4 peripheral ========== */\r
+#define PIO_PC28B_FLEXCOM4_IO0 (1u << 28) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD12B_FLEXCOM4_IO0 (1u << 12) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD21C_FLEXCOM4_IO0 (1u << 21) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PC29B_FLEXCOM4_IO1 (1u << 29) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD13B_FLEXCOM4_IO1 (1u << 13) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD22C_FLEXCOM4_IO1 (1u << 22) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PC30B_FLEXCOM4_IO2 (1u << 30) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD14B_FLEXCOM4_IO2 (1u << 14) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD23C_FLEXCOM4_IO2 (1u << 23) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PC31B_FLEXCOM4_IO3 (1u << 31) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD15B_FLEXCOM4_IO3 (1u << 15) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD24C_FLEXCOM4_IO3 (1u << 24) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD0B_FLEXCOM4_IO4 (1u << 0) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD16B_FLEXCOM4_IO4 (1u << 16) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD25C_FLEXCOM4_IO4 (1u << 25) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PB9F_GCOL (1u << 9) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PC23B_GCOL (1u << 23) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD4D_GCOL (1u << 4) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PB8F_GCRS (1u << 8) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PC22B_GCRS (1u << 22) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD3D_GCRS (1u << 3) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PB22F_GMDC (1u << 22) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PC18B_GMDC (1u << 18) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD17D_GMDC (1u << 17) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PB23F_GMDIO (1u << 23) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PC19B_GMDIO (1u << 19) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD18D_GMDIO (1u << 18) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PB18F_GRX0 (1u << 18) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PC14B_GRX0 (1u << 14) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD13D_GRX0 (1u << 13) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PB19F_GRX1 (1u << 19) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PC15B_GRX1 (1u << 15) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD14D_GRX1 (1u << 14) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PB10F_GRX2 (1u << 10) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PC24B_GRX2 (1u << 24) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD5D_GRX2 (1u << 5) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PB11F_GRX3 (1u << 11) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PC25B_GRX3 (1u << 25) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD6D_GRX3 (1u << 6) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PB7F_GRXCK (1u << 7) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PC20B_GRXCK (1u << 20) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD1D_GRXCK (1u << 1) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PB16F_GRXDV (1u << 16) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PC12B_GRXDV (1u << 12) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD11D_GRXDV (1u << 11) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PB17F_GRXER (1u << 17) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PC13B_GRXER (1u << 13) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD12D_GRXER (1u << 12) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB5F_GTSUCOMP (1u << 5) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PC9B_GTSUCOMP (1u << 9) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD0D_GTSUCOMP (1u << 0) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB20F_GTX0 (1u << 20) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PC16B_GTX0 (1u << 16) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD15D_GTX0 (1u << 15) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PB21F_GTX1 (1u << 21) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PC17B_GTX1 (1u << 17) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD16D_GTX1 (1u << 16) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PB12F_GTX2 (1u << 12) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PC26B_GTX2 (1u << 26) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD7D_GTX2 (1u << 7) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PB13F_GTX3 (1u << 13) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PC27B_GTX3 (1u << 27) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD8D_GTX3 (1u << 8) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PB14F_GTXCK (1u << 14) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PC10B_GTXCK (1u << 10) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD9D_GTXCK (1u << 9) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PB15F_GTXEN (1u << 15) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PC11B_GTXEN (1u << 11) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD10D_GTXEN (1u << 10) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PB6F_GTXER (1u << 6) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PC21B_GTXER (1u << 21) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PD2D_GTXER (1u << 2) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for I2SC0 peripheral ========== */\r
+#define PIO_PC1E_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PD19E_I2SC0_CK (1u << 19) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PC4E_I2SC0_DI0 (1u << 4) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PD22E_I2SC0_DI0 (1u << 22) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PC5E_I2SC0_DO0 (1u << 5) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PD23E_I2SC0_DO0 (1u << 23) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PC2E_I2SC0_MCK (1u << 2) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PD20E_I2SC0_MCK (1u << 20) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PC3E_I2SC0_WS (1u << 3) /**< \brief I2sc0 signal: I2SC0_WS */\r
+#define PIO_PD21E_I2SC0_WS (1u << 21) /**< \brief I2sc0 signal: I2SC0_WS */\r
+/* ========== Pio definition for I2SC1 peripheral ========== */\r
+#define PIO_PA15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PB15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PA17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PB17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PA18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PB18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PA14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PB14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PA16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+#define PIO_PB16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+/* ========== Pio definition for ISC peripheral ========== */\r
+#define PIO_PB26F_ISC_D0 (1u << 26) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PC9C_ISC_D0 (1u << 9) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PD7E_ISC_D0 (1u << 7) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PB27F_ISC_D1 (1u << 27) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PC10C_ISC_D1 (1u << 10) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PD8E_ISC_D1 (1u << 8) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PB24F_ISC_D10 (1u << 24) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PC19C_ISC_D10 (1u << 19) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD4E_ISC_D10 (1u << 4) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD18F_ISC_D10 (1u << 18) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PB25F_ISC_D11 (1u << 25) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PC20C_ISC_D11 (1u << 20) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD3E_ISC_D11 (1u << 3) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD19F_ISC_D11 (1u << 19) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PB28F_ISC_D2 (1u << 28) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PC11C_ISC_D2 (1u << 11) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PD9E_ISC_D2 (1u << 9) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PB29F_ISC_D3 (1u << 29) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PC12C_ISC_D3 (1u << 12) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PD10E_ISC_D3 (1u << 10) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PB30F_ISC_D4 (1u << 30) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PC13C_ISC_D4 (1u << 13) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD11E_ISC_D4 (1u << 11) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD12F_ISC_D4 (1u << 12) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PB31F_ISC_D5 (1u << 31) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC14C_ISC_D5 (1u << 14) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD12E_ISC_D5 (1u << 12) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD13F_ISC_D5 (1u << 13) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC0F_ISC_D6 (1u << 0) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC15C_ISC_D6 (1u << 15) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD13E_ISC_D6 (1u << 13) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD14F_ISC_D6 (1u << 14) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC1F_ISC_D7 (1u << 1) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC16C_ISC_D7 (1u << 16) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD14E_ISC_D7 (1u << 14) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD15F_ISC_D7 (1u << 15) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC2F_ISC_D8 (1u << 2) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC17C_ISC_D8 (1u << 17) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD6E_ISC_D8 (1u << 6) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD16F_ISC_D8 (1u << 16) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC3F_ISC_D9 (1u << 3) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC18C_ISC_D9 (1u << 18) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD5E_ISC_D9 (1u << 5) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD17F_ISC_D9 (1u << 17) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC8F_ISC_FIELD (1u << 8) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC25C_ISC_FIELD (1u << 25) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD18E_ISC_FIELD (1u << 18) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD23F_ISC_FIELD (1u << 23) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC6F_ISC_HSYNC (1u << 6) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC23C_ISC_HSYNC (1u << 23) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD17E_ISC_HSYNC (1u << 17) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD22F_ISC_HSYNC (1u << 22) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC7F_ISC_MCK (1u << 7) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC24C_ISC_MCK (1u << 24) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD2E_ISC_MCK (1u << 2) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD11F_ISC_MCK (1u << 11) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC4F_ISC_PCK (1u << 4) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC21C_ISC_PCK (1u << 21) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD15E_ISC_PCK (1u << 15) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD20F_ISC_PCK (1u << 20) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC5F_ISC_VSYNC (1u << 5) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PC22C_ISC_VSYNC (1u << 22) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD16E_ISC_VSYNC (1u << 16) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD21F_ISC_VSYNC (1u << 21) /**< \brief Isc signal: ISC_VSYNC */\r
+/* ========== Pio definition for LCDC peripheral ========== */\r
+#define PIO_PB11A_LCDDAT0 (1u << 11) /**< \brief Lcdc signal: LCDDAT0 */\r
+#define PIO_PB12A_LCDDAT1 (1u << 12) /**< \brief Lcdc signal: LCDDAT1 */\r
+#define PIO_PB21A_LCDDAT10 (1u << 21) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PC16A_LCDDAT10 (1u << 16) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PB22A_LCDDAT11 (1u << 22) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PC17A_LCDDAT11 (1u << 17) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PB23A_LCDDAT12 (1u << 23) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PC18A_LCDDAT12 (1u << 18) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PB24A_LCDDAT13 (1u << 24) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PC19A_LCDDAT13 (1u << 19) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PB25A_LCDDAT14 (1u << 25) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PC20A_LCDDAT14 (1u << 20) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PB26A_LCDDAT15 (1u << 26) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PC21A_LCDDAT15 (1u << 21) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PB27A_LCDDAT16 (1u << 27) /**< \brief Lcdc signal: LCDDAT16 */\r
+#define PIO_PB28A_LCDDAT17 (1u << 28) /**< \brief Lcdc signal: LCDDAT17 */\r
+#define PIO_PB29A_LCDDAT18 (1u << 29) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PC22A_LCDDAT18 (1u << 22) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PB30A_LCDDAT19 (1u << 30) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PC23A_LCDDAT19 (1u << 23) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PB13A_LCDDAT2 (1u << 13) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PC10A_LCDDAT2 (1u << 10) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PB31A_LCDDAT20 (1u << 31) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC24A_LCDDAT20 (1u << 24) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC0A_LCDDAT21 (1u << 0) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC25A_LCDDAT21 (1u << 25) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC1A_LCDDAT22 (1u << 1) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC26A_LCDDAT22 (1u << 26) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC2A_LCDDAT23 (1u << 2) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PC27A_LCDDAT23 (1u << 27) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PB14A_LCDDAT3 (1u << 14) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PC11A_LCDDAT3 (1u << 11) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PB15A_LCDDAT4 (1u << 15) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PC12A_LCDDAT4 (1u << 12) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PB16A_LCDDAT5 (1u << 16) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PC13A_LCDDAT5 (1u << 13) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PB17A_LCDDAT6 (1u << 17) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PC14A_LCDDAT6 (1u << 14) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PB18A_LCDDAT7 (1u << 18) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PC15A_LCDDAT7 (1u << 15) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PB19A_LCDDAT8 (1u << 19) /**< \brief Lcdc signal: LCDDAT8 */\r
+#define PIO_PB20A_LCDDAT9 (1u << 20) /**< \brief Lcdc signal: LCDDAT9 */\r
+#define PIO_PC8A_LCDDEN (1u << 8) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PD1A_LCDDEN (1u << 1) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PC4A_LCDDISP (1u << 4) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC29A_LCDDISP (1u << 29) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC6A_LCDHSYNC (1u << 6) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC31A_LCDHSYNC (1u << 31) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC7A_LCDPCK (1u << 7) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PD0A_LCDPCK (1u << 0) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PC3A_LCDPWM (1u << 3) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC28A_LCDPWM (1u << 28) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC5A_LCDVSYNC (1u << 5) /**< \brief Lcdc signal: LCDVSYNC */\r
+#define PIO_PC30A_LCDVSYNC (1u << 30) /**< \brief Lcdc signal: LCDVSYNC */\r
+/* ========== Pio definition for PDMIC peripheral ========== */\r
+#define PIO_PB12D_PDMIC_CLK (1u << 12) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB27D_PDMIC_CLK (1u << 27) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB11D_PDMIC_DAT (1u << 11) /**< \brief Pdmic signal: PDMIC_DAT */\r
+#define PIO_PB26D_PDMIC_DAT (1u << 26) /**< \brief Pdmic signal: PDMIC_DAT */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PC8D_PCK0 (1u << 8) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD19A_PCK0 (1u << 19) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD31E_PCK0 (1u << 31) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13C_PCK1 (1u << 13) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PB20E_PCK1 (1u << 20) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PC27C_PCK1 (1u << 27) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PD6B_PCK1 (1u << 6) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK2 (1u << 21) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PC28C_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD11B_PCK2 (1u << 11) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PB3D_PWMEXTRG0 (1u << 3) /**< \brief Pwm signal: PWMEXTRG0 */\r
+#define PIO_PB10C_PWMEXTRG1 (1u << 10) /**< \brief Pwm signal: PWMEXTRG1 */\r
+#define PIO_PB2D_PWMFI0 (1u << 2) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PB9C_PWMFI1 (1u << 9) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PA30D_PWMH0 (1u << 30) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0D_PWMH1 (1u << 0) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB5C_PWMH2 (1u << 5) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB7C_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA31D_PWML0 (1u << 31) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB1D_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB6C_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB8C_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for QSPI0 peripheral ========== */\r
+#define PIO_PA1B_QSPI0_CS (1u << 1) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA15C_QSPI0_CS (1u << 15) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA23F_QSPI0_CS (1u << 23) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA2B_QSPI0_IO0 (1u << 2) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA16C_QSPI0_IO0 (1u << 16) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA24F_QSPI0_IO0 (1u << 24) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA3B_QSPI0_IO1 (1u << 3) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA17C_QSPI0_IO1 (1u << 17) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA25F_QSPI0_IO1 (1u << 25) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA4B_QSPI0_IO2 (1u << 4) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA18C_QSPI0_IO2 (1u << 18) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA26F_QSPI0_IO2 (1u << 26) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA5B_QSPI0_IO3 (1u << 5) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA19C_QSPI0_IO3 (1u << 19) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA27F_QSPI0_IO3 (1u << 27) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA0B_QSPI0_SCK (1u << 0) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA14C_QSPI0_SCK (1u << 14) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA22F_QSPI0_SCK (1u << 22) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+/* ========== Pio definition for QSPI1 peripheral ========== */\r
+#define PIO_PA11B_QSPI1_CS (1u << 11) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB6D_QSPI1_CS (1u << 6) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB15E_QSPI1_CS (1u << 15) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PA7B_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB7D_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB16E_QSPI1_IO0 (1u << 16) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PA8B_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB8D_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB17E_QSPI1_IO1 (1u << 17) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PA9B_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB9D_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB18E_QSPI1_IO2 (1u << 18) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PA10B_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB10D_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB19E_QSPI1_IO3 (1u << 19) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PA6B_QSPI1_SCK (1u << 6) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB5D_QSPI1_SCK (1u << 5) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB14E_QSPI1_SCK (1u << 14) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+/* ========== Pio definition for SDMMC0 peripheral ========== */\r
+#define PIO_PA13A_SDMMC0_CD (1u << 13) /**< \brief Sdmmc0 signal: SDMMC0_CD */\r
+#define PIO_PA11A_SDMMC0_VDDSEL (1u << 11)/**< \brief Sdmmc0 signal: SDMMC0_VDDSEL */\r
+#define PIO_PA10A_SDMMC0_RSTN (1u << 10) /**< \brief Sdmmc0 signal: SDMMC0_RSTN */\r
+#define PIO_PA0A_SDMMC0_CK (1u << 0) /**< \brief Sdmmc0 signal: SDMMC0_CK */\r
+#define PIO_PA1A_SDMMC0_CMD (1u << 1) /**< \brief Sdmmc0 signal: SDMMC0_CMD */\r
+#define PIO_PA12A_SDMMC0_WP (1u << 12) /**< \brief Sdmmc0 signal: SDMMC0_WP */\r
+#define PIO_PA2A_SDMMC0_DAT0 (1u << 2) /**< \brief Sdmmc0 signal: SDMMC0_DAT0 */\r
+#define PIO_PA3A_SDMMC0_DAT1 (1u << 3) /**< \brief Sdmmc0 signal: SDMMC0_DAT1 */\r
+#define PIO_PA4A_SDMMC0_DAT2 (1u << 4) /**< \brief Sdmmc0 signal: SDMMC0_DAT2 */\r
+#define PIO_PA5A_SDMMC0_DAT3 (1u << 5) /**< \brief Sdmmc0 signal: SDMMC0_DAT3 */\r
+#define PIO_PA6A_SDMMC0_DAT4 (1u << 6) /**< \brief Sdmmc0 signal: SDMMC0_DAT4 */\r
+#define PIO_PA7A_SDMMC0_DAT5 (1u << 7) /**< \brief Sdmmc0 signal: SDMMC0_DAT5 */\r
+#define PIO_PA8A_SDMMC0_DAT6 (1u << 8) /**< \brief Sdmmc0 signal: SDMMC0_DAT6 */\r
+#define PIO_PA9A_SDMMC0_DAT7 (1u << 9) /**< \brief Sdmmc0 signal: SDMMC0_DAT7 */\r
+/* ========== Pio definition for SDMMC1 peripheral ========== */\r
+#define PIO_PA30E_SDMMC1_CD (1u << 30) /**< \brief Sdmmc1 signal: SDMMC1_CD */\r
+#define PIO_PA27E_SDMMC1_RSTN (1u << 27) /**< \brief Sdmmc1 signal: SDMMC1_RSTN */\r
+#define PIO_PA22E_SDMMC1_CK (1u << 22) /**< \brief Sdmmc1 signal: SDMMC1_CK */\r
+#define PIO_PA28E_SDMMC1_CMD (1u << 28) /**< \brief Sdmmc1 signal: SDMMC1_CMD */\r
+#define PIO_PA29E_SDMMC1_WP (1u << 29) /**< \brief Sdmmc1 signal: SDMMC1_WP */\r
+#define PIO_PA18E_SDMMC1_DAT0 (1u << 18) /**< \brief Sdmmc1 signal: SDMMC1_DAT0 */\r
+#define PIO_PA19E_SDMMC1_DAT1 (1u << 19) /**< \brief Sdmmc1 signal: SDMMC1_DAT1 */\r
+#define PIO_PA20E_SDMMC1_DAT2 (1u << 20) /**< \brief Sdmmc1 signal: SDMMC1_DAT2 */\r
+#define PIO_PA21E_SDMMC1_DAT3 (1u << 21) /**< \brief Sdmmc1 signal: SDMMC1_DAT3 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA16A_SPI0_MISO (1u << 16) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA31C_SPI0_MISO (1u << 31) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA15A_SPI0_MOSI (1u << 15) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB0C_SPI0_MOSI (1u << 0) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA17A_SPI0_NPCS0 (1u << 17) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA30C_SPI0_NPCS0 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA18A_SPI0_NPCS1 (1u << 18) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA29C_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA19A_SPI0_NPCS2 (1u << 19) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA27C_SPI0_NPCS2 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA20A_SPI0_NPCS3 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA28C_SPI0_NPCS3 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA14A_SPI0_SPCK (1u << 14) /**< \brief Spi0 signal: SPI0_SPCK */\r
+#define PIO_PB1C_SPI0_SPCK (1u << 1) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PA24D_SPI1_MISO (1u << 24) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC3D_SPI1_MISO (1u << 3) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PD27A_SPI1_MISO (1u << 27) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PA23D_SPI1_MOSI (1u << 23) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC2D_SPI1_MOSI (1u << 2) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PD26A_SPI1_MOSI (1u << 26) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PA25D_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC4D_SPI1_NPCS0 (1u << 4) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PD28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PA26D_SPI1_NPCS1 (1u << 26) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC5D_SPI1_NPCS1 (1u << 5) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PA27D_SPI1_NPCS2 (1u << 27) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC6D_SPI1_NPCS2 (1u << 6) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD30A_SPI1_NPCS2 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PA28D_SPI1_NPCS3 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC7D_SPI1_NPCS3 (1u << 7) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PA22D_SPI1_SPCK (1u << 22) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PC1D_SPI1_SPCK (1u << 1) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PD25A_SPI1_SPCK (1u << 25) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC0 peripheral ========== */\r
+#define PIO_PB23C_RD0 (1u << 23) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PC15E_RD0 (1u << 15) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PB25C_RF0 (1u << 25) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PC17E_RF0 (1u << 17) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PB24C_RK0 (1u << 24) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PC16E_RK0 (1u << 16) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PB22C_TD0 (1u << 22) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PC14E_TD0 (1u << 14) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PB21C_TF0 (1u << 21) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PC13E_TF0 (1u << 13) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PB20C_TK0 (1u << 20) /**< \brief Ssc0 signal: TK0 */\r
+#define PIO_PC12E_TK0 (1u << 12) /**< \brief Ssc0 signal: TK0 */\r
+/* ========== Pio definition for SSC1 peripheral ========== */\r
+#define PIO_PA17B_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PB17C_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PA19B_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PB19C_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PA18B_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PB18C_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PA16B_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PB16C_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PA15B_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PB15C_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PA14B_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+#define PIO_PB14C_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA21D_TCLK0 (1u << 21) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA29A_TCLK1 (1u << 29) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PC5C_TCLK1 (1u << 5) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PD13A_TCLK1 (1u << 13) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PB5A_TCLK2 (1u << 5) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB24D_TCLK2 (1u << 24) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PD22A_TCLK2 (1u << 22) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA19D_TIOA0 (1u << 19) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA27A_TIOA1 (1u << 27) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PC3C_TIOA1 (1u << 3) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PD11A_TIOA1 (1u << 11) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PB6A_TIOA2 (1u << 6) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB22D_TIOA2 (1u << 22) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PD20A_TIOA2 (1u << 20) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA20D_TIOB0 (1u << 20) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA28A_TIOB1 (1u << 28) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PC4C_TIOB1 (1u << 4) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PD12A_TIOB1 (1u << 12) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PB7A_TIOB2 (1u << 7) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PB23D_TIOB2 (1u << 23) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PD21A_TIOB2 (1u << 21) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PB8A_TCLK3 (1u << 8) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PB21D_TCLK3 (1u << 21) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PD31D_TCLK3 (1u << 31) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PA8D_TCLK5 (1u << 8) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB30D_TCLK5 (1u << 30) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB19D_TIOA3 (1u << 19) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PD29D_TIOA3 (1u << 29) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PA9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PA6D_TIOA5 (1u << 6) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB28D_TIOA5 (1u << 28) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB20D_TIOB3 (1u << 20) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PD30D_TIOB3 (1u << 30) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PA10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PA7D_TIOB5 (1u << 7) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PB29D_TIOB5 (1u << 29) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWIHS0 peripheral ========== */\r
+#define PIO_PC0D_TWCK0 (1u << 0) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PC28E_TWCK0 (1u << 28) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD22B_TWCK0 (1u << 22) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD30E_TWCK0 (1u << 30) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PB31D_TWD0 (1u << 31) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PC27E_TWD0 (1u << 27) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD21B_TWD0 (1u << 21) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD29E_TWD0 (1u << 29) /**< \brief Twihs0 signal: TWD0 */\r
+/* ========== Pio definition for TWIHS1 peripheral ========== */\r
+#define PIO_PC7C_TWCK1 (1u << 7) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD20B_TWCK1 (1u << 20) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PC6C_TWD1 (1u << 6) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD19B_TWD1 (1u << 19) /**< \brief Twihs1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PB26C_URXD0 (1u << 26) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PB27C_UTXD0 (1u << 27) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PC7E_URXD1 (1u << 7) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PD2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PC8E_UTXD1 (1u << 8) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD4B_URXD2 (1u << 4) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD19C_URXD2 (1u << 19) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD23A_URXD2 (1u << 23) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD5B_UTXD2 (1u << 5) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD20C_UTXD2 (1u << 20) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD24A_UTXD2 (1u << 24) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PB11C_URXD3 (1u << 11) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC12D_URXD3 (1u << 12) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC31C_URXD3 (1u << 31) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PB12C_UTXD3 (1u << 12) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PC13D_UTXD3 (1u << 13) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD0C_UTXD3 (1u << 0) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PB3A_URXD4 (1u << 3) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PB4A_UTXD4 (1u << 4) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PC31_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+#define PIO_PD24_IDX 120\r
+#define PIO_PD25_IDX 121\r
+#define PIO_PD26_IDX 122\r
+#define PIO_PD27_IDX 123\r
+#define PIO_PD28_IDX 124\r
+#define PIO_PD29_IDX 125\r
+#define PIO_PD30_IDX 126\r
+#define PIO_PD31_IDX 127\r
+\r
+#endif /* _SAMA5D26_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D27_PIO_\r
+#define _SAMA5D27_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PD19X1_AD0 (1u << 19) /**< \brief Adc signal: AD0 */\r
+#define PIO_PD20X1_AD1 (1u << 20) /**< \brief Adc signal: AD1 */\r
+#define PIO_PD29X1_AD10 (1u << 29) /**< \brief Adc signal: AD10 */\r
+#define PIO_PD30X1_AD11 (1u << 30) /**< \brief Adc signal: AD11 */\r
+#define PIO_PD21X1_AD2 (1u << 21) /**< \brief Adc signal: AD2 */\r
+#define PIO_PD22X1_AD3 (1u << 22) /**< \brief Adc signal: AD3 */\r
+#define PIO_PD23X1_AD4 (1u << 23) /**< \brief Adc signal: AD4 */\r
+#define PIO_PD24X1_AD5 (1u << 24) /**< \brief Adc signal: AD5 */\r
+#define PIO_PD25X1_AD6 (1u << 25) /**< \brief Adc signal: AD6 */\r
+#define PIO_PD26X1_AD7 (1u << 26) /**< \brief Adc signal: AD7 */\r
+#define PIO_PD27X1_AD8 (1u << 27) /**< \brief Adc signal: AD8 */\r
+#define PIO_PD28X1_AD9 (1u << 28) /**< \brief Adc signal: AD9 */\r
+#define PIO_PD31A_ADTRG (1u << 31) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for AIC peripheral ========== */\r
+#define PIO_PB4C_FIQ (1u << 4) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC8C_FIQ (1u << 8) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC9A_FIQ (1u << 9) /**< \brief Aic signal: FIQ */\r
+#define PIO_PD3B_FIQ (1u << 3) /**< \brief Aic signal: FIQ */\r
+#define PIO_PA12B_IRQ (1u << 12) /**< \brief Aic signal: IRQ */\r
+#define PIO_PA21A_IRQ (1u << 21) /**< \brief Aic signal: IRQ */\r
+#define PIO_PB3C_IRQ (1u << 3) /**< \brief Aic signal: IRQ */\r
+#define PIO_PD31C_IRQ (1u << 31) /**< \brief Aic signal: IRQ */\r
+/* ========== Pio definition for ARM peripheral ========== */\r
+#define PIO_PA26C_NTRST (1u << 26) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD10A_NTRST (1u << 10) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD18A_NTRST (1u << 18) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD31B_NTRST (1u << 31) /**< \brief Arm signal: NTRST */\r
+#define PIO_PA22C_TCK (1u << 22) /**< \brief Arm signal: TCK */\r
+#define PIO_PD6A_TCK (1u << 6) /**< \brief Arm signal: TCK */\r
+#define PIO_PD14A_TCK (1u << 14) /**< \brief Arm signal: TCK */\r
+#define PIO_PD27B_TCK (1u << 27) /**< \brief Arm signal: TCK */\r
+#define PIO_PA23C_TDI (1u << 23) /**< \brief Arm signal: TDI */\r
+#define PIO_PD7A_TDI (1u << 7) /**< \brief Arm signal: TDI */\r
+#define PIO_PD15A_TDI (1u << 15) /**< \brief Arm signal: TDI */\r
+#define PIO_PD28B_TDI (1u << 28) /**< \brief Arm signal: TDI */\r
+#define PIO_PA24C_TDO (1u << 24) /**< \brief Arm signal: TDO */\r
+#define PIO_PD8A_TDO (1u << 8) /**< \brief Arm signal: TDO */\r
+#define PIO_PD16A_TDO (1u << 16) /**< \brief Arm signal: TDO */\r
+#define PIO_PD29B_TDO (1u << 29) /**< \brief Arm signal: TDO */\r
+#define PIO_PA25C_TMS (1u << 25) /**< \brief Arm signal: TMS */\r
+#define PIO_PD9A_TMS (1u << 9) /**< \brief Arm signal: TMS */\r
+#define PIO_PD17A_TMS (1u << 17) /**< \brief Arm signal: TMS */\r
+#define PIO_PD30B_TMS (1u << 30) /**< \brief Arm signal: TMS */\r
+/* ========== Pio definition for CLASSD peripheral ========== */\r
+#define PIO_PA28F_CLASSD_L0 (1u << 28) /**< \brief Classd signal: CLASSD_L0 */\r
+#define PIO_PA29F_CLASSD_L1 (1u << 29) /**< \brief Classd signal: CLASSD_L1 */\r
+#define PIO_PA30F_CLASSD_L2 (1u << 30) /**< \brief Classd signal: CLASSD_L2 */\r
+#define PIO_PA31F_CLASSD_L3 (1u << 31) /**< \brief Classd signal: CLASSD_L3 */\r
+#define PIO_PB1F_CLASSD_R0 (1u << 1) /**< \brief Classd signal: CLASSD_R0 */\r
+#define PIO_PB2F_CLASSD_R1 (1u << 2) /**< \brief Classd signal: CLASSD_R1 */\r
+#define PIO_PB3F_CLASSD_R2 (1u << 3) /**< \brief Classd signal: CLASSD_R2 */\r
+#define PIO_PB4F_CLASSD_R3 (1u << 4) /**< \brief Classd signal: CLASSD_R3 */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PB11B_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB11B_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB12B_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC12F_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PB21B_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC21F_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PB22B_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC22F_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PB23B_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC23F_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PB24B_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PC24F_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PB25B_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PC25F_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PB26B_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PC26F_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PB27B_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PC27F_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PB28B_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PC28F_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PB29B_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PC29F_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PB30B_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC30F_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PB13B_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PC13F_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PB31B_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC31F_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PA10F_A21 (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA10F_NANDALE (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_A21 (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_NANDALE (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA11F_A22 (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA11F_NANDCLE (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_A22 (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_NANDCLE (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC0B_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PD0F_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC1B_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PD1F_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PC2B_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PD2F_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PB14B_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC14F_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PB15B_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC15F_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PB16B_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC16F_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PB17B_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC17F_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PB18B_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC18F_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PB19B_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC19F_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PB20B_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC20F_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PA0F_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA22B_D0 (1u << 22) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA1F_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA23B_D1 (1u << 23) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA15F_D10 (1u << 15) /**< \brief Ebi signal: D10 */\r
+#define PIO_PB5B_D10 (1u << 5) /**< \brief Ebi signal: D10 */\r
+#define PIO_PA16F_D11 (1u << 16) /**< \brief Ebi signal: D11 */\r
+#define PIO_PB6B_D11 (1u << 6) /**< \brief Ebi signal: D11 */\r
+#define PIO_PA17F_D12 (1u << 17) /**< \brief Ebi signal: D12 */\r
+#define PIO_PB7B_D12 (1u << 7) /**< \brief Ebi signal: D12 */\r
+#define PIO_PA18F_D13 (1u << 18) /**< \brief Ebi signal: D13 */\r
+#define PIO_PB8B_D13 (1u << 8) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA19F_D14 (1u << 19) /**< \brief Ebi signal: D14 */\r
+#define PIO_PB9B_D14 (1u << 9) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA20F_D15 (1u << 20) /**< \brief Ebi signal: D15 */\r
+#define PIO_PB10B_D15 (1u << 10) /**< \brief Ebi signal: D15 */\r
+#define PIO_PA2F_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA24B_D2 (1u << 24) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA3F_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA25B_D3 (1u << 25) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA4F_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA26B_D4 (1u << 26) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA5F_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA27B_D5 (1u << 27) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA6F_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA28B_D6 (1u << 28) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA7F_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA29B_D7 (1u << 29) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA13F_D8 (1u << 13) /**< \brief Ebi signal: D8 */\r
+#define PIO_PB3B_D8 (1u << 3) /**< \brief Ebi signal: D8 */\r
+#define PIO_PA14F_D9 (1u << 14) /**< \brief Ebi signal: D9 */\r
+#define PIO_PB4B_D9 (1u << 4) /**< \brief Ebi signal: D9 */\r
+#define PIO_PA21F_NANDRDY (1u << 21) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC8B_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PD8F_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC5B_NCS0 (1u << 5) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PD4F_NCS0 (1u << 4) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC6B_NCS1 (1u << 6) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PD5F_NCS1 (1u << 5) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PC7B_NCS2 (1u << 7) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PD6F_NCS2 (1u << 6) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PA9F_NCS3 (1u << 9) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA31B_NCS3 (1u << 31) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA12F_NRD (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PA12F_NANDOE (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NRD (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NANDOE (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PC3B_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PD3F_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PA8F_NWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA8F_NANDWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NANDWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PC4B_NWR1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PC4B_NBS1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NWR1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NBS1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+/* ========== Pio definition for FLEXCOM0 peripheral ========== */\r
+#define PIO_PB28C_FLEXCOM0_IO0 (1u << 28) /**< \brief Flexcom0 signal: FLEXCOM0_IO0 */\r
+#define PIO_PB29C_FLEXCOM0_IO1 (1u << 29) /**< \brief Flexcom0 signal: FLEXCOM0_IO1 */\r
+#define PIO_PB30C_FLEXCOM0_IO2 (1u << 30) /**< \brief Flexcom0 signal: FLEXCOM0_IO2 */\r
+#define PIO_PB31C_FLEXCOM0_IO3 (1u << 31) /**< \brief Flexcom0 signal: FLEXCOM0_IO3 */\r
+#define PIO_PC0C_FLEXCOM0_IO4 (1u << 0) /**< \brief Flexcom0 signal: FLEXCOM0_IO4 */\r
+/* ========== Pio definition for FLEXCOM1 peripheral ========== */\r
+#define PIO_PA24A_FLEXCOM1_IO0 (1u << 24) /**< \brief Flexcom1 signal: FLEXCOM1_IO0 */\r
+#define PIO_PA23A_FLEXCOM1_IO1 (1u << 23) /**< \brief Flexcom1 signal: FLEXCOM1_IO1 */\r
+#define PIO_PA22A_FLEXCOM1_IO2 (1u << 22) /**< \brief Flexcom1 signal: FLEXCOM1_IO2 */\r
+#define PIO_PA25A_FLEXCOM1_IO3 (1u << 25) /**< \brief Flexcom1 signal: FLEXCOM1_IO3 */\r
+#define PIO_PA26A_FLEXCOM1_IO4 (1u << 26) /**< \brief Flexcom1 signal: FLEXCOM1_IO4 */\r
+/* ========== Pio definition for FLEXCOM2 peripheral ========== */\r
+#define PIO_PA6E_FLEXCOM2_IO0 (1u << 6) /**< \brief Flexcom2 signal: FLEXCOM2_IO0 */\r
+#define PIO_PD26C_FLEXCOM2_IO0 (1u << 26) /**< \brief Flexcom2 signal: FLEXCOM2_IO0 */\r
+#define PIO_PA7E_FLEXCOM2_IO1 (1u << 7) /**< \brief Flexcom2 signal: FLEXCOM2_IO1 */\r
+#define PIO_PD27C_FLEXCOM2_IO1 (1u << 27) /**< \brief Flexcom2 signal: FLEXCOM2_IO1 */\r
+#define PIO_PA8E_FLEXCOM2_IO2 (1u << 8) /**< \brief Flexcom2 signal: FLEXCOM2_IO2 */\r
+#define PIO_PD28C_FLEXCOM2_IO2 (1u << 28) /**< \brief Flexcom2 signal: FLEXCOM2_IO2 */\r
+#define PIO_PA9E_FLEXCOM2_IO3 (1u << 9) /**< \brief Flexcom2 signal: FLEXCOM2_IO3 */\r
+#define PIO_PD29C_FLEXCOM2_IO3 (1u << 29) /**< \brief Flexcom2 signal: FLEXCOM2_IO3 */\r
+#define PIO_PA10E_FLEXCOM2_IO4 (1u << 10) /**< \brief Flexcom2 signal: FLEXCOM2_IO4 */\r
+#define PIO_PD30C_FLEXCOM2_IO4 (1u << 30) /**< \brief Flexcom2 signal: FLEXCOM2_IO4 */\r
+/* ========== Pio definition for FLEXCOM3 peripheral ========== */\r
+#define PIO_PA15E_FLEXCOM3_IO0 (1u << 15) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PB23E_FLEXCOM3_IO0 (1u << 23) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PC20E_FLEXCOM3_IO0 (1u << 20) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PA13E_FLEXCOM3_IO1 (1u << 13) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PB22E_FLEXCOM3_IO1 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PC19E_FLEXCOM3_IO1 (1u << 19) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PA14E_FLEXCOM3_IO2 (1u << 14) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PB21E_FLEXCOM3_IO2 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PC18E_FLEXCOM3_IO2 (1u << 18) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PA16E_FLEXCOM3_IO3 (1u << 16) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PB24E_FLEXCOM3_IO3 (1u << 24) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PC21E_FLEXCOM3_IO3 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PA17E_FLEXCOM3_IO4 (1u << 17) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PB25E_FLEXCOM3_IO4 (1u << 25) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PC22E_FLEXCOM3_IO4 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+/* ========== Pio definition for FLEXCOM4 peripheral ========== */\r
+#define PIO_PC28B_FLEXCOM4_IO0 (1u << 28) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD12B_FLEXCOM4_IO0 (1u << 12) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD21C_FLEXCOM4_IO0 (1u << 21) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PC29B_FLEXCOM4_IO1 (1u << 29) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD13B_FLEXCOM4_IO1 (1u << 13) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD22C_FLEXCOM4_IO1 (1u << 22) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PC30B_FLEXCOM4_IO2 (1u << 30) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD14B_FLEXCOM4_IO2 (1u << 14) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD23C_FLEXCOM4_IO2 (1u << 23) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PC31B_FLEXCOM4_IO3 (1u << 31) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD15B_FLEXCOM4_IO3 (1u << 15) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD24C_FLEXCOM4_IO3 (1u << 24) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD0B_FLEXCOM4_IO4 (1u << 0) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD16B_FLEXCOM4_IO4 (1u << 16) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD25C_FLEXCOM4_IO4 (1u << 25) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PB9F_GCOL (1u << 9) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PC23B_GCOL (1u << 23) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD4D_GCOL (1u << 4) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PB8F_GCRS (1u << 8) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PC22B_GCRS (1u << 22) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD3D_GCRS (1u << 3) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PB22F_GMDC (1u << 22) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PC18B_GMDC (1u << 18) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD17D_GMDC (1u << 17) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PB23F_GMDIO (1u << 23) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PC19B_GMDIO (1u << 19) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD18D_GMDIO (1u << 18) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PB18F_GRX0 (1u << 18) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PC14B_GRX0 (1u << 14) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD13D_GRX0 (1u << 13) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PB19F_GRX1 (1u << 19) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PC15B_GRX1 (1u << 15) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD14D_GRX1 (1u << 14) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PB10F_GRX2 (1u << 10) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PC24B_GRX2 (1u << 24) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD5D_GRX2 (1u << 5) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PB11F_GRX3 (1u << 11) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PC25B_GRX3 (1u << 25) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD6D_GRX3 (1u << 6) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PB7F_GRXCK (1u << 7) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PC20B_GRXCK (1u << 20) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD1D_GRXCK (1u << 1) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PB16F_GRXDV (1u << 16) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PC12B_GRXDV (1u << 12) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD11D_GRXDV (1u << 11) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PB17F_GRXER (1u << 17) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PC13B_GRXER (1u << 13) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD12D_GRXER (1u << 12) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB5F_GTSUCOMP (1u << 5) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PC9B_GTSUCOMP (1u << 9) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD0D_GTSUCOMP (1u << 0) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB20F_GTX0 (1u << 20) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PC16B_GTX0 (1u << 16) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD15D_GTX0 (1u << 15) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PB21F_GTX1 (1u << 21) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PC17B_GTX1 (1u << 17) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD16D_GTX1 (1u << 16) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PB12F_GTX2 (1u << 12) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PC26B_GTX2 (1u << 26) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD7D_GTX2 (1u << 7) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PB13F_GTX3 (1u << 13) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PC27B_GTX3 (1u << 27) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD8D_GTX3 (1u << 8) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PB14F_GTXCK (1u << 14) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PC10B_GTXCK (1u << 10) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD9D_GTXCK (1u << 9) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PB15F_GTXEN (1u << 15) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PC11B_GTXEN (1u << 11) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD10D_GTXEN (1u << 10) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PB6F_GTXER (1u << 6) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PC21B_GTXER (1u << 21) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PD2D_GTXER (1u << 2) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for I2SC0 peripheral ========== */\r
+#define PIO_PC1E_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PD19E_I2SC0_CK (1u << 19) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PC4E_I2SC0_DI0 (1u << 4) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PD22E_I2SC0_DI0 (1u << 22) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PC5E_I2SC0_DO0 (1u << 5) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PD23E_I2SC0_DO0 (1u << 23) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PC2E_I2SC0_MCK (1u << 2) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PD20E_I2SC0_MCK (1u << 20) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PC3E_I2SC0_WS (1u << 3) /**< \brief I2sc0 signal: I2SC0_WS */\r
+#define PIO_PD21E_I2SC0_WS (1u << 21) /**< \brief I2sc0 signal: I2SC0_WS */\r
+/* ========== Pio definition for I2SC1 peripheral ========== */\r
+#define PIO_PA15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PB15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PA17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PB17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PA18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PB18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PA14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PB14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PA16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+#define PIO_PB16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+/* ========== Pio definition for ISC peripheral ========== */\r
+#define PIO_PB26F_ISC_D0 (1u << 26) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PC9C_ISC_D0 (1u << 9) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PD7E_ISC_D0 (1u << 7) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PB27F_ISC_D1 (1u << 27) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PC10C_ISC_D1 (1u << 10) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PD8E_ISC_D1 (1u << 8) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PB24F_ISC_D10 (1u << 24) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PC19C_ISC_D10 (1u << 19) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD4E_ISC_D10 (1u << 4) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD18F_ISC_D10 (1u << 18) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PB25F_ISC_D11 (1u << 25) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PC20C_ISC_D11 (1u << 20) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD3E_ISC_D11 (1u << 3) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD19F_ISC_D11 (1u << 19) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PB28F_ISC_D2 (1u << 28) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PC11C_ISC_D2 (1u << 11) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PD9E_ISC_D2 (1u << 9) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PB29F_ISC_D3 (1u << 29) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PC12C_ISC_D3 (1u << 12) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PD10E_ISC_D3 (1u << 10) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PB30F_ISC_D4 (1u << 30) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PC13C_ISC_D4 (1u << 13) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD11E_ISC_D4 (1u << 11) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD12F_ISC_D4 (1u << 12) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PB31F_ISC_D5 (1u << 31) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC14C_ISC_D5 (1u << 14) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD12E_ISC_D5 (1u << 12) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD13F_ISC_D5 (1u << 13) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC0F_ISC_D6 (1u << 0) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC15C_ISC_D6 (1u << 15) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD13E_ISC_D6 (1u << 13) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD14F_ISC_D6 (1u << 14) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC1F_ISC_D7 (1u << 1) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC16C_ISC_D7 (1u << 16) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD14E_ISC_D7 (1u << 14) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD15F_ISC_D7 (1u << 15) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC2F_ISC_D8 (1u << 2) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC17C_ISC_D8 (1u << 17) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD6E_ISC_D8 (1u << 6) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD16F_ISC_D8 (1u << 16) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC3F_ISC_D9 (1u << 3) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC18C_ISC_D9 (1u << 18) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD5E_ISC_D9 (1u << 5) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD17F_ISC_D9 (1u << 17) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC8F_ISC_FIELD (1u << 8) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC25C_ISC_FIELD (1u << 25) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD18E_ISC_FIELD (1u << 18) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD23F_ISC_FIELD (1u << 23) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC6F_ISC_HSYNC (1u << 6) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC23C_ISC_HSYNC (1u << 23) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD17E_ISC_HSYNC (1u << 17) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD22F_ISC_HSYNC (1u << 22) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC7F_ISC_MCK (1u << 7) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC24C_ISC_MCK (1u << 24) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD2E_ISC_MCK (1u << 2) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD11F_ISC_MCK (1u << 11) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC4F_ISC_PCK (1u << 4) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC21C_ISC_PCK (1u << 21) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD15E_ISC_PCK (1u << 15) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD20F_ISC_PCK (1u << 20) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC5F_ISC_VSYNC (1u << 5) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PC22C_ISC_VSYNC (1u << 22) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD16E_ISC_VSYNC (1u << 16) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD21F_ISC_VSYNC (1u << 21) /**< \brief Isc signal: ISC_VSYNC */\r
+/* ========== Pio definition for LCDC peripheral ========== */\r
+#define PIO_PB11A_LCDDAT0 (1u << 11) /**< \brief Lcdc signal: LCDDAT0 */\r
+#define PIO_PB12A_LCDDAT1 (1u << 12) /**< \brief Lcdc signal: LCDDAT1 */\r
+#define PIO_PB21A_LCDDAT10 (1u << 21) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PC16A_LCDDAT10 (1u << 16) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PB22A_LCDDAT11 (1u << 22) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PC17A_LCDDAT11 (1u << 17) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PB23A_LCDDAT12 (1u << 23) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PC18A_LCDDAT12 (1u << 18) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PB24A_LCDDAT13 (1u << 24) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PC19A_LCDDAT13 (1u << 19) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PB25A_LCDDAT14 (1u << 25) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PC20A_LCDDAT14 (1u << 20) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PB26A_LCDDAT15 (1u << 26) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PC21A_LCDDAT15 (1u << 21) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PB27A_LCDDAT16 (1u << 27) /**< \brief Lcdc signal: LCDDAT16 */\r
+#define PIO_PB28A_LCDDAT17 (1u << 28) /**< \brief Lcdc signal: LCDDAT17 */\r
+#define PIO_PB29A_LCDDAT18 (1u << 29) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PC22A_LCDDAT18 (1u << 22) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PB30A_LCDDAT19 (1u << 30) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PC23A_LCDDAT19 (1u << 23) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PB13A_LCDDAT2 (1u << 13) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PC10A_LCDDAT2 (1u << 10) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PB31A_LCDDAT20 (1u << 31) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC24A_LCDDAT20 (1u << 24) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC0A_LCDDAT21 (1u << 0) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC25A_LCDDAT21 (1u << 25) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC1A_LCDDAT22 (1u << 1) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC26A_LCDDAT22 (1u << 26) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC2A_LCDDAT23 (1u << 2) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PC27A_LCDDAT23 (1u << 27) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PB14A_LCDDAT3 (1u << 14) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PC11A_LCDDAT3 (1u << 11) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PB15A_LCDDAT4 (1u << 15) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PC12A_LCDDAT4 (1u << 12) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PB16A_LCDDAT5 (1u << 16) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PC13A_LCDDAT5 (1u << 13) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PB17A_LCDDAT6 (1u << 17) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PC14A_LCDDAT6 (1u << 14) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PB18A_LCDDAT7 (1u << 18) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PC15A_LCDDAT7 (1u << 15) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PB19A_LCDDAT8 (1u << 19) /**< \brief Lcdc signal: LCDDAT8 */\r
+#define PIO_PB20A_LCDDAT9 (1u << 20) /**< \brief Lcdc signal: LCDDAT9 */\r
+#define PIO_PC8A_LCDDEN (1u << 8) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PD1A_LCDDEN (1u << 1) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PC4A_LCDDISP (1u << 4) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC29A_LCDDISP (1u << 29) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC6A_LCDHSYNC (1u << 6) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC31A_LCDHSYNC (1u << 31) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC7A_LCDPCK (1u << 7) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PD0A_LCDPCK (1u << 0) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PC3A_LCDPWM (1u << 3) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC28A_LCDPWM (1u << 28) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC5A_LCDVSYNC (1u << 5) /**< \brief Lcdc signal: LCDVSYNC */\r
+#define PIO_PC30A_LCDVSYNC (1u << 30) /**< \brief Lcdc signal: LCDVSYNC */\r
+/* ========== Pio definition for MCAN0 peripheral ========== */\r
+#define PIO_PC2C_CANRX0 (1u << 2) /**< \brief Mcan0 signal: CANRX0 */\r
+#define PIO_PC11E_CANRX0 (1u << 11) /**< \brief Mcan0 signal: CANRX0 */\r
+#define PIO_PC1C_CANTX0 (1u << 1) /**< \brief Mcan0 signal: CANTX0 */\r
+#define PIO_PC10E_CANTX0 (1u << 10) /**< \brief Mcan0 signal: CANTX0 */\r
+/* ========== Pio definition for MCAN1 peripheral ========== */\r
+#define PIO_PC27D_CANRX1 (1u << 27) /**< \brief Mcan1 signal: CANRX1 */\r
+#define PIO_PC26D_CANTX1 (1u << 26) /**< \brief Mcan1 signal: CANTX1 */\r
+/* ========== Pio definition for PDMIC peripheral ========== */\r
+#define PIO_PB12D_PDMIC_CLK (1u << 12) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB27D_PDMIC_CLK (1u << 27) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB11D_PDMIC_DAT (1u << 11) /**< \brief Pdmic signal: PDMIC_DAT */\r
+#define PIO_PB26D_PDMIC_DAT (1u << 26) /**< \brief Pdmic signal: PDMIC_DAT */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PC8D_PCK0 (1u << 8) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD19A_PCK0 (1u << 19) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD31E_PCK0 (1u << 31) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13C_PCK1 (1u << 13) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PB20E_PCK1 (1u << 20) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PC27C_PCK1 (1u << 27) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PD6B_PCK1 (1u << 6) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK2 (1u << 21) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PC28C_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD11B_PCK2 (1u << 11) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PB3D_PWMEXTRG0 (1u << 3) /**< \brief Pwm signal: PWMEXTRG0 */\r
+#define PIO_PB10C_PWMEXTRG1 (1u << 10) /**< \brief Pwm signal: PWMEXTRG1 */\r
+#define PIO_PB2D_PWMFI0 (1u << 2) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PB9C_PWMFI1 (1u << 9) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PA30D_PWMH0 (1u << 30) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0D_PWMH1 (1u << 0) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB5C_PWMH2 (1u << 5) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB7C_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA31D_PWML0 (1u << 31) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB1D_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB6C_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB8C_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for QSPI0 peripheral ========== */\r
+#define PIO_PA1B_QSPI0_CS (1u << 1) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA15C_QSPI0_CS (1u << 15) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA23F_QSPI0_CS (1u << 23) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA2B_QSPI0_IO0 (1u << 2) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA16C_QSPI0_IO0 (1u << 16) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA24F_QSPI0_IO0 (1u << 24) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA3B_QSPI0_IO1 (1u << 3) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA17C_QSPI0_IO1 (1u << 17) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA25F_QSPI0_IO1 (1u << 25) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA4B_QSPI0_IO2 (1u << 4) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA18C_QSPI0_IO2 (1u << 18) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA26F_QSPI0_IO2 (1u << 26) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA5B_QSPI0_IO3 (1u << 5) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA19C_QSPI0_IO3 (1u << 19) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA27F_QSPI0_IO3 (1u << 27) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA0B_QSPI0_SCK (1u << 0) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA14C_QSPI0_SCK (1u << 14) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA22F_QSPI0_SCK (1u << 22) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+/* ========== Pio definition for QSPI1 peripheral ========== */\r
+#define PIO_PA11B_QSPI1_CS (1u << 11) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB6D_QSPI1_CS (1u << 6) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB15E_QSPI1_CS (1u << 15) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PA7B_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB7D_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB16E_QSPI1_IO0 (1u << 16) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PA8B_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB8D_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB17E_QSPI1_IO1 (1u << 17) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PA9B_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB9D_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB18E_QSPI1_IO2 (1u << 18) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PA10B_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB10D_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB19E_QSPI1_IO3 (1u << 19) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PA6B_QSPI1_SCK (1u << 6) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB5D_QSPI1_SCK (1u << 5) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB14E_QSPI1_SCK (1u << 14) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+/* ========== Pio definition for SDMMC0 peripheral ========== */\r
+#define PIO_PA13A_SDMMC0_CD (1u << 13) /**< \brief Sdmmc0 signal: SDMMC0_CD */\r
+#define PIO_PA11A_SDMMC0_VDDSEL (1u << 11)/**< \brief Sdmmc0 signal: SDMMC0_VDDSEL */\r
+#define PIO_PA10A_SDMMC0_RSTN (1u << 10) /**< \brief Sdmmc0 signal: SDMMC0_RSTN */\r
+#define PIO_PA0A_SDMMC0_CK (1u << 0) /**< \brief Sdmmc0 signal: SDMMC0_CK */\r
+#define PIO_PA1A_SDMMC0_CMD (1u << 1) /**< \brief Sdmmc0 signal: SDMMC0_CMD */\r
+#define PIO_PA12A_SDMMC0_WP (1u << 12) /**< \brief Sdmmc0 signal: SDMMC0_WP */\r
+#define PIO_PA2A_SDMMC0_DAT0 (1u << 2) /**< \brief Sdmmc0 signal: SDMMC0_DAT0 */\r
+#define PIO_PA3A_SDMMC0_DAT1 (1u << 3) /**< \brief Sdmmc0 signal: SDMMC0_DAT1 */\r
+#define PIO_PA4A_SDMMC0_DAT2 (1u << 4) /**< \brief Sdmmc0 signal: SDMMC0_DAT2 */\r
+#define PIO_PA5A_SDMMC0_DAT3 (1u << 5) /**< \brief Sdmmc0 signal: SDMMC0_DAT3 */\r
+#define PIO_PA6A_SDMMC0_DAT4 (1u << 6) /**< \brief Sdmmc0 signal: SDMMC0_DAT4 */\r
+#define PIO_PA7A_SDMMC0_DAT5 (1u << 7) /**< \brief Sdmmc0 signal: SDMMC0_DAT5 */\r
+#define PIO_PA8A_SDMMC0_DAT6 (1u << 8) /**< \brief Sdmmc0 signal: SDMMC0_DAT6 */\r
+#define PIO_PA9A_SDMMC0_DAT7 (1u << 9) /**< \brief Sdmmc0 signal: SDMMC0_DAT7 */\r
+/* ========== Pio definition for SDMMC1 peripheral ========== */\r
+#define PIO_PA30E_SDMMC1_CD (1u << 30) /**< \brief Sdmmc1 signal: SDMMC1_CD */\r
+#define PIO_PA27E_SDMMC1_RSTN (1u << 27) /**< \brief Sdmmc1 signal: SDMMC1_RSTN */\r
+#define PIO_PA22E_SDMMC1_CK (1u << 22) /**< \brief Sdmmc1 signal: SDMMC1_CK */\r
+#define PIO_PA28E_SDMMC1_CMD (1u << 28) /**< \brief Sdmmc1 signal: SDMMC1_CMD */\r
+#define PIO_PA29E_SDMMC1_WP (1u << 29) /**< \brief Sdmmc1 signal: SDMMC1_WP */\r
+#define PIO_PA18E_SDMMC1_DAT0 (1u << 18) /**< \brief Sdmmc1 signal: SDMMC1_DAT0 */\r
+#define PIO_PA19E_SDMMC1_DAT1 (1u << 19) /**< \brief Sdmmc1 signal: SDMMC1_DAT1 */\r
+#define PIO_PA20E_SDMMC1_DAT2 (1u << 20) /**< \brief Sdmmc1 signal: SDMMC1_DAT2 */\r
+#define PIO_PA21E_SDMMC1_DAT3 (1u << 21) /**< \brief Sdmmc1 signal: SDMMC1_DAT3 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA16A_SPI0_MISO (1u << 16) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA31C_SPI0_MISO (1u << 31) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA15A_SPI0_MOSI (1u << 15) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB0C_SPI0_MOSI (1u << 0) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA17A_SPI0_NPCS0 (1u << 17) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA30C_SPI0_NPCS0 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA18A_SPI0_NPCS1 (1u << 18) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA29C_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA19A_SPI0_NPCS2 (1u << 19) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA27C_SPI0_NPCS2 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA20A_SPI0_NPCS3 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA28C_SPI0_NPCS3 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA14A_SPI0_SPCK (1u << 14) /**< \brief Spi0 signal: SPI0_SPCK */\r
+#define PIO_PB1C_SPI0_SPCK (1u << 1) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PA24D_SPI1_MISO (1u << 24) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC3D_SPI1_MISO (1u << 3) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PD27A_SPI1_MISO (1u << 27) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PA23D_SPI1_MOSI (1u << 23) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC2D_SPI1_MOSI (1u << 2) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PD26A_SPI1_MOSI (1u << 26) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PA25D_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC4D_SPI1_NPCS0 (1u << 4) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PD28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PA26D_SPI1_NPCS1 (1u << 26) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC5D_SPI1_NPCS1 (1u << 5) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PA27D_SPI1_NPCS2 (1u << 27) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC6D_SPI1_NPCS2 (1u << 6) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD30A_SPI1_NPCS2 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PA28D_SPI1_NPCS3 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC7D_SPI1_NPCS3 (1u << 7) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PA22D_SPI1_SPCK (1u << 22) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PC1D_SPI1_SPCK (1u << 1) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PD25A_SPI1_SPCK (1u << 25) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC0 peripheral ========== */\r
+#define PIO_PB23C_RD0 (1u << 23) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PC15E_RD0 (1u << 15) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PB25C_RF0 (1u << 25) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PC17E_RF0 (1u << 17) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PB24C_RK0 (1u << 24) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PC16E_RK0 (1u << 16) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PB22C_TD0 (1u << 22) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PC14E_TD0 (1u << 14) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PB21C_TF0 (1u << 21) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PC13E_TF0 (1u << 13) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PB20C_TK0 (1u << 20) /**< \brief Ssc0 signal: TK0 */\r
+#define PIO_PC12E_TK0 (1u << 12) /**< \brief Ssc0 signal: TK0 */\r
+/* ========== Pio definition for SSC1 peripheral ========== */\r
+#define PIO_PA17B_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PB17C_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PA19B_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PB19C_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PA18B_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PB18C_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PA16B_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PB16C_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PA15B_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PB15C_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PA14B_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+#define PIO_PB14C_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA21D_TCLK0 (1u << 21) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA29A_TCLK1 (1u << 29) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PC5C_TCLK1 (1u << 5) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PD13A_TCLK1 (1u << 13) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PB5A_TCLK2 (1u << 5) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB24D_TCLK2 (1u << 24) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PD22A_TCLK2 (1u << 22) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA19D_TIOA0 (1u << 19) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA27A_TIOA1 (1u << 27) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PC3C_TIOA1 (1u << 3) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PD11A_TIOA1 (1u << 11) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PB6A_TIOA2 (1u << 6) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB22D_TIOA2 (1u << 22) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PD20A_TIOA2 (1u << 20) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA20D_TIOB0 (1u << 20) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA28A_TIOB1 (1u << 28) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PC4C_TIOB1 (1u << 4) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PD12A_TIOB1 (1u << 12) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PB7A_TIOB2 (1u << 7) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PB23D_TIOB2 (1u << 23) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PD21A_TIOB2 (1u << 21) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PB8A_TCLK3 (1u << 8) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PB21D_TCLK3 (1u << 21) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PD31D_TCLK3 (1u << 31) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PA8D_TCLK5 (1u << 8) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB30D_TCLK5 (1u << 30) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB19D_TIOA3 (1u << 19) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PD29D_TIOA3 (1u << 29) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PA9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PA6D_TIOA5 (1u << 6) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB28D_TIOA5 (1u << 28) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB20D_TIOB3 (1u << 20) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PD30D_TIOB3 (1u << 30) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PA10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PA7D_TIOB5 (1u << 7) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PB29D_TIOB5 (1u << 29) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWIHS0 peripheral ========== */\r
+#define PIO_PC0D_TWCK0 (1u << 0) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PC28E_TWCK0 (1u << 28) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD22B_TWCK0 (1u << 22) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD30E_TWCK0 (1u << 30) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PB31D_TWD0 (1u << 31) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PC27E_TWD0 (1u << 27) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD21B_TWD0 (1u << 21) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD29E_TWD0 (1u << 29) /**< \brief Twihs0 signal: TWD0 */\r
+/* ========== Pio definition for TWIHS1 peripheral ========== */\r
+#define PIO_PC7C_TWCK1 (1u << 7) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD20B_TWCK1 (1u << 20) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PC6C_TWD1 (1u << 6) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD19B_TWD1 (1u << 19) /**< \brief Twihs1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PB26C_URXD0 (1u << 26) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PB27C_UTXD0 (1u << 27) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PC7E_URXD1 (1u << 7) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PD2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PC8E_UTXD1 (1u << 8) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD4B_URXD2 (1u << 4) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD19C_URXD2 (1u << 19) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD23A_URXD2 (1u << 23) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD5B_UTXD2 (1u << 5) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD20C_UTXD2 (1u << 20) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD24A_UTXD2 (1u << 24) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PB11C_URXD3 (1u << 11) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC12D_URXD3 (1u << 12) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC31C_URXD3 (1u << 31) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PB12C_UTXD3 (1u << 12) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PC13D_UTXD3 (1u << 13) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD0C_UTXD3 (1u << 0) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PB3A_URXD4 (1u << 3) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PB4A_UTXD4 (1u << 4) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PC31_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+#define PIO_PD24_IDX 120\r
+#define PIO_PD25_IDX 121\r
+#define PIO_PD26_IDX 122\r
+#define PIO_PD27_IDX 123\r
+#define PIO_PD28_IDX 124\r
+#define PIO_PD29_IDX 125\r
+#define PIO_PD30_IDX 126\r
+#define PIO_PD31_IDX 127\r
+\r
+#endif /* _SAMA5D27_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D28_PIO_\r
+#define _SAMA5D28_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PD19X1_AD0 (1u << 19) /**< \brief Adc signal: AD0 */\r
+#define PIO_PD20X1_AD1 (1u << 20) /**< \brief Adc signal: AD1 */\r
+#define PIO_PD29X1_AD10 (1u << 29) /**< \brief Adc signal: AD10 */\r
+#define PIO_PD30X1_AD11 (1u << 30) /**< \brief Adc signal: AD11 */\r
+#define PIO_PD21X1_AD2 (1u << 21) /**< \brief Adc signal: AD2 */\r
+#define PIO_PD22X1_AD3 (1u << 22) /**< \brief Adc signal: AD3 */\r
+#define PIO_PD23X1_AD4 (1u << 23) /**< \brief Adc signal: AD4 */\r
+#define PIO_PD24X1_AD5 (1u << 24) /**< \brief Adc signal: AD5 */\r
+#define PIO_PD25X1_AD6 (1u << 25) /**< \brief Adc signal: AD6 */\r
+#define PIO_PD26X1_AD7 (1u << 26) /**< \brief Adc signal: AD7 */\r
+#define PIO_PD27X1_AD8 (1u << 27) /**< \brief Adc signal: AD8 */\r
+#define PIO_PD28X1_AD9 (1u << 28) /**< \brief Adc signal: AD9 */\r
+#define PIO_PD31A_ADTRG (1u << 31) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for AIC peripheral ========== */\r
+#define PIO_PB4C_FIQ (1u << 4) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC8C_FIQ (1u << 8) /**< \brief Aic signal: FIQ */\r
+#define PIO_PC9A_FIQ (1u << 9) /**< \brief Aic signal: FIQ */\r
+#define PIO_PD3B_FIQ (1u << 3) /**< \brief Aic signal: FIQ */\r
+#define PIO_PA12B_IRQ (1u << 12) /**< \brief Aic signal: IRQ */\r
+#define PIO_PA21A_IRQ (1u << 21) /**< \brief Aic signal: IRQ */\r
+#define PIO_PB3C_IRQ (1u << 3) /**< \brief Aic signal: IRQ */\r
+#define PIO_PD31C_IRQ (1u << 31) /**< \brief Aic signal: IRQ */\r
+/* ========== Pio definition for ARM peripheral ========== */\r
+#define PIO_PA26C_NTRST (1u << 26) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD10A_NTRST (1u << 10) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD18A_NTRST (1u << 18) /**< \brief Arm signal: NTRST */\r
+#define PIO_PD31B_NTRST (1u << 31) /**< \brief Arm signal: NTRST */\r
+#define PIO_PA22C_TCK (1u << 22) /**< \brief Arm signal: TCK */\r
+#define PIO_PD6A_TCK (1u << 6) /**< \brief Arm signal: TCK */\r
+#define PIO_PD14A_TCK (1u << 14) /**< \brief Arm signal: TCK */\r
+#define PIO_PD27B_TCK (1u << 27) /**< \brief Arm signal: TCK */\r
+#define PIO_PA23C_TDI (1u << 23) /**< \brief Arm signal: TDI */\r
+#define PIO_PD7A_TDI (1u << 7) /**< \brief Arm signal: TDI */\r
+#define PIO_PD15A_TDI (1u << 15) /**< \brief Arm signal: TDI */\r
+#define PIO_PD28B_TDI (1u << 28) /**< \brief Arm signal: TDI */\r
+#define PIO_PA24C_TDO (1u << 24) /**< \brief Arm signal: TDO */\r
+#define PIO_PD8A_TDO (1u << 8) /**< \brief Arm signal: TDO */\r
+#define PIO_PD16A_TDO (1u << 16) /**< \brief Arm signal: TDO */\r
+#define PIO_PD29B_TDO (1u << 29) /**< \brief Arm signal: TDO */\r
+#define PIO_PA25C_TMS (1u << 25) /**< \brief Arm signal: TMS */\r
+#define PIO_PD9A_TMS (1u << 9) /**< \brief Arm signal: TMS */\r
+#define PIO_PD17A_TMS (1u << 17) /**< \brief Arm signal: TMS */\r
+#define PIO_PD30B_TMS (1u << 30) /**< \brief Arm signal: TMS */\r
+/* ========== Pio definition for CLASSD peripheral ========== */\r
+#define PIO_PA28F_CLASSD_L0 (1u << 28) /**< \brief Classd signal: CLASSD_L0 */\r
+#define PIO_PA29F_CLASSD_L1 (1u << 29) /**< \brief Classd signal: CLASSD_L1 */\r
+#define PIO_PA30F_CLASSD_L2 (1u << 30) /**< \brief Classd signal: CLASSD_L2 */\r
+#define PIO_PA31F_CLASSD_L3 (1u << 31) /**< \brief Classd signal: CLASSD_L3 */\r
+#define PIO_PB1F_CLASSD_R0 (1u << 1) /**< \brief Classd signal: CLASSD_R0 */\r
+#define PIO_PB2F_CLASSD_R1 (1u << 2) /**< \brief Classd signal: CLASSD_R1 */\r
+#define PIO_PB3F_CLASSD_R2 (1u << 3) /**< \brief Classd signal: CLASSD_R2 */\r
+#define PIO_PB4F_CLASSD_R3 (1u << 4) /**< \brief Classd signal: CLASSD_R3 */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PB11B_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB11B_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_A0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC11F_NBS0 (1u << 11) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PB12B_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC12F_A1 (1u << 12) /**< \brief Ebi signal: A1 */\r
+#define PIO_PB21B_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC21F_A10 (1u << 21) /**< \brief Ebi signal: A10 */\r
+#define PIO_PB22B_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC22F_A11 (1u << 22) /**< \brief Ebi signal: A11 */\r
+#define PIO_PB23B_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC23F_A12 (1u << 23) /**< \brief Ebi signal: A12 */\r
+#define PIO_PB24B_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PC24F_A13 (1u << 24) /**< \brief Ebi signal: A13 */\r
+#define PIO_PB25B_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PC25F_A14 (1u << 25) /**< \brief Ebi signal: A14 */\r
+#define PIO_PB26B_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PC26F_A15 (1u << 26) /**< \brief Ebi signal: A15 */\r
+#define PIO_PB27B_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PC27F_A16 (1u << 27) /**< \brief Ebi signal: A16 */\r
+#define PIO_PB28B_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PC28F_A17 (1u << 28) /**< \brief Ebi signal: A17 */\r
+#define PIO_PB29B_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PC29F_A18 (1u << 29) /**< \brief Ebi signal: A18 */\r
+#define PIO_PB30B_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC30F_A19 (1u << 30) /**< \brief Ebi signal: A19 */\r
+#define PIO_PB13B_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PC13F_A2 (1u << 13) /**< \brief Ebi signal: A2 */\r
+#define PIO_PB31B_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC31F_A20 (1u << 31) /**< \brief Ebi signal: A20 */\r
+#define PIO_PA10F_A21 (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA10F_NANDALE (1u << 10) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_A21 (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PB0B_NANDALE (1u << 0) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PA11F_A22 (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA11F_NANDCLE (1u << 11) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_A22 (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PB1B_NANDCLE (1u << 1) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC0B_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PD0F_A23 (1u << 0) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC1B_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PD1F_A24 (1u << 1) /**< \brief Ebi signal: A24 */\r
+#define PIO_PC2B_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PD2F_A25 (1u << 2) /**< \brief Ebi signal: A25 */\r
+#define PIO_PB14B_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC14F_A3 (1u << 14) /**< \brief Ebi signal: A3 */\r
+#define PIO_PB15B_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC15F_A4 (1u << 15) /**< \brief Ebi signal: A4 */\r
+#define PIO_PB16B_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC16F_A5 (1u << 16) /**< \brief Ebi signal: A5 */\r
+#define PIO_PB17B_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC17F_A6 (1u << 17) /**< \brief Ebi signal: A6 */\r
+#define PIO_PB18B_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC18F_A7 (1u << 18) /**< \brief Ebi signal: A7 */\r
+#define PIO_PB19B_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC19F_A8 (1u << 19) /**< \brief Ebi signal: A8 */\r
+#define PIO_PB20B_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC20F_A9 (1u << 20) /**< \brief Ebi signal: A9 */\r
+#define PIO_PA0F_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA22B_D0 (1u << 22) /**< \brief Ebi signal: D0 */\r
+#define PIO_PA1F_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA23B_D1 (1u << 23) /**< \brief Ebi signal: D1 */\r
+#define PIO_PA15F_D10 (1u << 15) /**< \brief Ebi signal: D10 */\r
+#define PIO_PB5B_D10 (1u << 5) /**< \brief Ebi signal: D10 */\r
+#define PIO_PA16F_D11 (1u << 16) /**< \brief Ebi signal: D11 */\r
+#define PIO_PB6B_D11 (1u << 6) /**< \brief Ebi signal: D11 */\r
+#define PIO_PA17F_D12 (1u << 17) /**< \brief Ebi signal: D12 */\r
+#define PIO_PB7B_D12 (1u << 7) /**< \brief Ebi signal: D12 */\r
+#define PIO_PA18F_D13 (1u << 18) /**< \brief Ebi signal: D13 */\r
+#define PIO_PB8B_D13 (1u << 8) /**< \brief Ebi signal: D13 */\r
+#define PIO_PA19F_D14 (1u << 19) /**< \brief Ebi signal: D14 */\r
+#define PIO_PB9B_D14 (1u << 9) /**< \brief Ebi signal: D14 */\r
+#define PIO_PA20F_D15 (1u << 20) /**< \brief Ebi signal: D15 */\r
+#define PIO_PB10B_D15 (1u << 10) /**< \brief Ebi signal: D15 */\r
+#define PIO_PA2F_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA24B_D2 (1u << 24) /**< \brief Ebi signal: D2 */\r
+#define PIO_PA3F_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA25B_D3 (1u << 25) /**< \brief Ebi signal: D3 */\r
+#define PIO_PA4F_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA26B_D4 (1u << 26) /**< \brief Ebi signal: D4 */\r
+#define PIO_PA5F_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA27B_D5 (1u << 27) /**< \brief Ebi signal: D5 */\r
+#define PIO_PA6F_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA28B_D6 (1u << 28) /**< \brief Ebi signal: D6 */\r
+#define PIO_PA7F_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA29B_D7 (1u << 29) /**< \brief Ebi signal: D7 */\r
+#define PIO_PA13F_D8 (1u << 13) /**< \brief Ebi signal: D8 */\r
+#define PIO_PB3B_D8 (1u << 3) /**< \brief Ebi signal: D8 */\r
+#define PIO_PA14F_D9 (1u << 14) /**< \brief Ebi signal: D9 */\r
+#define PIO_PB4B_D9 (1u << 4) /**< \brief Ebi signal: D9 */\r
+#define PIO_PA21F_NANDRDY (1u << 21) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC8B_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PD8F_NANDRDY (1u << 8) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC5B_NCS0 (1u << 5) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PD4F_NCS0 (1u << 4) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC6B_NCS1 (1u << 6) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PD5F_NCS1 (1u << 5) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PC7B_NCS2 (1u << 7) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PD6F_NCS2 (1u << 6) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PA9F_NCS3 (1u << 9) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA31B_NCS3 (1u << 31) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PA12F_NRD (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PA12F_NANDOE (1u << 12) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NRD (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PB2B_NANDOE (1u << 2) /**< \brief Ebi signal: NRD/NANDOE */\r
+#define PIO_PC3B_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PD3F_NWAIT (1u << 3) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PA8F_NWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA8F_NANDWE (1u << 8) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PA30B_NANDWE (1u << 30) /**< \brief Ebi signal: NWE/NANDWE */\r
+#define PIO_PC4B_NWR1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PC4B_NBS1 (1u << 4) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NWR1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD7F_NBS1 (1u << 7) /**< \brief Ebi signal: NWR1/NBS1 */\r
+/* ========== Pio definition for FLEXCOM0 peripheral ========== */\r
+#define PIO_PB28C_FLEXCOM0_IO0 (1u << 28) /**< \brief Flexcom0 signal: FLEXCOM0_IO0 */\r
+#define PIO_PB29C_FLEXCOM0_IO1 (1u << 29) /**< \brief Flexcom0 signal: FLEXCOM0_IO1 */\r
+#define PIO_PB30C_FLEXCOM0_IO2 (1u << 30) /**< \brief Flexcom0 signal: FLEXCOM0_IO2 */\r
+#define PIO_PB31C_FLEXCOM0_IO3 (1u << 31) /**< \brief Flexcom0 signal: FLEXCOM0_IO3 */\r
+#define PIO_PC0C_FLEXCOM0_IO4 (1u << 0) /**< \brief Flexcom0 signal: FLEXCOM0_IO4 */\r
+/* ========== Pio definition for FLEXCOM1 peripheral ========== */\r
+#define PIO_PA24A_FLEXCOM1_IO0 (1u << 24) /**< \brief Flexcom1 signal: FLEXCOM1_IO0 */\r
+#define PIO_PA23A_FLEXCOM1_IO1 (1u << 23) /**< \brief Flexcom1 signal: FLEXCOM1_IO1 */\r
+#define PIO_PA22A_FLEXCOM1_IO2 (1u << 22) /**< \brief Flexcom1 signal: FLEXCOM1_IO2 */\r
+#define PIO_PA25A_FLEXCOM1_IO3 (1u << 25) /**< \brief Flexcom1 signal: FLEXCOM1_IO3 */\r
+#define PIO_PA26A_FLEXCOM1_IO4 (1u << 26) /**< \brief Flexcom1 signal: FLEXCOM1_IO4 */\r
+/* ========== Pio definition for FLEXCOM2 peripheral ========== */\r
+#define PIO_PA6E_FLEXCOM2_IO0 (1u << 6) /**< \brief Flexcom2 signal: FLEXCOM2_IO0 */\r
+#define PIO_PD26C_FLEXCOM2_IO0 (1u << 26) /**< \brief Flexcom2 signal: FLEXCOM2_IO0 */\r
+#define PIO_PA7E_FLEXCOM2_IO1 (1u << 7) /**< \brief Flexcom2 signal: FLEXCOM2_IO1 */\r
+#define PIO_PD27C_FLEXCOM2_IO1 (1u << 27) /**< \brief Flexcom2 signal: FLEXCOM2_IO1 */\r
+#define PIO_PA8E_FLEXCOM2_IO2 (1u << 8) /**< \brief Flexcom2 signal: FLEXCOM2_IO2 */\r
+#define PIO_PD28C_FLEXCOM2_IO2 (1u << 28) /**< \brief Flexcom2 signal: FLEXCOM2_IO2 */\r
+#define PIO_PA9E_FLEXCOM2_IO3 (1u << 9) /**< \brief Flexcom2 signal: FLEXCOM2_IO3 */\r
+#define PIO_PD29C_FLEXCOM2_IO3 (1u << 29) /**< \brief Flexcom2 signal: FLEXCOM2_IO3 */\r
+#define PIO_PA10E_FLEXCOM2_IO4 (1u << 10) /**< \brief Flexcom2 signal: FLEXCOM2_IO4 */\r
+#define PIO_PD30C_FLEXCOM2_IO4 (1u << 30) /**< \brief Flexcom2 signal: FLEXCOM2_IO4 */\r
+/* ========== Pio definition for FLEXCOM3 peripheral ========== */\r
+#define PIO_PA15E_FLEXCOM3_IO0 (1u << 15) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PB23E_FLEXCOM3_IO0 (1u << 23) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PC20E_FLEXCOM3_IO0 (1u << 20) /**< \brief Flexcom3 signal: FLEXCOM3_IO0 */\r
+#define PIO_PA13E_FLEXCOM3_IO1 (1u << 13) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PB22E_FLEXCOM3_IO1 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PC19E_FLEXCOM3_IO1 (1u << 19) /**< \brief Flexcom3 signal: FLEXCOM3_IO1 */\r
+#define PIO_PA14E_FLEXCOM3_IO2 (1u << 14) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PB21E_FLEXCOM3_IO2 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PC18E_FLEXCOM3_IO2 (1u << 18) /**< \brief Flexcom3 signal: FLEXCOM3_IO2 */\r
+#define PIO_PA16E_FLEXCOM3_IO3 (1u << 16) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PB24E_FLEXCOM3_IO3 (1u << 24) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PC21E_FLEXCOM3_IO3 (1u << 21) /**< \brief Flexcom3 signal: FLEXCOM3_IO3 */\r
+#define PIO_PA17E_FLEXCOM3_IO4 (1u << 17) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PB25E_FLEXCOM3_IO4 (1u << 25) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+#define PIO_PC22E_FLEXCOM3_IO4 (1u << 22) /**< \brief Flexcom3 signal: FLEXCOM3_IO4 */\r
+/* ========== Pio definition for FLEXCOM4 peripheral ========== */\r
+#define PIO_PC28B_FLEXCOM4_IO0 (1u << 28) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD12B_FLEXCOM4_IO0 (1u << 12) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PD21C_FLEXCOM4_IO0 (1u << 21) /**< \brief Flexcom4 signal: FLEXCOM4_IO0 */\r
+#define PIO_PC29B_FLEXCOM4_IO1 (1u << 29) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD13B_FLEXCOM4_IO1 (1u << 13) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PD22C_FLEXCOM4_IO1 (1u << 22) /**< \brief Flexcom4 signal: FLEXCOM4_IO1 */\r
+#define PIO_PC30B_FLEXCOM4_IO2 (1u << 30) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD14B_FLEXCOM4_IO2 (1u << 14) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PD23C_FLEXCOM4_IO2 (1u << 23) /**< \brief Flexcom4 signal: FLEXCOM4_IO2 */\r
+#define PIO_PC31B_FLEXCOM4_IO3 (1u << 31) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD15B_FLEXCOM4_IO3 (1u << 15) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD24C_FLEXCOM4_IO3 (1u << 24) /**< \brief Flexcom4 signal: FLEXCOM4_IO3 */\r
+#define PIO_PD0B_FLEXCOM4_IO4 (1u << 0) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD16B_FLEXCOM4_IO4 (1u << 16) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+#define PIO_PD25C_FLEXCOM4_IO4 (1u << 25) /**< \brief Flexcom4 signal: FLEXCOM4_IO4 */\r
+/* ========== Pio definition for GMAC peripheral ========== */\r
+#define PIO_PB9F_GCOL (1u << 9) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PC23B_GCOL (1u << 23) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PD4D_GCOL (1u << 4) /**< \brief Gmac signal: GCOL */\r
+#define PIO_PB8F_GCRS (1u << 8) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PC22B_GCRS (1u << 22) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PD3D_GCRS (1u << 3) /**< \brief Gmac signal: GCRS */\r
+#define PIO_PB22F_GMDC (1u << 22) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PC18B_GMDC (1u << 18) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PD17D_GMDC (1u << 17) /**< \brief Gmac signal: GMDC */\r
+#define PIO_PB23F_GMDIO (1u << 23) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PC19B_GMDIO (1u << 19) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PD18D_GMDIO (1u << 18) /**< \brief Gmac signal: GMDIO */\r
+#define PIO_PB18F_GRX0 (1u << 18) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PC14B_GRX0 (1u << 14) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PD13D_GRX0 (1u << 13) /**< \brief Gmac signal: GRX0 */\r
+#define PIO_PB19F_GRX1 (1u << 19) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PC15B_GRX1 (1u << 15) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PD14D_GRX1 (1u << 14) /**< \brief Gmac signal: GRX1 */\r
+#define PIO_PB10F_GRX2 (1u << 10) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PC24B_GRX2 (1u << 24) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PD5D_GRX2 (1u << 5) /**< \brief Gmac signal: GRX2 */\r
+#define PIO_PB11F_GRX3 (1u << 11) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PC25B_GRX3 (1u << 25) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PD6D_GRX3 (1u << 6) /**< \brief Gmac signal: GRX3 */\r
+#define PIO_PB7F_GRXCK (1u << 7) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PC20B_GRXCK (1u << 20) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PD1D_GRXCK (1u << 1) /**< \brief Gmac signal: GRXCK */\r
+#define PIO_PB16F_GRXDV (1u << 16) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PC12B_GRXDV (1u << 12) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PD11D_GRXDV (1u << 11) /**< \brief Gmac signal: GRXDV */\r
+#define PIO_PB17F_GRXER (1u << 17) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PC13B_GRXER (1u << 13) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PD12D_GRXER (1u << 12) /**< \brief Gmac signal: GRXER */\r
+#define PIO_PB5F_GTSUCOMP (1u << 5) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PC9B_GTSUCOMP (1u << 9) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PD0D_GTSUCOMP (1u << 0) /**< \brief Gmac signal: GTSUCOMP */\r
+#define PIO_PB20F_GTX0 (1u << 20) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PC16B_GTX0 (1u << 16) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PD15D_GTX0 (1u << 15) /**< \brief Gmac signal: GTX0 */\r
+#define PIO_PB21F_GTX1 (1u << 21) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PC17B_GTX1 (1u << 17) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PD16D_GTX1 (1u << 16) /**< \brief Gmac signal: GTX1 */\r
+#define PIO_PB12F_GTX2 (1u << 12) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PC26B_GTX2 (1u << 26) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PD7D_GTX2 (1u << 7) /**< \brief Gmac signal: GTX2 */\r
+#define PIO_PB13F_GTX3 (1u << 13) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PC27B_GTX3 (1u << 27) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PD8D_GTX3 (1u << 8) /**< \brief Gmac signal: GTX3 */\r
+#define PIO_PB14F_GTXCK (1u << 14) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PC10B_GTXCK (1u << 10) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PD9D_GTXCK (1u << 9) /**< \brief Gmac signal: GTXCK */\r
+#define PIO_PB15F_GTXEN (1u << 15) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PC11B_GTXEN (1u << 11) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PD10D_GTXEN (1u << 10) /**< \brief Gmac signal: GTXEN */\r
+#define PIO_PB6F_GTXER (1u << 6) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PC21B_GTXER (1u << 21) /**< \brief Gmac signal: GTXER */\r
+#define PIO_PD2D_GTXER (1u << 2) /**< \brief Gmac signal: GTXER */\r
+/* ========== Pio definition for I2SC0 peripheral ========== */\r
+#define PIO_PC1E_I2SC0_CK (1u << 1) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PD19E_I2SC0_CK (1u << 19) /**< \brief I2sc0 signal: I2SC0_CK */\r
+#define PIO_PC4E_I2SC0_DI0 (1u << 4) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PD22E_I2SC0_DI0 (1u << 22) /**< \brief I2sc0 signal: I2SC0_DI0 */\r
+#define PIO_PC5E_I2SC0_DO0 (1u << 5) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PD23E_I2SC0_DO0 (1u << 23) /**< \brief I2sc0 signal: I2SC0_DO0 */\r
+#define PIO_PC2E_I2SC0_MCK (1u << 2) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PD20E_I2SC0_MCK (1u << 20) /**< \brief I2sc0 signal: I2SC0_MCK */\r
+#define PIO_PC3E_I2SC0_WS (1u << 3) /**< \brief I2sc0 signal: I2SC0_WS */\r
+#define PIO_PD21E_I2SC0_WS (1u << 21) /**< \brief I2sc0 signal: I2SC0_WS */\r
+/* ========== Pio definition for I2SC1 peripheral ========== */\r
+#define PIO_PA15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PB15D_I2SC1_CK (1u << 15) /**< \brief I2sc1 signal: I2SC1_CK */\r
+#define PIO_PA17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PB17D_I2SC1_DI0 (1u << 17) /**< \brief I2sc1 signal: I2SC1_DI0 */\r
+#define PIO_PA18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PB18D_I2SC1_DO0 (1u << 18) /**< \brief I2sc1 signal: I2SC1_DO0 */\r
+#define PIO_PA14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PB14D_I2SC1_MCK (1u << 14) /**< \brief I2sc1 signal: I2SC1_MCK */\r
+#define PIO_PA16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+#define PIO_PB16D_I2SC1_WS (1u << 16) /**< \brief I2sc1 signal: I2SC1_WS */\r
+/* ========== Pio definition for ISC peripheral ========== */\r
+#define PIO_PB26F_ISC_D0 (1u << 26) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PC9C_ISC_D0 (1u << 9) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PD7E_ISC_D0 (1u << 7) /**< \brief Isc signal: ISC_D0 */\r
+#define PIO_PB27F_ISC_D1 (1u << 27) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PC10C_ISC_D1 (1u << 10) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PD8E_ISC_D1 (1u << 8) /**< \brief Isc signal: ISC_D1 */\r
+#define PIO_PB24F_ISC_D10 (1u << 24) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PC19C_ISC_D10 (1u << 19) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD4E_ISC_D10 (1u << 4) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PD18F_ISC_D10 (1u << 18) /**< \brief Isc signal: ISC_D10 */\r
+#define PIO_PB25F_ISC_D11 (1u << 25) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PC20C_ISC_D11 (1u << 20) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD3E_ISC_D11 (1u << 3) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PD19F_ISC_D11 (1u << 19) /**< \brief Isc signal: ISC_D11 */\r
+#define PIO_PB28F_ISC_D2 (1u << 28) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PC11C_ISC_D2 (1u << 11) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PD9E_ISC_D2 (1u << 9) /**< \brief Isc signal: ISC_D2 */\r
+#define PIO_PB29F_ISC_D3 (1u << 29) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PC12C_ISC_D3 (1u << 12) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PD10E_ISC_D3 (1u << 10) /**< \brief Isc signal: ISC_D3 */\r
+#define PIO_PB30F_ISC_D4 (1u << 30) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PC13C_ISC_D4 (1u << 13) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD11E_ISC_D4 (1u << 11) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PD12F_ISC_D4 (1u << 12) /**< \brief Isc signal: ISC_D4 */\r
+#define PIO_PB31F_ISC_D5 (1u << 31) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC14C_ISC_D5 (1u << 14) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD12E_ISC_D5 (1u << 12) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PD13F_ISC_D5 (1u << 13) /**< \brief Isc signal: ISC_D5 */\r
+#define PIO_PC0F_ISC_D6 (1u << 0) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC15C_ISC_D6 (1u << 15) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD13E_ISC_D6 (1u << 13) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PD14F_ISC_D6 (1u << 14) /**< \brief Isc signal: ISC_D6 */\r
+#define PIO_PC1F_ISC_D7 (1u << 1) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC16C_ISC_D7 (1u << 16) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD14E_ISC_D7 (1u << 14) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PD15F_ISC_D7 (1u << 15) /**< \brief Isc signal: ISC_D7 */\r
+#define PIO_PC2F_ISC_D8 (1u << 2) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC17C_ISC_D8 (1u << 17) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD6E_ISC_D8 (1u << 6) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PD16F_ISC_D8 (1u << 16) /**< \brief Isc signal: ISC_D8 */\r
+#define PIO_PC3F_ISC_D9 (1u << 3) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC18C_ISC_D9 (1u << 18) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD5E_ISC_D9 (1u << 5) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PD17F_ISC_D9 (1u << 17) /**< \brief Isc signal: ISC_D9 */\r
+#define PIO_PC8F_ISC_FIELD (1u << 8) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC25C_ISC_FIELD (1u << 25) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD18E_ISC_FIELD (1u << 18) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PD23F_ISC_FIELD (1u << 23) /**< \brief Isc signal: ISC_FIELD */\r
+#define PIO_PC6F_ISC_HSYNC (1u << 6) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC23C_ISC_HSYNC (1u << 23) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD17E_ISC_HSYNC (1u << 17) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PD22F_ISC_HSYNC (1u << 22) /**< \brief Isc signal: ISC_HSYNC */\r
+#define PIO_PC7F_ISC_MCK (1u << 7) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC24C_ISC_MCK (1u << 24) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD2E_ISC_MCK (1u << 2) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PD11F_ISC_MCK (1u << 11) /**< \brief Isc signal: ISC_MCK */\r
+#define PIO_PC4F_ISC_PCK (1u << 4) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC21C_ISC_PCK (1u << 21) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD15E_ISC_PCK (1u << 15) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PD20F_ISC_PCK (1u << 20) /**< \brief Isc signal: ISC_PCK */\r
+#define PIO_PC5F_ISC_VSYNC (1u << 5) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PC22C_ISC_VSYNC (1u << 22) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD16E_ISC_VSYNC (1u << 16) /**< \brief Isc signal: ISC_VSYNC */\r
+#define PIO_PD21F_ISC_VSYNC (1u << 21) /**< \brief Isc signal: ISC_VSYNC */\r
+/* ========== Pio definition for LCDC peripheral ========== */\r
+#define PIO_PB11A_LCDDAT0 (1u << 11) /**< \brief Lcdc signal: LCDDAT0 */\r
+#define PIO_PB12A_LCDDAT1 (1u << 12) /**< \brief Lcdc signal: LCDDAT1 */\r
+#define PIO_PB21A_LCDDAT10 (1u << 21) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PC16A_LCDDAT10 (1u << 16) /**< \brief Lcdc signal: LCDDAT10 */\r
+#define PIO_PB22A_LCDDAT11 (1u << 22) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PC17A_LCDDAT11 (1u << 17) /**< \brief Lcdc signal: LCDDAT11 */\r
+#define PIO_PB23A_LCDDAT12 (1u << 23) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PC18A_LCDDAT12 (1u << 18) /**< \brief Lcdc signal: LCDDAT12 */\r
+#define PIO_PB24A_LCDDAT13 (1u << 24) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PC19A_LCDDAT13 (1u << 19) /**< \brief Lcdc signal: LCDDAT13 */\r
+#define PIO_PB25A_LCDDAT14 (1u << 25) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PC20A_LCDDAT14 (1u << 20) /**< \brief Lcdc signal: LCDDAT14 */\r
+#define PIO_PB26A_LCDDAT15 (1u << 26) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PC21A_LCDDAT15 (1u << 21) /**< \brief Lcdc signal: LCDDAT15 */\r
+#define PIO_PB27A_LCDDAT16 (1u << 27) /**< \brief Lcdc signal: LCDDAT16 */\r
+#define PIO_PB28A_LCDDAT17 (1u << 28) /**< \brief Lcdc signal: LCDDAT17 */\r
+#define PIO_PB29A_LCDDAT18 (1u << 29) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PC22A_LCDDAT18 (1u << 22) /**< \brief Lcdc signal: LCDDAT18 */\r
+#define PIO_PB30A_LCDDAT19 (1u << 30) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PC23A_LCDDAT19 (1u << 23) /**< \brief Lcdc signal: LCDDAT19 */\r
+#define PIO_PB13A_LCDDAT2 (1u << 13) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PC10A_LCDDAT2 (1u << 10) /**< \brief Lcdc signal: LCDDAT2 */\r
+#define PIO_PB31A_LCDDAT20 (1u << 31) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC24A_LCDDAT20 (1u << 24) /**< \brief Lcdc signal: LCDDAT20 */\r
+#define PIO_PC0A_LCDDAT21 (1u << 0) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC25A_LCDDAT21 (1u << 25) /**< \brief Lcdc signal: LCDDAT21 */\r
+#define PIO_PC1A_LCDDAT22 (1u << 1) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC26A_LCDDAT22 (1u << 26) /**< \brief Lcdc signal: LCDDAT22 */\r
+#define PIO_PC2A_LCDDAT23 (1u << 2) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PC27A_LCDDAT23 (1u << 27) /**< \brief Lcdc signal: LCDDAT23 */\r
+#define PIO_PB14A_LCDDAT3 (1u << 14) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PC11A_LCDDAT3 (1u << 11) /**< \brief Lcdc signal: LCDDAT3 */\r
+#define PIO_PB15A_LCDDAT4 (1u << 15) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PC12A_LCDDAT4 (1u << 12) /**< \brief Lcdc signal: LCDDAT4 */\r
+#define PIO_PB16A_LCDDAT5 (1u << 16) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PC13A_LCDDAT5 (1u << 13) /**< \brief Lcdc signal: LCDDAT5 */\r
+#define PIO_PB17A_LCDDAT6 (1u << 17) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PC14A_LCDDAT6 (1u << 14) /**< \brief Lcdc signal: LCDDAT6 */\r
+#define PIO_PB18A_LCDDAT7 (1u << 18) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PC15A_LCDDAT7 (1u << 15) /**< \brief Lcdc signal: LCDDAT7 */\r
+#define PIO_PB19A_LCDDAT8 (1u << 19) /**< \brief Lcdc signal: LCDDAT8 */\r
+#define PIO_PB20A_LCDDAT9 (1u << 20) /**< \brief Lcdc signal: LCDDAT9 */\r
+#define PIO_PC8A_LCDDEN (1u << 8) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PD1A_LCDDEN (1u << 1) /**< \brief Lcdc signal: LCDDEN */\r
+#define PIO_PC4A_LCDDISP (1u << 4) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC29A_LCDDISP (1u << 29) /**< \brief Lcdc signal: LCDDISP */\r
+#define PIO_PC6A_LCDHSYNC (1u << 6) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC31A_LCDHSYNC (1u << 31) /**< \brief Lcdc signal: LCDHSYNC */\r
+#define PIO_PC7A_LCDPCK (1u << 7) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PD0A_LCDPCK (1u << 0) /**< \brief Lcdc signal: LCDPCK */\r
+#define PIO_PC3A_LCDPWM (1u << 3) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC28A_LCDPWM (1u << 28) /**< \brief Lcdc signal: LCDPWM */\r
+#define PIO_PC5A_LCDVSYNC (1u << 5) /**< \brief Lcdc signal: LCDVSYNC */\r
+#define PIO_PC30A_LCDVSYNC (1u << 30) /**< \brief Lcdc signal: LCDVSYNC */\r
+/* ========== Pio definition for MCAN0 peripheral ========== */\r
+#define PIO_PC2C_CANRX0 (1u << 2) /**< \brief Mcan0 signal: CANRX0 */\r
+#define PIO_PC11E_CANRX0 (1u << 11) /**< \brief Mcan0 signal: CANRX0 */\r
+#define PIO_PC1C_CANTX0 (1u << 1) /**< \brief Mcan0 signal: CANTX0 */\r
+#define PIO_PC10E_CANTX0 (1u << 10) /**< \brief Mcan0 signal: CANTX0 */\r
+/* ========== Pio definition for MCAN1 peripheral ========== */\r
+#define PIO_PC27D_CANRX1 (1u << 27) /**< \brief Mcan1 signal: CANRX1 */\r
+#define PIO_PC26D_CANTX1 (1u << 26) /**< \brief Mcan1 signal: CANTX1 */\r
+/* ========== Pio definition for PDMIC peripheral ========== */\r
+#define PIO_PB12D_PDMIC_CLK (1u << 12) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB27D_PDMIC_CLK (1u << 27) /**< \brief Pdmic signal: PDMIC_CLK */\r
+#define PIO_PB11D_PDMIC_DAT (1u << 11) /**< \brief Pdmic signal: PDMIC_DAT */\r
+#define PIO_PB26D_PDMIC_DAT (1u << 26) /**< \brief Pdmic signal: PDMIC_DAT */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PC8D_PCK0 (1u << 8) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD19A_PCK0 (1u << 19) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PD31E_PCK0 (1u << 31) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13C_PCK1 (1u << 13) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PB20E_PCK1 (1u << 20) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PC27C_PCK1 (1u << 27) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PD6B_PCK1 (1u << 6) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK2 (1u << 21) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PC28C_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PD11B_PCK2 (1u << 11) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PB3D_PWMEXTRG0 (1u << 3) /**< \brief Pwm signal: PWMEXTRG0 */\r
+#define PIO_PB10C_PWMEXTRG1 (1u << 10) /**< \brief Pwm signal: PWMEXTRG1 */\r
+#define PIO_PB2D_PWMFI0 (1u << 2) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PB9C_PWMFI1 (1u << 9) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PA30D_PWMH0 (1u << 30) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0D_PWMH1 (1u << 0) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB5C_PWMH2 (1u << 5) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB7C_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA31D_PWML0 (1u << 31) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB1D_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB6C_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB8C_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for QSPI0 peripheral ========== */\r
+#define PIO_PA1B_QSPI0_CS (1u << 1) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA15C_QSPI0_CS (1u << 15) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA23F_QSPI0_CS (1u << 23) /**< \brief Qspi0 signal: QSPI0_CS */\r
+#define PIO_PA2B_QSPI0_IO0 (1u << 2) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA16C_QSPI0_IO0 (1u << 16) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA24F_QSPI0_IO0 (1u << 24) /**< \brief Qspi0 signal: QSPI0_IO0 */\r
+#define PIO_PA3B_QSPI0_IO1 (1u << 3) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA17C_QSPI0_IO1 (1u << 17) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA25F_QSPI0_IO1 (1u << 25) /**< \brief Qspi0 signal: QSPI0_IO1 */\r
+#define PIO_PA4B_QSPI0_IO2 (1u << 4) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA18C_QSPI0_IO2 (1u << 18) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA26F_QSPI0_IO2 (1u << 26) /**< \brief Qspi0 signal: QSPI0_IO2 */\r
+#define PIO_PA5B_QSPI0_IO3 (1u << 5) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA19C_QSPI0_IO3 (1u << 19) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA27F_QSPI0_IO3 (1u << 27) /**< \brief Qspi0 signal: QSPI0_IO3 */\r
+#define PIO_PA0B_QSPI0_SCK (1u << 0) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA14C_QSPI0_SCK (1u << 14) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+#define PIO_PA22F_QSPI0_SCK (1u << 22) /**< \brief Qspi0 signal: QSPI0_SCK */\r
+/* ========== Pio definition for QSPI1 peripheral ========== */\r
+#define PIO_PA11B_QSPI1_CS (1u << 11) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB6D_QSPI1_CS (1u << 6) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PB15E_QSPI1_CS (1u << 15) /**< \brief Qspi1 signal: QSPI1_CS */\r
+#define PIO_PA7B_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB7D_QSPI1_IO0 (1u << 7) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PB16E_QSPI1_IO0 (1u << 16) /**< \brief Qspi1 signal: QSPI1_IO0 */\r
+#define PIO_PA8B_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB8D_QSPI1_IO1 (1u << 8) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PB17E_QSPI1_IO1 (1u << 17) /**< \brief Qspi1 signal: QSPI1_IO1 */\r
+#define PIO_PA9B_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB9D_QSPI1_IO2 (1u << 9) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PB18E_QSPI1_IO2 (1u << 18) /**< \brief Qspi1 signal: QSPI1_IO2 */\r
+#define PIO_PA10B_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB10D_QSPI1_IO3 (1u << 10) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PB19E_QSPI1_IO3 (1u << 19) /**< \brief Qspi1 signal: QSPI1_IO3 */\r
+#define PIO_PA6B_QSPI1_SCK (1u << 6) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB5D_QSPI1_SCK (1u << 5) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+#define PIO_PB14E_QSPI1_SCK (1u << 14) /**< \brief Qspi1 signal: QSPI1_SCK */\r
+/* ========== Pio definition for SDMMC0 peripheral ========== */\r
+#define PIO_PA13A_SDMMC0_CD (1u << 13) /**< \brief Sdmmc0 signal: SDMMC0_CD */\r
+#define PIO_PA11A_SDMMC0_VDDSEL (1u << 11)/**< \brief Sdmmc0 signal: SDMMC0_VDDSEL */\r
+#define PIO_PA10A_SDMMC0_RSTN (1u << 10) /**< \brief Sdmmc0 signal: SDMMC0_RSTN */\r
+#define PIO_PA0A_SDMMC0_CK (1u << 0) /**< \brief Sdmmc0 signal: SDMMC0_CK */\r
+#define PIO_PA1A_SDMMC0_CMD (1u << 1) /**< \brief Sdmmc0 signal: SDMMC0_CMD */\r
+#define PIO_PA12A_SDMMC0_WP (1u << 12) /**< \brief Sdmmc0 signal: SDMMC0_WP */\r
+#define PIO_PA2A_SDMMC0_DAT0 (1u << 2) /**< \brief Sdmmc0 signal: SDMMC0_DAT0 */\r
+#define PIO_PA3A_SDMMC0_DAT1 (1u << 3) /**< \brief Sdmmc0 signal: SDMMC0_DAT1 */\r
+#define PIO_PA4A_SDMMC0_DAT2 (1u << 4) /**< \brief Sdmmc0 signal: SDMMC0_DAT2 */\r
+#define PIO_PA5A_SDMMC0_DAT3 (1u << 5) /**< \brief Sdmmc0 signal: SDMMC0_DAT3 */\r
+#define PIO_PA6A_SDMMC0_DAT4 (1u << 6) /**< \brief Sdmmc0 signal: SDMMC0_DAT4 */\r
+#define PIO_PA7A_SDMMC0_DAT5 (1u << 7) /**< \brief Sdmmc0 signal: SDMMC0_DAT5 */\r
+#define PIO_PA8A_SDMMC0_DAT6 (1u << 8) /**< \brief Sdmmc0 signal: SDMMC0_DAT6 */\r
+#define PIO_PA9A_SDMMC0_DAT7 (1u << 9) /**< \brief Sdmmc0 signal: SDMMC0_DAT7 */\r
+/* ========== Pio definition for SDMMC1 peripheral ========== */\r
+#define PIO_PA30E_SDMMC1_CD (1u << 30) /**< \brief Sdmmc1 signal: SDMMC1_CD */\r
+#define PIO_PA27E_SDMMC1_RSTN (1u << 27) /**< \brief Sdmmc1 signal: SDMMC1_RSTN */\r
+#define PIO_PA22E_SDMMC1_CK (1u << 22) /**< \brief Sdmmc1 signal: SDMMC1_CK */\r
+#define PIO_PA28E_SDMMC1_CMD (1u << 28) /**< \brief Sdmmc1 signal: SDMMC1_CMD */\r
+#define PIO_PA29E_SDMMC1_WP (1u << 29) /**< \brief Sdmmc1 signal: SDMMC1_WP */\r
+#define PIO_PA18E_SDMMC1_DAT0 (1u << 18) /**< \brief Sdmmc1 signal: SDMMC1_DAT0 */\r
+#define PIO_PA19E_SDMMC1_DAT1 (1u << 19) /**< \brief Sdmmc1 signal: SDMMC1_DAT1 */\r
+#define PIO_PA20E_SDMMC1_DAT2 (1u << 20) /**< \brief Sdmmc1 signal: SDMMC1_DAT2 */\r
+#define PIO_PA21E_SDMMC1_DAT3 (1u << 21) /**< \brief Sdmmc1 signal: SDMMC1_DAT3 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA16A_SPI0_MISO (1u << 16) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA31C_SPI0_MISO (1u << 31) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA15A_SPI0_MOSI (1u << 15) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PB0C_SPI0_MOSI (1u << 0) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA17A_SPI0_NPCS0 (1u << 17) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA30C_SPI0_NPCS0 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA18A_SPI0_NPCS1 (1u << 18) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA29C_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA19A_SPI0_NPCS2 (1u << 19) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA27C_SPI0_NPCS2 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA20A_SPI0_NPCS3 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA28C_SPI0_NPCS3 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA14A_SPI0_SPCK (1u << 14) /**< \brief Spi0 signal: SPI0_SPCK */\r
+#define PIO_PB1C_SPI0_SPCK (1u << 1) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PA24D_SPI1_MISO (1u << 24) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PC3D_SPI1_MISO (1u << 3) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PD27A_SPI1_MISO (1u << 27) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PA23D_SPI1_MOSI (1u << 23) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PC2D_SPI1_MOSI (1u << 2) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PD26A_SPI1_MOSI (1u << 26) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PA25D_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PC4D_SPI1_NPCS0 (1u << 4) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PD28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PA26D_SPI1_NPCS1 (1u << 26) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PC5D_SPI1_NPCS1 (1u << 5) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PD29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PA27D_SPI1_NPCS2 (1u << 27) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PC6D_SPI1_NPCS2 (1u << 6) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PD30A_SPI1_NPCS2 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PA28D_SPI1_NPCS3 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PC7D_SPI1_NPCS3 (1u << 7) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PA22D_SPI1_SPCK (1u << 22) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PC1D_SPI1_SPCK (1u << 1) /**< \brief Spi1 signal: SPI1_SPCK */\r
+#define PIO_PD25A_SPI1_SPCK (1u << 25) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC0 peripheral ========== */\r
+#define PIO_PB23C_RD0 (1u << 23) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PC15E_RD0 (1u << 15) /**< \brief Ssc0 signal: RD0 */\r
+#define PIO_PB25C_RF0 (1u << 25) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PC17E_RF0 (1u << 17) /**< \brief Ssc0 signal: RF0 */\r
+#define PIO_PB24C_RK0 (1u << 24) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PC16E_RK0 (1u << 16) /**< \brief Ssc0 signal: RK0 */\r
+#define PIO_PB22C_TD0 (1u << 22) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PC14E_TD0 (1u << 14) /**< \brief Ssc0 signal: TD0 */\r
+#define PIO_PB21C_TF0 (1u << 21) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PC13E_TF0 (1u << 13) /**< \brief Ssc0 signal: TF0 */\r
+#define PIO_PB20C_TK0 (1u << 20) /**< \brief Ssc0 signal: TK0 */\r
+#define PIO_PC12E_TK0 (1u << 12) /**< \brief Ssc0 signal: TK0 */\r
+/* ========== Pio definition for SSC1 peripheral ========== */\r
+#define PIO_PA17B_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PB17C_RD1 (1u << 17) /**< \brief Ssc1 signal: RD1 */\r
+#define PIO_PA19B_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PB19C_RF1 (1u << 19) /**< \brief Ssc1 signal: RF1 */\r
+#define PIO_PA18B_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PB18C_RK1 (1u << 18) /**< \brief Ssc1 signal: RK1 */\r
+#define PIO_PA16B_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PB16C_TD1 (1u << 16) /**< \brief Ssc1 signal: TD1 */\r
+#define PIO_PA15B_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PB15C_TF1 (1u << 15) /**< \brief Ssc1 signal: TF1 */\r
+#define PIO_PA14B_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+#define PIO_PB14C_TK1 (1u << 14) /**< \brief Ssc1 signal: TK1 */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA21D_TCLK0 (1u << 21) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA29A_TCLK1 (1u << 29) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PC5C_TCLK1 (1u << 5) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PD13A_TCLK1 (1u << 13) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PB5A_TCLK2 (1u << 5) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB24D_TCLK2 (1u << 24) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PD22A_TCLK2 (1u << 22) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA19D_TIOA0 (1u << 19) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA27A_TIOA1 (1u << 27) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PC3C_TIOA1 (1u << 3) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PD11A_TIOA1 (1u << 11) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PB6A_TIOA2 (1u << 6) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB22D_TIOA2 (1u << 22) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PD20A_TIOA2 (1u << 20) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA20D_TIOB0 (1u << 20) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA28A_TIOB1 (1u << 28) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PC4C_TIOB1 (1u << 4) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PD12A_TIOB1 (1u << 12) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PB7A_TIOB2 (1u << 7) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PB23D_TIOB2 (1u << 23) /**< \brief Tc0 signal: TIOB2 */\r
+#define PIO_PD21A_TIOB2 (1u << 21) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PB8A_TCLK3 (1u << 8) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PB21D_TCLK3 (1u << 21) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PD31D_TCLK3 (1u << 31) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC11D_TCLK4 (1u << 11) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PA8D_TCLK5 (1u << 8) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB30D_TCLK5 (1u << 30) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB19D_TIOA3 (1u << 19) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PD29D_TIOA3 (1u << 29) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PA9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC9D_TIOA4 (1u << 9) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PA6D_TIOA5 (1u << 6) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB28D_TIOA5 (1u << 28) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB20D_TIOB3 (1u << 20) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PD30D_TIOB3 (1u << 30) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PA10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC10D_TIOB4 (1u << 10) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PA7D_TIOB5 (1u << 7) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PB29D_TIOB5 (1u << 29) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWIHS0 peripheral ========== */\r
+#define PIO_PC0D_TWCK0 (1u << 0) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PC28E_TWCK0 (1u << 28) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD22B_TWCK0 (1u << 22) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PD30E_TWCK0 (1u << 30) /**< \brief Twihs0 signal: TWCK0 */\r
+#define PIO_PB31D_TWD0 (1u << 31) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PC27E_TWD0 (1u << 27) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD21B_TWD0 (1u << 21) /**< \brief Twihs0 signal: TWD0 */\r
+#define PIO_PD29E_TWD0 (1u << 29) /**< \brief Twihs0 signal: TWD0 */\r
+/* ========== Pio definition for TWIHS1 peripheral ========== */\r
+#define PIO_PC7C_TWCK1 (1u << 7) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PD20B_TWCK1 (1u << 20) /**< \brief Twihs1 signal: TWCK1 */\r
+#define PIO_PC6C_TWD1 (1u << 6) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */\r
+#define PIO_PD19B_TWD1 (1u << 19) /**< \brief Twihs1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PB26C_URXD0 (1u << 26) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PB27C_UTXD0 (1u << 27) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PC7E_URXD1 (1u << 7) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PD2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PC8E_UTXD1 (1u << 8) /**< \brief Uart1 signal: UTXD1 */\r
+#define PIO_PD3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for UART2 peripheral ========== */\r
+#define PIO_PD4B_URXD2 (1u << 4) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD19C_URXD2 (1u << 19) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD23A_URXD2 (1u << 23) /**< \brief Uart2 signal: URXD2 */\r
+#define PIO_PD5B_UTXD2 (1u << 5) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD20C_UTXD2 (1u << 20) /**< \brief Uart2 signal: UTXD2 */\r
+#define PIO_PD24A_UTXD2 (1u << 24) /**< \brief Uart2 signal: UTXD2 */\r
+/* ========== Pio definition for UART3 peripheral ========== */\r
+#define PIO_PB11C_URXD3 (1u << 11) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC12D_URXD3 (1u << 12) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PC31C_URXD3 (1u << 31) /**< \brief Uart3 signal: URXD3 */\r
+#define PIO_PB12C_UTXD3 (1u << 12) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PC13D_UTXD3 (1u << 13) /**< \brief Uart3 signal: UTXD3 */\r
+#define PIO_PD0C_UTXD3 (1u << 0) /**< \brief Uart3 signal: UTXD3 */\r
+/* ========== Pio definition for UART4 peripheral ========== */\r
+#define PIO_PB3A_URXD4 (1u << 3) /**< \brief Uart4 signal: URXD4 */\r
+#define PIO_PB4A_UTXD4 (1u << 4) /**< \brief Uart4 signal: UTXD4 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PC31_IDX 95\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+#define PIO_PD24_IDX 120\r
+#define PIO_PD25_IDX 121\r
+#define PIO_PD26_IDX 122\r
+#define PIO_PD27_IDX 123\r
+#define PIO_PD28_IDX 124\r
+#define PIO_PD29_IDX 125\r
+#define PIO_PD30_IDX 126\r
+#define PIO_PD31_IDX 127\r
+\r
+#endif /* _SAMA5D28_PIO_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D21_\r
+#define _SAMA5D21_\r
+\r
+/** \addtogroup SAMA5D21_definitions SAMA5D21 definitions\r
+ This file defines all structures and symbols for SAMA5D21:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "compiler.h"\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ *\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D21_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_aesb.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_aic.h"\r
+#include "component/component_aximx.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_classd.h"\r
+#include "component/component_flexcom.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_i2sc.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isc.h"\r
+#include "component/component_l2cc.h"\r
+#include "component/component_lcdc.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_mpddrc.h"\r
+#include "component/component_pdmic.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pit.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rxlp.h"\r
+#include "component/component_sckc.h"\r
+#include "component/component_sdmmc.h"\r
+#include "component/component_sfc.h"\r
+#include "component/component_sfr.h"\r
+#include "component/component_sfrbu.h"\r
+#include "component/component_sha.h"\r
+#include "component/component_shdwc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_tdes.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_udphs.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D21_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#define AXIMX ((Aximx *)0x00600000U) /**< \brief (AXIMX ) Base Address */\r
+#define L2CC ((L2cc *)0x00A00000U) /**< \brief (L2CC ) Base Address */\r
+#define SDMMC0 ((Sdmmc *)0xB0000000U) /**< \brief (SDMMC0 ) Base Address */\r
+#define LCDC ((Lcdc *)0xF0000000U) /**< \brief (LCDC ) Base Address */\r
+#define XDMAC1 ((Xdmac *)0xF0004000U) /**< \brief (XDMAC1 ) Base Address */\r
+#define ISC ((Isc *)0xF0008000U) /**< \brief (ISC ) Base Address */\r
+#define MPDDRC ((Mpddrc *)0xF000C000U) /**< \brief (MPDDRC ) Base Address */\r
+#define XDMAC0 ((Xdmac *)0xF0010000U) /**< \brief (XDMAC0 ) Base Address */\r
+#define PMC ((Pmc *)0xF0014000U) /**< \brief (PMC ) Base Address */\r
+#define MATRIX0 ((Matrix *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */\r
+#define AESB ((Aesb *)0xF001C000U) /**< \brief (AESB ) Base Address */\r
+#define QSPI0 ((Qspi *)0xF0020000U) /**< \brief (QSPI0 ) Base Address */\r
+#define QSPI1 ((Qspi *)0xF0024000U) /**< \brief (QSPI1 ) Base Address */\r
+#define SHA ((Sha *)0xF0028000U) /**< \brief (SHA ) Base Address */\r
+#define AES ((Aes *)0xF002C000U) /**< \brief (AES ) Base Address */\r
+#define SPI0 ((Spi *)0xF8000000U) /**< \brief (SPI0 ) Base Address */\r
+#define SSC0 ((Ssc *)0xF8004000U) /**< \brief (SSC0 ) Base Address */\r
+#define GMAC0 ((Gmac *)0xF8008000U) /**< \brief (GMAC0 ) Base Address */\r
+#define TC0 ((Tc *)0xF800C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0xF8010000U) /**< \brief (TC1 ) Base Address */\r
+#define HSMC ((Smc *)0xF8014000U) /**< \brief (HSMC ) Base Address */\r
+#define PDMIC ((Pdmic *)0xF8018000U) /**< \brief (PDMIC ) Base Address */\r
+#define UART0 ((Uart *)0xF801C000U) /**< \brief (UART0 ) Base Address */\r
+#define UART1 ((Uart *)0xF8020000U) /**< \brief (UART1 ) Base Address */\r
+#define UART2 ((Uart *)0xF8024000U) /**< \brief (UART2 ) Base Address */\r
+#define TWIHS0 ((Twihs *)0xF8028000U) /**< \brief (TWIHS0 ) Base Address */\r
+#define PWM ((Pwm *)0xF802C000U) /**< \brief (PWM ) Base Address */\r
+#define SFR ((Sfr *)0xF8030000U) /**< \brief (SFR ) Base Address */\r
+#define FLEXCOM0 ((Flexcom *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */\r
+#define USART0 ((Usart *)0xF8034200U) /**< \brief (FLEXCOM0_USART) Base Address */\r
+#define FCOMSPI0 ((Spi *)0xF8034400U) /**< \brief (FLEXCOM0_SPI) Base Address */\r
+#define TWI0 ((Twi *)0xF8034600U) /**< \brief (FLEXCOM0_TWI) Base Address */\r
+#define FLEXCOM1 ((Flexcom *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */\r
+#define USART1 ((Usart *)0xF8038200U) /**< \brief (FLEXCOM1_USART) Base Address */\r
+#define FCOMSPI1 ((Spi *)0xF8038400U) /**< \brief (FLEXCOM1_SPI) Base Address */\r
+#define TWI1 ((Twi *)0xF8038600U) /**< \brief (FLEXCOM1_TWI) Base Address */\r
+#define SAIC ((Aic *)0xF803C000U) /**< \brief (SAIC ) Base Address */\r
+#define ICM ((Icm *)0xF8040000U) /**< \brief (ICM ) Base Address */\r
+#define RSTC ((Rstc *)0xF8048000U) /**< \brief (RSTC ) Base Address */\r
+#define SHDWC ((Shdwc *)0xF8048010U) /**< \brief (SHDWC ) Base Address */\r
+#define PIT ((Pit *)0xF8048030U) /**< \brief (PIT ) Base Address */\r
+#define WDT ((Wdt *)0xF8048040U) /**< \brief (WDT ) Base Address */\r
+#define SCKC ((Sckc *)0xF8048050U) /**< \brief (SCKC ) Base Address */\r
+#define RTC ((Rtc *)0xF80480B0U) /**< \brief (RTC ) Base Address */\r
+#define RXLP ((Rxlp *)0xF8049000U) /**< \brief (RXLP ) Base Address */\r
+#define ACC ((Acc *)0xF804A000U) /**< \brief (ACC ) Base Address */\r
+#define SFC ((Sfc *)0xF804C000U) /**< \brief (SFC ) Base Address */\r
+#define I2SC0 ((I2sc *)0xF8050000U) /**< \brief (I2SC0 ) Base Address */\r
+#define SPI1 ((Spi *)0xFC000000U) /**< \brief (SPI1 ) Base Address */\r
+#define SSC1 ((Ssc *)0xFC004000U) /**< \brief (SSC1 ) Base Address */\r
+#define UART3 ((Uart *)0xFC008000U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0xFC00C000U) /**< \brief (UART4 ) Base Address */\r
+#define FLEXCOM3 ((Flexcom *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */\r
+#define USART3 ((Usart *)0xFC014200U) /**< \brief (FLEXCOM3_USART) Base Address */\r
+#define FCOMSPI3 ((Spi *)0xFC014400U) /**< \brief (FLEXCOM3_SPI) Base Address */\r
+#define TWI3 ((Twi *)0xFC014600U) /**< \brief (FLEXCOM3_TWI) Base Address */\r
+#define FLEXCOM4 ((Flexcom *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */\r
+#define USART4 ((Usart *)0xFC018200U) /**< \brief (FLEXCOM4_USART) Base Address */\r
+#define FCOMSPI4 ((Spi *)0xFC018400U) /**< \brief (FLEXCOM4_SPI) Base Address */\r
+#define TWI4 ((Twi *)0xFC018600U) /**< \brief (FLEXCOM4_TWI) Base Address */\r
+#define TRNG ((Trng *)0xFC01C000U) /**< \brief (TRNG ) Base Address */\r
+#define AIC ((Aic *)0xFC020000U) /**< \brief (AIC ) Base Address */\r
+#define TWIHS1 ((Twihs *)0xFC028000U) /**< \brief (TWIHS1 ) Base Address */\r
+#define UDPHS ((Udphs *)0xFC02C000U) /**< \brief (UDPHS ) Base Address */\r
+#define ADC ((Adc *)0xFC030000U) /**< \brief (ADC ) Base Address */\r
+#define PIOA ((Pio *)0xFC038000U) /**< \brief (PIOA ) Base Address */\r
+#define MATRIX1 ((Matrix *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */\r
+#define TDES ((Tdes *)0xFC044000U) /**< \brief (TDES ) Base Address */\r
+#define CLASSD ((Classd *)0xFC048000U) /**< \brief (CLASSD ) Base Address */\r
+#define I2SC1 ((I2sc *)0xFC04C000U) /**< \brief (I2SC1 ) Base Address */\r
+#define SFRBU ((Sfrbu *)0xFC05C000U) /**< \brief (SFRBU ) Base Address */\r
+#define CHIPID ((Chipid *)0xFC069000U) /**< \brief (CHIPID ) Base Address */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D21_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sama5d21.h"\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#define EBI_CS0_ADDR (0x10000000u) /**< EBI Chip Select 0 base address */\r
+#define DDR_CS_ADDR (0x20000000u) /**< DDR Chip Select base address */\r
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */\r
+#define EBI_CS1_ADDR (0x60000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x70000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x80000000u) /**< EBI Chip Select 3 base address */\r
+#define QSPI_AES0_ADDR (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */\r
+#define QSPI_AES1_ADDR (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */\r
+#define SDMMC0_ADDR (0xB0000000u) /**< SDMMC 0 base address */\r
+#define NFC_ADDR (0xC0000000u) /**< NAND Flash Controller Command base address */\r
+#define QSPIMEM0_ADDR (0xD0000000u) /**< QSPI Memory 0 base address */\r
+#define QSPIMEM1_ADDR (0xD8000000u) /**< QSPI Memory 1 base address */\r
+#define IROM_ADDR (0x00000000u) /**< Internal ROM base address */\r
+#define ECC_ROM_ADDR (0x00040000u) /**< ECC ROM base address */\r
+#define NFC_RAM_ADDR (0x00100000u) /**< NAND Flash Controller RAM base address */\r
+#define IRAM0_ADDR (0x00200000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x00220000u) /**< Internal RAM 1 base address */\r
+#define UDPHS_RAM_ADDR (0x00300000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */\r
+#define AXIMX_ADDR (0x00600000u) /**< AXI Bus Matrix base address */\r
+#define DAP_ADDR (0x00700000u) /**< Debug Access Port base address */\r
+#define PTCMEM_ADDR (0x00800000u) /**< PTC Memory base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3F03FUL)\r
+#define CHIP_CIDR (0x8A5C08C0UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMA5D21 */\r
+/* ************************************************************************** */\r
+\r
+/* %ATMEL_ELECTRICAL% */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D21_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D22_\r
+#define _SAMA5D22_\r
+\r
+/** \addtogroup SAMA5D22_definitions SAMA5D22 definitions\r
+ This file defines all structures and symbols for SAMA5D22:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D22 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D22_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_aesb.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_aic.h"\r
+#include "component/component_aximx.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_classd.h"\r
+#include "component/component_flexcom.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_i2sc.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isc.h"\r
+#include "component/component_l2cc.h"\r
+#include "component/component_lcdc.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_mcan.h"\r
+#include "component/component_mpddrc.h"\r
+#include "component/component_pdmic.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pit.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rxlp.h"\r
+#include "component/component_sckc.h"\r
+#include "component/component_sdmmc.h"\r
+#include "component/component_sfc.h"\r
+#include "component/component_sfr.h"\r
+#include "component/component_sfrbu.h"\r
+#include "component/component_sha.h"\r
+#include "component/component_shdwc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_tdes.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_udphs.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMA5D22 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D22_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#define AXIMX ((Aximx *)0x00600000U) /**< \brief (AXIMX ) Base Address */\r
+#define L2CC ((L2cc *)0x00A00000U) /**< \brief (L2CC ) Base Address */\r
+#define SDMMC0 ((Sdmmc *)0xB0000000U) /**< \brief (SDMMC0 ) Base Address */\r
+#define LCDC ((Lcdc *)0xF0000000U) /**< \brief (LCDC ) Base Address */\r
+#define XDMAC1 ((Xdmac *)0xF0004000U) /**< \brief (XDMAC1 ) Base Address */\r
+#define ISC ((Isc *)0xF0008000U) /**< \brief (ISC ) Base Address */\r
+#define MPDDRC ((Mpddrc *)0xF000C000U) /**< \brief (MPDDRC ) Base Address */\r
+#define XDMAC0 ((Xdmac *)0xF0010000U) /**< \brief (XDMAC0 ) Base Address */\r
+#define PMC ((Pmc *)0xF0014000U) /**< \brief (PMC ) Base Address */\r
+#define MATRIX0 ((Matrix *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */\r
+#define AESB ((Aesb *)0xF001C000U) /**< \brief (AESB ) Base Address */\r
+#define QSPI0 ((Qspi *)0xF0020000U) /**< \brief (QSPI0 ) Base Address */\r
+#define QSPI1 ((Qspi *)0xF0024000U) /**< \brief (QSPI1 ) Base Address */\r
+#define SHA ((Sha *)0xF0028000U) /**< \brief (SHA ) Base Address */\r
+#define AES ((Aes *)0xF002C000U) /**< \brief (AES ) Base Address */\r
+#define SPI0 ((Spi *)0xF8000000U) /**< \brief (SPI0 ) Base Address */\r
+#define SSC0 ((Ssc *)0xF8004000U) /**< \brief (SSC0 ) Base Address */\r
+#define GMAC0 ((Gmac *)0xF8008000U) /**< \brief (GMAC0 ) Base Address */\r
+#define TC0 ((Tc *)0xF800C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0xF8010000U) /**< \brief (TC1 ) Base Address */\r
+#define HSMC ((Smc *)0xF8014000U) /**< \brief (HSMC ) Base Address */\r
+#define PDMIC ((Pdmic *)0xF8018000U) /**< \brief (PDMIC ) Base Address */\r
+#define UART0 ((Uart *)0xF801C000U) /**< \brief (UART0 ) Base Address */\r
+#define UART1 ((Uart *)0xF8020000U) /**< \brief (UART1 ) Base Address */\r
+#define UART2 ((Uart *)0xF8024000U) /**< \brief (UART2 ) Base Address */\r
+#define TWIHS0 ((Twihs *)0xF8028000U) /**< \brief (TWIHS0 ) Base Address */\r
+#define PWM ((Pwm *)0xF802C000U) /**< \brief (PWM ) Base Address */\r
+#define SFR ((Sfr *)0xF8030000U) /**< \brief (SFR ) Base Address */\r
+#define FLEXCOM0 ((Flexcom *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */\r
+#define FLEXCOM1 ((Flexcom *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */\r
+#define SAIC ((Aic *)0xF803C000U) /**< \brief (SAIC ) Base Address */\r
+#define ICM ((Icm *)0xF8040000U) /**< \brief (ICM ) Base Address */\r
+#define RSTC ((Rstc *)0xF8048000U) /**< \brief (RSTC ) Base Address */\r
+#define SHDWC ((Shdwc *)0xF8048010U) /**< \brief (SHDWC ) Base Address */\r
+#define PIT ((Pit *)0xF8048030U) /**< \brief (PIT ) Base Address */\r
+#define WDT ((Wdt *)0xF8048040U) /**< \brief (WDT ) Base Address */\r
+#define SCKC ((Sckc *)0xF8048050U) /**< \brief (SCKC ) Base Address */\r
+#define RTC ((Rtc *)0xF80480B0U) /**< \brief (RTC ) Base Address */\r
+#define RXLP ((Rxlp *)0xF8049000U) /**< \brief (RXLP ) Base Address */\r
+#define ACC ((Acc *)0xF804A000U) /**< \brief (ACC ) Base Address */\r
+#define SFC ((Sfc *)0xF804C000U) /**< \brief (SFC ) Base Address */\r
+#define I2SC0 ((I2sc *)0xF8050000U) /**< \brief (I2SC0 ) Base Address */\r
+#define MCAN0 ((Mcan *)0xF8054000U) /**< \brief (MCAN0 ) Base Address */\r
+#define SPI1 ((Spi *)0xFC000000U) /**< \brief (SPI1 ) Base Address */\r
+#define SSC1 ((Ssc *)0xFC004000U) /**< \brief (SSC1 ) Base Address */\r
+#define UART3 ((Uart *)0xFC008000U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0xFC00C000U) /**< \brief (UART4 ) Base Address */\r
+#define FLEXCOM3 ((Flexcom *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */\r
+#define FLEXCOM4 ((Flexcom *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */\r
+#define TRNG ((Trng *)0xFC01C000U) /**< \brief (TRNG ) Base Address */\r
+#define AIC ((Aic *)0xFC020000U) /**< \brief (AIC ) Base Address */\r
+#define TWIHS1 ((Twihs *)0xFC028000U) /**< \brief (TWIHS1 ) Base Address */\r
+#define UDPHS ((Udphs *)0xFC02C000U) /**< \brief (UDPHS ) Base Address */\r
+#define ADC ((Adc *)0xFC030000U) /**< \brief (ADC ) Base Address */\r
+#define PIOA ((Pio *)0xFC038000U) /**< \brief (PIOA ) Base Address */\r
+#define MATRIX1 ((Matrix *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */\r
+#define TDES ((Tdes *)0xFC044000U) /**< \brief (TDES ) Base Address */\r
+#define CLASSD ((Classd *)0xFC048000U) /**< \brief (CLASSD ) Base Address */\r
+#define I2SC1 ((I2sc *)0xFC04C000U) /**< \brief (I2SC1 ) Base Address */\r
+#define SFRBU ((Sfrbu *)0xFC05C000U) /**< \brief (SFRBU ) Base Address */\r
+#define CHIPID ((Chipid *)0xFC069000U) /**< \brief (CHIPID ) Base Address */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMA5D22 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D22_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sama5d22.h"\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMA5D22 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#define EBI_CS0_ADDR (0x10000000u) /**< EBI Chip Select 0 base address */\r
+#define DDR_CS_ADDR (0x20000000u) /**< DDR Chip Select base address */\r
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */\r
+#define EBI_CS1_ADDR (0x60000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x70000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x80000000u) /**< EBI Chip Select 3 base address */\r
+#define QSPI_AES0_ADDR (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */\r
+#define QSPI_AES1_ADDR (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */\r
+#define SDMMC0_ADDR (0xB0000000u) /**< SDMMC 0 base address */\r
+#define NFC_ADDR (0xC0000000u) /**< NAND Flash Controller Command base address */\r
+#define QSPIMEM0_ADDR (0xD0000000u) /**< QSPI Memory 0 base address */\r
+#define QSPIMEM1_ADDR (0xD8000000u) /**< QSPI Memory 1 base address */\r
+#define IROM_ADDR (0x00000000u) /**< Internal ROM base address */\r
+#define ECC_ROM_ADDR (0x00040000u) /**< ECC ROM base address */\r
+#define NFC_RAM_ADDR (0x00100000u) /**< NAND Flash Controller RAM base address */\r
+#define IRAM0_ADDR (0x00200000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x00220000u) /**< Internal RAM 1 base address */\r
+#define UDPHS_RAM_ADDR (0x00300000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */\r
+#define AXIMX_ADDR (0x00600000u) /**< AXI Bus Matrix base address */\r
+#define DAP_ADDR (0x00700000u) /**< Debug Access Port base address */\r
+#define PTCMEM_ADDR (0x00800000u) /**< PTC Memory base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMA5D22 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3F03FUL)\r
+#define CHIP_CIDR (0x8A5C08C0UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMA5D22 */\r
+/* ************************************************************************** */\r
+\r
+/* %ATMEL_ELECTRICAL% */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D22_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D23_\r
+#define _SAMA5D23_\r
+\r
+/** \addtogroup SAMA5D23_definitions SAMA5D23 definitions\r
+ This file defines all structures and symbols for SAMA5D23:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D23 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D23_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_aesb.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_aic.h"\r
+#include "component/component_aximx.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_classd.h"\r
+#include "component/component_flexcom.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_i2sc.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isc.h"\r
+#include "component/component_l2cc.h"\r
+#include "component/component_lcdc.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_mcan.h"\r
+#include "component/component_mpddrc.h"\r
+#include "component/component_pdmic.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pit.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rxlp.h"\r
+#include "component/component_sckc.h"\r
+#include "component/component_sdmmc.h"\r
+#include "component/component_sfc.h"\r
+#include "component/component_sfr.h"\r
+#include "component/component_sfrbu.h"\r
+#include "component/component_sha.h"\r
+#include "component/component_shdwc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_tdes.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_udphs.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMA5D23 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D23_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#define AXIMX ((Aximx *)0x00600000U) /**< \brief (AXIMX ) Base Address */\r
+#define L2CC ((L2cc *)0x00A00000U) /**< \brief (L2CC ) Base Address */\r
+#define SDMMC0 ((Sdmmc *)0xB0000000U) /**< \brief (SDMMC0 ) Base Address */\r
+#define LCDC ((Lcdc *)0xF0000000U) /**< \brief (LCDC ) Base Address */\r
+#define XDMAC1 ((Xdmac *)0xF0004000U) /**< \brief (XDMAC1 ) Base Address */\r
+#define ISC ((Isc *)0xF0008000U) /**< \brief (ISC ) Base Address */\r
+#define MPDDRC ((Mpddrc *)0xF000C000U) /**< \brief (MPDDRC ) Base Address */\r
+#define XDMAC0 ((Xdmac *)0xF0010000U) /**< \brief (XDMAC0 ) Base Address */\r
+#define PMC ((Pmc *)0xF0014000U) /**< \brief (PMC ) Base Address */\r
+#define MATRIX0 ((Matrix *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */\r
+#define AESB ((Aesb *)0xF001C000U) /**< \brief (AESB ) Base Address */\r
+#define QSPI0 ((Qspi *)0xF0020000U) /**< \brief (QSPI0 ) Base Address */\r
+#define QSPI1 ((Qspi *)0xF0024000U) /**< \brief (QSPI1 ) Base Address */\r
+#define SHA ((Sha *)0xF0028000U) /**< \brief (SHA ) Base Address */\r
+#define AES ((Aes *)0xF002C000U) /**< \brief (AES ) Base Address */\r
+#define SPI0 ((Spi *)0xF8000000U) /**< \brief (SPI0 ) Base Address */\r
+#define SSC0 ((Ssc *)0xF8004000U) /**< \brief (SSC0 ) Base Address */\r
+#define GMAC ((Gmac *)0xF8008000U) /**< \brief (GMAC ) Base Address */\r
+#define TC0 ((Tc *)0xF800C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0xF8010000U) /**< \brief (TC1 ) Base Address */\r
+#define HSMC ((Smc *)0xF8014000U) /**< \brief (HSMC ) Base Address */\r
+#define PDMIC ((Pdmic *)0xF8018000U) /**< \brief (PDMIC ) Base Address */\r
+#define UART0 ((Uart *)0xF801C000U) /**< \brief (UART0 ) Base Address */\r
+#define UART1 ((Uart *)0xF8020000U) /**< \brief (UART1 ) Base Address */\r
+#define UART2 ((Uart *)0xF8024000U) /**< \brief (UART2 ) Base Address */\r
+#define TWIHS0 ((Twihs *)0xF8028000U) /**< \brief (TWIHS0 ) Base Address */\r
+#define PWM ((Pwm *)0xF802C000U) /**< \brief (PWM ) Base Address */\r
+#define SFR ((Sfr *)0xF8030000U) /**< \brief (SFR ) Base Address */\r
+#define FLEXCOM0 ((Flexcom *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */\r
+#define FLEXCOM1 ((Flexcom *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */\r
+#define SAIC ((Aic *)0xF803C000U) /**< \brief (SAIC ) Base Address */\r
+#define ICM ((Icm *)0xF8040000U) /**< \brief (ICM ) Base Address */\r
+#define RSTC ((Rstc *)0xF8048000U) /**< \brief (RSTC ) Base Address */\r
+#define SHDWC ((Shdwc *)0xF8048010U) /**< \brief (SHDWC ) Base Address */\r
+#define PIT ((Pit *)0xF8048030U) /**< \brief (PIT ) Base Address */\r
+#define WDT ((Wdt *)0xF8048040U) /**< \brief (WDT ) Base Address */\r
+#define SCKC ((Sckc *)0xF8048050U) /**< \brief (SCKC ) Base Address */\r
+#define RTC ((Rtc *)0xF80480B0U) /**< \brief (RTC ) Base Address */\r
+#define RXLP ((Rxlp *)0xF8049000U) /**< \brief (RXLP ) Base Address */\r
+#define ACC ((Acc *)0xF804A000U) /**< \brief (ACC ) Base Address */\r
+#define SFC ((Sfc *)0xF804C000U) /**< \brief (SFC ) Base Address */\r
+#define I2SC0 ((I2sc *)0xF8050000U) /**< \brief (I2SC0 ) Base Address */\r
+#define MCAN0 ((Mcan *)0xF8054000U) /**< \brief (MCAN0 ) Base Address */\r
+#define SPI1 ((Spi *)0xFC000000U) /**< \brief (SPI1 ) Base Address */\r
+#define SSC1 ((Ssc *)0xFC004000U) /**< \brief (SSC1 ) Base Address */\r
+#define UART3 ((Uart *)0xFC008000U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0xFC00C000U) /**< \brief (UART4 ) Base Address */\r
+#define FLEXCOM3 ((Flexcom *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */\r
+#define FLEXCOM4 ((Flexcom *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */\r
+#define TRNG ((Trng *)0xFC01C000U) /**< \brief (TRNG ) Base Address */\r
+#define AIC ((Aic *)0xFC020000U) /**< \brief (AIC ) Base Address */\r
+#define TWIHS1 ((Twihs *)0xFC028000U) /**< \brief (TWIHS1 ) Base Address */\r
+#define UDPHS ((Udphs *)0xFC02C000U) /**< \brief (UDPHS ) Base Address */\r
+#define ADC ((Adc *)0xFC030000U) /**< \brief (ADC ) Base Address */\r
+#define PIOA ((Pio *)0xFC038000U) /**< \brief (PIOA ) Base Address */\r
+#define MATRIX1 ((Matrix *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */\r
+#define TDES ((Tdes *)0xFC044000U) /**< \brief (TDES ) Base Address */\r
+#define CLASSD ((Classd *)0xFC048000U) /**< \brief (CLASSD ) Base Address */\r
+#define I2SC1 ((I2sc *)0xFC04C000U) /**< \brief (I2SC1 ) Base Address */\r
+#define SFRBU ((Sfrbu *)0xFC05C000U) /**< \brief (SFRBU ) Base Address */\r
+#define CHIPID ((Chipid *)0xFC069000U) /**< \brief (CHIPID ) Base Address */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMA5D23 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D23_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sama5d23.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMA5D23 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#define EBI_CS0_ADDR (0x10000000u) /**< EBI Chip Select 0 base address */\r
+#define DDR_CS_ADDR (0x20000000u) /**< DDR Chip Select base address */\r
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */\r
+#define EBI_CS1_ADDR (0x60000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x70000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x80000000u) /**< EBI Chip Select 3 base address */\r
+#define QSPI_AES0_ADDR (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */\r
+#define QSPI_AES1_ADDR (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */\r
+#define SDMMC0_ADDR (0xB0000000u) /**< SDMMC 0 base address */\r
+#define NFC_ADDR (0xC0000000u) /**< NAND Flash Controller Command base address */\r
+#define QSPIMEM0_ADDR (0xD0000000u) /**< QSPI Memory 0 base address */\r
+#define QSPIMEM1_ADDR (0xD8000000u) /**< QSPI Memory 1 base address */\r
+#define IROM_ADDR (0x00000000u) /**< Internal ROM base address */\r
+#define ECC_ROM_ADDR (0x00040000u) /**< ECC ROM base address */\r
+#define NFC_RAM_ADDR (0x00100000u) /**< NAND Flash Controller RAM base address */\r
+#define IRAM0_ADDR (0x00200000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x00220000u) /**< Internal RAM 1 base address */\r
+#define UDPHS_RAM_ADDR (0x00300000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */\r
+#define AXIMX_ADDR (0x00600000u) /**< AXI Bus Matrix base address */\r
+#define DAP_ADDR (0x00700000u) /**< Debug Access Port base address */\r
+#define PTCMEM_ADDR (0x00800000u) /**< PTC Memory base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMA5D23 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3F03FUL)\r
+#define CHIP_CIDR (0x8A5C08C0UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMA5D23 */\r
+/* ************************************************************************** */\r
+\r
+/* %ATMEL_ELECTRICAL% */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D23_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D24_\r
+#define _SAMA5D24_\r
+\r
+/** \addtogroup SAMA5D24_definitions SAMA5D24 definitions\r
+ This file defines all structures and symbols for SAMA5D24:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D24 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D24_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_aesb.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_aic.h"\r
+#include "component/component_aximx.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_classd.h"\r
+#include "component/component_flexcom.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_i2sc.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isc.h"\r
+#include "component/component_l2cc.h"\r
+#include "component/component_lcdc.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_mpddrc.h"\r
+#include "component/component_pdmic.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pit.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rxlp.h"\r
+#include "component/component_sckc.h"\r
+#include "component/component_sdmmc.h"\r
+#include "component/component_sfc.h"\r
+#include "component/component_sfr.h"\r
+#include "component/component_sfrbu.h"\r
+#include "component/component_sha.h"\r
+#include "component/component_shdwc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_tdes.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_udphs.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMA5D24 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D24_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#define AXIMX ((Aximx *)0x00600000U) /**< \brief (AXIMX ) Base Address */\r
+#define L2CC ((L2cc *)0x00A00000U) /**< \brief (L2CC ) Base Address */\r
+#define SDMMC0 ((Sdmmc *)0xA0000000U) /**< \brief (SDMMC0 ) Base Address */\r
+#define SDMMC1 ((Sdmmc *)0xB0000000U) /**< \brief (SDMMC1 ) Base Address */\r
+#define LCDC ((Lcdc *)0xF0000000U) /**< \brief (LCDC ) Base Address */\r
+#define XDMAC1 ((Xdmac *)0xF0004000U) /**< \brief (XDMAC1 ) Base Address */\r
+#define ISC ((Isc *)0xF0008000U) /**< \brief (ISC ) Base Address */\r
+#define MPDDRC ((Mpddrc *)0xF000C000U) /**< \brief (MPDDRC ) Base Address */\r
+#define XDMAC0 ((Xdmac *)0xF0010000U) /**< \brief (XDMAC0 ) Base Address */\r
+#define PMC ((Pmc *)0xF0014000U) /**< \brief (PMC ) Base Address */\r
+#define MATRIX0 ((Matrix *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */\r
+#define AESB ((Aesb *)0xF001C000U) /**< \brief (AESB ) Base Address */\r
+#define QSPI0 ((Qspi *)0xF0020000U) /**< \brief (QSPI0 ) Base Address */\r
+#define QSPI1 ((Qspi *)0xF0024000U) /**< \brief (QSPI1 ) Base Address */\r
+#define SHA ((Sha *)0xF0028000U) /**< \brief (SHA ) Base Address */\r
+#define AES ((Aes *)0xF002C000U) /**< \brief (AES ) Base Address */\r
+#define SPI0 ((Spi *)0xF8000000U) /**< \brief (SPI0 ) Base Address */\r
+#define SSC0 ((Ssc *)0xF8004000U) /**< \brief (SSC0 ) Base Address */\r
+#define GMAC0 ((Gmac *)0xF8008000U) /**< \brief (GMAC0 ) Base Address */\r
+#define TC0 ((Tc *)0xF800C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0xF8010000U) /**< \brief (TC1 ) Base Address */\r
+#define HSMC ((Smc *)0xF8014000U) /**< \brief (HSMC ) Base Address */\r
+#define PDMIC ((Pdmic *)0xF8018000U) /**< \brief (PDMIC ) Base Address */\r
+#define UART0 ((Uart *)0xF801C000U) /**< \brief (UART0 ) Base Address */\r
+#define UART1 ((Uart *)0xF8020000U) /**< \brief (UART1 ) Base Address */\r
+#define UART2 ((Uart *)0xF8024000U) /**< \brief (UART2 ) Base Address */\r
+#define TWIHS0 ((Twihs *)0xF8028000U) /**< \brief (TWIHS0 ) Base Address */\r
+#define PWM ((Pwm *)0xF802C000U) /**< \brief (PWM ) Base Address */\r
+#define SFR ((Sfr *)0xF8030000U) /**< \brief (SFR ) Base Address */\r
+#define FLEXCOM0 ((Flexcom *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */\r
+#define FLEXCOM1 ((Flexcom *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */\r
+#define SAIC ((Aic *)0xF803C000U) /**< \brief (SAIC ) Base Address */\r
+#define ICM ((Icm *)0xF8040000U) /**< \brief (ICM ) Base Address */\r
+#define RSTC ((Rstc *)0xF8048000U) /**< \brief (RSTC ) Base Address */\r
+#define SHDWC ((Shdwc *)0xF8048010U) /**< \brief (SHDWC ) Base Address */\r
+#define PIT ((Pit *)0xF8048030U) /**< \brief (PIT ) Base Address */\r
+#define WDT ((Wdt *)0xF8048040U) /**< \brief (WDT ) Base Address */\r
+#define SCKC ((Sckc *)0xF8048050U) /**< \brief (SCKC ) Base Address */\r
+#define RTC ((Rtc *)0xF80480B0U) /**< \brief (RTC ) Base Address */\r
+#define RXLP ((Rxlp *)0xF8049000U) /**< \brief (RXLP ) Base Address */\r
+#define ACC ((Acc *)0xF804A000U) /**< \brief (ACC ) Base Address */\r
+#define SFC ((Sfc *)0xF804C000U) /**< \brief (SFC ) Base Address */\r
+#define I2SC0 ((I2sc *)0xF8050000U) /**< \brief (I2SC0 ) Base Address */\r
+#define SPI1 ((Spi *)0xFC000000U) /**< \brief (SPI1 ) Base Address */\r
+#define SSC1 ((Ssc *)0xFC004000U) /**< \brief (SSC1 ) Base Address */\r
+#define UART3 ((Uart *)0xFC008000U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0xFC00C000U) /**< \brief (UART4 ) Base Address */\r
+#define FLEXCOM2 ((Flexcom *)0xFC010000U) /**< \brief (FLEXCOM2) Base Address */\r
+#define FLEXCOM3 ((Flexcom *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */\r
+#define FLEXCOM4 ((Flexcom *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */\r
+#define TRNG ((Trng *)0xFC01C000U) /**< \brief (TRNG ) Base Address */\r
+#define AIC ((Aic *)0xFC020000U) /**< \brief (AIC ) Base Address */\r
+#define TWIHS1 ((Twihs *)0xFC028000U) /**< \brief (TWIHS1 ) Base Address */\r
+#define UDPHS ((Udphs *)0xFC02C000U) /**< \brief (UDPHS ) Base Address */\r
+#define ADC ((Adc *)0xFC030000U) /**< \brief (ADC ) Base Address */\r
+#define PIOA ((Pio *)0xFC038000U) /**< \brief (PIOA ) Base Address */\r
+#define MATRIX1 ((Matrix *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */\r
+#define TDES ((Tdes *)0xFC044000U) /**< \brief (TDES ) Base Address */\r
+#define CLASSD ((Classd *)0xFC048000U) /**< \brief (CLASSD ) Base Address */\r
+#define I2SC1 ((I2sc *)0xFC04C000U) /**< \brief (I2SC1 ) Base Address */\r
+#define SFRBU ((Sfrbu *)0xFC05C000U) /**< \brief (SFRBU ) Base Address */\r
+#define CHIPID ((Chipid *)0xFC069000U) /**< \brief (CHIPID ) Base Address */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMA5D24 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D24_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sama5d24.h"\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMA5D24 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#define EBI_CS0_ADDR (0x10000000u) /**< EBI Chip Select 0 base address */\r
+#define DDR_CS_ADDR (0x20000000u) /**< DDR Chip Select base address */\r
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */\r
+#define EBI_CS1_ADDR (0x60000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x70000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x80000000u) /**< EBI Chip Select 3 base address */\r
+#define QSPI_AES0_ADDR (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */\r
+#define QSPI_AES1_ADDR (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */\r
+#define SDMMC0_ADDR (0xA0000000u) /**< SDMMC 0 base address */\r
+#define SDMMC1_ADDR (0xB0000000u) /**< SDMMC 1 base address */\r
+#define NFC_ADDR (0xC0000000u) /**< NAND Flash Controller Command base address */\r
+#define QSPIMEM0_ADDR (0xD0000000u) /**< QSPI Memory 0 base address */\r
+#define QSPIMEM1_ADDR (0xD8000000u) /**< QSPI Memory 1 base address */\r
+#define IROM_ADDR (0x00000000u) /**< Internal ROM base address */\r
+#define ECC_ROM_ADDR (0x00040000u) /**< ECC ROM base address */\r
+#define NFC_RAM_ADDR (0x00100000u) /**< NAND Flash Controller RAM base address */\r
+#define IRAM0_ADDR (0x00200000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x00220000u) /**< Internal RAM 1 base address */\r
+#define UDPHS_RAM_ADDR (0x00300000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */\r
+#define AXIMX_ADDR (0x00600000u) /**< AXI Bus Matrix base address */\r
+#define DAP_ADDR (0x00700000u) /**< Debug Access Port base address */\r
+#define PTCMEM_ADDR (0x00800000u) /**< PTC Memory base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMA5D24 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3F03FUL)\r
+#define CHIP_CIDR (0x8A5C08C0UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMA5D24 */\r
+/* ************************************************************************** */\r
+\r
+/* %ATMEL_ELECTRICAL% */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D24_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D26_\r
+#define _SAMA5D26_\r
+\r
+/** \addtogroup SAMA5D26_definitions SAMA5D26 definitions\r
+ This file defines all structures and symbols for SAMA5D26:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D26 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D26_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_aesb.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_aic.h"\r
+#include "component/component_aximx.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_classd.h"\r
+#include "component/component_flexcom.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_i2sc.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isc.h"\r
+#include "component/component_l2cc.h"\r
+#include "component/component_lcdc.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_mpddrc.h"\r
+#include "component/component_pdmic.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pit.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rxlp.h"\r
+#include "component/component_sckc.h"\r
+#include "component/component_sdmmc.h"\r
+#include "component/component_sfc.h"\r
+#include "component/component_sfr.h"\r
+#include "component/component_sfrbu.h"\r
+#include "component/component_sha.h"\r
+#include "component/component_shdwc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_tdes.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_udphs.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMA5D26 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D26_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#define AXIMX ((Aximx *)0x00600000U) /**< \brief (AXIMX ) Base Address */\r
+#define L2CC ((L2cc *)0x00A00000U) /**< \brief (L2CC ) Base Address */\r
+#define SDMMC0 ((Sdmmc *)0xA0000000U) /**< \brief (SDMMC0 ) Base Address */\r
+#define SDMMC1 ((Sdmmc *)0xB0000000U) /**< \brief (SDMMC1 ) Base Address */\r
+#define LCDC ((Lcdc *)0xF0000000U) /**< \brief (LCDC ) Base Address */\r
+#define XDMAC1 ((Xdmac *)0xF0004000U) /**< \brief (XDMAC1 ) Base Address */\r
+#define ISC ((Isc *)0xF0008000U) /**< \brief (ISC ) Base Address */\r
+#define MPDDRC ((Mpddrc *)0xF000C000U) /**< \brief (MPDDRC ) Base Address */\r
+#define XDMAC0 ((Xdmac *)0xF0010000U) /**< \brief (XDMAC0 ) Base Address */\r
+#define PMC ((Pmc *)0xF0014000U) /**< \brief (PMC ) Base Address */\r
+#define MATRIX0 ((Matrix *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */\r
+#define AESB ((Aesb *)0xF001C000U) /**< \brief (AESB ) Base Address */\r
+#define QSPI0 ((Qspi *)0xF0020000U) /**< \brief (QSPI0 ) Base Address */\r
+#define QSPI1 ((Qspi *)0xF0024000U) /**< \brief (QSPI1 ) Base Address */\r
+#define SHA ((Sha *)0xF0028000U) /**< \brief (SHA ) Base Address */\r
+#define AES ((Aes *)0xF002C000U) /**< \brief (AES ) Base Address */\r
+#define SPI0 ((Spi *)0xF8000000U) /**< \brief (SPI0 ) Base Address */\r
+#define SSC0 ((Ssc *)0xF8004000U) /**< \brief (SSC0 ) Base Address */\r
+#define GMAC0 ((Gmac *)0xF8008000U) /**< \brief (GMAC0 ) Base Address */\r
+#define TC0 ((Tc *)0xF800C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0xF8010000U) /**< \brief (TC1 ) Base Address */\r
+#define HSMC ((Smc *)0xF8014000U) /**< \brief (HSMC ) Base Address */\r
+#define PDMIC ((Pdmic *)0xF8018000U) /**< \brief (PDMIC ) Base Address */\r
+#define UART0 ((Uart *)0xF801C000U) /**< \brief (UART0 ) Base Address */\r
+#define UART1 ((Uart *)0xF8020000U) /**< \brief (UART1 ) Base Address */\r
+#define UART2 ((Uart *)0xF8024000U) /**< \brief (UART2 ) Base Address */\r
+#define TWIHS0 ((Twihs *)0xF8028000U) /**< \brief (TWIHS0 ) Base Address */\r
+#define PWM ((Pwm *)0xF802C000U) /**< \brief (PWM ) Base Address */\r
+#define SFR ((Sfr *)0xF8030000U) /**< \brief (SFR ) Base Address */\r
+#define FLEXCOM0 ((Flexcom *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */\r
+#define FLEXCOM1 ((Flexcom *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */\r
+#define SAIC ((Aic *)0xF803C000U) /**< \brief (SAIC ) Base Address */\r
+#define ICM ((Icm *)0xF8040000U) /**< \brief (ICM ) Base Address */\r
+#define RSTC ((Rstc *)0xF8048000U) /**< \brief (RSTC ) Base Address */\r
+#define SHDWC ((Shdwc *)0xF8048010U) /**< \brief (SHDWC ) Base Address */\r
+#define PIT ((Pit *)0xF8048030U) /**< \brief (PIT ) Base Address */\r
+#define WDT ((Wdt *)0xF8048040U) /**< \brief (WDT ) Base Address */\r
+#define SCKC ((Sckc *)0xF8048050U) /**< \brief (SCKC ) Base Address */\r
+#define RTC ((Rtc *)0xF80480B0U) /**< \brief (RTC ) Base Address */\r
+#define RXLP ((Rxlp *)0xF8049000U) /**< \brief (RXLP ) Base Address */\r
+#define ACC ((Acc *)0xF804A000U) /**< \brief (ACC ) Base Address */\r
+#define SFC ((Sfc *)0xF804C000U) /**< \brief (SFC ) Base Address */\r
+#define I2SC0 ((I2sc *)0xF8050000U) /**< \brief (I2SC0 ) Base Address */\r
+#define SPI1 ((Spi *)0xFC000000U) /**< \brief (SPI1 ) Base Address */\r
+#define SSC1 ((Ssc *)0xFC004000U) /**< \brief (SSC1 ) Base Address */\r
+#define UART3 ((Uart *)0xFC008000U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0xFC00C000U) /**< \brief (UART4 ) Base Address */\r
+#define FLEXCOM2 ((Flexcom *)0xFC010000U) /**< \brief (FLEXCOM2) Base Address */\r
+#define FLEXCOM3 ((Flexcom *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */\r
+#define FLEXCOM4 ((Flexcom *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */\r
+#define TRNG ((Trng *)0xFC01C000U) /**< \brief (TRNG ) Base Address */\r
+#define AIC ((Aic *)0xFC020000U) /**< \brief (AIC ) Base Address */\r
+#define TWIHS1 ((Twihs *)0xFC028000U) /**< \brief (TWIHS1 ) Base Address */\r
+#define UDPHS ((Udphs *)0xFC02C000U) /**< \brief (UDPHS ) Base Address */\r
+#define ADC ((Adc *)0xFC030000U) /**< \brief (ADC ) Base Address */\r
+#define PIOA ((Pio *)0xFC038000U) /**< \brief (PIOA ) Base Address */\r
+#define MATRIX1 ((Matrix *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */\r
+#define TDES ((Tdes *)0xFC044000U) /**< \brief (TDES ) Base Address */\r
+#define CLASSD ((Classd *)0xFC048000U) /**< \brief (CLASSD ) Base Address */\r
+#define I2SC1 ((I2sc *)0xFC04C000U) /**< \brief (I2SC1 ) Base Address */\r
+#define SFRBU ((Sfrbu *)0xFC05C000U) /**< \brief (SFRBU ) Base Address */\r
+#define CHIPID ((Chipid *)0xFC069000U) /**< \brief (CHIPID ) Base Address */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMA5D26 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D26_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sama5d26.h"\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMA5D26 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#define EBI_CS0_ADDR (0x10000000u) /**< EBI Chip Select 0 base address */\r
+#define DDR_CS_ADDR (0x20000000u) /**< DDR Chip Select base address */\r
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */\r
+#define EBI_CS1_ADDR (0x60000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x70000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x80000000u) /**< EBI Chip Select 3 base address */\r
+#define QSPI_AES0_ADDR (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */\r
+#define QSPI_AES1_ADDR (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */\r
+#define SDMMC0_ADDR (0xA0000000u) /**< SDMMC 0 base address */\r
+#define SDMMC1_ADDR (0xB0000000u) /**< SDMMC 1 base address */\r
+#define NFC_ADDR (0xC0000000u) /**< NAND Flash Controller Command base address */\r
+#define QSPIMEM0_ADDR (0xD0000000u) /**< QSPI Memory 0 base address */\r
+#define QSPIMEM1_ADDR (0xD8000000u) /**< QSPI Memory 1 base address */\r
+#define IROM_ADDR (0x00000000u) /**< Internal ROM base address */\r
+#define ECC_ROM_ADDR (0x00040000u) /**< ECC ROM base address */\r
+#define NFC_RAM_ADDR (0x00100000u) /**< NAND Flash Controller RAM base address */\r
+#define IRAM0_ADDR (0x00200000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x00220000u) /**< Internal RAM 1 base address */\r
+#define UDPHS_RAM_ADDR (0x00300000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */\r
+#define AXIMX_ADDR (0x00600000u) /**< AXI Bus Matrix base address */\r
+#define DAP_ADDR (0x00700000u) /**< Debug Access Port base address */\r
+#define PTCMEM_ADDR (0x00800000u) /**< PTC Memory base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMA5D26 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3F03FUL)\r
+#define CHIP_CIDR (0x8A5C08C0UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMA5D26 */\r
+/* ************************************************************************** */\r
+\r
+/* %ATMEL_ELECTRICAL% */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D26_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D27_\r
+#define _SAMA5D27_\r
+\r
+#include "compiler.h"\r
+\r
+/** \addtogroup SAMA5D27_definitions SAMA5D27 definitions\r
+ This file defines all structures and symbols for SAMA5D27:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D27 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D27_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_aesb.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_aic.h"\r
+#include "component/component_aximx.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_classd.h"\r
+#include "component/component_flexcom.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_i2sc.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isc.h"\r
+#include "component/component_l2cc.h"\r
+#include "component/component_lcdc.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_mcan.h"\r
+#include "component/component_mpddrc.h"\r
+#include "component/component_pdmic.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pit.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rxlp.h"\r
+#include "component/component_sckc.h"\r
+#include "component/component_sdmmc.h"\r
+#include "component/component_sfc.h"\r
+#include "component/component_sfr.h"\r
+#include "component/component_sfrbu.h"\r
+#include "component/component_sha.h"\r
+#include "component/component_shdwc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_tdes.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_udphs.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMA5D27 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D27_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#define AXIMX ((Aximx *)0x00600000U) /**< \brief (AXIMX ) Base Address */\r
+#define L2CC ((L2cc *)0x00A00000U) /**< \brief (L2CC ) Base Address */\r
+#define SDMMC0 ((Sdmmc *)0xA0000000U) /**< \brief (SDMMC0 ) Base Address */\r
+#define SDMMC1 ((Sdmmc *)0xB0000000U) /**< \brief (SDMMC1 ) Base Address */\r
+#define LCDC ((Lcdc *)0xF0000000U) /**< \brief (LCDC ) Base Address */\r
+#define XDMAC1 ((Xdmac *)0xF0004000U) /**< \brief (XDMAC1 ) Base Address */\r
+#define ISC ((Isc *)0xF0008000U) /**< \brief (ISC ) Base Address */\r
+#define MPDDRC ((Mpddrc *)0xF000C000U) /**< \brief (MPDDRC ) Base Address */\r
+#define XDMAC0 ((Xdmac *)0xF0010000U) /**< \brief (XDMAC0 ) Base Address */\r
+#define PMC ((Pmc *)0xF0014000U) /**< \brief (PMC ) Base Address */\r
+#define MATRIX0 ((Matrix *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */\r
+#define AESB ((Aesb *)0xF001C000U) /**< \brief (AESB ) Base Address */\r
+#define QSPI0 ((Qspi *)0xF0020000U) /**< \brief (QSPI0 ) Base Address */\r
+#define QSPI1 ((Qspi *)0xF0024000U) /**< \brief (QSPI1 ) Base Address */\r
+#define SHA ((Sha *)0xF0028000U) /**< \brief (SHA ) Base Address */\r
+#define AES ((Aes *)0xF002C000U) /**< \brief (AES ) Base Address */\r
+#define SPI0 ((Spi *)0xF8000000U) /**< \brief (SPI0 ) Base Address */\r
+#define SSC0 ((Ssc *)0xF8004000U) /**< \brief (SSC0 ) Base Address */\r
+#define GMAC0 ((Gmac *)0xF8008000U) /**< \brief (GMAC0 ) Base Address */\r
+#define TC0 ((Tc *)0xF800C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0xF8010000U) /**< \brief (TC1 ) Base Address */\r
+#define HSMC ((Smc *)0xF8014000U) /**< \brief (HSMC ) Base Address */\r
+#define PDMIC ((Pdmic *)0xF8018000U) /**< \brief (PDMIC ) Base Address */\r
+#define UART0 ((Uart *)0xF801C000U) /**< \brief (UART0 ) Base Address */\r
+#define UART1 ((Uart *)0xF8020000U) /**< \brief (UART1 ) Base Address */\r
+#define UART2 ((Uart *)0xF8024000U) /**< \brief (UART2 ) Base Address */\r
+#define TWIHS0 ((Twihs *)0xF8028000U) /**< \brief (TWIHS0 ) Base Address */\r
+#define PWM ((Pwm *)0xF802C000U) /**< \brief (PWM ) Base Address */\r
+#define SFR ((Sfr *)0xF8030000U) /**< \brief (SFR ) Base Address */\r
+#define FLEXCOM0 ((Flexcom *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */\r
+#define USART0 ((Usart *)0xF8034200U) /**< \brief (FLEXCOM0_USART) Base Address */\r
+#define FCOMSPI0 ((Spi *)0xF8034400U) /**< \brief (FLEXCOM0_SPI) Base Address */\r
+#define TWI0 ((Twi *)0xF8034600U) /**< \brief (FLEXCOM0_TWI) Base Address */\r
+#define FLEXCOM1 ((Flexcom *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */\r
+#define USART1 ((Usart *)0xF8038200U) /**< \brief (FLEXCOM1_USART) Base Address */\r
+#define FCOMSPI1 ((Spi *)0xF8038400U) /**< \brief (FLEXCOM1_SPI) Base Address */\r
+#define TWI1 ((Twi *)0xF8038600U) /**< \brief (FLEXCOM1_TWI) Base Address */\r
+#define SAIC ((Aic *)0xF803C000U) /**< \brief (SAIC ) Base Address */\r
+#define ICM ((Icm *)0xF8040000U) /**< \brief (ICM ) Base Address */\r
+#define RSTC ((Rstc *)0xF8048000U) /**< \brief (RSTC ) Base Address */\r
+#define SHDWC ((Shdwc *)0xF8048010U) /**< \brief (SHDWC ) Base Address */\r
+#define PIT ((Pit *)0xF8048030U) /**< \brief (PIT ) Base Address */\r
+#define WDT ((Wdt *)0xF8048040U) /**< \brief (WDT ) Base Address */\r
+#define SCKC ((Sckc *)0xF8048050U) /**< \brief (SCKC ) Base Address */\r
+#define RTC ((Rtc *)0xF80480B0U) /**< \brief (RTC ) Base Address */\r
+#define RXLP ((Rxlp *)0xF8049000U) /**< \brief (RXLP ) Base Address */\r
+#define ACC ((Acc *)0xF804A000U) /**< \brief (ACC ) Base Address */\r
+#define SFC ((Sfc *)0xF804C000U) /**< \brief (SFC ) Base Address */\r
+#define I2SC0 ((I2sc *)0xF8050000U) /**< \brief (I2SC0 ) Base Address */\r
+#define MCAN0 ((Mcan *)0xF8054000U) /**< \brief (MCAN0 ) Base Address */\r
+#define SPI1 ((Spi *)0xFC000000U) /**< \brief (SPI1 ) Base Address */\r
+#define SSC1 ((Ssc *)0xFC004000U) /**< \brief (SSC1 ) Base Address */\r
+#define UART3 ((Uart *)0xFC008000U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0xFC00C000U) /**< \brief (UART4 ) Base Address */\r
+#define FLEXCOM2 ((Flexcom *)0xFC010000U) /**< \brief (FLEXCOM2) Base Address */\r
+#define USART2 ((Usart *)0xFC010200U) /**< \brief (FLEXCOM2_USART) Base Address */\r
+#define FCOMSPI2 ((Spi *)0xFC010400U) /**< \brief (FLEXCOM2_SPI) Base Address */\r
+#define TWI2 ((Twi *)0xFC010600U) /**< \brief (FLEXCOM2_TWI) Base Address */\r
+#define FLEXCOM3 ((Flexcom *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */\r
+#define USART3 ((Usart *)0xFC014200U) /**< \brief (FLEXCOM3_USART) Base Address */\r
+#define FCOMSPI3 ((Spi *)0xFC014400U) /**< \brief (FLEXCOM3_SPI) Base Address */\r
+#define TWI3 ((Twi *)0xFC014600U) /**< \brief (FLEXCOM3_TWI) Base Address */\r
+#define FLEXCOM4 ((Flexcom *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */\r
+#define USART4 ((Usart *)0xFC018200U) /**< \brief (FLEXCOM4_USART) Base Address */\r
+#define FCOMSPI4 ((Spi *)0xFC018400U) /**< \brief (FLEXCOM4_SPI) Base Address */\r
+#define TWI4 ((Twi *)0xFC018600U) /**< \brief (FLEXCOM4_TWI) Base Address */\r
+#define TRNG ((Trng *)0xFC01C000U) /**< \brief (TRNG ) Base Address */\r
+#define AIC ((Aic *)0xFC020000U) /**< \brief (AIC ) Base Address */\r
+#define TWIHS1 ((Twihs *)0xFC028000U) /**< \brief (TWIHS1 ) Base Address */\r
+#define UDPHS ((Udphs *)0xFC02C000U) /**< \brief (UDPHS ) Base Address */\r
+#define ADC ((Adc *)0xFC030000U) /**< \brief (ADC ) Base Address */\r
+#define PIOA ((Pio *)0xFC038000U) /**< \brief (PIOA ) Base Address */\r
+#define MATRIX1 ((Matrix *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */\r
+#define TDES ((Tdes *)0xFC044000U) /**< \brief (TDES ) Base Address */\r
+#define CLASSD ((Classd *)0xFC048000U) /**< \brief (CLASSD ) Base Address */\r
+#define I2SC1 ((I2sc *)0xFC04C000U) /**< \brief (I2SC1 ) Base Address */\r
+#define MCAN1 ((Mcan *)0xFC050000U) /**< \brief (MCAN1 ) Base Address */\r
+#define SFRBU ((Sfrbu *)0xFC05C000U) /**< \brief (SFRBU ) Base Address */\r
+#define CHIPID ((Chipid *)0xFC069000U) /**< \brief (CHIPID ) Base Address */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMA5D27 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D27_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sama5d27.h"\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMA5D27 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#define EBI_CS0_ADDR (0x10000000u) /**< EBI Chip Select 0 base address */\r
+#define DDR_CS_ADDR (0x20000000u) /**< DDR Chip Select base address */\r
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */\r
+#define EBI_CS1_ADDR (0x60000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x70000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x80000000u) /**< EBI Chip Select 3 base address */\r
+#define QSPI_AES0_ADDR (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */\r
+#define QSPI_AES1_ADDR (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */\r
+#define SDMMC0_ADDR (0xA0000000u) /**< SDMMC 0 base address */\r
+#define SDMMC1_ADDR (0xB0000000u) /**< SDMMC 1 base address */\r
+#define NFC_ADDR (0xC0000000u) /**< NAND Flash Controller Command base address */\r
+#define QSPIMEM0_ADDR (0xD0000000u) /**< QSPI Memory 0 base address */\r
+#define QSPIMEM1_ADDR (0xD8000000u) /**< QSPI Memory 1 base address */\r
+#define IROM_ADDR (0x00000000u) /**< Internal ROM base address */\r
+#define ECC_ROM_ADDR (0x00040000u) /**< ECC ROM base address */\r
+#define NFC_RAM_ADDR (0x00100000u) /**< NAND Flash Controller RAM base address */\r
+#define IRAM0_ADDR (0x00200000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x00220000u) /**< Internal RAM 1 base address */\r
+#define UDPHS_RAM_ADDR (0x00300000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */\r
+#define AXIMX_ADDR (0x00600000u) /**< AXI Bus Matrix base address */\r
+#define DAP_ADDR (0x00700000u) /**< Debug Access Port base address */\r
+#define PTCMEM_ADDR (0x00800000u) /**< PTC Memory base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMA5D27 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3F03FUL)\r
+#define CHIP_CIDR (0x8A5C08C0UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMA5D27 */\r
+/* ************************************************************************** */\r
+\r
+/* %ATMEL_ELECTRICAL% */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D27_ */\r
--- /dev/null
+/* ---------------------------------------------------------------------------- */\r
+/* Atmel Microcontroller Software Support */\r
+/* SAM Software Package License */\r
+/* ---------------------------------------------------------------------------- */\r
+/* Copyright (c) 2015, Atmel Corporation */\r
+/* */\r
+/* All rights reserved. */\r
+/* */\r
+/* Redistribution and use in source and binary forms, with or without */\r
+/* modification, are permitted provided that the following condition is met: */\r
+/* */\r
+/* - Redistributions of source code must retain the above copyright notice, */\r
+/* this list of conditions and the disclaimer below. */\r
+/* */\r
+/* Atmel's name may not be used to endorse or promote products derived from */\r
+/* this software without specific prior written permission. */\r
+/* */\r
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */\r
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */\r
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */\r
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */\r
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */\r
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */\r
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+#ifndef _SAMA5D28_\r
+#define _SAMA5D28_\r
+\r
+/** \addtogroup SAMA5D28_definitions SAMA5D28 definitions\r
+ This file defines all structures and symbols for SAMA5D28:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D28 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D28_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_aesb.h"\r
+#include "component/component_aes.h"\r
+#include "component/component_aic.h"\r
+#include "component/component_aximx.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_classd.h"\r
+#include "component/component_flexcom.h"\r
+#include "component/component_gmac.h"\r
+#include "component/component_i2sc.h"\r
+#include "component/component_icm.h"\r
+#include "component/component_isc.h"\r
+#include "component/component_l2cc.h"\r
+#include "component/component_lcdc.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_mcan.h"\r
+#include "component/component_mpddrc.h"\r
+#include "component/component_pdmic.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pit.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_qspi.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rxlp.h"\r
+#include "component/component_sckc.h"\r
+#include "component/component_sdmmc.h"\r
+#include "component/component_sfc.h"\r
+#include "component/component_sfr.h"\r
+#include "component/component_sfrbu.h"\r
+#include "component/component_sha.h"\r
+#include "component/component_shdwc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_tdes.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twihs.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_udphs.h"\r
+#include "component/component_wdt.h"\r
+#include "component/component_xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAMA5D28 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D28_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#define AXIMX ((Aximx *)0x00600000U) /**< \brief (AXIMX ) Base Address */\r
+#define L2CC ((L2cc *)0x00A00000U) /**< \brief (L2CC ) Base Address */\r
+#define SDMMC0 ((Sdmmc *)0xA0000000U) /**< \brief (SDMMC0 ) Base Address */\r
+#define SDMMC1 ((Sdmmc *)0xB0000000U) /**< \brief (SDMMC1 ) Base Address */\r
+#define LCDC ((Lcdc *)0xF0000000U) /**< \brief (LCDC ) Base Address */\r
+#define XDMAC1 ((Xdmac *)0xF0004000U) /**< \brief (XDMAC1 ) Base Address */\r
+#define ISC ((Isc *)0xF0008000U) /**< \brief (ISC ) Base Address */\r
+#define MPDDRC ((Mpddrc *)0xF000C000U) /**< \brief (MPDDRC ) Base Address */\r
+#define XDMAC0 ((Xdmac *)0xF0010000U) /**< \brief (XDMAC0 ) Base Address */\r
+#define PMC ((Pmc *)0xF0014000U) /**< \brief (PMC ) Base Address */\r
+#define MATRIX0 ((Matrix *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */\r
+#define AESB ((Aesb *)0xF001C000U) /**< \brief (AESB ) Base Address */\r
+#define QSPI0 ((Qspi *)0xF0020000U) /**< \brief (QSPI0 ) Base Address */\r
+#define QSPI1 ((Qspi *)0xF0024000U) /**< \brief (QSPI1 ) Base Address */\r
+#define SHA ((Sha *)0xF0028000U) /**< \brief (SHA ) Base Address */\r
+#define AES ((Aes *)0xF002C000U) /**< \brief (AES ) Base Address */\r
+#define SPI0 ((Spi *)0xF8000000U) /**< \brief (SPI0 ) Base Address */\r
+#define SSC0 ((Ssc *)0xF8004000U) /**< \brief (SSC0 ) Base Address */\r
+#define GMAC0 ((Gmac *)0xF8008000U) /**< \brief (GMAC0 ) Base Address */\r
+#define TC0 ((Tc *)0xF800C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0xF8010000U) /**< \brief (TC1 ) Base Address */\r
+#define HSMC ((Smc *)0xF8014000U) /**< \brief (HSMC ) Base Address */\r
+#define PDMIC ((Pdmic *)0xF8018000U) /**< \brief (PDMIC ) Base Address */\r
+#define UART0 ((Uart *)0xF801C000U) /**< \brief (UART0 ) Base Address */\r
+#define UART1 ((Uart *)0xF8020000U) /**< \brief (UART1 ) Base Address */\r
+#define UART2 ((Uart *)0xF8024000U) /**< \brief (UART2 ) Base Address */\r
+#define TWIHS0 ((Twihs *)0xF8028000U) /**< \brief (TWIHS0 ) Base Address */\r
+#define PWM ((Pwm *)0xF802C000U) /**< \brief (PWM ) Base Address */\r
+#define SFR ((Sfr *)0xF8030000U) /**< \brief (SFR ) Base Address */\r
+#define FLEXCOM0 ((Flexcom *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */\r
+#define FLEXCOM1 ((Flexcom *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */\r
+#define SAIC ((Aic *)0xF803C000U) /**< \brief (SAIC ) Base Address */\r
+#define ICM ((Icm *)0xF8040000U) /**< \brief (ICM ) Base Address */\r
+#define RSTC ((Rstc *)0xF8048000U) /**< \brief (RSTC ) Base Address */\r
+#define SHDWC ((Shdwc *)0xF8048010U) /**< \brief (SHDWC ) Base Address */\r
+#define PIT ((Pit *)0xF8048030U) /**< \brief (PIT ) Base Address */\r
+#define WDT ((Wdt *)0xF8048040U) /**< \brief (WDT ) Base Address */\r
+#define SCKC ((Sckc *)0xF8048050U) /**< \brief (SCKC ) Base Address */\r
+#define RTC ((Rtc *)0xF80480B0U) /**< \brief (RTC ) Base Address */\r
+#define RXLP ((Rxlp *)0xF8049000U) /**< \brief (RXLP ) Base Address */\r
+#define ACC ((Acc *)0xF804A000U) /**< \brief (ACC ) Base Address */\r
+#define SFC ((Sfc *)0xF804C000U) /**< \brief (SFC ) Base Address */\r
+#define I2SC0 ((I2sc *)0xF8050000U) /**< \brief (I2SC0 ) Base Address */\r
+#define MCAN0 ((Mcan *)0xF8054000U) /**< \brief (MCAN0 ) Base Address */\r
+#define SPI1 ((Spi *)0xFC000000U) /**< \brief (SPI1 ) Base Address */\r
+#define SSC1 ((Ssc *)0xFC004000U) /**< \brief (SSC1 ) Base Address */\r
+#define UART3 ((Uart *)0xFC008000U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0xFC00C000U) /**< \brief (UART4 ) Base Address */\r
+#define FLEXCOM2 ((Flexcom *)0xFC010000U) /**< \brief (FLEXCOM2) Base Address */\r
+#define FLEXCOM3 ((Flexcom *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */\r
+#define FLEXCOM4 ((Flexcom *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */\r
+#define TRNG ((Trng *)0xFC01C000U) /**< \brief (TRNG ) Base Address */\r
+#define AIC ((Aic *)0xFC020000U) /**< \brief (AIC ) Base Address */\r
+#define TWIHS1 ((Twihs *)0xFC028000U) /**< \brief (TWIHS1 ) Base Address */\r
+#define UDPHS ((Udphs *)0xFC02C000U) /**< \brief (UDPHS ) Base Address */\r
+#define ADC ((Adc *)0xFC030000U) /**< \brief (ADC ) Base Address */\r
+#define PIOA ((Pio *)0xFC038000U) /**< \brief (PIOA ) Base Address */\r
+#define MATRIX1 ((Matrix *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */\r
+#define TDES ((Tdes *)0xFC044000U) /**< \brief (TDES ) Base Address */\r
+#define CLASSD ((Classd *)0xFC048000U) /**< \brief (CLASSD ) Base Address */\r
+#define I2SC1 ((I2sc *)0xFC04C000U) /**< \brief (I2SC1 ) Base Address */\r
+#define MCAN1 ((Mcan *)0xFC050000U) /**< \brief (MCAN1 ) Base Address */\r
+#define SFRBU ((Sfrbu *)0xFC05C000U) /**< \brief (SFRBU ) Base Address */\r
+#define CHIPID ((Chipid *)0xFC069000U) /**< \brief (CHIPID ) Base Address */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAMA5D28 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAMA5D28_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sama5d28.h"\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAMA5D28 */\r
+/* ************************************************************************** */\r
+\r
+\r
+#define EBI_CS0_ADDR (0x10000000u) /**< EBI Chip Select 0 base address */\r
+#define DDR_CS_ADDR (0x20000000u) /**< DDR Chip Select base address */\r
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */\r
+#define EBI_CS1_ADDR (0x60000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x70000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x80000000u) /**< EBI Chip Select 3 base address */\r
+#define QSPI_AES0_ADDR (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */\r
+#define QSPI_AES1_ADDR (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */\r
+#define SDMMC0_ADDR (0xA0000000u) /**< SDMMC 0 base address */\r
+#define SDMMC1_ADDR (0xB0000000u) /**< SDMMC 1 base address */\r
+#define NFC_ADDR (0xC0000000u) /**< NAND Flash Controller Command base address */\r
+#define QSPIMEM0_ADDR (0xD0000000u) /**< QSPI Memory 0 base address */\r
+#define QSPIMEM1_ADDR (0xD8000000u) /**< QSPI Memory 1 base address */\r
+#define IROM_ADDR (0x00000000u) /**< Internal ROM base address */\r
+#define ECC_ROM_ADDR (0x00040000u) /**< ECC ROM base address */\r
+#define NFC_RAM_ADDR (0x00100000u) /**< NAND Flash Controller RAM base address */\r
+#define IRAM0_ADDR (0x00200000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x00220000u) /**< Internal RAM 1 base address */\r
+#define UDPHS_RAM_ADDR (0x00300000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */\r
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */\r
+#define AXIMX_ADDR (0x00600000u) /**< AXI Bus Matrix base address */\r
+#define DAP_ADDR (0x00700000u) /**< Debug Access Port base address */\r
+#define PTCMEM_ADDR (0x00800000u) /**< PTC Memory base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAMA5D28 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3F03FUL)\r
+#define CHIP_CIDR (0x8A5C08C0UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAMA5D28 */\r
+/* ************************************************************************** */\r
+\r
+/* %ATMEL_ELECTRICAL% */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAMA5D28_ */\r
--- /dev/null
+# Connect to the J-Link gdb server\r
+define jlink_connect\r
+ target remote localhost:2331\r
+end\r
+\r
+define reset_peripherals\r
+ # Disable all interrupts and go to supervisor mode\r
+ mon reg cpsr = 0xd3\r
+\r
+ # Reset the chip to get to a known state\r
+ #monitor reset\r
+\r
+ # Reset peripherals (using RSTC_CR)\r
+ set *0xF8048000 = 0xA5000004\r
+\r
+ # Reset L2 Cache controller\r
+ set *0x00A00100 = 0x0\r
+\r
+ # Disable Watchdog (using WDT_MR)\r
+ set *0xF8048044 = 0x00008000\r
+\r
+ # Disable D-Cache, I-Cache and MMU\r
+ mon cp15 1 0 0 0 = 0x00C50078\r
+end\r
+\r
+# Disable DDR clock and MPDDRC controller\r
+# to avoid corrupted RAM data on soft reset.\r
+define disable_ddr\r
+ set *0xF0014004 = 0x4\r
+ set *0xF0014014 = (1 << 13) \r
+end\r
+\r
+define reset_registers\r
+ # Zero registers (cannot reset core because it will disable JTAG)\r
+ mon reg r8_fiq = 0\r
+ mon reg r9_fiq = 0\r
+ mon reg r10_fiq = 0\r
+ mon reg r11_fiq = 0\r
+ mon reg r12_fiq = 0\r
+ mon reg sp_fiq = 0\r
+ mon reg lr_fiq = 0\r
+ mon reg spsr_fiq = 0\r
+ mon reg sp_irq = 0\r
+ mon reg lr_irq = 0\r
+ mon reg spsr_irq = 0\r
+ mon reg sp_abt = 0\r
+ mon reg lr_abt = 0\r
+ mon reg spsr_abt = 0\r
+ mon reg sp_und = 0\r
+ mon reg lr_und = 0\r
+ mon reg spsr_und = 0\r
+ mon reg sp_svc = 0\r
+ mon reg lr_svc = 0\r
+ mon reg spsr_svc = 0\r
+ mon reg r0 = 0\r
+ mon reg r1 = 0\r
+ mon reg r2 = 0\r
+ mon reg r3 = 0\r
+ mon reg r4 = 0\r
+ mon reg r5 = 0\r
+ mon reg r6 = 0\r
+ mon reg r7 = 0\r
+ mon reg r8_usr = 0\r
+ mon reg r9_usr = 0\r
+ mon reg r10_usr = 0\r
+ mon reg r11_usr = 0\r
+ mon reg r12_usr = 0\r
+ mon reg sp_usr = 0\r
+ mon reg lr_usr = 0 \r
+end\r
+\r
+define init_ddr \r
+\r
+ reset_registers\r
+ \r
+ load target/bootstrap.elf\r
+ \r
+ # Initialize PC\r
+ mon reg pc = 0x00200000\r
+ mon reg pc = 0x00200000\r
+\r
+ continue\r
+end\r
+\r
+define load_in_ddr\r
+\r
+ reset_registers\r
+\r
+ load\r
+ \r
+ # Initialize PC\r
+ mon reg pc = 0x20000000\r
+end\r
+\r
+define load_in_sram\r
+ reset_registers\r
+\r
+ load\r
+\r
+ # Initialize PC\r
+ mon reg pc = 0x00200000\r
+end\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2014, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+#define AIC 0xFC020000\r
+#define SAIC 0xF803C000\r
+#define AIC_IVR 0x10\r
+#define AIC_EOICR 0x38\r
+\r
+#define MODE_MSK 0x1F\r
+\r
+#define ARM_MODE_FIQ 0x11\r
+#define ARM_MODE_IRQ 0x12\r
+#define ARM_MODE_SVC 0x13\r
+#define ARM_MODE_ABT 0x17\r
+#define ARM_MODE_UND 0x1B\r
+#define ARM_MODE_SYS 0x1F\r
+\r
+#define I_BIT 0x80\r
+#define F_BIT 0x40\r
+\r
+#define FPU_NON_SECURE_ACCESS_OFFSET 10\r
+#define FPU_ACCESS_CONTROL_OFFSET 20\r
+#define FPU_FPEXC_EN_BIT 0x40000000\r
+\r
+//------------------------------------------------------------------------------\r
+// Startup routine\r
+//------------------------------------------------------------------------------\r
+\r
+ .align 4\r
+ .arm\r
+\r
+/* Exception vectors\r
+ *******************/\r
+ .section .vectors, "a", %progbits\r
+\r
+resetVector:\r
+/* Reset */\r
+ ldr pc, =resetHandler\r
+/* Undefined Instruction */\r
+ ldr pc, =undefined_instruction_irq_handler\r
+/* Software Interrupt */\r
+ ldr pc, =software_interrupt_irq_handler\r
+/* Prefetch Abort */\r
+ ldr pc, =prefetch_abort_irq_handler\r
+/* Data Abort */\r
+ ldr pc, =data_abort_irq_handler\r
+/* Reserved for future use */\r
+1:\r
+ b 1b\r
+/* Interrupt */\r
+ b irqHandler\r
+/* Fast interrupt */\r
+ b fiqHandler\r
+\r
+//------------------------------------------------------------------------------\r
+/// Handles a fast interrupt request by branching to the address defined in the\r
+/// AIC.\r
+//------------------------------------------------------------------------------\r
+fiqHandler:\r
+ sub lr, lr, #4\r
+ stmfd sp!, {lr}\r
+ //mrs lr, SPSR\r
+ stmfd sp!, {r0}\r
+\r
+ /* Write in the IVR to support Protect Mode */\r
+\r
+ ldr lr, =SAIC\r
+ ldr r0, [r14, #AIC_IVR]\r
+ str lr, [r14, #AIC_IVR]\r
+\r
+ /* Branch to interrupt handler in Supervisor mode */\r
+\r
+ msr CPSR_c, #ARM_MODE_SVC\r
+ stmfd sp!, {r1-r3, r4, r12, lr}\r
+\r
+ blx r0\r
+\r
+ ldmia sp!, {r1-r3, r4, r12, lr}\r
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT\r
+\r
+ /* Acknowledge interrupt */\r
+\r
+ ldr lr, =SAIC\r
+ str lr, [r14, #AIC_EOICR]\r
+\r
+ /* Restore interrupt context and branch back to calling code */\r
+\r
+ ldmia sp!, {r0}\r
+ //msr SPSR_cxsf, lr\r
+ ldmia sp!, {pc}^\r
+\r
+//------------------------------------------------------------------------------\r
+/// Handles incoming interrupt requests by branching to the corresponding\r
+/// handler, as defined in the AIC. Supports interrupt nesting.\r
+//------------------------------------------------------------------------------\r
+irqHandler:\r
+ /* Save interrupt context on the stack to allow nesting */\r
+\r
+ sub lr, lr, #4\r
+ stmfd sp!, {lr}\r
+ mrs lr, SPSR\r
+ stmfd sp!, {r0, lr}\r
+\r
+ /* Write in the IVR to support Protect Mode */\r
+\r
+ ldr lr, =AIC\r
+ ldr r0, [r14, #AIC_IVR]\r
+ str lr, [r14, #AIC_IVR]\r
+\r
+ /* Branch to interrupt handler in Supervisor mode */\r
+\r
+ msr CPSR_c, #ARM_MODE_SVC\r
+ stmfd sp!, {r1-r3, r4, r12, lr}\r
+\r
+ /* Check for 8-byte alignment and save lr plus a */\r
+ /* word to indicate the stack adjustment used (0 or 4) */\r
+\r
+ and r1, sp, #4\r
+ sub sp, sp, r1\r
+ stmfd sp!, {r1, lr}\r
+\r
+ blx r0\r
+\r
+ ldmia sp!, {r1, lr}\r
+ add sp, sp, r1\r
+\r
+ ldmia sp!, {r1-r3, r4, r12, lr}\r
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT\r
+\r
+ /* Acknowledge interrupt */\r
+\r
+ ldr lr, =AIC\r
+ str lr, [r14, #AIC_EOICR]\r
+\r
+ /* Restore interrupt context and branch back to calling code */\r
+\r
+ ldmia sp!, {r0, lr}\r
+ msr SPSR_cxsf, lr\r
+ ldmia sp!, {pc}^\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the chip and branches to the main() function.\r
+//------------------------------------------------------------------------------\r
+ .section .textEntry\r
+ .global entry\r
+\r
+entry:\r
+resetHandler:\r
+\r
+ cpsie a\r
+\r
+/* Useless instruction for referencing the .vectors section */\r
+\r
+ ldr r0, =resetVector\r
+\r
+/* Set pc to actual code location (i.e. not in remap zone) */\r
+\r
+ ldr pc, =1f\r
+1:\r
+\r
+/* Relocate */\r
+ ldr r0, =_etext\r
+ ldr r1, =_srelocate\r
+ ldr r2, =_erelocate\r
+1:\r
+ cmp r1, r2\r
+ ldrcc r3, [r0], #4\r
+ strcc r3, [r1], #4\r
+ bcc 1b\r
+\r
+/* Set up the fast interrupt stack pointer */\r
+\r
+ mrs r0, CPSR\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_FIQ\r
+ msr CPSR_c, r0\r
+ ldr sp, =_fiqstack\r
+ bic sp, sp, #0x7\r
+\r
+/* Set up the normal interrupt stack pointer */\r
+\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_IRQ\r
+ msr CPSR_c, r0\r
+ ldr sp, =_irqstack\r
+ bic sp, sp, #0x7\r
+\r
+/* Set up the abort mode stack pointer */\r
+\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_ABT\r
+ msr CPSR_c, r0\r
+ ldr sp, =_abtstack\r
+ bic sp, sp, #0x7\r
+\r
+/* Set up the undefined mode stack pointer */\r
+\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_UND\r
+ msr CPSR_c, r0\r
+ ldr sp, =_undstack\r
+ bic sp, sp, #0x7\r
+\r
+/* Set up the system mode stack pointer */\r
+\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_SYS\r
+ msr CPSR_c, r0\r
+ ldr sp, =_sysstack\r
+ bic sp, sp, #0x7\r
+\r
+/* Set up the supervisor mode stack pointer */\r
+\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_SVC\r
+ msr CPSR_c, r0\r
+ ldr sp, =_cstack\r
+ bic sp, sp, #0x7\r
+\r
+/* Perform low-level initialization of the chip using low_level_init() */\r
+\r
+ ldr r0, =low_level_init\r
+ blx r0\r
+\r
+/* Clear the zero segment */\r
+ ldr r0, =_szero\r
+ ldr r1, =_ezero\r
+ mov r2, #0\r
+1:\r
+ cmp r0, r1\r
+ strcc r2, [r0], #4\r
+ bcc 1b\r
+\r
+/* Enable fpu */\r
+ /* Grant non secure access for CP10 and CP11 */\r
+ mrc p15, 0, r0, c1, c1, 2\r
+ orr r0, r0, #3 << FPU_NON_SECURE_ACCESS_OFFSET\r
+ mcr p15, 0, r0, c1, c1, 2\r
+ /* Set CP10 and CP11 access permission (Privileged and User mode) */\r
+ ldr r0, =(0xF << FPU_ACCESS_CONTROL_OFFSET)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ /* Set the FPEXC EN bit to enable the FPU (and NEON instructions) */\r
+ mov r1, #FPU_FPEXC_EN_BIT\r
+ vmsr FPEXC, r1\r
+\r
+/* Initialize the C library */\r
+\r
+ ldr r0, =__libc_init_array\r
+ blx r0\r
+\r
+/* Branch to main() */\r
+\r
+ ldr r0, =main\r
+ blx r0\r
+\r
+/* Loop indefinitely when program is finished */\r
+\r
+1:\r
+ b 1b\r
--- /dev/null
+source target/common.gdb\r
+\r
+define reset\r
+ jlink_connect\r
+ reset_peripherals\r
+ disable_ddr\r
+\r
+ init_ddr\r
+ load_in_ddr\r
+ # Show registers state\r
+ mon regs\r
+end\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Linker script for running in internal DDRAM on the SAMA5-MIURA\r
+ *----------------------------------------------------------------------------*/\r
+\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+ENTRY(entry)\r
+SEARCH_DIR(.)\r
+\r
+/* Memory Spaces Definitions */\r
+MEMORY\r
+{\r
+ sram (W!RX) : ORIGIN = 0x200000, LENGTH = 128K /* sram */\r
+ ddr (W!RX) : ORIGIN = 0x20000000, LENGTH = 64M /* ddr */\r
+ ddr_nocache (RWX) : ORIGIN = 0x24000000, LENGTH = 16M /* ddr (non-cached) */\r
+}\r
+\r
+/* Sizes of the stacks used by the application. NOTE: you need to adjust */\r
+C_STACK_SIZE = 0x3000;\r
+IRQ_STACK_SIZE = 0x60;\r
+FIQ_STACK_SIZE = 0x60;\r
+SYS_STACK_SIZE = 0x40;\r
+ABT_STACK_SIZE = 0x40;\r
+UND_STACK_SIZE = 0x40;\r
+HEAP_SIZE = 0x200;\r
+\r
+/* Section Definitions */\r
+SECTIONS\r
+{\r
+ .fixed0 :\r
+ {\r
+ . = ALIGN(4);\r
+ _sfixed = .;\r
+ *(.textEntry)\r
+ *(.text .text.* .gnu.linkonce.t.*)\r
+ *(.glue_7t) *(.glue_7)\r
+ *(.cp15_*)\r
+ *(.rodata .rodata* .gnu.linkonce.r.*)\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+\r
+ /* Support C constructors, and C destructors in both user code\r
+ and the C library. This also provides support for C++ code. */\r
+ . = ALIGN(4);\r
+ KEEP(*(.init))\r
+ . = ALIGN(4);\r
+ __preinit_array_start = .;\r
+ KEEP (*(.preinit_array))\r
+ __preinit_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ __init_array_start = .;\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array))\r
+ __init_array_end = .;\r
+\r
+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+ __fini_array_start = .;\r
+ KEEP (*(.fini_array))\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ __fini_array_end = .;\r
+\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
+ *(.data .data.*);\r
+ . = ALIGN(4);\r
+ _efixed = .; /* End of text section */\r
+ } >ddr\r
+\r
+ /* .ARM.exidx is sorted, so has to go in its own output section. */\r
+ PROVIDE_HIDDEN (__exidx_start = .);\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } >ddr\r
+ PROVIDE_HIDDEN (__exidx_end = .);\r
+\r
+ /* _etext must be just before .relocate section */\r
+ . = ALIGN(4);\r
+ _etext = .;\r
+\r
+ .relocate :\r
+ {\r
+ . = ALIGN(4);\r
+ _srelocate = .;\r
+ *(.vectors);\r
+ *(.ramfunc)\r
+ . = ALIGN(4);\r
+ _erelocate = .;\r
+ } >sram AT>ddr\r
+\r
+ .region_sram (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ *(.region_sram)\r
+ } >sram\r
+\r
+ .region_ddr (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ *(.region_ddr)\r
+ } >ddr\r
+\r
+ .region_ddr_nocache (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ *(.region_ddr_nocache)\r
+ } >ddr_nocache\r
+\r
+ /* .bss section which is used for uninitialized data */\r
+ .bss (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ _sbss = . ;\r
+ _szero = .;\r
+ *(.bss .bss.*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ _ebss = . ;\r
+ _ezero = .;\r
+ } >ddr\r
+\r
+ .stack (NOLOAD) :\r
+ {\r
+ __stack_start__ = . ;\r
+\r
+ . += IRQ_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _irqstack = . ;\r
+\r
+ . += FIQ_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _fiqstack = . ;\r
+\r
+ . += ABT_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _abtstack = . ;\r
+\r
+ . += UND_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _undstack = . ;\r
+\r
+ . += SYS_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _sysstack = . ;\r
+\r
+ . += C_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _cstack = . ;\r
+\r
+ . += HEAP_SIZE;\r
+ . = ALIGN (4);\r
+ _heap = . ;\r
+\r
+ __stack_end__ = .;\r
+ } >ddr\r
+}\r
--- /dev/null
+source target/common.gdb\r
+\r
+# define 'reset' command\r
+define reset\r
+\r
+ # Connect to the J-Link gdb server\r
+ jlink_connect\r
+ \r
+ reset_peripherals\r
+\r
+ disable_ddr\r
+\r
+ load_in_sram\r
+\r
+end\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Linker script for running in internal SRAM on the SAMA5D2\r
+ *----------------------------------------------------------------------------*/\r
+\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+ENTRY(entry)\r
+SEARCH_DIR(.)\r
+\r
+/* Memory Spaces Definitions */\r
+MEMORY\r
+{\r
+ sram (W!RX) : ORIGIN = 0x200000, LENGTH = 128K /* sram */\r
+ ddr (W!RX) : ORIGIN = 0x20000000, LENGTH = 64M /* ddr */\r
+ ddr_nocache (RWX) : ORIGIN = 0x24000000, LENGTH = 16M /* ddr (non-cached) */\r
+}\r
+\r
+/* Sizes of the stacks used by the application. NOTE: you need to adjust */\r
+C_STACK_SIZE = 0x3000;\r
+IRQ_STACK_SIZE = 0x60;\r
+FIQ_STACK_SIZE = 0x60;\r
+SYS_STACK_SIZE = 0x40;\r
+ABT_STACK_SIZE = 0x40;\r
+UND_STACK_SIZE = 0x40;\r
+HEAP_SIZE = 0x200;\r
+\r
+/* Section Definitions */\r
+SECTIONS\r
+{\r
+ .fixed0 :\r
+ {\r
+ . = ALIGN(4);\r
+ _sfixed = .;\r
+ KEEP(*(.vectors .vectors.*))\r
+ *(.textEntry)\r
+ *(.text .text.* .gnu.linkonce.t.*)\r
+ *(.glue_7t) *(.glue_7)\r
+ *(.cp15_*)\r
+ *(.rodata .rodata* .gnu.linkonce.r.*)\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+\r
+ /* Support C constructors, and C destructors in both user code\r
+ and the C library. This also provides support for C++ code. */\r
+ . = ALIGN(4);\r
+ KEEP(*(.init))\r
+ . = ALIGN(4);\r
+ __preinit_array_start = .;\r
+ KEEP (*(.preinit_array))\r
+ __preinit_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ __init_array_start = .;\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array))\r
+ __init_array_end = .;\r
+\r
+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+ __fini_array_start = .;\r
+ KEEP (*(.fini_array))\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ __fini_array_end = .;\r
+\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
+ *(.data .data.*);\r
+ . = ALIGN(4);\r
+ _efixed = .; /* End of text section */\r
+\r
+ /* no relocation when running from sram */\r
+ _srelocate = .;\r
+ _erelocate = .;\r
+ } >sram\r
+\r
+ /* .ARM.exidx is sorted, so has to go in its own output section. */\r
+ PROVIDE_HIDDEN (__exidx_start = .);\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } >sram\r
+ PROVIDE_HIDDEN (__exidx_end = .);\r
+\r
+ . = ALIGN(4);\r
+ _etext = .;\r
+\r
+ .region_sram (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ *(.region_sram)\r
+ } >sram\r
+\r
+ .region_ddr (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ *(.region_ddr)\r
+ } >ddr\r
+\r
+ .region_ddr_nocache (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ *(.region_ddr_nocache)\r
+ } >ddr_nocache\r
+\r
+ /* .bss section which is used for uninitialized data */\r
+ .bss (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ _sbss = . ;\r
+ _szero = .;\r
+ *(.bss .bss.*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ _ebss = . ;\r
+ _ezero = .;\r
+ } >sram\r
+\r
+ .stack (NOLOAD) :\r
+ {\r
+ __stack_start__ = . ;\r
+\r
+ . += IRQ_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _irqstack = . ;\r
+\r
+ . += FIQ_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _fiqstack = . ;\r
+\r
+ . += ABT_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _abtstack = . ;\r
+\r
+ . += UND_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _undstack = . ;\r
+\r
+ . += SYS_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _sysstack = . ;\r
+\r
+ . += C_STACK_SIZE;\r
+ . = ALIGN (4);\r
+ _cstack = . ;\r
+\r
+ . += HEAP_SIZE;\r
+ . = ALIGN (4);\r
+ _heap = . ;\r
+\r
+ __stack_end__ = .;\r
+ } >sram\r
+\r
+ _end = . ;\r
+ __end = . ;\r
+ PROVIDE(end = .);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION IRQ_STACK:DATA:NOROOT(2)\r
+ SECTION FIQ_STACK:DATA:NOROOT(2)\r
+ SECTION ABT_STACK:DATA:NOROOT(2)\r
+ SECTION UND_STACK:DATA:NOROOT(2)\r
+ SECTION SYS_STACK:DATA:NOROOT(2)\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+#define __ASSEMBLY__\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+AT91C_BASE_AIC DEFINE 0xFC020000\r
+AT91C_BASE_SAIC DEFINE 0xF803C000\r
+AIC_IVR DEFINE 0x10\r
+AIC_EOICR DEFINE 0x38\r
+\r
+MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR\r
+\r
+ARM_MODE_ABT DEFINE 0x17\r
+ARM_MODE_FIQ DEFINE 0x11\r
+ARM_MODE_IRQ DEFINE 0x12\r
+ARM_MODE_SVC DEFINE 0x13\r
+ARM_MODE_SYS DEFINE 0x1F\r
+ARM_MODE_UND DEFINE 0x1B\r
+\r
+I_BIT DEFINE 0x80\r
+F_BIT DEFINE 0x40\r
+\r
+//------------------------------------------------------------------------------\r
+// Startup routine\r
+//------------------------------------------------------------------------------\r
+\r
+ SECTION .vectors:CODE:NOROOT(2)\r
+\r
+ PUBLIC _reset_vector\r
+ PUBLIC __iar_program_start\r
+ PUBLIC irqHandler\r
+ PUBLIC fiqHandler\r
+\r
+ EXTERN undefined_instruction_irq_handler\r
+ EXTERN prefetch_abort_irq_handler\r
+ EXTERN data_abort_irq_handler\r
+ EXTERN software_interrupt_irq_handler\r
+\r
+ DATA\r
+\r
+__iar_init$$done: ; The vector table is not needed\r
+ ; until after copy initialization is done\r
+\r
+_reset_vector: ; Make this a DATA label, so that stack usage\r
+ ; analysis doesn't consider it an uncalled fun\r
+\r
+ ARM\r
+\r
+ ldr pc, reset_addr ; 0x0 Reset\r
+ ldr pc, undefined_addr ; 0x4 Undefined instructions\r
+ ldr pc, soft_int_addr ; 0x8 Software interrupt (SWI/SVC)\r
+ ldr pc, prefetch_abt_addr ; 0xc Prefetch abort\r
+ ldr pc, data_abt_addr ; 0x10 Data abort\r
+ DCD 0 ; 0x14 RESERVED\r
+ ldr pc, irq_addr ; 0x18 IRQ\r
+ ldr pc, fiq_addr ; 0x1c FIQ\r
+\r
+ DATA\r
+\r
+; All default handlers (except reset, irq and fiq) are\r
+; defined as weak symbol definitions.\r
+; If a handler is defined by the application it will take precedence.\r
+reset_addr: DCD __iar_program_start\r
+undefined_addr: DCD undefined_instruction_irq_handler\r
+soft_int_addr: DCD software_interrupt_irq_handler\r
+prefetch_abt_addr: DCD prefetch_abort_irq_handler\r
+data_abt_addr: DCD data_abort_irq_handler\r
+irq_addr: DCD irqHandler\r
+fiq_addr: DCD fiqHandler\r
+\r
+;------------------------------------------------------------------------------\r
+; Handles a fast interrupt request by branching to the address defined in the\r
+; AIC.\r
+;------------------------------------------------------------------------------\r
+ SECTION .text:CODE:NOROOT(2)\r
+ ARM\r
+fiqHandler:\r
+ sub lr, lr, #4\r
+ stmfd sp!, {lr}\r
+ stmfd sp!, {r0}\r
+\r
+ ; Write in the IVR to support Protect Mode\r
+\r
+ ldr lr, =AT91C_BASE_SAIC\r
+ ldr r0, [r14, #AIC_IVR]\r
+ str lr, [r14, #AIC_IVR]\r
+\r
+ ; Branch to interrupt handler in Supervisor mode\r
+\r
+ msr CPSR_c, #ARM_MODE_SVC\r
+ stmfd sp!, { r1-r3, r4, r12, lr}\r
+\r
+ blx r0\r
+\r
+ ldmia sp!, { r1-r3, r4, r12, lr}\r
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT\r
+\r
+ ; Acknowledge interrupt\r
+\r
+ ldr lr, =AT91C_BASE_SAIC\r
+ str lr, [r14, #AIC_EOICR]\r
+\r
+ ; Restore interrupt context and branch back to calling code\r
+ ldmia sp!, {r0}\r
+ ldmia sp!, {pc}^\r
+\r
+;------------------------------------------------------------------------------\r
+; Handles incoming interrupt requests by branching to the corresponding\r
+; handler, as defined in the AIC. Supports interrupt nesting.\r
+;------------------------------------------------------------------------------\r
+ SECTION .text:CODE:NOROOT(2)\r
+ ARM\r
+irqHandler:\r
+ ; Save interrupt context on the stack to allow nesting\r
+\r
+ sub lr, lr, #4\r
+ stmfd sp!, {lr}\r
+ mrs lr, SPSR\r
+ stmfd sp!, {r0, lr}\r
+\r
+ ; Write in the IVR to support Protect Mode\r
+\r
+ ldr lr, =AT91C_BASE_AIC\r
+ ldr r0, [r14, #AIC_IVR]\r
+ str lr, [r14, #AIC_IVR]\r
+\r
+ ; Branch to interrupt handler in Supervisor mode\r
+\r
+ msr CPSR_c, #ARM_MODE_SVC\r
+ stmfd sp!, { r1-r3, r4, r12, lr}\r
+\r
+ ; Check for 8-byte alignment and save lr plus a\r
+ ; word to indicate the stack adjustment used (0 or 4)\r
+\r
+ and r1, sp, #4\r
+ sub sp, sp, r1\r
+ stmfd sp!, {r1, lr}\r
+\r
+ blx r0\r
+\r
+ ldmia sp!, {r1, lr}\r
+ add sp, sp, r1\r
+\r
+ ldmia sp!, { r1-r3, r4, r12, lr}\r
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT\r
+\r
+ ; Acknowledge interrupt\r
+\r
+ ldr lr, =AT91C_BASE_AIC\r
+ str lr, [r14, #AIC_EOICR]\r
+\r
+ ; Restore interrupt context and branch back to calling code\r
+\r
+ ldmia sp!, {r0, lr}\r
+ msr SPSR_cxsf, lr\r
+ ldmia sp!, {pc}^\r
+\r
+//------------------------------------------------------------------------------\r
+/// Initializes the chip and branches to the main() function.\r
+//------------------------------------------------------------------------------\r
+\r
+ SECTION .text:CODE:NOROOT(2)\r
+ PUBLIC __iar_program_start\r
+ EXTERN __cmain\r
+ EXTERN low_level_init\r
+ REQUIRE _reset_vector\r
+\r
+ EXTWEAK __iar_init_core\r
+ EXTWEAK __iar_init_vfp\r
+\r
+ ARM\r
+\r
+__iar_program_start:\r
+?cstartup:\r
+\r
+ cpsie a\r
+\r
+ ; Set up the fast interrupt stack pointer\r
+\r
+ mrs r0, CPSR\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_FIQ\r
+ msr cpsr_c, r0\r
+ ldr sp, =SFE(FIQ_STACK)\r
+ bic sp, sp, #0x7\r
+\r
+ ; Set up the normal interrupt stack pointer\r
+\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_IRQ\r
+ msr CPSR_c, r0\r
+ ldr sp, =SFE(IRQ_STACK)\r
+ bic sp, sp, #0x7\r
+\r
+ ; Set up the abort mode stack pointer\r
+\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_ABT\r
+ msr CPSR_c, r0\r
+ ldr sp, =SFE(ABT_STACK)\r
+ bic sp, sp, #0x7\r
+\r
+ ; Set up the undefined mode stack pointer\r
+\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_UND\r
+ msr CPSR_c, r0\r
+ ldr sp, =SFE(UND_STACK)\r
+ bic sp, sp, #0x7\r
+\r
+ ; Set up the system mode stack pointer\r
+\r
+ bic r0, r0, #MODE_MSK\r
+ orr r0, r0, #ARM_MODE_SYS\r
+ msr CPSR_c, r0\r
+ ldr sp, =SFE(SYS_STACK)\r
+ bic sp, sp, #0x7\r
+\r
+ ; Set up the supervisor mode stack pointer\r
+\r
+ bic r0 ,r0, #MODE_MSK\r
+ orr r0 ,r0, #ARM_MODE_SVC\r
+ msr cpsr_c, r0\r
+ ldr sp, =SFE(CSTACK)\r
+ bic sp, sp, #0x7\r
+\r
+ ; Perform low-level initialization of the chip using low_level_init()\r
+\r
+ ldr r0, =low_level_init\r
+ blx r0\r
+\r
+ ; Turn on core features assumed to be enabled\r
+ FUNCALL __iar_program_start, __iar_init_core\r
+ bl __iar_init_core\r
+\r
+ ;; Initialize VFP (if needed)\r
+ FUNCALL __iar_program_start, __iar_init_vfp\r
+ bl __iar_init_vfp\r
+\r
+ FUNCALL __iar_program_start, __cmain\r
+ bl __cmain\r
+\r
+ ;; Loop indefinitely when program is finished\r
+loop4: b loop4\r
+\r
+ END\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_1.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_IROM1_start__ = 0x0;\r
+define symbol __ICFEDIT_region_IROM1_end__ = 0x0;\r
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;\r
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;\r
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x200000;\r
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x21FFFF;\r
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\r
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;\r
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x23FFFFFF;\r
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x24000000;\r
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x24FFFFFF;\r
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\r
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_intvec__ = 0x100;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_fiqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_abtstack__ = 0x40;\r
+define symbol __ICFEDIT_size_undstack__ = 0x40;\r
+define symbol __ICFEDIT_size_sysstack__ = 0x40;\r
+define symbol __ICFEDIT_size_cstack__ = 0x3000;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region VEC_region = mem:[from __ICFEDIT_region_IRAM1_start__ size __ICFEDIT_size_intvec__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__+__ICFEDIT_size_intvec__ to __ICFEDIT_region_IRAM1_end__];\r
+define region DDRAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];\r
+define region DDRAM_NOCACHE_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };\r
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };\r
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };\r
+define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { readonly section .noinit };\r
+/* Warning: ICC still considers the sections below as zero-initialized, by default. */\r
+do not initialize { section .region_sram };\r
+do not initialize { section .region_ddr };\r
+do not initialize { section .region_ddr_nocache };\r
+\r
+place in VEC_region { section .vectors };\r
+place in RAM_region { section .region_sram };\r
+place in DDRAM_region { readonly };\r
+place in DDRAM_region { section .cstartup };\r
+place in DDRAM_region { readwrite, block IRQ_STACK, block FIQ_STACK, block ABT_STACK, block UND_STACK, block SYS_STACK, block CSTACK, block HEAP };\r
+place in DDRAM_region { section .region_ddr };\r
+place in DDRAM_NOCACHE_region { section .region_ddr_nocache };\r
--- /dev/null
+// ---------------------------------------------------------\r
+// ATMEL Microcontroller Software Support\r
+// ---------------------------------------------------------\r
+// The software is delivered "AS IS" without warranty or\r
+// condition of any kind, either express, implied or\r
+// statutory. This includes without limitation any warranty\r
+// or condition with respect to merchantability or fitness\r
+// for any particular purpose, or against the infringements of\r
+// intellectual property rights of others.\r
+// ---------------------------------------------------------\r
+// File: sama5d2-xplained_ddram.mac\r
+// User setup file for CSPY debugger.\r
+//\r
+// ---------------------------------------------------------\r
+\r
+__var __tempo_var;\r
+__var __tempo_reg;\r
+__var __dummy_read;\r
+__var __ba_offset;\r
+__var __data_test;\r
+__var __mac_i;\r
+\r
+__var REG_CKGR_MOR;\r
+__var CKGR_MOR_MOSCXTEN;\r
+__var CKGR_MOR_MOSCXTBY;\r
+__var CKGR_MOR_MOSCRCEN;\r
+__var CKGR_MOR_MOSCSEL;\r
+__var REG_CKGR_MCFR;\r
+__var CKGR_MCFR_MAINFRDY;\r
+__var REG_PMC_SR;\r
+__var PMC_SR_MCKRDY;\r
+__var PMC_SR_LOCKA;\r
+__var PMC_PCK_CSS_MAIN_CLK;\r
+__var REG_CKGR_PLLAR;\r
+__var REG_PMC_PLLICPR;\r
+__var REG_PMC_MCKR;\r
+__var PMC_MCKR_PLLADIV2_DIV2;\r
+__var PMC_MCKR_PRES_Msk;\r
+__var PMC_MCKR_PRES_CLOCK;\r
+__var PMC_MCKR_MDIV_Msk;\r
+__var PMC_MCKR_MDIV_PCK_DIV3;\r
+__var PMC_MCKR_CSS_PLLA_CLK;\r
+__var PMC_SR_MOSCSELS;\r
+\r
+__var REG_MPDDRC_RTR;\r
+\r
+/*********************************************************************\r
+* pmc_select_external_osc()\r
+*\r
+* Function description\r
+* Select external 12MHz oscillator\r
+*********************************************************************/\r
+pmc_select_external_osc()\r
+{\r
+ REG_CKGR_MOR = 0xF0014020;\r
+ CKGR_MOR_MOSCXTEN = (0x1 << 0); /*(CKGR_MOR) Main Crystal Oscillator Enable */\r
+ CKGR_MOR_MOSCXTBY = (0x1 << 1); /*(CKGR_MOR) Main Crystal Oscillator Bypass */\r
+ CKGR_MOR_MOSCRCEN = (0x1 << 3); /*(CKGR_MOR) Main On-Chip RC Oscillator Enable */\r
+ CKGR_MOR_MOSCSEL = (0x1 << 24); /*(CKGR_MOR) Main Oscillator Selection */\r
+\r
+ REG_CKGR_MCFR = 0xF0014024; /*(PMC) Main Clock Frequency Register */\r
+ CKGR_MCFR_MAINFRDY = (0x1 << 16); /*(CKGR_MCFR) Main Clock Ready */\r
+\r
+ REG_PMC_SR = 0xF0014068; /*(PMC) Status Register */\r
+ PMC_SR_MOSCSELS = (0x1 << 16); /*(PMC_SR) Main Oscillator Selection Status */\r
+ PMC_SR_MCKRDY = (0x1 << 3); /*(PMC_SR) Master Clock Status */\r
+\r
+ /* enable external OSC 12 MHz */\r
+ __tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");\r
+ __tempo_var |= CKGR_MOR_MOSCXTEN | (0x37 << 16);\r
+ __writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");\r
+\r
+ /* wait Main CLK Ready */\r
+ while(!((__readMemory32(REG_CKGR_MCFR,"Memory")) & CKGR_MCFR_MAINFRDY));\r
+\r
+ /* disable external OSC 12 MHz bypass */\r
+ __tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");\r
+ __tempo_var = (__tempo_var & ~CKGR_MOR_MOSCXTBY) | (0x37 << 16);\r
+ __writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");\r
+\r
+ /* switch MAIN clock to external OSC 12 MHz*/\r
+ __tempo_var = __readMemory32(REG_CKGR_MOR,"Memory");\r
+ __tempo_var |= CKGR_MOR_MOSCSEL | (0x37 << 16);\r
+ __writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory");\r
+\r
+ /* wait MAIN clock status change for external OSC 12 MHz selection*/\r
+ while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MOSCSELS));\r
+\r
+ /* in case when MCK is running on MAIN CLK */\r
+ while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));\r
+\r
+}\r
+\r
+/*********************************************************************\r
+* pmc_switch_mck_to_main()\r
+*\r
+* Function description\r
+* Switch PMC from MCK to main clock.\r
+*********************************************************************/\r
+pmc_switch_mck_to_main()\r
+{\r
+ REG_PMC_MCKR = 0xF0014030; /*(PMC) Master Clock Register */\r
+ PMC_PCK_CSS_MAIN_CLK = (0x1 << 0); /*(PMC_PCK[3]) Main Clock is selected */\r
+\r
+ REG_PMC_SR = 0xF0018068; /*(PMC) Status Register */\r
+ PMC_SR_MCKRDY = (0x1 << 3); /*(PMC_SR) Master Clock Status */\r
+\r
+ /* Select Main Oscillator as input clock for PCK and MCK */\r
+ __tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");\r
+ __tempo_var = (__tempo_var & ~0x03)| PMC_PCK_CSS_MAIN_CLK ;\r
+ __writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");\r
+ while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));\r
+ __mac_i=__readMemory32(REG_PMC_MCKR,"Memory");\r
+ __message " --- Master clock switched to main --- REG_PMC_MCKR 0x",__mac_i:%X;\r
+}\r
+\r
+/*********************************************************************\r
+* pmc_set_plla()\r
+*\r
+* Function description\r
+* Configure PLLA Registe.\r
+*********************************************************************/\r
+pmc_set_plla(pllmul)\r
+{\r
+ REG_CKGR_PLLAR = 0xF0014028; /*(PMC) PLLA Register */\r
+ REG_PMC_PLLICPR = 0xF0014080; /*(PMC) PLL Charge Pump Current Register */\r
+ REG_PMC_SR = 0xF0014068; /*(PMC) Status Register */\r
+ PMC_SR_LOCKA = (0x1 << 1); /*(PMC_SR) PLLA Lock Status */\r
+\r
+ __writeMemory32(((0x1 << 29) | (0x3F << 8) | ( 0 << 14) | ((pllmul) << 18) | 1 ), REG_CKGR_PLLAR,"Memory");\r
+ //__writeMemory32((0x03<<8), REG_PMC_PLLICPR,"Memory");\r
+ while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_LOCKA));\r
+ __mac_i=__readMemory32(REG_CKGR_PLLAR,"Memory");\r
+ __message " --- PLL A set up -------------------- REG_CKGR_PLLAR 0x",__mac_i:%X;\r
+}\r
+\r
+/*********************************************************************\r
+* pmc_set_mck_plla_div()\r
+*\r
+* Function description\r
+* Configure MCK PLLA divider.\r
+*********************************************************************/\r
+pmc_set_mck_plla_div()\r
+{\r
+ REG_PMC_MCKR = 0xF0014030; /*(PMC) Master Clock Register */\r
+ PMC_MCKR_PLLADIV2_DIV2 = (0x1 << 12); /*(PMC_MCKR) PLLA clock frequency is divided by 2. */\r
+ __tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");\r
+ if ((__tempo_var & PMC_MCKR_PLLADIV2_DIV2) != PMC_MCKR_PLLADIV2_DIV2)\r
+ {\r
+ __tempo_var |= PMC_MCKR_PLLADIV2_DIV2;\r
+ __writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");\r
+ while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));\r
+ }\r
+}\r
+\r
+/*********************************************************************\r
+* pmc_set_mck_prescaler()\r
+*\r
+* Function description\r
+* Configure MCK Prescaler.\r
+*********************************************************************/\r
+pmc_set_mck_prescaler()\r
+{\r
+ REG_PMC_MCKR = 0xF0014030; /*(PMC) Master Clock Register */\r
+ PMC_MCKR_PRES_Msk = (0x7 << 4); /*(PMC_MCKR) Master/Processor Clock Prescaler */\r
+ PMC_MCKR_PRES_CLOCK = (0x0 << 4); /*(PMC_MCKR) Selected clock */\r
+\r
+ /* Change MCK Prescaler divider in PMC_MCKR register */\r
+ __tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");\r
+ __tempo_var = (__tempo_var & ~PMC_MCKR_PRES_Msk) | PMC_MCKR_PRES_CLOCK;\r
+ __writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");\r
+ while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));\r
+ __mac_i=__readMemory32(REG_PMC_MCKR,"Memory");\r
+ __message " --- Master clock prescaler set ------ REG_PMC_MCKR 0x",__mac_i:%X;\r
+}\r
+\r
+/*********************************************************************\r
+* pmc_set_mck_divider()\r
+*\r
+* Function description\r
+* Configure MCK Divider.\r
+*********************************************************************/\r
+pmc_set_mck_divider()\r
+{\r
+ REG_PMC_MCKR = 0xF0014030; /*(PMC) Master Clock Register */\r
+ PMC_MCKR_MDIV_Msk = (0x3 << 8); /*(PMC_MCKR) Master Clock Division */\r
+ PMC_MCKR_MDIV_PCK_DIV3 = (0x3 << 8); /*(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */\r
+\r
+ /* change MCK Prescaler divider in PMC_MCKR register */\r
+ __tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");\r
+ __tempo_var = (__tempo_var & ~PMC_MCKR_MDIV_Msk) | PMC_MCKR_MDIV_PCK_DIV3;\r
+ __writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");\r
+ while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));\r
+ __mac_i=__readMemory32(REG_PMC_MCKR,"Memory");\r
+ __message " --- Master clock divider set -------- REG_PMC_MCKR 0x",__mac_i:%X;\r
+}\r
+\r
+/*********************************************************************\r
+* pmc_switch_mck_to_pll()\r
+*\r
+* Function description\r
+* Switch PMC from MCK to PLL clock.\r
+*********************************************************************/\r
+pmc_switch_mck_to_pll()\r
+{\r
+ REG_PMC_MCKR = 0xF0014030; /*(PMC) Master Clock Register */\r
+ PMC_MCKR_CSS_PLLA_CLK = (0x2 << 0); /*(PMC_MCKR) PLLACK/PLLADIV2 is selected */\r
+\r
+ /* Select PLL as input clock for PCK and MCK */\r
+ __tempo_var = __readMemory32(REG_PMC_MCKR,"Memory");\r
+ __tempo_var = (__tempo_var & ~0x03) | PMC_MCKR_CSS_PLLA_CLK;\r
+ __writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory");\r
+ while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY));\r
+ __mac_i=__readMemory32(REG_PMC_MCKR,"Memory");\r
+ __message " --- Master clock is on PLL ---------- REG_PMC_MCKR 0x",__mac_i:%X;\r
+}\r
+\r
+\r
+\r
+send_nop()\r
+{\r
+ __writeMemory32(0x00000001,0xF000C000,"Memory");\r
+ /* Write to memory to acknoledge the command */\r
+ __writeMemory32(0x00000000,0x20000000,"Memory");\r
+}\r
+\r
+send_ext_lmr(opcode, offset)\r
+{\r
+ __writeMemory32(0x00000005,0xF000C000,"Memory");\r
+ /* Write to memory to acknoledge the command */\r
+ __writeMemory32(0x00000000,0x20000000 + (opcode << offset),"Memory");\r
+}\r
+\r
+send_lmr()\r
+{\r
+ __writeMemory32(0x00000003,0xF000C000,"Memory");\r
+ /* Write to memory to acknoledge the command */\r
+ __writeMemory32(0x00000000,0x20000000,"Memory");\r
+}\r
+\r
+send_calib()\r
+{\r
+ __writeMemory32(0x00000006,0xF000C000,"Memory");\r
+ /* Write to memory to acknoledge the command */\r
+ __writeMemory32(0x00000000,0x20000000,"Memory");\r
+}\r
+\r
+send_normal()\r
+{\r
+ __writeMemory32(0x00000000,0xF000C000,"Memory");\r
+ /* Write to memory to acknoledge the command */\r
+ __writeMemory32(0x00000000,0x20000000,"Memory");\r
+}\r
+\r
+\r
+matrix_configure_slave_ddr()\r
+{\r
+\r
+ /* matrix_remove_write_protection(MATRIX0);*/\r
+ __tempo_reg = 0xF00181E4;\r
+ __tempo_var = (0x4D4154u << 8);\r
+ __writeMemory32(__tempo_var, __tempo_reg,"Memory");\r
+\r
+ for (__tempo_var = 3 ; __tempo_var < 10 ; __tempo_var = __tempo_var + 1)\r
+ {\r
+ __tempo_reg = 0xF0018200 + 4 * __tempo_var;\r
+ /* matrix_configure_slave_sec(MATRIX0, i, 0xFF, 0xFF, 0xFF); */\r
+ __writeMemory32(0xFFFFFF, __tempo_reg,"Memory");\r
+\r
+ /* matrix_set_slave_split_addr(MATRIX0, i, MATRIX_AREA_128M, 0xF);*/\r
+ __tempo_reg = 0xF0018240 + 4 * __tempo_var;\r
+ __writeMemory32(0xFFFF, __tempo_reg,"Memory");\r
+\r
+ /* matrix_set_slave_region_size(MATRIX0, i, MATRIX_AREA_128M, 0x1); */\r
+ __tempo_reg = 0xF0018280 + 4 * __tempo_var;\r
+ __writeMemory32(0xF, __tempo_reg,"Memory");\r
+ }\r
+}\r
+\r
+initialize_ddr()\r
+{\r
+ REG_MPDDRC_RTR = 0xF000C004;\r
+ matrix_configure_slave_ddr();\r
+\r
+ /* Enable DDR and MPDDRC clocks */\r
+ __writeMemory32((1<<2), 0xF0014000, "Memory");\r
+\r
+ __writeMemory32(13, 0xF001410C, "Memory");\r
+ __writeMemory32((13 | (1<<28) | (1<<12)) , 0xF001410C, "Memory");\r
+\r
+ /* Step 1: Program memory device type */\r
+ __writeMemory32(0x00000004, 0xF000C020, "Memory");\r
+\r
+ /* set driver impedance */\r
+ __writeMemory32(0x00000004, 0xF000C034, "Memory");\r
+ __writeMemory32(0x00000002, 0xF000C05C, "Memory");\r
+\r
+ /* Step 2: Program features of the DDR3-SDRAM device in the\r
+ * configuration register and timing parameter registers (TPR0\r
+ * TPR1 and TPR2) */\r
+ __writeMemory32(0x00d0025d, 0xF000C008, "Memory");\r
+\r
+ /* Timings */\r
+ /* tp0 */\r
+ __writeMemory32(0x44439425, 0xF000C00C, "Memory"); //0x32139336\r
+ /* tp1 */\r
+ __writeMemory32(0x0f001d1b, 0xF000C010, "Memory"); //0x03001d1b\r
+ /* tp2 */\r
+ __writeMemory32(0x00072000, 0xF000C014, "Memory"); //0x00072328\r
+\r
+ __tempo_var = __readMemory32(0xF000C008,"Memory");\r
+ __ba_offset = (__tempo_var & 0x3) + 9;\r
+\r
+ if (!(__tempo_var & (1<<0x22))== (1<<0x22) )\r
+ {\r
+ __ba_offset += ((__tempo_var & (0x3<<2))>>2) + 11;\r
+ }\r
+\r
+ __tempo_var = __readMemory32(0xF000C020,"Memory");\r
+\r
+ if (__tempo_var & 0x10)\r
+ {\r
+ __ba_offset += 1;\r
+ }\r
+ else\r
+ {\r
+ __ba_offset += 2;\r
+ }\r
+\r
+ /*\r
+ * Step 3: Issue a NOP command to the memory controller using\r
+ * its mode register (MPDDRC_MR).\r
+ */\r
+ send_nop();\r
+\r
+ /*\r
+ * Step 4: A pause of at least 500us must be observed before a\r
+ * single toggle.\r
+ */\r
+ __delay(50);\r
+\r
+ /*\r
+ * Step 5: Issue a NOP command to the memory controller using\r
+ * its mode register (MPDDRC_MR). CKE is now driven high.\r
+ */\r
+ send_nop();\r
+ __delay(10);\r
+\r
+ /*\r
+ * Step 6: Issue Extended Mode Register Set 2 (EMRS2) cycle to\r
+ * choose between commercial or high temperature\r
+ * operations.\r
+ */\r
+ send_ext_lmr(0x2, __ba_offset);\r
+ __delay(10);\r
+\r
+ /*\r
+ * Step 7: Issue Extended Mode Register Set 3 (EMRS3) cycle to set\r
+ * the Extended Mode Register to 0.\r
+ */\r
+ send_ext_lmr(0x3, __ba_offset);\r
+ __delay(10);\r
+\r
+ /*\r
+ * Step 8: Issue Extended Mode Register Set 1 (EMRS1) cycle to\r
+ * disable and to program O.D.S. (Output Driver Strength).\r
+ */\r
+ send_ext_lmr(0x1, __ba_offset);\r
+ __delay(10);\r
+\r
+ /*\r
+ * Step 9: Write a one to the DLL bit (enable DLL reset) in the MPDDRC\r
+ * Configuration Register (MPDDRC_CR)\r
+ */\r
+ /* Not done for DDR3 */\r
+\r
+ /*\r
+ * Step 10: Issue a Mode Register Set (MRS) cycle to reset DLL.\r
+ */\r
+ send_lmr();\r
+ __delay(10);\r
+\r
+ /*\r
+ * Step 11: Issue a Calibration command (MRS) cycle to calibrate RTT and\r
+ * RON values for the Process Voltage Temperature (PVT).\r
+ */\r
+ send_calib();\r
+ __delay(10);\r
+\r
+ /*\r
+ * Step 12: A Normal Mode command is provided.\r
+ * Program the Normal mode in the MPDDRC_MR and perform a write access\r
+ * to any DDR3-SDRAM address to acknowledge this command.\r
+ */\r
+ send_normal();\r
+ __delay(10);\r
+ /*\r
+ * Step 13: Perform a write access to any DDR3-SDRAM address.\r
+ */\r
+ __writeMemory32(0x00000000,0x20000000,"Memory");\r
+\r
+ /* Last step: Write the refresh rate */\r
+ /* Refresh Timer is (64ms / (bank_size)) * master_clock */\r
+ __writeMemory32(0x511, REG_MPDDRC_RTR,"Memory");\r
+ __delay(10);\r
+\r
+}\r
+\r
+initialize_clocks()\r
+{\r
+ pmc_select_external_osc();\r
+ pmc_switch_mck_to_main();\r
+ pmc_set_mck_plla_div();\r
+ pmc_set_plla(82);\r
+ pmc_set_mck_prescaler();\r
+ pmc_set_mck_divider();\r
+ pmc_switch_mck_to_pll();\r
+}\r
+\r
+/*********************************************************************\r
+* execUserReset()\r
+*********************************************************************/\r
+execUserReset()\r
+{\r
+ __message "--- execUserReset -------------------";\r
+\r
+ /* Reset peripherals (using RSTC_CR) */\r
+ __writeMemory32(0xA5000004, 0xF8048000, "Memory");\r
+\r
+ /* Disable Watchdog (using WDT_MR) */\r
+ __writeMemory32(0x00008000, 0xF8048044, "Memory");\r
+\r
+ /* Disable D-Cache, I-Cache and MMU */\r
+ __jtagCP15WriteReg(1, 0, 0, 0, 0x00C50078);\r
+\r
+ /* Disable all interrupts and go to supervisor mode */\r
+ #CPSR = 0xD3;\r
+\r
+ /* Zero registers (cannot reset core because it will disable JTAG) */\r
+ #R8_fiq = 0;\r
+ #R9_fiq = 0;\r
+ #R10_fiq = 0;\r
+ #R11_fiq = 0;\r
+ #R12_fiq = 0;\r
+ #SP_fiq = 0;\r
+ #LR_fiq = 0;\r
+ #SPSR_fiq = 0;\r
+ #SP_irq = 0;\r
+ #LR_irq = 0;\r
+ #SPSR_irq = 0;\r
+ #SP_abt = 0;\r
+ #LR_abt = 0;\r
+ #SPSR_abt = 0;\r
+ #SP_und = 0;\r
+ #LR_und = 0;\r
+ #SPSR_und = 0;\r
+ #SP_svc = 0;\r
+ #LR_svc = 0;\r
+ #SPSR_svc = 0;\r
+ #R0 = 0;\r
+ #R1 = 0;\r
+ #R2 = 0;\r
+ #R3 = 0;\r
+ #R4 = 0;\r
+ #R5 = 0;\r
+ #R6 = 0;\r
+ #R7 = 0;\r
+ #R8_usr = 0;\r
+ #R9_usr = 0;\r
+ #R10_usr = 0;\r
+ #R11_usr = 0;\r
+ #R12_usr = 0;\r
+ #SP_usr = 0;\r
+ #LR_usr = 0;\r
+}\r
+\r
+/*********************************************************************\r
+* execUserPreload()\r
+*********************************************************************/\r
+execUserPreload()\r
+{\r
+ __message "------------------------------ execUserPreload ---------------------------------";\r
+ /* Reset peripherals (using RSTC_CR) */\r
+ __writeMemory32(0xA5000004, 0xF8048000, "Memory");\r
+\r
+ /* Disable Watchdog (using WDT_MR) */\r
+ __writeMemory32(0x00008000, 0xF8048044, "Memory");\r
+\r
+ /* Disable D-Cache, I-Cache and MMU */\r
+ __jtagCP15WriteReg(1, 0, 0, 0, 0x00C50078);\r
+\r
+ /* Reset L2 Cache controller */\r
+ __writeMemory32(0x0, 0x00A00100, "Memory");\r
+\r
+\r
+ initialize_clocks();\r
+\r
+ initialize_ddr();\r
+}\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_1.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_IROM1_start__ = 0x0;\r
+define symbol __ICFEDIT_region_IROM1_end__ = 0x0;\r
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;\r
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;\r
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;\r
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x200000;\r
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x21FFFF;\r
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\r
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;\r
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x23FFFFFF;\r
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x24000000;\r
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x24FFFFFF;\r
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\r
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_intvec__ = 0x100;\r
+define symbol __ICFEDIT_size_irqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_fiqstack__ = 0x60;\r
+define symbol __ICFEDIT_size_abtstack__ = 0x40;\r
+define symbol __ICFEDIT_size_undstack__ = 0x40;\r
+define symbol __ICFEDIT_size_sysstack__ = 0x40;\r
+define symbol __ICFEDIT_size_cstack__ = 0x3000;\r
+define symbol __ICFEDIT_size_heap__ = 0x200;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region VEC_region = mem:[from __ICFEDIT_region_IRAM1_start__ size __ICFEDIT_size_intvec__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__+__ICFEDIT_size_intvec__ to __ICFEDIT_region_IRAM1_end__];\r
+define region DDRAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];\r
+define region DDRAM_NOCACHE_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };\r
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };\r
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };\r
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };\r
+define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy with packing=none { readwrite };\r
+do not initialize { readonly section .noinit };\r
+/* Warning: ICC still considers the sections below as zero-initialized, by default. */\r
+do not initialize { section .region_sram };\r
+do not initialize { section .region_ddr };\r
+do not initialize { section .region_ddr_nocache };\r
+\r
+place in VEC_region { section .vectors };\r
+place in RAM_region { readonly };\r
+place in RAM_region { section .cstartup };\r
+place in RAM_region { readwrite, block IRQ_STACK, block FIQ_STACK, block ABT_STACK, block UND_STACK, block SYS_STACK, block CSTACK, block HEAP };\r
+place in RAM_region { section .region_sram };\r
+place in DDRAM_region { section .region_ddr };\r
+place in DDRAM_NOCACHE_region { section .region_ddr_nocache };\r
--- /dev/null
+/*********************************************************************\r
+* execUserReset()\r
+*********************************************************************/\r
+execUserReset()\r
+{\r
+ __message "------------------------------ execUserReset ---------------------------------";\r
+\r
+ /* Reset peripherals (using RSTC_CR) */\r
+ __writeMemory32(0xA5000004, 0xF8048000, "Memory");\r
+\r
+ /* Disable Watchdog (using WDT_MR) */\r
+ __writeMemory32(0x00008000, 0xF8048044, "Memory");\r
+\r
+ /* Disable D-Cache, I-Cache and MMU */\r
+ __jtagCP15WriteReg(1, 0, 0, 0, 0x00C50078);\r
+\r
+ /* Reset L2 Cache controller */\r
+ __writeMemory32(0x0, 0x00A00100, "Memory");\r
+\r
+ /* Disable DDR clock and MPDDRC controller to avoid */\r
+ /* corrupted RAM data on soft reset. */\r
+ __writeMemory32(0x00000004, 0xF0014004, "Memory");\r
+ __writeMemory32(0x00002000, 0xF0014014, "Memory");\r
+\r
+ /* Disable all interrupts and go to supervisor mode */\r
+ #CPSR = 0xD3;\r
+\r
+ /* Zero registers (cannot reset core because it will disable JTAG) */\r
+ #R8_fiq = 0;\r
+ #R9_fiq = 0;\r
+ #R10_fiq = 0;\r
+ #R11_fiq = 0;\r
+ #R12_fiq = 0;\r
+ #SP_fiq = 0;\r
+ #LR_fiq = 0;\r
+ #SPSR_fiq = 0;\r
+ #SP_irq = 0;\r
+ #LR_irq = 0;\r
+ #SPSR_irq = 0;\r
+ #SP_abt = 0;\r
+ #LR_abt = 0;\r
+ #SPSR_abt = 0;\r
+ #SP_und = 0;\r
+ #LR_und = 0;\r
+ #SPSR_und = 0;\r
+ #SP_svc = 0;\r
+ #LR_svc = 0;\r
+ #SPSR_svc = 0;\r
+ #R0 = 0;\r
+ #R1 = 0;\r
+ #R2 = 0;\r
+ #R3 = 0;\r
+ #R4 = 0;\r
+ #R5 = 0;\r
+ #R6 = 0;\r
+ #R7 = 0;\r
+ #R8_usr = 0;\r
+ #R9_usr = 0;\r
+ #R10_usr = 0;\r
+ #R11_usr = 0;\r
+ #R12_usr = 0;\r
+ #SP_usr = 0;\r
+ #LR_usr = 0;\r
+\r
+ /* Initialize PC */\r
+ #PC = 0x200000;\r
+}\r
+\r
+/*********************************************************************\r
+* execUserPreload()\r
+*********************************************************************/\r
+execUserPreload()\r
+{\r
+ __message "------------------------------ execUserPreload ---------------------------------";\r
+}\r
--- /dev/null
+# ----------------------------------------------------------------------------\r
+# SAM Software Package License\r
+# ----------------------------------------------------------------------------\r
+# Copyright (c) 2015, Atmel Corporation\r
+#\r
+# All rights reserved.\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# - Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the disclaimer below.\r
+#\r
+# Atmel's name may not be used to endorse or promote products derived from\r
+# this software without specific prior written permission.\r
+#\r
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+# ----------------------------------------------------------------------------\r
+\r
+CFLAGS_INC += -I$(TOP)/utils\r
+\r
+lib-y += utils/utils.a\r
+\r
+utils-y := utils/dbg_util.o\r
+utils-y += utils/hamming.o\r
+utils-y += utils/rand.o\r
+utils-y += utils/trace.o\r
+utils-y += utils/syscalls.o\r
+utils-y += utils/crc.o\r
+utils-y += utils/timer.o\r
+utils-y += utils/mutex.o\r
+utils-y += utils/mutex_gcc.o\r
+utils-y += utils/font.o\r
+utils-y += utils/lcd_draw.o\r
+utils-y += utils/lcd_font.o\r
+utils-y += utils/wav.o\r
+\r
+UTILS_OBJS := $(addprefix $(BUILDDIR)/,$(utils-y))\r
+\r
+-include $(UTILS_OBJS:.o=.d)\r
+\r
+$(BUILDDIR)/utils/utils.a: $(UTILS_OBJS)\r
+ @mkdir -p $(dir $@)\r
+ $(ECHO) AR $@\r
+ $(Q)$(AR) -cr $@ $^\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Provide a routine for asynchronos transfer.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "chip.h"\r
+#include "async.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+/**\r
+* \brief Returns 1 if the given transfer has ended; otherwise returns 0.\r
+* \param pAsync Pointer to an Async instance.\r
+*/\r
+uint32_t async_is_finished(struct _async * pAsync)\r
+{\r
+ return (pAsync->status != ASYNC_STATUS_PENDING);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Provide a routine for asynchronous transfer.\r
+ *\r
+ */\r
+\r
+#ifndef _ASYNC_\r
+#define _ASYNC_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definition\r
+ *----------------------------------------------------------------------------*/\r
+/** Transfer is still pending.*/\r
+#define ASYNC_STATUS_PENDING 0xFF\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Type\r
+ *----------------------------------------------------------------------------*/\r
+/** \brief Asynchronous transfer descriptor. */\r
+struct _async {\r
+ /** Asynchronous transfer status.*/\r
+ volatile uint32_t status;\r
+ /** Callback function to invoke when transfer completes or fails.*/\r
+ void *callback;\r
+ /** Driver storage area; do not use.*/\r
+ uint8_t pStorage[12];\r
+} ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+extern uint32_t async_is_finished(struct _async * pAsync);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* #ifndef _ASYNC_ */\r
--- /dev/null
+#ifndef _COMPILER_H_\r
+#define _COMPILER_H_\r
+\r
+#define _CC_PRAGMA(x) _Pragma(#x)\r
+\r
+#define PACK_SET(alignment) _CC_PRAGMA(pack(alignment))\r
+#define PACK_RESET() _CC_PRAGMA(pack())\r
+\r
+#if defined(__ICCARM__)\r
+ #define WEAK __weak\r
+ #define CONSTRUCTOR\r
+ #define SECTION(a) _CC_PRAGMA(location = a)\r
+ #define ALIGNED(a) _CC_PRAGMA(data_alignment = a)\r
+#elif defined(__GNUC__)\r
+ #define WEAK __attribute__((weak))\r
+ #define CONSTRUCTOR __attribute__((constructor))\r
+ #define SECTION(a) __attribute__((__section__(a)))\r
+ #define ALIGNED(a) __attribute__((__aligned__(a)))\r
+#else\r
+ #error Unknown compiler!\r
+#endif\r
+\r
+#if defined(__ICCARM__)\r
+ #define DMB() asm("dmb")\r
+ #define DSB() asm("dsb")\r
+ #define ISB() asm("isb")\r
+ #define COMPILER_BARRIER()\r
+#elif defined(__GNUC__)\r
+ #define DMB() asm("dmb":::"memory")\r
+ #define DSB() asm volatile ("dsb":::"memory")\r
+ #define ISB() asm volatile ("isb":::"memory")\r
+ #define COMPILER_BARRIER() asm volatile ("":::"memory")\r
+#else\r
+ #error Unknown compiler!\r
+#endif\r
+\r
+#ifndef NULL\r
+ #define NULL ((void*)0)\r
+#endif\r
+\r
+#define ROUND_UP_MULT(x,m) (((x) + ((m)-1)) & ~((m)-1))\r
+\r
+#define ROUND_INT_DIV(n,d) ((2 * (n) + (d)) / (2 * (d)))\r
+\r
+#define ARRAY_SIZE(x) (sizeof ((x)) / sizeof(*(x)))\r
+\r
+#define _STRINGY_EXPAND(x) #x\r
+#define STRINGIFY(x) _STRINGY_EXPAND(x)\r
+\r
+#if defined(__GNUC__) && \\r
+ (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 8))\r
+ #define SWAP(a, b) do { \\r
+ __auto_type _swp = (a); \\r
+ (a) = (b); \\r
+ (b) = _swp; } while (0)\r
+#else\r
+ /* The compiler will replace memcpy calls with direct assignations */\r
+ #define SWAP(a, b) do { \\r
+ uint8_t _swp[sizeof(a) == sizeof(b) ? (signed)sizeof(a) : -1]; \\r
+ memcpy(_swp, &(a), sizeof(a)); \\r
+ memcpy(&(a), &(b), sizeof(a)); \\r
+ memcpy(&(b), _swp, sizeof(a)); } while(0)\r
+#endif\r
+\r
+#define BIG_ENDIAN_TO_HOST(x) (((x) & 0xFF) << 24) | (((x) & 0xFF00) << 8) \\r
+ | (((x) & 0xFF0000) >> 8) | (((x) & 0xFF000000) >> 24)\r
+\r
+#endif /* _COMPILER_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "chip.h"\r
+\r
+#include "crc.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+uint8_t Crc8;\r
+\r
+//------------------------------------------------------------------------------\r
+/// Local functions\r
+//------------------------------------------------------------------------------\r
+\r
+//------------------------------------------------------------------------------\r
+// Calculate the CRC8 of the byte value provided with the current\r
+// global 'crc8' value.\r
+// Returns current global crc8 value\r
+//------------------------------------------------------------------------------\r
+\r
+static const uint8_t dscrc_table[] =\r
+{\r
+ 0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65,\r
+ 157,195, 33,127,252,162, 64, 30, 95, 1,227,189, 62, 96,130,220,\r
+ 35,125,159,193, 66, 28,254,160,225,191, 93, 3,128,222, 60, 98,\r
+ 190,224, 2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255,\r
+ 70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89, 7,\r
+ 219,133,103, 57,186,228, 6, 88, 25, 71,165,251,120, 38,196,154,\r
+ 101, 59,217,135, 4, 90,184,230,167,249, 27, 69,198,152,122, 36,\r
+ 248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91, 5,231,185,\r
+ 140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205,\r
+ 17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80,\r
+ 175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238,\r
+ 50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115,\r
+ 202,148,118, 40,171,245, 23, 73, 8, 86,180,234,105, 55,213,139,\r
+ 87, 9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22,\r
+ 233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168,\r
+ 116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53};\r
+\r
+static uint8_t _do_crc8 (uint8_t value)\r
+{\r
+ return dscrc_table[Crc8 ^ value];\r
+}\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+\r
+uint8_t compute_crc8 (uint8_t* pData, uint8_t Length)\r
+{\r
+ Crc8 = 0x00;\r
+ while (Length)\r
+ {\r
+ Crc8 = _do_crc8( *pData);\r
+ pData ++;\r
+ Length--;\r
+ }\r
+ return Crc8;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _CRC_H_\r
+#define _CRC_H_\r
+\r
+#include <stdint.h>\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+\r
+extern uint8_t compute_crc8 (uint8_t* pData, uint8_t Length);\r
+\r
+\r
+#endif // _CRC_H_\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Implement simple DBGU usage as stream receiver.\r
+ */\r
+\r
+/*-------------------------------\r
+ * Headers\r
+ *-------------------------------*/\r
+\r
+//#include <board.h>\r
+#include <stdio.h>\r
+#include "dbg_util.h"\r
+#include "timer.h"\r
+\r
+#include "misc/console.h"\r
+\r
+/*-------------------------------\r
+ * Defines\r
+ *-------------------------------*/\r
+\r
+/** Data RX timeout in binary start up */\r
+#define TIMEOUT_RX_START (1000*20)\r
+/** Data RX timeout default value */\r
+#define TIMEOUT_RX (200)\r
+\r
+/* ASCII Character Codes */\r
+#define SOH 0x01\r
+#define STX 0x02\r
+#define EOT 0x04\r
+#define CTRL_D 0x04 /**< Transfer Done */\r
+#define ACK 0x06\r
+#define NAK 0x15\r
+#define CAN 0x18 /**< Cancel transfer */\r
+#define CTRL_X 0x24\r
+\r
+/* 1K XMODEM Parameters */\r
+#define SOH_LENGTH 128\r
+#define STX_LENGTH 1024\r
+#define SOH_TIMEOUT 1000\r
+\r
+/*-------------------------------\r
+ * Local functions\r
+ *-------------------------------*/\r
+\r
+/**\r
+ * \brief Compute the CRC\r
+ */\r
+static uint16_t\r
+_GetCRC(uint8_t bByte, uint16_t wCrc)\r
+{\r
+ int32_t cnt;\r
+ uint8_t newBit;\r
+ for (cnt = 7; cnt >= 0; cnt--) {\r
+ newBit = ((wCrc >> 15) & 0x1) ^ ((bByte >> cnt) & 0x1);\r
+ wCrc <<= 1;\r
+ if (newBit)\r
+ wCrc ^= (0x1021);\r
+ }\r
+ return wCrc;\r
+\r
+}\r
+\r
+/*-------------------------------\r
+ * Exported functions\r
+ *-------------------------------*/\r
+\r
+/**\r
+ * \brief Receives byte with timeout.\r
+ * \param pByte pointer to locate received byte, can be NULL\r
+ * to discard data.\r
+ * \param timeOut timeout setting, in number of ticks.\r
+ */\r
+uint8_t\r
+DbgReceiveByte(uint8_t * pByte, uint32_t timeOut)\r
+{\r
+ uint32_t tick;\r
+ uint32_t delay;\r
+ tick = timer_get_tick();\r
+ while (1) {\r
+ if (console_is_rx_ready()) {\r
+ uint8_t tmp = console_get_char();\r
+ if (pByte)\r
+ *pByte = tmp;\r
+ return 1;\r
+ }\r
+\r
+ if (timeOut == 0) {\r
+ /* Never timeout */\r
+ } else {\r
+ delay = timer_get_interval(tick, timer_get_tick());\r
+ if (delay > timeOut) {\r
+ return 0;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Receives raw binary file through DBGU.\r
+ * \param bStart 1 to start a new data stream.\r
+ * \param address receiving data address\r
+ * \param maxSize max receive data size in bytes\r
+ * \return number of received bytes\r
+ */\r
+uint32_t\r
+DbgReceiveBinary(uint8_t bStart, uint32_t address, uint32_t maxSize)\r
+{\r
+ volatile uint32_t tick0;\r
+ uint32_t delay;\r
+ uint8_t *pBuffer = (uint8_t *) address;\r
+ uint8_t xSign = 0;\r
+ uint32_t rxCnt = 0;\r
+\r
+ if (maxSize == 0)\r
+ return 0;\r
+\r
+ if (bStart) {\r
+ printf("\n\r-- Please start binary data in %d seconds:\n\r",\r
+ TIMEOUT_RX_START / 1000);\r
+ tick0 = timer_get_tick();\r
+ while (1) {\r
+ if (console_is_rx_ready()) {\r
+ pBuffer[rxCnt++] = console_get_char();\r
+ console_put_char(' ');\r
+ break;\r
+ } else {\r
+ delay = timer_get_interval(tick0, timer_get_tick());\r
+ if ((delay % 1000) == 0) {\r
+ if (xSign == 0) {\r
+ console_put_char('*');\r
+ xSign = 1;\r
+ }\r
+ } else if (xSign) {\r
+ xSign = 0;\r
+ }\r
+\r
+ if (delay > TIMEOUT_RX_START) {\r
+ printf("\n\rRX timeout!\n\r");\r
+ return rxCnt;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Get data */\r
+ while (1) {\r
+ tick0 = timer_get_tick();\r
+ while (1) {\r
+ if (console_is_rx_ready()) {\r
+ pBuffer[rxCnt++] = console_get_char();\r
+ if ((rxCnt % (10 * 1024)) == 0) {\r
+ console_put_char('.');\r
+ }\r
+ if (rxCnt >= maxSize) {\r
+ /* Wait until file transfer finished */\r
+ return rxCnt;\r
+ }\r
+ break;\r
+ }\r
+ delay = timer_get_interval(tick0, timer_get_tick());\r
+ if (delay > TIMEOUT_RX) {\r
+ return rxCnt;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Receives raw binary file through DBGU.\r
+ *\r
+ * \note When "CCC..", uses Ctrl + D to exit.\r
+ *\r
+ * \param pktBuffer 1K size packet buffer\r
+ * \param address receiving data address\r
+ * \param maxSize max receive data size in bytes\r
+ * \return number of received bytes\r
+ */\r
+uint32_t\r
+DbgReceive1KXModem(uint8_t * pktBuffer, uint32_t address, uint32_t maxSize)\r
+{\r
+ uint8_t inChar;\r
+ uint32_t i, index = 0, pktLen = 0;\r
+ uint8_t pktNum = 0, prevPktNum = 0;\r
+ uint32_t error = 0;\r
+ uint16_t inCrc, myCrc;\r
+ uint8_t inCheckSum = 0xFF, checkSum = 0;\r
+ uint8_t *pBuffer = (uint8_t *) address;\r
+ uint32_t totalLen = 0;\r
+\r
+ console_put_char('C');\r
+ while (1) {\r
+ if (!DbgReceiveByte(&inChar, SOH_TIMEOUT)) {\r
+ console_put_char('C');\r
+ continue;\r
+ }\r
+ /* Done */\r
+ if (EOT == inChar) {\r
+ error = 0;\r
+ console_put_char(ACK);\r
+ break;\r
+ } else if (CAN == inChar) {\r
+ error = 2;\r
+ } else if (CTRL_X == inChar) {\r
+ error = 3;\r
+ } else if (SOH == inChar) {\r
+ pktLen = SOH_LENGTH;\r
+ } else if (STX == inChar) {\r
+ pktLen = STX_LENGTH;\r
+ } else\r
+ continue;\r
+ /* Get Packet Number */\r
+ if (!DbgReceiveByte(&pktNum, SOH_TIMEOUT))\r
+ error = 4;\r
+ /* Get 1's complement of packet number */\r
+ if (!DbgReceiveByte(&inChar, SOH_TIMEOUT))\r
+ error = 5;\r
+ /* Get 1 packet of information. */\r
+ checkSum = 0;\r
+ myCrc = 0;\r
+ index = 0;\r
+ for (i = 0; i < pktLen; i++) {\r
+ if (!DbgReceiveByte(&inChar, SOH_TIMEOUT))\r
+ error = 6;\r
+ checkSum += inChar;\r
+ myCrc = _GetCRC(inChar, myCrc);\r
+ if (pktNum != prevPktNum) {\r
+ pktBuffer[index++] = inChar;\r
+ }\r
+ }\r
+ /* Get CRC bytes */\r
+ if (!DbgReceiveByte(&inCheckSum, SOH_TIMEOUT))\r
+ error = 7;\r
+ inCrc = inCheckSum << 8;\r
+ if (!DbgReceiveByte(&inCheckSum, SOH_TIMEOUT))\r
+ error = 7;\r
+ inCrc += inCheckSum;\r
+ /* If CRC error, NAK */\r
+ if (error || (inCrc != myCrc)) {\r
+ console_put_char(NAK);\r
+ error = 0;\r
+ }\r
+ /* Save packet, ACK and next */\r
+ else {\r
+ prevPktNum = pktNum;\r
+\r
+ /* Buffer full? */\r
+ if (totalLen + pktLen > maxSize) {\r
+ /* Copy until buffer full? */\r
+ /* Stop transfer */\r
+ console_put_char(CAN);\r
+ return totalLen;\r
+ }\r
+\r
+ /* Copy the packet */\r
+ for (i = 0; i < pktLen; i++) {\r
+ pBuffer[totalLen + i] = pktBuffer[i];\r
+ }\r
+ totalLen += pktLen;\r
+ console_put_char(ACK);\r
+ }\r
+ }\r
+\r
+ return totalLen;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * Implements DBG utility that uses DBGU and System tick to get byte or binary\r
+ * stream from DBGU console.\r
+ */\r
+\r
+#ifndef _DBG_UTIL_\r
+#define _DBG_UTIL_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern uint8_t DbgReceiveByte(uint8_t * pByte, uint32_t timeOut);\r
+\r
+extern uint32_t DbgReceiveBinary(uint8_t start,\r
+ uint32_t address, uint32_t maxSize);\r
+\r
+extern uint32_t DbgReceive1KXModem(uint8_t * pktBuffer,\r
+ uint32_t address, uint32_t maxSize);\r
+\r
+#endif /* _DBG_UTIL_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#include "font.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ *\r
+ *----------------------------------------------------------------------------*/\r
+\r
+struct _font_parameters font_param[NB_FONT] = {\r
+ {10, 14, 2, pCharset10x14},\r
+ {10, 8, 1, pCharset10x8},\r
+ {8, 8, 1, pCharset8x8},\r
+ {6, 8, 0, pCharset6x8},\r
+} ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Char set of font 10x14\r
+ *----------------------------------------------------------------------------*/\r
+\r
+const uint8_t pCharset10x14[] =\r
+{\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC,\r
+ 0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0,\r
+ 0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0,\r
+ 0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18,\r
+ 0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC,\r
+ 0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00,\r
+ 0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78,\r
+ 0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18,\r
+ 0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8,\r
+ 0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0,\r
+ 0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0,\r
+ 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0xFC, 0xC1, 0xCC, 0xC3, 0x8C,\r
+ 0xC7, 0x0C, 0xCE, 0x0C, 0xFC, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x70, 0x0C, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x30, 0x0C, 0x70, 0x1C, 0xE0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC,\r
+ 0xC1, 0xCC, 0xC3, 0x8C, 0xE7, 0x0C, 0x7E, 0x0C, 0x3C, 0x0C,\r
+ 0x30, 0x30, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+ 0x03, 0xC0, 0x07, 0xC0, 0x0E, 0xC0, 0x1C, 0xC0, 0x38, 0xC0,\r
+ 0x70, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0xC0,\r
+ 0xFC, 0x30, 0xFC, 0x38, 0xCC, 0x1C, 0xCC, 0x0C, 0xCC, 0x0C,\r
+ 0xCC, 0x0C, 0xCC, 0x0C, 0xCE, 0x1C, 0xC7, 0xF8, 0xC3, 0xF0,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE3, 0x1C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x9C, 0x71, 0xF8, 0x30, 0xF0,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC3, 0xFC,\r
+ 0xC7, 0xFC, 0xCE, 0x00, 0xDC, 0x00, 0xF8, 0x00, 0xF0, 0x00,\r
+ 0x3C, 0xF0, 0x7F, 0xF8, 0xE7, 0x9C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+ 0x3C, 0x00, 0x7E, 0x00, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x1C,\r
+ 0xC3, 0x38, 0xC3, 0x70, 0xE7, 0xE0, 0x7F, 0xC0, 0x3F, 0x80,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x60, 0x3C, 0xF0,\r
+ 0x3C, 0xF0, 0x18, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x44, 0x3C, 0xEC,\r
+ 0x3C, 0xF8, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0,\r
+ 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0x00, 0x00,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x00, 0x00, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x38, 0x70,\r
+ 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,\r
+ 0x30, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC1, 0xEC,\r
+ 0xC3, 0xEC, 0xC3, 0x00, 0xE6, 0x00, 0x7E, 0x00, 0x3C, 0x00,\r
+ 0x30, 0xF0, 0x71, 0xF8, 0xE3, 0x9C, 0xC3, 0x0C, 0xC3, 0xFC,\r
+ 0xC3, 0xFC, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0x3F, 0xFC, 0x7F, 0xFC, 0xE0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,\r
+ 0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xC0, 0x7F, 0xFC, 0x3F, 0xFC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x30, 0x30,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,\r
+ 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x73, 0xF8, 0x33, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x30, 0x00, 0x38, 0xC0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x07, 0x80, 0x07, 0x80, 0x0F, 0xC0,\r
+ 0x1C, 0xE0, 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x70, 0x00, 0x38, 0x00, 0x1F, 0x00,\r
+ 0x1F, 0x00, 0x38, 0x00, 0x70, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00,\r
+ 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,\r
+ 0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x00, 0x3C, 0x00,\r
+ 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0xCC,\r
+ 0xC0, 0xEC, 0xC0, 0x7C, 0xE0, 0x38, 0x7F, 0xFC, 0x3F, 0xEC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x80, 0xC3, 0x80,\r
+ 0xC3, 0xC0, 0xC3, 0xC0, 0xE7, 0x70, 0x7E, 0x3C, 0x3C, 0x1C,\r
+ 0x3C, 0x18, 0x7E, 0x1C, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,\r
+ 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x9C, 0xE1, 0xF8, 0x60, 0xF0,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,\r
+ 0xFF, 0xC0, 0xFF, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,\r
+ 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0xFF, 0xE0, 0xFF, 0xC0,\r
+ 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0xF8,\r
+ 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,\r
+ 0xF0, 0x3C, 0xF8, 0x7C, 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80,\r
+ 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, 0xF8, 0x7C, 0xF0, 0x3C,\r
+ 0xFC, 0x00, 0xFE, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xFC,\r
+ 0x01, 0xFC, 0x03, 0x80, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x00,\r
+ 0xC0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, 0xC1, 0xCC, 0xC3, 0x8C,\r
+ 0xC7, 0x0C, 0xCE, 0x0C, 0xDC, 0x0C, 0xF8, 0x0C, 0xF0, 0x0C,\r
+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C,\r
+ 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x30, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x30,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00,\r
+ 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00,\r
+ 0x38, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x30, 0x06, 0x78, 0x0E, 0xFC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xCC, 0x07, 0xFC, 0x03, 0xF8,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C,\r
+ 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x9C, 0x01, 0xF8, 0x00, 0xF0,\r
+ 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,\r
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0x30,\r
+ 0x00, 0xF0, 0x01, 0xF8, 0x03, 0x9C, 0x03, 0x0C, 0x03, 0x0C,\r
+ 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0xDC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xDC, 0x07, 0xD8, 0x03, 0x90,\r
+ 0x00, 0x00, 0x03, 0x00, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x00,\r
+ 0xE3, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xDC, 0x0F, 0xF8, 0x07, 0xF0,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,\r
+ 0x03, 0x00, 0x03, 0x80, 0x01, 0xFC, 0x00, 0xFC, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0xFC,\r
+ 0x1B, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x1C, 0xCF, 0xF8, 0xCF, 0xF0, 0x00, 0x00,\r
+ 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xE0, 0x01, 0xE0,\r
+ 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x0E, 0x00, 0x07, 0x00, 0x03, 0xC0,\r
+ 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0F, 0xFC, 0x0F, 0xFC,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00,\r
+ 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0xFC, 0x03, 0xFC,\r
+ 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,\r
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0xF8, 0x03, 0xF0,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00,\r
+ 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,\r
+ 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xFC, 0x0F, 0xFC,\r
+ 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00,\r
+ 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x00,\r
+ 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,\r
+ 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xFC, 0x0E, 0x78, 0x06, 0x30,\r
+ 0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0xFF, 0xF0, 0xFF, 0xF8,\r
+ 0x0C, 0x1C, 0x0C, 0x1C, 0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00,\r
+ 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,\r
+ 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,\r
+ 0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,\r
+ 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x0F, 0xE0, 0x0F, 0xC0,\r
+ 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0xF8,\r
+ 0x00, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,\r
+ 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0xF0, 0x01, 0xE0,\r
+ 0x01, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C,\r
+ 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x0C, 0x03, 0x9C, 0x01, 0xF8,\r
+ 0x01, 0xF0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00,\r
+ 0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x3C, 0x0C, 0x7C, 0x0C, 0xEC,\r
+ 0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C,\r
+ 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8,\r
+ 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00,\r
+ 0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C,\r
+ 0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C,\r
+ 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C,\r
+ 0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC,\r
+ 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC\r
+} ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Char set of font 10x8\r
+ *----------------------------------------------------------------------------*/\r
+const uint8_t pCharset10x8[] =\r
+{\r
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // space 0x20\r
+0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18, // !\r
+0x63,0x63,0x63,0x22,0x00,0x00,0x00,0x00,0x00,0x00, // "\r
+0x00,0x36,0x36,0x7F,0x36,0x36,0x36,0x7F,0x36,0x36, // #\r
+0x3E,0x63,0x61,0x60,0x3E,0x03,0x03,0x43,0x63,0x3E, // $\r
+0x00,0x00,0x00,0x61,0x63,0x06,0x0C,0x18,0x33,0x63, // %\r
+0x00,0x1C,0x36,0x36,0x1C,0x3B,0x6E,0x66,0x66,0x3B, // &\r
+0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00, // '\r
+0x0C,0x18,0x18,0x30,0x30,0x30,0x30,0x18,0x18,0x0C, // (\r
+0x18,0x0C,0x0C,0x06,0x06,0x06,0x06,0x0C,0x0C,0x18, // )\r
+0x00,0x00,0x42,0x66,0x3C,0xFF,0x3C,0x66,0x42,0x00, // *\r
+0x00,0x00,0x18,0x18,0x18,0xFF,0x18,0x18,0x18,0x00, // +\r
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18, // ,\r
+0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00, // -\r
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18, // .\r
+0x01,0x03,0x07,0x0E,0x1C,0x38,0x70,0xE0,0xC0,0x80, // / (forward slash)\r
+0x3E,0x63,0x63,0x63,0x6B,0x6B,0x63,0x63,0x63,0x3E, // 0 0x30\r
+0x0C,0x1C,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3F, // 1\r
+0x3E,0x63,0x03,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F, // 2\r
+0x3E,0x63,0x03,0x03,0x1E,0x03,0x03,0x03,0x63,0x3E, // 3\r
+0x06,0x0E,0x1E,0x36,0x66,0x66,0x7F,0x06,0x06,0x0F, // 4\r
+0x7F,0x60,0x60,0x60,0x7E,0x03,0x03,0x63,0x73,0x3E, // 5\r
+0x1C,0x30,0x60,0x60,0x7E,0x63,0x63,0x63,0x63,0x3E, // 6\r
+0x7F,0x63,0x03,0x06,0x06,0x0C,0x0C,0x18,0x18,0x18, // 7\r
+0x3E,0x63,0x63,0x63,0x3E,0x63,0x63,0x63,0x63,0x3E, // 8\r
+0x3E,0x63,0x63,0x63,0x63,0x3F,0x03,0x03,0x06,0x3C, // 9\r
+0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18, // :\r
+0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18, // ;\r
+0x00,0x06,0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x06, // <\r
+0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00, // =\r
+0x00,0x60,0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x60, // >\r
+0x3E,0x63,0x63,0x06,0x0C,0x0C,0x0C,0x00,0x0C,0x0C, // ?\r
+0x3E,0x63,0x63,0x6F,0x6B,0x6B,0x6E,0x60,0x60,0x3E, // @ 0x40\r
+0x08,0x1C,0x36,0x63,0x63,0x63,0x7F,0x63,0x63,0x63, // A\r
+0x7E,0x33,0x33,0x33,0x3E,0x33,0x33,0x33,0x33,0x7E, // B\r
+0x1E,0x33,0x61,0x60,0x60,0x60,0x60,0x61,0x33,0x1E, // C\r
+0x7C,0x36,0x33,0x33,0x33,0x33,0x33,0x33,0x36,0x7C, // D\r
+0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x31,0x33,0x7F, // E\r
+0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x30,0x30,0x78, // F\r
+0x1E,0x33,0x61,0x60,0x60,0x6F,0x63,0x63,0x37,0x1D, // G\r
+0x63,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x63,0x63, // H\r
+0x3C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x3C, // I\r
+0x0F,0x06,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C, // J\r
+0x73,0x33,0x36,0x36,0x3C,0x36,0x36,0x33,0x33,0x73, // K\r
+0x78,0x30,0x30,0x30,0x30,0x30,0x30,0x31,0x33,0x7F, // L\r
+0x63,0x77,0x7F,0x6B,0x63,0x63,0x63,0x63,0x63,0x63, // M\r
+0x63,0x63,0x73,0x7B,0x7F,0x6F,0x67,0x63,0x63,0x63, // N\r
+0x1C,0x36,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C, // O\r
+0x7E,0x33,0x33,0x33,0x3E,0x30,0x30,0x30,0x30,0x78, // P 0x50\r
+0x3E,0x63,0x63,0x63,0x63,0x6B,0x6F,0x3E,0x06,0x07, // Q\r
+0x7E,0x33,0x33,0x33,0x3E,0x36,0x36,0x33,0x33,0x73, // R\r
+0x3E,0x63,0x63,0x30,0x1C,0x06,0x03,0x63,0x63,0x3E, // S\r
+0xFF,0xDB,0x99,0x18,0x18,0x18,0x18,0x18,0x18,0x3C, // T\r
+0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x3E, // U\r
+0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x08, // V\r
+0x63,0x63,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x36, // W\r
+0xC3,0xC3,0x66,0x3C,0x18,0x18,0x3C,0x66,0xC3,0xC3, // X\r
+0xC3,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x18,0x18,0x3C, // Y\r
+0x7F,0x63,0x43,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F, // Z\r
+0x3C,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x3C, // [\r
+0x80,0xC0,0xE0,0x70,0x38,0x1C,0x0E,0x07,0x03,0x01, // \ (back slash)\r
+0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C, // ]\r
+0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00,0x00,0x00, // ^\r
+0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00, // _\r
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // ` 0x60\r
+0x00,0x00,0x00,0x3C,0x46,0x06,0x3E,0x66,0x66,0x3B, // a\r
+0x70,0x30,0x30,0x3C,0x36,0x33,0x33,0x33,0x33,0x6E, // b\r
+0x00,0x00,0x00,0x3E,0x63,0x60,0x60,0x60,0x63,0x3E, // c\r
+0x0E,0x06,0x06,0x1E,0x36,0x66,0x66,0x66,0x66,0x3B, // d\r
+0x00,0x00,0x00,0x3E,0x63,0x63,0x7E,0x60,0x63,0x3E, // e\r
+0x1C,0x36,0x32,0x30,0x7C,0x30,0x30,0x30,0x30,0x78, // f\r
+0x00,0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x66,0x3C, // g\r
+0x70,0x30,0x30,0x36,0x3B,0x33,0x33,0x33,0x33,0x73, // h\r
+0x0C,0x0C,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E, // i\r
+0x06,0x06,0x00,0x0E,0x06,0x06,0x06,0x66,0x66,0x3C, // j\r
+0x70,0x30,0x30,0x33,0x33,0x36,0x3C,0x36,0x33,0x73, // k\r
+0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E, // l\r
+0x00,0x00,0x00,0x6E,0x7F,0x6B,0x6B,0x6B,0x6B,0x6B, // m\r
+0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x33,0x33, // n\r
+0x00,0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x3E, // o\r
+0x00,0x00,0x00,0x6E,0x33,0x33,0x3E,0x30,0x30,0x78, // p\r
+0x00,0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x06,0x0F, // q\r
+0x00,0x00,0x00,0x6E,0x3B,0x33,0x30,0x30,0x30,0x78, // r\r
+0x00,0x00,0x00,0x3E,0x63,0x38,0x0E,0x03,0x63,0x3E, // s\r
+0x08,0x18,0x18,0x7E,0x18,0x18,0x18,0x18,0x1B,0x0E, // t\r
+0x00,0x00,0x00,0x66,0x66,0x66,0x66,0x66,0x66,0x3B, // u\r
+0x00,0x00,0x00,0x63,0x63,0x36,0x36,0x1C,0x1C,0x08, // v\r
+0x00,0x00,0x00,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36, // w\r
+0x00,0x00,0x00,0x63,0x36,0x1C,0x1C,0x1C,0x36,0x63, // x\r
+0x00,0x00,0x63,0x63,0x63,0x63,0x3F,0x03,0x06,0x3C, // y\r
+0x00,0x00,0x00,0x7F,0x66,0x0C,0x18,0x30,0x63,0x7F, // z\r
+0x0E,0x18,0x18,0x18,0x70,0x18,0x18,0x18,0x18,0x0E, // {\r
+0x18,0x18,0x18,0x18,0x18,0x00,0x18,0x18,0x18,0x18, // |\r
+0x70,0x18,0x18,0x18,0x0E,0x18,0x18,0x18,0x18,0x70, // }\r
+0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // ~\r
+0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00,0x00,0x00, // DEL\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Char set of font 8x8\r
+ *----------------------------------------------------------------------------*/\r
+const uint8_t pCharset8x8[] =\r
+{\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // U+0020 (space)\r
+ 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18, 0x00, // U+0021 (!)\r
+ 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // U+0022 (")\r
+ 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36, 0x00, // U+0023 (#)\r
+ 0x0C, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x0C, 0x00, // U+0024 ($)\r
+ 0x00, 0x63, 0x33, 0x18, 0x0C, 0x66, 0x63, 0x00, // U+0025 (%)\r
+ 0x1C, 0x36, 0x1C, 0x6E, 0x3B, 0x33, 0x6E, 0x00, // U+0026 (&)\r
+ 0x06, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, // U+0027 (')\r
+ 0x18, 0x0C, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x00, // U+0028 (()\r
+ 0x06, 0x0C, 0x18, 0x18, 0x18, 0x0C, 0x06, 0x00, // U+0029 ())\r
+ 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00, // U+002A (*)\r
+ 0x00, 0x0C, 0x0C, 0x3F, 0x0C, 0x0C, 0x00, 0x00, // U+002B (+)\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x06, // U+002C (,)\r
+ 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, // U+002D (-)\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00, // U+002E (.)\r
+ 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x00, // U+002F (/)\r
+ 0x3E, 0x63, 0x73, 0x7B, 0x6F, 0x67, 0x3E, 0x00, // U+0030 (0)\r
+ 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x3F, 0x00, // U+0031 (1)\r
+ 0x1E, 0x33, 0x30, 0x1C, 0x06, 0x33, 0x3F, 0x00, // U+0032 (2)\r
+ 0x1E, 0x33, 0x30, 0x1C, 0x30, 0x33, 0x1E, 0x00, // U+0033 (3)\r
+ 0x38, 0x3C, 0x36, 0x33, 0x7F, 0x30, 0x78, 0x00, // U+0034 (4)\r
+ 0x3F, 0x03, 0x1F, 0x30, 0x30, 0x33, 0x1E, 0x00, // U+0035 (5)\r
+ 0x1C, 0x06, 0x03, 0x1F, 0x33, 0x33, 0x1E, 0x00, // U+0036 (6)\r
+ 0x3F, 0x33, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00, // U+0037 (7)\r
+ 0x1E, 0x33, 0x33, 0x1E, 0x33, 0x33, 0x1E, 0x00, // U+0038 (8)\r
+ 0x1E, 0x33, 0x33, 0x3E, 0x30, 0x18, 0x0E, 0x00, // U+0039 (9)\r
+ 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x00, // U+003A (:)\r
+ 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x06, // U+003B (//)\r
+ 0x18, 0x0C, 0x06, 0x03, 0x06, 0x0C, 0x18, 0x00, // U+003C (<)\r
+ 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00, // U+003D (=)\r
+ 0x06, 0x0C, 0x18, 0x30, 0x18, 0x0C, 0x06, 0x00, // U+003E (>)\r
+ 0x1E, 0x33, 0x30, 0x18, 0x0C, 0x00, 0x0C, 0x00, // U+003F (?)\r
+ 0x3E, 0x63, 0x7B, 0x7B, 0x7B, 0x03, 0x1E, 0x00, // U+0040 (@)\r
+ 0x0C, 0x1E, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x00, // U+0041 (A)\r
+ 0x3F, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3F, 0x00, // U+0042 (B)\r
+ 0x3C, 0x66, 0x03, 0x03, 0x03, 0x66, 0x3C, 0x00, // U+0043 (C)\r
+ 0x1F, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1F, 0x00, // U+0044 (D)\r
+ 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x46, 0x7F, 0x00, // U+0045 (E)\r
+ 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x06, 0x0F, 0x00, // U+0046 (F)\r
+ 0x3C, 0x66, 0x03, 0x03, 0x73, 0x66, 0x7C, 0x00, // U+0047 (G)\r
+ 0x33, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x33, 0x00, // U+0048 (H)\r
+ 0x1E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00, // U+0049 (I)\r
+ 0x78, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E, 0x00, // U+004A (J)\r
+ 0x67, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x67, 0x00, // U+004B (K)\r
+ 0x0F, 0x06, 0x06, 0x06, 0x46, 0x66, 0x7F, 0x00, // U+004C (L)\r
+ 0x63, 0x77, 0x7F, 0x7F, 0x6B, 0x63, 0x63, 0x00, // U+004D (M)\r
+ 0x63, 0x67, 0x6F, 0x7B, 0x73, 0x63, 0x63, 0x00, // U+004E (N)\r
+ 0x1C, 0x36, 0x63, 0x63, 0x63, 0x36, 0x1C, 0x00, // U+004F (O)\r
+ 0x3F, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x0F, 0x00, // U+0050 (P)\r
+ 0x1E, 0x33, 0x33, 0x33, 0x3B, 0x1E, 0x38, 0x00, // U+0051 (Q)\r
+ 0x3F, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x67, 0x00, // U+0052 (R)\r
+ 0x1E, 0x33, 0x07, 0x0E, 0x38, 0x33, 0x1E, 0x00, // U+0053 (S)\r
+ 0x3F, 0x2D, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00, // U+0054 (T)\r
+ 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F, 0x00, // U+0055 (U)\r
+ 0x33, 0x33, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00, // U+0056 (V)\r
+ 0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63, 0x00, // U+0057 (W)\r
+ 0x63, 0x63, 0x36, 0x1C, 0x1C, 0x36, 0x63, 0x00, // U+0058 (X)\r
+ 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x0C, 0x1E, 0x00, // U+0059 (Y)\r
+ 0x7F, 0x63, 0x31, 0x18, 0x4C, 0x66, 0x7F, 0x00, // U+005A (Z)\r
+ 0x1E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x1E, 0x00, // U+005B ([)\r
+ 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00, // U+005C (\)\r
+ 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x00, // U+005D (])\r
+ 0x08, 0x1C, 0x36, 0x63, 0x00, 0x00, 0x00, 0x00, // U+005E (^)\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, // U+005F (_)\r
+ 0x0C, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, // U+0060 (`)\r
+ 0x00, 0x00, 0x1E, 0x30, 0x3E, 0x33, 0x6E, 0x00, // U+0061 (a)\r
+ 0x07, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3B, 0x00, // U+0062 (b)\r
+ 0x00, 0x00, 0x1E, 0x33, 0x03, 0x33, 0x1E, 0x00, // U+0063 (c)\r
+ 0x38, 0x30, 0x30, 0x3e, 0x33, 0x33, 0x6E, 0x00, // U+0064 (d)\r
+ 0x00, 0x00, 0x1E, 0x33, 0x3f, 0x03, 0x1E, 0x00, // U+0065 (e)\r
+ 0x1C, 0x36, 0x06, 0x0f, 0x06, 0x06, 0x0F, 0x00, // U+0066 (f)\r
+ 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x1F, // U+0067 (g)\r
+ 0x07, 0x06, 0x36, 0x6E, 0x66, 0x66, 0x67, 0x00, // U+0068 (h)\r
+ 0x0C, 0x00, 0x0E, 0x0C, 0x0C, 0x0C, 0x1E, 0x00, // U+0069 (i)\r
+ 0x30, 0x00, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E, // U+006A (j)\r
+ 0x07, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x67, 0x00, // U+006B (k)\r
+ 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00, // U+006C (l)\r
+ 0x00, 0x00, 0x33, 0x7F, 0x7F, 0x6B, 0x63, 0x00, // U+006D (m)\r
+ 0x00, 0x00, 0x1F, 0x33, 0x33, 0x33, 0x33, 0x00, // U+006E (n)\r
+ 0x00, 0x00, 0x1E, 0x33, 0x33, 0x33, 0x1E, 0x00, // U+006F (o)\r
+ 0x00, 0x00, 0x3B, 0x66, 0x66, 0x3E, 0x06, 0x0F, // U+0070 (p)\r
+ 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x78, // U+0071 (q)\r
+ 0x00, 0x00, 0x3B, 0x6E, 0x66, 0x06, 0x0F, 0x00, // U+0072 (r)\r
+ 0x00, 0x00, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x00, // U+0073 (s)\r
+ 0x08, 0x0C, 0x3E, 0x0C, 0x0C, 0x2C, 0x18, 0x00, // U+0074 (t)\r
+ 0x00, 0x00, 0x33, 0x33, 0x33, 0x33, 0x6E, 0x00, // U+0075 (u)\r
+ 0x00, 0x00, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00, // U+0076 (v)\r
+ 0x00, 0x00, 0x63, 0x6B, 0x7F, 0x7F, 0x36, 0x00, // U+0077 (w)\r
+ 0x00, 0x00, 0x63, 0x36, 0x1C, 0x36, 0x63, 0x00, // U+0078 (x)\r
+ 0x00, 0x00, 0x33, 0x33, 0x33, 0x3E, 0x30, 0x1F, // U+0079 (y)\r
+ 0x00, 0x00, 0x3F, 0x19, 0x0C, 0x26, 0x3F, 0x00, // U+007A (z)\r
+ 0x38, 0x0C, 0x0C, 0x07, 0x0C, 0x0C, 0x38, 0x00, // U+007B ()\r
+ 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00, // U+007C (|)\r
+ 0x07, 0x0C, 0x0C, 0x38, 0x0C, 0x0C, 0x07, 0x00, // U+007D ()\r
+ 0x6E, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // U+007E (~)\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // U+007F\r
+} ;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Char set of font 6x8\r
+ *----------------------------------------------------------------------------*/\r
+const uint8_t pCharset6x8[] =\r
+{\r
+0x00,0x00,0x00,0x00,0x00,0x00, // Symbol 20\r
+0x00,0x00,0x00,0x5F,0x00,0x00, // Symbol 21\r
+0x00,0x00,0x03,0x00,0x03,0x00, // Symbol 22\r
+0x22,0x7F,0x22,0x22,0x7F,0x22, // Symbol 23\r
+0x00,0x24,0x2A,0x6B,0x2A,0x12, // Symbol 24\r
+0x00,0x23,0x13,0x08,0x64,0x62, // Symbol 25\r
+0x00,0x3A,0x45,0x45,0x3A,0x28, // Symbol 26\r
+0x00,0x00,0x00,0x02,0x01,0x00, // Symbol 27\r
+0x00,0x00,0x3E,0x41,0x00,0x00, // Symbol 28\r
+0x00,0x00,0x41,0x3E,0x00,0x00, // Symbol 29\r
+0x00,0x2A,0x1C,0x1C,0x2A,0x00, // Symbol 2A\r
+0x00,0x08,0x08,0x3E,0x08,0x08, // Symbol 2B\r
+0x00,0x00,0x80,0x40,0x00,0x00, // Symbol 2C\r
+0x00,0x08,0x08,0x08,0x08,0x00, // Symbol 2D\r
+0x00,0x00,0x00,0x40,0x00,0x00, // Symbol 2E\r
+0x00,0x20,0x10,0x08,0x04,0x02, // Symbol 2F\r
+0x00,0x3E,0x51,0x49,0x45,0x3E, // Symbol 30\r
+0x00,0x00,0x42,0x7F,0x40,0x00, // Symbol 31\r
+0x00,0x62,0x51,0x51,0x51,0x4E, // Symbol 32\r
+0x00,0x21,0x41,0x45,0x45,0x3B, // Symbol 33\r
+0x00,0x18,0x16,0x11,0x7F,0x10, // Symbol 34\r
+0x00,0x27,0x45,0x45,0x45,0x39, // Symbol 35\r
+0x00,0x3E,0x49,0x49,0x49,0x32, // Symbol 36\r
+0x00,0x01,0x61,0x11,0x09,0x07, // Symbol 37\r
+0x00,0x36,0x49,0x49,0x49,0x36, // Symbol 38\r
+0x00,0x26,0x49,0x49,0x49,0x3E, // Symbol 39\r
+0x00,0x00,0x00,0x12,0x00,0x00, // Symbol 3A\r
+0x00,0x00,0x20,0x12,0x00,0x00, // Symbol 3B\r
+0x00,0x08,0x14,0x22,0x41,0x00, // Symbol 3C\r
+0x00,0x14,0x14,0x14,0x14,0x14, // Symbol 3D\r
+0x00,0x41,0x22,0x14,0x08,0x00, // Symbol 3E\r
+0x00,0x06,0x01,0x51,0x09,0x06, // Symbol 3F\r
+0x00,0x3E,0x41,0x4D,0x4D,0x2E, // Symbol 40\r
+0x00,0x78,0x16,0x11,0x16,0x78, // Symbol 41\r
+0x00,0x7F,0x49,0x49,0x49,0x36, // Symbol 42\r
+0x00,0x3E,0x41,0x41,0x41,0x22, // Symbol 43\r
+0x00,0x7F,0x41,0x41,0x41,0x3E, // Symbol 44\r
+0x00,0x7F,0x49,0x49,0x49,0x41, // Symbol 45\r
+0x00,0x7F,0x09,0x09,0x09,0x01, // Symbol 46\r
+0x00,0x3E,0x41,0x41,0x51,0x32, // Symbol 47\r
+0x00,0x7F,0x08,0x08,0x08,0x7F, // Symbol 48\r
+0x00,0x00,0x41,0x7F,0x41,0x00, // Symbol 49\r
+0x00,0x30,0x40,0x41,0x41,0x3F, // Symbol 4A\r
+0x00,0x7F,0x08,0x08,0x14,0x63, // Symbol 4B\r
+0x00,0x7F,0x40,0x40,0x40,0x60, // Symbol 4C\r
+0x00,0x7F,0x04,0x18,0x04,0x7F, // Symbol 4D\r
+0x00,0x7F,0x04,0x08,0x10,0x7F, // Symbol 4E\r
+0x00,0x3E,0x41,0x41,0x41,0x3E, // Symbol 4F\r
+0x00,0x7F,0x09,0x09,0x09,0x06, // Symbol 50\r
+0x00,0x3E,0x41,0x61,0x21,0x5E, // Symbol 51\r
+0x00,0x7F,0x09,0x09,0x19,0x66, // Symbol 52\r
+0x00,0x26,0x49,0x49,0x49,0x32, // Symbol 53\r
+0x00,0x01,0x01,0x7F,0x01,0x01, // Symbol 54\r
+0x00,0x3F,0x40,0x40,0x40,0x3F, // Symbol 55\r
+0x00,0x07,0x18,0x60,0x18,0x07, // Symbol 56\r
+0x00,0x1F,0x60,0x18,0x60,0x1F, // Symbol 57\r
+0x00,0x63,0x14,0x08,0x14,0x63, // Symbol 58\r
+0x00,0x03,0x04,0x78,0x04,0x03, // Symbol 59\r
+0x00,0x61,0x51,0x49,0x45,0x43, // Symbol 5A\r
+0x00,0x00,0x7F,0x41,0x00,0x00, // Symbol 5B\r
+0x00,0x02,0x04,0x08,0x10,0x20, // Symbol 5C\r
+0x00,0x00,0x41,0x7F,0x00,0x00, // Symbol 5D\r
+0x00,0x00,0x00,0x00,0x00,0x00, // Symbol 5E\r
+0x40,0x40,0x40,0x40,0x40,0x40, // Symbol 5F\r
+0x00,0x00,0x00,0x01,0x02,0x00, // Symbol 60\r
+0x00,0x20,0x54,0x54,0x54,0x78, // Symbol 61\r
+0x00,0x7E,0x48,0x48,0x48,0x30, // Symbol 62\r
+0x00,0x38,0x44,0x44,0x44,0x28, // Symbol 63\r
+0x00,0x30,0x48,0x48,0x48,0x7E, // Symbol 64\r
+0x00,0x38,0x54,0x54,0x54,0x18, // Symbol 65\r
+0x00,0x10,0x7C,0x12,0x02,0x04, // Symbol 66\r
+0x00,0x0C,0x52,0x52,0x3C,0x02, // Symbol 67\r
+0x00,0x7E,0x08,0x08,0x08,0x70, // Symbol 68\r
+0x00,0x00,0x00,0x74,0x00,0x00, // Symbol 69\r
+0x00,0x40,0x80,0x80,0x74,0x00, // Symbol 6A\r
+0x00,0x7E,0x10,0x10,0x10,0x6C, // Symbol 6B\r
+0x00,0x00,0x02,0x7E,0x00,0x00, // Symbol 6C\r
+0x00,0x7C,0x04,0x78,0x04,0x78, // Symbol 6D\r
+0x00,0x7C,0x04,0x04,0x04,0x78, // Symbol 6E\r
+0x00,0x38,0x44,0x44,0x44,0x38, // Symbol 6F\r
+0x00,0xFC,0x24,0x24,0x24,0x18, // Symbol 70\r
+0x00,0x18,0x24,0x24,0x24,0xFC, // Symbol 71\r
+0x00,0x7C,0x08,0x04,0x04,0x08, // Symbol 72\r
+0x00,0x48,0x54,0x54,0x54,0x20, // Symbol 73\r
+0x00,0x08,0x3E,0x48,0x40,0x00, // Symbol 74\r
+0x00,0x3C,0x40,0x40,0x40,0x3C, // Symbol 75\r
+0x00,0x1C,0x20,0x40,0x20,0x1C, // Symbol 76\r
+0x00,0x3C,0x40,0x30,0x40,0x3C, // Symbol 77\r
+0x00,0x44,0x28,0x10,0x28,0x44, // Symbol 78\r
+0x00,0x1C,0x20,0xA0,0xA0,0x7C, // Symbol 79\r
+0x00,0x44,0x64,0x54,0x4C,0x44, // Symbol 7A\r
+0x00,0x08,0x36,0x41,0x00,0x00, // Symbol 7B\r
+0x00,0x00,0x00,0x7F,0x00,0x00, // Symbol 7C\r
+0x00,0x00,0x41,0x36,0x08,0x00, // Symbol 7D\r
+0x02,0x01,0x01,0x02,0x02,0x01, // Symbol 7E\r
+0x00,0x7F,0x7F,0x7F,0x7F,0x7F // Symbol 7F\r
+};\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+// End of file\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _FONT_H_\r
+#define _FONT_H_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+typedef enum\r
+{\r
+ FONT10x14 = 0,\r
+ FONT10x8,\r
+ FONT8x8,\r
+ FONT6x8,\r
+} _FONT_enum;\r
+\r
+struct _font_parameters\r
+{\r
+ uint8_t width; /* Font width in pixels. */\r
+ uint8_t height; /* Font height in pixels. */\r
+ uint8_t char_space; /* Inter char space */\r
+ const uint8_t* pfont; /* pointer to char table */\r
+} ;\r
+\r
+#define NB_FONT 4\r
+extern struct _font_parameters font_param[NB_FONT];\r
+\r
+extern const uint8_t pCharset10x14[];\r
+extern const uint8_t pCharset10x8[];\r
+extern const uint8_t pCharset8x8[];\r
+extern const uint8_t pCharset6x8[];\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+//------------------------------------------------------------------------------\r
+#endif /* _FONT_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "hamming.h"\r
+#include "trace.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Internal function\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Counts and return the number of bits set to '1' in the given byte.\r
+ * \param byte Byte to count.\r
+ */\r
+static uint8_t count_bits_in_byte(uint8_t byte)\r
+{\r
+ uint8_t count = 0;\r
+\r
+ while (byte > 0) {\r
+ if (byte & 1) {\r
+ count++;\r
+ }\r
+ byte >>= 1;\r
+ }\r
+\r
+ return count;\r
+}\r
+\r
+/**\r
+ * Counts and return the number of bits set to '1' in the given hamming code.\r
+ * \param code Hamming code.\r
+ */\r
+static uint8_t count_bits_in_code256(uint8_t *code)\r
+{\r
+ return count_bits_in_byte(code[0]) +\r
+ count_bits_in_byte(code[1]) +\r
+ count_bits_in_byte(code[2]);\r
+}\r
+\r
+/**\r
+ * Calculates the 22-bit hamming code for a 256-bytes block of data.\r
+ * \param data Data buffer to calculate code for.\r
+ * \param code Pointer to a buffer where the code should be stored.\r
+ */\r
+static void compute256(const uint8_t *data, uint8_t *code)\r
+{\r
+ uint32_t i;\r
+ uint8_t column_sum = 0;\r
+ uint8_t even_line_code = 0;\r
+ uint8_t odd_line_code = 0;\r
+ uint8_t even_column_code = 0;\r
+ uint8_t odd_column_code = 0;\r
+\r
+ // Xor all bytes together to get the column sum;\r
+ // At the same time, calculate the even and odd line codes\r
+ for (i = 0; i < 256; i++) {\r
+ column_sum ^= data[i];\r
+\r
+ // If the xor sum of the byte is 0, then this byte has no incidence on\r
+ // the computed code; so check if the sum is 1.\r
+ if ((count_bits_in_byte(data[i]) & 1) == 1) {\r
+ // Parity groups are formed by forcing a particular index bit to 0\r
+ // (even) or 1 (odd).\r
+ // Example on one byte:\r
+ //\r
+ // bits (dec) 7 6 5 4 3 2 1 0\r
+ // (bin) 111 110 101 100 011 010 001 000\r
+ // '---'---'---'----------.\r
+ // |\r
+ // groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4 |\r
+ // P2' ooooooo eeeeeee ooooooo eeeeeee P2 |\r
+ // P1' ooo eee ooo eee ooo eee ooo eee P1 |\r
+ // |\r
+ // We can see that: |\r
+ // - P4 -> bit 2 of index is 0 --------------------'\r
+ // - P4' -> bit 2 of index is 1.\r
+ // - P2 -> bit 1 of index if 0.\r
+ // - etc...\r
+ // We deduce that a bit position has an impact on all even Px if\r
+ // the log2(x)nth bit of its index is 0\r
+ // ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3)\r
+ // and on all odd Px' if the log2(x)nth bit of its index is 1\r
+ // ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5)\r
+ //\r
+ // As such, we calculate all the possible Px and Px' values at the\r
+ // same time in two variables, even_line_code and odd_line_code, such as\r
+ // even_line_code bits: P128 P64 P32 P16 P8 P4 P2 P1\r
+ // odd_line_code bits: P128' P64' P32' P16' P8' P4' P2' P1'\r
+ //\r
+ even_line_code ^= (255 - i);\r
+ odd_line_code ^= i;\r
+ }\r
+ }\r
+\r
+ // At this point, we have the line parities, and the column sum. First, We\r
+ // must caculate the parity group values on the column sum.\r
+ for (i = 0; i < 8; i++) {\r
+ if (column_sum & 1) {\r
+ even_column_code ^= (7 - i);\r
+ odd_column_code ^= i;\r
+ }\r
+ column_sum >>= 1;\r
+ }\r
+\r
+ // Now, we must interleave the parity values, to obtain the following layout:\r
+ // Code[0] = Line1\r
+ // Code[1] = Line2\r
+ // Code[2] = Column\r
+ // Line = Px' Px P(x-1)- P(x-1) ...\r
+ // Column = P4' P4 P2' P2 P1' P1 PadBit PadBit\r
+ code[0] = 0;\r
+ code[1] = 0;\r
+ code[2] = 0;\r
+\r
+ for (i = 0; i < 4; i++) {\r
+ code[0] <<= 2;\r
+ code[1] <<= 2;\r
+ code[2] <<= 2;\r
+\r
+ // Line 1\r
+ if ((odd_line_code & 0x80) != 0) {\r
+ code[0] |= 2;\r
+ }\r
+\r
+ if ((even_line_code & 0x80) != 0) {\r
+ code[0] |= 1;\r
+ }\r
+ // Line 2\r
+ if ((odd_line_code & 0x08) != 0) {\r
+ code[1] |= 2;\r
+ }\r
+\r
+ if ((even_line_code & 0x08) != 0) {\r
+ code[1] |= 1;\r
+ }\r
+ // Column\r
+ if ((odd_column_code & 0x04) != 0) {\r
+ code[2] |= 2;\r
+ }\r
+\r
+ if ((even_column_code & 0x04) != 0) {\r
+ code[2] |= 1;\r
+ }\r
+\r
+ odd_line_code <<= 1;\r
+ even_line_code <<= 1;\r
+ odd_column_code <<= 1;\r
+ even_column_code <<= 1;\r
+ }\r
+\r
+ // Invert codes (linux compatibility)\r
+ code[0] = ~code[0];\r
+ code[1] = ~code[1];\r
+ code[2] = ~code[2];\r
+\r
+ trace_debug("Computed code = %02x %02x %02x\n\r",\r
+ (unsigned)code[0],\r
+ (unsigned)code[1],\r
+ (unsigned)code[2]);\r
+}\r
+\r
+/**\r
+ * Verifies and corrects a 256-bytes block of data using the given 22-bits\r
+ * hamming code.\r
+ *\r
+ * \param data Data buffer to check.\r
+ * \param code Hamming code to use for verifying the data.\r
+ *\r
+ * \return 0 if there is no error, otherwise returns a HAMMING_ERROR code.\r
+ */\r
+static uint8_t verify256(uint8_t *data, const uint8_t *code)\r
+{\r
+ /* Calculate new code */\r
+ uint8_t computed_code[3];\r
+ uint8_t correction_code[3];\r
+\r
+ compute256(data, computed_code);\r
+\r
+ /* Xor both codes together */\r
+ correction_code[0] = computed_code[0] ^ code[0];\r
+ correction_code[1] = computed_code[1] ^ code[1];\r
+ correction_code[2] = computed_code[2] ^ code[2];\r
+\r
+ trace_debug("Correction code = %02x %02x %02x\n\r",\r
+ (unsigned)correction_code[0],\r
+ (unsigned)correction_code[1],\r
+ (unsigned)correction_code[2]);\r
+\r
+ // If all bytes are 0, there is no error\r
+ if (correction_code[0] == 0 && correction_code[1] == 0 &&\r
+ correction_code[2] == 0) {\r
+ return 0;\r
+ }\r
+\r
+ /* If there is a single bit error, there are 11 bits set to 1 */\r
+ if (count_bits_in_code256(correction_code) == 11) {\r
+ // Get byte and bit indexes\r
+ uint8_t byte = correction_code[0] & 0x80;\r
+ byte |= (correction_code[0] << 1) & 0x40;\r
+ byte |= (correction_code[0] << 2) & 0x20;\r
+ byte |= (correction_code[0] << 3) & 0x10;\r
+\r
+ byte |= (correction_code[1] >> 4) & 0x08;\r
+ byte |= (correction_code[1] >> 3) & 0x04;\r
+ byte |= (correction_code[1] >> 2) & 0x02;\r
+ byte |= (correction_code[1] >> 1) & 0x01;\r
+\r
+ uint8_t bit = (correction_code[2] >> 5) & 0x04;\r
+ bit |= (correction_code[2] >> 4) & 0x02;\r
+ bit |= (correction_code[2] >> 3) & 0x01;\r
+\r
+ /* Correct bit */\r
+ printf("Correcting byte #%d at bit %d\n\r", byte, bit);\r
+ data[byte] ^= (1 << bit);\r
+\r
+ return HAMMING_ERROR_SINGLEBIT;\r
+ }\r
+\r
+ /* Check if ECC has been corrupted */\r
+ if (count_bits_in_code256(correction_code) == 1) {\r
+ return HAMMING_ERROR_ECC;\r
+ } else {\r
+ /* Otherwise, this is a multi-bit error */\r
+ return HAMMING_ERROR_MULTIPLEBITS;\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Computes 3-bytes hamming codes for a data block whose size is multiple of\r
+ * 256 bytes. Each 256 bytes block gets its own code.\r
+ * \param data Data to compute code for.\r
+ * \param size Data size in bytes.\r
+ * \param code Codes buffer.\r
+ */\r
+void hamming_compute_256x(const uint8_t *data, uint32_t size, uint8_t *code)\r
+{\r
+ trace_debug("hamming_compute_256x()\n\r");\r
+\r
+ while (size > 0) {\r
+ compute256(data, code);\r
+\r
+ data += 256;\r
+ code += 3;\r
+ size -= 256;\r
+ }\r
+}\r
+\r
+/**\r
+ * Verifies 3-bytes hamming codes for a data block whose size is multiple of\r
+ * 256 bytes. Each 256-bytes block is verified with its own code.\r
+ *\r
+ * \return 0 if the data is correct, HAMMING_ERROR_SINGLEBIT if one or more\r
+ * block(s) have had a single bit corrected, or either HAMMING_ERROR_ECC\r
+ * or HAMMING_ERROR_MULTIPLEBITS.\r
+ *\r
+ * \param data Data buffer to verify.\r
+ * \param size Size of the data in bytes.\r
+ * \param code Original codes.\r
+ */\r
+uint8_t hamming_verify_256x(uint8_t *data, uint32_t size, const uint8_t *code)\r
+{\r
+ uint8_t error;\r
+ uint8_t result = 0;\r
+\r
+ trace_debug("hamming_verify_256x()\n\r");\r
+\r
+ while (size > 0) {\r
+ error = verify256(data, code);\r
+\r
+ if (error == HAMMING_ERROR_SINGLEBIT) {\r
+ result = HAMMING_ERROR_SINGLEBIT;\r
+ } else {\r
+ if (error) {\r
+ return error;\r
+ }\r
+ }\r
+\r
+ data += 256;\r
+ code += 3;\r
+ size -= 256;\r
+ }\r
+\r
+ return result;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _HAMMING_\r
+#define _HAMMING_\r
+\r
+#include <stdint.h>\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Defines\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * These are the possible errors when trying to verify a block of data encoded\r
+ * using a Hamming code:\r
+ *\r
+ * \section Errors\r
+ * - HAMMING_ERROR_SINGLEBIT\r
+ * - HAMMING_ERROR_ECC\r
+ * - HAMMING_ERROR_MULTIPLEBITS\r
+ */\r
+\r
+/** A single bit was incorrect but has been recovered. */\r
+#define HAMMING_ERROR_SINGLEBIT 1\r
+\r
+/** The original code has been corrupted. */\r
+#define HAMMING_ERROR_ECC 2\r
+\r
+/** Multiple bits are incorrect in the data and they cannot be corrected. */\r
+#define HAMMING_ERROR_MULTIPLEBITS 3\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+void hamming_compute_256x(const uint8_t *data, uint32_t size, uint8_t *code);\r
+\r
+extern uint8_t hamming_verify_256x(uint8_t *data, uint32_t size,\r
+ const uint8_t *code);\r
+\r
+#endif /* _HAMMING_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _INTMATH_H_\r
+#define _INTMATH_H_\r
+\r
+/**\r
+ * \brief Compute the absolute value of the difference between two integers.\r
+ * \param a The first integer.\r
+ * \param b The second integer.\r
+ * \return The absolute difference.\r
+ */\r
+#define ABS_DIFF(a,b) ((a) < (b) ? (b) - (a) : (a) - (b))\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/**\r
+ * Returns the minimum value between two integers.\r
+ * \param a First integer to compare\r
+ * \param b Second integer to compare\r
+ */\r
+static inline int32_t min_u32(uint32_t a, uint32_t b)\r
+{\r
+ return a < b ? a : b;\r
+}\r
+\r
+/**\r
+ * Returns the absolute value of an integer.\r
+ * \param value Integer value\r
+ */\r
+static inline uint32_t abs_u32(int32_t value)\r
+{\r
+ return value > 0 ? value : -value;\r
+}\r
+\r
+/**\r
+ * Computes and returns x to the power of y.\r
+ * \param x Value\r
+ * \param y Power\r
+ */\r
+static inline uint32_t power_u32(uint32_t x, uint32_t y)\r
+{\r
+ uint32_t result = 1;\r
+ while (y > 0) {\r
+ result *= x;\r
+ y--;\r
+ }\r
+ return result;\r
+}\r
+\r
+/** ISO/IEC 14882:2003(E) - 5.6 Multiplicative operators:\r
+ * The binary / operator yields the quotient, and the binary % operator yields the remainder\r
+ * from the division of the first expression by the second.\r
+ * If the second operand of / or % is zero the behavior is undefined; otherwise (a/b)*b + a%b is equal to a.\r
+ * If both operands are nonnegative then the remainder is nonnegative;\r
+ * if not, the sign of the remainder is implementation-defined 74).\r
+ */\r
+static inline int fixed_mod(int a, int b)\r
+{\r
+ int rem = a % b;\r
+ while (rem < 0)\r
+ rem += b;\r
+\r
+ return rem;\r
+}\r
+\r
+#endif /* _INTMATH_H_ */\r
--- /dev/null
+#ifndef UTILS_IO_HEADER\r
+#define UTILS_IO_HEADER\r
+\r
+#include <stdint.h>\r
+\r
+struct _buffer\r
+{\r
+ uint8_t* data;\r
+ uint32_t size;\r
+};\r
+\r
+static inline void writeb(volatile void* reg, uint8_t value)\r
+{\r
+ *(volatile uint8_t*)reg = value;\r
+}\r
+\r
+static inline void writehw(volatile void* reg, uint16_t value)\r
+{\r
+ *(volatile uint16_t*)reg = value;\r
+}\r
+\r
+static inline void readb(volatile const void* reg, uint8_t* value)\r
+{\r
+ *value = *(volatile const uint8_t*)reg;\r
+}\r
+\r
+static inline void readhw(volatile const void* reg, uint16_t* value)\r
+{\r
+ *value = *(volatile const uint16_t*)reg;\r
+}\r
+\r
+#endif\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef COLOR_H\r
+#define COLOR_H\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * RGB 24-bits color table definition.\r
+ *\r
+ */\r
+\r
+#define color_t uint32_t\r
+\r
+/*\r
+ * RGB 24 Bpp\r
+ */\r
+\r
+// From HTML color names\r
+// 140 color names are defined in the HTML and CSS color specification\r
+// (17 standard colors plus 123 more).\r
+// The table below lists them all, along with their hexadecimal values.\r
+\r
+// The 17 standard colors are: aqua, black, blue, fuchsia, gray, green,\r
+// lime, maroon, navy, olive, orange, purple, red, silver, teal, white,\r
+// and yellow.\r
+\r
+#define COLOR_AliceBlue 0xF0F8FF\r
+#define COLOR_AntiqueWhite 0xFAEBD7\r
+#define COLOR_Aqua 0x00FFFF\r
+#define COLOR_Aquamarine 0x7FFFD4\r
+#define COLOR_AZUR 0xF0FFFF\r
+#define COLOR_BEIGE 0xF5F5DC\r
+#define COLOR_Bisque 0xFFE4C4\r
+#define COLOR_BLACK 0x000000\r
+#define COLOR_BlanchedAlmond 0xFFEBCD\r
+#define COLOR_BLUE 0x0000FF\r
+#define COLOR_BLUEVIOLET 0x8A2BE2\r
+#define COLOR_BROWN 0xA52A2A\r
+#define COLOR_BurlyWood 0xDEB887\r
+#define COLOR_CadetBlue 0x5F9EA0\r
+#define COLOR_Chartreuse 0x7FFF00\r
+#define COLOR_Chocolate 0xD2691E\r
+#define COLOR_Coral 0xFF7F50\r
+#define COLOR_CornflowerBlue 0x6495ED\r
+#define COLOR_Cornsilk 0xFFF8DC\r
+#define COLOR_Crimson 0xDC143C\r
+#define COLOR_CYAN 0x00FFFF\r
+#define COLOR_DARKBLUE 0x00008B\r
+#define COLOR_DARKCYAN 0x008B8B\r
+#define COLOR_DarkGoldenRod 0xB8860B\r
+#define COLOR_DARKGRAY 0xA9A9A9\r
+#define COLOR_DARKGREEN 0x006400\r
+#define COLOR_DarkKhaki 0xBDB76B\r
+#define COLOR_DarkMagenta 0x8B008B\r
+#define COLOR_DarkOliveGreen 0x556B2F\r
+#define COLOR_DarkOrange 0xFF8C00\r
+#define COLOR_DarkOrchid 0x9932CC\r
+#define COLOR_DARKRED 0x8B0000\r
+#define COLOR_DarkSalmon 0xE9967A\r
+#define COLOR_DarkSeaGreen 0x8FBC8F\r
+#define COLOR_DarkSlateBlue 0x483D8B\r
+#define COLOR_DarkSlateGray 0x2F4F4F\r
+#define COLOR_DarkTurquoise 0x00CED1\r
+#define COLOR_DARKVIOLET 0x9400D3\r
+#define COLOR_DeepPink 0xFF1493\r
+#define COLOR_DeepSkyBlue 0x00BFFF\r
+#define COLOR_DimGray 0x696969\r
+#define COLOR_DodgerBlue 0x1E90FF\r
+#define COLOR_FireBrick 0xB22222\r
+#define COLOR_FloralWhite 0xFFFAF0\r
+#define COLOR_ForestGreen 0x228B22\r
+#define COLOR_Fuchsia 0xFF00FF\r
+#define COLOR_Gainsboro 0xDCDCDC\r
+#define COLOR_GhostWhite 0xF8F8FF\r
+#define COLOR_GOLD 0xFFD700\r
+#define COLOR_GoldenRod 0xDAA520\r
+#define COLOR_GRAY 0x808080\r
+#define COLOR_GREEN 0x008000\r
+#define COLOR_GREENYELLOW 0xADFF2F\r
+#define COLOR_HoneyDew 0xF0FFF0\r
+#define COLOR_HotPink 0xFF69B4\r
+#define COLOR_IndianRed 0xCD5C5C\r
+#define COLOR_INDIGO 0x4B0082\r
+#define COLOR_Ivory 0xFFFFF0\r
+#define COLOR_Khaki 0xF0E68C\r
+#define COLOR_Lavender 0xE6E6FA\r
+#define COLOR_LavenderBlush 0xFFF0F5\r
+#define COLOR_LawnGreen 0x7CFC00\r
+#define COLOR_LemonChiffon 0xFFFACD\r
+#define COLOR_LIGHTBLUE 0xADD8E6\r
+#define COLOR_LightCoral 0xF08080\r
+#define COLOR_LIGHTCYAN 0xE0FFFF\r
+#define COLOR_LightGoldenRodYellow 0xFAFAD2\r
+#define COLOR_LIGHTGREY 0xD3D3D3\r
+#define COLOR_LIGHTGREEN 0x90EE90\r
+#define COLOR_LightPink 0xFFB6C1\r
+#define COLOR_LightSalmon 0xFFA07A\r
+#define COLOR_LightSeaGreen 0x20B2AA\r
+#define COLOR_LightSkyBlue 0x87CEFA\r
+#define COLOR_LightSlateGray 0x778899\r
+#define COLOR_LightSteelBlue 0xB0C4DE\r
+#define COLOR_LightYellow 0xFFFFE0\r
+#define COLOR_Lime 0x00FF00\r
+#define COLOR_LimeGreen 0x32CD32\r
+#define COLOR_Linen 0xFAF0E6\r
+#define COLOR_MAGENTA 0xFF00FF\r
+#define COLOR_Maroon 0x800000\r
+#define COLOR_MediumAquaMarine 0x66CDAA\r
+#define COLOR_MediumBlue 0x0000CD\r
+#define COLOR_MediumOrchid 0xBA55D3\r
+#define COLOR_MediumPurple 0x9370DB\r
+#define COLOR_MediumSeaGreen 0x3CB371\r
+#define COLOR_MediumSlateBlue 0x7B68EE\r
+#define COLOR_MediumSpringGreen 0x00FA9A\r
+#define COLOR_MediumTurquoise 0x48D1CC\r
+#define COLOR_MediumVioletRed 0xC71585\r
+#define COLOR_MidnightBlue 0x191970\r
+#define COLOR_MintCream 0xF5FFFA\r
+#define COLOR_MistyRose 0xFFE4E1\r
+#define COLOR_Moccasin 0xFFE4B5\r
+#define COLOR_NavajoWhite 0xFFDEAD\r
+#define COLOR_NAVY 0x000080\r
+#define COLOR_OldLace 0xFDF5E6\r
+#define COLOR_OLIVE 0x808000\r
+#define COLOR_OliveDrab 0x6B8E23\r
+#define COLOR_ORANGE 0xFFA500\r
+#define COLOR_OrangeRed 0xFF4500\r
+#define COLOR_Orchid 0xDA70D6\r
+#define COLOR_PaleGoldenRod 0xEEE8AA\r
+#define COLOR_PaleGreen 0x98FB98\r
+#define COLOR_PaleTurquoise 0xAFEEEE\r
+#define COLOR_PaleVioletRed 0xDB7093\r
+#define COLOR_PapayaWhip 0xFFEFD5\r
+#define COLOR_PeachPuff 0xFFDAB9\r
+#define COLOR_Peru 0xCD853F\r
+#define COLOR_Pink 0xFFC0CB\r
+#define COLOR_Plum 0xDDA0DD\r
+#define COLOR_PowderBlue 0xB0E0E6\r
+#define COLOR_Purple 0x800080\r
+#define COLOR_RebeccaPurple 0x663399\r
+#define COLOR_RED 0xFF0000\r
+#define COLOR_RosyBrown 0xBC8F8F\r
+#define COLOR_RoyalBlue 0x4169E1\r
+#define COLOR_SaddleBrown 0x8B4513\r
+#define COLOR_Salmon 0xFA8072\r
+#define COLOR_SandyBrown 0xF4A460\r
+#define COLOR_SeaGreen 0x2E8B57\r
+#define COLOR_SeaShell 0xFFF5EE\r
+#define COLOR_SIENNA 0xA0522D\r
+#define COLOR_SILVER 0xC0C0C0\r
+#define COLOR_SKYBLUE 0x87CEEB\r
+#define COLOR_SlateBlue 0x6A5ACD\r
+#define COLOR_SlateGray 0x708090\r
+#define COLOR_SNOW 0xFFFAFA\r
+#define COLOR_SpringGreen 0x00FF7F\r
+#define COLOR_SteelBlue 0x4682B4\r
+#define COLOR_Tan 0xD2B48C\r
+#define COLOR_Teal 0x008080\r
+#define COLOR_Thistle 0xD8BFD8\r
+#define COLOR_TOMATO 0xFF6347\r
+#define COLOR_TURQUOISE 0x40E0D0\r
+#define COLOR_VIOLET 0xEE82EE\r
+#define COLOR_Wheat 0xF5DEB3\r
+#define COLOR_WHITE 0xFFFFFF\r
+#define COLOR_WhiteSmoke 0xF5F5F5\r
+#define COLOR_YELLOW 0xFFFF00\r
+#define COLOR_YELLOWGREEN 0x9ACD32\r
+\r
+#endif /* #define COLOR_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \addtogroup lcdd_draw\r
+ *\r
+ * Implementation of draw function on LCD, Include draw text, image\r
+ * and basic shapes (line, rectangle, circle).\r
+ *\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+#include "video/lcdd.h"\r
+\r
+#include "lcd_draw.h"\r
+#include "lcd_font.h"\r
+#include "font.h"\r
+\r
+#include <string.h>\r
+#include <stdlib.h>\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variable\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Front color cache */\r
+static uint32_t front_color;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Hide canvas layer\r
+ */\r
+static void _hide_canvas(void)\r
+{\r
+ //lcdd_enable_layer(lcdd_get_canvas()->layer_id, false);\r
+}\r
+\r
+/**\r
+ * Update canvas\r
+ */\r
+static void _show_canvas(void)\r
+{\r
+ //lcdd_enable_layer(lcdd_get_canvas()->layer_id, true);\r
+}\r
+\r
+/**\r
+ * Set front color\r
+ * \param color Pixel color.\r
+ */\r
+static void _set_front_color(uint32_t color)\r
+{\r
+ front_color = color;\r
+}\r
+\r
+/**\r
+ * \brief Draw a pixel on LCD of front color.\r
+ *\r
+ * \param dwX X-coordinate of pixel.\r
+ * \param dwY Y-coordinate of pixel.\r
+ */\r
+static void _draw_pixel(uint32_t dwX, uint32_t dwY)\r
+{\r
+ struct _lcdd_layer *pDisp = lcdd_get_canvas();\r
+ uint8_t *buffer = pDisp->buffer;\r
+ uint16_t w = pDisp->width;\r
+ //uint16_t h = pDisp->height;\r
+ uint16_t cw = pDisp->bpp / 8; /* color width */\r
+ uint32_t rw = w * cw; /* row width in bytes */\r
+ //uint8_t r, g, b;\r
+ uint8_t *pPix;\r
+\r
+ if (buffer == NULL)\r
+ return;\r
+\r
+ if (rw & 0x3)\r
+ rw = (rw | 0x3) + 1; /* 4-byte aligned rows */\r
+ pPix = &buffer[dwY * rw + cw * dwX];\r
+\r
+ switch (pDisp->bpp) {\r
+ case 16: /* TRGB 1555 */\r
+ pPix[0] = (front_color) & 0xFF;\r
+ pPix[1] = (front_color >> 8) & 0xFF;\r
+ break;\r
+ case 24: /* RGB 888 */\r
+ pPix[0] = (front_color) & 0xFF;\r
+ pPix[1] = (front_color >> 8) & 0xFF;\r
+ pPix[2] = (front_color >> 16) & 0xFF;\r
+ break;\r
+ case 32: /* ARGB 8888 */\r
+ pPix[0] = (front_color) & 0xFF;\r
+ pPix[1] = (front_color >> 8) & 0xFF;\r
+ pPix[2] = (front_color >> 16) & 0xFF;\r
+ pPix[3] = (front_color >> 24) & 0xFF;\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Fill rectangle with front color.\r
+ * \param dwX1 X-coordinate of top left.\r
+ * \param dwY1 Y-coordinate of top left.\r
+ * \param dwX2 X-coordinate of bottom right.\r
+ * \param dwY1 Y-coordinate of bottom right.\r
+ */\r
+static void _fill_rect(uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2)\r
+{\r
+ struct _lcdd_layer *pDisp = lcdd_get_canvas();\r
+ uint16_t w = pDisp->width;\r
+ uint16_t cw = pDisp->bpp / 8; /* color width */\r
+ uint32_t rw = w * cw; /* row width in bytes */\r
+ uint8_t *base = pDisp->buffer;\r
+ uint8_t *buffer = pDisp->buffer;\r
+ uint32_t fillStart, fillEnd;\r
+ uint32_t i;\r
+ if (buffer == NULL)\r
+ return;\r
+\r
+ /* 4-byte aligned rows */\r
+ if (rw & 0x3)\r
+ rw = (rw | 0x3) + 1;\r
+ /* Buffer address for the starting row */\r
+ base = &buffer[dwY1 * rw];\r
+\r
+ fillStart = dwX1 * cw;\r
+ fillEnd = dwX2 * cw;\r
+\r
+#if 1 /* Memcopy pixel */\r
+ buffer = base;\r
+ for (; dwY1 <= dwY2; dwY1++) {\r
+ for (i = fillStart; i <= fillEnd; i += cw) {\r
+ memcpy(&buffer[i], &front_color, cw);\r
+ }\r
+ buffer = &buffer[rw];\r
+ }\r
+#endif\r
+\r
+#if 0 /* Pixel by pixel */\r
+ for (; dwY1 <= dwY2; dwY1++) {\r
+ for (i = dwX1; i <= dwX2; i++) {\r
+ _draw_pixel(i, dwY1);\r
+ }\r
+ }\r
+#endif\r
+\r
+#if 0 /* Optimized */\r
+ /* First row */\r
+ for (i = fillStart; i <= fillEnd; i += cw) {\r
+ memcpy(&base[i], &front_color, cw);\r
+ }\r
+ /* Next rows, copy first */\r
+ buffer = &base[rw + fillStart];\r
+ for (i = dwY1 + 1; i <= dwY2; i++) {\r
+ memcpy(buffer, &base[fillStart], fillEnd - fillStart + cw);\r
+ buffer = &buffer[rw];\r
+ }\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Draw a line on LCD, which is not horizontal or vertical.\r
+ *\r
+ * \param dwX1 X-coordinate of line start.\r
+ * \param dwY1 Y-coordinate of line start.\r
+ * \param dwX2 X-coordinate of line end.\r
+ * \param dwY2 Y-coordinate of line end.\r
+ */\r
+\r
+/*\r
+static uint32_t _draw_line_bresenham (uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2)\r
+{\r
+ int dx, dy;\r
+ int i;\r
+ int xinc, yinc, cumul;\r
+ int x, y;\r
+\r
+ x = dwX1;\r
+ y = dwY1;\r
+ dx = dwX2 - dwX1;\r
+ dy = dwY2 - dwY1;\r
+\r
+ xinc = (dx > 0) ? 1 : -1;\r
+ yinc = (dy > 0) ? 1 : -1;\r
+ dx = (dx > 0) ? dx : -dx;\r
+ dy = (dy > 0) ? dy : -dy;\r
+\r
+ _draw_pixel(x, y);\r
+\r
+ if (dx > dy) {\r
+ cumul = dx / 2;\r
+ for (i = 1; i <= dx; i++) {\r
+ x += xinc;\r
+ cumul += dy;\r
+\r
+ if (cumul >= dx) {\r
+ cumul -= dx;\r
+ y += yinc;\r
+ }\r
+ _draw_pixel(x, y);\r
+ }\r
+ } else {\r
+ cumul = dy / 2;\r
+ for (i = 1; i <= dy; i++) {\r
+ y += yinc;\r
+ cumul += dx;\r
+\r
+ if (cumul >= dy) {\r
+ cumul -= dy;\r
+ x += xinc;\r
+ }\r
+\r
+ _draw_pixel(x, y);\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+*/\r
+\r
+static uint32_t _draw_line_bresenham (uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2)\r
+{\r
+ int dx = abs(dwX2 - dwX1);\r
+ int dy = abs(dwY2 - dwY1);\r
+ int sx = (dwX1 < dwX2) ? 1 : -1;\r
+ int sy = (dwY1 < dwY2) ? 1 : -1;\r
+ int err = dx - dy;\r
+ int e2 ;\r
+\r
+ while (1) {\r
+ _draw_pixel(dwX1, dwY1);\r
+ if ((dwX1 == dwX2) && (dwY1 == dwY2))\r
+ break;\r
+ e2 = 2 * err;\r
+ if (e2 > -dy) {\r
+ err -= dy; dwX1 += sx;\r
+ }\r
+ if (e2 < dx) {\r
+ err += dx; dwY1 += sy;\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Fills the given LCD buffer with a particular color.\r
+ *\r
+ * \param color Fill color.\r
+ */\r
+void lcdd_fill(uint32_t color)\r
+{\r
+ struct _lcdd_layer *pDisp = lcdd_get_canvas();\r
+ _set_front_color(color);\r
+ _hide_canvas();\r
+ _fill_rect(0, 0, pDisp->width, pDisp->height);\r
+ _show_canvas();\r
+}\r
+\r
+void lcdd_fill_white(void)\r
+{\r
+ struct _lcdd_layer *pDisp = lcdd_get_canvas();\r
+ _hide_canvas();\r
+ _set_front_color(0x0000FF);\r
+ _fill_rect(0, 0, pDisp->width / 3, pDisp->height);\r
+ _set_front_color(0xFFFFFF);\r
+ _fill_rect(pDisp->width/3, 0, pDisp->width/3+pDisp->width/3, pDisp->height);\r
+ _set_front_color(0xFF0000);\r
+ _fill_rect(pDisp->width/3+pDisp->width/3, 0, pDisp->width-1, pDisp->height);\r
+ _show_canvas();\r
+}\r
+\r
+/**\r
+ * \brief Draw a pixel on LCD of given color.\r
+ *\r
+ * \param x X-coordinate of pixel.\r
+ * \param y Y-coordinate of pixel.\r
+ * \param color Pixel color.\r
+ */\r
+void lcdd_draw_pixel(uint32_t x, uint32_t y, uint32_t color)\r
+{\r
+ _set_front_color(color);\r
+ _hide_canvas();\r
+ _draw_pixel(x, y);\r
+ _show_canvas();\r
+}\r
+\r
+/**\r
+ * \brief Read a pixel from LCD.\r
+ *\r
+ * \param x X-coordinate of pixel.\r
+ * \param y Y-coordinate of pixel.\r
+ *\r
+ * \return color Readed pixel color.\r
+ */\r
+extern uint32_t lcdd_read_pixel(uint32_t x, uint32_t y)\r
+{\r
+ struct _lcdd_layer *pDisp = lcdd_get_canvas();\r
+ uint8_t *buffer = pDisp->buffer;\r
+ uint16_t w = pDisp->width;\r
+ //uint16_t h = pDisp->height;\r
+ uint16_t cw = pDisp->bpp / 8; /* color width */\r
+ uint32_t rw = w * cw; /* row width in bytes */\r
+ uint8_t *pPix;\r
+ uint32_t color = 0;\r
+\r
+ if (buffer == NULL)\r
+ return 0;\r
+\r
+ if (rw & 0x3)\r
+ rw = (rw | 0x3) + 1; /* 4-byte aligned rows */\r
+ pPix = &buffer[x * rw + cw * y];\r
+\r
+ switch (pDisp->bpp) {\r
+ case 16: /* TRGB 1555 */\r
+ color = pPix[0] | (pPix[1] << 8);\r
+ break;\r
+ case 24: /* RGB 888 */\r
+ color = pPix[0] | (pPix[1] << 8) | (pPix[2] << 16);\r
+ break;\r
+ case 32: /* ARGB 8888 */\r
+ color =\r
+ pPix[0] | (pPix[1] << 8) | (pPix[2] << 16) | (pPix[3] <<\r
+ 24);\r
+ break;\r
+ }\r
+ return color;\r
+}\r
+\r
+/**\r
+ * \brief Draw a line on LCD, horizontal and vertical line are supported.\r
+ *\r
+ * \param x1 X-coordinate of line start.\r
+ * \param y1 Y-coordinate of line start.\r
+ * \param x2 X-coordinate of line end.\r
+ * \param y2 Y-coordinate of line end.\r
+ * \param color Pixel color.\r
+ */\r
+void lcdd_draw_line(uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2,\r
+ uint32_t color)\r
+{\r
+ _set_front_color(color);\r
+\r
+ if ((x1 == x2) && (y1 > y2)) {\r
+ SWAP(y1, y2);\r
+ }\r
+ if ((x1 > x2) & (y1 == y2)) {\r
+ SWAP(x1, x2);\r
+ }\r
+\r
+ if ((x1 == x2) || (y1 == y2)) {\r
+ lcdd_draw_filled_rectangle(x1, y1, x2, y2, color);\r
+ } else {\r
+ _hide_canvas();\r
+ _draw_line_bresenham(x1, y1, x2, y2);\r
+ _show_canvas();\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Draws a rectangle on LCD, at the given coordinates.\r
+ *\r
+ * \param x X-coordinate of upper-left rectangle corner.\r
+ * \param y Y-coordinate of upper-left rectangle corner.\r
+ * \param width Rectangle width in pixels.\r
+ * \param height Rectangle height in pixels.\r
+ * \param color Rectangle color.\r
+ */\r
+void lcdd_draw_rectangle(uint32_t x, uint32_t y, uint32_t width, uint32_t height,\r
+ uint32_t color)\r
+{\r
+ uint32_t x1 = x + width - 1;\r
+ uint32_t y1 = y + height - 1;\r
+\r
+ _set_front_color(color);\r
+ _hide_canvas();\r
+ _fill_rect(x, y, x1, y);\r
+ _fill_rect(x1, y, x1, y1);\r
+ _fill_rect(x, y, x, y1);\r
+ _fill_rect(x, y1, x1, y1);\r
+ _show_canvas();\r
+}\r
+\r
+/**\r
+ * \brief Draws a rectangle with fill inside on LCD, at the given coordinates.\r
+ *\r
+ * \param dwX1 X-coordinate of upper-left rectangle corner.\r
+ * \param dwY1 Y-coordinate of upper-left rectangle corner.\r
+ * \param dwX2 X-coordinate of down-right rectangle corner.\r
+ * \param dwY2 Y-coordinate of down-right rectangle corner.\r
+ * \param color Rectangle color.\r
+ */\r
+void lcdd_draw_filled_rectangle(uint32_t dwX1, uint32_t dwY1,\r
+ uint32_t dwX2, uint32_t dwY2, uint32_t color)\r
+{\r
+ _set_front_color(color);\r
+ _hide_canvas();\r
+ _fill_rect(dwX1, dwY1, dwX2, dwY2);\r
+ _show_canvas();\r
+}\r
+\r
+/**\r
+ * \brief Draws a circle on LCD, at the given coordinates.\r
+ *\r
+ * \param dwX X-coordinate of circle center.\r
+ * \param dwY Y-coordinate of circle center.\r
+ * \param dwR circle radius.\r
+ * \param color circle color.\r
+ */\r
+void lcdd_draw_circle(uint32_t dwX, uint32_t dwY, uint32_t dwR, uint32_t color)\r
+{\r
+ int32_t d; /* Decision Variable */\r
+ uint32_t curX; /* Current X Value */\r
+ uint32_t curY; /* Current Y Value */\r
+\r
+ if (dwR == 0)\r
+ return;\r
+ _set_front_color(color);\r
+\r
+ d = 3 - (dwR << 1);\r
+ curX = 0;\r
+ curY = dwR;\r
+\r
+ _hide_canvas();\r
+ while (curX <= curY) {\r
+ _draw_pixel(dwX + curX, dwY + curY);\r
+ _draw_pixel(dwX + curX, dwY - curY);\r
+ _draw_pixel(dwX - curX, dwY + curY);\r
+ _draw_pixel(dwX - curX, dwY - curY);\r
+ _draw_pixel(dwX + curY, dwY + curX);\r
+ _draw_pixel(dwX + curY, dwY - curX);\r
+ _draw_pixel(dwX - curY, dwY + curX);\r
+ _draw_pixel(dwX - curY, dwY - curX);\r
+\r
+ if (d < 0) {\r
+ d += (curX << 2) + 6;\r
+ } else {\r
+ d += ((curX - curY) << 2) + 10;\r
+ curY--;\r
+ }\r
+ curX++;\r
+ }\r
+ _show_canvas();\r
+}\r
+\r
+/**\r
+ * \brief Draws a filled circle on LCD, at the given coordinates.\r
+ *\r
+ * \param dwX X-coordinate of circle center.\r
+ * \param dwY Y-coordinate of circle center.\r
+ * \param dwR circle radius.\r
+ * \param color circle color.\r
+ */\r
+void lcdd_draw_filled_circle(uint32_t dwX, uint32_t dwY, uint32_t dwR,\r
+ uint32_t color)\r
+{\r
+ signed int d; // Decision Variable\r
+ uint32_t dwCurX; // Current X Value\r
+ uint32_t dwCurY; // Current Y Value\r
+ uint32_t dwXmin, dwYmin;\r
+\r
+ if (dwR == 0)\r
+ return;\r
+ _set_front_color(color);\r
+\r
+ d = 3 - (dwR << 1);\r
+ dwCurX = 0;\r
+ dwCurY = dwR;\r
+\r
+ _hide_canvas();\r
+ while (dwCurX <= dwCurY) {\r
+ dwXmin = (dwCurX > dwX) ? 0 : dwX - dwCurX;\r
+ dwYmin = (dwCurY > dwY) ? 0 : dwY - dwCurY;\r
+ _fill_rect(dwXmin, dwYmin, dwX + dwCurX, dwYmin);\r
+ _fill_rect(dwXmin, dwY + dwCurY, dwX + dwCurX, dwY + dwCurY);\r
+ dwXmin = (dwCurY > dwX) ? 0 : dwX - dwCurY;\r
+ dwYmin = (dwCurX > dwY) ? 0 : dwY - dwCurX;\r
+ _fill_rect(dwXmin, dwYmin, dwX + dwCurY, dwYmin);\r
+ _fill_rect(dwXmin, dwY + dwCurX, dwX + dwCurY, dwY + dwCurX);\r
+\r
+ if (d < 0) {\r
+ d += (dwCurX << 2) + 6;\r
+ } else {\r
+ d += ((dwCurX - dwCurY) << 2) + 10;\r
+ dwCurY--;\r
+ }\r
+\r
+ dwCurX++;\r
+ }\r
+ _show_canvas();\r
+}\r
+\r
+/**\r
+ * \brief Draws a string inside a LCD buffer, at the given coordinates. Line breaks\r
+ * will be honored.\r
+ *\r
+ * \param x X-coordinate of string top-left corner.\r
+ * \param y Y-coordinate of string top-left corner.\r
+ * \param p_string String to display.\r
+ * \param color String color.\r
+ */\r
+void lcdd_draw_string(uint32_t x, uint32_t y, const char *p_string, uint32_t color)\r
+{\r
+ uint32_t xorg = x;\r
+ uint8_t font_sel = lcdd_get_selected_font();\r
+ uint8_t width = font_param[font_sel].width ;\r
+ uint8_t height = font_param[font_sel].height;\r
+ uint8_t char_space = font_param[font_sel].char_space;\r
+\r
+ /* Font 10*8 reverse height and width */\r
+ if (font_sel == FONT10x8) {\r
+ width = font_param[font_sel].height ;\r
+ height = font_param[font_sel].width;\r
+ }\r
+\r
+ while (*p_string) {\r
+ if (*p_string == '\n') {\r
+ y += height + char_space;\r
+ x = xorg;\r
+ } else {\r
+ lcdd_draw_char(x, y, *p_string, color);\r
+ x += width + char_space;\r
+ }\r
+ p_string++;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Draws a string inside a LCD buffer, at the given coordinates\r
+ * with given background color. Line breaks will be honored.\r
+ *\r
+ * \param x X-coordinate of string top-left corner.\r
+ * \param y Y-coordinate of string top-left corner.\r
+ * \param p_string String to display.\r
+ * \param fontColor String color.\r
+ * \param bgColor Background color.\r
+ */\r
+void lcdd_draw_string_with_bgcolor(uint32_t x, uint32_t y,\r
+ const char *p_string,\r
+ uint32_t fontColor,\r
+ uint32_t bgColor)\r
+{\r
+ uint32_t xorg = x;\r
+ uint8_t font_sel = lcdd_get_selected_font();\r
+ uint8_t width = font_param[font_sel].width ;\r
+ uint8_t height = font_param[font_sel].height;\r
+ uint8_t char_space = font_param[font_sel].char_space;\r
+\r
+ /* Font 10*8 reverse height and width */\r
+ if (font_sel == FONT10x8) {\r
+ width = font_param[font_sel].height ;\r
+ height = font_param[font_sel].width;\r
+ }\r
+\r
+ while (*p_string) {\r
+ if (*p_string == '\n') {\r
+ y += height + char_space;;\r
+ x = xorg;\r
+ } else {\r
+ lcdd_draw_char_with_bgcolor(x, y, *p_string, fontColor, bgColor);\r
+ x += width + char_space;;\r
+ }\r
+ p_string++;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Returns the width & height in pixels that a string will occupy on the screen\r
+ * if drawn using lcdd_draw_string.\r
+ *\r
+ * \param p_string String.\r
+ * \param p_width Pointer for storing the string width (optional).\r
+ * \param p_height Pointer for storing the string height (optional).\r
+ *\r
+ * \return String width in pixels.\r
+ */\r
+void lcdd_get_string_size(const char *p_string, uint32_t * p_width, uint32_t * p_height)\r
+{\r
+ uint8_t font_sel = lcdd_get_selected_font();\r
+ uint8_t width = font_param[font_sel].width;\r
+ uint8_t height = font_param[font_sel].height;\r
+ uint8_t char_space = font_param[font_sel].char_space;\r
+ uint32_t str_width = 0;\r
+\r
+ /* Font 10*8 reverse height and width */\r
+ if (font_sel == FONT10x8) {\r
+ width = font_param[font_sel].height ;\r
+ height = font_param[font_sel].width;\r
+ }\r
+\r
+ while (*p_string) {\r
+ if (*p_string == '\n')\r
+ height += height + char_space;\r
+ else\r
+ str_width += width + char_space;\r
+ p_string++;\r
+ }\r
+ if (width > 0)\r
+ str_width -= char_space;\r
+\r
+ if (p_width != NULL)\r
+ *p_width = str_width;\r
+ if (p_height != NULL)\r
+ *p_height = height;\r
+}\r
+\r
+/**\r
+ * \brief Draw a raw image at given position on LCD.\r
+ *\r
+ * \param dwX X-coordinate of image start.\r
+ * \param dwY Y-coordinate of image start.\r
+ * \param pImage Image buffer.\r
+ * \param width Image width.\r
+ * \param height Image height.\r
+ */\r
+void lcdd_draw_image(uint32_t dwX, uint32_t dwY, const uint8_t * pImage,\r
+ uint32_t width, uint32_t height)\r
+{\r
+ struct _lcdd_layer *pDisp = lcdd_get_canvas();\r
+ uint16_t cw = pDisp->bpp / 8; /* color width */\r
+ uint32_t rw = pDisp->width * cw; /* Row width in bytes */\r
+ uint32_t rws = width * cw; /* Source Row Width */\r
+ uint32_t rl = (rw & 0x3) ? ((rw | 0x3) + 1) : rw; /* Aligned length */\r
+ uint32_t rls = (rws & 0x3) ? ((rws | 0x3) + 1) : rws; /* Aligned length */\r
+ uint8_t *pSrc, *pDst;\r
+ uint32_t i;\r
+\r
+ pSrc = (uint8_t *) pImage;\r
+ pDst = pDisp->buffer;\r
+ pDst = &pDst[dwX * cw + dwY * rl];\r
+\r
+ for (i = 0; i < height; i++) {\r
+ memcpy(pDst, pSrc, rws);\r
+ pSrc = &pSrc[rls];\r
+ pDst = &pDst[rl];\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Clear a window with an color.\r
+ *\r
+ * \param dwX X-coordinate of the window.\r
+ * \param dwY Y-coordinate of the window.\r
+ * \param width window width.\r
+ * \param height window height.\r
+ * \param color background color\r
+ */\r
+void lcdd_clear_window(uint32_t dwX, uint32_t dwY, uint32_t width,\r
+ uint32_t height, uint32_t color)\r
+{\r
+ _set_front_color(color);\r
+ _hide_canvas();\r
+ _fill_rect(0, 0, dwX + width - 1, dwY + height - 1);\r
+ _show_canvas();\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Draw fast vertical line\r
+ */\r
+void lcdd_draw_fast_vline (uint32_t x, uint32_t y, uint32_t h, uint32_t color)\r
+{\r
+ lcdd_draw_line(x, y, x, y+h-1, color);\r
+}\r
+/**\r
+ * Draw fast horizontal line\r
+ */\r
+void lcdd_draw_fast_hline (uint32_t x, uint32_t y, uint32_t w, uint32_t color)\r
+{\r
+ lcdd_draw_line(x, y, x+w-1, y, color);\r
+}\r
+/**\r
+ * Fill rectangle with color\r
+ */\r
+static void _lcdd_fill_rectangle (uint32_t x, uint32_t y, uint32_t w, uint32_t h, uint32_t color)\r
+{\r
+ uint32_t i;\r
+ for (i=x; i<x+w; i++) lcdd_draw_fast_vline(i, y, h, color);\r
+}\r
+/**\r
+ * Draw a circle\r
+ */\r
+static void _lcdd_draw_circle (uint32_t x0, uint32_t y0, uint32_t r, uint8_t corner, uint32_t color)\r
+{\r
+ int32_t f = 1 - r;\r
+ int32_t ddF_x = 1;\r
+ int32_t ddF_y = -2 * (int32_t)r;\r
+ int32_t x = 0;\r
+ int32_t y = r;\r
+\r
+ while (x<y) {\r
+ if (f >= 0)\r
+ {\r
+ y--;\r
+ ddF_y += 2;\r
+ f += ddF_y;\r
+ }\r
+ x++;\r
+ ddF_x += 2;\r
+ f += ddF_x;\r
+ if (corner & 0x4) {\r
+ _draw_pixel(x0 + x, y0 + y);\r
+ _draw_pixel(x0 + y, y0 + x);\r
+ }\r
+ if (corner & 0x2) {\r
+ _draw_pixel(x0 + x, y0 - y);\r
+ _draw_pixel(x0 + y, y0 - x);\r
+ }\r
+ if (corner & 0x8) {\r
+ _draw_pixel(x0 - y, y0 + x);\r
+ _draw_pixel(x0 - x, y0 + y);\r
+ }\r
+ if (corner & 0x1) {\r
+ _draw_pixel(x0 - y, y0 - x);\r
+ _draw_pixel(x0 - x, y0 - y);\r
+ }\r
+ }\r
+}\r
+/**\r
+ * Fill a circle\r
+ */\r
+static void _lcdd_fill_circle (uint32_t x0, uint32_t y0, uint32_t r, uint8_t corner, uint32_t delta, uint32_t color)\r
+{\r
+ int32_t f = 1 - r;\r
+ int32_t ddF_x = 1;\r
+ int32_t ddF_y = -2 * (int32_t)r;\r
+ int32_t x = 0;\r
+ int32_t y = r;\r
+\r
+ while (x<y) {\r
+ if (f >= 0) {\r
+ y--;\r
+ ddF_y += 2;\r
+ f += ddF_y;\r
+ }\r
+ x++;\r
+ ddF_x += 2;\r
+ f += ddF_x;\r
+\r
+ if (corner & 0x1) {\r
+ lcdd_draw_fast_vline(x0+x, y0-y, 2*y+1+delta, color);\r
+ lcdd_draw_fast_vline(x0+y, y0-x, 2*x+1+delta, color);\r
+ }\r
+ if (corner & 0x2) {\r
+ lcdd_draw_fast_vline(x0-x, y0-y, 2*y+1+delta, color);\r
+ lcdd_draw_fast_vline(x0-y, y0-x, 2*x+1+delta, color);\r
+ }\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Draw a rectangle with rounded corners\r
+ */\r
+void lcdd_draw_rounded_rect (uint32_t x, uint32_t y, uint32_t w, uint32_t h, uint32_t r, uint32_t color)\r
+{\r
+ _set_front_color(color);\r
+ _hide_canvas();\r
+ // smarter version\r
+ lcdd_draw_fast_hline(x+r, y, w-2*r, color); // Top\r
+ lcdd_draw_fast_hline(x+r, y+h-1, w-2*r, color); // Bottom\r
+ lcdd_draw_fast_vline(x, y+r, h-2*r, color); // Left\r
+ lcdd_draw_fast_vline(x+w-1, y+r, h-2*r, color); // Right\r
+ // draw four corners\r
+ _lcdd_draw_circle(x+r, y+r, r, 1, color);\r
+ _lcdd_draw_circle(x+w-r-1, y+r, r, 2, color);\r
+ _lcdd_draw_circle(x+w-r-1, y+h-r-1, r, 4, color);\r
+ _lcdd_draw_circle(x+r, y+h-r-1, r, 8, color);\r
+ _show_canvas();\r
+}\r
+/**\r
+ * Fill a rectangle with rounded corners\r
+ */\r
+void lcdd_fill_rounded_rect(uint32_t x, uint32_t y, uint32_t w, uint32_t h, uint32_t r, uint32_t color)\r
+{\r
+ _set_front_color(color);\r
+ _hide_canvas();\r
+ if (w>(2*r)) {\r
+ _lcdd_fill_rectangle(x+r, y, w-(2*r), h, color);\r
+ // draw four corners\r
+ _lcdd_fill_circle(x+w-r-1, y+r, r, 1, h-2*r-1, color);\r
+ _lcdd_fill_circle(x+r, y+r, r, 2, h-2*r-1, color);\r
+ }\r
+ _show_canvas();\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/** \addtogroup lcdd_draw Drawing On LCD\r
+ *\r
+ * Interface for drawing function on LCD.\r
+ *\r
+ * \note Before drawing, <b>canvas</b> should be selected via\r
+ * lcdd_select_canvas(), or created by lcdd_create_canvas().\r
+ *\r
+ * Following functions can use:\r
+ * - Simple drawing:\r
+ * - lcdd_fill()\r
+ * - lcdd_draw_pixel()\r
+ * - lcdd_read_pixel()\r
+ * - lcdd_draw_line()\r
+ * - lcdd_draw_rectangle(), lcdd_draw_filled_rectangle()\r
+ * - lcdd_draw_circle(), lcdd_draw_filled_circle()\r
+ * - lcdd_draw_image()\r
+ * - String related:\r
+ * - lcdd_draw_string()\r
+ * - lcdd_get_string_size()\r
+ *\r
+ * \sa \ref lcdd_module, \ref lcdd_font\r
+ */\r
+\r
+#ifndef DRAW_H\r
+#define DRAW_H\r
+/** \addtogroup lcdd_draw\r
+ *@{\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+ /** \addtogroup lcdd_draw_func LCD Drawing Functions */\r
+/** @{*/\r
+extern void lcdd_fill_white(void);\r
+\r
+extern void lcdd_fill(uint32_t color);\r
+\r
+extern void lcdd_draw_pixel(uint32_t x, uint32_t y, uint32_t c);\r
+\r
+extern uint32_t lcdd_read_pixel(uint32_t x, uint32_t y);\r
+\r
+extern void lcdd_draw_line(uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2,\r
+ uint32_t color);\r
+\r
+extern void lcdd_draw_rectangle(uint32_t dwX, uint32_t dwY, uint32_t dwWidth,\r
+ uint32_t dwHeight, uint32_t dwColor);\r
+\r
+extern void lcdd_draw_filled_rectangle(uint32_t dwX1, uint32_t dwY1,\r
+ uint32_t dwX2, uint32_t dwY2, uint32_t dwColor);\r
+\r
+extern void lcdd_draw_circle(uint32_t x, uint32_t y, uint32_t r, uint32_t color);\r
+extern void lcdd_draw_filled_circle(uint32_t dwX, uint32_t dwY, uint32_t dwR,\r
+ uint32_t dwColor);\r
+\r
+extern void lcdd_draw_string(uint32_t x, uint32_t y, const char *pString,\r
+ uint32_t color);\r
+\r
+extern void lcdd_draw_string_with_bgcolor(uint32_t x, uint32_t y,\r
+ const char *pString, uint32_t fontColor,\r
+ uint32_t bgColor);\r
+\r
+extern void lcdd_get_string_size(const char *pString, uint32_t * pWidth,\r
+ uint32_t * pHeight);\r
+\r
+extern void lcdd_draw_image(uint32_t x, uint32_t y, const uint8_t * pImage,\r
+ uint32_t width, uint32_t height);\r
+\r
+extern void lcdd_clear_window(uint32_t dwX, uint32_t dwY, uint32_t dwWidth,\r
+ uint32_t dwHeight, uint32_t dwColor);\r
+\r
+\r
+extern void lcdd_draw_rounded_rect (uint32_t x, uint32_t y, uint32_t w, uint32_t h, uint32_t r, uint32_t color);\r
+\r
+extern void lcdd_fill_rounded_rect(uint32_t x, uint32_t y, uint32_t w, uint32_t h, uint32_t r, uint32_t color);\r
+\r
+\r
+extern void lcdd_draw_fast_vline (uint32_t x, uint32_t y, uint32_t h, uint32_t color);\r
+extern void lcdd_draw_fast_hline (uint32_t x, uint32_t y, uint32_t w, uint32_t color);\r
+\r
+/** @}*/\r
+/**@}*/\r
+#endif /* #ifndef DRAW_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file\r
+ *\r
+ * Implementation of draw font on LCD.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "lcd_font.h"\r
+#include "lcd_draw.h"\r
+\r
+#include "font.h"\r
+\r
+#include <assert.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Global variable describing the font being instanced. */\r
+//const Font gFont = { 10, 14 };\r
+\r
+static uint8_t font_sel = FONT10x14;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+struct _font_parameters* lcdd_select_font (_FONT_enum font)\r
+{\r
+ font_sel = font;\r
+ return &font_param[font];\r
+}\r
+\r
+uint8_t lcdd_get_selected_font (void)\r
+{\r
+ return font_sel;\r
+}\r
+\r
+void lcdd_draw_char(uint32_t x, uint32_t y, uint8_t c, uint32_t color)\r
+{\r
+ uint32_t row, col;\r
+ uint8_t Ch;\r
+ uint8_t width = font_param[font_sel].width ;\r
+ uint8_t height = font_param[font_sel].height;\r
+ const uint8_t* pfont = font_param[font_sel].pfont;\r
+\r
+ assert((c >= 0x20) && (c <= 0x7F));\r
+\r
+ switch (font_sel)\r
+ {\r
+ case FONT10x14:\r
+ for (col=0 ; col < width ; col++ ) {\r
+ for (row=0 ; row<8 ; row++ ) {\r
+ Ch = (pfont[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1;\r
+ if (Ch) lcdd_draw_pixel( x+col, y+row, color) ;\r
+ }\r
+ for (row=0; row<6; row++ ) {\r
+ Ch = (pfont[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1;\r
+ if (Ch) lcdd_draw_pixel( x+col, y+row+8, color) ;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case FONT10x8:\r
+ for (col=0 ; col < width ; col++ ) {\r
+ Ch = pfont[((c-0x20)*width)+ col];\r
+ if (Ch) {\r
+ for (row=0 ; row < height; row++ ) {\r
+ if ((Ch>>row)&0x1) {\r
+ lcdd_draw_pixel( x+(height-row), y+col, color) ;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ break;\r
+\r
+ case FONT8x8:\r
+ case FONT6x8:\r
+ for (col=0 ; col < width ; col++ ) {\r
+ Ch = pfont[((c-0x20)*width)+ col];\r
+ if (Ch) {\r
+ for (row=0 ; row < height; row++ ) {\r
+ if ((Ch>>row)&0x1) {\r
+ if (font_sel == FONT8x8)\r
+ lcdd_draw_pixel( x+row, y+col, color) ;\r
+ else\r
+ lcdd_draw_pixel( x+col, y+row, color) ;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Draws an ASCII character on LCD with given background color.\r
+ *\r
+ * \param x X-coordinate of character upper-left corner.\r
+ * \param y Y-coordinate of character upper-left corner.\r
+ * \param c Character to output.\r
+ * \param fontColor Character color.\r
+ * \param bgColor Background color.\r
+ */\r
+void lcdd_draw_char_with_bgcolor(uint32_t x, uint32_t y, uint8_t c, uint32_t fontColor,\r
+ uint32_t bgColor)\r
+{\r
+ uint32_t row, col;\r
+ uint8_t Ch;\r
+ uint8_t width = font_param[font_sel].width ;\r
+ uint8_t height = font_param[font_sel].height;\r
+ const uint8_t* pfont = font_param[font_sel].pfont;\r
+\r
+ assert((c >= 0x20) && (c <= 0x7F));\r
+\r
+ switch (font_sel)\r
+ {\r
+ case FONT10x14:\r
+ for (col=0 ; col < width ; col++ ) {\r
+ for (row=0 ; row<8 ; row++ ) {\r
+ Ch = (pfont[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1;\r
+ if (Ch) lcdd_draw_pixel( x+col, y+row, fontColor) ;\r
+ else lcdd_draw_pixel( x+col, y+row, bgColor) ;\r
+ }\r
+ for (row=0; row<6; row++ ) {\r
+ Ch = (pfont[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1;\r
+ if (Ch) lcdd_draw_pixel( x+col, y+row+8, fontColor) ;\r
+ else lcdd_draw_pixel( x+col, y+row+8, bgColor) ;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case FONT10x8:\r
+ for (col=0 ; col < width ; col++ ) {\r
+ Ch = pfont[((c-0x20)*width)+ col];\r
+ if (Ch) {\r
+ for (row=0 ; row < height; row++ ) {\r
+ if ((Ch>>row)&0x1) {\r
+ lcdd_draw_pixel( x+(height-row), y+col, fontColor) ;\r
+ }\r
+ else {\r
+ lcdd_draw_pixel( x+(height-row), y+col, bgColor) ;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ break;\r
+\r
+ case FONT8x8:\r
+ case FONT6x8:\r
+ for (col=0 ; col < width ; col++ ) {\r
+ Ch = pfont[((c-0x20)*width)+ col];\r
+ if (Ch) {\r
+ for (row=0 ; row < height; row++ ) {\r
+ if ((Ch>>row)&0x1) {\r
+ if (font_sel == FONT8x8)\r
+ lcdd_draw_pixel( x+row, y+col, fontColor) ;\r
+ else\r
+ lcdd_draw_pixel( x+col, y+row, fontColor) ;\r
+ }\r
+ else {\r
+ if (font_sel == FONT8x8)\r
+ lcdd_draw_pixel( x+row, y+col, bgColor) ;\r
+ else\r
+ lcdd_draw_pixel( x+col, y+row, bgColor) ;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ break;\r
+ }\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * Interface for draw font on LCD.\r
+ *\r
+ */\r
+\r
+/**\r
+ * \addtogroup lcdd_font LCD Font Drawing\r
+ *\r
+ * \section Purpose\r
+ *\r
+ * The lcd_font.h files declares a font structure and a LCDD_DrawChar() function\r
+ * that must be implemented by a font definition file to be used with the\r
+ * lcdd_draw_string() method of draw.h.\r
+ *\r
+ * The font10x14.c implements the necessary variable and function for a 10x14\r
+ * font.\r
+ *\r
+ * \note Before drawing fonts, <b>canvas</b> should be selected via\r
+ * LCDD_SelectCanvas(), or created by LCDD_CreateCanvas().\r
+ *\r
+ * \section Usage\r
+ *\r
+ * -# Declare a gFont global variable with the necessary Font information.\r
+ * -# Implement an LCDD_DrawChar() function which displays the specified\r
+ * character on the LCD.\r
+ * -# Select or create canvas via LCDD_SelectCanvas() or LCDD_CreateCanvas().\r
+ * -# Use the lcdd_draw_string() method defined in draw.h to display a complete\r
+ * string.\r
+ *\r
+ * \sa \ref lcdd_module, \ref lcdd_draw.\r
+ */\r
+\r
+#ifndef _LCD_FONT_\r
+#define _LCD_FONT_\r
+/** \addtogroup lcdd_font\r
+ *@{\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "font.h"\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** \brief Describes the font (width, height, supported characters, etc.) used by\r
+ * the LCD driver draw API.\r
+ */\r
+struct _font {\r
+ uint8_t width; /* Font width in pixels. */\r
+ uint8_t height; /* Font height in pixels. */\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+/** \addtogroup lcdd_font_func Font Functions */\r
+/** @{*/\r
+\r
+extern struct _font_parameters* lcdd_select_font (_FONT_enum font);\r
+\r
+extern uint8_t lcdd_get_selected_font (void);\r
+\r
+extern void lcdd_draw_char(uint32_t x, uint32_t y, uint8_t c, uint32_t color);\r
+\r
+extern void lcdd_draw_char_with_bgcolor(uint32_t x, uint32_t y, uint8_t c,\r
+ uint32_t fontColor, uint32_t bgColor);\r
+/** @}*/\r
+/**@}*/\r
+#endif /* #ifndef LCD_FONT_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#include "mutex.h"\r
+\r
+void mutex_lock(mutex_t* mutex)\r
+{\r
+ while(mutex_try_lock(mutex));\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef MUTEX_HEADER_\r
+#define MUTEX_HEADER_\r
+\r
+#include "compiler.h"\r
+\r
+/* Instances of mutex_t should be word-aligned (ALIGNED(4)) */\r
+typedef volatile int mutex_t;\r
+\r
+int mutex_try_lock(mutex_t* mutex);\r
+void mutex_free(mutex_t* mutex);\r
+void mutex_lock(mutex_t* mutex);\r
+int mutex_is_locked(const mutex_t* mutex);\r
+\r
+#endif /* MUTEX_HEADER_ */\r
--- /dev/null
+#define LOCKED 0x1\r
+#define FREE 0x0\r
+#define SUCCESS 0x1\r
+#define FAILURE 0x0\r
+\r
+\r
+/* try to lock mutex */\r
+ .global mutex_try_lock\r
+ .section .text.mutex_try_lock\r
+mutex_try_lock:\r
+ push {r1,r2,r3}\r
+ mov r1, #LOCKED\r
+ mov r3, #SUCCESS\r
+1:\r
+ ldrex r2, [r0]\r
+ cmp r2, r1 /* Test if mutex is locked or unlocked */\r
+ moveq r3, #FAILURE /* If locked */\r
+ beq 2f /* return failure */\r
+ strexne r2, r1, [r0] /* Not locked, attempt to lock it */\r
+ cmp r2, #LOCKED /* Check if Store-Exclusive failed */\r
+ movne r3, #FAILURE /* If failed - return failure */\r
+2:\r
+ dmb /* Required before accessing protected resource */\r
+ mov r0, r3\r
+ pop {r1,r2,r3}\r
+ bx lr\r
+\r
+\r
+/* free mutex */\r
+ .global mutex_free\r
+ .section .text.mutex_free\r
+mutex_free:\r
+ push {r1}\r
+ mov r1, #FREE\r
+ dmb /* Required before releasing protected resource */\r
+ str r1, [r0] /* Unlock mutex */\r
+ pop {r1}\r
+ bx lr\r
+\r
+/* Check if mutex is locked or not */\r
+ .global mutex_is_locked\r
+ .section .text.mutex_is_locked\r
+mutex_is_locked:\r
+ push {r1, r2}\r
+ mov r1, #LOCKED\r
+\r
+ ldrex r2, [r0]\r
+ cmp r2, r1 /* Test if mutex is locked or unlocked */\r
+ moveq r0, #SUCCESS\r
+ movne r0, #FAILURE\r
+ pop {r1, r2}\r
+ bx lr\r
--- /dev/null
+ MODULE ?mutex\r
+\r
+ //// Forward declaration of sections.\r
+ SECTION IRQ_STACK:DATA:NOROOT(2)\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+#define LOCKED 0x1\r
+#define FREE 0x0\r
+#define SUCCESS 0x1\r
+#define FAILURE 0x0\r
+\r
+/* try to lock mutex */\r
+ SECTION .mutex_try_lock:CODE:NOROOT(2)\r
+ PUBLIC mutex_try_lock\r
+mutex_try_lock:\r
+ push {r1,r2,r3}\r
+ mov r1, #LOCKED\r
+ mov r3, #SUCCESS\r
+\r
+ ldrex r2, [r0]\r
+ cmp r2, r1 /* Test if mutex is locked or unlocked */\r
+ moveq r3, #FAILURE /* If locked */\r
+ beq lbl1 /* return failure */\r
+ strexne r2, r1, [r0] /* Not locked, attempt to lock it */\r
+ cmp r2, #LOCKED /* Check if Store-Exclusive failed */\r
+ movne r3, #FAILURE /* If failed - return failure */\r
+lbl1:\r
+ dmb /* Required before accessing protected resource */\r
+ mov r0, r3\r
+ pop {r1,r2,r3}\r
+ bx lr\r
+\r
+\r
+/* free mutex */\r
+ SECTION .mutex_free:CODE:NOROOT(2)\r
+ PUBLIC mutex_free\r
+mutex_free:\r
+ push {r1}\r
+ mov r1, #FREE\r
+ dmb /* Required before releasing protected resource */\r
+ str r1, [r0] /* Unlock mutex */\r
+ pop {r1}\r
+ bx lr\r
+\r
+/* Check if mutex is locked or not */\r
+ SECTION .mutex_is_locked:CODE:NOROOT(2)\r
+ PUBLIC mutex_is_locked\r
+mutex_is_locked:\r
+ push {r1, r2}\r
+ mov r1, #LOCKED\r
+\r
+ ldrex r2, [r0]\r
+ cmp r2, r1 /* Test if mutex is locked or unlocked */\r
+ moveq r0, #SUCCESS\r
+ movne r0, #FAILURE\r
+ pop {r1, r2}\r
+ bx lr\r
+\r
+ END\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Header\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+\r
+#include "rand.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global Variables\r
+ *------------------------------------------------------------------------------*/\r
+\r
+static uint32_t _dwRandNext = 1;\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported Functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Initialize the seed for rand generator.\r
+ *\r
+ * \param dwSeed rand initiation seed\r
+ */\r
+void srand(uint32_t dwSeed)\r
+{\r
+ _dwRandNext = dwSeed;\r
+}\r
+\r
+/**\r
+ * Return a random number, maxinum assumed to be 65536\r
+ */\r
+uint32_t rand(void)\r
+{\r
+ _dwRandNext = _dwRandNext * 1103515245 + 12345;\r
+\r
+ return (uint32_t) (_dwRandNext / 131072) % 65536;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * \file\r
+ *\r
+ * \section Purpose\r
+ * Small function for gererating random number.\r
+ *\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#ifndef _RAND_\r
+#define _RAND_\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Global Functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+void srand(uint32_t dwSeed);\r
+extern uint32_t rand(void);\r
+\r
+#endif /* #ifndef _RAND_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * ATMEL Microcontroller Software Support\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef _RING_H_\r
+#define _RING_H_\r
+\r
+#include "intmath.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Exported functions\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/** Return count in buffer */\r
+#define RING_CNT(head,tail,size) fixed_mod((head) - (tail), (size))\r
+\r
+/** Return space available, 0..size-1. always leave one free char as a\r
+ * completely full buffer has head == tail, which is the same as empty */\r
+#define RING_SPACE(head,tail,size) RING_CNT((tail),((head) + 1),(size))\r
+\r
+/** Return count up to the end of the buffer. Carefully avoid accessing head\r
+ * and tail more than once, so they can change underneath us without returning\r
+ * inconsistent results */\r
+#define RING_CNT_TO_END(head,tail,size) \\r
+ ({int end = (size) - (tail); \\r
+ int n = fixed_mod((head) + end, (size)); \\r
+ n < end ? n : end;})\r
+\r
+/** Return space available up to the end of the buffer */\r
+#define RING_SPACE_TO_END(head,tail,size) \\r
+ ({int end = (size) - 1 - (head); \\r
+ int n = fixed_mod(end + (tail), (size)); \\r
+ n <= end ? n : end+1;})\r
+\r
+/** Increment head or tail */\r
+#define RING_INC(headortail,size) \\r
+ (headortail)++; \\r
+ if((headortail) >= (size)) { \\r
+ (headortail) = 0; \\r
+ }\r
+\r
+/** Decrement head or tail */\r
+#define RING_DEC(headortail,size) \\r
+ if((headortail) == 0) { \\r
+ (headortail) = (size) - 1; \\r
+ } else { \\r
+ (headortail)--; \\r
+ }\r
+\r
+/** Circular buffer is empty ? */\r
+#define RING_EMPTY(head, tail) ((head) == (tail))\r
+\r
+/** Clear circular buffer */\r
+#define RING_CLEAR(head, tail) ((head) = (tail) = 0)\r
+\r
+#endif /* _RING_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file syscalls.c\r
+ *\r
+ * Implementation of syscall bindings.\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+#include "compiler.h"\r
+#include "misc/console.h"\r
+\r
+#ifdef __GNUC__\r
+\r
+#include <stdio.h>\r
+#include <stdarg.h>\r
+#include <sys/types.h>\r
+#include <sys/stat.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Imported variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern int _heap;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/* Desactivate stream buffering */\r
+CONSTRUCTOR static void _disable_io_buffering(void)\r
+{\r
+ setvbuf(stdout, (char *)NULL, _IONBF, 0);\r
+}\r
+\r
+extern caddr_t _sbrk(int incr);\r
+caddr_t _sbrk(int incr)\r
+{\r
+ static unsigned char *heap = NULL;\r
+ unsigned char *prev_heap;\r
+\r
+ if (heap == NULL) {\r
+ heap = (unsigned char *) &_heap;\r
+ }\r
+ prev_heap = heap;\r
+\r
+ heap += incr;\r
+\r
+ return (caddr_t) prev_heap;\r
+}\r
+\r
+extern int _getpid(void);\r
+int _getpid(void)\r
+{\r
+ return -1;\r
+}\r
+\r
+extern void _kill(int pid, int sig);\r
+void _kill(int pid, int sig)\r
+{\r
+ return;\r
+}\r
+\r
+extern void _exit(int status);\r
+void _exit(int status)\r
+{\r
+ printf("Program terminated with status %d.\n", status);\r
+ while (1) ;\r
+}\r
+\r
+extern int _fstat(int file, struct stat *st);\r
+int _fstat(int file, struct stat *st)\r
+{\r
+ st->st_mode = S_IFCHR;\r
+ return 0;\r
+}\r
+\r
+extern int _lseek(int file, int ptr, int dir);\r
+int _lseek(int file, int ptr, int dir)\r
+{\r
+ return 0;\r
+}\r
+\r
+extern int _isatty(int file);\r
+int _isatty(int file)\r
+{\r
+ return 1;\r
+}\r
+\r
+extern int _read(int file, char *ptr, int len);\r
+int _read(int file, char *ptr, int len)\r
+{\r
+ return 0;\r
+}\r
+\r
+extern int _write(int file, char *ptr, int len);\r
+int _write(int file, char *ptr, int len)\r
+{\r
+ int i;\r
+\r
+ for (i = 0; i < len; i++, ptr++) {\r
+ console_put_char(*ptr);\r
+ }\r
+\r
+ return i;\r
+}\r
+\r
+extern int _close(int file);\r
+int _close(int file)\r
+{\r
+ return -1;\r
+}\r
+\r
+#elif defined __ICCARM__ /* IAR Ewarm 5.41+ */\r
+\r
+/**\r
+ * \brief Outputs a character on the DBGU.\r
+ *\r
+ * \param c Character to output.\r
+ *\r
+ * \return The character that was output.\r
+ */\r
+WEAK int putchar(int c)\r
+{\r
+ console_put_char(c);\r
+ return c;\r
+}\r
+\r
+#endif /* defined __ICCARM__ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Implement simple PIT usage as system tick.\r
+ */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "timer.h"\r
+#include "peripherals/tc.h"\r
+#include "peripherals/pit.h"\r
+#include "peripherals/aic.h"\r
+#include "peripherals/pmc.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Local variables\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Tick Counter */\r
+static volatile uint32_t _timer = 0;\r
+static uint32_t _resolution = 0;\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported Functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Handler for Sytem Tick interrupt.\r
+ */\r
+static void timer_increment(void)\r
+{\r
+ uint32_t status;\r
+\r
+ /* Read the PIT status register */\r
+ status = pit_get_status() & PIT_SR_PITS;\r
+ if (status != 0) {\r
+\r
+ /* 1 = The Periodic Interval timer has reached PIV\r
+ * since the last read of PIT_PIVR. Read the PIVR to\r
+ * acknowledge interrupt and get number of ticks\r
+ * Returns the number of occurrences of periodic\r
+ * intervals since the last read of PIT_PIVR. */\r
+ _timer += (pit_get_pivr() >> 20);\r
+ }\r
+}\r
+\r
+uint32_t timer_configure(uint32_t resolution)\r
+{\r
+ pit_disable_it();\r
+ if (!resolution)\r
+ resolution = BOARD_TIMER_RESOLUTION;\r
+ _timer = 0;\r
+ pmc_enable_peripheral(ID_PIT);\r
+ pit_init(resolution);\r
+ aic_set_source_vector(ID_PIT, timer_increment);\r
+ aic_enable(ID_PIT);\r
+ pit_enable_it();\r
+ pit_enable();\r
+ _resolution = resolution;\r
+ return 0;\r
+}\r
+\r
+uint32_t timer_get_resolution(void)\r
+{\r
+ return _resolution;\r
+}\r
+\r
+uint32_t timer_get_interval(uint32_t start, uint32_t end)\r
+{\r
+ if (end >= start)\r
+ return (end - start);\r
+ return (end + (0xFFFFFFFF - start) + 1);\r
+}\r
+\r
+void timer_start_timeout(struct _timeout* timeout, uint32_t count)\r
+{\r
+ timeout->start = _timer;\r
+ timeout->count = count;\r
+}\r
+\r
+uint8_t timer_timeout_reached(struct _timeout* timeout)\r
+{\r
+ return timer_get_interval(timeout->start, _timer) >= timeout->count;\r
+}\r
+\r
+void timer_wait(uint32_t count)\r
+{\r
+ uint32_t start, current;\r
+ start = _timer;\r
+ do {\r
+ current = _timer;\r
+ } while (timer_get_interval(start, current) < count);\r
+}\r
+\r
+void timer_sleep(uint32_t count)\r
+{\r
+ uint32_t start, current;\r
+ asm("CPSIE I");\r
+ start = _timer;\r
+\r
+ do {\r
+ asm("WFI");\r
+ current = _timer;\r
+ } while (timer_get_interval(start, current) < count);\r
+}\r
+\r
+uint32_t timer_get_tick(void)\r
+{\r
+ return _timer;\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * Methods and definitions for an internal timer.\r
+ *\r
+ * Defines a common and simpliest use of timer to generate delays using PIT\r
+ *\r
+ * \par Usage\r
+ *\r
+ * -# Configure the System Tick with timer_configure() when MCK changed\r
+ * \note\r
+ * Must be done before any invoke of timer_wait(), or timer_sleep()\r
+ * -# Uses timer_wait to actively wait according to your timer resolution.\r
+ * -# Uses timer_sleep to passively wait ccording to your timer resolution.\r
+ *\r
+ */\r
+\r
+#ifndef TIMER_HEADER_\r
+#define TIMER_HEADER_\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+\r
+struct _timeout\r
+{\r
+ uint32_t start;\r
+ uint32_t count;\r
+};\r
+/*----------------------------------------------------------------------------\r
+ * Global functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Configures the PIT & reset _timer.\r
+ * Systick interrupt handler will generates 1ms interrupt and increase a\r
+ * tickCount.\r
+ *\r
+ * \note PIT is enabled automatically in this function.\r
+ * \warning This function also set PIT handler to aic which is\r
+ * mandatory to make the timer API work\r
+ *\r
+ * \param resolution initialize PIT resolution (in nano seconds)\r
+ */\r
+extern uint32_t timer_configure(uint32_t resolution);\r
+\r
+/**\r
+ * \brief Sync wait for count times resoltion\r
+ */\r
+extern void timer_wait(uint32_t count);\r
+\r
+/**\r
+ * \brief Retrieve current timer resolution.\r
+ *\r
+ * \return Current timer resolution (0 if not already set)\r
+ */\r
+extern uint32_t timer_get_resolution(void);\r
+\r
+/**\r
+ * \brief Sync sleep for count times resolution\r
+ */\r
+extern void timer_sleep(uint32_t count);\r
+\r
+/**\r
+ * \brief Initialize a timeout\r
+ */\r
+extern void timer_start_timeout(struct _timeout* timeout, uint32_t count);\r
+\r
+/**\r
+ * \brief Tells if the timeout as been reached\r
+ */\r
+extern uint8_t timer_timeout_reached(struct _timeout* timeout);\r
+\r
+/**\r
+ * \brief Compute elapsed number of ticks between start and end with\r
+ * taking overlaps into accounts\r
+ *\r
+ * \param start Start tick point.\r
+ * \param end End tick point.\r
+ */\r
+extern uint32_t timer_get_interval(uint32_t start, uint32_t end);\r
+\r
+/**\r
+ * \brief Returns the current number of ticks\r
+ */\r
+extern uint32_t timer_get_tick(void);\r
+\r
+#endif /* TIMER_HEADER_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Headers\r
+ *------------------------------------------------------------------------------*/\r
+\r
+#include "board.h"\r
+#include "trace.h"\r
+#include "misc/console.h"\r
+#include "peripherals/pio.h"\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Internal variables\r
+ *------------------------------------------------------------------------------*/\r
+\r
+/** Current trace level */\r
+uint32_t trace_level = TRACE_LEVEL;\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * Standard output methods for reporting debug information, warnings and\r
+ * errors, which can be easily be turned on/off.\r
+ *\r
+ * \par Usage\r
+ * -# Uses the trace_debug(), trace_info(), trace_warning(), trace_error()\r
+ * trace_fatal() macros to output traces throughout the program.\r
+ * -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2\r
+ * and Fatal 1. Disable a group of traces by changing the value of\r
+ * TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL\r
+ * are not generated. To generate no trace, use the reserved value 0.\r
+ * -# Trace disabling can be dynamic. The trace level can be modified in\r
+ * runtime but messages with a level higher that TRACE_LEVEL are compiled-out\r
+ * an will not be displayed regardless of the value of trace_level.\r
+ *\r
+ * \par traceevels Trace level description\r
+ * -# trace_debug (5): Traces whose only purpose is for debugging the program,\r
+ * and which do not produce meaningful information otherwise.\r
+ * -# trace_info (4): Informational trace about the program execution. Should\r
+ * enable the user to see the execution flow.\r
+ * -# trace_warning (3): Indicates that a minor error has happened. In most case\r
+ * it can be discarded safely; it may even be expected.\r
+ * -# trace_error (2): Indicates an error which may not stop the program execution,\r
+ * but which indicates there is a problem with the code.\r
+ * -# trace_fatal (1): Indicates a major error which prevents the program from going\r
+ * any further. Program will stop after the fatal trace message is displayed.\r
+ */\r
+\r
+#ifndef _TRACE_H_\r
+#define _TRACE_H_\r
+\r
+/* ------------------------------------------------------------------------------\r
+ * Headers\r
+ * ----------------------------------------------------------------------------*/\r
+\r
+#include "compiler.h"\r
+#include <stdio.h>\r
+#include <stdint.h>\r
+\r
+/* ------------------------------------------------------------------------------\r
+ * Exported Definitions\r
+ * ----------------------------------------------------------------------------*/\r
+\r
+#define TRACE_LEVEL_DEBUG 5\r
+#define TRACE_LEVEL_INFO 4\r
+#define TRACE_LEVEL_WARNING 3\r
+#define TRACE_LEVEL_ERROR 2\r
+#define TRACE_LEVEL_FATAL 1\r
+#define TRACE_LEVEL_SILENT 0\r
+\r
+/* By default, all traces are output except the debug one. */\r
+#ifndef TRACE_LEVEL\r
+#define TRACE_LEVEL TRACE_LEVEL_INFO\r
+#endif\r
+\r
+/* ------------------------------------------------------------------------------\r
+ * Exported variables\r
+ * ----------------------------------------------------------------------------*/\r
+\r
+/** Trace level is modifable at runtime */\r
+extern uint32_t trace_level;\r
+\r
+/* ------------------------------------------------------------------------------\r
+ * Exported functions\r
+ * ----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * Outputs a formatted string using 'printf' if the log level is high\r
+ * enough. Can be disabled by defining TRACE_LEVEL=0 during compilation.\r
+ * \param ... Additional parameters depending on formatted string.\r
+ */\r
+\r
+#if (TRACE_LEVEL >= 1)\r
+#define trace_fatal(...) \\r
+ { if (trace_level >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } }\r
+#define trace_fatal_wp(...) \\r
+ { if (trace_level >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } }\r
+#else\r
+#define trace_fatal(...) \\r
+ { while (1); }\r
+#define trace_fatal_wp(...) \\r
+ { while (1); }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= 2)\r
+#define trace_error(...) \\r
+ { if (trace_level >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } }\r
+#define trace_error_wp(...) \\r
+ { if (trace_level >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } }\r
+#else\r
+#define trace_error(...) { }\r
+#define trace_error_wp(...) { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= 3)\r
+#define trace_warning(...) \\r
+ { if (trace_level >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } }\r
+#define trace_warning_wp(...) \\r
+ { if (trace_level >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } }\r
+#else\r
+#define trace_warning(...) { }\r
+#define trace_warning_wp(...) { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= 4)\r
+#define trace_info(...) \\r
+ { if (trace_level >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } }\r
+#define trace_info_wp(...) \\r
+ { if (trace_level >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } }\r
+#else\r
+#define trace_info(...) { }\r
+#define trace_info_wp(...) { }\r
+#endif\r
+\r
+#if (TRACE_LEVEL >= 5)\r
+#define trace_debug(...) \\r
+ { if (trace_level >= TRACE_LEVEL_DEBUG) { printf("-D- " __FILE__ ":" STRINGIFY(__LINE__) " " __VA_ARGS__); } }\r
+#define trace_debug_wp(...) \\r
+ { if (trace_level >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } }\r
+#else\r
+#define trace_debug(...) { }\r
+#define trace_debug_wp(...) { }\r
+#endif\r
+\r
+#endif /* _TRACE_H_ */\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/** \file */\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdio.h>\r
+\r
+#include "wav.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Definitions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** WAV letters "RIFF" */\r
+#define WAV_CHUNKID 0x46464952\r
+\r
+/** WAV letters "WAVE"*/\r
+#define WAV_FORMAT 0x45564157\r
+\r
+/** WAV letters "fmt "*/\r
+#define WAV_SUBCHUNKID 0x20746D66\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * \brief Check if the header of a Wav file is valid or not.\r
+ *\r
+ * \param header Wav header information.\r
+ * \return true if the header of a Wav file is valid; otherwise returns false.\r
+ */\r
+bool wav_is_valid(const struct _wav_header *header)\r
+{\r
+ return (header->chunk_id == WAV_CHUNKID\r
+ && header->format == WAV_FORMAT\r
+ && header->subchunk1_size == 0x10);\r
+}\r
+\r
+/**\r
+ * \brief Display the information of the WAV file (sample rate, stereo/mono\r
+ * and frame size).\r
+ *\r
+ * \param header Wav header information.\r
+ */\r
+\r
+void wav_display_info(const struct _wav_header *header)\r
+{\r
+ printf("Wave file header information\n\r");\r
+ printf("--------------------------------\n\r");\r
+ printf(" - Chunk ID = 0x%08X\n\r",\r
+ (unsigned int)header->chunk_id);\r
+ printf(" - Chunk Size = %u\n\r",\r
+ (unsigned int)header->chunk_size);\r
+ printf(" - Format = 0x%08X\n\r",\r
+ (unsigned int)header->format);\r
+ printf(" - SubChunk ID = 0x%08X\n\r",\r
+ (unsigned int)header->subchunk1_id);\r
+ printf(" - Subchunk1 Size = %u\n\r",\r
+ (unsigned int)header->subchunk1_size);\r
+ printf(" - Audio Format = 0x%04X\n\r",\r
+ (unsigned int)header->audio_format);\r
+ printf(" - Num. Channels = %d\n\r",\r
+ (unsigned int)header->num_channels);\r
+ printf(" - Sample Rate = %u\n\r",\r
+ (unsigned int)header->sample_rate);\r
+ printf(" - Byte Rate = %u\n\r",\r
+ (unsigned int)header->byte_rate);\r
+ printf(" - Block Align = %d\n\r",\r
+ (unsigned int)header->block_align);\r
+ printf(" - Bits Per Sample = %d\n\r",\r
+ (unsigned int)header->bits_per_sample);\r
+ printf(" - Subchunk2 ID = 0x%08X\n\r",\r
+ (unsigned int)header->subchunk2_id);\r
+ printf(" - Subchunk2 Size = %u\n\r",\r
+ (unsigned int)header->subchunk2_size);\r
+}\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2015, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef WAV_H\r
+#define WAV_H\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Headers\r
+ *----------------------------------------------------------------------------*/\r
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Types\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/** Standard WAV file header information. */\r
+struct _wav_header {\r
+ /** Contains the letters "RIFF" in ASCII form. */\r
+ uint32_t chunk_id;\r
+ /** Size of the rest of the chunk following this number. */\r
+ uint32_t chunk_size;\r
+ /** Contains the letters "WAVE". */\r
+ uint32_t format;\r
+ /** Contains the letters "fmt ". */\r
+ uint32_t subchunk1_id;\r
+ /** 16 for PCM. This is the size of the rest of the Subchunk which follows this number. */\r
+ uint32_t subchunk1_size;\r
+ /** PCM = 1 (i.e. Linear quantization). Values other than 1 indicate some form of compression. */\r
+ uint16_t audio_format;\r
+ /** Mono = 1, Stereo = 2, etc. */\r
+ uint16_t num_channels;\r
+ /** 8000, 44100, etc. */\r
+ uint32_t sample_rate;\r
+ /** SampleRate * NumChannels * BitsPerSample/8 */\r
+ uint32_t byte_rate;\r
+ /** NumChannels * BitsPerSample/8 */\r
+ uint16_t block_align;\r
+ /** 8 bits = 8, 16 bits = 16, etc. */\r
+ uint16_t bits_per_sample;\r
+ /** Contains the letters "data". */\r
+ uint32_t subchunk2_id;\r
+ /** Number of bytes in the data. */\r
+ uint32_t subchunk2_size;\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+ * Exported functions\r
+ *----------------------------------------------------------------------------*/\r
+\r
+extern bool wav_is_valid(const struct _wav_header *header);\r
+\r
+extern void wav_display_info(const struct _wav_header *header);\r
+\r
+#endif /* #ifndef WAV_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configCPU_CLOCK_HZ /* Not used in this port as the value comes from the Atmel libraries. */\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#define configUSE_TICKLESS_IDLE 0\r
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 1\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 42 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xEventGroupSetBitsFromISR 1\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+format the raw data provided by the uxTaskGetSystemState() function in to human\r
+readable ASCII form. See the notes in the implementation of vTaskList() within\r
+FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
+\r
+/* Cortex-A specific setting: FPU has 16 (rather than 32) d registers. See:\r
+http://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-proprietary-interrupt-controller.html */\r
+#define configFPU_D32 0\r
+\r
+/* Cortex-A specific setting for Atmel SAMA5D2x. */\r
+#define configAIC_BASE_ADDRESS ( 0xFC020000UL )\r
+#define configPIT_BASE_ADDRESS ( 0xF8048030UL )\r
+\r
+/* Cortex-A specific setting: The address of the register within the interrupt\r
+controller from which the address of the current interrupt's handling function\r
+can be obtained. See:\r
+http://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-proprietary-interrupt-controller.html */\r
+#define configINTERRUPT_VECTOR_ADDRESS ( configAIC_BASE_ADDRESS + 0x10UL )\r
+\r
+/* Cortex-A specific setting: The address of End of Interrupt register within\r
+the interrupt controller. See:\r
+http://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-proprietary-interrupt-controller.html */\r
+#define configEOI_ADDRESS ( configAIC_BASE_ADDRESS + 0x38UL )\r
+\r
+/* Cortex-A specific setting: configCLEAR_TICK_INTERRUPT() is a macro that is\r
+called by the RTOS kernel's tick handler to clear the source of the tick\r
+interrupt. See:\r
+http://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-proprietary-interrupt-controller.html */\r
+#define configPIT_PIVR ( *( ( volatile uint32_t * ) ( configPIT_BASE_ADDRESS + 0x8UL ) ) )\r
+#define configCLEAR_TICK_INTERRUPT() ( void ) configPIT_PIVR /* Read PIT_PIVR to clear interrupt. */\r
+\r
+/* Prevent C code being included in assembly files when the IAR compiler is\r
+used. */\r
+#ifndef __IASMARM__\r
+\r
+ /* The interrupt nesting test creates a 20KHz timer. For convenience the\r
+ 20KHz timer is also used to generate the run time stats time base, removing\r
+ the need to use a separate timer for that purpose. The 20KHz timer\r
+ increments ulHighFrequencyTimerCounts, which is used as the time base.\r
+ Therefore the following macro is not implemented. */\r
+ #define configGENERATE_RUN_TIME_STATS 1\r
+ extern volatile uint32_t ulHighFrequencyTimerCounts;\r
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+ #define portGET_RUN_TIME_COUNTER_VALUE() ulHighFrequencyTimerCounts\r
+\r
+ /* The size of the global output buffer that is available for use when there\r
+ are multiple command interpreters running at once (for example, one on a UART\r
+ and one on TCP/IP). This is done to prevent an output buffer being defined by\r
+ each implementation - which would waste RAM. In this case, there is only one\r
+ command interpreter running. */\r
+ #define configCOMMAND_INT_MAX_OUTPUT_SIZE 3000\r
+\r
+ /* Normal assert() semantics without relying on the provision of an assert.h\r
+ header file. */\r
+ void vAssertCalled( const char * pcFile, unsigned long ulLine );\r
+ #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ );\r
+\r
+\r
+\r
+ /****** Hardware specific settings. *******************************************/\r
+\r
+ /*\r
+ * The application must provide a function that configures a peripheral to\r
+ * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()\r
+ * in FreeRTOSConfig.h to call the function. FreeRTOS_Tick_Handler() must\r
+ * be installed as the peripheral's interrupt handler.\r
+ */\r
+ void vConfigureTickInterrupt( void );\r
+ #define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()\r
+\r
+#endif /* __IASMARM__ */\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Library includes. */\r
+#include "peripherals/aic.h"\r
+#include "peripherals/pio.h"\r
+#include "peripherals/pit.h"\r
+#include "board.h"\r
+\r
+/*\r
+ * The FreeRTOS tick handler. This function must be installed as the handler\r
+ * for the timer used to generate the tick interrupt. Note that the interrupt\r
+ * generated by the PIT is shared by other system peripherals, so if the PIT is\r
+ * used for Tick generation then FreeRTOS_Tick_Handler() can only be installed\r
+ * directly as the PIT handler if no other system interrupts need to be\r
+ * serviced. If system interrupts other than the PIT need to be serviced then\r
+ * install System_Handler() as the PIT interrupt handler in place of\r
+ * FreeRTOS_Tick_Handler() and add additional interrupt processing into the\r
+ * implementation of System_Handler().\r
+ */\r
+extern void FreeRTOS_Tick_Handler( void );\r
+static void System_Handler( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static void System_Handler( void )\r
+{\r
+ /* See the comments above the function prototype in this file. */\r
+ FreeRTOS_Tick_Handler();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The application must provide a function that configures a peripheral to\r
+ * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()\r
+ * in FreeRTOSConfig.h to call the function. This file contains a function\r
+ * that is suitable for use on the Atmel SAMA5.\r
+ */\r
+void vConfigureTickInterrupt( void )\r
+{\r
+ /* NOTE: The PIT interrupt is cleared by the configCLEAR_TICK_INTERRUPT()\r
+ macro in FreeRTOSConfig.h. */\r
+\r
+ /* Enable the PIT clock. */\r
+ PMC->PMC_PCER0 = 1 << ID_PIT;\r
+\r
+ /* Initialize the PIT to the desired frequency - specified in uS. */\r
+ pit_init( 1000000UL / configTICK_RATE_HZ );\r
+\r
+ /* Configure interrupt on PIT. Note this is on the system interrupt, which\r
+ is shared with other system peripherals, so System_Handler() must be\r
+ installed in place of FreeRTOS_Tick_Handler() if other system handlers are\r
+ required. The tick must be given the lowest priority (0 in the SAMA5 AIC) */\r
+ aic_configure( ID_PIT, AIC_SMR_SRCTYPE_EXT_POSITIVE_EDGE );\r
+ aic_set_source_vector( ID_PIT, FreeRTOS_Tick_Handler );\r
+ /* See commend directly above IRQ_ConfigureIT( ID_PIT, 0, System_Handler ); */\r
+ aic_enable( ID_PIT );\r
+ pit_enable_it();\r
+\r
+ /* Enable the pit. */\r
+ pit_enable();\r
+\r
+ /* Prevent compiler warnings in the case where System_Handler() is not used\r
+ as the handler. See the comments above the System_Handler() function\r
+ prototype at the top of this file. */\r
+ ( void ) System_Handler;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * This file initialises three timers as follows:\r
+ *\r
+ * TC0 channels 0 and 1 provide the interrupts that are used with the IntQ\r
+ * standard demo tasks, which test interrupt nesting and using queues from\r
+ * interrupts. As the interrupt is shared the nesting achieved is not as deep\r
+ * as normal when this test is executed, but still worth while.\r
+ *\r
+ * TC2 channel 0 provides a much higher frequency timer that tests the nesting\r
+ * of interrupts that don't use the FreeRTOS API. For convenience, the high\r
+ * frequency timer also keeps a count of the number of time it executes, and the\r
+ * count is used as the time base for the run time stats (which can be viewed\r
+ * through the CLI).\r
+ *\r
+ * All the timers can nest with the tick interrupt - creating a maximum\r
+ * interrupt nesting depth of 3 (normally 4, if the first two timers used\r
+ * separate interrupts).\r
+ *\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/* Library includes. */\r
+#include "peripherals/pio.h"\r
+#include "peripherals/pmc.h"\r
+#include "peripherals/aic.h"\r
+#include "peripherals/tc.h"\r
+#include "board.h"\r
+\r
+/* The frequencies at which the first two timers expire are slightly offset to\r
+ensure they don't remain synchronised. The frequency of the highest priority\r
+interrupt is 20 times faster so really hammers the interrupt entry and exit\r
+code. */\r
+#define tmrTIMER_0_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_1_FREQUENCY ( 1690UL )\r
+#define tmrTIMER_2_FREQUENCY ( 20000UL )\r
+\r
+/* The channels used in TC0 for generating the three interrupts. */\r
+#define tmrTC0_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */\r
+#define tmrTC0_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */\r
+#define tmrTC1_CHANNEL_0 0 /* At tmrTIMER_2_FREQUENCY */\r
+\r
+/* The bit within the RC_SR register that indicates an RC compare. */\r
+#define tmrRC_COMPARE ( 1UL << 4UL )\r
+\r
+/* The high frequency interrupt given the highest priority or all. The priority\r
+of the lower frequency timers must still be above the tick interrupt priority. */\r
+#define tmrLOWER_PRIORITY 1\r
+#define tmrHIGHER_PRIORITY 5\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Handlers for the two timer peripherals - two channels are used in the TC0\r
+timer. */\r
+static void prvTC0_Handler( void );\r
+static void prvTC1_Handler( void );\r
+\r
+/* Used to provide a means of ensuring the intended interrupt nesting depth is\r
+actually being reached. */\r
+extern uint32_t ulPortInterruptNesting;\r
+static uint32_t ulMaxRecordedNesting = 0;\r
+\r
+/* For convenience the high frequency timer increments a variable that is then\r
+used as the time base for the run time stats. */\r
+volatile uint32_t ulHighFrequencyTimerCounts = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+ /* Enable the TC clocks. */\r
+ pmc_enable_peripheral( ID_TC0 );\r
+ pmc_enable_peripheral( ID_TC1 );\r
+\r
+ /* Configure TC0 channel 0 for a tmrTIMER_0_FREQUENCY frequency and trigger\r
+ on RC compare. */\r
+ tc_trigger_on_freq( TC0, tmrTC0_CHANNEL_0, tmrTIMER_0_FREQUENCY );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Configure TC0 channel 1 for a tmrTIMER_1_FREQUENCY frequency and trigger\r
+ on RC compare. */\r
+ tc_trigger_on_freq( TC0, tmrTC0_CHANNEL_1, tmrTIMER_1_FREQUENCY );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Configure TC1 channel 0 tmrTIMER_2_FREQUENCY frequency and trigger on\r
+ RC compare. */\r
+ tc_trigger_on_freq( TC1, tmrTC0_CHANNEL_0, tmrTIMER_2_FREQUENCY );\r
+ TC1->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Enable interrupts and start the timers. */\r
+ aic_configure( ID_TC0, tmrLOWER_PRIORITY );\r
+ aic_set_source_vector( ID_TC0, prvTC0_Handler );\r
+ aic_configure( ID_TC1, tmrHIGHER_PRIORITY );\r
+ aic_set_source_vector( ID_TC1, prvTC1_Handler );\r
+ aic_enable( ID_TC0 );\r
+ aic_enable( ID_TC1 );\r
+ tc_start( TC0, tmrTC0_CHANNEL_0 );\r
+ tc_start( TC0, tmrTC0_CHANNEL_1 );\r
+ tc_start( TC1, tmrTC1_CHANNEL_0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTC0_Handler( void )\r
+{\r
+ /* Read will clear the status bit. */\r
+ if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_SR & tmrRC_COMPARE ) != 0 )\r
+ {\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+ }\r
+\r
+ if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_SR & tmrRC_COMPARE ) != 0 )\r
+ {\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTC1_Handler( void )\r
+{\r
+volatile uint32_t ulDummy;\r
+\r
+ /* Dummy read to clear status bit. */\r
+ ulDummy = TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_SR;\r
+\r
+ /* Latch the maximum nesting count. */\r
+ if( ulPortInterruptNesting > ulMaxRecordedNesting )\r
+ {\r
+ ulMaxRecordedNesting = ulPortInterruptNesting;\r
+ }\r
+\r
+ /* Keep a count of the number of interrupts to use as a time base for the\r
+ run-time stats. */\r
+ ulHighFrequencyTimerCounts++;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+BaseType_t xTimer0Handler( void );\r
+BaseType_t xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ *\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and software timers, then\r
+ * starts the scheduler. The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" task - The check task period is initially set to three seconds. The\r
+ * task checks that all the standard demo tasks, and the register check tasks,\r
+ * are not only still executing, but are executing without reporting any errors.\r
+ * If the check task discovers that a task has either stalled, or reported an\r
+ * error, then it changes its own execution period from the initial three\r
+ * seconds, to just 200ms. The check task also toggles an LED each time it is\r
+ * called. This provides a visual indication of the system status: If the LED\r
+ * toggles every three seconds, then no issues have been discovered. If the LED\r
+ * toggles every 200ms, then an issue has been discovered with at least one\r
+ * task. The LED used is defined in mainCHECK_LED, below.\r
+ *\r
+ * NOTE on LEDS:\r
+ *\r
+ * This demo is NOT configured to use the LED built onto the SAMA6D2\r
+ * XPLained board!\r
+ *\r
+ * The LED driver PIN_LED definitions have been altered in\r
+ * board_sama5d2-xplained.h to remap them to GPIOs terminating on pins 30,\r
+ * 32 and 34 of J17. (This change is conditional on the preprocessor\r
+ * #define "LEDS_ON_J17".) These GPIOs are configured to be "high drive"\r
+ * push-pull outputs; they can source up to 18mA at 1.8v. Low\r
+ * forward-voltage LEDs may be connected via 100 ohm resistors to pins\r
+ * 30, 32 and 34 with their cathodes to pin 35/36 (GND).\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "flop.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+#include "serial.h"\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "IntQueue.h"\r
+#include "EventGroupsDemo.h"\r
+#include "flash.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainLED_FLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCDC_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2UL )\r
+#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The initial priority used by the UART command console task. */\r
+#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
+\r
+/* The LED used by the check task. */\r
+#define mainCHECK_LED ( 2 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period of the check task, in ms, provided no errors have been reported by\r
+any of the standard demo tasks. ms are converted to the equivalent in ticks\r
+using the pdMS_TO_TICKS() macro constant. */\r
+#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL )\r
+\r
+/* The period of the check task, in ms, if an error has been reported in one of\r
+the standard demo tasks. ms are converted to the equivalent in ticks using the\r
+pdMS_TO_TICKS() macro. */\r
+#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL )\r
+\r
+/* Parameters that are passed into the register check tasks solely for the\r
+purpose of ensuring parameters are passed into tasks correctly. */\r
+#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )\r
+#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )\r
+\r
+/* The base period used by the timer test tasks. */\r
+#define mainTIMER_TEST_PERIOD ( 50 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main() to run the full demo (as opposed to the blinky demo) when\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+void main_full( void );\r
+\r
+/*\r
+ * The check task, as described at the top of this file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the FPU registers, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly file, but the\r
+ * entry points are kept in the C file for the convenience of checking the task\r
+ * parameter.\r
+ */\r
+static void prvRegTestTaskEntry1( void *pvParameters );\r
+extern void vRegTest1Implementation( void );\r
+static void prvRegTestTaskEntry2( void *pvParameters );\r
+extern void vRegTest2Implementation( void );\r
+\r
+/*\r
+ * A high priority task that does nothing other than execute at a pseudo random\r
+ * time to ensure the other test tasks don't just execute in a repeating\r
+ * pattern.\r
+ */\r
+static void prvPseudoRandomiser( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check task. If the variables keep incrementing,\r
+then the register check tasks have not discovered any errors. If a variable\r
+stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* Start all the other standard demo/test tasks. They have no particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartInterruptQueueTasks();\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+ vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );\r
+ vStartEventGroupTasks();\r
+\r
+ /* Create the register check tasks, as described at the top of this file */\r
+ xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the task that just adds a little random behaviour. */\r
+ xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
+\r
+ /* Create the task that performs the 'check' functionality, as described at\r
+ the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* The set of tasks created by the following function call have to be\r
+ created last as they keep account of the number of tasks they expect to see\r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
+TickType_t xLastExecutionTime;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. The onboard LED is toggled on each iteration.\r
+ If an error is detected then the delay period is decreased from\r
+ mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
+ effect of increasing the rate at which the onboard LED toggles, and in so\r
+ doing gives visual feedback of the system status. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+ if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xIsQueueOverwriteTaskStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreEventGroupTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash the LED\r
+ at a higher frequency to give visible feedback that something has\r
+ gone wrong (it might just be that the loop back connector required\r
+ by the comtest tasks has not been fitted). */\r
+ xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTestTaskEntry1( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )\r
+ {\r
+ /* The reg test task also tests the floating point registers. Tasks\r
+ that use the floating point unit must call vPortTaskUsesFPU() before\r
+ any floating point instructions are executed. */\r
+ vPortTaskUsesFPU();\r
+\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest1Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check task will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTestTaskEntry2( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )\r
+ {\r
+ /* The reg test task also tests the floating point registers. Tasks\r
+ that use the floating point unit must call vPortTaskUsesFPU() before\r
+ any floating point instructions are executed. */\r
+ vPortTaskUsesFPU();\r
+\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest2Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check task will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPseudoRandomiser( void *pvParameters )\r
+{\r
+const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ), ulIBit = ( 1UL << 7UL );\r
+volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;\r
+\r
+ /* A few minor port tests before entering the randomiser loop.\r
+\r
+ At this point interrupts should be enabled. */\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == 0 );\r
+\r
+ /* The CPU does not have an interrupt mask register, so critical sections\r
+ have to globally disable interrupts. Therefore entering a critical section\r
+ should leave the I bit set. */\r
+ taskENTER_CRITICAL();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+\r
+ /* Nest the critical sections. */\r
+ taskENTER_CRITICAL();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+\r
+ /* After yielding the I bit should still be set. Note yielding is possible\r
+ in a critical section as each task maintains its own critical section\r
+ nesting count so some tasks are in critical sections and others are not -\r
+ however this is *not* something task code should do! */\r
+ taskYIELD();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+\r
+ /* The I bit should not be cleared again until both critical sections have\r
+ been exited. */\r
+ taskEXIT_CRITICAL();\r
+ taskYIELD();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == ulIBit );\r
+ taskEXIT_CRITICAL();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == 0 );\r
+ taskYIELD();\r
+ configASSERT( ( __get_CPSR() & ulIBit ) == 0 );\r
+\r
+ /* This task does nothing other than ensure there is a little bit of\r
+ disruption in the scheduling pattern of the other tasks. Normally this is\r
+ done by generating interrupts at pseudo random times. */\r
+ for( ;; )\r
+ {\r
+ ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;\r
+ ulValue = ( ulNextRand >> 16UL ) & 0xffUL;\r
+\r
+ if( ulValue < ulMinDelay )\r
+ {\r
+ ulValue = ulMinDelay;\r
+ }\r
+\r
+ vTaskDelay( ulValue );\r
+\r
+ while( ulValue > 0 )\r
+ {\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+\r
+ ulValue--;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+;/*\r
+; FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+;\r
+; FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+; http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * FreeRTOS tutorial books are available in pdf and paperback. *\r
+; * Complete, revised, and edited pdf reference manuals are also *\r
+; * available. *\r
+; * *\r
+; * Purchasing FreeRTOS documentation will not only help you, by *\r
+; * ensuring you get running as quickly as possible and with an *\r
+; * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+; * the FreeRTOS project to continue with its mission of providing *\r
+; * professional grade, cross platform, de facto standard solutions *\r
+; * for microcontrollers - completely free of charge! *\r
+; * *\r
+; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+; * *\r
+; * Thank you for using FreeRTOS, and thank you for your support! *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify it under\r
+; the terms of the GNU General Public License (version 2) as published by the\r
+; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+;\r
+; >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
+; distribute a combined work that includes FreeRTOS without being obliged to\r
+; provide the source code for proprietary components outside of the FreeRTOS\r
+; kernel.\r
+;\r
+; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+; FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
+; details. You should have received a copy of the GNU General Public License\r
+; and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
+; viewed here: http://www.freertos.org/a00114.html and also obtained by\r
+; writing to Real Time Engineers Ltd., contact details for whom are available\r
+; on the FreeRTOS WEB site.\r
+;\r
+; 1 tab == 4 spaces!\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * Having a problem? Start by reading the FAQ "My application does *\r
+; * not run, what could be wrong?" *\r
+; * *\r
+; * http://www.FreeRTOS.org/FAQHelp.html *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+;\r
+; http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+; license and Real Time Engineers Ltd. contact details.\r
+;\r
+; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+; including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
+; fully thread aware and reentrant UDP/IP stack.\r
+;\r
+; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+; Integrity Systems, who sell the code with commercial support,\r
+; indemnification and middleware, under the OpenRTOS brand.\r
+;\r
+; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+; engineered and independently SIL3 certified version for use in safety and\r
+; mission critical applications that require provable dependability.\r
+;*/\r
+\r
+ EXPORT vRegTest1Implementation\r
+ EXPORT vRegTest2Implementation\r
+\r
+ ; This file is built with IAR and ARM compilers. When the ARM compiler\r
+ ; is used the compiler options must define __IASMARM__ as 0 using the\r
+ ; --predefine "__IASMARM__ SETA 0" command line option. When compiling\r
+ ; with IAR __IASMARM__ is automatically set to 1 so no additional assembler\r
+ ; options are required.\r
+ SECTION .text:CODE:ROOT(2)\r
+ ARM\r
+\r
+ ; This function is explained in the comments at the top of main-full.c.\r
+vRegTest1Implementation\r
+\r
+ PRESERVE8\r
+ IMPORT ulRegTest1LoopCounter\r
+\r
+ ; Fill each general purpose register with a known value.\r
+ mov r0, #0xFF\r
+ mov r1, #0x11\r
+ mov r2, #0x22\r
+ mov r3, #0x33\r
+ mov r4, #0x44\r
+ mov r5, #0x55\r
+ mov r6, #0x66\r
+ mov r7, #0x77\r
+ mov r8, #0x88\r
+ mov r9, #0x99\r
+ mov r10, #0xAA\r
+ mov r11, #0xBB\r
+ mov r12, #0xCC\r
+ mov r14, #0xEE\r
+\r
+ ; Fill each FPU register with a known value.\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+ ; Loop, checking each iteration that each register still contains the\r
+ ; expected value.\r
+reg1_loop\r
+ ; Yield to increase test coverage\r
+ svc 0\r
+\r
+ ; Check all the VFP registers still contain the values set above.\r
+ ; First save registers that are clobbered by the test.\r
+ push { r0-r1 }\r
+\r
+ vmov r0, r1, d0\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x11\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #0x22\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x33\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #0x44\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x55\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #0x66\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x77\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #0x88\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x99\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #0xAA\r
+ bne reg1_error_loopf\r
+ cmp r1, #0xBB\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x11\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #0x22\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x33\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #0x44\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x55\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #0x66\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x77\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #0x88\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x99\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #0xAA\r
+ bne reg1_error_loopf\r
+ cmp r1, #0xBB\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x11\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #0x22\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x33\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #0x44\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x55\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #0x66\r
+ bne reg1_error_loopf\r
+ cmp r1, #0x77\r
+ bne reg1_error_loopf\r
+\r
+ ; Restore the registers that were clobbered by the test.\r
+ pop {r0-r1}\r
+\r
+ ; VFP register test passed. Jump to the core register test.\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ ; If this line is hit then a VFP register value was found to be\r
+ ; incorrect.\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ ; Test each general purpose register to check that it still contains the\r
+ ; expected known value, jumping to reg1_error_loop if any register contains\r
+ ; an unexpected value.\r
+ cmp r0, #0xFF\r
+ bne reg1_error_loop\r
+ cmp r1, #0x11\r
+ bne reg1_error_loop\r
+ cmp r2, #0x22\r
+ bne reg1_error_loop\r
+ cmp r3, #0x33\r
+ bne reg1_error_loop\r
+ cmp r4, #0x44\r
+ bne reg1_error_loop\r
+ cmp r5, #0x55\r
+ bne reg1_error_loop\r
+ cmp r6, #0x66\r
+ bne reg1_error_loop\r
+ cmp r7, #0x77\r
+ bne reg1_error_loop\r
+ cmp r8, #0x88\r
+ bne reg1_error_loop\r
+ cmp r9, #0x99\r
+ bne reg1_error_loop\r
+ cmp r10, #0xAA\r
+ bne reg1_error_loop\r
+ cmp r11, #0xBB\r
+ bne reg1_error_loop\r
+ cmp r12, #0xCC\r
+ bne reg1_error_loop\r
+ cmp r14, #0xEE\r
+ bne reg1_error_loop\r
+\r
+ ; Everything passed, increment the loop counter.\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+\r
+ ; Start again.\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ ; If this line is hit then there was an error in a core register value.\r
+ ; The loop ensures the loop counter stops incrementing.\r
+ b reg1_error_loop\r
+ nop\r
+\r
+;/*-----------------------------------------------------------*/\r
+\r
+vRegTest2Implementation\r
+\r
+ PRESERVE8\r
+ IMPORT ulRegTest2LoopCounter\r
+\r
+ ; Put a known value in each register.\r
+ mov r0, #0xFF000000\r
+ mov r1, #0x11000000\r
+ mov r2, #0x22000000\r
+ mov r3, #0x33000000\r
+ mov r4, #0x44000000\r
+ mov r5, #0x55000000\r
+ mov r6, #0x66000000\r
+ mov r7, #0x77000000\r
+ mov r8, #0x88000000\r
+ mov r9, #0x99000000\r
+ mov r10, #0xAA000000\r
+ mov r11, #0xBB000000\r
+ mov r12, #0xCC000000\r
+ mov r14, #0xEE000000\r
+\r
+ ; Likewise the floating point registers\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+ ; Loop, checking each iteration that each register still contains the\r
+ ; expected value.\r
+reg2_loop\r
+ ; Check all the VFP registers still contain the values set above.\r
+ ; First save registers that are clobbered by the test.\r
+ push { r0-r1 }\r
+\r
+ vmov r0, r1, d0\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #0x22000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x33000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #0x44000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x55000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #0x66000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x77000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #0x88000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x99000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #0xAA000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0xBB000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #0x22000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x33000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #0x44000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x55000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #0x66000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x77000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #0x88000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x99000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #0xAA000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0xBB000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #0x22000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x33000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #0x44000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x55000000\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #0x66000000\r
+ bne reg2_error_loopf\r
+ cmp r1, #0x77000000\r
+ bne reg2_error_loopf\r
+\r
+ ; Restore the registers that were clobbered by the test.\r
+ pop {r0-r1}\r
+\r
+ ; VFP register test passed. Jump to the core register test.\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ ; If this line is hit then a VFP register value was found to be\r
+ ; incorrect.\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #0xFF000000\r
+ bne reg2_error_loop\r
+ cmp r1, #0x11000000\r
+ bne reg2_error_loop\r
+ cmp r2, #0x22000000\r
+ bne reg2_error_loop\r
+ cmp r3, #0x33000000\r
+ bne reg2_error_loop\r
+ cmp r4, #0x44000000\r
+ bne reg2_error_loop\r
+ cmp r5, #0x55000000\r
+ bne reg2_error_loop\r
+ cmp r6, #0x66000000\r
+ bne reg2_error_loop\r
+ cmp r7, #0x77000000\r
+ bne reg2_error_loop\r
+ cmp r8, #0x88000000\r
+ bne reg2_error_loop\r
+ cmp r9, #0x99000000\r
+ bne reg2_error_loop\r
+ cmp r10, #0xAA000000\r
+ bne reg2_error_loop\r
+ cmp r11, #0xBB000000\r
+ bne reg2_error_loop\r
+ cmp r12, #0xCC000000\r
+ bne reg2_error_loop\r
+ cmp r14, #0xEE000000\r
+ bne reg2_error_loop\r
+\r
+ ; Everything passed, increment the loop counter.\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+\r
+ ; Start again.\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ ; If this line is hit then there was an error in a core register value.\r
+ ; The loop ensures the loop counter stops incrementing.\r
+ b reg2_error_loop\r
+ nop\r
+\r
+\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ * This file is called ParTest.c for historic reasons. Originally it stood for\r
+ * PARallel port TEST.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include "misc/led.h"\r
+#include "peripherals/pio.h"\r
+#include "board.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ led_configure( 0 );\r
+ led_configure( 1 );\r
+ led_configure( 2 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue )\r
+{\r
+ if( xValue == pdTRUE )\r
+ {\r
+ led_set( uxLED );\r
+ }\r
+ else\r
+ {\r
+ led_clear( uxLED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ led_toggle( uxLED );\r
+}\r
+\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>sram</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>28</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\</state>\r
+ </option>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state>$PROJ_DIR$\AtmelFiles\target\sama5d2\toolchain\iar\sram.mac</state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\Atmel\ATSAMA5D35.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>5.50.0.51907</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>CMSISDAP_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>7.60.1.11206</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CLowLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDeviceConfigMacroFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDebuggerExtraOption</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCAllMTBOptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreNrOfCores</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreMaster</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticorePort</name>\r
+ <state>53461</state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreWorkspace</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreSlaveProject</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCMulticoreSlaveConfiguration</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadExtraImage</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCAttachSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspConfigFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CMSISDAP_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>4</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPSelectedCPUBehaviour</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCMSISDAPUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCMSISDAPUsbSerialNoSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>GDBSERVER_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IJET_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>8</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetResetList</name>\r
+ <version>1</version>\r
+ <state>10</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerFromProbe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProtocolRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPin</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPrescalerList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSelectedCPUBehaviour</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCJetEmuParams</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPreferETB</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSettingsList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetTraceSizeList</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashBoardPathSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIjetUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCIjetUsbSerialNoSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>16</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkDeviceName</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkUsbSerialNoSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>TIFET_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetResetList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetTargetVccTypeDefault</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetTargetVoltage</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetVCCDefault</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetTargetSettlingtime</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetRadioJtagSpeedType</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetConnection</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetUsbComPort</name>\r
+ <state>Automatic</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetAllowAccessToBSL</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMSPFetRadioEraseFlash</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>5</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackageOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackage</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>BoardFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100BreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100DoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100UpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100CpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100SwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100SwoClockEdit</name>\r
+ <state>1000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100HWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100ResetList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100UsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100UsbSerialNoSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100JtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100ProbeList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\middleware\PercepioTraceExporter\PercepioTraceExportPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>sram</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>24</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>sram\bin</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>sram\obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>sram\obj</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>3</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>2</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>7.60.1.11206</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>ATSAMA5D35 Atmel ATSAMA5D35</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLowLevelInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianModeBE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGBufferedTerminalOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>24</version>\r
+ <state>48</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibThreads</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CoreVariant</name>\r
+ <version>24</version>\r
+ <state>48</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUDeviceSlave</name>\r
+ <state>ATSAMA5D35 Atmel ATSAMA5D35</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU2</name>\r
+ <version>0</version>\r
+ <state>5</state>\r
+ </option>\r
+ <option>\r
+ <name>NrRegs</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>NEON</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave2</name>\r
+ <version>24</version>\r
+ <state>48</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>31</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCOptimizationNoSizeConstraints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>CONFIG_BOARD_SAMA5D2_XPLAINED</state>\r
+ <state>CONFIG_SOC_SAMA5D27</state>\r
+ <state>CONFIG_HAVE_TWI_ALTERNATE_CMD</state>\r
+ <state>LEDS_ON_J17</state>\r
+ <state>sram</state>\r
+ <state>TRACE_LEVEL=0</state>\r
+ <state>CONFIG_HAVE_PIO4</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>Pa131, Pa039</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>11111110</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$/.</state>\r
+ <state>$PROJ_DIR$\..\..\Source\include</state>\r
+ <state>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC</state>\r
+ <state>$PROJ_DIR$\..\Common\include</state>\r
+ <state>$PROJ_DIR$\Full_Demo</state>\r
+ <state>$PROJ_DIR$\AtmelFiles\target\sama5d2</state>\r
+ <state>$PROJ_DIR$\AtmelFiles\target\sama5d2\pio</state>\r
+ <state>$PROJ_DIR$\AtmelFiles\target\sama5d2\component</state>\r
+ <state>$PROJ_DIR$\AtmelFiles\utils</state>\r
+ <state>$PROJ_DIR$\AtmelFiles\drivers</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeSection</name>\r
+ <state>SOFTPACK</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork2</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevel</name>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptStrategy</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevelSlave</name>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
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+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_i2sc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_icm.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_isc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_l2cc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_lcdc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_matrix.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_mcan.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_mpddrc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_pdmic.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_pio.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_pit.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_pmc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_pwm.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_qspi.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_rstc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_rtc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_rxlp.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_sckc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_sdmmc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_sfc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_sfr.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_sfrbu.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_sha.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_shdwc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_smc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_spi.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_ssc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_tc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_tdes.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_trng.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_twihs.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_uart.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_udphs.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_wdt.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\component\component_xdmac.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>pio</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\pio\pio_sama5d21.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\pio\pio_sama5d22.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\pio\pio_sama5d23.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\pio\pio_sama5d24.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\pio\pio_sama5d26.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\pio\pio_sama5d27.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\pio\pio_sama5d28.h</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\board.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\board_lowlevel.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\board_lowlevel.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\board_memories.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\board_sama5d2-ptc-engi.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\board_sama5d2-vb-bga196.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\board_sama5d2-vb-bga289.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\board_sama5d2-xplained-proto.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\board_sama5d2-xplained.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\chip.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\chip.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\chip_pins.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\sama5d21.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\sama5d22.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\sama5d23.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\sama5d24.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\sama5d26.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\sama5d27.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\target\sama5d2\sama5d28.h</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>utils</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\async.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\compiler.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\crc.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\dbg_util.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\font.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\hamming.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\intmath.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\io.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\lcd_color.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\lcd_draw.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\lcd_font.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\mutex.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\rand.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\ring.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\timer.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\trace.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\AtmelFiles\utils\wav.h</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <group>\r
+ <name>Blinky Demo</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\blinky_demo\main_blinky.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>FreeRTOS Source</name>\r
+ <group>\r
+ <name>portable</name>\r
+ <group>\r
+ <name>MemMang</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC\portASM.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC\portASM.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC\portmacro.h</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\event_groups.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Full Demo</name>\r
+ <group>\r
+ <name>Common Demo Tasks</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flop.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\IntQueue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\Full_Demo\IntQueueTimer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Full_Demo\main_full.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Full_Demo\reg_test.S</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\cstartup_with_FreeRTOS_vectors.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\FreeRTOS_tick_config.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\FreeRTOSConfig.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\LEDs.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds...and so on.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles an LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ *\r
+ * NOTE on LEDS:\r
+ *\r
+ * This demo is NOT configured to use the LED built onto the SAMA6D2\r
+ * XPLained board!\r
+ *\r
+ * The LED driver PIN_LED definitions have been altered in\r
+ * board_sama5d2-xplained.h to remap them to GPIOs terminating on pins 30,\r
+ * 32 and 34 of J17. (This change is conditional on the preprocessor\r
+ * #define "LEDS_ON_J17".) These GPIOs are configured to be "high drive"\r
+ * push-pull outputs; they can source up to 18mA at 1.8v. Low\r
+ * forward-voltage LEDs may be connected via 100 ohm resistors to pins\r
+ * 30, 32 and 34 with their cathodes to pin 35/36 (GND).\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* The LED toggled by the Rx task. */\r
+#define mainTASK_LED ( 2 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in\r
+ * main.c.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static QueueHandle_t xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+const unsigned long ulExpectedValue = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == ulExpectedValue )\r
+ {\r
+ vParTestToggleLED( mainTASK_LED );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/* ----------------------------------------------------------------------------\r
+ * SAM Software Package License\r
+ * ----------------------------------------------------------------------------\r
+ * Copyright (c) 2011, Atmel Corporation\r
+ *\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * - Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the disclaimer below.\r
+ *\r
+ * Atmel's name may not be used to endorse or promote products derived from\r
+ * this software without specific prior written permission.\r
+ *\r
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+/*\r
+ IAR startup file for AT91SAMA5D3X microcontrollers.\r
+ */\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION IRQ_STACK:DATA:NOROOT(2)\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+//------------------------------------------------------------------------------\r
+// Headers\r
+//------------------------------------------------------------------------------\r
+\r
+//#define __ASSEMBLY__\r
+//#include "board.h"\r
+\r
+//------------------------------------------------------------------------------\r
+// Definitions\r
+//------------------------------------------------------------------------------\r
+\r
+#define ARM_MODE_ABT 0x17\r
+#define ARM_MODE_FIQ 0x11\r
+#define ARM_MODE_IRQ 0x12\r
+#define ARM_MODE_SVC 0x13\r
+#define ARM_MODE_SYS 0x1F\r
+\r
+#define I_BIT 0x80\r
+#define F_BIT 0x40\r
+\r
+//------------------------------------------------------------------------------\r
+// Startup routine\r
+//------------------------------------------------------------------------------\r
+\r
+/*\r
+ Exception vectors\r
+ */\r
+ SECTION .vectors:CODE:NOROOT(2)\r
+\r
+ PUBLIC resetVector\r
+\r
+ EXTERN FreeRTOS_IRQ_Handler\r
+ EXTERN Undefined_Handler\r
+ EXTERN FreeRTOS_SWI_Handler\r
+ EXTERN Prefetch_Handler\r
+ EXTERN Abort_Handler\r
+ EXTERN FIQ_Handler\r
+\r
+ ARM\r
+\r
+__iar_init$$done: ; The interrupt vector is not needed\r
+ ; until after copy initialization is done\r
+\r
+resetVector:\r
+ ; All default exception handlers (except reset) are\r
+ ; defined as weak symbol definitions.\r
+ ; If a handler is defined by the application it will take precedence.\r
+ LDR pc, =resetHandler ; Reset\r
+ LDR pc, Undefined_Addr ; Undefined instructions\r
+ LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)\r
+ LDR pc, Prefetch_Addr ; Prefetch abort\r
+ LDR pc, Abort_Addr ; Data abort\r
+ B . ; RESERVED\r
+ LDR pc, IRQ_Addr ; IRQ\r
+ LDR pc, FIQ_Addr ; FIQ\r
+\r
+IRQ_Addr: DCD FreeRTOS_IRQ_Handler\r
+Undefined_Addr: DCD Undefined_Handler\r
+SWI_Addr: DCD FreeRTOS_SWI_Handler\r
+Prefetch_Addr: DCD Prefetch_Handler\r
+Abort_Addr: DCD Abort_Handler\r
+FIQ_Addr: DCD FIQ_Handler\r
+\r
+\r
+/*\r
+ After a reset, execution starts here, the mode is ARM, supervisor\r
+ with interrupts disabled.\r
+ Initializes the chip and branches to the main() function.\r
+ */\r
+ SECTION .cstartup:CODE:NOROOT(2)\r
+\r
+ PUBLIC resetHandler\r
+ EXTERN low_level_init\r
+ EXTERN ?main\r
+ REQUIRE resetVector\r
+ ARM\r
+\r
+resetHandler:\r
+ CPSIE A\r
+ /* Enable VFP */\r
+ /* - Enable access to CP10 and CP11 in CP15.CACR */\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ orr r0, r0, #0xf00000\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ /* - Enable access to CP10 and CP11 in CP15.NSACR */\r
+ /* - Set FPEXC.EN (B30) */\r
+ fmrx r0, fpexc\r
+ orr r0, r0, #0x40000000\r
+ fmxr fpexc, r0\r
+ /* Set pc to actual code location (i.e. not in remap zone) */\r
+ LDR pc, =label\r
+\r
+ /* Perform low-level initialization of the chip using LowLevelInit() */\r
+label:\r
+ /* Sets up Supervisor stack before running LowLevelInit. The supervisor\r
+ stack is reused by interrupts, which switch from IRQ mode to SVC mode. */\r
+ LDR r0, =low_level_init\r
+ LDR r4, =SFE(CSTACK)\r
+ MOV sp, r4\r
+ BLX r0\r
+\r
+ /* Set up the interrupt stack pointer. */\r
+ MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode\r
+ LDR sp, =SFE(IRQ_STACK)\r
+\r
+ /* No need to set up stacks for any other mode as that stack used by\r
+ tasks is allocated by FreeRTOS. */\r
+\r
+ /* Back to Supervisor mode bfore calling main(). The schduduler should\r
+ be started from Supervisor mode. */\r
+ MSR cpsr_c, #ARM_MODE_SVC | F_BIT ; Change the mode\r
+\r
+ /* Branch to main() */\r
+ LDR r0, =?main\r
+ BLX r0\r
+\r
+ /* Loop indefinitely when program is finished */\r
+loop4:\r
+ B loop4\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup, standard FreeRTOS hook functions, and the ISR hander called\r
+ * by the RTOS after interrupt entry (including nesting) has been taken care of.\r
+ *\r
+ * NOTE on LEDS:\r
+ *\r
+ * This demo is NOT configured to use the LED built onto the SAMA6D2\r
+ * XPLained board!\r
+ *\r
+ * The LED driver PIN_LED definitions have been altered in\r
+ * board_sama5d2-xplained.h to remap them to GPIOs terminating on pins 30,\r
+ * 32 and 34 of J17. (This change is conditional on the preprocessor\r
+ * #define "LEDS_ON_J17".) These GPIOs are configured to be "high drive"\r
+ * push-pull outputs; they can source up to 18mA at 1.8v. Low\r
+ * forward-voltage LEDs may be connected via 100 ohm resistors to pins\r
+ * 30, 32 and 34 with their cathodes to pin 35/36 (GND).\r
+ *\r
+ */\r
+\r
+/*\r
+ * Procedure to download and execute code from RAM\r
+ * -----------------------------------------------\r
+ *\r
+ * 1. Close jumper JP9(BOOT_DIS) and JP2(DEBUG_DIS).\r
+ * 2. Open jumper JP1(EDBG_DIS).\r
+ * 3. Power on the board by USB connection on J14(EDBG_JTAG).\r
+ * 4. Open \93EDBG Virtual COM Port\94 with setting \9357600,8,N,1\94.\r
+ * 5. Type \93#\94 on HyperTerminal and get \93>\94 as a reply.\r
+ * 6. Don\92t reset the board during debugging. For IAR, set the Debugger to CMSIS\r
+ * DAP, with the "Disabled(no reset)" option.\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "EventGroupsDemo.h"\r
+\r
+/* Library includes. */\r
+#include "board_sama5d2-xplained.h"\r
+#include "peripherals/wdt.h"\r
+#include "peripherals/pio.h"\r
+#include "chip.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware as necessary to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ extern void main_blinky( void );\r
+#else\r
+ extern void main_full( void );\r
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port\r
+layer. */\r
+void vApplicationIRQHandler( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Configure the hardware ready to run the demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Disable watchdog */\r
+ wdt_disable( );\r
+\r
+ /* Set protect mode in the AIC for easier debugging. */\r
+ AIC->AIC_DCR |= AIC_DCR_PROT;\r
+\r
+ /* Configure ports used by LEDs. */\r
+ vParTestInitialise();\r
+\r
+ #if defined (ddram)\r
+ MMU_Initialize( ( uint32_t * ) 0x30C000 );\r
+ CP15_EnableMMU();\r
+ CP15_EnableDcache();\r
+ CP15_EnableIcache();\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
+ internally by FreeRTOS API functions that create tasks, queues, software\r
+ timers, and semaphores. The size of the FreeRTOS heap is set by the\r
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeHeapSpace;\r
+\r
+ /* This is just a trivial example of an idle hook. It is called on each\r
+ cycle of the idle task. It must *NOT* attempt to block. In this case the\r
+ idle task just queries the amount of FreeRTOS heap that remains. See the\r
+ memory management section on the http://www.FreeRTOS.org web site for memory\r
+ management options. If there is a lot of heap memory free then the\r
+ configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
+ RAM. */\r
+ xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+ /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
+ ( void ) xFreeHeapSpace;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAssertCalled( const char * pcFile, unsigned long ulLine )\r
+{\r
+volatile unsigned long ul = 0;\r
+\r
+ ( void ) pcFile;\r
+ ( void ) ulLine;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Set ul to a non-zero value using the debugger to step out of this\r
+ function. */\r
+ while( ul == 0 )\r
+ {\r
+ portNOP();\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0\r
+ {\r
+ /* The full demo includes a software timer demo/test that requires\r
+ prodding periodically from the tick interrupt. */\r
+ vTimerPeriodicISRTests();\r
+\r
+ /* Call the periodic queue overwrite from ISR demo. */\r
+ vQueueOverwritePeriodicISRDemo();\r
+\r
+ /* Call the periodic event group from ISR demo. */\r
+ vPeriodicEventGroupsProcessing();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The function called by the RTOS port layer after it has managed interrupt\r
+entry. */\r
+void vApplicationIRQHandler( void )\r
+{\r
+typedef void (*ISRFunction_t)( void );\r
+ISRFunction_t pxISRFunction;\r
+volatile uint32_t * pulAIC_IVR = ( uint32_t * ) configINTERRUPT_VECTOR_ADDRESS;\r
+\r
+ /* Obtain the address of the interrupt handler from the AIR. */\r
+ pxISRFunction = ( ISRFunction_t ) *pulAIC_IVR;\r
+\r
+ /* Write back to the SAMA5's interrupt controller's IVR register in case the\r
+ CPU is in protect mode. If the interrupt controller is not in protect mode\r
+ then this write is not necessary. */\r
+ *pulAIC_IVR = ( uint32_t ) pxISRFunction;\r
+\r
+ /* Ensure the write takes before re-enabling interrupts. */\r
+ __DSB();\r
+ __ISB();\r
+ __enable_irq();\r
+\r
+ /* Call the installed ISR. */\r
+ pxISRFunction();\r
+}\r
+\r
+/* Keep the linker quiet. */\r
+size_t __write(int, const unsigned char *, size_t);\r
+size_t __write(int f, const unsigned char *p, size_t s)\r
+{\r
+ (void) f;\r
+ (void) p;\r
+ (void) s;\r
+ return 0;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<crun>\r
+ <version>1</version>\r
+ <filter_entries>\r
+ <filter index="0" type="default">\r
+ <type>*</type>\r
+ <start_file>*</start_file>\r
+ <end_file>*</end_file>\r
+ <action_debugger>0</action_debugger>\r
+ <action_log>1</action_log>\r
+ </filter>\r
+ </filter_entries>\r
+</crun>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+ <Desktop>\r
+ <Static>\r
+ <Debug-Log>\r
+ \r
+ \r
+ <PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window><Window><Factory>Find-in-Files</Factory></Window></Windows></PreferedWindows></Build>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>221</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Disassembly>\r
+ <col-names>\r
+ \r
+ \r
+ <item>Disassembly</item><item>_I0</item></col-names>\r
+ <col-widths>\r
+ \r
+ \r
+ <item>500</item><item>20</item></col-widths>\r
+ <DisasmHistory><item>0x305444</item><item>0x0030211C</item><item>0x00302750</item></DisasmHistory>\r
+ \r
+ \r
+ <PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ShowCodeCoverage>1</ShowCodeCoverage><ShowInstrProfiling>1</ShowInstrProfiling></Disassembly>\r
+ <Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><RegFindHistory/></Register><WATCH_1><expressions><item>xTickCount</item><item></item></expressions><col-names><item>Expression</item><item>Location</item><item>Type</item><item>Value</item></col-names><col-widths><item>207</item><item>150</item><item>100</item><item>294</item></col-widths><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></WATCH_1><CallStack><PreferedWindows><Position>1</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><col-names><item>Frame</item><item>_I0</item></col-names><col-widths><item>400</item><item>20</item></col-widths></CallStack><Breakpoints><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><col-names><item>Breakpoint</item><item>_I0</item></col-names><col-widths><item>500</item><item>35</item></col-widths></Breakpoints><Find-in-Files><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window></Windows></PreferedWindows><ColumnWidth0>497</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>746</ColumnWidth2><ColumnWidth3>331</ColumnWidth3></Find-in-Files><QuickWatch><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><col-names><item>Expression</item><item>Location</item><item>Type</item><item>Value</item></col-names><col-widths><item>100</item><item>150</item><item>100</item><item>100</item></col-widths><QWatchHistory><item>TC0</item><item>TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_RC</item></QWatchHistory></QuickWatch><Memory><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><TASKVIEW><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column8>150</Column8><Column0>200</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3><Column4>100</Column4><Column5>100</Column5><Column6>100</Column6><Column7>150</Column7></TASKVIEW><QUEUEVIEW><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>300</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3><Column4>100</Column4><Column5>100</Column5><Column6>100</Column6></QUEUEVIEW><STACK_1><PreferedWindows><Position>1</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><stack>CSTACK</stack><width>4</width><vars>1</vars><offset>0</offset><col-names><item>Data</item><item>Frame</item><item>Location</item><item>Type</item><item>Value</item><item>Variable</item></col-names><col-widths><item>100</item><item>100</item><item>100</item><item>100</item><item>100</item><item>100</item></col-widths></STACK_1></Static>\r
+ <Windows>\r
+ \r
+ \r
+ \r
+ <Wnd1>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-24673-23877</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Blinky Demo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS+CLI</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd1><Wnd3><Tabs><Tab><Identity>TabID-17936-21395</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3><Wnd5><Tabs><Tab><Identity>TabID-2504-23322</Identity><TabName>Watch 1</TabName><Factory>WATCH_1</Factory></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd5></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\AtmelFiles\drivers\peripherals\pmc.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>661</YPos2><SelStart2>17472</SelStart2><SelEnd2>17518</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\FreeRTOSConfig.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>63</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\Full_Demo\IntQueueTimer.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>124</YPos2><SelStart2>7425</SelStart2><SelEnd2>7425</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\AtmelFiles\target\sama5d2\board_sama5d2-xplained.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>287</YPos2><SelStart2>3046</SelStart2><SelEnd2>3046</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\AtmelFiles\drivers\peripherals\tc.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>103</YPos2><SelStart2>4433</SelStart2><SelEnd2>4433</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\Common\Minimal\flop.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>318</YPos2><SelStart2>12375</SelStart2><SelEnd2>12375</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\tasks.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>2670</YPos2><SelStart2>90667</SelStart2><SelEnd2>90667</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\Full_Demo\reg_test.S</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>396</YPos2><SelStart2>12233</SelStart2><SelEnd2>12233</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\portable\IAR\ARM_CA5_No_GIC\port.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>65</YPos2><SelStart2>12238</SelStart2><SelEnd2>12238</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\queue.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>818</YPos2><SelStart2>31969</SelStart2><SelEnd2>31969</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\Common\Minimal\IntQueue.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>692</YPos2><SelStart2>26557</SelStart2><SelEnd2>26557</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\Full_Demo\main_full.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>128</YPos2><SelStart2>7751</SelStart2><SelEnd2>7751</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\Common\Minimal\flash.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>82</YPos2><SelStart2>5071</SelStart2><SelEnd2>5071</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\AtmelFiles\drivers\peripherals\pio4.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>137</YPos2><SelStart2>5255</SelStart2><SelEnd2>5255</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>136</YPos2><SelStart2>7392</SelStart2><SelEnd2>7392</SelEnd2></Tab><ActiveTab>14</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\blinky_demo\main_blinky.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>81</YPos2><SelStart2>6895</SelStart2><SelEnd2>6895</SelEnd2></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-00DB5748><key>iaridepm.enu1</key></Toolbar-00DB5748><Toolbar-12C42948><key>debuggergui.enu1</key></Toolbar-12C42948></Sizes></Row0><Row1><Sizes><Toolbar-12C42F88><key>armjet.enu1</key></Toolbar-12C42F88></Sizes></Row1></Top><Left><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>868</Bottom><Right>295</Right><x>-2</x><y>-2</y><xscreen>228</xscreen><yscreen>230</yscreen><sizeHorzCX>118750</sizeHorzCX><sizeHorzCY>202822</sizeHorzCY><sizeVertCX>154688</sizeVertCX><sizeVertCY>767196</sizeVertCY></Rect></Wnd1></Sizes></Row0></Left><Right><Row0><Sizes><Wnd5><Rect><Top>-2</Top><Left>-2</Left><Bottom>868</Bottom><Right>642</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>104167</sizeHorzCX><sizeHorzCY>176367</sizeHorzCY><sizeVertCX>335417</sizeVertCX><sizeVertCY>767196</sizeVertCY></Rect></Wnd5></Sizes></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1922</Right><x>-2</x><y>-2</y><xscreen>1924</xscreen><yscreen>200</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>176367</sizeHorzCY><sizeVertCX>104167</sizeVertCX><sizeVertCY>176367</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Project>\r
+\r
+\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.0\common\bin\cspybat" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armproc.dll" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armjlink.dll" %1 --plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armbat.dll" --macro "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_A5_SAMA5D3x_Xplained_IAR\..\..\..\..\libraries\libboard_sama5d3x-ek\resources\ewarm\sama5d3x-ek-ddram.mac" --backend -B "--endian=little" "--cpu=Cortex-A5" "--fpu=None" "-p" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\CONFIG\debugger\Atmel\ATSAMA5D35.ddf" "--drv_verify_download" "--semihosting=none" "--device=ATSAMA5D35" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--drv_catch_exceptions=0x000" \r
+\r
+\r
--- /dev/null
+[Stack]\r
+FillEnabled=0\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=0\r
+WarnLogOnly=1\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[JLinkDriver]\r
+WatchCond=_ 0\r
+Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0\r
+Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0\r
+CStepIntDis=_ 0\r
+LeaveTargetRunning=_ 0\r
+[DebugChecksum]\r
+Checksum=-596461035\r
+[Exceptions]\r
+StopOnUncaught=_ 0\r
+StopOnThrow=_ 0\r
+[CallStack]\r
+ShowArgs=0\r
+[Disassembly]\r
+MixedMode=1\r
+[CallStackLog]\r
+Enabled=0\r
+[DriverProfiling]\r
+Enabled=0\r
+Mode=0\r
+Graph=0\r
+Symbiont=0\r
+Exclusions=\r
+[PlDriver]\r
+MemConfigValue=C:\DevTools\IAR Systems\Embedded Workbench 7.4\arm\CONFIG\debugger\Atmel\ATSAMA5D35.ddf\r
+FirstRun=0\r
+[Jet]\r
+DisableInterrupts=0\r
+MultiCoreRunAll=0\r
+JetConnSerialNo=408243741\r
+JetConnFoundProbes=\r
+OnlineReset=Software\r
+PrevWtdReset=Disabled (no reset)\r
+LeaveRunning=0\r
+[ArmDriver]\r
+EnableCache=1\r
+[SWOManager]\r
+SamplingDivider=8192\r
+OverrideClock=0\r
+CpuClock=1919246957\r
+SwoClock=941636128\r
+DataLogMode=0\r
+ItmPortsEnabled=63\r
+ItmTermIOPorts=1\r
+ItmLogPorts=0\r
+ItmLogFile=$PROJ_DIR$\ITM.log\r
+PowerForcePC=1\r
+PowerConnectPC=1\r
+[watch_formats]\r
+Fmt0={W}1:xTickCount 3 0\r
+[Trace1]\r
+Enabled=0\r
+ShowSource=1\r
+[ETMTraceWindow]\r
+PortWidth=4\r
+PortMode=0\r
+CaptureDataValues=0\r
+CaptureDataAddresses=0\r
+CaptureDataRange=0\r
+DataFirst=0\r
+DataLast=-1\r
+StopWhen=0\r
+StallCPU=0\r
+NoPCCapture=0\r
+[Trace2]\r
+Enabled=0\r
+ShowSource=0\r
+[SWOTraceWindow]\r
+ForcedPcSampling=0\r
+ForcedInterruptLogs=0\r
+ForcedItmLogs=0\r
+EventCPI=0\r
+EventEXC=0\r
+EventFOLD=0\r
+EventLSU=0\r
+EventSLEEP=0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints2]\r
+Bp0=_ 1 "EMUL_CODE" "{$PROJ_DIR$\main.c}.254.2" 0 0 1 "" 0 "" 0\r
+Count=1\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+@echo off \r
+\r
+if not "%~1" == "" goto debugFile \r
+\r
+@echo on \r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.4\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_A5_SAMA5D2x_Xplained_IAR\settings\RTOSDemo.sram.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_A5_SAMA5D2x_Xplained_IAR\settings\RTOSDemo.sram.driver.xcl" \r
+\r
+@echo off \r
+goto end \r
+\r
+:debugFile \r
+\r
+@echo on \r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.4\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_A5_SAMA5D2x_Xplained_IAR\settings\RTOSDemo.sram.general.xcl" "--debug_file=%~1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_A5_SAMA5D2x_Xplained_IAR\settings\RTOSDemo.sram.driver.xcl" \r
+\r
+@echo off \r
+:end
\ No newline at end of file
--- /dev/null
+"--endian=little" \r
+\r
+"--cpu=Cortex-A5" \r
+\r
+"--fpu=VFPv4Neon" \r
+\r
+"-p" \r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.4\arm\CONFIG\debugger\Atmel\ATSAMA5D35.ddf" \r
+\r
+"--drv_verify_download" \r
+\r
+"--semihosting=none" \r
+\r
+"--device=ATSAMA5D35" \r
+\r
+"--multicore_nr_of_cores=1" \r
+\r
+"--jet_probe=cmsisdap" \r
+\r
+"--jet_standard_reset=0,0,0" \r
+\r
+"--reset_style=\"0,-,1,Disabled__no_reset_\"" \r
+\r
+"--reset_style=\"1,-,0,Software\"" \r
+\r
+"--reset_style=\"2,-,0,Hardware\"" \r
+\r
+"--reset_style=\"5,SoftwareReset,0,Custom\"" \r
+\r
+"--drv_catch_exceptions=0x01a" \r
+\r
+\r
+\r
+\r
--- /dev/null
+"C:\DevTools\IAR Systems\Embedded Workbench 7.4\arm\bin\armproc.dll" \r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.4\arm\bin\armJET.dll" \r
+\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_A5_SAMA5D2x_Xplained_IAR\sram\bin\sram.out" \r
+\r
+--plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.4\arm\bin\armbat.dll" \r
+\r
+--device_macro "C:\DevTools\IAR Systems\Embedded Workbench 7.4\arm\config\debugger\Atmel\SAMA5D3.dmac" \r
+\r
+--macro "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_A5_SAMA5D2x_Xplained_IAR\AtmelFiles\target\sama5d2\toolchain\iar\sram.mac" \r
+\r
+\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>RTOSDemo/sram</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>362</Column0><Column1>0</Column1><Column2>27</Column2><Column3>0</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <CRunMessageRules>\r
+ <col-names>\r
+ <item>Action</item>\r
+ <item>Check</item>\r
+ <item>Source File</item>\r
+ </col-names>\r
+ <col-widths>\r
+ <item>100</item>\r
+ <item>400</item>\r
+ <item>200</item>\r
+ </col-widths>\r
+ </CRunMessageRules>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>\r
+ <Debug-Log><ColumnWidth0>18</ColumnWidth0><ColumnWidth1>1624</ColumnWidth1></Debug-Log><TerminalIO/><Select-Ambiguous-Definitions><ColumnWidth0>552</ColumnWidth0><ColumnWidth1>78</ColumnWidth1><ColumnWidth2>946</ColumnWidth2></Select-Ambiguous-Definitions><Find-in-Files><ColumnWidth0>846</ColumnWidth0><ColumnWidth1>82</ColumnWidth1><ColumnWidth2>746</ColumnWidth2><ColumnWidth3>331</ColumnWidth3></Find-in-Files><Breakpoints><col-names><item>Breakpoint</item><item>_I0</item></col-names><col-widths><item>500</item><item>35</item></col-widths><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Breakpoints></Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd2>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-22351-19008</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS+CLI</ExpandedNode><ExpandedNode>RTOSDemo/Output</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-21076-19237</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ <Tab><Identity>TabID-23502-23081</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-24431-23894</Identity><TabName>Ambiguous Definitions</TabName><Factory>Select-Ambiguous-Definitions</Factory><Session/></Tab><Tab><Identity>TabID-9033-6116</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>73</YPos2><SelStart2>4651</SelStart2><SelEnd2>5276</SelEnd2></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\Full_Demo\main_full.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>66</YPos2><SelStart2>6963</SelStart2><SelEnd2>6963</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\blinky_demo\main_blinky.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>69</YPos2><SelStart2>6708</SelStart2><SelEnd2>6708</SelEnd2></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-00DB5748><key>iaridepm.enu1</key></Toolbar-00DB5748></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>848</Bottom><Right>409</Right><x>-2</x><y>-2</y><xscreen>148</xscreen><yscreen>151</yscreen><sizeHorzCX>77083</sizeHorzCX><sizeHorzCY>133157</sizeHorzCY><sizeVertCX>214063</sizeVertCX><sizeVertCY>749559</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>242</Bottom><Right>1922</Right><x>-2</x><y>-2</y><xscreen>1924</xscreen><yscreen>244</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>215168</sizeHorzCY><sizeVertCX>77083</sizeVertCX><sizeVertCY>133157</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+[MainWindow]\r
+WindowPlacement=_ 352 17 1850 887 3\r
--- /dev/null
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="UNSPECIFIED"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
projects / freertos / commitdiff