1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2015, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAMA5D2_PIO_COMPONENT_
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31 #define _SAMA5D2_PIO_COMPONENT_
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33 /* ============================================================================= */
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34 /** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
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35 /* ============================================================================= */
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36 /** \addtogroup SAMA5D2_PIO Parallel Input/Output Controller */
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39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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40 /** \brief PioIo_group hardware registers */
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42 __IO uint32_t PIO_MSKR; /**< \brief (PioIo_group Offset: 0x0) PIO Mask Register */
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43 __IO uint32_t PIO_CFGR; /**< \brief (PioIo_group Offset: 0x4) PIO Configuration Register */
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44 __I uint32_t PIO_PDSR; /**< \brief (PioIo_group Offset: 0x8) PIO Pin Data Status Register */
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45 __I uint32_t PIO_LOCKSR; /**< \brief (PioIo_group Offset: 0xC) PIO Lock Status Register */
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46 __O uint32_t PIO_SODR; /**< \brief (PioIo_group Offset: 0x10) PIO Set Output Data Register */
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47 __O uint32_t PIO_CODR; /**< \brief (PioIo_group Offset: 0x14) PIO Clear Output Data Register */
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48 __IO uint32_t PIO_ODSR; /**< \brief (PioIo_group Offset: 0x18) PIO Output Data Status Register */
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49 __I uint32_t Reserved1[1];
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50 __O uint32_t PIO_IER; /**< \brief (PioIo_group Offset: 0x20) PIO Interrupt Enable Register */
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51 __O uint32_t PIO_IDR; /**< \brief (PioIo_group Offset: 0x24) PIO Interrupt Disable Register */
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52 __I uint32_t PIO_IMR; /**< \brief (PioIo_group Offset: 0x28) PIO Interrupt Mask Register */
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53 __I uint32_t PIO_ISR; /**< \brief (PioIo_group Offset: 0x2C) PIO Interrupt Status Register */
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54 __I uint32_t Reserved2[3];
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55 __O uint32_t PIO_IOFR; /**< \brief (PioIo_group Offset: 0x3C) PIO I/O Freeze Register */
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57 /** \brief PioPio_ hardware registers */
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59 __IO uint32_t S_PIO_MSKR; /**< \brief (PioPio_ Offset: 0x0) Secure PIO Mask Register */
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60 __IO uint32_t S_PIO_CFGR; /**< \brief (PioPio_ Offset: 0x4) Secure PIO Configuration Register */
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61 __I uint32_t S_PIO_PDSR; /**< \brief (PioPio_ Offset: 0x8) Secure PIO Pin Data Status Register */
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62 __I uint32_t S_PIO_LOCKSR; /**< \brief (PioPio_ Offset: 0xC) Secure PIO Lock Status Register */
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63 __O uint32_t S_PIO_SODR; /**< \brief (PioPio_ Offset: 0x10) Secure PIO Set Output Data Register */
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64 __O uint32_t S_PIO_CODR; /**< \brief (PioPio_ Offset: 0x14) Secure PIO Clear Output Data Register */
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65 __IO uint32_t S_PIO_ODSR; /**< \brief (PioPio_ Offset: 0x18) Secure PIO Output Data Status Register */
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66 __I uint32_t Reserved3[1];
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67 __O uint32_t S_PIO_IER; /**< \brief (PioPio_ Offset: 0x20) Secure PIO Interrupt Enable Register */
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68 __O uint32_t S_PIO_IDR; /**< \brief (PioPio_ Offset: 0x24) Secure PIO Interrupt Disable Register */
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69 __I uint32_t S_PIO_IMR; /**< \brief (PioPio_ Offset: 0x28) Secure PIO Interrupt Mask Register */
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70 __I uint32_t S_PIO_ISR; /**< \brief (PioPio_ Offset: 0x2C) Secure PIO Interrupt Status Register */
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71 __O uint32_t S_PIO_SIONR; /**< \brief (PioPio_ Offset: 0x30) Secure PIO Set I/O Non-Secure Register */
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72 __O uint32_t S_PIO_SIOSR; /**< \brief (PioPio_ Offset: 0x34) Secure PIO Set I/O Secure Register */
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73 __I uint32_t S_PIO_IOSSR; /**< \brief (PioPio_ Offset: 0x38) Secure PIO I/O Security Status Register */
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74 __O uint32_t S_PIO_IOFR; /**< \brief (PioPio_ Offset: 0x3C) Secure PIO I/O Freeze Register */
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76 /** \brief Pio hardware registers */
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77 #define PIOIO_GROUP_NUMBER 4
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78 #define PIOPIO__NUMBER 4
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80 PioIo_group PIO_IO_GROUP[PIOIO_GROUP_NUMBER]; /**< \brief (Pio Offset: 0x0) io_group = 0 .. 3 */
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81 __I uint32_t Reserved1[312];
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82 __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x5E0) PIO Write Protection Mode Register */
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83 __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x5E4) PIO Write Protection Status Register */
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84 __I uint32_t Reserved2[5];
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85 __I uint32_t PIO_VERSION; /**< \brief (Pio Offset: 0x5FC) Version Register */
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86 __I uint32_t Reserved3[640];
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87 PioPio_ PIO_PIO_[PIOPIO__NUMBER]; /**< \brief (Pio Offset: 0x1000) io_group = 0 .. 3 */
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88 __I uint32_t Reserved4[256];
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89 __IO uint32_t S_PIO_SCDR; /**< \brief (Pio Offset: 0x1500) Secure PIO Slow Clock Divider Debouncing Register */
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90 __I uint32_t Reserved5[55];
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91 __IO uint32_t S_PIO_WPMR; /**< \brief (Pio Offset: 0x15E0) Secure PIO Write Protection Mode Register */
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92 __I uint32_t S_PIO_WPSR; /**< \brief (Pio Offset: 0x15E4) Secure PIO Write Protection Status Register */
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94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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95 /* -------- PIO_MSKR : (PIO Offset: N/A) PIO Mask Register -------- */
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96 #define PIO_MSKR_MSK0 (0x1u << 0) /**< \brief (PIO_MSKR) PIO Line 0 Mask */
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97 #define PIO_MSKR_MSK0_DISABLED (0x0u << 0) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
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98 #define PIO_MSKR_MSK0_ENABLED (0x1u << 0) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
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99 #define PIO_MSKR_MSK1 (0x1u << 1) /**< \brief (PIO_MSKR) PIO Line 1 Mask */
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100 #define PIO_MSKR_MSK1_DISABLED (0x0u << 1) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
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101 #define PIO_MSKR_MSK1_ENABLED (0x1u << 1) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
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102 #define PIO_MSKR_MSK2 (0x1u << 2) /**< \brief (PIO_MSKR) PIO Line 2 Mask */
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103 #define PIO_MSKR_MSK2_DISABLED (0x0u << 2) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
104 #define PIO_MSKR_MSK2_ENABLED (0x1u << 2) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
105 #define PIO_MSKR_MSK3 (0x1u << 3) /**< \brief (PIO_MSKR) PIO Line 3 Mask */
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106 #define PIO_MSKR_MSK3_DISABLED (0x0u << 3) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
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107 #define PIO_MSKR_MSK3_ENABLED (0x1u << 3) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
108 #define PIO_MSKR_MSK4 (0x1u << 4) /**< \brief (PIO_MSKR) PIO Line 4 Mask */
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109 #define PIO_MSKR_MSK4_DISABLED (0x0u << 4) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
110 #define PIO_MSKR_MSK4_ENABLED (0x1u << 4) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
111 #define PIO_MSKR_MSK5 (0x1u << 5) /**< \brief (PIO_MSKR) PIO Line 5 Mask */
\r
112 #define PIO_MSKR_MSK5_DISABLED (0x0u << 5) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
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113 #define PIO_MSKR_MSK5_ENABLED (0x1u << 5) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
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114 #define PIO_MSKR_MSK6 (0x1u << 6) /**< \brief (PIO_MSKR) PIO Line 6 Mask */
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115 #define PIO_MSKR_MSK6_DISABLED (0x0u << 6) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
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116 #define PIO_MSKR_MSK6_ENABLED (0x1u << 6) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
117 #define PIO_MSKR_MSK7 (0x1u << 7) /**< \brief (PIO_MSKR) PIO Line 7 Mask */
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118 #define PIO_MSKR_MSK7_DISABLED (0x0u << 7) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
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119 #define PIO_MSKR_MSK7_ENABLED (0x1u << 7) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
120 #define PIO_MSKR_MSK8 (0x1u << 8) /**< \brief (PIO_MSKR) PIO Line 8 Mask */
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121 #define PIO_MSKR_MSK8_DISABLED (0x0u << 8) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
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122 #define PIO_MSKR_MSK8_ENABLED (0x1u << 8) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
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123 #define PIO_MSKR_MSK9 (0x1u << 9) /**< \brief (PIO_MSKR) PIO Line 9 Mask */
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124 #define PIO_MSKR_MSK9_DISABLED (0x0u << 9) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
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125 #define PIO_MSKR_MSK9_ENABLED (0x1u << 9) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
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126 #define PIO_MSKR_MSK10 (0x1u << 10) /**< \brief (PIO_MSKR) PIO Line 10 Mask */
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127 #define PIO_MSKR_MSK10_DISABLED (0x0u << 10) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
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128 #define PIO_MSKR_MSK10_ENABLED (0x1u << 10) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
129 #define PIO_MSKR_MSK11 (0x1u << 11) /**< \brief (PIO_MSKR) PIO Line 11 Mask */
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130 #define PIO_MSKR_MSK11_DISABLED (0x0u << 11) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
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131 #define PIO_MSKR_MSK11_ENABLED (0x1u << 11) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
132 #define PIO_MSKR_MSK12 (0x1u << 12) /**< \brief (PIO_MSKR) PIO Line 12 Mask */
\r
133 #define PIO_MSKR_MSK12_DISABLED (0x0u << 12) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
134 #define PIO_MSKR_MSK12_ENABLED (0x1u << 12) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
135 #define PIO_MSKR_MSK13 (0x1u << 13) /**< \brief (PIO_MSKR) PIO Line 13 Mask */
\r
136 #define PIO_MSKR_MSK13_DISABLED (0x0u << 13) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
137 #define PIO_MSKR_MSK13_ENABLED (0x1u << 13) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
138 #define PIO_MSKR_MSK14 (0x1u << 14) /**< \brief (PIO_MSKR) PIO Line 14 Mask */
\r
139 #define PIO_MSKR_MSK14_DISABLED (0x0u << 14) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
140 #define PIO_MSKR_MSK14_ENABLED (0x1u << 14) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
141 #define PIO_MSKR_MSK15 (0x1u << 15) /**< \brief (PIO_MSKR) PIO Line 15 Mask */
\r
142 #define PIO_MSKR_MSK15_DISABLED (0x0u << 15) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
143 #define PIO_MSKR_MSK15_ENABLED (0x1u << 15) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
144 #define PIO_MSKR_MSK16 (0x1u << 16) /**< \brief (PIO_MSKR) PIO Line 16 Mask */
\r
145 #define PIO_MSKR_MSK16_DISABLED (0x0u << 16) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
146 #define PIO_MSKR_MSK16_ENABLED (0x1u << 16) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
147 #define PIO_MSKR_MSK17 (0x1u << 17) /**< \brief (PIO_MSKR) PIO Line 17 Mask */
\r
148 #define PIO_MSKR_MSK17_DISABLED (0x0u << 17) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
149 #define PIO_MSKR_MSK17_ENABLED (0x1u << 17) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
150 #define PIO_MSKR_MSK18 (0x1u << 18) /**< \brief (PIO_MSKR) PIO Line 18 Mask */
\r
151 #define PIO_MSKR_MSK18_DISABLED (0x0u << 18) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
152 #define PIO_MSKR_MSK18_ENABLED (0x1u << 18) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
153 #define PIO_MSKR_MSK19 (0x1u << 19) /**< \brief (PIO_MSKR) PIO Line 19 Mask */
\r
154 #define PIO_MSKR_MSK19_DISABLED (0x0u << 19) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
155 #define PIO_MSKR_MSK19_ENABLED (0x1u << 19) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
156 #define PIO_MSKR_MSK20 (0x1u << 20) /**< \brief (PIO_MSKR) PIO Line 20 Mask */
\r
157 #define PIO_MSKR_MSK20_DISABLED (0x0u << 20) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
158 #define PIO_MSKR_MSK20_ENABLED (0x1u << 20) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
159 #define PIO_MSKR_MSK21 (0x1u << 21) /**< \brief (PIO_MSKR) PIO Line 21 Mask */
\r
160 #define PIO_MSKR_MSK21_DISABLED (0x0u << 21) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
161 #define PIO_MSKR_MSK21_ENABLED (0x1u << 21) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
162 #define PIO_MSKR_MSK22 (0x1u << 22) /**< \brief (PIO_MSKR) PIO Line 22 Mask */
\r
163 #define PIO_MSKR_MSK22_DISABLED (0x0u << 22) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
164 #define PIO_MSKR_MSK22_ENABLED (0x1u << 22) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
165 #define PIO_MSKR_MSK23 (0x1u << 23) /**< \brief (PIO_MSKR) PIO Line 23 Mask */
\r
166 #define PIO_MSKR_MSK23_DISABLED (0x0u << 23) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
167 #define PIO_MSKR_MSK23_ENABLED (0x1u << 23) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
168 #define PIO_MSKR_MSK24 (0x1u << 24) /**< \brief (PIO_MSKR) PIO Line 24 Mask */
\r
169 #define PIO_MSKR_MSK24_DISABLED (0x0u << 24) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
170 #define PIO_MSKR_MSK24_ENABLED (0x1u << 24) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
171 #define PIO_MSKR_MSK25 (0x1u << 25) /**< \brief (PIO_MSKR) PIO Line 25 Mask */
\r
172 #define PIO_MSKR_MSK25_DISABLED (0x0u << 25) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
173 #define PIO_MSKR_MSK25_ENABLED (0x1u << 25) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
174 #define PIO_MSKR_MSK26 (0x1u << 26) /**< \brief (PIO_MSKR) PIO Line 26 Mask */
\r
175 #define PIO_MSKR_MSK26_DISABLED (0x0u << 26) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
176 #define PIO_MSKR_MSK26_ENABLED (0x1u << 26) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
177 #define PIO_MSKR_MSK27 (0x1u << 27) /**< \brief (PIO_MSKR) PIO Line 27 Mask */
\r
178 #define PIO_MSKR_MSK27_DISABLED (0x0u << 27) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
179 #define PIO_MSKR_MSK27_ENABLED (0x1u << 27) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
180 #define PIO_MSKR_MSK28 (0x1u << 28) /**< \brief (PIO_MSKR) PIO Line 28 Mask */
\r
181 #define PIO_MSKR_MSK28_DISABLED (0x0u << 28) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
182 #define PIO_MSKR_MSK28_ENABLED (0x1u << 28) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
183 #define PIO_MSKR_MSK29 (0x1u << 29) /**< \brief (PIO_MSKR) PIO Line 29 Mask */
\r
184 #define PIO_MSKR_MSK29_DISABLED (0x0u << 29) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
185 #define PIO_MSKR_MSK29_ENABLED (0x1u << 29) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
186 #define PIO_MSKR_MSK30 (0x1u << 30) /**< \brief (PIO_MSKR) PIO Line 30 Mask */
\r
187 #define PIO_MSKR_MSK30_DISABLED (0x0u << 30) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
188 #define PIO_MSKR_MSK30_ENABLED (0x1u << 30) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
189 #define PIO_MSKR_MSK31 (0x1u << 31) /**< \brief (PIO_MSKR) PIO Line 31 Mask */
\r
190 #define PIO_MSKR_MSK31_DISABLED (0x0u << 31) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
191 #define PIO_MSKR_MSK31_ENABLED (0x1u << 31) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
\r
192 /* -------- PIO_CFGR : (PIO Offset: N/A) PIO Configuration Register -------- */
\r
193 #define PIO_CFGR_FUNC_Pos 0
\r
194 #define PIO_CFGR_FUNC_Msk (0x7u << PIO_CFGR_FUNC_Pos) /**< \brief (PIO_CFGR) I/O Line Function */
\r
195 #define PIO_CFGR_FUNC(value) ((PIO_CFGR_FUNC_Msk & ((value) << PIO_CFGR_FUNC_Pos)))
\r
196 #define PIO_CFGR_FUNC_GPIO (0x0u << 0) /**< \brief (PIO_CFGR) Select the PIO mode for the selected I/O lines. */
\r
197 #define PIO_CFGR_FUNC_PERIPH_A (0x1u << 0) /**< \brief (PIO_CFGR) Select the peripheral A for the selected I/O lines. */
\r
198 #define PIO_CFGR_FUNC_PERIPH_B (0x2u << 0) /**< \brief (PIO_CFGR) Select the peripheral B for the selected I/O lines. */
\r
199 #define PIO_CFGR_FUNC_PERIPH_C (0x3u << 0) /**< \brief (PIO_CFGR) Select the peripheral C for the selected I/O lines. */
\r
200 #define PIO_CFGR_FUNC_PERIPH_D (0x4u << 0) /**< \brief (PIO_CFGR) Select the peripheral D for the selected I/O lines. */
\r
201 #define PIO_CFGR_FUNC_PERIPH_E (0x5u << 0) /**< \brief (PIO_CFGR) Select the peripheral E for the selected I/O lines. */
\r
202 #define PIO_CFGR_FUNC_PERIPH_F (0x6u << 0) /**< \brief (PIO_CFGR) Select the peripheral F for the selected I/O lines. */
\r
203 #define PIO_CFGR_FUNC_PERIPH_G (0x7u << 0) /**< \brief (PIO_CFGR) Select the peripheral G for the selected I/O lines. */
\r
204 #define PIO_CFGR_DIR (0x1u << 8) /**< \brief (PIO_CFGR) Direction */
\r
205 #define PIO_CFGR_DIR_INPUT (0x0u << 8) /**< \brief (PIO_CFGR) The selected I/O lines are pure inputs. */
\r
206 #define PIO_CFGR_DIR_OUTPUT (0x1u << 8) /**< \brief (PIO_CFGR) The selected I/O lines are enabled in output. */
\r
207 #define PIO_CFGR_PUEN (0x1u << 9) /**< \brief (PIO_CFGR) Pull-Up Enable */
\r
208 #define PIO_CFGR_PUEN_DISABLED (0x0u << 9) /**< \brief (PIO_CFGR) Pull-Up is disabled for the selected I/O lines. */
\r
209 #define PIO_CFGR_PUEN_ENABLED (0x1u << 9) /**< \brief (PIO_CFGR) Pull-Up is enabled for the selected I/O lines. */
\r
210 #define PIO_CFGR_PDEN (0x1u << 10) /**< \brief (PIO_CFGR) Pull-Down Enable */
\r
211 #define PIO_CFGR_PDEN_DISABLED (0x0u << 10) /**< \brief (PIO_CFGR) Pull-Down is disabled for the selected I/O lines. */
\r
212 #define PIO_CFGR_PDEN_ENABLED (0x1u << 10) /**< \brief (PIO_CFGR) Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1). */
\r
213 #define PIO_CFGR_IFEN (0x1u << 12) /**< \brief (PIO_CFGR) Input Filter Enable */
\r
214 #define PIO_CFGR_IFEN_DISABLED (0x0u << 12) /**< \brief (PIO_CFGR) The input filter is disabled for the selected I/O lines. */
\r
215 #define PIO_CFGR_IFEN_ENABLED (0x1u << 12) /**< \brief (PIO_CFGR) The input filter is enabled for the selected I/O lines. */
\r
216 #define PIO_CFGR_IFSCEN (0x1u << 13) /**< \brief (PIO_CFGR) Input Filter Slow Clock Enable */
\r
217 #define PIO_CFGR_IFSCEN_DISABLED (0x0u << 13) /**< \brief (PIO_CFGR) The glitch filter is able to filter glitches with a duration < tmck/2 for the selected I/O lines. */
\r
218 #define PIO_CFGR_IFSCEN_ENABLED (0x1u << 13) /**< \brief (PIO_CFGR) The debouncing filter is able to filter pulses with a duration < tdiv_slck/2 for the selected I/O lines. */
\r
219 #define PIO_CFGR_OPD (0x1u << 14) /**< \brief (PIO_CFGR) Open-Drain */
\r
220 #define PIO_CFGR_OPD_DISABLED (0x0u << 14) /**< \brief (PIO_CFGR) The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level. */
\r
221 #define PIO_CFGR_OPD_ENABLED (0x1u << 14) /**< \brief (PIO_CFGR) The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only. */
\r
222 #define PIO_CFGR_SCHMITT (0x1u << 15) /**< \brief (PIO_CFGR) Schmitt Trigger */
\r
223 #define PIO_CFGR_SCHMITT_ENABLED (0x0u << 15) /**< \brief (PIO_CFGR) Schmitt trigger is enabled for the selected I/O lines. */
\r
224 #define PIO_CFGR_SCHMITT_DISABLED (0x1u << 15) /**< \brief (PIO_CFGR) Schmitt trigger is disabled for the selected I/O lines. */
\r
225 #define PIO_CFGR_DRVSTR_Pos 16
\r
226 #define PIO_CFGR_DRVSTR_Msk (0x3u << PIO_CFGR_DRVSTR_Pos) /**< \brief (PIO_CFGR) Drive Strength */
\r
227 #define PIO_CFGR_DRVSTR(value) ((PIO_CFGR_DRVSTR_Msk & ((value) << PIO_CFGR_DRVSTR_Pos)))
\r
228 #define PIO_CFGR_DRVSTR_LO (0x0u << 16) /**< \brief (PIO_CFGR) Low drive */
\r
229 #define PIO_CFGR_DRVSTR_ME (0x2u << 16) /**< \brief (PIO_CFGR) Medium drive */
\r
230 #define PIO_CFGR_DRVSTR_HI (0x3u << 16) /**< \brief (PIO_CFGR) High drive */
\r
231 #define PIO_CFGR_EVTSEL_Pos 24
\r
232 #define PIO_CFGR_EVTSEL_Msk (0x7u << PIO_CFGR_EVTSEL_Pos) /**< \brief (PIO_CFGR) Event Selection */
\r
233 #define PIO_CFGR_EVTSEL(value) ((PIO_CFGR_EVTSEL_Msk & ((value) << PIO_CFGR_EVTSEL_Pos)))
\r
234 #define PIO_CFGR_EVTSEL_FALLING (0x0u << 24) /**< \brief (PIO_CFGR) Event detection on input falling edge */
\r
235 #define PIO_CFGR_EVTSEL_RISING (0x1u << 24) /**< \brief (PIO_CFGR) Event detection on input rising edge */
\r
236 #define PIO_CFGR_EVTSEL_BOTH (0x2u << 24) /**< \brief (PIO_CFGR) Event detection on input both edge */
\r
237 #define PIO_CFGR_EVTSEL_LOW (0x3u << 24) /**< \brief (PIO_CFGR) Event detection on low level input */
\r
238 #define PIO_CFGR_EVTSEL_HIGH (0x4u << 24) /**< \brief (PIO_CFGR) Event detection on high level input */
\r
239 #define PIO_CFGR_PCFS (0x1u << 29) /**< \brief (PIO_CFGR) Physical Configuration Freeze Status */
\r
240 #define PIO_CFGR_PCFS_NOT_FROZEN (0x0u << 29) /**< \brief (PIO_CFGR) The fields are not frozen and can be written for this I/O line. */
\r
241 #define PIO_CFGR_PCFS_FROZEN (0x1u << 29) /**< \brief (PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */
\r
242 #define PIO_CFGR_ICFS (0x1u << 30) /**< \brief (PIO_CFGR) Interrupt Configuration Freeze Status */
\r
243 #define PIO_CFGR_ICFS_NOT_FROZEN (0x0u << 30) /**< \brief (PIO_CFGR) The fields are not frozen and can be written for this I/O line. */
\r
244 #define PIO_CFGR_ICFS_FROZEN (0x1u << 30) /**< \brief (PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */
\r
245 /* -------- PIO_PDSR : (PIO Offset: N/A) PIO Pin Data Status Register -------- */
\r
246 #define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Input Data Status */
\r
247 #define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Input Data Status */
\r
248 #define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Input Data Status */
\r
249 #define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Input Data Status */
\r
250 #define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Input Data Status */
\r
251 #define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Input Data Status */
\r
252 #define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Input Data Status */
\r
253 #define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Input Data Status */
\r
254 #define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Input Data Status */
\r
255 #define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Input Data Status */
\r
256 #define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Input Data Status */
\r
257 #define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Input Data Status */
\r
258 #define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Input Data Status */
\r
259 #define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Input Data Status */
\r
260 #define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Input Data Status */
\r
261 #define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Input Data Status */
\r
262 #define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Input Data Status */
\r
263 #define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Input Data Status */
\r
264 #define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Input Data Status */
\r
265 #define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Input Data Status */
\r
266 #define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Input Data Status */
\r
267 #define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Input Data Status */
\r
268 #define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Input Data Status */
\r
269 #define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Input Data Status */
\r
270 #define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Input Data Status */
\r
271 #define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Input Data Status */
\r
272 #define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Input Data Status */
\r
273 #define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Input Data Status */
\r
274 #define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Input Data Status */
\r
275 #define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Input Data Status */
\r
276 #define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Input Data Status */
\r
277 #define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Input Data Status */
\r
278 /* -------- PIO_LOCKSR : (PIO Offset: N/A) PIO Lock Status Register -------- */
\r
279 #define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */
\r
280 #define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */
\r
281 #define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */
\r
282 #define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */
\r
283 #define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */
\r
284 #define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */
\r
285 #define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */
\r
286 #define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */
\r
287 #define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */
\r
288 #define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */
\r
289 #define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */
\r
290 #define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */
\r
291 #define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */
\r
292 #define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */
\r
293 #define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */
\r
294 #define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */
\r
295 #define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */
\r
296 #define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */
\r
297 #define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */
\r
298 #define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */
\r
299 #define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */
\r
300 #define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */
\r
301 #define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */
\r
302 #define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */
\r
303 #define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */
\r
304 #define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */
\r
305 #define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */
\r
306 #define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */
\r
307 #define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */
\r
308 #define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */
\r
309 #define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */
\r
310 #define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */
\r
311 /* -------- PIO_SODR : (PIO Offset: N/A) PIO Set Output Data Register -------- */
\r
312 #define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
\r
313 #define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
\r
314 #define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
\r
315 #define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
\r
316 #define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
\r
317 #define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
\r
318 #define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
\r
319 #define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
\r
320 #define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
\r
321 #define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
\r
322 #define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
\r
323 #define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
\r
324 #define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
\r
325 #define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
\r
326 #define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
\r
327 #define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
\r
328 #define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
\r
329 #define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
\r
330 #define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
\r
331 #define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
\r
332 #define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
\r
333 #define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
\r
334 #define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
\r
335 #define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
\r
336 #define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
\r
337 #define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
\r
338 #define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
\r
339 #define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
\r
340 #define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
\r
341 #define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
\r
342 #define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
\r
343 #define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
\r
344 /* -------- PIO_CODR : (PIO Offset: N/A) PIO Clear Output Data Register -------- */
\r
345 #define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
\r
346 #define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
\r
347 #define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
\r
348 #define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
\r
349 #define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
\r
350 #define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
\r
351 #define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
\r
352 #define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
\r
353 #define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
\r
354 #define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
\r
355 #define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
\r
356 #define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
\r
357 #define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
\r
358 #define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
\r
359 #define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
\r
360 #define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
\r
361 #define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
\r
362 #define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
\r
363 #define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
\r
364 #define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
\r
365 #define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
\r
366 #define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
\r
367 #define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
\r
368 #define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
\r
369 #define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
\r
370 #define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
\r
371 #define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
\r
372 #define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
\r
373 #define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
\r
374 #define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
\r
375 #define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
\r
376 #define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
\r
377 /* -------- PIO_ODSR : (PIO Offset: N/A) PIO Output Data Status Register -------- */
\r
378 #define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
\r
379 #define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
\r
380 #define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
\r
381 #define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
\r
382 #define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
\r
383 #define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
\r
384 #define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
\r
385 #define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
\r
386 #define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
\r
387 #define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
\r
388 #define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
\r
389 #define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
\r
390 #define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
\r
391 #define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
\r
392 #define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
\r
393 #define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
\r
394 #define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
\r
395 #define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
\r
396 #define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
\r
397 #define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
\r
398 #define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
\r
399 #define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
\r
400 #define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
\r
401 #define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
\r
402 #define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
\r
403 #define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
\r
404 #define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
\r
405 #define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
\r
406 #define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
\r
407 #define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
\r
408 #define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
\r
409 #define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
\r
410 /* -------- PIO_IER : (PIO Offset: N/A) PIO Interrupt Enable Register -------- */
\r
411 #define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
412 #define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
413 #define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
414 #define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
415 #define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
416 #define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
417 #define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
418 #define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
419 #define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
420 #define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
421 #define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
422 #define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
423 #define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
424 #define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
425 #define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
426 #define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
427 #define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
428 #define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
429 #define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
430 #define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
431 #define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
432 #define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
433 #define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
434 #define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
435 #define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
436 #define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
437 #define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
438 #define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
439 #define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
440 #define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
441 #define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
442 #define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
443 /* -------- PIO_IDR : (PIO Offset: N/A) PIO Interrupt Disable Register -------- */
\r
444 #define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
445 #define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
446 #define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
447 #define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
448 #define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
449 #define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
450 #define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
451 #define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
452 #define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
453 #define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
454 #define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
455 #define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
456 #define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
457 #define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
458 #define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
459 #define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
460 #define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
461 #define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
462 #define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
463 #define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
464 #define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
465 #define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
466 #define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
467 #define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
468 #define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
469 #define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
470 #define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
471 #define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
472 #define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
473 #define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
474 #define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
475 #define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
476 /* -------- PIO_IMR : (PIO Offset: N/A) PIO Interrupt Mask Register -------- */
\r
477 #define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
478 #define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
479 #define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
480 #define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
481 #define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
482 #define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
483 #define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
484 #define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
485 #define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
486 #define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
487 #define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
488 #define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
489 #define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
490 #define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
491 #define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
492 #define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
493 #define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
494 #define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
495 #define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
496 #define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
497 #define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
498 #define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
499 #define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
500 #define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
501 #define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
502 #define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
503 #define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
504 #define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
505 #define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
506 #define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
507 #define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
508 #define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
509 /* -------- PIO_ISR : (PIO Offset: N/A) PIO Interrupt Status Register -------- */
\r
510 #define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
511 #define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
512 #define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
513 #define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
514 #define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
515 #define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
516 #define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
517 #define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
518 #define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
519 #define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
520 #define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
521 #define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
522 #define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
523 #define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
524 #define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
525 #define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
526 #define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
527 #define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
528 #define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
529 #define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
530 #define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
531 #define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
532 #define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
533 #define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
534 #define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
535 #define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
536 #define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
537 #define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
538 #define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
539 #define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
540 #define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
541 #define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
542 /* -------- PIO_IOFR : (PIO Offset: N/A) PIO I/O Freeze Register -------- */
\r
543 #define PIO_IOFR_FPHY (0x1u << 0) /**< \brief (PIO_IOFR) Freeze Physical Configuration */
\r
544 #define PIO_IOFR_FINT (0x1u << 1) /**< \brief (PIO_IOFR) Freeze Interrupt Configuration */
\r
545 #define PIO_IOFR_FRZKEY_Pos 8
\r
546 #define PIO_IOFR_FRZKEY_Msk (0xffffffu << PIO_IOFR_FRZKEY_Pos) /**< \brief (PIO_IOFR) Freeze Key */
\r
547 #define PIO_IOFR_FRZKEY(value) ((PIO_IOFR_FRZKEY_Msk & ((value) << PIO_IOFR_FRZKEY_Pos)))
\r
548 #define PIO_IOFR_FRZKEY_PASSWD (0x494F46u << 8) /**< \brief (PIO_IOFR) Writing any other value in this field aborts the write operation of the WPEN bit. */
\r
549 /* -------- PIO_WPMR : (PIO Offset: 0x5E0) PIO Write Protection Mode Register -------- */
\r
550 #define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */
\r
551 #define PIO_WPMR_WPKEY_Pos 8
\r
552 #define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */
\r
553 #define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
\r
554 #define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
\r
555 /* -------- PIO_WPSR : (PIO Offset: 0x5E4) PIO Write Protection Status Register -------- */
\r
556 #define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */
\r
557 #define PIO_WPSR_WPVSRC_Pos 8
\r
558 #define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */
\r
559 /* -------- PIO_VERSION : (PIO Offset: 0x5FC) Version Register -------- */
\r
560 #define PIO_VERSION_VERSION_Pos 0
\r
561 #define PIO_VERSION_VERSION_Msk (0xfffu << PIO_VERSION_VERSION_Pos) /**< \brief (PIO_VERSION) Hardware Module Version */
\r
562 #define PIO_VERSION_MFN_Pos 16
\r
563 #define PIO_VERSION_MFN_Msk (0x7u << PIO_VERSION_MFN_Pos) /**< \brief (PIO_VERSION) Metal Fix Number */
\r
564 /* -------- S_PIO_MSKR : (PIO Offset: N/A) Secure PIO Mask Register -------- */
\r
565 #define S_PIO_MSKR_MSK0 (0x1u << 0) /**< \brief (S_PIO_MSKR) PIO Line 0 Mask */
\r
566 #define S_PIO_MSKR_MSK0_DISABLED (0x0u << 0) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
567 #define S_PIO_MSKR_MSK0_ENABLED (0x1u << 0) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
568 #define S_PIO_MSKR_MSK1 (0x1u << 1) /**< \brief (S_PIO_MSKR) PIO Line 1 Mask */
\r
569 #define S_PIO_MSKR_MSK1_DISABLED (0x0u << 1) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
570 #define S_PIO_MSKR_MSK1_ENABLED (0x1u << 1) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
571 #define S_PIO_MSKR_MSK2 (0x1u << 2) /**< \brief (S_PIO_MSKR) PIO Line 2 Mask */
\r
572 #define S_PIO_MSKR_MSK2_DISABLED (0x0u << 2) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
573 #define S_PIO_MSKR_MSK2_ENABLED (0x1u << 2) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
574 #define S_PIO_MSKR_MSK3 (0x1u << 3) /**< \brief (S_PIO_MSKR) PIO Line 3 Mask */
\r
575 #define S_PIO_MSKR_MSK3_DISABLED (0x0u << 3) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
576 #define S_PIO_MSKR_MSK3_ENABLED (0x1u << 3) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
577 #define S_PIO_MSKR_MSK4 (0x1u << 4) /**< \brief (S_PIO_MSKR) PIO Line 4 Mask */
\r
578 #define S_PIO_MSKR_MSK4_DISABLED (0x0u << 4) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
579 #define S_PIO_MSKR_MSK4_ENABLED (0x1u << 4) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
580 #define S_PIO_MSKR_MSK5 (0x1u << 5) /**< \brief (S_PIO_MSKR) PIO Line 5 Mask */
\r
581 #define S_PIO_MSKR_MSK5_DISABLED (0x0u << 5) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
582 #define S_PIO_MSKR_MSK5_ENABLED (0x1u << 5) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
583 #define S_PIO_MSKR_MSK6 (0x1u << 6) /**< \brief (S_PIO_MSKR) PIO Line 6 Mask */
\r
584 #define S_PIO_MSKR_MSK6_DISABLED (0x0u << 6) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
585 #define S_PIO_MSKR_MSK6_ENABLED (0x1u << 6) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
586 #define S_PIO_MSKR_MSK7 (0x1u << 7) /**< \brief (S_PIO_MSKR) PIO Line 7 Mask */
\r
587 #define S_PIO_MSKR_MSK7_DISABLED (0x0u << 7) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
588 #define S_PIO_MSKR_MSK7_ENABLED (0x1u << 7) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
589 #define S_PIO_MSKR_MSK8 (0x1u << 8) /**< \brief (S_PIO_MSKR) PIO Line 8 Mask */
\r
590 #define S_PIO_MSKR_MSK8_DISABLED (0x0u << 8) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
591 #define S_PIO_MSKR_MSK8_ENABLED (0x1u << 8) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
592 #define S_PIO_MSKR_MSK9 (0x1u << 9) /**< \brief (S_PIO_MSKR) PIO Line 9 Mask */
\r
593 #define S_PIO_MSKR_MSK9_DISABLED (0x0u << 9) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
594 #define S_PIO_MSKR_MSK9_ENABLED (0x1u << 9) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
595 #define S_PIO_MSKR_MSK10 (0x1u << 10) /**< \brief (S_PIO_MSKR) PIO Line 10 Mask */
\r
596 #define S_PIO_MSKR_MSK10_DISABLED (0x0u << 10) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
597 #define S_PIO_MSKR_MSK10_ENABLED (0x1u << 10) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
598 #define S_PIO_MSKR_MSK11 (0x1u << 11) /**< \brief (S_PIO_MSKR) PIO Line 11 Mask */
\r
599 #define S_PIO_MSKR_MSK11_DISABLED (0x0u << 11) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
600 #define S_PIO_MSKR_MSK11_ENABLED (0x1u << 11) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
601 #define S_PIO_MSKR_MSK12 (0x1u << 12) /**< \brief (S_PIO_MSKR) PIO Line 12 Mask */
\r
602 #define S_PIO_MSKR_MSK12_DISABLED (0x0u << 12) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
603 #define S_PIO_MSKR_MSK12_ENABLED (0x1u << 12) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
604 #define S_PIO_MSKR_MSK13 (0x1u << 13) /**< \brief (S_PIO_MSKR) PIO Line 13 Mask */
\r
605 #define S_PIO_MSKR_MSK13_DISABLED (0x0u << 13) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
606 #define S_PIO_MSKR_MSK13_ENABLED (0x1u << 13) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
607 #define S_PIO_MSKR_MSK14 (0x1u << 14) /**< \brief (S_PIO_MSKR) PIO Line 14 Mask */
\r
608 #define S_PIO_MSKR_MSK14_DISABLED (0x0u << 14) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
609 #define S_PIO_MSKR_MSK14_ENABLED (0x1u << 14) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
610 #define S_PIO_MSKR_MSK15 (0x1u << 15) /**< \brief (S_PIO_MSKR) PIO Line 15 Mask */
\r
611 #define S_PIO_MSKR_MSK15_DISABLED (0x0u << 15) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
612 #define S_PIO_MSKR_MSK15_ENABLED (0x1u << 15) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
613 #define S_PIO_MSKR_MSK16 (0x1u << 16) /**< \brief (S_PIO_MSKR) PIO Line 16 Mask */
\r
614 #define S_PIO_MSKR_MSK16_DISABLED (0x0u << 16) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
615 #define S_PIO_MSKR_MSK16_ENABLED (0x1u << 16) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
616 #define S_PIO_MSKR_MSK17 (0x1u << 17) /**< \brief (S_PIO_MSKR) PIO Line 17 Mask */
\r
617 #define S_PIO_MSKR_MSK17_DISABLED (0x0u << 17) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
618 #define S_PIO_MSKR_MSK17_ENABLED (0x1u << 17) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
619 #define S_PIO_MSKR_MSK18 (0x1u << 18) /**< \brief (S_PIO_MSKR) PIO Line 18 Mask */
\r
620 #define S_PIO_MSKR_MSK18_DISABLED (0x0u << 18) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
621 #define S_PIO_MSKR_MSK18_ENABLED (0x1u << 18) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
622 #define S_PIO_MSKR_MSK19 (0x1u << 19) /**< \brief (S_PIO_MSKR) PIO Line 19 Mask */
\r
623 #define S_PIO_MSKR_MSK19_DISABLED (0x0u << 19) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
624 #define S_PIO_MSKR_MSK19_ENABLED (0x1u << 19) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
625 #define S_PIO_MSKR_MSK20 (0x1u << 20) /**< \brief (S_PIO_MSKR) PIO Line 20 Mask */
\r
626 #define S_PIO_MSKR_MSK20_DISABLED (0x0u << 20) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
627 #define S_PIO_MSKR_MSK20_ENABLED (0x1u << 20) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
628 #define S_PIO_MSKR_MSK21 (0x1u << 21) /**< \brief (S_PIO_MSKR) PIO Line 21 Mask */
\r
629 #define S_PIO_MSKR_MSK21_DISABLED (0x0u << 21) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
630 #define S_PIO_MSKR_MSK21_ENABLED (0x1u << 21) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
631 #define S_PIO_MSKR_MSK22 (0x1u << 22) /**< \brief (S_PIO_MSKR) PIO Line 22 Mask */
\r
632 #define S_PIO_MSKR_MSK22_DISABLED (0x0u << 22) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
633 #define S_PIO_MSKR_MSK22_ENABLED (0x1u << 22) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
634 #define S_PIO_MSKR_MSK23 (0x1u << 23) /**< \brief (S_PIO_MSKR) PIO Line 23 Mask */
\r
635 #define S_PIO_MSKR_MSK23_DISABLED (0x0u << 23) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
636 #define S_PIO_MSKR_MSK23_ENABLED (0x1u << 23) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
637 #define S_PIO_MSKR_MSK24 (0x1u << 24) /**< \brief (S_PIO_MSKR) PIO Line 24 Mask */
\r
638 #define S_PIO_MSKR_MSK24_DISABLED (0x0u << 24) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
639 #define S_PIO_MSKR_MSK24_ENABLED (0x1u << 24) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
640 #define S_PIO_MSKR_MSK25 (0x1u << 25) /**< \brief (S_PIO_MSKR) PIO Line 25 Mask */
\r
641 #define S_PIO_MSKR_MSK25_DISABLED (0x0u << 25) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
642 #define S_PIO_MSKR_MSK25_ENABLED (0x1u << 25) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
643 #define S_PIO_MSKR_MSK26 (0x1u << 26) /**< \brief (S_PIO_MSKR) PIO Line 26 Mask */
\r
644 #define S_PIO_MSKR_MSK26_DISABLED (0x0u << 26) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
645 #define S_PIO_MSKR_MSK26_ENABLED (0x1u << 26) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
646 #define S_PIO_MSKR_MSK27 (0x1u << 27) /**< \brief (S_PIO_MSKR) PIO Line 27 Mask */
\r
647 #define S_PIO_MSKR_MSK27_DISABLED (0x0u << 27) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
648 #define S_PIO_MSKR_MSK27_ENABLED (0x1u << 27) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
649 #define S_PIO_MSKR_MSK28 (0x1u << 28) /**< \brief (S_PIO_MSKR) PIO Line 28 Mask */
\r
650 #define S_PIO_MSKR_MSK28_DISABLED (0x0u << 28) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
651 #define S_PIO_MSKR_MSK28_ENABLED (0x1u << 28) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
652 #define S_PIO_MSKR_MSK29 (0x1u << 29) /**< \brief (S_PIO_MSKR) PIO Line 29 Mask */
\r
653 #define S_PIO_MSKR_MSK29_DISABLED (0x0u << 29) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
654 #define S_PIO_MSKR_MSK29_ENABLED (0x1u << 29) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
655 #define S_PIO_MSKR_MSK30 (0x1u << 30) /**< \brief (S_PIO_MSKR) PIO Line 30 Mask */
\r
656 #define S_PIO_MSKR_MSK30_DISABLED (0x0u << 30) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
657 #define S_PIO_MSKR_MSK30_ENABLED (0x1u << 30) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
658 #define S_PIO_MSKR_MSK31 (0x1u << 31) /**< \brief (S_PIO_MSKR) PIO Line 31 Mask */
\r
659 #define S_PIO_MSKR_MSK31_DISABLED (0x0u << 31) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
\r
660 #define S_PIO_MSKR_MSK31_ENABLED (0x1u << 31) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
\r
661 /* -------- S_PIO_CFGR : (PIO Offset: N/A) Secure PIO Configuration Register -------- */
\r
662 #define S_PIO_CFGR_FUNC_Pos 0
\r
663 #define S_PIO_CFGR_FUNC_Msk (0x7u << S_PIO_CFGR_FUNC_Pos) /**< \brief (S_PIO_CFGR) I/O Line Function */
\r
664 #define S_PIO_CFGR_FUNC(value) ((S_PIO_CFGR_FUNC_Msk & ((value) << S_PIO_CFGR_FUNC_Pos)))
\r
665 #define S_PIO_CFGR_FUNC_GPIO (0x0u << 0) /**< \brief (S_PIO_CFGR) Select the PIO mode for the selected I/O lines. */
\r
666 #define S_PIO_CFGR_FUNC_PERIPH_A (0x1u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral A for the selected I/O lines. */
\r
667 #define S_PIO_CFGR_FUNC_PERIPH_B (0x2u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral B for the selected I/O lines. */
\r
668 #define S_PIO_CFGR_FUNC_PERIPH_C (0x3u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral C for the selected I/O lines. */
\r
669 #define S_PIO_CFGR_FUNC_PERIPH_D (0x4u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral D for the selected I/O lines. */
\r
670 #define S_PIO_CFGR_FUNC_PERIPH_E (0x5u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral E for the selected I/O lines. */
\r
671 #define S_PIO_CFGR_FUNC_PERIPH_F (0x6u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral F for the selected I/O lines. */
\r
672 #define S_PIO_CFGR_FUNC_PERIPH_G (0x7u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral G for the selected I/O lines. */
\r
673 #define S_PIO_CFGR_DIR (0x1u << 8) /**< \brief (S_PIO_CFGR) Direction */
\r
674 #define S_PIO_CFGR_DIR_INPUT (0x0u << 8) /**< \brief (S_PIO_CFGR) The selected I/O lines are pure inputs. */
\r
675 #define S_PIO_CFGR_DIR_OUTPUT (0x1u << 8) /**< \brief (S_PIO_CFGR) The selected I/O lines are enabled in output. */
\r
676 #define S_PIO_CFGR_PUEN (0x1u << 9) /**< \brief (S_PIO_CFGR) Pull-Up Enable */
\r
677 #define S_PIO_CFGR_PUEN_DISABLED (0x0u << 9) /**< \brief (S_PIO_CFGR) Pull-Up is disabled for the selected I/O lines. */
\r
678 #define S_PIO_CFGR_PUEN_ENABLED (0x1u << 9) /**< \brief (S_PIO_CFGR) Pull-Up is enabled for the selected I/O lines. */
\r
679 #define S_PIO_CFGR_PDEN (0x1u << 10) /**< \brief (S_PIO_CFGR) Pull-Down Enable */
\r
680 #define S_PIO_CFGR_PDEN_DISABLED (0x0u << 10) /**< \brief (S_PIO_CFGR) Pull-Down is disabled for the selected I/O lines. */
\r
681 #define S_PIO_CFGR_PDEN_ENABLED (0x1u << 10) /**< \brief (S_PIO_CFGR) Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1). */
\r
682 #define S_PIO_CFGR_IFEN (0x1u << 12) /**< \brief (S_PIO_CFGR) Input Filter Enable */
\r
683 #define S_PIO_CFGR_IFEN_DISABLED (0x0u << 12) /**< \brief (S_PIO_CFGR) The input filter is disabled for the selected I/O lines. */
\r
684 #define S_PIO_CFGR_IFEN_ENABLED (0x1u << 12) /**< \brief (S_PIO_CFGR) The input filter is enabled for the selected I/O lines. */
\r
685 #define S_PIO_CFGR_IFSCEN (0x1u << 13) /**< \brief (S_PIO_CFGR) Input Filter Slow Clock Enable */
\r
686 #define S_PIO_CFGR_OPD (0x1u << 14) /**< \brief (S_PIO_CFGR) Open-Drain */
\r
687 #define S_PIO_CFGR_OPD_DISABLED (0x0u << 14) /**< \brief (S_PIO_CFGR) The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level. */
\r
688 #define S_PIO_CFGR_OPD_ENABLED (0x1u << 14) /**< \brief (S_PIO_CFGR) The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only. */
\r
689 #define S_PIO_CFGR_SCHMITT (0x1u << 15) /**< \brief (S_PIO_CFGR) Schmitt Trigger */
\r
690 #define S_PIO_CFGR_SCHMITT_ENABLED (0x0u << 15) /**< \brief (S_PIO_CFGR) Schmitt trigger is enabled for the selected I/O lines. */
\r
691 #define S_PIO_CFGR_SCHMITT_DISABLED (0x1u << 15) /**< \brief (S_PIO_CFGR) Schmitt trigger is disabled for the selected I/O lines. */
\r
692 #define S_PIO_CFGR_DRVSTR_Pos 16
\r
693 #define S_PIO_CFGR_DRVSTR_Msk (0x3u << S_PIO_CFGR_DRVSTR_Pos) /**< \brief (S_PIO_CFGR) */
\r
694 #define S_PIO_CFGR_DRVSTR(value) ((S_PIO_CFGR_DRVSTR_Msk & ((value) << S_PIO_CFGR_DRVSTR_Pos)))
\r
695 #define S_PIO_CFGR_EVTSEL_Pos 24
\r
696 #define S_PIO_CFGR_EVTSEL_Msk (0x7u << S_PIO_CFGR_EVTSEL_Pos) /**< \brief (S_PIO_CFGR) Event Selection */
\r
697 #define S_PIO_CFGR_EVTSEL(value) ((S_PIO_CFGR_EVTSEL_Msk & ((value) << S_PIO_CFGR_EVTSEL_Pos)))
\r
698 #define S_PIO_CFGR_EVTSEL_FALLING (0x0u << 24) /**< \brief (S_PIO_CFGR) Event detection on input falling edge */
\r
699 #define S_PIO_CFGR_EVTSEL_RISING (0x1u << 24) /**< \brief (S_PIO_CFGR) Event detection on input rising edge */
\r
700 #define S_PIO_CFGR_EVTSEL_BOTH (0x2u << 24) /**< \brief (S_PIO_CFGR) Event detection on input both edge */
\r
701 #define S_PIO_CFGR_EVTSEL_LOW (0x3u << 24) /**< \brief (S_PIO_CFGR) Event detection on low level input */
\r
702 #define S_PIO_CFGR_EVTSEL_HIGH (0x4u << 24) /**< \brief (S_PIO_CFGR) Event detection on high level input */
\r
703 #define S_PIO_CFGR_PCFS (0x1u << 29) /**< \brief (S_PIO_CFGR) Physical Configuration Freeze Status */
\r
704 #define S_PIO_CFGR_PCFS_NOT_FROZEN (0x0u << 29) /**< \brief (S_PIO_CFGR) The fields are not frozen and can be written for this I/O line. */
\r
705 #define S_PIO_CFGR_PCFS_FROZEN (0x1u << 29) /**< \brief (S_PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */
\r
706 #define S_PIO_CFGR_ICFS (0x1u << 30) /**< \brief (S_PIO_CFGR) Interrupt Configuration Freeze Status */
\r
707 #define S_PIO_CFGR_ICFS_NOT_FROZEN (0x0u << 30) /**< \brief (S_PIO_CFGR) The fields are not frozen and can be written for this I/O line. */
\r
708 #define S_PIO_CFGR_ICFS_FROZEN (0x1u << 30) /**< \brief (S_PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */
\r
709 /* -------- S_PIO_PDSR : (PIO Offset: N/A) Secure PIO Pin Data Status Register -------- */
\r
710 #define S_PIO_PDSR_P0 (0x1u << 0) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
711 #define S_PIO_PDSR_P1 (0x1u << 1) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
712 #define S_PIO_PDSR_P2 (0x1u << 2) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
713 #define S_PIO_PDSR_P3 (0x1u << 3) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
714 #define S_PIO_PDSR_P4 (0x1u << 4) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
715 #define S_PIO_PDSR_P5 (0x1u << 5) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
716 #define S_PIO_PDSR_P6 (0x1u << 6) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
717 #define S_PIO_PDSR_P7 (0x1u << 7) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
718 #define S_PIO_PDSR_P8 (0x1u << 8) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
719 #define S_PIO_PDSR_P9 (0x1u << 9) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
720 #define S_PIO_PDSR_P10 (0x1u << 10) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
721 #define S_PIO_PDSR_P11 (0x1u << 11) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
722 #define S_PIO_PDSR_P12 (0x1u << 12) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
723 #define S_PIO_PDSR_P13 (0x1u << 13) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
724 #define S_PIO_PDSR_P14 (0x1u << 14) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
725 #define S_PIO_PDSR_P15 (0x1u << 15) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
726 #define S_PIO_PDSR_P16 (0x1u << 16) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
727 #define S_PIO_PDSR_P17 (0x1u << 17) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
728 #define S_PIO_PDSR_P18 (0x1u << 18) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
729 #define S_PIO_PDSR_P19 (0x1u << 19) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
730 #define S_PIO_PDSR_P20 (0x1u << 20) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
731 #define S_PIO_PDSR_P21 (0x1u << 21) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
732 #define S_PIO_PDSR_P22 (0x1u << 22) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
733 #define S_PIO_PDSR_P23 (0x1u << 23) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
734 #define S_PIO_PDSR_P24 (0x1u << 24) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
735 #define S_PIO_PDSR_P25 (0x1u << 25) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
736 #define S_PIO_PDSR_P26 (0x1u << 26) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
737 #define S_PIO_PDSR_P27 (0x1u << 27) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
738 #define S_PIO_PDSR_P28 (0x1u << 28) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
739 #define S_PIO_PDSR_P29 (0x1u << 29) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
740 #define S_PIO_PDSR_P30 (0x1u << 30) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
741 #define S_PIO_PDSR_P31 (0x1u << 31) /**< \brief (S_PIO_PDSR) Input Data Status */
\r
742 /* -------- S_PIO_SODR : (PIO Offset: N/A) Secure PIO Set Output Data Register -------- */
\r
743 #define S_PIO_SODR_P0 (0x1u << 0) /**< \brief (S_PIO_SODR) Set Output Data */
\r
744 #define S_PIO_SODR_P1 (0x1u << 1) /**< \brief (S_PIO_SODR) Set Output Data */
\r
745 #define S_PIO_SODR_P2 (0x1u << 2) /**< \brief (S_PIO_SODR) Set Output Data */
\r
746 #define S_PIO_SODR_P3 (0x1u << 3) /**< \brief (S_PIO_SODR) Set Output Data */
\r
747 #define S_PIO_SODR_P4 (0x1u << 4) /**< \brief (S_PIO_SODR) Set Output Data */
\r
748 #define S_PIO_SODR_P5 (0x1u << 5) /**< \brief (S_PIO_SODR) Set Output Data */
\r
749 #define S_PIO_SODR_P6 (0x1u << 6) /**< \brief (S_PIO_SODR) Set Output Data */
\r
750 #define S_PIO_SODR_P7 (0x1u << 7) /**< \brief (S_PIO_SODR) Set Output Data */
\r
751 #define S_PIO_SODR_P8 (0x1u << 8) /**< \brief (S_PIO_SODR) Set Output Data */
\r
752 #define S_PIO_SODR_P9 (0x1u << 9) /**< \brief (S_PIO_SODR) Set Output Data */
\r
753 #define S_PIO_SODR_P10 (0x1u << 10) /**< \brief (S_PIO_SODR) Set Output Data */
\r
754 #define S_PIO_SODR_P11 (0x1u << 11) /**< \brief (S_PIO_SODR) Set Output Data */
\r
755 #define S_PIO_SODR_P12 (0x1u << 12) /**< \brief (S_PIO_SODR) Set Output Data */
\r
756 #define S_PIO_SODR_P13 (0x1u << 13) /**< \brief (S_PIO_SODR) Set Output Data */
\r
757 #define S_PIO_SODR_P14 (0x1u << 14) /**< \brief (S_PIO_SODR) Set Output Data */
\r
758 #define S_PIO_SODR_P15 (0x1u << 15) /**< \brief (S_PIO_SODR) Set Output Data */
\r
759 #define S_PIO_SODR_P16 (0x1u << 16) /**< \brief (S_PIO_SODR) Set Output Data */
\r
760 #define S_PIO_SODR_P17 (0x1u << 17) /**< \brief (S_PIO_SODR) Set Output Data */
\r
761 #define S_PIO_SODR_P18 (0x1u << 18) /**< \brief (S_PIO_SODR) Set Output Data */
\r
762 #define S_PIO_SODR_P19 (0x1u << 19) /**< \brief (S_PIO_SODR) Set Output Data */
\r
763 #define S_PIO_SODR_P20 (0x1u << 20) /**< \brief (S_PIO_SODR) Set Output Data */
\r
764 #define S_PIO_SODR_P21 (0x1u << 21) /**< \brief (S_PIO_SODR) Set Output Data */
\r
765 #define S_PIO_SODR_P22 (0x1u << 22) /**< \brief (S_PIO_SODR) Set Output Data */
\r
766 #define S_PIO_SODR_P23 (0x1u << 23) /**< \brief (S_PIO_SODR) Set Output Data */
\r
767 #define S_PIO_SODR_P24 (0x1u << 24) /**< \brief (S_PIO_SODR) Set Output Data */
\r
768 #define S_PIO_SODR_P25 (0x1u << 25) /**< \brief (S_PIO_SODR) Set Output Data */
\r
769 #define S_PIO_SODR_P26 (0x1u << 26) /**< \brief (S_PIO_SODR) Set Output Data */
\r
770 #define S_PIO_SODR_P27 (0x1u << 27) /**< \brief (S_PIO_SODR) Set Output Data */
\r
771 #define S_PIO_SODR_P28 (0x1u << 28) /**< \brief (S_PIO_SODR) Set Output Data */
\r
772 #define S_PIO_SODR_P29 (0x1u << 29) /**< \brief (S_PIO_SODR) Set Output Data */
\r
773 #define S_PIO_SODR_P30 (0x1u << 30) /**< \brief (S_PIO_SODR) Set Output Data */
\r
774 #define S_PIO_SODR_P31 (0x1u << 31) /**< \brief (S_PIO_SODR) Set Output Data */
\r
775 /* -------- S_PIO_CODR : (PIO Offset: N/A) Secure PIO Clear Output Data Register -------- */
\r
776 #define S_PIO_CODR_P0 (0x1u << 0) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
777 #define S_PIO_CODR_P1 (0x1u << 1) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
778 #define S_PIO_CODR_P2 (0x1u << 2) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
779 #define S_PIO_CODR_P3 (0x1u << 3) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
780 #define S_PIO_CODR_P4 (0x1u << 4) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
781 #define S_PIO_CODR_P5 (0x1u << 5) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
782 #define S_PIO_CODR_P6 (0x1u << 6) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
783 #define S_PIO_CODR_P7 (0x1u << 7) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
784 #define S_PIO_CODR_P8 (0x1u << 8) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
785 #define S_PIO_CODR_P9 (0x1u << 9) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
786 #define S_PIO_CODR_P10 (0x1u << 10) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
787 #define S_PIO_CODR_P11 (0x1u << 11) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
788 #define S_PIO_CODR_P12 (0x1u << 12) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
789 #define S_PIO_CODR_P13 (0x1u << 13) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
790 #define S_PIO_CODR_P14 (0x1u << 14) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
791 #define S_PIO_CODR_P15 (0x1u << 15) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
792 #define S_PIO_CODR_P16 (0x1u << 16) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
793 #define S_PIO_CODR_P17 (0x1u << 17) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
794 #define S_PIO_CODR_P18 (0x1u << 18) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
795 #define S_PIO_CODR_P19 (0x1u << 19) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
796 #define S_PIO_CODR_P20 (0x1u << 20) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
797 #define S_PIO_CODR_P21 (0x1u << 21) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
798 #define S_PIO_CODR_P22 (0x1u << 22) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
799 #define S_PIO_CODR_P23 (0x1u << 23) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
800 #define S_PIO_CODR_P24 (0x1u << 24) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
801 #define S_PIO_CODR_P25 (0x1u << 25) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
802 #define S_PIO_CODR_P26 (0x1u << 26) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
803 #define S_PIO_CODR_P27 (0x1u << 27) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
804 #define S_PIO_CODR_P28 (0x1u << 28) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
805 #define S_PIO_CODR_P29 (0x1u << 29) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
806 #define S_PIO_CODR_P30 (0x1u << 30) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
807 #define S_PIO_CODR_P31 (0x1u << 31) /**< \brief (S_PIO_CODR) Clear Output Data */
\r
808 /* -------- S_PIO_ODSR : (PIO Offset: N/A) Secure PIO Output Data Status Register -------- */
\r
809 #define S_PIO_ODSR_P0 (0x1u << 0) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
810 #define S_PIO_ODSR_P1 (0x1u << 1) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
811 #define S_PIO_ODSR_P2 (0x1u << 2) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
812 #define S_PIO_ODSR_P3 (0x1u << 3) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
813 #define S_PIO_ODSR_P4 (0x1u << 4) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
814 #define S_PIO_ODSR_P5 (0x1u << 5) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
815 #define S_PIO_ODSR_P6 (0x1u << 6) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
816 #define S_PIO_ODSR_P7 (0x1u << 7) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
817 #define S_PIO_ODSR_P8 (0x1u << 8) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
818 #define S_PIO_ODSR_P9 (0x1u << 9) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
819 #define S_PIO_ODSR_P10 (0x1u << 10) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
820 #define S_PIO_ODSR_P11 (0x1u << 11) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
821 #define S_PIO_ODSR_P12 (0x1u << 12) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
822 #define S_PIO_ODSR_P13 (0x1u << 13) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
823 #define S_PIO_ODSR_P14 (0x1u << 14) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
824 #define S_PIO_ODSR_P15 (0x1u << 15) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
825 #define S_PIO_ODSR_P16 (0x1u << 16) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
826 #define S_PIO_ODSR_P17 (0x1u << 17) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
827 #define S_PIO_ODSR_P18 (0x1u << 18) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
828 #define S_PIO_ODSR_P19 (0x1u << 19) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
829 #define S_PIO_ODSR_P20 (0x1u << 20) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
830 #define S_PIO_ODSR_P21 (0x1u << 21) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
831 #define S_PIO_ODSR_P22 (0x1u << 22) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
832 #define S_PIO_ODSR_P23 (0x1u << 23) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
833 #define S_PIO_ODSR_P24 (0x1u << 24) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
834 #define S_PIO_ODSR_P25 (0x1u << 25) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
835 #define S_PIO_ODSR_P26 (0x1u << 26) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
836 #define S_PIO_ODSR_P27 (0x1u << 27) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
837 #define S_PIO_ODSR_P28 (0x1u << 28) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
838 #define S_PIO_ODSR_P29 (0x1u << 29) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
839 #define S_PIO_ODSR_P30 (0x1u << 30) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
840 #define S_PIO_ODSR_P31 (0x1u << 31) /**< \brief (S_PIO_ODSR) Output Data Status */
\r
841 /* -------- S_PIO_IER : (PIO Offset: N/A) Secure PIO Interrupt Enable Register -------- */
\r
842 #define S_PIO_IER_P0 (0x1u << 0) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
843 #define S_PIO_IER_P1 (0x1u << 1) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
844 #define S_PIO_IER_P2 (0x1u << 2) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
845 #define S_PIO_IER_P3 (0x1u << 3) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
846 #define S_PIO_IER_P4 (0x1u << 4) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
847 #define S_PIO_IER_P5 (0x1u << 5) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
848 #define S_PIO_IER_P6 (0x1u << 6) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
849 #define S_PIO_IER_P7 (0x1u << 7) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
850 #define S_PIO_IER_P8 (0x1u << 8) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
851 #define S_PIO_IER_P9 (0x1u << 9) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
852 #define S_PIO_IER_P10 (0x1u << 10) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
853 #define S_PIO_IER_P11 (0x1u << 11) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
854 #define S_PIO_IER_P12 (0x1u << 12) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
855 #define S_PIO_IER_P13 (0x1u << 13) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
856 #define S_PIO_IER_P14 (0x1u << 14) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
857 #define S_PIO_IER_P15 (0x1u << 15) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
858 #define S_PIO_IER_P16 (0x1u << 16) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
859 #define S_PIO_IER_P17 (0x1u << 17) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
860 #define S_PIO_IER_P18 (0x1u << 18) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
861 #define S_PIO_IER_P19 (0x1u << 19) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
862 #define S_PIO_IER_P20 (0x1u << 20) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
863 #define S_PIO_IER_P21 (0x1u << 21) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
864 #define S_PIO_IER_P22 (0x1u << 22) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
865 #define S_PIO_IER_P23 (0x1u << 23) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
866 #define S_PIO_IER_P24 (0x1u << 24) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
867 #define S_PIO_IER_P25 (0x1u << 25) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
868 #define S_PIO_IER_P26 (0x1u << 26) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
869 #define S_PIO_IER_P27 (0x1u << 27) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
870 #define S_PIO_IER_P28 (0x1u << 28) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
871 #define S_PIO_IER_P29 (0x1u << 29) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
872 #define S_PIO_IER_P30 (0x1u << 30) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
873 #define S_PIO_IER_P31 (0x1u << 31) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
\r
874 /* -------- S_PIO_IDR : (PIO Offset: N/A) Secure PIO Interrupt Disable Register -------- */
\r
875 #define S_PIO_IDR_P0 (0x1u << 0) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
876 #define S_PIO_IDR_P1 (0x1u << 1) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
877 #define S_PIO_IDR_P2 (0x1u << 2) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
878 #define S_PIO_IDR_P3 (0x1u << 3) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
879 #define S_PIO_IDR_P4 (0x1u << 4) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
880 #define S_PIO_IDR_P5 (0x1u << 5) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
881 #define S_PIO_IDR_P6 (0x1u << 6) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
882 #define S_PIO_IDR_P7 (0x1u << 7) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
883 #define S_PIO_IDR_P8 (0x1u << 8) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
884 #define S_PIO_IDR_P9 (0x1u << 9) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
885 #define S_PIO_IDR_P10 (0x1u << 10) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
886 #define S_PIO_IDR_P11 (0x1u << 11) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
887 #define S_PIO_IDR_P12 (0x1u << 12) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
888 #define S_PIO_IDR_P13 (0x1u << 13) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
889 #define S_PIO_IDR_P14 (0x1u << 14) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
890 #define S_PIO_IDR_P15 (0x1u << 15) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
891 #define S_PIO_IDR_P16 (0x1u << 16) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
892 #define S_PIO_IDR_P17 (0x1u << 17) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
893 #define S_PIO_IDR_P18 (0x1u << 18) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
894 #define S_PIO_IDR_P19 (0x1u << 19) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
895 #define S_PIO_IDR_P20 (0x1u << 20) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
896 #define S_PIO_IDR_P21 (0x1u << 21) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
897 #define S_PIO_IDR_P22 (0x1u << 22) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
898 #define S_PIO_IDR_P23 (0x1u << 23) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
899 #define S_PIO_IDR_P24 (0x1u << 24) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
900 #define S_PIO_IDR_P25 (0x1u << 25) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
901 #define S_PIO_IDR_P26 (0x1u << 26) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
902 #define S_PIO_IDR_P27 (0x1u << 27) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
903 #define S_PIO_IDR_P28 (0x1u << 28) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
904 #define S_PIO_IDR_P29 (0x1u << 29) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
905 #define S_PIO_IDR_P30 (0x1u << 30) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
906 #define S_PIO_IDR_P31 (0x1u << 31) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
\r
907 /* -------- S_PIO_IMR : (PIO Offset: N/A) Secure PIO Interrupt Mask Register -------- */
\r
908 #define S_PIO_IMR_P0 (0x1u << 0) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
909 #define S_PIO_IMR_P1 (0x1u << 1) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
910 #define S_PIO_IMR_P2 (0x1u << 2) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
911 #define S_PIO_IMR_P3 (0x1u << 3) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
912 #define S_PIO_IMR_P4 (0x1u << 4) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
913 #define S_PIO_IMR_P5 (0x1u << 5) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
914 #define S_PIO_IMR_P6 (0x1u << 6) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
915 #define S_PIO_IMR_P7 (0x1u << 7) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
916 #define S_PIO_IMR_P8 (0x1u << 8) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
917 #define S_PIO_IMR_P9 (0x1u << 9) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
918 #define S_PIO_IMR_P10 (0x1u << 10) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
919 #define S_PIO_IMR_P11 (0x1u << 11) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
920 #define S_PIO_IMR_P12 (0x1u << 12) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
921 #define S_PIO_IMR_P13 (0x1u << 13) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
922 #define S_PIO_IMR_P14 (0x1u << 14) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
923 #define S_PIO_IMR_P15 (0x1u << 15) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
924 #define S_PIO_IMR_P16 (0x1u << 16) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
925 #define S_PIO_IMR_P17 (0x1u << 17) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
926 #define S_PIO_IMR_P18 (0x1u << 18) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
927 #define S_PIO_IMR_P19 (0x1u << 19) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
928 #define S_PIO_IMR_P20 (0x1u << 20) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
929 #define S_PIO_IMR_P21 (0x1u << 21) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
930 #define S_PIO_IMR_P22 (0x1u << 22) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
931 #define S_PIO_IMR_P23 (0x1u << 23) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
932 #define S_PIO_IMR_P24 (0x1u << 24) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
933 #define S_PIO_IMR_P25 (0x1u << 25) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
934 #define S_PIO_IMR_P26 (0x1u << 26) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
935 #define S_PIO_IMR_P27 (0x1u << 27) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
936 #define S_PIO_IMR_P28 (0x1u << 28) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
937 #define S_PIO_IMR_P29 (0x1u << 29) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
938 #define S_PIO_IMR_P30 (0x1u << 30) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
939 #define S_PIO_IMR_P31 (0x1u << 31) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
\r
940 /* -------- S_PIO_ISR : (PIO Offset: N/A) Secure PIO Interrupt Status Register -------- */
\r
941 #define S_PIO_ISR_P0 (0x1u << 0) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
942 #define S_PIO_ISR_P1 (0x1u << 1) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
943 #define S_PIO_ISR_P2 (0x1u << 2) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
944 #define S_PIO_ISR_P3 (0x1u << 3) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
945 #define S_PIO_ISR_P4 (0x1u << 4) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
946 #define S_PIO_ISR_P5 (0x1u << 5) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
947 #define S_PIO_ISR_P6 (0x1u << 6) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
948 #define S_PIO_ISR_P7 (0x1u << 7) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
949 #define S_PIO_ISR_P8 (0x1u << 8) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
950 #define S_PIO_ISR_P9 (0x1u << 9) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
951 #define S_PIO_ISR_P10 (0x1u << 10) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
952 #define S_PIO_ISR_P11 (0x1u << 11) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
953 #define S_PIO_ISR_P12 (0x1u << 12) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
954 #define S_PIO_ISR_P13 (0x1u << 13) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
955 #define S_PIO_ISR_P14 (0x1u << 14) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
956 #define S_PIO_ISR_P15 (0x1u << 15) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
957 #define S_PIO_ISR_P16 (0x1u << 16) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
958 #define S_PIO_ISR_P17 (0x1u << 17) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
959 #define S_PIO_ISR_P18 (0x1u << 18) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
960 #define S_PIO_ISR_P19 (0x1u << 19) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
961 #define S_PIO_ISR_P20 (0x1u << 20) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
962 #define S_PIO_ISR_P21 (0x1u << 21) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
963 #define S_PIO_ISR_P22 (0x1u << 22) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
964 #define S_PIO_ISR_P23 (0x1u << 23) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
965 #define S_PIO_ISR_P24 (0x1u << 24) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
966 #define S_PIO_ISR_P25 (0x1u << 25) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
967 #define S_PIO_ISR_P26 (0x1u << 26) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
968 #define S_PIO_ISR_P27 (0x1u << 27) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
969 #define S_PIO_ISR_P28 (0x1u << 28) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
970 #define S_PIO_ISR_P29 (0x1u << 29) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
971 #define S_PIO_ISR_P30 (0x1u << 30) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
972 #define S_PIO_ISR_P31 (0x1u << 31) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
\r
973 /* -------- S_PIO_SIONR : (PIO Offset: N/A) Secure PIO Set I/O Non-Secure Register -------- */
\r
974 #define S_PIO_SIONR_P0 (0x1u << 0) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
975 #define S_PIO_SIONR_P1 (0x1u << 1) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
976 #define S_PIO_SIONR_P2 (0x1u << 2) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
977 #define S_PIO_SIONR_P3 (0x1u << 3) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
978 #define S_PIO_SIONR_P4 (0x1u << 4) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
979 #define S_PIO_SIONR_P5 (0x1u << 5) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
980 #define S_PIO_SIONR_P6 (0x1u << 6) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
981 #define S_PIO_SIONR_P7 (0x1u << 7) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
982 #define S_PIO_SIONR_P8 (0x1u << 8) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
983 #define S_PIO_SIONR_P9 (0x1u << 9) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
984 #define S_PIO_SIONR_P10 (0x1u << 10) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
985 #define S_PIO_SIONR_P11 (0x1u << 11) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
986 #define S_PIO_SIONR_P12 (0x1u << 12) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
987 #define S_PIO_SIONR_P13 (0x1u << 13) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
988 #define S_PIO_SIONR_P14 (0x1u << 14) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
989 #define S_PIO_SIONR_P15 (0x1u << 15) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
990 #define S_PIO_SIONR_P16 (0x1u << 16) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
991 #define S_PIO_SIONR_P17 (0x1u << 17) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
992 #define S_PIO_SIONR_P18 (0x1u << 18) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
993 #define S_PIO_SIONR_P19 (0x1u << 19) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
994 #define S_PIO_SIONR_P20 (0x1u << 20) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
995 #define S_PIO_SIONR_P21 (0x1u << 21) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
996 #define S_PIO_SIONR_P22 (0x1u << 22) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
997 #define S_PIO_SIONR_P23 (0x1u << 23) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
998 #define S_PIO_SIONR_P24 (0x1u << 24) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
999 #define S_PIO_SIONR_P25 (0x1u << 25) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
1000 #define S_PIO_SIONR_P26 (0x1u << 26) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
1001 #define S_PIO_SIONR_P27 (0x1u << 27) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
1002 #define S_PIO_SIONR_P28 (0x1u << 28) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
1003 #define S_PIO_SIONR_P29 (0x1u << 29) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
1004 #define S_PIO_SIONR_P30 (0x1u << 30) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
1005 #define S_PIO_SIONR_P31 (0x1u << 31) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
\r
1006 /* -------- S_PIO_SIOSR : (PIO Offset: N/A) Secure PIO Set I/O Secure Register -------- */
\r
1007 #define S_PIO_SIOSR_P0 (0x1u << 0) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1008 #define S_PIO_SIOSR_P1 (0x1u << 1) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1009 #define S_PIO_SIOSR_P2 (0x1u << 2) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1010 #define S_PIO_SIOSR_P3 (0x1u << 3) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1011 #define S_PIO_SIOSR_P4 (0x1u << 4) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1012 #define S_PIO_SIOSR_P5 (0x1u << 5) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1013 #define S_PIO_SIOSR_P6 (0x1u << 6) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1014 #define S_PIO_SIOSR_P7 (0x1u << 7) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1015 #define S_PIO_SIOSR_P8 (0x1u << 8) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1016 #define S_PIO_SIOSR_P9 (0x1u << 9) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1017 #define S_PIO_SIOSR_P10 (0x1u << 10) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1018 #define S_PIO_SIOSR_P11 (0x1u << 11) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1019 #define S_PIO_SIOSR_P12 (0x1u << 12) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1020 #define S_PIO_SIOSR_P13 (0x1u << 13) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1021 #define S_PIO_SIOSR_P14 (0x1u << 14) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1022 #define S_PIO_SIOSR_P15 (0x1u << 15) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1023 #define S_PIO_SIOSR_P16 (0x1u << 16) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1024 #define S_PIO_SIOSR_P17 (0x1u << 17) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1025 #define S_PIO_SIOSR_P18 (0x1u << 18) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1026 #define S_PIO_SIOSR_P19 (0x1u << 19) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1027 #define S_PIO_SIOSR_P20 (0x1u << 20) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1028 #define S_PIO_SIOSR_P21 (0x1u << 21) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1029 #define S_PIO_SIOSR_P22 (0x1u << 22) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1030 #define S_PIO_SIOSR_P23 (0x1u << 23) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1031 #define S_PIO_SIOSR_P24 (0x1u << 24) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1032 #define S_PIO_SIOSR_P25 (0x1u << 25) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1033 #define S_PIO_SIOSR_P26 (0x1u << 26) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1034 #define S_PIO_SIOSR_P27 (0x1u << 27) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1035 #define S_PIO_SIOSR_P28 (0x1u << 28) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1036 #define S_PIO_SIOSR_P29 (0x1u << 29) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1037 #define S_PIO_SIOSR_P30 (0x1u << 30) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1038 #define S_PIO_SIOSR_P31 (0x1u << 31) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
\r
1039 /* -------- S_PIO_IOSSR : (PIO Offset: N/A) Secure PIO I/O Security Status Register -------- */
\r
1040 #define S_PIO_IOSSR_P0 (0x1u << 0) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1041 #define S_PIO_IOSSR_P0_SECURE (0x0u << 0) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1042 #define S_PIO_IOSSR_P0_NON_SECURE (0x1u << 0) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1043 #define S_PIO_IOSSR_P1 (0x1u << 1) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1044 #define S_PIO_IOSSR_P1_SECURE (0x0u << 1) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1045 #define S_PIO_IOSSR_P1_NON_SECURE (0x1u << 1) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1046 #define S_PIO_IOSSR_P2 (0x1u << 2) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1047 #define S_PIO_IOSSR_P2_SECURE (0x0u << 2) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1048 #define S_PIO_IOSSR_P2_NON_SECURE (0x1u << 2) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1049 #define S_PIO_IOSSR_P3 (0x1u << 3) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1050 #define S_PIO_IOSSR_P3_SECURE (0x0u << 3) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1051 #define S_PIO_IOSSR_P3_NON_SECURE (0x1u << 3) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1052 #define S_PIO_IOSSR_P4 (0x1u << 4) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1053 #define S_PIO_IOSSR_P4_SECURE (0x0u << 4) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1054 #define S_PIO_IOSSR_P4_NON_SECURE (0x1u << 4) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1055 #define S_PIO_IOSSR_P5 (0x1u << 5) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1056 #define S_PIO_IOSSR_P5_SECURE (0x0u << 5) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1057 #define S_PIO_IOSSR_P5_NON_SECURE (0x1u << 5) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1058 #define S_PIO_IOSSR_P6 (0x1u << 6) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1059 #define S_PIO_IOSSR_P6_SECURE (0x0u << 6) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1060 #define S_PIO_IOSSR_P6_NON_SECURE (0x1u << 6) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1061 #define S_PIO_IOSSR_P7 (0x1u << 7) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1062 #define S_PIO_IOSSR_P7_SECURE (0x0u << 7) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1063 #define S_PIO_IOSSR_P7_NON_SECURE (0x1u << 7) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1064 #define S_PIO_IOSSR_P8 (0x1u << 8) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1065 #define S_PIO_IOSSR_P8_SECURE (0x0u << 8) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1066 #define S_PIO_IOSSR_P8_NON_SECURE (0x1u << 8) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1067 #define S_PIO_IOSSR_P9 (0x1u << 9) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1068 #define S_PIO_IOSSR_P9_SECURE (0x0u << 9) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1069 #define S_PIO_IOSSR_P9_NON_SECURE (0x1u << 9) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1070 #define S_PIO_IOSSR_P10 (0x1u << 10) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1071 #define S_PIO_IOSSR_P10_SECURE (0x0u << 10) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1072 #define S_PIO_IOSSR_P10_NON_SECURE (0x1u << 10) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1073 #define S_PIO_IOSSR_P11 (0x1u << 11) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1074 #define S_PIO_IOSSR_P11_SECURE (0x0u << 11) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1075 #define S_PIO_IOSSR_P11_NON_SECURE (0x1u << 11) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1076 #define S_PIO_IOSSR_P12 (0x1u << 12) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1077 #define S_PIO_IOSSR_P12_SECURE (0x0u << 12) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1078 #define S_PIO_IOSSR_P12_NON_SECURE (0x1u << 12) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1079 #define S_PIO_IOSSR_P13 (0x1u << 13) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1080 #define S_PIO_IOSSR_P13_SECURE (0x0u << 13) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1081 #define S_PIO_IOSSR_P13_NON_SECURE (0x1u << 13) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1082 #define S_PIO_IOSSR_P14 (0x1u << 14) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1083 #define S_PIO_IOSSR_P14_SECURE (0x0u << 14) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1084 #define S_PIO_IOSSR_P14_NON_SECURE (0x1u << 14) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1085 #define S_PIO_IOSSR_P15 (0x1u << 15) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1086 #define S_PIO_IOSSR_P15_SECURE (0x0u << 15) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1087 #define S_PIO_IOSSR_P15_NON_SECURE (0x1u << 15) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1088 #define S_PIO_IOSSR_P16 (0x1u << 16) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1089 #define S_PIO_IOSSR_P16_SECURE (0x0u << 16) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1090 #define S_PIO_IOSSR_P16_NON_SECURE (0x1u << 16) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1091 #define S_PIO_IOSSR_P17 (0x1u << 17) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1092 #define S_PIO_IOSSR_P17_SECURE (0x0u << 17) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1093 #define S_PIO_IOSSR_P17_NON_SECURE (0x1u << 17) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1094 #define S_PIO_IOSSR_P18 (0x1u << 18) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1095 #define S_PIO_IOSSR_P18_SECURE (0x0u << 18) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1096 #define S_PIO_IOSSR_P18_NON_SECURE (0x1u << 18) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1097 #define S_PIO_IOSSR_P19 (0x1u << 19) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1098 #define S_PIO_IOSSR_P19_SECURE (0x0u << 19) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1099 #define S_PIO_IOSSR_P19_NON_SECURE (0x1u << 19) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1100 #define S_PIO_IOSSR_P20 (0x1u << 20) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1101 #define S_PIO_IOSSR_P20_SECURE (0x0u << 20) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1102 #define S_PIO_IOSSR_P20_NON_SECURE (0x1u << 20) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1103 #define S_PIO_IOSSR_P21 (0x1u << 21) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1104 #define S_PIO_IOSSR_P21_SECURE (0x0u << 21) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1105 #define S_PIO_IOSSR_P21_NON_SECURE (0x1u << 21) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1106 #define S_PIO_IOSSR_P22 (0x1u << 22) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1107 #define S_PIO_IOSSR_P22_SECURE (0x0u << 22) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1108 #define S_PIO_IOSSR_P22_NON_SECURE (0x1u << 22) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1109 #define S_PIO_IOSSR_P23 (0x1u << 23) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1110 #define S_PIO_IOSSR_P23_SECURE (0x0u << 23) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1111 #define S_PIO_IOSSR_P23_NON_SECURE (0x1u << 23) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1112 #define S_PIO_IOSSR_P24 (0x1u << 24) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1113 #define S_PIO_IOSSR_P24_SECURE (0x0u << 24) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1114 #define S_PIO_IOSSR_P24_NON_SECURE (0x1u << 24) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1115 #define S_PIO_IOSSR_P25 (0x1u << 25) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1116 #define S_PIO_IOSSR_P25_SECURE (0x0u << 25) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1117 #define S_PIO_IOSSR_P25_NON_SECURE (0x1u << 25) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1118 #define S_PIO_IOSSR_P26 (0x1u << 26) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1119 #define S_PIO_IOSSR_P26_SECURE (0x0u << 26) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1120 #define S_PIO_IOSSR_P26_NON_SECURE (0x1u << 26) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1121 #define S_PIO_IOSSR_P27 (0x1u << 27) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1122 #define S_PIO_IOSSR_P27_SECURE (0x0u << 27) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1123 #define S_PIO_IOSSR_P27_NON_SECURE (0x1u << 27) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1124 #define S_PIO_IOSSR_P28 (0x1u << 28) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1125 #define S_PIO_IOSSR_P28_SECURE (0x0u << 28) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1126 #define S_PIO_IOSSR_P28_NON_SECURE (0x1u << 28) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1127 #define S_PIO_IOSSR_P29 (0x1u << 29) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1128 #define S_PIO_IOSSR_P29_SECURE (0x0u << 29) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1129 #define S_PIO_IOSSR_P29_NON_SECURE (0x1u << 29) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1130 #define S_PIO_IOSSR_P30 (0x1u << 30) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1131 #define S_PIO_IOSSR_P30_SECURE (0x0u << 30) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1132 #define S_PIO_IOSSR_P30_NON_SECURE (0x1u << 30) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1133 #define S_PIO_IOSSR_P31 (0x1u << 31) /**< \brief (S_PIO_IOSSR) I/O Security Status */
\r
1134 #define S_PIO_IOSSR_P31_SECURE (0x0u << 31) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
\r
1135 #define S_PIO_IOSSR_P31_NON_SECURE (0x1u << 31) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
\r
1136 /* -------- S_PIO_IOFR : (PIO Offset: N/A) Secure PIO I/O Freeze Register -------- */
\r
1137 #define S_PIO_IOFR_FPHY (0x1u << 0) /**< \brief (S_PIO_IOFR) Freeze Physical Configuration */
\r
1138 #define S_PIO_IOFR_FINT (0x1u << 1) /**< \brief (S_PIO_IOFR) Freeze Interrupt Configuration */
\r
1139 #define S_PIO_IOFR_FRZKEY_Pos 8
\r
1140 #define S_PIO_IOFR_FRZKEY_Msk (0xffffffu << S_PIO_IOFR_FRZKEY_Pos) /**< \brief (S_PIO_IOFR) Freeze Key */
\r
1141 #define S_PIO_IOFR_FRZKEY(value) ((S_PIO_IOFR_FRZKEY_Msk & ((value) << S_PIO_IOFR_FRZKEY_Pos)))
\r
1142 #define S_PIO_IOFR_FRZKEY_PASSWD (0x494F46u << 8) /**< \brief (S_PIO_IOFR) Writing any other value in this field aborts the write operation of the WPEN bit. */
\r
1143 /* -------- S_PIO_SCDR : (PIO Offset: 0x1500) Secure PIO Slow Clock Divider Debouncing Register -------- */
\r
1144 #define S_PIO_SCDR_DIV_Pos 0
\r
1145 #define S_PIO_SCDR_DIV_Msk (0x3fffu << S_PIO_SCDR_DIV_Pos) /**< \brief (S_PIO_SCDR) Slow Clock Divider Selection for Debouncing */
\r
1146 #define S_PIO_SCDR_DIV(value) ((S_PIO_SCDR_DIV_Msk & ((value) << S_PIO_SCDR_DIV_Pos)))
\r
1147 /* -------- S_PIO_WPMR : (PIO Offset: 0x15E0) Secure PIO Write Protection Mode Register -------- */
\r
1148 #define S_PIO_WPMR_WPEN (0x1u << 0) /**< \brief (S_PIO_WPMR) Write Protection Enable */
\r
1149 #define S_PIO_WPMR_WPKEY_Pos 8
\r
1150 #define S_PIO_WPMR_WPKEY_Msk (0xffffffu << S_PIO_WPMR_WPKEY_Pos) /**< \brief (S_PIO_WPMR) Write Protection Key */
\r
1151 #define S_PIO_WPMR_WPKEY(value) ((S_PIO_WPMR_WPKEY_Msk & ((value) << S_PIO_WPMR_WPKEY_Pos)))
\r
1152 #define S_PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (S_PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
\r
1153 /* -------- S_PIO_WPSR : (PIO Offset: 0x15E4) Secure PIO Write Protection Status Register -------- */
\r
1154 #define S_PIO_WPSR_WPVS (0x1u << 0) /**< \brief (S_PIO_WPSR) Write Protection Violation Status */
\r
1155 #define S_PIO_WPSR_WPVSRC_Pos 8
\r
1156 #define S_PIO_WPSR_WPVSRC_Msk (0xffffu << S_PIO_WPSR_WPVSRC_Pos) /**< \brief (S_PIO_WPSR) Write Protection Violation Source */
\r
1161 #endif /* _SAMA5D2_PIO_COMPONENT_ */
\r
projects / freertos / blob