1 /* ---------------------------------------------------------------------------- */
\r
2 /* Atmel Microcontroller Software Support */
\r
3 /* SAM Software Package License */
\r
4 /* ---------------------------------------------------------------------------- */
\r
5 /* Copyright (c) 2015, Atmel Corporation */
\r
7 /* All rights reserved. */
\r
9 /* Redistribution and use in source and binary forms, with or without */
\r
10 /* modification, are permitted provided that the following condition is met: */
\r
12 /* - Redistributions of source code must retain the above copyright notice, */
\r
13 /* this list of conditions and the disclaimer below. */
\r
15 /* Atmel's name may not be used to endorse or promote products derived from */
\r
16 /* this software without specific prior written permission. */
\r
18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
\r
19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
\r
20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
\r
21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
\r
22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
\r
23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
\r
24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
\r
25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
\r
26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
\r
27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
\r
28 /* ---------------------------------------------------------------------------- */
\r
30 #ifndef _SAMA5D2_TC_COMPONENT_
\r
31 #define _SAMA5D2_TC_COMPONENT_
\r
33 /* ============================================================================= */
\r
34 /** SOFTWARE API DEFINITION FOR Timer Counter */
\r
35 /* ============================================================================= */
\r
36 /** \addtogroup SAMA5D2_TC Timer Counter */
\r
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
40 /** \brief TcChannel hardware registers */
\r
42 __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
\r
43 __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
\r
44 __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
\r
45 __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */
\r
46 __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
\r
47 __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
\r
48 __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
\r
49 __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
\r
50 __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
\r
51 __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
\r
52 __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
\r
53 __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
\r
54 __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */
\r
55 __I uint32_t Reserved1[3];
\r
57 /** \brief Tc hardware registers */
\r
58 #define TCCHANNEL_NUMBER 3
\r
60 TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
\r
61 __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */
\r
62 __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */
\r
63 __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
\r
64 __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
\r
65 __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
\r
66 __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
\r
67 __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
\r
68 __I uint32_t Reserved1[2];
\r
69 __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */
\r
70 __I uint32_t Reserved2[5];
\r
71 __I uint32_t TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */
\r
73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
74 /* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
\r
75 #define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
\r
76 #define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
\r
77 #define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
\r
78 /* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
\r
79 #define TC_CMR_TCCLKS_Pos 0
\r
80 #define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
\r
81 #define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)))
\r
82 #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal GCLK [TC_ID] clock signal (from PMC) */
\r
83 #define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal div8 clock signal (from PMC) */
\r
84 #define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal div32 clock signal (from PMC) */
\r
85 #define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal div128 clock signal (from PMC) */
\r
86 #define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal slow_clock clock signal (from PMC) */
\r
87 #define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
\r
88 #define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
\r
89 #define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
\r
90 #define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
\r
91 #define TC_CMR_BURST_Pos 4
\r
92 #define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
\r
93 #define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)))
\r
94 #define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
\r
95 #define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
\r
96 #define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
\r
97 #define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
\r
98 #define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
\r
99 #define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
\r
100 #define TC_CMR_ETRGEDG_Pos 8
\r
101 #define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
\r
102 #define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)))
\r
103 #define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
\r
104 #define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
\r
105 #define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
\r
106 #define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
\r
107 #define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
\r
108 #define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
\r
109 #define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
\r
110 #define TC_CMR_LDRA_Pos 16
\r
111 #define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
\r
112 #define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)))
\r
113 #define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
\r
114 #define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
\r
115 #define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
\r
116 #define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
\r
117 #define TC_CMR_LDRB_Pos 18
\r
118 #define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
\r
119 #define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)))
\r
120 #define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
\r
121 #define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
\r
122 #define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
\r
123 #define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
\r
124 #define TC_CMR_SBSMPLR_Pos 20
\r
125 #define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */
\r
126 #define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)))
\r
127 #define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */
\r
128 #define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */
\r
129 #define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */
\r
130 #define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */
\r
131 #define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */
\r
132 #define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
\r
133 #define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
\r
134 #define TC_CMR_EEVTEDG_Pos 8
\r
135 #define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
\r
136 #define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos)))
\r
137 #define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
\r
138 #define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
\r
139 #define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
\r
140 #define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
\r
141 #define TC_CMR_EEVT_Pos 10
\r
142 #define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
\r
143 #define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos)))
\r
144 #define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
\r
145 #define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
\r
146 #define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
\r
147 #define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
\r
148 #define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
\r
149 #define TC_CMR_WAVSEL_Pos 13
\r
150 #define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
\r
151 #define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos)))
\r
152 #define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
\r
153 #define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
\r
154 #define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
\r
155 #define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
\r
156 #define TC_CMR_ACPA_Pos 16
\r
157 #define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
\r
158 #define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos)))
\r
159 #define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
\r
160 #define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
\r
161 #define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
\r
162 #define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
\r
163 #define TC_CMR_ACPC_Pos 18
\r
164 #define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
\r
165 #define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos)))
\r
166 #define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
\r
167 #define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
\r
168 #define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
\r
169 #define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
\r
170 #define TC_CMR_AEEVT_Pos 20
\r
171 #define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
\r
172 #define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos)))
\r
173 #define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
\r
174 #define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
\r
175 #define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
\r
176 #define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
\r
177 #define TC_CMR_ASWTRG_Pos 22
\r
178 #define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
\r
179 #define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos)))
\r
180 #define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
\r
181 #define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
\r
182 #define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
\r
183 #define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
\r
184 #define TC_CMR_BCPB_Pos 24
\r
185 #define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
\r
186 #define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos)))
\r
187 #define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
\r
188 #define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
\r
189 #define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
\r
190 #define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
\r
191 #define TC_CMR_BCPC_Pos 26
\r
192 #define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
\r
193 #define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos)))
\r
194 #define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
\r
195 #define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
\r
196 #define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
\r
197 #define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
\r
198 #define TC_CMR_BEEVT_Pos 28
\r
199 #define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
\r
200 #define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos)))
\r
201 #define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
\r
202 #define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
\r
203 #define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
\r
204 #define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
\r
205 #define TC_CMR_BSWTRG_Pos 30
\r
206 #define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
\r
207 #define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos)))
\r
208 #define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
\r
209 #define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
\r
210 #define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
\r
211 #define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
\r
212 /* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
\r
213 #define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
\r
214 #define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */
\r
215 /* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */
\r
216 #define TC_RAB_RAB_Pos 0
\r
217 #define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */
\r
218 /* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
\r
219 #define TC_CV_CV_Pos 0
\r
220 #define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
\r
221 /* -------- TC_RA : (TC Offset: N/A) Register A -------- */
\r
222 #define TC_RA_RA_Pos 0
\r
223 #define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
\r
224 #define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
\r
225 /* -------- TC_RB : (TC Offset: N/A) Register B -------- */
\r
226 #define TC_RB_RB_Pos 0
\r
227 #define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
\r
228 #define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
\r
229 /* -------- TC_RC : (TC Offset: N/A) Register C -------- */
\r
230 #define TC_RC_RC_Pos 0
\r
231 #define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
\r
232 #define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
\r
233 /* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
\r
234 #define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */
\r
235 #define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */
\r
236 #define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */
\r
237 #define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */
\r
238 #define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */
\r
239 #define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */
\r
240 #define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */
\r
241 #define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */
\r
242 #define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
\r
243 #define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
\r
244 #define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
\r
245 /* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
\r
246 #define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
\r
247 #define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
\r
248 #define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
\r
249 #define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
\r
250 #define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
\r
251 #define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
\r
252 #define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
\r
253 #define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
\r
254 /* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
\r
255 #define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
\r
256 #define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
\r
257 #define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
\r
258 #define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
\r
259 #define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
\r
260 #define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
\r
261 #define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
\r
262 #define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
\r
263 /* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
\r
264 #define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
\r
265 #define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
\r
266 #define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
\r
267 #define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
\r
268 #define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
\r
269 #define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
\r
270 #define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
\r
271 #define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
\r
272 /* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */
\r
273 #define TC_EMR_TRIGSRCA_Pos 0
\r
274 #define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */
\r
275 #define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)))
\r
276 #define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */
\r
277 #define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */
\r
278 #define TC_EMR_TRIGSRCB_Pos 4
\r
279 #define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */
\r
280 #define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)))
\r
281 #define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */
\r
282 #define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */
\r
283 #define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */
\r
284 /* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
\r
285 #define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
\r
286 /* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
\r
287 #define TC_BMR_TC0XC0S_Pos 0
\r
288 #define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
\r
289 #define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)))
\r
290 #define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
\r
291 #define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
\r
292 #define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
\r
293 #define TC_BMR_TC1XC1S_Pos 2
\r
294 #define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
\r
295 #define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)))
\r
296 #define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
\r
297 #define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
\r
298 #define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
\r
299 #define TC_BMR_TC2XC2S_Pos 4
\r
300 #define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
\r
301 #define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)))
\r
302 #define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
\r
303 #define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */
\r
304 #define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
\r
305 #define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */
\r
306 #define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */
\r
307 #define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */
\r
308 #define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */
\r
309 #define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */
\r
310 #define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */
\r
311 #define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */
\r
312 #define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */
\r
313 #define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */
\r
314 #define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */
\r
315 #define TC_BMR_AUTOC (0x1u << 18) /**< \brief (TC_BMR) Auto-Correction of missing pulses */
\r
316 #define TC_BMR_AUTOC_DISABLED (0x0u << 18) /**< \brief (TC_BMR) The detection and auto-correction function is disabled. */
\r
317 #define TC_BMR_AUTOC_ENABLED (0x1u << 18) /**< \brief (TC_BMR) The detection and auto-correction function is enabled. */
\r
318 #define TC_BMR_MAXFILT_Pos 20
\r
319 #define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */
\r
320 #define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
\r
321 #define TC_BMR_MAXCMP_Pos 26
\r
322 #define TC_BMR_MAXCMP_Msk (0xfu << TC_BMR_MAXCMP_Pos) /**< \brief (TC_BMR) Maximum Consecutive Missing Pulses */
\r
323 #define TC_BMR_MAXCMP(value) ((TC_BMR_MAXCMP_Msk & ((value) << TC_BMR_MAXCMP_Pos)))
\r
324 /* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
\r
325 #define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */
\r
326 #define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */
\r
327 #define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */
\r
328 /* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
\r
329 #define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */
\r
330 #define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */
\r
331 #define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */
\r
332 /* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
\r
333 #define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */
\r
334 #define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */
\r
335 #define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */
\r
336 /* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
\r
337 #define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */
\r
338 #define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */
\r
339 #define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */
\r
340 #define TC_QISR_MPE (0x1u << 3) /**< \brief (TC_QISR) Consecutive Missing Pulse Error */
\r
341 #define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
\r
342 /* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
\r
343 #define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */
\r
344 #define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */
\r
345 /* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */
\r
346 #define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */
\r
347 #define TC_WPMR_WPKEY_Pos 8
\r
348 #define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */
\r
349 #define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
\r
350 #define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
\r
351 /* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */
\r
352 #define TC_VER_VERSION_Pos 0
\r
353 #define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos) /**< \brief (TC_VER) Version of the Hardware Module */
\r
354 #define TC_VER_MFN_Pos 16
\r
355 #define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos) /**< \brief (TC_VER) Metal Fix Number */
\r
360 #endif /* _SAMA5D2_TC_COMPONENT_ */
\r
projects / freertos / blob