1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2015, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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32 ;; Forward declaration of sections.
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33 SECTION IRQ_STACK:DATA:NOROOT(2)
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34 SECTION FIQ_STACK:DATA:NOROOT(2)
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35 SECTION ABT_STACK:DATA:NOROOT(2)
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36 SECTION UND_STACK:DATA:NOROOT(2)
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37 SECTION SYS_STACK:DATA:NOROOT(2)
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38 SECTION CSTACK:DATA:NOROOT(3)
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40 //------------------------------------------------------------------------------
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42 //------------------------------------------------------------------------------
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44 #define __ASSEMBLY__
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46 //------------------------------------------------------------------------------
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48 //------------------------------------------------------------------------------
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50 AT91C_BASE_AIC DEFINE 0xFC020000
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51 AT91C_BASE_SAIC DEFINE 0xF803C000
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53 AIC_EOICR DEFINE 0x38
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55 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
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57 ARM_MODE_ABT DEFINE 0x17
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58 ARM_MODE_FIQ DEFINE 0x11
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59 ARM_MODE_IRQ DEFINE 0x12
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60 ARM_MODE_SVC DEFINE 0x13
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61 ARM_MODE_SYS DEFINE 0x1F
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62 ARM_MODE_UND DEFINE 0x1B
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67 //------------------------------------------------------------------------------
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69 //------------------------------------------------------------------------------
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71 SECTION .vectors:CODE:NOROOT(2)
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73 PUBLIC _reset_vector
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74 PUBLIC __iar_program_start
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78 EXTERN undefined_instruction_irq_handler
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79 EXTERN prefetch_abort_irq_handler
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80 EXTERN data_abort_irq_handler
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81 EXTERN software_interrupt_irq_handler
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85 __iar_init$$done: ; The vector table is not needed
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86 ; until after copy initialization is done
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88 _reset_vector: ; Make this a DATA label, so that stack usage
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89 ; analysis doesn't consider it an uncalled fun
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93 ldr pc, reset_addr ; 0x0 Reset
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94 ldr pc, undefined_addr ; 0x4 Undefined instructions
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95 ldr pc, soft_int_addr ; 0x8 Software interrupt (SWI/SVC)
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96 ldr pc, prefetch_abt_addr ; 0xc Prefetch abort
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97 ldr pc, data_abt_addr ; 0x10 Data abort
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98 DCD 0 ; 0x14 RESERVED
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99 ldr pc, irq_addr ; 0x18 IRQ
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100 ldr pc, fiq_addr ; 0x1c FIQ
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104 ; All default handlers (except reset, irq and fiq) are
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105 ; defined as weak symbol definitions.
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106 ; If a handler is defined by the application it will take precedence.
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107 reset_addr: DCD __iar_program_start
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108 undefined_addr: DCD undefined_instruction_irq_handler
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109 soft_int_addr: DCD software_interrupt_irq_handler
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110 prefetch_abt_addr: DCD prefetch_abort_irq_handler
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111 data_abt_addr: DCD data_abort_irq_handler
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112 irq_addr: DCD irqHandler
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113 fiq_addr: DCD fiqHandler
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115 ;------------------------------------------------------------------------------
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116 ; Handles a fast interrupt request by branching to the address defined in the
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118 ;------------------------------------------------------------------------------
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119 SECTION .text:CODE:NOROOT(2)
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126 ; Write in the IVR to support Protect Mode
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128 ldr lr, =AT91C_BASE_SAIC
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129 ldr r0, [r14, #AIC_IVR]
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130 str lr, [r14, #AIC_IVR]
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132 ; Branch to interrupt handler in Supervisor mode
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134 msr CPSR_c, #ARM_MODE_SVC
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135 stmfd sp!, { r1-r3, r4, r12, lr}
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139 ldmia sp!, { r1-r3, r4, r12, lr}
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140 msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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142 ; Acknowledge interrupt
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144 ldr lr, =AT91C_BASE_SAIC
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145 str lr, [r14, #AIC_EOICR]
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147 ; Restore interrupt context and branch back to calling code
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151 ;------------------------------------------------------------------------------
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152 ; Handles incoming interrupt requests by branching to the corresponding
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153 ; handler, as defined in the AIC. Supports interrupt nesting.
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154 ;------------------------------------------------------------------------------
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155 SECTION .text:CODE:NOROOT(2)
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158 ; Save interrupt context on the stack to allow nesting
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163 stmfd sp!, {r0, lr}
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165 ; Write in the IVR to support Protect Mode
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167 ldr lr, =AT91C_BASE_AIC
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168 ldr r0, [r14, #AIC_IVR]
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169 str lr, [r14, #AIC_IVR]
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171 ; Branch to interrupt handler in Supervisor mode
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173 msr CPSR_c, #ARM_MODE_SVC
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174 stmfd sp!, { r1-r3, r4, r12, lr}
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176 ; Check for 8-byte alignment and save lr plus a
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177 ; word to indicate the stack adjustment used (0 or 4)
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181 stmfd sp!, {r1, lr}
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185 ldmia sp!, {r1, lr}
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188 ldmia sp!, { r1-r3, r4, r12, lr}
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189 msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
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191 ; Acknowledge interrupt
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193 ldr lr, =AT91C_BASE_AIC
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194 str lr, [r14, #AIC_EOICR]
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196 ; Restore interrupt context and branch back to calling code
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198 ldmia sp!, {r0, lr}
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202 //------------------------------------------------------------------------------
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203 /// Initializes the chip and branches to the main() function.
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204 //------------------------------------------------------------------------------
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206 SECTION .text:CODE:NOROOT(2)
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207 PUBLIC __iar_program_start
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209 EXTERN low_level_init
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210 REQUIRE _reset_vector
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212 EXTWEAK __iar_init_core
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213 EXTWEAK __iar_init_vfp
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217 __iar_program_start:
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222 ; Set up the fast interrupt stack pointer
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225 bic r0, r0, #MODE_MSK
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226 orr r0, r0, #ARM_MODE_FIQ
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228 ldr sp, =SFE(FIQ_STACK)
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231 ; Set up the normal interrupt stack pointer
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233 bic r0, r0, #MODE_MSK
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234 orr r0, r0, #ARM_MODE_IRQ
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236 ldr sp, =SFE(IRQ_STACK)
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239 ; Set up the abort mode stack pointer
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241 bic r0, r0, #MODE_MSK
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242 orr r0, r0, #ARM_MODE_ABT
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244 ldr sp, =SFE(ABT_STACK)
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247 ; Set up the undefined mode stack pointer
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249 bic r0, r0, #MODE_MSK
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250 orr r0, r0, #ARM_MODE_UND
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252 ldr sp, =SFE(UND_STACK)
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255 ; Set up the system mode stack pointer
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257 bic r0, r0, #MODE_MSK
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258 orr r0, r0, #ARM_MODE_SYS
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260 ldr sp, =SFE(SYS_STACK)
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263 ; Set up the supervisor mode stack pointer
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265 bic r0 ,r0, #MODE_MSK
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266 orr r0 ,r0, #ARM_MODE_SVC
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268 ldr sp, =SFE(CSTACK)
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271 ; Perform low-level initialization of the chip using low_level_init()
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273 ldr r0, =low_level_init
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276 ; Turn on core features assumed to be enabled
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277 FUNCALL __iar_program_start, __iar_init_core
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280 ;; Initialize VFP (if needed)
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281 FUNCALL __iar_program_start, __iar_init_vfp
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284 FUNCALL __iar_program_start, __cmain
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287 ;; Loop indefinitely when program is finished
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