1 /*******************************************************************************
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3 * Copyright 2013 Altera Corporation. All Rights Reserved. *
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5 * Redistribution and use in source and binary forms, with or without *
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6 * modification, are permitted provided that the following conditions are met: *
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8 * 1. Redistributions of source code must retain the above copyright notice, *
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9 * this list of conditions and the following disclaimer. *
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11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
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12 * this list of conditions and the following disclaimer in the documentation *
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13 * and/or other materials provided with the distribution. *
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15 * 3. The name of the author may not be used to endorse or promote products *
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16 * derived from this software without specific prior written permission. *
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18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
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19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
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20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
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21 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
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22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
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23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
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24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
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25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
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26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
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27 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
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29 *******************************************************************************/
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31 /* Altera - ALT_QSPI */
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33 #ifndef __ALTERA_ALT_QSPI_H__
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34 #define __ALTERA_ALT_QSPI_H__
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39 #endif /* __cplusplus */
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42 * Component : QSPI Flash Controller Module Registers - ALT_QSPI
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43 * QSPI Flash Controller Module Registers
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45 * Registers in the QSPI Flash Controller module accessible via its APB slave
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49 * Register : QSPI Configuration Register - cfg
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53 * Bits | Access | Reset | Description
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54 * :--------|:-------|:------|:-------------------------------------------
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55 * [0] | RW | 0x0 | QSPI Enable
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56 * [1] | RW | 0x0 | Clock Polarity
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57 * [2] | RW | 0x0 | Select Clock Phase
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58 * [6:3] | ??? | 0x0 | *UNDEFINED*
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59 * [7] | RW | 0x0 | Enable Direct Access Controller
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60 * [8] | RW | 0x0 | Legacy IP Mode Enable
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61 * [9] | RW | 0x0 | Peripheral select decode
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62 * [13:10] | RW | 0x0 | Peripheral Chip Select Lines
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63 * [14] | RW | 0x0 | Write Protect Flash Pin
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64 * [15] | RW | 0x0 | Enable DMA Peripheral Interface
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65 * [16] | RW | 0x0 | Enable AHB Address Re-mapping
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66 * [17] | RW | 0x0 | Enter XIP Mode on next READ
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67 * [18] | RW | 0x0 | Enter XIP Mode Immediately
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68 * [22:19] | RW | 0xf | Master Mode Baud Rate Divisor
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69 * [30:23] | ??? | 0x0 | *UNDEFINED*
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70 * [31] | R | 0x0 | Serial interface and QSPI pipeline is IDLE
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74 * Field : QSPI Enable - en
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76 * If this bit is disabled, the QSPI will finish the current transfer of the data
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77 * word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output
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78 * enables are inactive and all pins are set to input mode.
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80 * Field Enumeration Values:
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82 * Enum | Value | Description
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83 * :----------------------|:------|:-----------------
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84 * ALT_QSPI_CFG_EN_E_DIS | 0x0 | Disable the QSPI
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85 * ALT_QSPI_CFG_EN_E_EN | 0x1 | Enable the QSPI
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87 * Field Access Macros:
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91 * Enumerated value for register field ALT_QSPI_CFG_EN
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95 #define ALT_QSPI_CFG_EN_E_DIS 0x0
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97 * Enumerated value for register field ALT_QSPI_CFG_EN
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101 #define ALT_QSPI_CFG_EN_E_EN 0x1
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103 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */
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104 #define ALT_QSPI_CFG_EN_LSB 0
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105 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */
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106 #define ALT_QSPI_CFG_EN_MSB 0
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107 /* The width in bits of the ALT_QSPI_CFG_EN register field. */
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108 #define ALT_QSPI_CFG_EN_WIDTH 1
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109 /* The mask used to set the ALT_QSPI_CFG_EN register field value. */
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110 #define ALT_QSPI_CFG_EN_SET_MSK 0x00000001
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111 /* The mask used to clear the ALT_QSPI_CFG_EN register field value. */
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112 #define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
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113 /* The reset value of the ALT_QSPI_CFG_EN register field. */
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114 #define ALT_QSPI_CFG_EN_RESET 0x0
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115 /* Extracts the ALT_QSPI_CFG_EN field value from a register. */
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116 #define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
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117 /* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */
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118 #define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
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121 * Field : Clock Polarity - selclkpol
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123 * Controls spiclk modes of operation.
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125 * Field Enumeration Values:
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127 * Enum | Value | Description
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128 * :------------------------------|:------|:----------------------------
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129 * ALT_QSPI_CFG_SELCLKPOL_E_LOW | 0x1 | SPI clock is quiescent low
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130 * ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0 | SPI clock is quiescent high
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132 * Field Access Macros:
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136 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL
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138 * SPI clock is quiescent low
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140 #define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
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142 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL
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144 * SPI clock is quiescent high
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146 #define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
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148 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */
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149 #define ALT_QSPI_CFG_SELCLKPOL_LSB 1
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150 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */
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151 #define ALT_QSPI_CFG_SELCLKPOL_MSB 1
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152 /* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */
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153 #define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
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154 /* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */
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155 #define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
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156 /* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */
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157 #define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
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158 /* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */
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159 #define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
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160 /* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */
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161 #define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
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162 /* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */
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163 #define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
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166 * Field : Select Clock Phase - selclkphase
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168 * Selects whether the clock is in an active or inactive phase outside the SPI
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171 * Field Enumeration Values:
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173 * Enum | Value | Description
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174 * :---------------------------------|:------|:---------------------------
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175 * ALT_QSPI_CFG_SELCLKPHASE_E_ACT | 0x0 | SPI clock is quiescent low
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176 * ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1 | Clock Inactive
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178 * Field Access Macros:
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182 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE
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184 * SPI clock is quiescent low
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186 #define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0
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188 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE
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192 #define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1
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194 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */
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195 #define ALT_QSPI_CFG_SELCLKPHASE_LSB 2
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196 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */
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197 #define ALT_QSPI_CFG_SELCLKPHASE_MSB 2
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198 /* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */
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199 #define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
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200 /* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */
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201 #define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
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202 /* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */
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203 #define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
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204 /* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */
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205 #define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
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206 /* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */
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207 #define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
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208 /* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */
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209 #define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
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212 * Field : Enable Direct Access Controller - endiracc
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214 * If disabled, the Direct Access Controller becomes inactive once the current
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215 * transfer of the data word (FF_W) is complete. When the Direct Access Controller
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216 * and Indirect Access Controller are both disabled, all AHB requests are completed
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217 * with an error response.
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219 * Field Enumeration Values:
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221 * Enum | Value | Description
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222 * :----------------------------|:------|:---------------------------
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223 * ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0 | Disable Direct Access Ctrl
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224 * ALT_QSPI_CFG_ENDIRACC_E_EN | 0x1 | Enable Direct Access Ctrl
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226 * Field Access Macros:
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230 * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC
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232 * Disable Direct Access Ctrl
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234 #define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0
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236 * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC
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238 * Enable Direct Access Ctrl
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240 #define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1
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242 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */
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243 #define ALT_QSPI_CFG_ENDIRACC_LSB 7
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244 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */
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245 #define ALT_QSPI_CFG_ENDIRACC_MSB 7
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246 /* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */
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247 #define ALT_QSPI_CFG_ENDIRACC_WIDTH 1
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248 /* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */
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249 #define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
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250 /* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */
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251 #define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
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252 /* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */
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253 #define ALT_QSPI_CFG_ENDIRACC_RESET 0x0
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254 /* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */
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255 #define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
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256 /* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */
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257 #define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
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260 * Field : Legacy IP Mode Enable - enlegacyip
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262 * This bit can select the Direct Access Controller/Indirect Access Controller or
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263 * legacy mode.If legacy mode is selected, any write to the controller via the AHB
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264 * interface is serialized and sent to the FLASH device. Any valid AHB read will
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265 * pop the internal RX-FIFO, retrieving data that was forwarded by the external
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266 * FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and
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267 * controlled via the HSIZE input.
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269 * Field Enumeration Values:
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271 * Enum | Value | Description
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272 * :---------------------------------|:------|:--------------------------------------
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273 * ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1 | Legacy Mode
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274 * ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD | 0x0 | Use Direct/Indirect Access Controller
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276 * Field Access Macros:
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280 * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP
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284 #define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1
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286 * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP
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288 * Use Direct/Indirect Access Controller
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290 #define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0
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292 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */
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293 #define ALT_QSPI_CFG_ENLEGACYIP_LSB 8
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294 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */
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295 #define ALT_QSPI_CFG_ENLEGACYIP_MSB 8
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296 /* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */
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297 #define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
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298 /* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */
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299 #define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
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300 /* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */
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301 #define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
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302 /* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */
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303 #define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
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304 /* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */
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305 #define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
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306 /* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */
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307 #define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
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310 * Field : Peripheral select decode - perseldec
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312 * Select between '1 of 4 selects' or 'external 4-to-16 decode'. The
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313 * qspi_n_ss_out[3:0] output signals are controlled.
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315 * Field Enumeration Values:
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317 * Enum | Value | Description
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318 * :----------------------------------|:------|:----------------------------------
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319 * ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1 | Select external 4-to-16 decode
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320 * ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 | 0x0 | Selects 1 of 4 qspi_n_ss_out[3:0]
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322 * Field Access Macros:
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326 * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC
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328 * Select external 4-to-16 decode
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330 #define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
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332 * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC
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334 * Selects 1 of 4 qspi_n_ss_out[3:0]
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336 #define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
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338 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */
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339 #define ALT_QSPI_CFG_PERSELDEC_LSB 9
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340 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */
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341 #define ALT_QSPI_CFG_PERSELDEC_MSB 9
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342 /* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */
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343 #define ALT_QSPI_CFG_PERSELDEC_WIDTH 1
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344 /* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */
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345 #define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
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346 /* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */
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347 #define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
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348 /* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */
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349 #define ALT_QSPI_CFG_PERSELDEC_RESET 0x0
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350 /* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */
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351 #define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
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352 /* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */
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353 #define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
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356 * Field : Peripheral Chip Select Lines - percslines
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358 * Peripheral chip select line output decode type. As per perseldec, if perseldec =
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359 * 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The
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360 * asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0]
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361 * require an external 4 to 16 decoder.
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363 * Field Access Macros:
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366 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */
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367 #define ALT_QSPI_CFG_PERCSLINES_LSB 10
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368 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */
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369 #define ALT_QSPI_CFG_PERCSLINES_MSB 13
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370 /* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */
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371 #define ALT_QSPI_CFG_PERCSLINES_WIDTH 4
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372 /* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */
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373 #define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
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374 /* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */
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375 #define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
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376 /* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */
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377 #define ALT_QSPI_CFG_PERCSLINES_RESET 0x0
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378 /* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */
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379 #define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
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380 /* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */
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381 #define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
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384 * Field : Write Protect Flash Pin - wp
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386 * This bit controls the write protect pin of the flash devices. The signal
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387 * qspi_mo2_wpn needs to be resynchronized to the generated memory clock as
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390 * Field Enumeration Values:
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392 * Enum | Value | Description
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393 * :-----------------------------|:------|:----------------------
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394 * ALT_QSPI_CFG_WP_E_WRPROTON | 0x1 | Enable Write Protect
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395 * ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0 | Disable Write Protect
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397 * Field Access Macros:
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401 * Enumerated value for register field ALT_QSPI_CFG_WP
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403 * Enable Write Protect
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405 #define ALT_QSPI_CFG_WP_E_WRPROTON 0x1
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407 * Enumerated value for register field ALT_QSPI_CFG_WP
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409 * Disable Write Protect
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411 #define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
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413 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */
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414 #define ALT_QSPI_CFG_WP_LSB 14
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415 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */
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416 #define ALT_QSPI_CFG_WP_MSB 14
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417 /* The width in bits of the ALT_QSPI_CFG_WP register field. */
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418 #define ALT_QSPI_CFG_WP_WIDTH 1
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419 /* The mask used to set the ALT_QSPI_CFG_WP register field value. */
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420 #define ALT_QSPI_CFG_WP_SET_MSK 0x00004000
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421 /* The mask used to clear the ALT_QSPI_CFG_WP register field value. */
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422 #define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
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423 /* The reset value of the ALT_QSPI_CFG_WP register field. */
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424 #define ALT_QSPI_CFG_WP_RESET 0x0
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425 /* Extracts the ALT_QSPI_CFG_WP field value from a register. */
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426 #define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
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427 /* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */
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428 #define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
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431 * Field : Enable DMA Peripheral Interface - endma
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433 * Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer
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434 * requests via the DMA peripheral interface.
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436 * Field Enumeration Values:
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438 * Enum | Value | Description
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439 * :-------------------------|:------|:-----------------
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440 * ALT_QSPI_CFG_ENDMA_E_EN | 0x1 | Enable DMA Mode
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441 * ALT_QSPI_CFG_ENDMA_E_DIS | 0x0 | Disable DMA Mode
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443 * Field Access Macros:
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447 * Enumerated value for register field ALT_QSPI_CFG_ENDMA
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451 #define ALT_QSPI_CFG_ENDMA_E_EN 0x1
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453 * Enumerated value for register field ALT_QSPI_CFG_ENDMA
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457 #define ALT_QSPI_CFG_ENDMA_E_DIS 0x0
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459 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */
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460 #define ALT_QSPI_CFG_ENDMA_LSB 15
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461 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */
\r
462 #define ALT_QSPI_CFG_ENDMA_MSB 15
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463 /* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */
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464 #define ALT_QSPI_CFG_ENDMA_WIDTH 1
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465 /* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */
\r
466 #define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
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467 /* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */
\r
468 #define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
\r
469 /* The reset value of the ALT_QSPI_CFG_ENDMA register field. */
\r
470 #define ALT_QSPI_CFG_ENDMA_RESET 0x0
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471 /* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */
\r
472 #define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
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473 /* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */
\r
474 #define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
\r
477 * Field : Enable AHB Address Re-mapping - enahbremap
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479 * (Direct Access Mode Only) When enabled, the incoming AHB address will be adapted
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480 * and sent to the FLASH device as (address + N), where N is the value stored in
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481 * the remap address register.
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483 * Field Enumeration Values:
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485 * Enum | Value | Description
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486 * :------------------------------|:------|:-----------------------
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487 * ALT_QSPI_CFG_ENAHBREMAP_E_EN | 0x1 | Enable AHB Re-mapping
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488 * ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0 | Disable AHB Re-mapping
\r
490 * Field Access Macros:
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494 * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP
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496 * Enable AHB Re-mapping
\r
498 #define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1
\r
500 * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP
\r
502 * Disable AHB Re-mapping
\r
504 #define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0
\r
506 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */
\r
507 #define ALT_QSPI_CFG_ENAHBREMAP_LSB 16
\r
508 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */
\r
509 #define ALT_QSPI_CFG_ENAHBREMAP_MSB 16
\r
510 /* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */
\r
511 #define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
\r
512 /* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */
\r
513 #define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
\r
514 /* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */
\r
515 #define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
\r
516 /* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */
\r
517 #define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
\r
518 /* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */
\r
519 #define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
\r
520 /* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */
\r
521 #define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
\r
524 * Field : Enter XIP Mode on next READ - enterxipnextrd
\r
526 * If XIP is enabled, then setting to disabled will cause the controller to exit
\r
527 * XIP mode on the next READ instruction. If XIP is disabled, then setting to
\r
528 * enabled will inform the controller that the device is ready to enter XIP on the
\r
529 * next READ instruction. The controller will therefore send the appropriate
\r
530 * command sequence, including mode bits to cause the device to enter XIP mode. Use
\r
531 * this register after the controller has ensured the FLASH device has been
\r
532 * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit
\r
533 * should be set to 0. This will take effect in the attached device only AFTER the
\r
534 * next READ instruction is executed. Software should therefore ensure that at
\r
535 * least one READ instruction is requested after resetting this bit before it can
\r
536 * be sure XIP mode in the device is exited.
\r
538 * Field Enumeration Values:
\r
540 * Enum | Value | Description
\r
541 * :----------------------------------|:------|:----------------------------------------
\r
542 * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN | 0x1 | Enter XIP Mode on next READ instruction
\r
543 * ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0 | Exit XIP Mode on next READ instruction
\r
545 * Field Access Macros:
\r
549 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD
\r
551 * Enter XIP Mode on next READ instruction
\r
553 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1
\r
555 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD
\r
557 * Exit XIP Mode on next READ instruction
\r
559 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0
\r
561 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
\r
562 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
\r
563 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
\r
564 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
\r
565 /* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
\r
566 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
\r
567 /* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */
\r
568 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
\r
569 /* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */
\r
570 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
\r
571 /* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */
\r
572 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
\r
573 /* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */
\r
574 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
\r
575 /* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */
\r
576 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
\r
579 * Field : Enter XIP Mode Immediately - enterxipimm
\r
581 * If XIP is enabled, then setting to disabled will cause the controller to exit
\r
582 * XIP mode on the next READ instruction. If XIP is disabled, then setting enable
\r
583 * will operate the device in XIP mode immediately. Use this register when the
\r
584 * external device wakes up in XIP mode (as per the contents of its non- volatile
\r
585 * configuration register). The controller will assume the next READ instruction
\r
586 * will be passed to the device as an XIP instruction, and therefore will not
\r
587 * require the READ opcode to be transferred. Note: To exit XIP mode, this bit
\r
588 * should be set to 0. This will take effect in the attached device only after the
\r
589 * next READ instruction is executed. Software therefore should ensure that at
\r
590 * least one READ instruction is requested after resetting this bit in order to be
\r
591 * sure that XIP mode is exited.
\r
593 * Field Enumeration Values:
\r
595 * Enum | Value | Description
\r
596 * :-------------------------------|:------|:---------------------------------------
\r
597 * ALT_QSPI_CFG_ENTERXIPIMM_E_EN | 0x1 | Enter XIP Mode immediately
\r
598 * ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0 | Exit XIP Mode on next READ instruction
\r
600 * Field Access Macros:
\r
604 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM
\r
606 * Enter XIP Mode immediately
\r
608 #define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1
\r
610 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM
\r
612 * Exit XIP Mode on next READ instruction
\r
614 #define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0
\r
616 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
\r
617 #define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
\r
618 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
\r
619 #define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
\r
620 /* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
\r
621 #define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
\r
622 /* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */
\r
623 #define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
\r
624 /* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */
\r
625 #define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
\r
626 /* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */
\r
627 #define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
\r
628 /* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */
\r
629 #define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
\r
630 /* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */
\r
631 #define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
\r
634 * Field : Master Mode Baud Rate Divisor - bauddiv
\r
636 * SPI baud rate = ref_clk / (2 * baud_rate_divisor)
\r
638 * Field Enumeration Values:
\r
640 * Enum | Value | Description
\r
641 * :------------------------------|:------|:-----------------
\r
642 * ALT_QSPI_CFG_BAUDDIV_E_BAUD2 | 0x0 | Baud Rate Div/2
\r
643 * ALT_QSPI_CFG_BAUDDIV_E_BAUD4 | 0x1 | Baud Rate Div/4
\r
644 * ALT_QSPI_CFG_BAUDDIV_E_BAUD6 | 0x2 | Baud Rate Div/6
\r
645 * ALT_QSPI_CFG_BAUDDIV_E_BAUD8 | 0x3 | Baud Rate Div/8
\r
646 * ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4 | Baud Rate Div/10
\r
647 * ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5 | Baud Rate Div/12
\r
648 * ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6 | Baud Rate Div/14
\r
649 * ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7 | Baud Rate Div/16
\r
650 * ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8 | Baud Rate Div/18
\r
651 * ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9 | Baud Rate Div/20
\r
652 * ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa | Baud Rate Div/22
\r
653 * ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb | Baud Rate Div/24
\r
654 * ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc | Baud Rate Div/26
\r
655 * ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd | Baud Rate Div/28
\r
656 * ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe | Baud Rate Div/30
\r
657 * ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf | Baud Rate Div/32
\r
659 * Field Access Macros:
\r
663 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
667 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
\r
669 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
673 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
\r
675 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
679 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
\r
681 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
685 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
\r
687 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
691 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
\r
693 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
697 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
\r
699 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
703 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
\r
705 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
709 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
\r
711 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
715 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
\r
717 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
721 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
\r
723 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
727 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
\r
729 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
733 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
\r
735 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
739 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
\r
741 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
745 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
\r
747 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
751 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
\r
753 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV
\r
757 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
\r
759 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */
\r
760 #define ALT_QSPI_CFG_BAUDDIV_LSB 19
\r
761 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */
\r
762 #define ALT_QSPI_CFG_BAUDDIV_MSB 22
\r
763 /* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */
\r
764 #define ALT_QSPI_CFG_BAUDDIV_WIDTH 4
\r
765 /* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */
\r
766 #define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
\r
767 /* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */
\r
768 #define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
\r
769 /* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */
\r
770 #define ALT_QSPI_CFG_BAUDDIV_RESET 0xf
\r
771 /* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */
\r
772 #define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
\r
773 /* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */
\r
774 #define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
\r
777 * Field : Serial interface and QSPI pipeline is IDLE - idle
\r
779 * This is a STATUS read-only bit. Note this is a retimed signal, so there will be
\r
780 * some inherent delay on the generation of this status signal.
\r
782 * Field Enumeration Values:
\r
784 * Enum | Value | Description
\r
785 * :---------------------------|:------|:--------------
\r
786 * ALT_QSPI_CFG_IDLE_E_SET | 0x1 | Idle Mode
\r
787 * ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0 | Non-Idle Mode
\r
789 * Field Access Macros:
\r
793 * Enumerated value for register field ALT_QSPI_CFG_IDLE
\r
797 #define ALT_QSPI_CFG_IDLE_E_SET 0x1
\r
799 * Enumerated value for register field ALT_QSPI_CFG_IDLE
\r
803 #define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
\r
805 /* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */
\r
806 #define ALT_QSPI_CFG_IDLE_LSB 31
\r
807 /* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */
\r
808 #define ALT_QSPI_CFG_IDLE_MSB 31
\r
809 /* The width in bits of the ALT_QSPI_CFG_IDLE register field. */
\r
810 #define ALT_QSPI_CFG_IDLE_WIDTH 1
\r
811 /* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */
\r
812 #define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
\r
813 /* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */
\r
814 #define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
\r
815 /* The reset value of the ALT_QSPI_CFG_IDLE register field. */
\r
816 #define ALT_QSPI_CFG_IDLE_RESET 0x0
\r
817 /* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */
\r
818 #define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
\r
819 /* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */
\r
820 #define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
\r
822 #ifndef __ASSEMBLY__
\r
824 * WARNING: The C register and register group struct declarations are provided for
\r
825 * convenience and illustrative purposes. They should, however, be used with
\r
826 * caution as the C language standard provides no guarantees about the alignment or
\r
827 * atomicity of device memory accesses. The recommended practice for writing
\r
828 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
829 * alt_write_word() functions.
\r
831 * The struct declaration for register ALT_QSPI_CFG.
\r
833 struct ALT_QSPI_CFG_s
\r
835 uint32_t en : 1; /* QSPI Enable */
\r
836 uint32_t selclkpol : 1; /* Clock Polarity */
\r
837 uint32_t selclkphase : 1; /* Select Clock Phase */
\r
838 uint32_t : 4; /* *UNDEFINED* */
\r
839 uint32_t endiracc : 1; /* Enable Direct Access Controller */
\r
840 uint32_t enlegacyip : 1; /* Legacy IP Mode Enable */
\r
841 uint32_t perseldec : 1; /* Peripheral select decode */
\r
842 uint32_t percslines : 4; /* Peripheral Chip Select Lines */
\r
843 uint32_t wp : 1; /* Write Protect Flash Pin */
\r
844 uint32_t endma : 1; /* Enable DMA Peripheral Interface */
\r
845 uint32_t enahbremap : 1; /* Enable AHB Address Re-mapping */
\r
846 uint32_t enterxipnextrd : 1; /* Enter XIP Mode on next READ */
\r
847 uint32_t enterxipimm : 1; /* Enter XIP Mode Immediately */
\r
848 uint32_t bauddiv : 4; /* Master Mode Baud Rate Divisor */
\r
849 uint32_t : 8; /* *UNDEFINED* */
\r
850 const uint32_t idle : 1; /* Serial interface and QSPI pipeline is IDLE */
\r
853 /* The typedef declaration for register ALT_QSPI_CFG. */
\r
854 typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t;
\r
855 #endif /* __ASSEMBLY__ */
\r
857 /* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */
\r
858 #define ALT_QSPI_CFG_OFST 0x0
\r
861 * Register : Device Read Instruction Register - devrd
\r
865 * Bits | Access | Reset | Description
\r
866 * :--------|:-------|:------|:----------------------------
\r
867 * [7:0] | RW | 0x3 | Read Opcode in non-XIP mode
\r
868 * [9:8] | RW | 0x0 | Instruction Transfer Width
\r
869 * [11:10] | ??? | 0x0 | *UNDEFINED*
\r
870 * [13:12] | RW | 0x0 | Address Transfer Width
\r
871 * [15:14] | ??? | 0x0 | *UNDEFINED*
\r
872 * [17:16] | RW | 0x0 | Data Transfer Width
\r
873 * [19:18] | ??? | 0x0 | *UNDEFINED*
\r
874 * [20] | RW | 0x0 | Mode Bit Enable
\r
875 * [23:21] | ??? | 0x0 | *UNDEFINED*
\r
876 * [28:24] | RW | 0x0 | Dummy Read Clock Cycles
\r
877 * [31:29] | ??? | 0x0 | *UNDEFINED*
\r
881 * Field : Read Opcode in non-XIP mode - rdopcode
\r
883 * Read Opcode to use when not in XIP mode
\r
885 * Field Enumeration Values:
\r
887 * Enum | Value | Description
\r
888 * :---------------------------------|:------|:----------------------------
\r
889 * ALT_QSPI_DEVRD_RDOPCODE_E_RD | 0x3 | Read Opcode in Non-XIP mode
\r
890 * ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb | Fast Read in Non-XIP mode
\r
892 * Field Access Macros:
\r
896 * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
\r
898 * Read Opcode in Non-XIP mode
\r
900 #define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3
\r
902 * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
\r
904 * Fast Read in Non-XIP mode
\r
906 #define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb
\r
908 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */
\r
909 #define ALT_QSPI_DEVRD_RDOPCODE_LSB 0
\r
910 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */
\r
911 #define ALT_QSPI_DEVRD_RDOPCODE_MSB 7
\r
912 /* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */
\r
913 #define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
\r
914 /* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */
\r
915 #define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
\r
916 /* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */
\r
917 #define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
\r
918 /* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */
\r
919 #define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
\r
920 /* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */
\r
921 #define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
\r
922 /* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */
\r
923 #define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
\r
926 * Field : Instruction Transfer Width - instwidth
\r
928 * Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions
\r
929 * sent to SPI flash device (not just read instructions).
\r
931 * Field Enumeration Values:
\r
933 * Enum | Value | Description
\r
934 * :----------------------------------|:------|:-------------------------------------------------
\r
935 * ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0 | Instruction transferred on DQ0. Supported by all
\r
936 * : | | SPI flash devices.
\r
937 * ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL | 0x1 | Instruction transferred on DQ0 and DQ1.
\r
938 * : | | Supported by all SPI flash devices that support
\r
939 * : | | the Dual SP (DIO-SPI) Protocol.
\r
940 * ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD | 0x2 | Instruction transferred on DQ0, DQ1, DQ2, and
\r
941 * : | | DQ3. Supported by all SPI flash devices that
\r
942 * : | | support the Quad SP (QIO-SPI) Protocol.
\r
944 * Field Access Macros:
\r
948 * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
\r
950 * Instruction transferred on DQ0. Supported by all SPI flash devices.
\r
952 #define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
\r
954 * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
\r
956 * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that
\r
957 * support the Dual SP (DIO-SPI) Protocol.
\r
959 #define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
\r
961 * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
\r
963 * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash
\r
964 * devices that support the Quad SP (QIO-SPI) Protocol.
\r
966 #define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
\r
968 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
\r
969 #define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
\r
970 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
\r
971 #define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
\r
972 /* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
\r
973 #define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
\r
974 /* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */
\r
975 #define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
\r
976 /* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */
\r
977 #define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
\r
978 /* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */
\r
979 #define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
\r
980 /* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */
\r
981 #define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
\r
982 /* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */
\r
983 #define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
\r
986 * Field : Address Transfer Width - addrwidth
\r
988 * Sets read address transfer width (1, 2, or 4 bits).
\r
990 * Field Enumeration Values:
\r
992 * Enum | Value | Description
\r
993 * :----------------------------------|:------|:-------------------------------------------------
\r
994 * ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0 | Read address transferred on DQ0. Supported by
\r
995 * : | | all SPI flash devices
\r
996 * ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1.
\r
997 * : | | Supported by some SPI flash devices that support
\r
998 * : | | the Extended SPI Protocol and by all SPI flash
\r
999 * : | | devices that support the Dual SP (DIO-SPI)
\r
1000 * : | | Protocol.
\r
1001 * ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and
\r
1002 * : | | DQ3. Supported by some SPI flash devices that
\r
1003 * : | | support the Extended SPI Protocol and by all SPI
\r
1004 * : | | flash devices that support the Quad SP (QIO-SPI)
\r
1005 * : | | Protocol.
\r
1007 * Field Access Macros:
\r
1011 * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
\r
1013 * Read address transferred on DQ0. Supported by all SPI flash devices
\r
1015 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
\r
1017 * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
\r
1019 * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices
\r
1020 * that support the Extended SPI Protocol and by all SPI flash devices that support
\r
1021 * the Dual SP (DIO-SPI) Protocol.
\r
1023 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
\r
1025 * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
\r
1027 * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
\r
1028 * devices that support the Extended SPI Protocol and by all SPI flash devices that
\r
1029 * support the Quad SP (QIO-SPI) Protocol.
\r
1031 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
\r
1033 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
\r
1034 #define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
\r
1035 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
\r
1036 #define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
\r
1037 /* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
\r
1038 #define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
\r
1039 /* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */
\r
1040 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
\r
1041 /* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */
\r
1042 #define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
\r
1043 /* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */
\r
1044 #define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
\r
1045 /* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */
\r
1046 #define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
\r
1047 /* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */
\r
1048 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
\r
1051 * Field : Data Transfer Width - datawidth
\r
1053 * Sets read data transfer width (1, 2, or 4 bits).
\r
1055 * Field Enumeration Values:
\r
1057 * Enum | Value | Description
\r
1058 * :----------------------------------|:------|:-------------------------------------------------
\r
1059 * ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0 | Read data transferred on DQ0. Supported by all
\r
1060 * : | | SPI flash devices
\r
1061 * ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported
\r
1062 * : | | by some SPI flash devices that support the
\r
1063 * : | | Extended SPI Protocol and by all SPI flash
\r
1064 * : | | devices that support the Dual SP (DIO-SPI)
\r
1065 * : | | Protocol.
\r
1066 * ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3.
\r
1067 * : | | Supported by some SPI flash devices that support
\r
1068 * : | | the Extended SPI Protocol and by all SPI flash
\r
1069 * : | | devices that support the Quad SP (QIO-SPI)
\r
1070 * : | | Protocol.
\r
1072 * Field Access Macros:
\r
1076 * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
\r
1078 * Read data transferred on DQ0. Supported by all SPI flash devices
\r
1080 #define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
\r
1082 * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
\r
1084 * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that
\r
1085 * support the Extended SPI Protocol and by all SPI flash devices that support the
\r
1086 * Dual SP (DIO-SPI) Protocol.
\r
1088 #define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
\r
1090 * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
\r
1092 * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
\r
1093 * devices that support the Extended SPI Protocol and by all SPI flash devices that
\r
1094 * support the Quad SP (QIO-SPI) Protocol.
\r
1096 #define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
\r
1098 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
\r
1099 #define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
\r
1100 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
\r
1101 #define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
\r
1102 /* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
\r
1103 #define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
\r
1104 /* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */
\r
1105 #define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
\r
1106 /* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */
\r
1107 #define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
\r
1108 /* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */
\r
1109 #define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
\r
1110 /* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */
\r
1111 #define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
\r
1112 /* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */
\r
1113 #define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
\r
1116 * Field : Mode Bit Enable - enmodebits
\r
1118 * If this bit is set, the mode bits as defined in the Mode Bit Configuration
\r
1119 * register are sent following the address bytes.
\r
1121 * Field Enumeration Values:
\r
1123 * Enum | Value | Description
\r
1124 * :-----------------------------------|:------|:-------------------------------
\r
1125 * ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0 | No Order
\r
1126 * ALT_QSPI_DEVRD_ENMODBITS_E_ORDER | 0x1 | Mode Bits follow address bytes
\r
1128 * Field Access Macros:
\r
1132 * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS
\r
1136 #define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0
\r
1138 * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS
\r
1140 * Mode Bits follow address bytes
\r
1142 #define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1
\r
1144 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */
\r
1145 #define ALT_QSPI_DEVRD_ENMODBITS_LSB 20
\r
1146 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */
\r
1147 #define ALT_QSPI_DEVRD_ENMODBITS_MSB 20
\r
1148 /* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */
\r
1149 #define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1
\r
1150 /* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */
\r
1151 #define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000
\r
1152 /* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */
\r
1153 #define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff
\r
1154 /* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */
\r
1155 #define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0
\r
1156 /* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */
\r
1157 #define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20)
\r
1158 /* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */
\r
1159 #define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000)
\r
1162 * Field : Dummy Read Clock Cycles - dummyrdclks
\r
1164 * Number of dummy clock cycles required by device for read instruction.
\r
1166 * Field Access Macros:
\r
1169 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
\r
1170 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
\r
1171 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
\r
1172 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
\r
1173 /* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
\r
1174 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
\r
1175 /* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */
\r
1176 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
\r
1177 /* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */
\r
1178 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
\r
1179 /* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */
\r
1180 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
\r
1181 /* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */
\r
1182 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
\r
1183 /* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */
\r
1184 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
\r
1186 #ifndef __ASSEMBLY__
\r
1188 * WARNING: The C register and register group struct declarations are provided for
\r
1189 * convenience and illustrative purposes. They should, however, be used with
\r
1190 * caution as the C language standard provides no guarantees about the alignment or
\r
1191 * atomicity of device memory accesses. The recommended practice for writing
\r
1192 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
1193 * alt_write_word() functions.
\r
1195 * The struct declaration for register ALT_QSPI_DEVRD.
\r
1197 struct ALT_QSPI_DEVRD_s
\r
1199 uint32_t rdopcode : 8; /* Read Opcode in non-XIP mode */
\r
1200 uint32_t instwidth : 2; /* Instruction Transfer Width */
\r
1201 uint32_t : 2; /* *UNDEFINED* */
\r
1202 uint32_t addrwidth : 2; /* Address Transfer Width */
\r
1203 uint32_t : 2; /* *UNDEFINED* */
\r
1204 uint32_t datawidth : 2; /* Data Transfer Width */
\r
1205 uint32_t : 2; /* *UNDEFINED* */
\r
1206 uint32_t enmodebits : 1; /* Mode Bit Enable */
\r
1207 uint32_t : 3; /* *UNDEFINED* */
\r
1208 uint32_t dummyrdclks : 5; /* Dummy Read Clock Cycles */
\r
1209 uint32_t : 3; /* *UNDEFINED* */
\r
1212 /* The typedef declaration for register ALT_QSPI_DEVRD. */
\r
1213 typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t;
\r
1214 #endif /* __ASSEMBLY__ */
\r
1216 /* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */
\r
1217 #define ALT_QSPI_DEVRD_OFST 0x4
\r
1220 * Register : Device Write Instruction Register - devwr
\r
1224 * Bits | Access | Reset | Description
\r
1225 * :--------|:-------|:------|:-------------------------
\r
1226 * [7:0] | RW | 0x2 | Write Opcode
\r
1227 * [11:8] | ??? | 0x0 | *UNDEFINED*
\r
1228 * [13:12] | RW | 0x0 | Address Transfer Width
\r
1229 * [15:14] | ??? | 0x0 | *UNDEFINED*
\r
1230 * [17:16] | RW | 0x0 | Data Transfer Width
\r
1231 * [23:18] | ??? | 0x0 | *UNDEFINED*
\r
1232 * [28:24] | RW | 0x0 | Dummy Write Clock Cycles
\r
1233 * [31:29] | ??? | 0x0 | *UNDEFINED*
\r
1237 * Field : Write Opcode - wropcode
\r
1241 * Field Access Macros:
\r
1244 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */
\r
1245 #define ALT_QSPI_DEVWR_WROPCODE_LSB 0
\r
1246 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */
\r
1247 #define ALT_QSPI_DEVWR_WROPCODE_MSB 7
\r
1248 /* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */
\r
1249 #define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
\r
1250 /* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */
\r
1251 #define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
\r
1252 /* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */
\r
1253 #define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
\r
1254 /* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */
\r
1255 #define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
\r
1256 /* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */
\r
1257 #define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
\r
1258 /* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */
\r
1259 #define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
\r
1262 * Field : Address Transfer Width - addrwidth
\r
1264 * Sets write address transfer width (1, 2, or 4 bits).
\r
1266 * Field Enumeration Values:
\r
1268 * Enum | Value | Description
\r
1269 * :----------------------------------|:------|:-------------------------------------------------
\r
1270 * ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0 | Write address transferred on DQ0. Supported by
\r
1271 * : | | all SPI flash devices
\r
1272 * ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL | 0x1 | Read address transferred on DQ0 and DQ1.
\r
1273 * : | | Supported by some SPI flash devices that support
\r
1274 * : | | the Extended SPI Protocol and by all SPI flash
\r
1275 * : | | devices that support the Dual SP (DIO-SPI)
\r
1276 * : | | Protocol.
\r
1277 * ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD | 0x2 | Read address transferred on DQ0, DQ1, DQ2, and
\r
1278 * : | | DQ3. Supported by some SPI flash devices that
\r
1279 * : | | support the Extended SPI Protocol and by all SPI
\r
1280 * : | | flash devices that support the Quad SP (QIO-SPI)
\r
1281 * : | | Protocol.
\r
1283 * Field Access Macros:
\r
1287 * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
\r
1289 * Write address transferred on DQ0. Supported by all SPI flash devices
\r
1291 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
\r
1293 * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
\r
1295 * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices
\r
1296 * that support the Extended SPI Protocol and by all SPI flash devices that support
\r
1297 * the Dual SP (DIO-SPI) Protocol.
\r
1299 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
\r
1301 * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
\r
1303 * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
\r
1304 * devices that support the Extended SPI Protocol and by all SPI flash devices that
\r
1305 * support the Quad SP (QIO-SPI) Protocol.
\r
1307 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
\r
1309 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
\r
1310 #define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
\r
1311 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
\r
1312 #define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
\r
1313 /* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
\r
1314 #define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
\r
1315 /* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */
\r
1316 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
\r
1317 /* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */
\r
1318 #define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
\r
1319 /* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */
\r
1320 #define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
\r
1321 /* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */
\r
1322 #define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
\r
1323 /* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */
\r
1324 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
\r
1327 * Field : Data Transfer Width - datawidth
\r
1329 * Sets write data transfer width (1, 2, or 4 bits).
\r
1331 * Field Enumeration Values:
\r
1333 * Enum | Value | Description
\r
1334 * :----------------------------------|:------|:-------------------------------------------------
\r
1335 * ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0 | Write data transferred on DQ0. Supported by all
\r
1336 * : | | SPI flash devices
\r
1337 * ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL | 0x1 | Read data transferred on DQ0 and DQ1. Supported
\r
1338 * : | | by some SPI flash devices that support the
\r
1339 * : | | Extended SPI Protocol and by all SPI flash
\r
1340 * : | | devices that support the Dual SP (DIO-SPI)
\r
1341 * : | | Protocol.
\r
1342 * ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD | 0x2 | Read data transferred on DQ0, DQ1, DQ2, and DQ3.
\r
1343 * : | | Supported by some SPI flash devices that support
\r
1344 * : | | the Extended SPI Protocol and by all SPI flash
\r
1345 * : | | devices that support the Quad SP (QIO-SPI)
\r
1346 * : | | Protocol.
\r
1348 * Field Access Macros:
\r
1352 * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
\r
1354 * Write data transferred on DQ0. Supported by all SPI flash devices
\r
1356 #define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
\r
1358 * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
\r
1360 * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that
\r
1361 * support the Extended SPI Protocol and by all SPI flash devices that support the
\r
1362 * Dual SP (DIO-SPI) Protocol.
\r
1364 #define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
\r
1366 * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
\r
1368 * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash
\r
1369 * devices that support the Extended SPI Protocol and by all SPI flash devices that
\r
1370 * support the Quad SP (QIO-SPI) Protocol.
\r
1372 #define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
\r
1374 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
\r
1375 #define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
\r
1376 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
\r
1377 #define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
\r
1378 /* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
\r
1379 #define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
\r
1380 /* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */
\r
1381 #define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
\r
1382 /* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */
\r
1383 #define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
\r
1384 /* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */
\r
1385 #define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
\r
1386 /* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */
\r
1387 #define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
\r
1388 /* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */
\r
1389 #define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
\r
1392 * Field : Dummy Write Clock Cycles - dummywrclks
\r
1394 * Number of dummy clock cycles required by device for write instruction.
\r
1396 * Field Access Macros:
\r
1399 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
\r
1400 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
\r
1401 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
\r
1402 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
\r
1403 /* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
\r
1404 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
\r
1405 /* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */
\r
1406 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
\r
1407 /* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */
\r
1408 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
\r
1409 /* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */
\r
1410 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
\r
1411 /* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */
\r
1412 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
\r
1413 /* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */
\r
1414 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
\r
1416 #ifndef __ASSEMBLY__
\r
1418 * WARNING: The C register and register group struct declarations are provided for
\r
1419 * convenience and illustrative purposes. They should, however, be used with
\r
1420 * caution as the C language standard provides no guarantees about the alignment or
\r
1421 * atomicity of device memory accesses. The recommended practice for writing
\r
1422 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
1423 * alt_write_word() functions.
\r
1425 * The struct declaration for register ALT_QSPI_DEVWR.
\r
1427 struct ALT_QSPI_DEVWR_s
\r
1429 uint32_t wropcode : 8; /* Write Opcode */
\r
1430 uint32_t : 4; /* *UNDEFINED* */
\r
1431 uint32_t addrwidth : 2; /* Address Transfer Width */
\r
1432 uint32_t : 2; /* *UNDEFINED* */
\r
1433 uint32_t datawidth : 2; /* Data Transfer Width */
\r
1434 uint32_t : 6; /* *UNDEFINED* */
\r
1435 uint32_t dummywrclks : 5; /* Dummy Write Clock Cycles */
\r
1436 uint32_t : 3; /* *UNDEFINED* */
\r
1439 /* The typedef declaration for register ALT_QSPI_DEVWR. */
\r
1440 typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t;
\r
1441 #endif /* __ASSEMBLY__ */
\r
1443 /* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */
\r
1444 #define ALT_QSPI_DEVWR_OFST 0x8
\r
1447 * Register : QSPI Device Delay Register - delay
\r
1449 * This register is used to introduce relative delays into the generation of the
\r
1450 * master output signals. All timings are defined in cycles of the qspi_clk.
\r
1454 * Bits | Access | Reset | Description
\r
1455 * :--------|:-------|:------|:-----------------------------------------
\r
1456 * [7:0] | RW | 0x0 | Clock Delay with qspi_n_ss_out
\r
1457 * [15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit
\r
1458 * [23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation
\r
1459 * [31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert
\r
1463 * Field : Clock Delay with qspi_n_ss_out - init
\r
1465 * Delay in master reference clocks between setting qspi_n_ss_out low and first bit
\r
1468 * Field Access Macros:
\r
1471 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */
\r
1472 #define ALT_QSPI_DELAY_INIT_LSB 0
\r
1473 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */
\r
1474 #define ALT_QSPI_DELAY_INIT_MSB 7
\r
1475 /* The width in bits of the ALT_QSPI_DELAY_INIT register field. */
\r
1476 #define ALT_QSPI_DELAY_INIT_WIDTH 8
\r
1477 /* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */
\r
1478 #define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
\r
1479 /* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */
\r
1480 #define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
\r
1481 /* The reset value of the ALT_QSPI_DELAY_INIT register field. */
\r
1482 #define ALT_QSPI_DELAY_INIT_RESET 0x0
\r
1483 /* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */
\r
1484 #define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
\r
1485 /* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */
\r
1486 #define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
\r
1489 * Field : Clock Delay for Last Transaction Bit - after
\r
1491 * Delay in master reference clocks between last bit of current transaction and
\r
1492 * deasserting the device chip select (qspi_n_ss_out). By default, the chip select
\r
1493 * will be deasserted on the cycle following the completion of the current
\r
1496 * Field Access Macros:
\r
1499 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */
\r
1500 #define ALT_QSPI_DELAY_AFTER_LSB 8
\r
1501 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */
\r
1502 #define ALT_QSPI_DELAY_AFTER_MSB 15
\r
1503 /* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */
\r
1504 #define ALT_QSPI_DELAY_AFTER_WIDTH 8
\r
1505 /* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */
\r
1506 #define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
\r
1507 /* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */
\r
1508 #define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
\r
1509 /* The reset value of the ALT_QSPI_DELAY_AFTER register field. */
\r
1510 #define ALT_QSPI_DELAY_AFTER_RESET 0x0
\r
1511 /* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */
\r
1512 #define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
\r
1513 /* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */
\r
1514 #define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
\r
1517 * Field : Clock Delay for Chip Select Deactivation - btwn
\r
1519 * Delay in master reference clocks between one chip select being de-activated and
\r
1520 * the activation of another. This is used to ensure a quiet period between the
\r
1521 * selection of two different slaves and requires the transmit FIFO to be empty.
\r
1523 * Field Access Macros:
\r
1526 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */
\r
1527 #define ALT_QSPI_DELAY_BTWN_LSB 16
\r
1528 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */
\r
1529 #define ALT_QSPI_DELAY_BTWN_MSB 23
\r
1530 /* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */
\r
1531 #define ALT_QSPI_DELAY_BTWN_WIDTH 8
\r
1532 /* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */
\r
1533 #define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
\r
1534 /* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */
\r
1535 #define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
\r
1536 /* The reset value of the ALT_QSPI_DELAY_BTWN register field. */
\r
1537 #define ALT_QSPI_DELAY_BTWN_RESET 0x0
\r
1538 /* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */
\r
1539 #define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
\r
1540 /* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */
\r
1541 #define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
\r
1544 * Field : Clock Delay for Chip Select Deassert - nss
\r
1546 * Delay in master reference clocks for the length that the master mode chip select
\r
1547 * outputs are de-asserted between transactions. The minimum delay is always
\r
1548 * qspi_sck_out period to ensure the chip select is never re-asserted within an
\r
1549 * qspi_sck_out period.
\r
1551 * Field Access Macros:
\r
1554 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */
\r
1555 #define ALT_QSPI_DELAY_NSS_LSB 24
\r
1556 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */
\r
1557 #define ALT_QSPI_DELAY_NSS_MSB 31
\r
1558 /* The width in bits of the ALT_QSPI_DELAY_NSS register field. */
\r
1559 #define ALT_QSPI_DELAY_NSS_WIDTH 8
\r
1560 /* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */
\r
1561 #define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
\r
1562 /* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */
\r
1563 #define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
\r
1564 /* The reset value of the ALT_QSPI_DELAY_NSS register field. */
\r
1565 #define ALT_QSPI_DELAY_NSS_RESET 0x0
\r
1566 /* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */
\r
1567 #define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
\r
1568 /* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */
\r
1569 #define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
\r
1571 #ifndef __ASSEMBLY__
\r
1573 * WARNING: The C register and register group struct declarations are provided for
\r
1574 * convenience and illustrative purposes. They should, however, be used with
\r
1575 * caution as the C language standard provides no guarantees about the alignment or
\r
1576 * atomicity of device memory accesses. The recommended practice for writing
\r
1577 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
1578 * alt_write_word() functions.
\r
1580 * The struct declaration for register ALT_QSPI_DELAY.
\r
1582 struct ALT_QSPI_DELAY_s
\r
1584 uint32_t init : 8; /* Clock Delay with qspi_n_ss_out */
\r
1585 uint32_t after : 8; /* Clock Delay for Last Transaction Bit */
\r
1586 uint32_t btwn : 8; /* Clock Delay for Chip Select Deactivation */
\r
1587 uint32_t nss : 8; /* Clock Delay for Chip Select Deassert */
\r
1590 /* The typedef declaration for register ALT_QSPI_DELAY. */
\r
1591 typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t;
\r
1592 #endif /* __ASSEMBLY__ */
\r
1594 /* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */
\r
1595 #define ALT_QSPI_DELAY_OFST 0xc
\r
1598 * Register : Read Data Capture Register - rddatacap
\r
1602 * Bits | Access | Reset | Description
\r
1603 * :-------|:-------|:------|:------------
\r
1604 * [0] | RW | 0x1 | Bypass
\r
1605 * [4:1] | RW | 0x0 | Read Delay
\r
1606 * [31:5] | ??? | 0x0 | *UNDEFINED*
\r
1610 * Field : Bypass - byp
\r
1612 * Controls bypass of the adapted loopback clock circuit
\r
1614 * Field Enumeration Values:
\r
1616 * Enum | Value | Description
\r
1617 * :----------------------------------|:------|:------------------------------
\r
1618 * ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x0 | No Bypass
\r
1619 * ALT_QSPI_RDDATACAP_BYP_E_BYPASS | 0x1 | Bypass loopback clock circuit
\r
1621 * Field Access Macros:
\r
1625 * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP
\r
1629 #define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0
\r
1631 * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP
\r
1633 * Bypass loopback clock circuit
\r
1635 #define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1
\r
1637 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */
\r
1638 #define ALT_QSPI_RDDATACAP_BYP_LSB 0
\r
1639 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */
\r
1640 #define ALT_QSPI_RDDATACAP_BYP_MSB 0
\r
1641 /* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */
\r
1642 #define ALT_QSPI_RDDATACAP_BYP_WIDTH 1
\r
1643 /* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */
\r
1644 #define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
\r
1645 /* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */
\r
1646 #define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
\r
1647 /* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */
\r
1648 #define ALT_QSPI_RDDATACAP_BYP_RESET 0x1
\r
1649 /* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */
\r
1650 #define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
\r
1651 /* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */
\r
1652 #define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
\r
1655 * Field : Read Delay - delay
\r
1657 * Delay the read data capturing logic by the programmed number of qspi_clk cycles
\r
1659 * Field Access Macros:
\r
1662 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */
\r
1663 #define ALT_QSPI_RDDATACAP_DELAY_LSB 1
\r
1664 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */
\r
1665 #define ALT_QSPI_RDDATACAP_DELAY_MSB 4
\r
1666 /* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */
\r
1667 #define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
\r
1668 /* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */
\r
1669 #define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
\r
1670 /* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */
\r
1671 #define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
\r
1672 /* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */
\r
1673 #define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
\r
1674 /* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */
\r
1675 #define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
\r
1676 /* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */
\r
1677 #define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
\r
1679 #ifndef __ASSEMBLY__
\r
1681 * WARNING: The C register and register group struct declarations are provided for
\r
1682 * convenience and illustrative purposes. They should, however, be used with
\r
1683 * caution as the C language standard provides no guarantees about the alignment or
\r
1684 * atomicity of device memory accesses. The recommended practice for writing
\r
1685 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
1686 * alt_write_word() functions.
\r
1688 * The struct declaration for register ALT_QSPI_RDDATACAP.
\r
1690 struct ALT_QSPI_RDDATACAP_s
\r
1692 uint32_t byp : 1; /* Bypass */
\r
1693 uint32_t delay : 4; /* Read Delay */
\r
1694 uint32_t : 27; /* *UNDEFINED* */
\r
1697 /* The typedef declaration for register ALT_QSPI_RDDATACAP. */
\r
1698 typedef volatile struct ALT_QSPI_RDDATACAP_s ALT_QSPI_RDDATACAP_t;
\r
1699 #endif /* __ASSEMBLY__ */
\r
1701 /* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */
\r
1702 #define ALT_QSPI_RDDATACAP_OFST 0x10
\r
1705 * Register : Device Size Register - devsz
\r
1709 * Bits | Access | Reset | Description
\r
1710 * :--------|:-------|:------|:--------------------------------
\r
1711 * [3:0] | RW | 0x2 | Number of address Bytes
\r
1712 * [15:4] | RW | 0x100 | Number of Bytes per Device Page
\r
1713 * [20:16] | RW | 0x10 | Number of Bytes per Block
\r
1714 * [31:21] | ??? | 0x0 | *UNDEFINED*
\r
1718 * Field : Number of address Bytes - numaddrbytes
\r
1720 * Number of address bytes. A value of 0 indicates 1 byte.
\r
1722 * Field Access Macros:
\r
1725 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
\r
1726 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
\r
1727 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
\r
1728 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
\r
1729 /* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
\r
1730 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
\r
1731 /* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */
\r
1732 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
\r
1733 /* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */
\r
1734 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
\r
1735 /* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */
\r
1736 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
\r
1737 /* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */
\r
1738 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
\r
1739 /* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */
\r
1740 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
\r
1743 * Field : Number of Bytes per Device Page - bytesperdevicepage
\r
1745 * Number of bytes per device page. This is required by the controller for
\r
1746 * performing FLASH writes up to and across page boundaries.
\r
1748 * Field Access Macros:
\r
1751 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
\r
1752 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
\r
1753 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
\r
1754 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
\r
1755 /* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
\r
1756 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
\r
1757 /* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */
\r
1758 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
\r
1759 /* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */
\r
1760 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
\r
1761 /* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */
\r
1762 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
\r
1763 /* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */
\r
1764 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
\r
1765 /* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */
\r
1766 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
\r
1769 * Field : Number of Bytes per Block - bytespersubsector
\r
1771 * Number of bytes per Block. This is required by the controller for performing the
\r
1772 * write protection logic. The number of bytes per block must be a power of 2
\r
1775 * Field Access Macros:
\r
1778 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
\r
1779 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
\r
1780 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
\r
1781 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
\r
1782 /* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
\r
1783 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
\r
1784 /* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */
\r
1785 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
\r
1786 /* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */
\r
1787 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
\r
1788 /* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */
\r
1789 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
\r
1790 /* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */
\r
1791 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
\r
1792 /* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */
\r
1793 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
\r
1795 #ifndef __ASSEMBLY__
\r
1797 * WARNING: The C register and register group struct declarations are provided for
\r
1798 * convenience and illustrative purposes. They should, however, be used with
\r
1799 * caution as the C language standard provides no guarantees about the alignment or
\r
1800 * atomicity of device memory accesses. The recommended practice for writing
\r
1801 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
1802 * alt_write_word() functions.
\r
1804 * The struct declaration for register ALT_QSPI_DEVSZ.
\r
1806 struct ALT_QSPI_DEVSZ_s
\r
1808 uint32_t numaddrbytes : 4; /* Number of address Bytes */
\r
1809 uint32_t bytesperdevicepage : 12; /* Number of Bytes per Device Page */
\r
1810 uint32_t bytespersubsector : 5; /* Number of Bytes per Block */
\r
1811 uint32_t : 11; /* *UNDEFINED* */
\r
1814 /* The typedef declaration for register ALT_QSPI_DEVSZ. */
\r
1815 typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t;
\r
1816 #endif /* __ASSEMBLY__ */
\r
1818 /* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */
\r
1819 #define ALT_QSPI_DEVSZ_OFST 0x14
\r
1822 * Register : SRAM Partition Register - srampart
\r
1826 * Bits | Access | Reset | Description
\r
1827 * :-------|:-------|:------|:-----------------------------
\r
1828 * [6:0] | RW | 0x40 | Indirect Read Partition Size
\r
1829 * [31:7] | ??? | 0x0 | *UNDEFINED*
\r
1833 * Field : Indirect Read Partition Size - addr
\r
1835 * Defines the size of the indirect read partition in the SRAM, in units of SRAM
\r
1836 * locations. By default, half of the SRAM is reserved for indirect read operations
\r
1837 * and half for indirect write operations.
\r
1839 * Field Access Macros:
\r
1842 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */
\r
1843 #define ALT_QSPI_SRAMPART_ADDR_LSB 0
\r
1844 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */
\r
1845 #define ALT_QSPI_SRAMPART_ADDR_MSB 6
\r
1846 /* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */
\r
1847 #define ALT_QSPI_SRAMPART_ADDR_WIDTH 7
\r
1848 /* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */
\r
1849 #define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f
\r
1850 /* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */
\r
1851 #define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80
\r
1852 /* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */
\r
1853 #define ALT_QSPI_SRAMPART_ADDR_RESET 0x40
\r
1854 /* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */
\r
1855 #define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
\r
1856 /* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */
\r
1857 #define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f)
\r
1859 #ifndef __ASSEMBLY__
\r
1861 * WARNING: The C register and register group struct declarations are provided for
\r
1862 * convenience and illustrative purposes. They should, however, be used with
\r
1863 * caution as the C language standard provides no guarantees about the alignment or
\r
1864 * atomicity of device memory accesses. The recommended practice for writing
\r
1865 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
1866 * alt_write_word() functions.
\r
1868 * The struct declaration for register ALT_QSPI_SRAMPART.
\r
1870 struct ALT_QSPI_SRAMPART_s
\r
1872 uint32_t addr : 7; /* Indirect Read Partition Size */
\r
1873 uint32_t : 25; /* *UNDEFINED* */
\r
1876 /* The typedef declaration for register ALT_QSPI_SRAMPART. */
\r
1877 typedef volatile struct ALT_QSPI_SRAMPART_s ALT_QSPI_SRAMPART_t;
\r
1878 #endif /* __ASSEMBLY__ */
\r
1880 /* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */
\r
1881 #define ALT_QSPI_SRAMPART_OFST 0x18
\r
1884 * Register : Indirect AHB Address Trigger Register - indaddrtrig
\r
1888 * Bits | Access | Reset | Description
\r
1889 * :-------|:-------|:------|:----------------
\r
1890 * [31:0] | RW | 0x0 | Trigger Address
\r
1894 * Field : Trigger Address - addr
\r
1896 * This is the base address that will be used by the AHB controller. When the
\r
1897 * incoming AHB read access address matches a range of addresses from this trigger
\r
1898 * address to the trigger address + 15, then the AHB request will be completed by
\r
1899 * fetching data from the Indirect Controllers SRAM.
\r
1901 * Field Access Macros:
\r
1904 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
\r
1905 #define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
\r
1906 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
\r
1907 #define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
\r
1908 /* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
\r
1909 #define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
\r
1910 /* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */
\r
1911 #define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
\r
1912 /* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */
\r
1913 #define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
\r
1914 /* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */
\r
1915 #define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
\r
1916 /* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */
\r
1917 #define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
\r
1918 /* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */
\r
1919 #define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
\r
1921 #ifndef __ASSEMBLY__
\r
1923 * WARNING: The C register and register group struct declarations are provided for
\r
1924 * convenience and illustrative purposes. They should, however, be used with
\r
1925 * caution as the C language standard provides no guarantees about the alignment or
\r
1926 * atomicity of device memory accesses. The recommended practice for writing
\r
1927 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
1928 * alt_write_word() functions.
\r
1930 * The struct declaration for register ALT_QSPI_INDADDRTRIG.
\r
1932 struct ALT_QSPI_INDADDRTRIG_s
\r
1934 uint32_t addr : 32; /* Trigger Address */
\r
1937 /* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */
\r
1938 typedef volatile struct ALT_QSPI_INDADDRTRIG_s ALT_QSPI_INDADDRTRIG_t;
\r
1939 #endif /* __ASSEMBLY__ */
\r
1941 /* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */
\r
1942 #define ALT_QSPI_INDADDRTRIG_OFST 0x1c
\r
1945 * Register : DMA Peripheral Register - dmaper
\r
1949 * Bits | Access | Reset | Description
\r
1950 * :--------|:-------|:------|:-----------------------
\r
1951 * [3:0] | RW | 0x0 | Number of Single Bytes
\r
1952 * [7:4] | ??? | 0x0 | *UNDEFINED*
\r
1953 * [11:8] | RW | 0x0 | Number of Burst Bytes
\r
1954 * [31:12] | ??? | 0x0 | *UNDEFINED*
\r
1958 * Field : Number of Single Bytes - numsglreqbytes
\r
1960 * Number of bytes in a single type request on the DMA peripheral request. A
\r
1961 * programmed value of 0 represents a single byte. This should be setup before
\r
1962 * starting the indirect read or write operation. The actual number of bytes used
\r
1963 * is 2**(value in this register) which will simplify implementation.
\r
1965 * Field Access Macros:
\r
1968 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
\r
1969 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
\r
1970 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
\r
1971 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
\r
1972 /* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
\r
1973 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
\r
1974 /* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */
\r
1975 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
\r
1976 /* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */
\r
1977 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
\r
1978 /* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */
\r
1979 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
\r
1980 /* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */
\r
1981 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
\r
1982 /* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */
\r
1983 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
\r
1986 * Field : Number of Burst Bytes - numburstreqbytes
\r
1988 * Number of bytes in a burst type request on the DMA peripheral request. A
\r
1989 * programmed value of 0 represents a single byte. This should be setup before
\r
1990 * starting the indirect read or write operation. The actual number of bytes used
\r
1991 * is 2**(value in this register) which will simplify implementation.
\r
1993 * Field Access Macros:
\r
1996 /* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
\r
1997 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
\r
1998 /* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
\r
1999 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
\r
2000 /* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
\r
2001 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
\r
2002 /* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */
\r
2003 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
\r
2004 /* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */
\r
2005 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
\r
2006 /* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */
\r
2007 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
\r
2008 /* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */
\r
2009 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
\r
2010 /* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */
\r
2011 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
\r
2013 #ifndef __ASSEMBLY__
\r
2015 * WARNING: The C register and register group struct declarations are provided for
\r
2016 * convenience and illustrative purposes. They should, however, be used with
\r
2017 * caution as the C language standard provides no guarantees about the alignment or
\r
2018 * atomicity of device memory accesses. The recommended practice for writing
\r
2019 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
2020 * alt_write_word() functions.
\r
2022 * The struct declaration for register ALT_QSPI_DMAPER.
\r
2024 struct ALT_QSPI_DMAPER_s
\r
2026 uint32_t numsglreqbytes : 4; /* Number of Single Bytes */
\r
2027 uint32_t : 4; /* *UNDEFINED* */
\r
2028 uint32_t numburstreqbytes : 4; /* Number of Burst Bytes */
\r
2029 uint32_t : 20; /* *UNDEFINED* */
\r
2032 /* The typedef declaration for register ALT_QSPI_DMAPER. */
\r
2033 typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t;
\r
2034 #endif /* __ASSEMBLY__ */
\r
2036 /* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */
\r
2037 #define ALT_QSPI_DMAPER_OFST 0x20
\r
2040 * Register : Remap Address Register - remapaddr
\r
2042 * This register is used to remap an incoming AHB address to a different address
\r
2043 * used by the FLASH device.
\r
2047 * Bits | Access | Reset | Description
\r
2048 * :-------|:-------|:------|:---------------------
\r
2049 * [31:0] | RW | 0x0 | Remap Address Offset
\r
2053 * Field : Remap Address Offset - value
\r
2055 * This offset is added to the incoming AHB address to determine the address used
\r
2056 * by the FLASH device.
\r
2058 * Field Access Macros:
\r
2061 /* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */
\r
2062 #define ALT_QSPI_REMAPADDR_VALUE_LSB 0
\r
2063 /* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */
\r
2064 #define ALT_QSPI_REMAPADDR_VALUE_MSB 31
\r
2065 /* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */
\r
2066 #define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
\r
2067 /* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */
\r
2068 #define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
\r
2069 /* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */
\r
2070 #define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
\r
2071 /* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */
\r
2072 #define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
\r
2073 /* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */
\r
2074 #define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
\r
2075 /* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */
\r
2076 #define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
\r
2078 #ifndef __ASSEMBLY__
\r
2080 * WARNING: The C register and register group struct declarations are provided for
\r
2081 * convenience and illustrative purposes. They should, however, be used with
\r
2082 * caution as the C language standard provides no guarantees about the alignment or
\r
2083 * atomicity of device memory accesses. The recommended practice for writing
\r
2084 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
2085 * alt_write_word() functions.
\r
2087 * The struct declaration for register ALT_QSPI_REMAPADDR.
\r
2089 struct ALT_QSPI_REMAPADDR_s
\r
2091 uint32_t value : 32; /* Remap Address Offset */
\r
2094 /* The typedef declaration for register ALT_QSPI_REMAPADDR. */
\r
2095 typedef volatile struct ALT_QSPI_REMAPADDR_s ALT_QSPI_REMAPADDR_t;
\r
2096 #endif /* __ASSEMBLY__ */
\r
2098 /* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */
\r
2099 #define ALT_QSPI_REMAPADDR_OFST 0x24
\r
2102 * Register : Mode Bit Register - modebit
\r
2106 * Bits | Access | Reset | Description
\r
2107 * :-------|:-------|:------|:------------
\r
2108 * [7:0] | RW | 0x0 | Mode
\r
2109 * [31:8] | ??? | 0x0 | *UNDEFINED*
\r
2113 * Field : Mode - mode
\r
2115 * These are the 8 mode bits that are sent to the device following the address
\r
2116 * bytes if mode bit transmission has been enabled.
\r
2118 * Field Access Macros:
\r
2121 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */
\r
2122 #define ALT_QSPI_MODBIT_MOD_LSB 0
\r
2123 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */
\r
2124 #define ALT_QSPI_MODBIT_MOD_MSB 7
\r
2125 /* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */
\r
2126 #define ALT_QSPI_MODBIT_MOD_WIDTH 8
\r
2127 /* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */
\r
2128 #define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff
\r
2129 /* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */
\r
2130 #define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00
\r
2131 /* The reset value of the ALT_QSPI_MODBIT_MOD register field. */
\r
2132 #define ALT_QSPI_MODBIT_MOD_RESET 0x0
\r
2133 /* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */
\r
2134 #define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0)
\r
2135 /* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */
\r
2136 #define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff)
\r
2138 #ifndef __ASSEMBLY__
\r
2140 * WARNING: The C register and register group struct declarations are provided for
\r
2141 * convenience and illustrative purposes. They should, however, be used with
\r
2142 * caution as the C language standard provides no guarantees about the alignment or
\r
2143 * atomicity of device memory accesses. The recommended practice for writing
\r
2144 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
2145 * alt_write_word() functions.
\r
2147 * The struct declaration for register ALT_QSPI_MODBIT.
\r
2149 struct ALT_QSPI_MODBIT_s
\r
2151 uint32_t mode : 8; /* Mode */
\r
2152 uint32_t : 24; /* *UNDEFINED* */
\r
2155 /* The typedef declaration for register ALT_QSPI_MODBIT. */
\r
2156 typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t;
\r
2157 #endif /* __ASSEMBLY__ */
\r
2159 /* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */
\r
2160 #define ALT_QSPI_MODBIT_OFST 0x28
\r
2163 * Register : SRAM Fill Register - sramfill
\r
2167 * Bits | Access | Reset | Description
\r
2168 * :--------|:-------|:------|:-------------------------------------------------------------------
\r
2169 * [15:0] | R | 0x0 | SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS
\r
2170 * [31:16] | R | 0x0 | SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS
\r
2174 * Field : SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - indrdpart
\r
2176 * Field Access Macros:
\r
2179 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
\r
2180 #define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
\r
2181 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
\r
2182 #define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
\r
2183 /* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
\r
2184 #define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
\r
2185 /* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */
\r
2186 #define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
\r
2187 /* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */
\r
2188 #define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
\r
2189 /* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */
\r
2190 #define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
\r
2191 /* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */
\r
2192 #define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
\r
2193 /* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */
\r
2194 #define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
\r
2197 * Field : SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - indwrpart
\r
2199 * Field Access Macros:
\r
2202 /* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
\r
2203 #define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
\r
2204 /* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
\r
2205 #define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
\r
2206 /* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
\r
2207 #define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
\r
2208 /* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */
\r
2209 #define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
\r
2210 /* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */
\r
2211 #define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
\r
2212 /* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */
\r
2213 #define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
\r
2214 /* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */
\r
2215 #define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
\r
2216 /* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */
\r
2217 #define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
\r
2219 #ifndef __ASSEMBLY__
\r
2221 * WARNING: The C register and register group struct declarations are provided for
\r
2222 * convenience and illustrative purposes. They should, however, be used with
\r
2223 * caution as the C language standard provides no guarantees about the alignment or
\r
2224 * atomicity of device memory accesses. The recommended practice for writing
\r
2225 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
2226 * alt_write_word() functions.
\r
2228 * The struct declaration for register ALT_QSPI_SRAMFILL.
\r
2230 struct ALT_QSPI_SRAMFILL_s
\r
2232 const uint32_t indrdpart : 16; /* SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS */
\r
2233 const uint32_t indwrpart : 16; /* SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS */
\r
2236 /* The typedef declaration for register ALT_QSPI_SRAMFILL. */
\r
2237 typedef volatile struct ALT_QSPI_SRAMFILL_s ALT_QSPI_SRAMFILL_t;
\r
2238 #endif /* __ASSEMBLY__ */
\r
2240 /* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */
\r
2241 #define ALT_QSPI_SRAMFILL_OFST 0x2c
\r
2244 * Register : TX Threshold Register - txthresh
\r
2248 * Bits | Access | Reset | Description
\r
2249 * :-------|:-------|:------|:------------
\r
2250 * [3:0] | RW | 0x1 | Level
\r
2251 * [31:4] | ??? | 0x0 | *UNDEFINED*
\r
2255 * Field : Level - level
\r
2257 * Defines the level at which the transmit FIFO not full interrupt is generated
\r
2259 * Field Access Macros:
\r
2262 /* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */
\r
2263 #define ALT_QSPI_TXTHRESH_LEVEL_LSB 0
\r
2264 /* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */
\r
2265 #define ALT_QSPI_TXTHRESH_LEVEL_MSB 3
\r
2266 /* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */
\r
2267 #define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
\r
2268 /* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */
\r
2269 #define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
\r
2270 /* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */
\r
2271 #define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
\r
2272 /* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */
\r
2273 #define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
\r
2274 /* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */
\r
2275 #define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
\r
2276 /* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */
\r
2277 #define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
\r
2279 #ifndef __ASSEMBLY__
\r
2281 * WARNING: The C register and register group struct declarations are provided for
\r
2282 * convenience and illustrative purposes. They should, however, be used with
\r
2283 * caution as the C language standard provides no guarantees about the alignment or
\r
2284 * atomicity of device memory accesses. The recommended practice for writing
\r
2285 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
2286 * alt_write_word() functions.
\r
2288 * The struct declaration for register ALT_QSPI_TXTHRESH.
\r
2290 struct ALT_QSPI_TXTHRESH_s
\r
2292 uint32_t level : 4; /* Level */
\r
2293 uint32_t : 28; /* *UNDEFINED* */
\r
2296 /* The typedef declaration for register ALT_QSPI_TXTHRESH. */
\r
2297 typedef volatile struct ALT_QSPI_TXTHRESH_s ALT_QSPI_TXTHRESH_t;
\r
2298 #endif /* __ASSEMBLY__ */
\r
2300 /* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */
\r
2301 #define ALT_QSPI_TXTHRESH_OFST 0x30
\r
2304 * Register : RX Threshold Register - rxthresh
\r
2306 * Device Instruction Register
\r
2310 * Bits | Access | Reset | Description
\r
2311 * :-------|:-------|:------|:------------
\r
2312 * [3:0] | RW | 0x1 | Level
\r
2313 * [31:4] | ??? | 0x0 | *UNDEFINED*
\r
2317 * Field : Level - level
\r
2319 * Defines the level at which the receive FIFO not empty interrupt is generated
\r
2321 * Field Access Macros:
\r
2324 /* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */
\r
2325 #define ALT_QSPI_RXTHRESH_LEVEL_LSB 0
\r
2326 /* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */
\r
2327 #define ALT_QSPI_RXTHRESH_LEVEL_MSB 3
\r
2328 /* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */
\r
2329 #define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
\r
2330 /* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */
\r
2331 #define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
\r
2332 /* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */
\r
2333 #define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
\r
2334 /* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */
\r
2335 #define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
\r
2336 /* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */
\r
2337 #define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
\r
2338 /* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */
\r
2339 #define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
\r
2341 #ifndef __ASSEMBLY__
\r
2343 * WARNING: The C register and register group struct declarations are provided for
\r
2344 * convenience and illustrative purposes. They should, however, be used with
\r
2345 * caution as the C language standard provides no guarantees about the alignment or
\r
2346 * atomicity of device memory accesses. The recommended practice for writing
\r
2347 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
2348 * alt_write_word() functions.
\r
2350 * The struct declaration for register ALT_QSPI_RXTHRESH.
\r
2352 struct ALT_QSPI_RXTHRESH_s
\r
2354 uint32_t level : 4; /* Level */
\r
2355 uint32_t : 28; /* *UNDEFINED* */
\r
2358 /* The typedef declaration for register ALT_QSPI_RXTHRESH. */
\r
2359 typedef volatile struct ALT_QSPI_RXTHRESH_s ALT_QSPI_RXTHRESH_t;
\r
2360 #endif /* __ASSEMBLY__ */
\r
2362 /* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */
\r
2363 #define ALT_QSPI_RXTHRESH_OFST 0x34
\r
2366 * Register : Interrupt Status Register - irqstat
\r
2368 * The status fields in this register are set when the described event occurs and
\r
2369 * the interrupt is enabled in the mask register. When any of these bit fields are
\r
2370 * set, the interrupt output is asserted high. The fields are each cleared by
\r
2371 * writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when
\r
2372 * legacy SPI mode is active.
\r
2376 * Bits | Access | Reset | Description
\r
2377 * :--------|:-------|:------|:------------------------------------
\r
2378 * [0] | ??? | 0x0 | *UNDEFINED*
\r
2379 * [1] | RW | 0x0 | Underflow Detected
\r
2380 * [2] | RW | 0x0 | Indirect Operation Complete
\r
2381 * [3] | RW | 0x0 | Indirect Read Reject
\r
2382 * [4] | RW | 0x0 | Protected Area Write Attempt
\r
2383 * [5] | RW | 0x0 | Illegal AHB Access Detected
\r
2384 * [6] | RW | 0x0 | Transfer Watermark Reached
\r
2385 * [7] | RW | 0x0 | Receive Overflow
\r
2386 * [8] | RW | 0x1 | Transmit FIFO Compared to Threshold
\r
2387 * [9] | RW | 0x0 | Transmit FIFO Full
\r
2388 * [10] | RW | 0x0 | Receive FIFO Compared to Threshold
\r
2389 * [11] | RW | 0x0 | Receive FIFO Full
\r
2390 * [12] | RW | 0x0 | Indirect Read Partition overflow
\r
2391 * [31:13] | ??? | 0x0 | *UNDEFINED*
\r
2395 * Field : Underflow Detected - underflowdet
\r
2397 * An underflow is detected when an attempt to transfer data is made when the
\r
2398 * transmit FIFO is empty. This may occur when the AHB write data is being supplied
\r
2399 * too slowly to keep up with the requested write operation. This bit is reset only
\r
2400 * by a system reset and cleared only when the register is read.
\r
2402 * Field Enumeration Values:
\r
2404 * Enum | Value | Description
\r
2405 * :--------------------------------------------|:------|:-------------
\r
2406 * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW | 0x1 | Underflow
\r
2407 * ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0 | No Underflow
\r
2409 * Field Access Macros:
\r
2413 * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
\r
2417 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
\r
2419 * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
\r
2423 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
\r
2425 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
\r
2426 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
\r
2427 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
\r
2428 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
\r
2429 /* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
\r
2430 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
\r
2431 /* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */
\r
2432 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
\r
2433 /* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */
\r
2434 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
\r
2435 /* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */
\r
2436 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
\r
2437 /* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */
\r
2438 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
\r
2439 /* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */
\r
2440 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
\r
2443 * Field : Indirect Operation Complete - indopdone
\r
2445 * Controller has completed last triggered indirect operation
\r
2447 * Field Enumeration Values:
\r
2449 * Enum | Value | Description
\r
2450 * :------------------------------------------|:------|:-----------------------------
\r
2451 * ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP | 0x1 | Completed Indirect Operation
\r
2452 * ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0 | No Indirect Operation
\r
2454 * Field Access Macros:
\r
2458 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
\r
2460 * Completed Indirect Operation
\r
2462 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
\r
2464 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
\r
2466 * No Indirect Operation
\r
2468 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
\r
2470 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
\r
2471 #define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
\r
2472 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
\r
2473 #define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
\r
2474 /* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
\r
2475 #define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
\r
2476 /* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */
\r
2477 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
\r
2478 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */
\r
2479 #define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
\r
2480 /* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */
\r
2481 #define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
\r
2482 /* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */
\r
2483 #define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
\r
2484 /* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */
\r
2485 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
\r
2488 * Field : Indirect Read Reject - indrdreject
\r
2490 * Indirect operation was requested but could not be accepted. Two indirect
\r
2491 * operations already in storage.
\r
2493 * Field Enumeration Values:
\r
2495 * Enum | Value | Description
\r
2496 * :---------------------------------------------|:------|:-----------------------------
\r
2497 * ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ | 0x1 | Indirect Operation Requested
\r
2498 * ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0 | No Indirect Operation
\r
2500 * Field Access Macros:
\r
2504 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
\r
2506 * Indirect Operation Requested
\r
2508 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
\r
2510 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
\r
2512 * No Indirect Operation
\r
2514 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
\r
2516 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
\r
2517 #define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
\r
2518 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
\r
2519 #define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
\r
2520 /* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
\r
2521 #define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
\r
2522 /* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */
\r
2523 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
\r
2524 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */
\r
2525 #define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
\r
2526 /* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */
\r
2527 #define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
\r
2528 /* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */
\r
2529 #define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
\r
2530 /* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */
\r
2531 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
\r
2534 * Field : Protected Area Write Attempt - protwrattempt
\r
2536 * Write to protected area was attempted and rejected.
\r
2538 * Field Enumeration Values:
\r
2540 * Enum | Value | Description
\r
2541 * :------------------------------------------|:------|:--------------------------------
\r
2542 * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT | 0x1 | Write Attempt to protected area
\r
2543 * ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0 | No Write Attempt
\r
2545 * Field Access Macros:
\r
2549 * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
\r
2551 * Write Attempt to protected area
\r
2553 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1
\r
2555 * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
\r
2557 * No Write Attempt
\r
2559 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0
\r
2561 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
\r
2562 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
\r
2563 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
\r
2564 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
\r
2565 /* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
\r
2566 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
\r
2567 /* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */
\r
2568 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
\r
2569 /* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */
\r
2570 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
\r
2571 /* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */
\r
2572 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
\r
2573 /* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */
\r
2574 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
\r
2575 /* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */
\r
2576 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
\r
2579 * Field : Illegal AHB Access Detected - illegalacc
\r
2581 * Illegal AHB access has been detected. AHB wrapping bursts and the use of
\r
2582 * SPLIT/RETRY accesses will cause this error interrupt to trigger.
\r
2584 * Field Enumeration Values:
\r
2586 * Enum | Value | Description
\r
2587 * :-------------------------------------------|:------|:-----------------------
\r
2588 * ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB | 0x1 | Illegal AHB attempt
\r
2589 * ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0 | No Illegal AHB attempt
\r
2591 * Field Access Macros:
\r
2595 * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
\r
2597 * Illegal AHB attempt
\r
2599 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
\r
2601 * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
\r
2603 * No Illegal AHB attempt
\r
2605 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
\r
2607 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
\r
2608 #define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
\r
2609 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
\r
2610 #define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
\r
2611 /* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
\r
2612 #define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
\r
2613 /* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */
\r
2614 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
\r
2615 /* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */
\r
2616 #define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
\r
2617 /* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */
\r
2618 #define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
\r
2619 /* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */
\r
2620 #define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
\r
2621 /* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */
\r
2622 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
\r
2625 * Field : Transfer Watermark Reached - indxfrlvl
\r
2627 * Indirect Transfer Watermark Level Reached
\r
2629 * Field Enumeration Values:
\r
2631 * Enum | Value | Description
\r
2632 * :----------------------------------------|:------|:-----------------------
\r
2633 * ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL | 0x1 | Water level reached
\r
2634 * ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0 | No water level reached
\r
2636 * Field Access Macros:
\r
2640 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
\r
2642 * Water level reached
\r
2644 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
\r
2646 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
\r
2648 * No water level reached
\r
2650 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
\r
2652 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
\r
2653 #define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
\r
2654 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
\r
2655 #define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
\r
2656 /* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
\r
2657 #define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
\r
2658 /* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */
\r
2659 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
\r
2660 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */
\r
2661 #define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
\r
2662 /* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */
\r
2663 #define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
\r
2664 /* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */
\r
2665 #define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
\r
2666 /* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */
\r
2667 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
\r
2670 * Field : Receive Overflow - rxover
\r
2672 * This should only occur in Legacy SPI mode. Set if an attempt is made to push the
\r
2673 * RX FIFO when it is full. This bit is reset only by a system reset and cleared
\r
2674 * only when this register is read. If a new push to the RX FIFO occurs coincident
\r
2675 * with a register read this flag will remain set. 0 : no overflow has been
\r
2676 * detected. 1 : an overflow has occurred.
\r
2678 * Field Enumeration Values:
\r
2680 * Enum | Value | Description
\r
2681 * :------------------------------------|:------|:--------------------
\r
2682 * ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER | 0x1 | Receive Overflow
\r
2683 * ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0 | No Receive Overflow
\r
2685 * Field Access Macros:
\r
2689 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
\r
2691 * Receive Overflow
\r
2693 #define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
\r
2695 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
\r
2697 * No Receive Overflow
\r
2699 #define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
\r
2701 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */
\r
2702 #define ALT_QSPI_IRQSTAT_RXOVER_LSB 7
\r
2703 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */
\r
2704 #define ALT_QSPI_IRQSTAT_RXOVER_MSB 7
\r
2705 /* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */
\r
2706 #define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
\r
2707 /* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */
\r
2708 #define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
\r
2709 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */
\r
2710 #define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
\r
2711 /* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */
\r
2712 #define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
\r
2713 /* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */
\r
2714 #define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
\r
2715 /* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */
\r
2716 #define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
\r
2719 * Field : Transmit FIFO Compared to Threshold - txthreshcmp
\r
2721 * Indicates the number of entries in the transmit FIFO with respect to the
\r
2722 * threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode.
\r
2724 * Field Enumeration Values:
\r
2726 * Enum | Value | Description
\r
2727 * :----------------------------------|:------|:-----------------------------
\r
2728 * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0 | FIFO has > TXTHRESH entries
\r
2729 * ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1 | FIFO has <= TXTHRESH entries
\r
2731 * Field Access Macros:
\r
2735 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
\r
2737 * FIFO has > TXTHRESH entries
\r
2739 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
\r
2741 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
\r
2743 * FIFO has <= TXTHRESH entries
\r
2745 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
\r
2747 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
\r
2748 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
\r
2749 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
\r
2750 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
\r
2751 /* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
\r
2752 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
\r
2753 /* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */
\r
2754 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
\r
2755 /* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */
\r
2756 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
\r
2757 /* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */
\r
2758 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
\r
2759 /* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */
\r
2760 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
\r
2761 /* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */
\r
2762 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
\r
2765 * Field : Transmit FIFO Full - txfull
\r
2767 * Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy
\r
2770 * Field Enumeration Values:
\r
2772 * Enum | Value | Description
\r
2773 * :----------------------------------|:------|:-----------------------
\r
2774 * ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0 | Transmit FIFO Not Full
\r
2775 * ALT_QSPI_IRQSTAT_TXFULL_E_FULL | 0x1 | Transmit FIFO Full
\r
2777 * Field Access Macros:
\r
2781 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
\r
2783 * Transmit FIFO Not Full
\r
2785 #define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
\r
2787 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
\r
2789 * Transmit FIFO Full
\r
2791 #define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
\r
2793 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */
\r
2794 #define ALT_QSPI_IRQSTAT_TXFULL_LSB 9
\r
2795 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */
\r
2796 #define ALT_QSPI_IRQSTAT_TXFULL_MSB 9
\r
2797 /* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */
\r
2798 #define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
\r
2799 /* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */
\r
2800 #define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
\r
2801 /* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */
\r
2802 #define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
\r
2803 /* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */
\r
2804 #define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
\r
2805 /* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */
\r
2806 #define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
\r
2807 /* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */
\r
2808 #define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
\r
2811 * Field : Receive FIFO Compared to Threshold - rxthreshcmp
\r
2813 * Indicates the number of entries in the receive FIFO with respect to the
\r
2814 * threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode.
\r
2816 * Field Enumeration Values:
\r
2818 * Enum | Value | Description
\r
2819 * :----------------------------------|:------|:-----------------------------
\r
2820 * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0 | FIFO has <= RXTHRESH entries
\r
2821 * ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1 | FIFO has > RXTHRESH entries
\r
2823 * Field Access Macros:
\r
2827 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
\r
2829 * FIFO has <= RXTHRESH entries
\r
2831 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
\r
2833 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
\r
2835 * FIFO has > RXTHRESH entries
\r
2837 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
\r
2839 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
\r
2840 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
\r
2841 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
\r
2842 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
\r
2843 /* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
\r
2844 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
\r
2845 /* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */
\r
2846 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
\r
2847 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */
\r
2848 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
\r
2849 /* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */
\r
2850 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
\r
2851 /* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */
\r
2852 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
\r
2853 /* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */
\r
2854 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
\r
2857 * Field : Receive FIFO Full - rxfull
\r
2859 * Indicates that the receive FIFO is full or not. Only relevant in SPI legacy
\r
2862 * Field Enumeration Values:
\r
2864 * Enum | Value | Description
\r
2865 * :----------------------------------|:------|:----------------------
\r
2866 * ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0 | Receive FIFO Not Full
\r
2867 * ALT_QSPI_IRQSTAT_RXFULL_E_FULL | 0x1 | Receive FIFO Full
\r
2869 * Field Access Macros:
\r
2873 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
\r
2875 * Receive FIFO Not Full
\r
2877 #define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
\r
2879 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
\r
2881 * Receive FIFO Full
\r
2883 #define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
\r
2885 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */
\r
2886 #define ALT_QSPI_IRQSTAT_RXFULL_LSB 11
\r
2887 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */
\r
2888 #define ALT_QSPI_IRQSTAT_RXFULL_MSB 11
\r
2889 /* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */
\r
2890 #define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
\r
2891 /* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */
\r
2892 #define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
\r
2893 /* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */
\r
2894 #define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
\r
2895 /* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */
\r
2896 #define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
\r
2897 /* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */
\r
2898 #define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
\r
2899 /* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */
\r
2900 #define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
\r
2903 * Field : Indirect Read Partition overflow - indsramfull
\r
2905 * Indirect Read Partition of SRAM is full and unable to immediately complete
\r
2906 * indirect operation
\r
2908 * Field Enumeration Values:
\r
2910 * Enum | Value | Description
\r
2911 * :---------------------------------------------|:------|:-----------------
\r
2912 * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL | 0x1 | SRAM is full
\r
2913 * ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0 | SRAM is not full
\r
2915 * Field Access Macros:
\r
2919 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
\r
2923 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
\r
2925 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
\r
2927 * SRAM is not full
\r
2929 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
\r
2931 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
\r
2932 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
\r
2933 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
\r
2934 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
\r
2935 /* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
\r
2936 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
\r
2937 /* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */
\r
2938 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
\r
2939 /* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */
\r
2940 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
\r
2941 /* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */
\r
2942 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
\r
2943 /* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */
\r
2944 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
\r
2945 /* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */
\r
2946 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
\r
2948 #ifndef __ASSEMBLY__
\r
2950 * WARNING: The C register and register group struct declarations are provided for
\r
2951 * convenience and illustrative purposes. They should, however, be used with
\r
2952 * caution as the C language standard provides no guarantees about the alignment or
\r
2953 * atomicity of device memory accesses. The recommended practice for writing
\r
2954 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
2955 * alt_write_word() functions.
\r
2957 * The struct declaration for register ALT_QSPI_IRQSTAT.
\r
2959 struct ALT_QSPI_IRQSTAT_s
\r
2961 uint32_t : 1; /* *UNDEFINED* */
\r
2962 uint32_t underflowdet : 1; /* Underflow Detected */
\r
2963 uint32_t indopdone : 1; /* Indirect Operation Complete */
\r
2964 uint32_t indrdreject : 1; /* Indirect Read Reject */
\r
2965 uint32_t protwrattempt : 1; /* Protected Area Write Attempt */
\r
2966 uint32_t illegalacc : 1; /* Illegal AHB Access Detected */
\r
2967 uint32_t indxfrlvl : 1; /* Transfer Watermark Reached */
\r
2968 uint32_t rxover : 1; /* Receive Overflow */
\r
2969 uint32_t txthreshcmp : 1; /* Transmit FIFO Compared to Threshold */
\r
2970 uint32_t txfull : 1; /* Transmit FIFO Full */
\r
2971 uint32_t rxthreshcmp : 1; /* Receive FIFO Compared to Threshold */
\r
2972 uint32_t rxfull : 1; /* Receive FIFO Full */
\r
2973 uint32_t indsramfull : 1; /* Indirect Read Partition overflow */
\r
2974 uint32_t : 19; /* *UNDEFINED* */
\r
2977 /* The typedef declaration for register ALT_QSPI_IRQSTAT. */
\r
2978 typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t;
\r
2979 #endif /* __ASSEMBLY__ */
\r
2981 /* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */
\r
2982 #define ALT_QSPI_IRQSTAT_OFST 0x40
\r
2985 * Register : Interrupt Mask - irqmask
\r
2987 * If disabled, the interrupt for the corresponding interrupt status register bit
\r
2988 * is disabled. If enabled, the interrupt for the corresponding interrupt status
\r
2989 * register bit is enabled.
\r
2993 * Bits | Access | Reset | Description
\r
2994 * :--------|:-------|:------|:--------------------------------------
\r
2995 * [0] | ??? | 0x0 | *UNDEFINED*
\r
2996 * [1] | RW | 0x0 | Underflow Detected Mask
\r
2997 * [2] | RW | 0x0 | Mask
\r
2998 * [3] | RW | 0x0 | Indirect Read Reject Mask
\r
2999 * [4] | RW | 0x0 | Protected Area Write Attempt Mask
\r
3000 * [5] | RW | 0x0 | Illegal Access Detected Mask
\r
3001 * [6] | RW | 0x0 | Transfer Watermark Breach Mask
\r
3002 * [7] | RW | 0x0 | Receive Overflow Mask
\r
3003 * [8] | RW | 0x0 | Transmit FIFO Threshold Compare Mask
\r
3004 * [9] | RW | 0x0 | Transmit FIFO Full Mask
\r
3005 * [10] | RW | 0x0 | Receive FIFO Threshold Compare Mask
\r
3006 * [11] | RW | 0x0 | Receive FIFO full Mask
\r
3007 * [12] | RW | 0x0 | Indirect Read Partition overflow mask
\r
3008 * [31:13] | ??? | 0x0 | *UNDEFINED*
\r
3012 * Field : Underflow Detected Mask - underflowdet
\r
3014 * Field Enumeration Values:
\r
3016 * Enum | Value | Description
\r
3017 * :------------------------------------|:------|:-----------------------------
\r
3018 * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3019 * ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END | 0x1 | Enable Interrupt
\r
3021 * Field Access Macros:
\r
3025 * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET
\r
3027 * Disable Interrupt by Masking
\r
3029 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0
\r
3031 * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET
\r
3033 * Enable Interrupt
\r
3035 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1
\r
3037 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
\r
3038 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1
\r
3039 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
\r
3040 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1
\r
3041 /* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
\r
3042 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1
\r
3043 /* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */
\r
3044 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002
\r
3045 /* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */
\r
3046 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd
\r
3047 /* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */
\r
3048 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0
\r
3049 /* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */
\r
3050 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
\r
3051 /* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */
\r
3052 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
\r
3055 * Field : Mask - indopdone
\r
3057 * Field Enumeration Values:
\r
3059 * Enum | Value | Description
\r
3060 * :---------------------------------|:------|:-----------------------------
\r
3061 * ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3062 * ALT_QSPI_IRQMSK_INDOPDONE_E_END | 0x1 | Enable Interrupt
\r
3064 * Field Access Macros:
\r
3068 * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE
\r
3070 * Disable Interrupt by Masking
\r
3072 #define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0
\r
3074 * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE
\r
3076 * Enable Interrupt
\r
3078 #define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1
\r
3080 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
\r
3081 #define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2
\r
3082 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
\r
3083 #define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2
\r
3084 /* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
\r
3085 #define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1
\r
3086 /* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */
\r
3087 #define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004
\r
3088 /* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */
\r
3089 #define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb
\r
3090 /* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */
\r
3091 #define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0
\r
3092 /* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */
\r
3093 #define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
\r
3094 /* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */
\r
3095 #define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
\r
3098 * Field : Indirect Read Reject Mask - indrdreject
\r
3100 * Field Enumeration Values:
\r
3102 * Enum | Value | Description
\r
3103 * :-----------------------------------|:------|:-----------------------------
\r
3104 * ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3105 * ALT_QSPI_IRQMSK_INDRDREJECT_E_END | 0x1 | Enable Interrupt
\r
3107 * Field Access Macros:
\r
3111 * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT
\r
3113 * Disable Interrupt by Masking
\r
3115 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0
\r
3117 * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT
\r
3119 * Enable Interrupt
\r
3121 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1
\r
3123 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
\r
3124 #define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3
\r
3125 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
\r
3126 #define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3
\r
3127 /* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
\r
3128 #define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1
\r
3129 /* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */
\r
3130 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008
\r
3131 /* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */
\r
3132 #define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7
\r
3133 /* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */
\r
3134 #define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0
\r
3135 /* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */
\r
3136 #define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
\r
3137 /* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */
\r
3138 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
\r
3141 * Field : Protected Area Write Attempt Mask - protwrattempt
\r
3143 * Field Enumeration Values:
\r
3145 * Enum | Value | Description
\r
3146 * :-------------------------------------|:------|:-----------------------------
\r
3147 * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3148 * ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END | 0x1 | Enable Interrupt
\r
3150 * Field Access Macros:
\r
3154 * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT
\r
3156 * Disable Interrupt by Masking
\r
3158 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0
\r
3160 * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT
\r
3162 * Enable Interrupt
\r
3164 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1
\r
3166 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
\r
3167 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4
\r
3168 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
\r
3169 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4
\r
3170 /* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
\r
3171 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1
\r
3172 /* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */
\r
3173 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010
\r
3174 /* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */
\r
3175 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef
\r
3176 /* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */
\r
3177 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0
\r
3178 /* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */
\r
3179 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
\r
3180 /* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */
\r
3181 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
\r
3184 * Field : Illegal Access Detected Mask - illegalacc
\r
3186 * Field Enumeration Values:
\r
3188 * Enum | Value | Description
\r
3189 * :----------------------------------|:------|:-----------------------------
\r
3190 * ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3191 * ALT_QSPI_IRQMSK_ILLEGALACC_E_END | 0x1 | Enable Interrupt
\r
3193 * Field Access Macros:
\r
3197 * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC
\r
3199 * Disable Interrupt by Masking
\r
3201 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0
\r
3203 * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC
\r
3205 * Enable Interrupt
\r
3207 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1
\r
3209 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
\r
3210 #define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5
\r
3211 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
\r
3212 #define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5
\r
3213 /* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
\r
3214 #define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1
\r
3215 /* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */
\r
3216 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020
\r
3217 /* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */
\r
3218 #define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf
\r
3219 /* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */
\r
3220 #define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0
\r
3221 /* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */
\r
3222 #define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
\r
3223 /* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */
\r
3224 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
\r
3227 * Field : Transfer Watermark Breach Mask - indxfrlvl
\r
3229 * Field Enumeration Values:
\r
3231 * Enum | Value | Description
\r
3232 * :---------------------------------|:------|:-----------------------------
\r
3233 * ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3234 * ALT_QSPI_IRQMSK_INDXFRLVL_E_END | 0x1 | Enable Interrupt
\r
3236 * Field Access Macros:
\r
3240 * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL
\r
3242 * Disable Interrupt by Masking
\r
3244 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0
\r
3246 * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL
\r
3248 * Enable Interrupt
\r
3250 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1
\r
3252 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
\r
3253 #define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6
\r
3254 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
\r
3255 #define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6
\r
3256 /* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
\r
3257 #define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1
\r
3258 /* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */
\r
3259 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040
\r
3260 /* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */
\r
3261 #define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf
\r
3262 /* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */
\r
3263 #define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0
\r
3264 /* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */
\r
3265 #define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
\r
3266 /* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */
\r
3267 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
\r
3270 * Field : Receive Overflow Mask - rxover
\r
3272 * Field Enumeration Values:
\r
3274 * Enum | Value | Description
\r
3275 * :------------------------------|:------|:-----------------------------
\r
3276 * ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3277 * ALT_QSPI_IRQMSK_RXOVER_E_END | 0x1 | Enable Interrupt
\r
3279 * Field Access Macros:
\r
3283 * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER
\r
3285 * Disable Interrupt by Masking
\r
3287 #define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0
\r
3289 * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER
\r
3291 * Enable Interrupt
\r
3293 #define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1
\r
3295 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */
\r
3296 #define ALT_QSPI_IRQMSK_RXOVER_LSB 7
\r
3297 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */
\r
3298 #define ALT_QSPI_IRQMSK_RXOVER_MSB 7
\r
3299 /* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */
\r
3300 #define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1
\r
3301 /* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */
\r
3302 #define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080
\r
3303 /* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */
\r
3304 #define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f
\r
3305 /* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */
\r
3306 #define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0
\r
3307 /* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */
\r
3308 #define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
\r
3309 /* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */
\r
3310 #define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
\r
3313 * Field : Transmit FIFO Threshold Compare Mask - txthreshcmp
\r
3315 * Field Enumeration Values:
\r
3317 * Enum | Value | Description
\r
3318 * :-----------------------------------|:------|:-----------------------------
\r
3319 * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3320 * ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END | 0x1 | Enable Interrupt
\r
3322 * Field Access Macros:
\r
3326 * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP
\r
3328 * Disable Interrupt by Masking
\r
3330 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0
\r
3332 * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP
\r
3334 * Enable Interrupt
\r
3336 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1
\r
3338 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
\r
3339 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8
\r
3340 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
\r
3341 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8
\r
3342 /* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
\r
3343 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1
\r
3344 /* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */
\r
3345 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100
\r
3346 /* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */
\r
3347 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff
\r
3348 /* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */
\r
3349 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0
\r
3350 /* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */
\r
3351 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
\r
3352 /* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */
\r
3353 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
\r
3356 * Field : Transmit FIFO Full Mask - txfull
\r
3358 * Field Enumeration Values:
\r
3360 * Enum | Value | Description
\r
3361 * :------------------------------|:------|:-----------------------------
\r
3362 * ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3363 * ALT_QSPI_IRQMSK_TXFULL_E_END | 0x1 | Enable Interrupt
\r
3365 * Field Access Macros:
\r
3369 * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL
\r
3371 * Disable Interrupt by Masking
\r
3373 #define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0
\r
3375 * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL
\r
3377 * Enable Interrupt
\r
3379 #define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1
\r
3381 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */
\r
3382 #define ALT_QSPI_IRQMSK_TXFULL_LSB 9
\r
3383 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */
\r
3384 #define ALT_QSPI_IRQMSK_TXFULL_MSB 9
\r
3385 /* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */
\r
3386 #define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1
\r
3387 /* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */
\r
3388 #define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200
\r
3389 /* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */
\r
3390 #define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff
\r
3391 /* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */
\r
3392 #define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0
\r
3393 /* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */
\r
3394 #define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
\r
3395 /* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */
\r
3396 #define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
\r
3399 * Field : Receive FIFO Threshold Compare Mask - rxthreshcmp
\r
3401 * Field Enumeration Values:
\r
3403 * Enum | Value | Description
\r
3404 * :-----------------------------------|:------|:-----------------------------
\r
3405 * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3406 * ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END | 0x1 | Enable Interrupt
\r
3408 * Field Access Macros:
\r
3412 * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP
\r
3414 * Disable Interrupt by Masking
\r
3416 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0
\r
3418 * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP
\r
3420 * Enable Interrupt
\r
3422 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1
\r
3424 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
\r
3425 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10
\r
3426 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
\r
3427 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10
\r
3428 /* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
\r
3429 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1
\r
3430 /* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */
\r
3431 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400
\r
3432 /* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */
\r
3433 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff
\r
3434 /* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */
\r
3435 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0
\r
3436 /* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */
\r
3437 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
\r
3438 /* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */
\r
3439 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
\r
3442 * Field : Receive FIFO full Mask - rxfull
\r
3444 * Field Enumeration Values:
\r
3446 * Enum | Value | Description
\r
3447 * :------------------------------|:------|:-----------------------------
\r
3448 * ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3449 * ALT_QSPI_IRQMSK_RXFULL_E_END | 0x1 | Enable Interrupt
\r
3451 * Field Access Macros:
\r
3455 * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL
\r
3457 * Disable Interrupt by Masking
\r
3459 #define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0
\r
3461 * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL
\r
3463 * Enable Interrupt
\r
3465 #define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1
\r
3467 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */
\r
3468 #define ALT_QSPI_IRQMSK_RXFULL_LSB 11
\r
3469 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */
\r
3470 #define ALT_QSPI_IRQMSK_RXFULL_MSB 11
\r
3471 /* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */
\r
3472 #define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1
\r
3473 /* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */
\r
3474 #define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800
\r
3475 /* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */
\r
3476 #define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff
\r
3477 /* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */
\r
3478 #define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0
\r
3479 /* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */
\r
3480 #define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
\r
3481 /* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */
\r
3482 #define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
\r
3485 * Field : Indirect Read Partition overflow mask - indsramfull
\r
3487 * Field Enumeration Values:
\r
3489 * Enum | Value | Description
\r
3490 * :-----------------------------------|:------|:-----------------------------
\r
3491 * ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0 | Disable Interrupt by Masking
\r
3492 * ALT_QSPI_IRQMSK_INDSRAMFULL_E_END | 0x1 | Enable Interrupt
\r
3494 * Field Access Macros:
\r
3498 * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL
\r
3500 * Disable Interrupt by Masking
\r
3502 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0
\r
3504 * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL
\r
3506 * Enable Interrupt
\r
3508 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1
\r
3510 /* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
\r
3511 #define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12
\r
3512 /* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
\r
3513 #define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12
\r
3514 /* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
\r
3515 #define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1
\r
3516 /* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */
\r
3517 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000
\r
3518 /* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */
\r
3519 #define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff
\r
3520 /* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */
\r
3521 #define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0
\r
3522 /* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */
\r
3523 #define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
\r
3524 /* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */
\r
3525 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
\r
3527 #ifndef __ASSEMBLY__
\r
3529 * WARNING: The C register and register group struct declarations are provided for
\r
3530 * convenience and illustrative purposes. They should, however, be used with
\r
3531 * caution as the C language standard provides no guarantees about the alignment or
\r
3532 * atomicity of device memory accesses. The recommended practice for writing
\r
3533 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
3534 * alt_write_word() functions.
\r
3536 * The struct declaration for register ALT_QSPI_IRQMSK.
\r
3538 struct ALT_QSPI_IRQMSK_s
\r
3540 uint32_t : 1; /* *UNDEFINED* */
\r
3541 uint32_t underflowdet : 1; /* Underflow Detected Mask */
\r
3542 uint32_t indopdone : 1; /* Mask */
\r
3543 uint32_t indrdreject : 1; /* Indirect Read Reject Mask */
\r
3544 uint32_t protwrattempt : 1; /* Protected Area Write Attempt Mask */
\r
3545 uint32_t illegalacc : 1; /* Illegal Access Detected Mask */
\r
3546 uint32_t indxfrlvl : 1; /* Transfer Watermark Breach Mask */
\r
3547 uint32_t rxover : 1; /* Receive Overflow Mask */
\r
3548 uint32_t txthreshcmp : 1; /* Transmit FIFO Threshold Compare Mask */
\r
3549 uint32_t txfull : 1; /* Transmit FIFO Full Mask */
\r
3550 uint32_t rxthreshcmp : 1; /* Receive FIFO Threshold Compare Mask */
\r
3551 uint32_t rxfull : 1; /* Receive FIFO full Mask */
\r
3552 uint32_t indsramfull : 1; /* Indirect Read Partition overflow mask */
\r
3553 uint32_t : 19; /* *UNDEFINED* */
\r
3556 /* The typedef declaration for register ALT_QSPI_IRQMSK. */
\r
3557 typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t;
\r
3558 #endif /* __ASSEMBLY__ */
\r
3560 /* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */
\r
3561 #define ALT_QSPI_IRQMSK_OFST 0x44
\r
3564 * Register : Lower Write Protection Register - lowwrprot
\r
3568 * Bits | Access | Reset | Description
\r
3569 * :-------|:-------|:------|:-------------
\r
3570 * [31:0] | RW | 0x0 | Block Number
\r
3574 * Field : Block Number - subsector
\r
3576 * The block number that defines the lower block in the range of blocks that is to
\r
3577 * be locked from writing. The definition of a block in terms of number of bytes is
\r
3578 * programmable via the Device Size Configuration register.
\r
3580 * Field Access Macros:
\r
3583 /* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
\r
3584 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
\r
3585 /* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
\r
3586 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
\r
3587 /* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
\r
3588 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
\r
3589 /* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */
\r
3590 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
\r
3591 /* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */
\r
3592 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
\r
3593 /* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */
\r
3594 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
\r
3595 /* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */
\r
3596 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
\r
3597 /* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */
\r
3598 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
\r
3600 #ifndef __ASSEMBLY__
\r
3602 * WARNING: The C register and register group struct declarations are provided for
\r
3603 * convenience and illustrative purposes. They should, however, be used with
\r
3604 * caution as the C language standard provides no guarantees about the alignment or
\r
3605 * atomicity of device memory accesses. The recommended practice for writing
\r
3606 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
3607 * alt_write_word() functions.
\r
3609 * The struct declaration for register ALT_QSPI_LOWWRPROT.
\r
3611 struct ALT_QSPI_LOWWRPROT_s
\r
3613 uint32_t subsector : 32; /* Block Number */
\r
3616 /* The typedef declaration for register ALT_QSPI_LOWWRPROT. */
\r
3617 typedef volatile struct ALT_QSPI_LOWWRPROT_s ALT_QSPI_LOWWRPROT_t;
\r
3618 #endif /* __ASSEMBLY__ */
\r
3620 /* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */
\r
3621 #define ALT_QSPI_LOWWRPROT_OFST 0x50
\r
3624 * Register : Upper Write Protection Register - uppwrprot
\r
3628 * Bits | Access | Reset | Description
\r
3629 * :-------|:-------|:------|:-------------
\r
3630 * [31:0] | RW | 0x0 | Block Number
\r
3634 * Field : Block Number - subsector
\r
3636 * The block number that defines the upper block in the range of blocks that is to
\r
3637 * be locked from writing. The definition of a block in terms of number of bytes is
\r
3638 * programmable via the Device Size Configuration register.
\r
3640 * Field Access Macros:
\r
3643 /* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
\r
3644 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
\r
3645 /* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
\r
3646 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
\r
3647 /* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
\r
3648 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
\r
3649 /* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */
\r
3650 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
\r
3651 /* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */
\r
3652 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
\r
3653 /* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */
\r
3654 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
\r
3655 /* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */
\r
3656 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
\r
3657 /* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */
\r
3658 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
\r
3660 #ifndef __ASSEMBLY__
\r
3662 * WARNING: The C register and register group struct declarations are provided for
\r
3663 * convenience and illustrative purposes. They should, however, be used with
\r
3664 * caution as the C language standard provides no guarantees about the alignment or
\r
3665 * atomicity of device memory accesses. The recommended practice for writing
\r
3666 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
3667 * alt_write_word() functions.
\r
3669 * The struct declaration for register ALT_QSPI_UPPWRPROT.
\r
3671 struct ALT_QSPI_UPPWRPROT_s
\r
3673 uint32_t subsector : 32; /* Block Number */
\r
3676 /* The typedef declaration for register ALT_QSPI_UPPWRPROT. */
\r
3677 typedef volatile struct ALT_QSPI_UPPWRPROT_s ALT_QSPI_UPPWRPROT_t;
\r
3678 #endif /* __ASSEMBLY__ */
\r
3680 /* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */
\r
3681 #define ALT_QSPI_UPPWRPROT_OFST 0x54
\r
3684 * Register : Write Protection Register - wrprot
\r
3688 * Bits | Access | Reset | Description
\r
3689 * :-------|:-------|:------|:-------------------------------
\r
3690 * [0] | RW | 0x0 | Write Protection Inversion Bit
\r
3691 * [1] | RW | 0x0 | Write Protection Enable Bit
\r
3692 * [31:2] | ??? | 0x0 | *UNDEFINED*
\r
3696 * Field : Write Protection Inversion Bit - inv
\r
3698 * When enabled, the protection region defined in the lower and upper write
\r
3699 * protection registers is inverted meaning it is the region that the system is
\r
3700 * permitted to write to. When disabled, the protection region defined in the lower
\r
3701 * and upper write protection registers is the region that the system is not
\r
3702 * permitted to write to.
\r
3704 * Field Enumeration Values:
\r
3706 * Enum | Value | Description
\r
3707 * :--------------------------|:------|:-------------------------
\r
3708 * ALT_QSPI_WRPROT_INV_E_EN | 0x1 | Write Region allowed
\r
3709 * ALT_QSPI_WRPROT_INV_E_DIS | 0x0 | Write Region not allowed
\r
3711 * Field Access Macros:
\r
3715 * Enumerated value for register field ALT_QSPI_WRPROT_INV
\r
3717 * Write Region allowed
\r
3719 #define ALT_QSPI_WRPROT_INV_E_EN 0x1
\r
3721 * Enumerated value for register field ALT_QSPI_WRPROT_INV
\r
3723 * Write Region not allowed
\r
3725 #define ALT_QSPI_WRPROT_INV_E_DIS 0x0
\r
3727 /* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */
\r
3728 #define ALT_QSPI_WRPROT_INV_LSB 0
\r
3729 /* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */
\r
3730 #define ALT_QSPI_WRPROT_INV_MSB 0
\r
3731 /* The width in bits of the ALT_QSPI_WRPROT_INV register field. */
\r
3732 #define ALT_QSPI_WRPROT_INV_WIDTH 1
\r
3733 /* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */
\r
3734 #define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
\r
3735 /* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */
\r
3736 #define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
\r
3737 /* The reset value of the ALT_QSPI_WRPROT_INV register field. */
\r
3738 #define ALT_QSPI_WRPROT_INV_RESET 0x0
\r
3739 /* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */
\r
3740 #define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
\r
3741 /* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */
\r
3742 #define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
\r
3745 * Field : Write Protection Enable Bit - en
\r
3747 * When enabled, any AHB write access with an address within the protection region
\r
3748 * defined in the lower and upper write protection registers is rejected. An AHB
\r
3749 * error response is generated and an interrupt source triggered. When disabled,
\r
3750 * the protection region is disabled.
\r
3752 * Field Enumeration Values:
\r
3754 * Enum | Value | Description
\r
3755 * :-------------------------|:------|:---------------------------
\r
3756 * ALT_QSPI_WRPROT_EN_E_EN | 0x1 | AHB Write Access rejected
\r
3757 * ALT_QSPI_WRPROT_EN_E_DIS | 0x0 | Protection Region Disabled
\r
3759 * Field Access Macros:
\r
3763 * Enumerated value for register field ALT_QSPI_WRPROT_EN
\r
3765 * AHB Write Access rejected
\r
3767 #define ALT_QSPI_WRPROT_EN_E_EN 0x1
\r
3769 * Enumerated value for register field ALT_QSPI_WRPROT_EN
\r
3771 * Protection Region Disabled
\r
3773 #define ALT_QSPI_WRPROT_EN_E_DIS 0x0
\r
3775 /* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */
\r
3776 #define ALT_QSPI_WRPROT_EN_LSB 1
\r
3777 /* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */
\r
3778 #define ALT_QSPI_WRPROT_EN_MSB 1
\r
3779 /* The width in bits of the ALT_QSPI_WRPROT_EN register field. */
\r
3780 #define ALT_QSPI_WRPROT_EN_WIDTH 1
\r
3781 /* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */
\r
3782 #define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
\r
3783 /* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */
\r
3784 #define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
\r
3785 /* The reset value of the ALT_QSPI_WRPROT_EN register field. */
\r
3786 #define ALT_QSPI_WRPROT_EN_RESET 0x0
\r
3787 /* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */
\r
3788 #define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
\r
3789 /* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */
\r
3790 #define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
\r
3792 #ifndef __ASSEMBLY__
\r
3794 * WARNING: The C register and register group struct declarations are provided for
\r
3795 * convenience and illustrative purposes. They should, however, be used with
\r
3796 * caution as the C language standard provides no guarantees about the alignment or
\r
3797 * atomicity of device memory accesses. The recommended practice for writing
\r
3798 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
3799 * alt_write_word() functions.
\r
3801 * The struct declaration for register ALT_QSPI_WRPROT.
\r
3803 struct ALT_QSPI_WRPROT_s
\r
3805 uint32_t inv : 1; /* Write Protection Inversion Bit */
\r
3806 uint32_t en : 1; /* Write Protection Enable Bit */
\r
3807 uint32_t : 30; /* *UNDEFINED* */
\r
3810 /* The typedef declaration for register ALT_QSPI_WRPROT. */
\r
3811 typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t;
\r
3812 #endif /* __ASSEMBLY__ */
\r
3814 /* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */
\r
3815 #define ALT_QSPI_WRPROT_OFST 0x58
\r
3818 * Register : Indirect Read Transfer Register - indrd
\r
3822 * Bits | Access | Reset | Description
\r
3823 * :-------|:-------|:--------|:--------------------------------
\r
3824 * [0] | RW | 0x0 | Start Indirect Read
\r
3825 * [1] | RW | 0x0 | Cancel Indirect Read
\r
3826 * [2] | R | Unknown | Indirect Read Status
\r
3827 * [3] | RW | Unknown | SRAM Full
\r
3828 * [4] | R | Unknown | Queued Indirect Read Operations
\r
3829 * [5] | RW | Unknown | Indirect Completion Status
\r
3830 * [7:6] | R | Unknown | Completed Indirect Operations
\r
3831 * [31:8] | ??? | 0x0 | *UNDEFINED*
\r
3835 * Field : Start Indirect Read - start
\r
3837 * When this bit is enabled, it will trigger an indirect read operation. The
\r
3838 * assumption is that the indirect start address and the indirect number of bytes
\r
3839 * register is setup before triggering the indirect read operation.
\r
3841 * Field Enumeration Values:
\r
3843 * Enum | Value | Description
\r
3844 * :----------------------------|:------|:----------------------
\r
3845 * ALT_QSPI_INDRD_START_E_END | 0x1 | Trigger Indirect Read
\r
3846 * ALT_QSPI_INDRD_START_E_DISD | 0x0 | No Indirect Read
\r
3848 * Field Access Macros:
\r
3852 * Enumerated value for register field ALT_QSPI_INDRD_START
\r
3854 * Trigger Indirect Read
\r
3856 #define ALT_QSPI_INDRD_START_E_END 0x1
\r
3858 * Enumerated value for register field ALT_QSPI_INDRD_START
\r
3860 * No Indirect Read
\r
3862 #define ALT_QSPI_INDRD_START_E_DISD 0x0
\r
3864 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */
\r
3865 #define ALT_QSPI_INDRD_START_LSB 0
\r
3866 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */
\r
3867 #define ALT_QSPI_INDRD_START_MSB 0
\r
3868 /* The width in bits of the ALT_QSPI_INDRD_START register field. */
\r
3869 #define ALT_QSPI_INDRD_START_WIDTH 1
\r
3870 /* The mask used to set the ALT_QSPI_INDRD_START register field value. */
\r
3871 #define ALT_QSPI_INDRD_START_SET_MSK 0x00000001
\r
3872 /* The mask used to clear the ALT_QSPI_INDRD_START register field value. */
\r
3873 #define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
\r
3874 /* The reset value of the ALT_QSPI_INDRD_START register field. */
\r
3875 #define ALT_QSPI_INDRD_START_RESET 0x0
\r
3876 /* Extracts the ALT_QSPI_INDRD_START field value from a register. */
\r
3877 #define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
\r
3878 /* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */
\r
3879 #define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
\r
3882 * Field : Cancel Indirect Read - cancel
\r
3884 * This bit will cancel all ongoing indirect read operations.
\r
3886 * Field Enumeration Values:
\r
3888 * Enum | Value | Description
\r
3889 * :---------------------------------|:------|:----------------------------
\r
3890 * ALT_QSPI_INDRD_CANCEL_E_CANCEL | 0x1 | Cancel Indirect Read
\r
3891 * ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0 | Do Not Cancel Indirect Read
\r
3893 * Field Access Macros:
\r
3897 * Enumerated value for register field ALT_QSPI_INDRD_CANCEL
\r
3899 * Cancel Indirect Read
\r
3901 #define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
\r
3903 * Enumerated value for register field ALT_QSPI_INDRD_CANCEL
\r
3905 * Do Not Cancel Indirect Read
\r
3907 #define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
\r
3909 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */
\r
3910 #define ALT_QSPI_INDRD_CANCEL_LSB 1
\r
3911 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */
\r
3912 #define ALT_QSPI_INDRD_CANCEL_MSB 1
\r
3913 /* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */
\r
3914 #define ALT_QSPI_INDRD_CANCEL_WIDTH 1
\r
3915 /* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */
\r
3916 #define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
\r
3917 /* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */
\r
3918 #define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
\r
3919 /* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */
\r
3920 #define ALT_QSPI_INDRD_CANCEL_RESET 0x0
\r
3921 /* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */
\r
3922 #define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
\r
3923 /* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */
\r
3924 #define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
\r
3927 * Field : Indirect Read Status - rd_status
\r
3929 * Indirect read operation in progress (status)
\r
3931 * Field Enumeration Values:
\r
3933 * Enum | Value | Description
\r
3934 * :----------------------------------|:------|:------------------------------
\r
3935 * ALT_QSPI_INDRD_RD_STAT_E_RDOP | 0x1 | Read Operation in progress
\r
3936 * ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0 | No read operation in progress
\r
3938 * Field Access Macros:
\r
3942 * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT
\r
3944 * Read Operation in progress
\r
3946 #define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1
\r
3948 * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT
\r
3950 * No read operation in progress
\r
3952 #define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0
\r
3954 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */
\r
3955 #define ALT_QSPI_INDRD_RD_STAT_LSB 2
\r
3956 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */
\r
3957 #define ALT_QSPI_INDRD_RD_STAT_MSB 2
\r
3958 /* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */
\r
3959 #define ALT_QSPI_INDRD_RD_STAT_WIDTH 1
\r
3960 /* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */
\r
3961 #define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004
\r
3962 /* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */
\r
3963 #define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb
\r
3964 /* The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN. */
\r
3965 #define ALT_QSPI_INDRD_RD_STAT_RESET 0x0
\r
3966 /* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */
\r
3967 #define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2)
\r
3968 /* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */
\r
3969 #define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004)
\r
3972 * Field : SRAM Full - sram_full
\r
3974 * SRAM full and unable to immediately complete an indirect operation. Write a 1 to
\r
3975 * this field to clear it. ; indirect operation (status)
\r
3977 * Field Enumeration Values:
\r
3979 * Enum | Value | Description
\r
3980 * :------------------------------------|:------|:-----------------------------------
\r
3981 * ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1 | Sram Full- Cant complete operation
\r
3982 * ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0 | SRram Not Full
\r
3984 * Field Access Macros:
\r
3988 * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
\r
3990 * Sram Full- Cant complete operation
\r
3992 #define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
\r
3994 * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
\r
3998 #define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
\r
4000 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */
\r
4001 #define ALT_QSPI_INDRD_SRAM_FULL_LSB 3
\r
4002 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */
\r
4003 #define ALT_QSPI_INDRD_SRAM_FULL_MSB 3
\r
4004 /* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */
\r
4005 #define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
\r
4006 /* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */
\r
4007 #define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
\r
4008 /* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */
\r
4009 #define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
\r
4010 /* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN. */
\r
4011 #define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
\r
4012 /* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */
\r
4013 #define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
\r
4014 /* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */
\r
4015 #define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
\r
4018 * Field : Queued Indirect Read Operations - rd_queued
\r
4020 * Two indirect read operations have been queued
\r
4022 * Field Enumeration Values:
\r
4024 * Enum | Value | Description
\r
4025 * :----------------------------------------|:------|:---------------------
\r
4026 * ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1 | Queued Indirect Read
\r
4027 * ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION | 0x0 | No Queued Read
\r
4029 * Field Access Macros:
\r
4033 * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
\r
4035 * Queued Indirect Read
\r
4037 #define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
\r
4039 * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
\r
4043 #define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
\r
4045 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */
\r
4046 #define ALT_QSPI_INDRD_RD_QUEUED_LSB 4
\r
4047 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */
\r
4048 #define ALT_QSPI_INDRD_RD_QUEUED_MSB 4
\r
4049 /* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */
\r
4050 #define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
\r
4051 /* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */
\r
4052 #define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
\r
4053 /* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */
\r
4054 #define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
\r
4055 /* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN. */
\r
4056 #define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
\r
4057 /* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */
\r
4058 #define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
\r
4059 /* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */
\r
4060 #define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
\r
4063 * Field : Indirect Completion Status - ind_ops_done_status
\r
4065 * This field is set to 1 when an indirect operation has completed. Write a 1 to
\r
4066 * this field to clear it.
\r
4068 * Field Enumeration Values:
\r
4070 * Enum | Value | Description
\r
4071 * :--------------------------------------------|:------|:-------------------------------
\r
4072 * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP | 0x1 | Indirect Op Complete operation
\r
4073 * ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0 | Indirect Op Not Complete
\r
4075 * Field Access Macros:
\r
4079 * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT
\r
4081 * Indirect Op Complete operation
\r
4083 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1
\r
4085 * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT
\r
4087 * Indirect Op Not Complete
\r
4089 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0
\r
4091 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
\r
4092 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5
\r
4093 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
\r
4094 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5
\r
4095 /* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */
\r
4096 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1
\r
4097 /* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */
\r
4098 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020
\r
4099 /* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */
\r
4100 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf
\r
4101 /* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN. */
\r
4102 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0
\r
4103 /* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */
\r
4104 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5)
\r
4105 /* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */
\r
4106 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020)
\r
4109 * Field : Completed Indirect Operations - num_ind_ops_done
\r
4111 * This field contains the number of indirect operations which have been completed.
\r
4112 * This is used in conjunction with the indirect completion status field (bit 5).
\r
4114 * Field Access Macros:
\r
4117 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
\r
4118 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
\r
4119 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
\r
4120 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
\r
4121 /* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */
\r
4122 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
\r
4123 /* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */
\r
4124 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
\r
4125 /* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */
\r
4126 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
\r
4127 /* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN. */
\r
4128 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
\r
4129 /* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */
\r
4130 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
\r
4131 /* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */
\r
4132 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
\r
4134 #ifndef __ASSEMBLY__
\r
4136 * WARNING: The C register and register group struct declarations are provided for
\r
4137 * convenience and illustrative purposes. They should, however, be used with
\r
4138 * caution as the C language standard provides no guarantees about the alignment or
\r
4139 * atomicity of device memory accesses. The recommended practice for writing
\r
4140 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
4141 * alt_write_word() functions.
\r
4143 * The struct declaration for register ALT_QSPI_INDRD.
\r
4145 struct ALT_QSPI_INDRD_s
\r
4147 uint32_t start : 1; /* Start Indirect Read */
\r
4148 uint32_t cancel : 1; /* Cancel Indirect Read */
\r
4149 const uint32_t rd_status : 1; /* Indirect Read Status */
\r
4150 uint32_t sram_full : 1; /* SRAM Full */
\r
4151 const uint32_t rd_queued : 1; /* Queued Indirect Read Operations */
\r
4152 uint32_t ind_ops_done_status : 1; /* Indirect Completion Status */
\r
4153 const uint32_t num_ind_ops_done : 2; /* Completed Indirect Operations */
\r
4154 uint32_t : 24; /* *UNDEFINED* */
\r
4157 /* The typedef declaration for register ALT_QSPI_INDRD. */
\r
4158 typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t;
\r
4159 #endif /* __ASSEMBLY__ */
\r
4161 /* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */
\r
4162 #define ALT_QSPI_INDRD_OFST 0x60
\r
4165 * Register : Indirect Read Transfer Watermark Register - indrdwater
\r
4169 * Bits | Access | Reset | Description
\r
4170 * :-------|:-------|:------|:----------------
\r
4171 * [31:0] | RW | 0x0 | Watermark Value
\r
4175 * Field : Watermark Value - level
\r
4177 * This represents the minimum fill level of the SRAM before a DMA peripheral
\r
4178 * access is permitted. When the SRAM fill level passes the watermark, an interrupt
\r
4179 * is also generated. This field can be disabled by writing a value of all zeroes.
\r
4180 * The units of this register are BYTES
\r
4182 * Field Access Macros:
\r
4185 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */
\r
4186 #define ALT_QSPI_INDRDWATER_LEVEL_LSB 0
\r
4187 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */
\r
4188 #define ALT_QSPI_INDRDWATER_LEVEL_MSB 31
\r
4189 /* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */
\r
4190 #define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
\r
4191 /* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */
\r
4192 #define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
\r
4193 /* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */
\r
4194 #define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
\r
4195 /* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */
\r
4196 #define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
\r
4197 /* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */
\r
4198 #define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
\r
4199 /* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */
\r
4200 #define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
\r
4202 #ifndef __ASSEMBLY__
\r
4204 * WARNING: The C register and register group struct declarations are provided for
\r
4205 * convenience and illustrative purposes. They should, however, be used with
\r
4206 * caution as the C language standard provides no guarantees about the alignment or
\r
4207 * atomicity of device memory accesses. The recommended practice for writing
\r
4208 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
4209 * alt_write_word() functions.
\r
4211 * The struct declaration for register ALT_QSPI_INDRDWATER.
\r
4213 struct ALT_QSPI_INDRDWATER_s
\r
4215 uint32_t level : 32; /* Watermark Value */
\r
4218 /* The typedef declaration for register ALT_QSPI_INDRDWATER. */
\r
4219 typedef volatile struct ALT_QSPI_INDRDWATER_s ALT_QSPI_INDRDWATER_t;
\r
4220 #endif /* __ASSEMBLY__ */
\r
4222 /* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */
\r
4223 #define ALT_QSPI_INDRDWATER_OFST 0x64
\r
4226 * Register : Indirect Read Transfer Start Address Register - indrdstaddr
\r
4230 * Bits | Access | Reset | Description
\r
4231 * :-------|:-------|:------|:---------------------------------
\r
4232 * [31:0] | RW | 0x0 | Start Address of Indirect Access
\r
4236 * Field : Start Address of Indirect Access - addr
\r
4238 * This is the start address from which the indirect access will commence its READ
\r
4241 * Field Access Macros:
\r
4244 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
\r
4245 #define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
\r
4246 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
\r
4247 #define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
\r
4248 /* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
\r
4249 #define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
\r
4250 /* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */
\r
4251 #define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
\r
4252 /* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */
\r
4253 #define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
\r
4254 /* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */
\r
4255 #define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
\r
4256 /* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */
\r
4257 #define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
\r
4258 /* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */
\r
4259 #define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
\r
4261 #ifndef __ASSEMBLY__
\r
4263 * WARNING: The C register and register group struct declarations are provided for
\r
4264 * convenience and illustrative purposes. They should, however, be used with
\r
4265 * caution as the C language standard provides no guarantees about the alignment or
\r
4266 * atomicity of device memory accesses. The recommended practice for writing
\r
4267 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
4268 * alt_write_word() functions.
\r
4270 * The struct declaration for register ALT_QSPI_INDRDSTADDR.
\r
4272 struct ALT_QSPI_INDRDSTADDR_s
\r
4274 uint32_t addr : 32; /* Start Address of Indirect Access */
\r
4277 /* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */
\r
4278 typedef volatile struct ALT_QSPI_INDRDSTADDR_s ALT_QSPI_INDRDSTADDR_t;
\r
4279 #endif /* __ASSEMBLY__ */
\r
4281 /* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */
\r
4282 #define ALT_QSPI_INDRDSTADDR_OFST 0x68
\r
4285 * Register : Indirect Read Transfer Number Bytes Register - indrdcnt
\r
4289 * Bits | Access | Reset | Description
\r
4290 * :-------|:-------|:------|:---------------
\r
4291 * [31:0] | RW | 0x0 | Indirect Count
\r
4295 * Field : Indirect Count - value
\r
4297 * This is the number of bytes that the indirect access will consume. This can be
\r
4298 * bigger than the configured size of SRAM.
\r
4300 * Field Access Macros:
\r
4303 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */
\r
4304 #define ALT_QSPI_INDRDCNT_VALUE_LSB 0
\r
4305 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */
\r
4306 #define ALT_QSPI_INDRDCNT_VALUE_MSB 31
\r
4307 /* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */
\r
4308 #define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
\r
4309 /* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */
\r
4310 #define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
\r
4311 /* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */
\r
4312 #define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
\r
4313 /* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */
\r
4314 #define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
\r
4315 /* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */
\r
4316 #define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
\r
4317 /* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */
\r
4318 #define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
\r
4320 #ifndef __ASSEMBLY__
\r
4322 * WARNING: The C register and register group struct declarations are provided for
\r
4323 * convenience and illustrative purposes. They should, however, be used with
\r
4324 * caution as the C language standard provides no guarantees about the alignment or
\r
4325 * atomicity of device memory accesses. The recommended practice for writing
\r
4326 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
4327 * alt_write_word() functions.
\r
4329 * The struct declaration for register ALT_QSPI_INDRDCNT.
\r
4331 struct ALT_QSPI_INDRDCNT_s
\r
4333 uint32_t value : 32; /* Indirect Count */
\r
4336 /* The typedef declaration for register ALT_QSPI_INDRDCNT. */
\r
4337 typedef volatile struct ALT_QSPI_INDRDCNT_s ALT_QSPI_INDRDCNT_t;
\r
4338 #endif /* __ASSEMBLY__ */
\r
4340 /* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */
\r
4341 #define ALT_QSPI_INDRDCNT_OFST 0x6c
\r
4344 * Register : Indirect Write Transfer Register - indwr
\r
4348 * Bits | Access | Reset | Description
\r
4349 * :-------|:-------|:--------|:---------------------------------
\r
4350 * [0] | RW | 0x0 | Start Indirect Write
\r
4351 * [1] | RW | 0x0 | Cancel Indirect Write
\r
4352 * [2] | R | Unknown | Indirect Write Status
\r
4353 * [3] | R | 0x0 | Reserved
\r
4354 * [4] | R | Unknown | Queued Indirect Write Operations
\r
4355 * [5] | RW | Unknown | Indirect Completion Status
\r
4356 * [7:6] | R | Unknown | Completed Indirect Operations
\r
4357 * [31:8] | ??? | 0x0 | *UNDEFINED*
\r
4361 * Field : Start Indirect Write - start
\r
4363 * Writing a 1 to this bit will trigger an indirect write operation. The assumption
\r
4364 * is that the indirect start address and the indirect number of bytes register is
\r
4365 * setup before triggering the indirect write operation.
\r
4367 * Field Enumeration Values:
\r
4369 * Enum | Value | Description
\r
4370 * :----------------------------|:------|:---------------------------------
\r
4371 * ALT_QSPI_INDWR_START_E_END | 0x1 | Trigger indirect write operation
\r
4372 * ALT_QSPI_INDWR_START_E_DISD | 0x0 | No Action
\r
4374 * Field Access Macros:
\r
4378 * Enumerated value for register field ALT_QSPI_INDWR_START
\r
4380 * Trigger indirect write operation
\r
4382 #define ALT_QSPI_INDWR_START_E_END 0x1
\r
4384 * Enumerated value for register field ALT_QSPI_INDWR_START
\r
4388 #define ALT_QSPI_INDWR_START_E_DISD 0x0
\r
4390 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */
\r
4391 #define ALT_QSPI_INDWR_START_LSB 0
\r
4392 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */
\r
4393 #define ALT_QSPI_INDWR_START_MSB 0
\r
4394 /* The width in bits of the ALT_QSPI_INDWR_START register field. */
\r
4395 #define ALT_QSPI_INDWR_START_WIDTH 1
\r
4396 /* The mask used to set the ALT_QSPI_INDWR_START register field value. */
\r
4397 #define ALT_QSPI_INDWR_START_SET_MSK 0x00000001
\r
4398 /* The mask used to clear the ALT_QSPI_INDWR_START register field value. */
\r
4399 #define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
\r
4400 /* The reset value of the ALT_QSPI_INDWR_START register field. */
\r
4401 #define ALT_QSPI_INDWR_START_RESET 0x0
\r
4402 /* Extracts the ALT_QSPI_INDWR_START field value from a register. */
\r
4403 #define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
\r
4404 /* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */
\r
4405 #define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
\r
4408 * Field : Cancel Indirect Write - cancel
\r
4410 * Writing a 1 to this bit will cancel all ongoing indirect write operations.
\r
4412 * Field Enumeration Values:
\r
4414 * Enum | Value | Description
\r
4415 * :-----------------------------------|:------|:--------------------------------
\r
4416 * ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1 | Cancel Indirect write operation
\r
4417 * ALT_QSPI_INDWR_CANCEL_E_NOACTION | 0x0 | No Action
\r
4419 * Field Access Macros:
\r
4423 * Enumerated value for register field ALT_QSPI_INDWR_CANCEL
\r
4425 * Cancel Indirect write operation
\r
4427 #define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
\r
4429 * Enumerated value for register field ALT_QSPI_INDWR_CANCEL
\r
4433 #define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
\r
4435 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */
\r
4436 #define ALT_QSPI_INDWR_CANCEL_LSB 1
\r
4437 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */
\r
4438 #define ALT_QSPI_INDWR_CANCEL_MSB 1
\r
4439 /* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */
\r
4440 #define ALT_QSPI_INDWR_CANCEL_WIDTH 1
\r
4441 /* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */
\r
4442 #define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
\r
4443 /* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */
\r
4444 #define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
\r
4445 /* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */
\r
4446 #define ALT_QSPI_INDWR_CANCEL_RESET 0x0
\r
4447 /* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */
\r
4448 #define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
\r
4449 /* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */
\r
4450 #define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
\r
4453 * Field : Indirect Write Status - rdstat
\r
4455 * Indirect write operation in progress (status)
\r
4457 * Field Enumeration Values:
\r
4459 * Enum | Value | Description
\r
4460 * :----------------------------------|:------|:-------------------------
\r
4461 * ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1 | Indirect write operation
\r
4462 * ALT_QSPI_INDWR_RDSTAT_E_NOACTION | 0x0 | No Action
\r
4464 * Field Access Macros:
\r
4468 * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
\r
4470 * Indirect write operation
\r
4472 #define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
\r
4474 * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
\r
4478 #define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
\r
4480 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */
\r
4481 #define ALT_QSPI_INDWR_RDSTAT_LSB 2
\r
4482 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */
\r
4483 #define ALT_QSPI_INDWR_RDSTAT_MSB 2
\r
4484 /* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */
\r
4485 #define ALT_QSPI_INDWR_RDSTAT_WIDTH 1
\r
4486 /* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */
\r
4487 #define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
\r
4488 /* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */
\r
4489 #define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
\r
4490 /* The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN. */
\r
4491 #define ALT_QSPI_INDWR_RDSTAT_RESET 0x0
\r
4492 /* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */
\r
4493 #define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
\r
4494 /* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */
\r
4495 #define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
\r
4498 * Field : Reserved - sramfull
\r
4500 * Field Access Macros:
\r
4503 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */
\r
4504 #define ALT_QSPI_INDWR_SRAMFULL_LSB 3
\r
4505 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */
\r
4506 #define ALT_QSPI_INDWR_SRAMFULL_MSB 3
\r
4507 /* The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field. */
\r
4508 #define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1
\r
4509 /* The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value. */
\r
4510 #define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008
\r
4511 /* The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value. */
\r
4512 #define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7
\r
4513 /* The reset value of the ALT_QSPI_INDWR_SRAMFULL register field. */
\r
4514 #define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0
\r
4515 /* Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register. */
\r
4516 #define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3)
\r
4517 /* Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register. */
\r
4518 #define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008)
\r
4521 * Field : Queued Indirect Write Operations - rdqueued
\r
4523 * Two indirect write operations have been queued
\r
4525 * Field Enumeration Values:
\r
4527 * Enum | Value | Description
\r
4528 * :-----------------------------------|:------|:-----------------------------
\r
4529 * ALT_QSPI_INDWR_RDQUEUED_E_INDWROP | 0x1 | Two Indirect write operation
\r
4530 * ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0 | No Action
\r
4532 * Field Access Macros:
\r
4536 * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
\r
4538 * Two Indirect write operation
\r
4540 #define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
\r
4542 * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
\r
4546 #define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
\r
4548 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */
\r
4549 #define ALT_QSPI_INDWR_RDQUEUED_LSB 4
\r
4550 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */
\r
4551 #define ALT_QSPI_INDWR_RDQUEUED_MSB 4
\r
4552 /* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */
\r
4553 #define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
\r
4554 /* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */
\r
4555 #define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
\r
4556 /* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */
\r
4557 #define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
\r
4558 /* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN. */
\r
4559 #define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
\r
4560 /* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */
\r
4561 #define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
\r
4562 /* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */
\r
4563 #define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
\r
4566 * Field : Indirect Completion Status - inddone
\r
4568 * This field is set to 1 when an indirect operation has completed. Write a 1 to
\r
4569 * this field to clear it.
\r
4571 * Field Enumeration Values:
\r
4573 * Enum | Value | Description
\r
4574 * :-----------------------------------|:------|:-----------------------------
\r
4575 * ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1 | Indirect operation completed
\r
4576 * ALT_QSPI_INDWR_INDDONE_E_NOACTION | 0x0 | No Action
\r
4578 * Field Access Macros:
\r
4582 * Enumerated value for register field ALT_QSPI_INDWR_INDDONE
\r
4584 * Indirect operation completed
\r
4586 #define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
\r
4588 * Enumerated value for register field ALT_QSPI_INDWR_INDDONE
\r
4592 #define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
\r
4594 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */
\r
4595 #define ALT_QSPI_INDWR_INDDONE_LSB 5
\r
4596 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */
\r
4597 #define ALT_QSPI_INDWR_INDDONE_MSB 5
\r
4598 /* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */
\r
4599 #define ALT_QSPI_INDWR_INDDONE_WIDTH 1
\r
4600 /* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */
\r
4601 #define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
\r
4602 /* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */
\r
4603 #define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
\r
4604 /* The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN. */
\r
4605 #define ALT_QSPI_INDWR_INDDONE_RESET 0x0
\r
4606 /* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */
\r
4607 #define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
\r
4608 /* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */
\r
4609 #define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
\r
4612 * Field : Completed Indirect Operations - indcnt
\r
4614 * This field contains the count of indirect operations which have been completed.
\r
4615 * This is used in conjunction with the indirect completion status field (bit 5).
\r
4617 * Field Access Macros:
\r
4620 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */
\r
4621 #define ALT_QSPI_INDWR_INDCNT_LSB 6
\r
4622 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */
\r
4623 #define ALT_QSPI_INDWR_INDCNT_MSB 7
\r
4624 /* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */
\r
4625 #define ALT_QSPI_INDWR_INDCNT_WIDTH 2
\r
4626 /* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */
\r
4627 #define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
\r
4628 /* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */
\r
4629 #define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
\r
4630 /* The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN. */
\r
4631 #define ALT_QSPI_INDWR_INDCNT_RESET 0x0
\r
4632 /* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */
\r
4633 #define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
\r
4634 /* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */
\r
4635 #define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
\r
4637 #ifndef __ASSEMBLY__
\r
4639 * WARNING: The C register and register group struct declarations are provided for
\r
4640 * convenience and illustrative purposes. They should, however, be used with
\r
4641 * caution as the C language standard provides no guarantees about the alignment or
\r
4642 * atomicity of device memory accesses. The recommended practice for writing
\r
4643 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
4644 * alt_write_word() functions.
\r
4646 * The struct declaration for register ALT_QSPI_INDWR.
\r
4648 struct ALT_QSPI_INDWR_s
\r
4650 uint32_t start : 1; /* Start Indirect Write */
\r
4651 uint32_t cancel : 1; /* Cancel Indirect Write */
\r
4652 const uint32_t rdstat : 1; /* Indirect Write Status */
\r
4653 const uint32_t sramfull : 1; /* Reserved */
\r
4654 const uint32_t rdqueued : 1; /* Queued Indirect Write Operations */
\r
4655 uint32_t inddone : 1; /* Indirect Completion Status */
\r
4656 const uint32_t indcnt : 2; /* Completed Indirect Operations */
\r
4657 uint32_t : 24; /* *UNDEFINED* */
\r
4660 /* The typedef declaration for register ALT_QSPI_INDWR. */
\r
4661 typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t;
\r
4662 #endif /* __ASSEMBLY__ */
\r
4664 /* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */
\r
4665 #define ALT_QSPI_INDWR_OFST 0x70
\r
4668 * Register : Indirect Write Transfer Watermark Register - indwrwater
\r
4672 * Bits | Access | Reset | Description
\r
4673 * :-------|:-------|:-----------|:----------------
\r
4674 * [31:0] | RW | 0xffffffff | Watermark Value
\r
4678 * Field : Watermark Value - level
\r
4680 * This represents the maximum fill level of the SRAM before a DMA peripheral
\r
4681 * access is permitted. When the SRAM fill level falls below the watermark, an
\r
4682 * interrupt is also generated. This field can be disabled by writing a value of
\r
4683 * all ones. The units of this register are bytes.
\r
4685 * Field Access Macros:
\r
4688 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */
\r
4689 #define ALT_QSPI_INDWRWATER_LEVEL_LSB 0
\r
4690 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */
\r
4691 #define ALT_QSPI_INDWRWATER_LEVEL_MSB 31
\r
4692 /* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */
\r
4693 #define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
\r
4694 /* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */
\r
4695 #define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
\r
4696 /* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */
\r
4697 #define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
\r
4698 /* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */
\r
4699 #define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
\r
4700 /* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */
\r
4701 #define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
\r
4702 /* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */
\r
4703 #define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
\r
4705 #ifndef __ASSEMBLY__
\r
4707 * WARNING: The C register and register group struct declarations are provided for
\r
4708 * convenience and illustrative purposes. They should, however, be used with
\r
4709 * caution as the C language standard provides no guarantees about the alignment or
\r
4710 * atomicity of device memory accesses. The recommended practice for writing
\r
4711 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
4712 * alt_write_word() functions.
\r
4714 * The struct declaration for register ALT_QSPI_INDWRWATER.
\r
4716 struct ALT_QSPI_INDWRWATER_s
\r
4718 uint32_t level : 32; /* Watermark Value */
\r
4721 /* The typedef declaration for register ALT_QSPI_INDWRWATER. */
\r
4722 typedef volatile struct ALT_QSPI_INDWRWATER_s ALT_QSPI_INDWRWATER_t;
\r
4723 #endif /* __ASSEMBLY__ */
\r
4725 /* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */
\r
4726 #define ALT_QSPI_INDWRWATER_OFST 0x74
\r
4729 * Register : Indirect Write Transfer Start Address Register - indwrstaddr
\r
4733 * Bits | Access | Reset | Description
\r
4734 * :-------|:-------|:------|:-------------------------
\r
4735 * [31:0] | RW | 0x0 | Start of Indirect Access
\r
4739 * Field : Start of Indirect Access - addr
\r
4741 * This is the start address from which the indirect access will commence its write
\r
4744 * Field Access Macros:
\r
4747 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
\r
4748 #define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
\r
4749 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
\r
4750 #define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
\r
4751 /* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
\r
4752 #define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
\r
4753 /* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */
\r
4754 #define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
\r
4755 /* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */
\r
4756 #define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
\r
4757 /* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */
\r
4758 #define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
\r
4759 /* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */
\r
4760 #define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
\r
4761 /* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */
\r
4762 #define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
\r
4764 #ifndef __ASSEMBLY__
\r
4766 * WARNING: The C register and register group struct declarations are provided for
\r
4767 * convenience and illustrative purposes. They should, however, be used with
\r
4768 * caution as the C language standard provides no guarantees about the alignment or
\r
4769 * atomicity of device memory accesses. The recommended practice for writing
\r
4770 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
4771 * alt_write_word() functions.
\r
4773 * The struct declaration for register ALT_QSPI_INDWRSTADDR.
\r
4775 struct ALT_QSPI_INDWRSTADDR_s
\r
4777 uint32_t addr : 32; /* Start of Indirect Access */
\r
4780 /* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */
\r
4781 typedef volatile struct ALT_QSPI_INDWRSTADDR_s ALT_QSPI_INDWRSTADDR_t;
\r
4782 #endif /* __ASSEMBLY__ */
\r
4784 /* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */
\r
4785 #define ALT_QSPI_INDWRSTADDR_OFST 0x78
\r
4788 * Register : Indirect Write Transfer Count Register - indwrcnt
\r
4792 * Bits | Access | Reset | Description
\r
4793 * :-------|:-------|:------|:-------------------------
\r
4794 * [31:0] | RW | 0x0 | Indirect Number of Bytes
\r
4798 * Field : Indirect Number of Bytes - value
\r
4800 * This is the number of bytes that the indirect access will consume. This can be
\r
4801 * bigger than the configured size of SRAM.
\r
4803 * Field Access Macros:
\r
4806 /* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */
\r
4807 #define ALT_QSPI_INDWRCNT_VALUE_LSB 0
\r
4808 /* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */
\r
4809 #define ALT_QSPI_INDWRCNT_VALUE_MSB 31
\r
4810 /* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */
\r
4811 #define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
\r
4812 /* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */
\r
4813 #define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
\r
4814 /* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */
\r
4815 #define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
\r
4816 /* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */
\r
4817 #define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
\r
4818 /* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */
\r
4819 #define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
\r
4820 /* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */
\r
4821 #define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
\r
4823 #ifndef __ASSEMBLY__
\r
4825 * WARNING: The C register and register group struct declarations are provided for
\r
4826 * convenience and illustrative purposes. They should, however, be used with
\r
4827 * caution as the C language standard provides no guarantees about the alignment or
\r
4828 * atomicity of device memory accesses. The recommended practice for writing
\r
4829 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
4830 * alt_write_word() functions.
\r
4832 * The struct declaration for register ALT_QSPI_INDWRCNT.
\r
4834 struct ALT_QSPI_INDWRCNT_s
\r
4836 uint32_t value : 32; /* Indirect Number of Bytes */
\r
4839 /* The typedef declaration for register ALT_QSPI_INDWRCNT. */
\r
4840 typedef volatile struct ALT_QSPI_INDWRCNT_s ALT_QSPI_INDWRCNT_t;
\r
4841 #endif /* __ASSEMBLY__ */
\r
4843 /* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */
\r
4844 #define ALT_QSPI_INDWRCNT_OFST 0x7c
\r
4847 * Register : Flash Command Register - flashcmd
\r
4851 * Bits | Access | Reset | Description
\r
4852 * :--------|:-------|:------|:---------------------------
\r
4853 * [0] | RW | 0x0 | Execute Command
\r
4854 * [1] | R | 0x0 | Command Execution Status
\r
4855 * [6:2] | ??? | 0x0 | *UNDEFINED*
\r
4856 * [11:7] | RW | 0x0 | Number of Dummy Bytes
\r
4857 * [14:12] | RW | 0x0 | Number of Write Data Bytes
\r
4858 * [15] | RW | 0x0 | Write Data Enable
\r
4859 * [17:16] | RW | 0x0 | Number of Address Bytes
\r
4860 * [18] | RW | 0x0 | Mode Bit Enable
\r
4861 * [19] | RW | 0x0 | Command Address Enable
\r
4862 * [22:20] | RW | 0x0 | Number of Read Data Bytes
\r
4863 * [23] | RW | 0x0 | Read Data Enable
\r
4864 * [31:24] | RW | 0x0 | Command Opcode
\r
4868 * Field : Execute Command - execcmd
\r
4870 * Execute the command.
\r
4872 * Field Enumeration Values:
\r
4874 * Enum | Value | Description
\r
4875 * :------------------------------------|:------|:----------------
\r
4876 * ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE | 0x1 | Execute Command
\r
4877 * ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0 | No Action
\r
4879 * Field Access Macros:
\r
4883 * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD
\r
4887 #define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1
\r
4889 * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD
\r
4893 #define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0
\r
4895 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
\r
4896 #define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0
\r
4897 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
\r
4898 #define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0
\r
4899 /* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
\r
4900 #define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1
\r
4901 /* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */
\r
4902 #define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001
\r
4903 /* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */
\r
4904 #define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe
\r
4905 /* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */
\r
4906 #define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0
\r
4907 /* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */
\r
4908 #define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
\r
4909 /* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */
\r
4910 #define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
\r
4913 * Field : Command Execution Status - cmdexecstat
\r
4915 * Command execution in progress.
\r
4917 * Field Enumeration Values:
\r
4919 * Enum | Value | Description
\r
4920 * :-------------------------------------------|:------|:-------------------------
\r
4921 * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1 | Command Execution Status
\r
4922 * ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION | 0x0 | No Action
\r
4924 * Field Access Macros:
\r
4928 * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT
\r
4930 * Command Execution Status
\r
4932 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
\r
4934 * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT
\r
4938 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0
\r
4940 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
\r
4941 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1
\r
4942 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
\r
4943 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1
\r
4944 /* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
\r
4945 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1
\r
4946 /* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */
\r
4947 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002
\r
4948 /* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */
\r
4949 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
\r
4950 /* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */
\r
4951 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0
\r
4952 /* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */
\r
4953 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
\r
4954 /* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */
\r
4955 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
\r
4958 * Field : Number of Dummy Bytes - numdummybytes
\r
4960 * Set to the number of dummy bytes required This should be setup before triggering
\r
4961 * the command via the execute field of this register.
\r
4963 * Field Access Macros:
\r
4966 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
\r
4967 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7
\r
4968 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
\r
4969 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11
\r
4970 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
\r
4971 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5
\r
4972 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */
\r
4973 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
\r
4974 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */
\r
4975 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
\r
4976 /* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */
\r
4977 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0
\r
4978 /* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */
\r
4979 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
\r
4980 /* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */
\r
4981 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
\r
4984 * Field : Number of Write Data Bytes - numwrdatabytes
\r
4986 * Up to 8 Data bytes may be written using this command.
\r
4988 * Field Enumeration Values:
\r
4990 * Enum | Value | Description
\r
4991 * :------------------------------------------|:------|:-------------
\r
4992 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0 | Write 1 Byte
\r
4993 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1 | Write 2 Byte
\r
4994 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2 | Write 3 Byte
\r
4995 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3 | Write 4 Byte
\r
4996 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4 | Write 5 Byte
\r
4997 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5 | Write 6 Byte
\r
4998 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6 | Write 7 Byte
\r
4999 * ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7 | Write 8 Byte
\r
5001 * Field Access Macros:
\r
5005 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
\r
5009 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
\r
5011 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
\r
5015 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
\r
5017 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
\r
5021 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
\r
5023 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
\r
5027 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
\r
5029 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
\r
5033 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
\r
5035 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
\r
5039 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
\r
5041 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
\r
5045 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
\r
5047 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES
\r
5051 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
\r
5053 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
\r
5054 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12
\r
5055 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
\r
5056 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14
\r
5057 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
\r
5058 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3
\r
5059 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */
\r
5060 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
\r
5061 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */
\r
5062 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
\r
5063 /* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */
\r
5064 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0
\r
5065 /* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */
\r
5066 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
\r
5067 /* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */
\r
5068 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
\r
5071 * Field : Write Data Enable - enwrdata
\r
5073 * Set to 1 if the command specified in the command opcode field requires write
\r
5074 * data bytes to be sent to the device.
\r
5076 * Field Enumeration Values:
\r
5078 * Enum | Value | Description
\r
5079 * :----------------------------------------|:------|:----------------------------------
\r
5080 * ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1 | Command requires write data bytes
\r
5081 * ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION | 0x0 | No Action
\r
5083 * Field Access Macros:
\r
5087 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA
\r
5089 * Command requires write data bytes
\r
5091 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1
\r
5093 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA
\r
5097 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0
\r
5099 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
\r
5100 #define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15
\r
5101 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
\r
5102 #define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15
\r
5103 /* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
\r
5104 #define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1
\r
5105 /* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */
\r
5106 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000
\r
5107 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */
\r
5108 #define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff
\r
5109 /* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */
\r
5110 #define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0
\r
5111 /* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */
\r
5112 #define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
\r
5113 /* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */
\r
5114 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
\r
5117 * Field : Number of Address Bytes - numaddrbytes
\r
5119 * Set to the number of address bytes required (the address itself is programmed in
\r
5120 * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the
\r
5121 * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address
\r
5122 * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes
\r
5124 * Field Enumeration Values:
\r
5126 * Enum | Value | Description
\r
5127 * :------------------------------------------|:------|:----------------------
\r
5128 * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0 | Write 1 Address Byte
\r
5129 * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1 | Write 2 Address Bytes
\r
5130 * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2 | Write 3 Address Bytes
\r
5131 * ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3 | Write 4 Address Bytes
\r
5133 * Field Access Macros:
\r
5137 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
\r
5139 * Write 1 Address Byte
\r
5141 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
\r
5143 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
\r
5145 * Write 2 Address Bytes
\r
5147 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
\r
5149 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
\r
5151 * Write 3 Address Bytes
\r
5153 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
\r
5155 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES
\r
5157 * Write 4 Address Bytes
\r
5159 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
\r
5161 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
\r
5162 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16
\r
5163 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
\r
5164 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17
\r
5165 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
\r
5166 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2
\r
5167 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */
\r
5168 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000
\r
5169 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */
\r
5170 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
\r
5171 /* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */
\r
5172 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0
\r
5173 /* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */
\r
5174 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
\r
5175 /* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */
\r
5176 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
\r
5179 * Field : Mode Bit Enable - enmodebit
\r
5181 * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration
\r
5182 * register are sent following the address bytes.
\r
5184 * Field Enumeration Values:
\r
5186 * Enum | Value | Description
\r
5187 * :---------------------------------|:------|:-------------------------------
\r
5188 * ALT_QSPI_FLSHCMD_ENMODBIT_E_END | 0x1 | Mode Bit follows address bytes
\r
5189 * ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0 | No Action
\r
5191 * Field Access Macros:
\r
5195 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT
\r
5197 * Mode Bit follows address bytes
\r
5199 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1
\r
5201 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT
\r
5205 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0
\r
5207 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
\r
5208 #define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18
\r
5209 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
\r
5210 #define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18
\r
5211 /* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
\r
5212 #define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1
\r
5213 /* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */
\r
5214 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000
\r
5215 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */
\r
5216 #define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff
\r
5217 /* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */
\r
5218 #define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0
\r
5219 /* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */
\r
5220 #define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18)
\r
5221 /* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */
\r
5222 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000)
\r
5225 * Field : Command Address Enable - encmdaddr
\r
5227 * If enabled, the command specified in bits 31:24 requires an address. This should
\r
5228 * be setup before triggering the command via writing a 1 to the execute field.
\r
5230 * Field Enumeration Values:
\r
5232 * Enum | Value | Description
\r
5233 * :----------------------------------|:------|:---------------------------------------
\r
5234 * ALT_QSPI_FLSHCMD_ENCMDADDR_E_END | 0x1 | Command in bits 31:24 requires address
\r
5235 * ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0 | No Action
\r
5237 * Field Access Macros:
\r
5241 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR
\r
5243 * Command in bits 31:24 requires address
\r
5245 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1
\r
5247 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR
\r
5251 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0
\r
5253 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
\r
5254 #define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19
\r
5255 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
\r
5256 #define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19
\r
5257 /* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
\r
5258 #define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1
\r
5259 /* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */
\r
5260 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000
\r
5261 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */
\r
5262 #define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
\r
5263 /* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */
\r
5264 #define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0
\r
5265 /* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */
\r
5266 #define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
\r
5267 /* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */
\r
5268 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
\r
5271 * Field : Number of Read Data Bytes - numrddatabytes
\r
5273 * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for
\r
5276 * Field Enumeration Values:
\r
5278 * Enum | Value | Description
\r
5279 * :------------------------------------------|:------|:------------
\r
5280 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0 | Read 1 Byte
\r
5281 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1 | Read 2 Byte
\r
5282 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2 | Read 3 Byte
\r
5283 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3 | Read 4 Byte
\r
5284 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4 | Read 5 Byte
\r
5285 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5 | Read 6 Byte
\r
5286 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6 | Read 7 Byte
\r
5287 * ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7 | Read 8 Byte
\r
5289 * Field Access Macros:
\r
5293 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
\r
5297 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
\r
5299 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
\r
5303 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
\r
5305 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
\r
5309 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
\r
5311 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
\r
5315 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
\r
5317 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
\r
5321 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
\r
5323 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
\r
5327 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
\r
5329 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
\r
5333 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
\r
5335 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES
\r
5339 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
\r
5341 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
\r
5342 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20
\r
5343 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
\r
5344 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22
\r
5345 /* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
\r
5346 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3
\r
5347 /* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */
\r
5348 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
\r
5349 /* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */
\r
5350 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
\r
5351 /* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */
\r
5352 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0
\r
5353 /* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */
\r
5354 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
\r
5355 /* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */
\r
5356 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
\r
5359 * Field : Read Data Enable - enrddata
\r
5361 * If enabled, the command specified in the command opcode field (bits 31:24)
\r
5362 * requires read data bytes to be received from the device.
\r
5364 * Field Enumeration Values:
\r
5366 * Enum | Value | Description
\r
5367 * :-------------------------------------|:------|:---------------------------
\r
5368 * ALT_QSPI_FLSHCMD_ENRDDATA_E_EN | 0x1 | Command Requires read data
\r
5369 * ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0 | No Action
\r
5371 * Field Access Macros:
\r
5375 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA
\r
5377 * Command Requires read data
\r
5379 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1
\r
5381 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA
\r
5385 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0
\r
5387 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
\r
5388 #define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23
\r
5389 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
\r
5390 #define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23
\r
5391 /* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
\r
5392 #define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1
\r
5393 /* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */
\r
5394 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000
\r
5395 /* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */
\r
5396 #define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff
\r
5397 /* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */
\r
5398 #define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0
\r
5399 /* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */
\r
5400 #define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
\r
5401 /* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */
\r
5402 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
\r
5405 * Field : Command Opcode - cmdopcode
\r
5407 * The command opcode field should be setup before triggering the command. For
\r
5408 * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of
\r
5409 * this register launches the command. NOTE : Using this approach to issue commands
\r
5410 * to the device will make use of the instruction type of the device instruction
\r
5411 * configuration register. If this field is set to 2'b00, then the command opcode,
\r
5412 * command address, command dummy bytes and command data will all be transferred in
\r
5413 * a serial fashion. If this field is set to 2'b01, then the command opcode,
\r
5414 * command address, command dummy bytes and command data will all be transferred in
\r
5415 * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command
\r
5416 * opcode, command address, command dummy bytes and command data will all be
\r
5417 * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins.
\r
5419 * Field Access Macros:
\r
5422 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
\r
5423 #define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24
\r
5424 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
\r
5425 #define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31
\r
5426 /* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
\r
5427 #define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8
\r
5428 /* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */
\r
5429 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000
\r
5430 /* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */
\r
5431 #define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
\r
5432 /* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */
\r
5433 #define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0
\r
5434 /* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */
\r
5435 #define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
\r
5436 /* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */
\r
5437 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
\r
5439 #ifndef __ASSEMBLY__
\r
5441 * WARNING: The C register and register group struct declarations are provided for
\r
5442 * convenience and illustrative purposes. They should, however, be used with
\r
5443 * caution as the C language standard provides no guarantees about the alignment or
\r
5444 * atomicity of device memory accesses. The recommended practice for writing
\r
5445 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
5446 * alt_write_word() functions.
\r
5448 * The struct declaration for register ALT_QSPI_FLSHCMD.
\r
5450 struct ALT_QSPI_FLSHCMD_s
\r
5452 uint32_t execcmd : 1; /* Execute Command */
\r
5453 const uint32_t cmdexecstat : 1; /* Command Execution Status */
\r
5454 uint32_t : 5; /* *UNDEFINED* */
\r
5455 uint32_t numdummybytes : 5; /* Number of Dummy Bytes */
\r
5456 uint32_t numwrdatabytes : 3; /* Number of Write Data Bytes */
\r
5457 uint32_t enwrdata : 1; /* Write Data Enable */
\r
5458 uint32_t numaddrbytes : 2; /* Number of Address Bytes */
\r
5459 uint32_t enmodebit : 1; /* Mode Bit Enable */
\r
5460 uint32_t encmdaddr : 1; /* Command Address Enable */
\r
5461 uint32_t numrddatabytes : 3; /* Number of Read Data Bytes */
\r
5462 uint32_t enrddata : 1; /* Read Data Enable */
\r
5463 uint32_t cmdopcode : 8; /* Command Opcode */
\r
5466 /* The typedef declaration for register ALT_QSPI_FLSHCMD. */
\r
5467 typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t;
\r
5468 #endif /* __ASSEMBLY__ */
\r
5470 /* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */
\r
5471 #define ALT_QSPI_FLSHCMD_OFST 0x90
\r
5474 * Register : Flash Command Address Registers - flashcmdaddr
\r
5478 * Bits | Access | Reset | Description
\r
5479 * :-------|:-------|:------|:----------------
\r
5480 * [31:0] | RW | 0x0 | Command Address
\r
5484 * Field : Command Address - addr
\r
5486 * This should be setup before triggering the command with execute field (bit 0) of
\r
5487 * the Flash Command Control register. It is the address used by the command
\r
5488 * specified in the opcode field (bits 31:24) of the Flash Command Control
\r
5491 * Field Access Macros:
\r
5494 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
\r
5495 #define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0
\r
5496 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
\r
5497 #define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31
\r
5498 /* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
\r
5499 #define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32
\r
5500 /* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */
\r
5501 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff
\r
5502 /* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */
\r
5503 #define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000
\r
5504 /* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */
\r
5505 #define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0
\r
5506 /* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */
\r
5507 #define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
\r
5508 /* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */
\r
5509 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
\r
5511 #ifndef __ASSEMBLY__
\r
5513 * WARNING: The C register and register group struct declarations are provided for
\r
5514 * convenience and illustrative purposes. They should, however, be used with
\r
5515 * caution as the C language standard provides no guarantees about the alignment or
\r
5516 * atomicity of device memory accesses. The recommended practice for writing
\r
5517 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
5518 * alt_write_word() functions.
\r
5520 * The struct declaration for register ALT_QSPI_FLSHCMDADDR.
\r
5522 struct ALT_QSPI_FLSHCMDADDR_s
\r
5524 uint32_t addr : 32; /* Command Address */
\r
5527 /* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */
\r
5528 typedef volatile struct ALT_QSPI_FLSHCMDADDR_s ALT_QSPI_FLSHCMDADDR_t;
\r
5529 #endif /* __ASSEMBLY__ */
\r
5531 /* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */
\r
5532 #define ALT_QSPI_FLSHCMDADDR_OFST 0x94
\r
5535 * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo
\r
5539 * Bits | Access | Reset | Description
\r
5540 * :-------|:-------|:------|:-------------------------------
\r
5541 * [31:0] | RW | 0x0 | Command Read Data (Lower byte)
\r
5545 * Field : Command Read Data (Lower byte) - data
\r
5547 * This is the data that is returned by the flash device for any status or
\r
5548 * configuration read operation carried out by triggering the event in the control
\r
5549 * register. The register will be valid when the polling bit in the control
\r
5550 * register is low.
\r
5552 * Field Access Macros:
\r
5555 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
\r
5556 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0
\r
5557 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
\r
5558 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31
\r
5559 /* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
\r
5560 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32
\r
5561 /* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */
\r
5562 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff
\r
5563 /* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */
\r
5564 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000
\r
5565 /* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */
\r
5566 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0
\r
5567 /* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */
\r
5568 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
\r
5569 /* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */
\r
5570 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
\r
5572 #ifndef __ASSEMBLY__
\r
5574 * WARNING: The C register and register group struct declarations are provided for
\r
5575 * convenience and illustrative purposes. They should, however, be used with
\r
5576 * caution as the C language standard provides no guarantees about the alignment or
\r
5577 * atomicity of device memory accesses. The recommended practice for writing
\r
5578 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
5579 * alt_write_word() functions.
\r
5581 * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO.
\r
5583 struct ALT_QSPI_FLSHCMDRDDATALO_s
\r
5585 uint32_t data : 32; /* Command Read Data (Lower byte) */
\r
5588 /* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */
\r
5589 typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s ALT_QSPI_FLSHCMDRDDATALO_t;
\r
5590 #endif /* __ASSEMBLY__ */
\r
5592 /* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */
\r
5593 #define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0
\r
5596 * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup
\r
5598 * Device Instruction Register
\r
5602 * Bits | Access | Reset | Description
\r
5603 * :-------|:-------|:------|:-------------------------------
\r
5604 * [31:0] | RW | 0x0 | Command Read Data (Upper byte)
\r
5608 * Field : Command Read Data (Upper byte) - data
\r
5610 * This is the data that is returned by the FLASH device for any status or
\r
5611 * configuration read operation carried out by triggering the event in the control
\r
5612 * register. The register will be valid when the polling bit in the control
\r
5613 * register is low.
\r
5615 * Field Access Macros:
\r
5618 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
\r
5619 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0
\r
5620 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
\r
5621 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31
\r
5622 /* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
\r
5623 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32
\r
5624 /* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */
\r
5625 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
\r
5626 /* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */
\r
5627 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
\r
5628 /* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */
\r
5629 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0
\r
5630 /* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */
\r
5631 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
\r
5632 /* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */
\r
5633 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
\r
5635 #ifndef __ASSEMBLY__
\r
5637 * WARNING: The C register and register group struct declarations are provided for
\r
5638 * convenience and illustrative purposes. They should, however, be used with
\r
5639 * caution as the C language standard provides no guarantees about the alignment or
\r
5640 * atomicity of device memory accesses. The recommended practice for writing
\r
5641 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
5642 * alt_write_word() functions.
\r
5644 * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP.
\r
5646 struct ALT_QSPI_FLSHCMDRDDATAUP_s
\r
5648 uint32_t data : 32; /* Command Read Data (Upper byte) */
\r
5651 /* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */
\r
5652 typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s ALT_QSPI_FLSHCMDRDDATAUP_t;
\r
5653 #endif /* __ASSEMBLY__ */
\r
5655 /* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */
\r
5656 #define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4
\r
5659 * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo
\r
5663 * Bits | Access | Reset | Description
\r
5664 * :-------|:-------|:------|:------------------------------
\r
5665 * [31:0] | RW | 0x0 | Command Write Data Lower Byte
\r
5669 * Field : Command Write Data Lower Byte - data
\r
5671 * This is the command write data lower byte. This should be setup before
\r
5672 * triggering the command with execute field (bit 0) of the Flash Command Control
\r
5673 * register. It is the data that is to be written to the flash for any status or
\r
5674 * configuration write operation carried out by triggering the event in the Flash
\r
5675 * Command Control register.
\r
5677 * Field Access Macros:
\r
5680 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
\r
5681 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0
\r
5682 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
\r
5683 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31
\r
5684 /* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
\r
5685 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32
\r
5686 /* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */
\r
5687 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff
\r
5688 /* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */
\r
5689 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000
\r
5690 /* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */
\r
5691 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0
\r
5692 /* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */
\r
5693 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
\r
5694 /* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */
\r
5695 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
\r
5697 #ifndef __ASSEMBLY__
\r
5699 * WARNING: The C register and register group struct declarations are provided for
\r
5700 * convenience and illustrative purposes. They should, however, be used with
\r
5701 * caution as the C language standard provides no guarantees about the alignment or
\r
5702 * atomicity of device memory accesses. The recommended practice for writing
\r
5703 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
5704 * alt_write_word() functions.
\r
5706 * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO.
\r
5708 struct ALT_QSPI_FLSHCMDWRDATALO_s
\r
5710 uint32_t data : 32; /* Command Write Data Lower Byte */
\r
5713 /* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */
\r
5714 typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s ALT_QSPI_FLSHCMDWRDATALO_t;
\r
5715 #endif /* __ASSEMBLY__ */
\r
5717 /* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */
\r
5718 #define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8
\r
5721 * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup
\r
5725 * Bits | Access | Reset | Description
\r
5726 * :-------|:-------|:------|:------------------------------
\r
5727 * [31:0] | RW | 0x0 | ALT_QSPI_FLSHCMDWRDATAUP_DATA
\r
5733 * This is the command write data upper byte. This should be setup before
\r
5734 * triggering the command with execute field (bit 0) of the Flash Command Control
\r
5735 * register. It is the data that is to be written to the flash for any status or
\r
5736 * configuration write operation carried out by triggering the event in the Flash
\r
5737 * Command Control register.
\r
5739 * Field Access Macros:
\r
5742 /* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
\r
5743 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0
\r
5744 /* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
\r
5745 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31
\r
5746 /* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
\r
5747 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32
\r
5748 /* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */
\r
5749 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
\r
5750 /* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */
\r
5751 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
\r
5752 /* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */
\r
5753 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0
\r
5754 /* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */
\r
5755 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
\r
5756 /* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */
\r
5757 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
\r
5759 #ifndef __ASSEMBLY__
\r
5761 * WARNING: The C register and register group struct declarations are provided for
\r
5762 * convenience and illustrative purposes. They should, however, be used with
\r
5763 * caution as the C language standard provides no guarantees about the alignment or
\r
5764 * atomicity of device memory accesses. The recommended practice for writing
\r
5765 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
5766 * alt_write_word() functions.
\r
5768 * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP.
\r
5770 struct ALT_QSPI_FLSHCMDWRDATAUP_s
\r
5772 uint32_t data : 32; /* ALT_QSPI_FLSHCMDWRDATAUP_DATA */
\r
5775 /* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */
\r
5776 typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s ALT_QSPI_FLSHCMDWRDATAUP_t;
\r
5777 #endif /* __ASSEMBLY__ */
\r
5779 /* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */
\r
5780 #define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac
\r
5783 * Register : Module ID Register - moduleid
\r
5787 * Bits | Access | Reset | Description
\r
5788 * :--------|:-------|:-------|:-----------------
\r
5789 * [24:0] | R | 0x1001 | Module ID number
\r
5790 * [31:25] | ??? | 0x0 | *UNDEFINED*
\r
5794 * Field : Module ID number - value
\r
5796 * Field Access Macros:
\r
5799 /* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */
\r
5800 #define ALT_QSPI_MODULEID_VALUE_LSB 0
\r
5801 /* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */
\r
5802 #define ALT_QSPI_MODULEID_VALUE_MSB 24
\r
5803 /* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */
\r
5804 #define ALT_QSPI_MODULEID_VALUE_WIDTH 25
\r
5805 /* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */
\r
5806 #define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
\r
5807 /* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */
\r
5808 #define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
\r
5809 /* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */
\r
5810 #define ALT_QSPI_MODULEID_VALUE_RESET 0x1001
\r
5811 /* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */
\r
5812 #define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
\r
5813 /* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */
\r
5814 #define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
\r
5816 #ifndef __ASSEMBLY__
\r
5818 * WARNING: The C register and register group struct declarations are provided for
\r
5819 * convenience and illustrative purposes. They should, however, be used with
\r
5820 * caution as the C language standard provides no guarantees about the alignment or
\r
5821 * atomicity of device memory accesses. The recommended practice for writing
\r
5822 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
5823 * alt_write_word() functions.
\r
5825 * The struct declaration for register ALT_QSPI_MODULEID.
\r
5827 struct ALT_QSPI_MODULEID_s
\r
5829 const uint32_t value : 25; /* Module ID number */
\r
5830 uint32_t : 7; /* *UNDEFINED* */
\r
5833 /* The typedef declaration for register ALT_QSPI_MODULEID. */
\r
5834 typedef volatile struct ALT_QSPI_MODULEID_s ALT_QSPI_MODULEID_t;
\r
5835 #endif /* __ASSEMBLY__ */
\r
5837 /* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */
\r
5838 #define ALT_QSPI_MODULEID_OFST 0xfc
\r
5840 #ifndef __ASSEMBLY__
\r
5842 * WARNING: The C register and register group struct declarations are provided for
\r
5843 * convenience and illustrative purposes. They should, however, be used with
\r
5844 * caution as the C language standard provides no guarantees about the alignment or
\r
5845 * atomicity of device memory accesses. The recommended practice for writing
\r
5846 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
\r
5847 * alt_write_word() functions.
\r
5849 * The struct declaration for register group ALT_QSPI.
\r
5853 volatile ALT_QSPI_CFG_t cfg; /* ALT_QSPI_CFG */
\r
5854 volatile ALT_QSPI_DEVRD_t devrd; /* ALT_QSPI_DEVRD */
\r
5855 volatile ALT_QSPI_DEVWR_t devwr; /* ALT_QSPI_DEVWR */
\r
5856 volatile ALT_QSPI_DELAY_t delay; /* ALT_QSPI_DELAY */
\r
5857 volatile ALT_QSPI_RDDATACAP_t rddatacap; /* ALT_QSPI_RDDATACAP */
\r
5858 volatile ALT_QSPI_DEVSZ_t devsz; /* ALT_QSPI_DEVSZ */
\r
5859 volatile ALT_QSPI_SRAMPART_t srampart; /* ALT_QSPI_SRAMPART */
\r
5860 volatile ALT_QSPI_INDADDRTRIG_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */
\r
5861 volatile ALT_QSPI_DMAPER_t dmaper; /* ALT_QSPI_DMAPER */
\r
5862 volatile ALT_QSPI_REMAPADDR_t remapaddr; /* ALT_QSPI_REMAPADDR */
\r
5863 volatile ALT_QSPI_MODBIT_t modebit; /* ALT_QSPI_MODBIT */
\r
5864 volatile ALT_QSPI_SRAMFILL_t sramfill; /* ALT_QSPI_SRAMFILL */
\r
5865 volatile ALT_QSPI_TXTHRESH_t txthresh; /* ALT_QSPI_TXTHRESH */
\r
5866 volatile ALT_QSPI_RXTHRESH_t rxthresh; /* ALT_QSPI_RXTHRESH */
\r
5867 volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
\r
5868 volatile ALT_QSPI_IRQSTAT_t irqstat; /* ALT_QSPI_IRQSTAT */
\r
5869 volatile ALT_QSPI_IRQMSK_t irqmask; /* ALT_QSPI_IRQMSK */
\r
5870 volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */
\r
5871 volatile ALT_QSPI_LOWWRPROT_t lowwrprot; /* ALT_QSPI_LOWWRPROT */
\r
5872 volatile ALT_QSPI_UPPWRPROT_t uppwrprot; /* ALT_QSPI_UPPWRPROT */
\r
5873 volatile ALT_QSPI_WRPROT_t wrprot; /* ALT_QSPI_WRPROT */
\r
5874 volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
\r
5875 volatile ALT_QSPI_INDRD_t indrd; /* ALT_QSPI_INDRD */
\r
5876 volatile ALT_QSPI_INDRDWATER_t indrdwater; /* ALT_QSPI_INDRDWATER */
\r
5877 volatile ALT_QSPI_INDRDSTADDR_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */
\r
5878 volatile ALT_QSPI_INDRDCNT_t indrdcnt; /* ALT_QSPI_INDRDCNT */
\r
5879 volatile ALT_QSPI_INDWR_t indwr; /* ALT_QSPI_INDWR */
\r
5880 volatile ALT_QSPI_INDWRWATER_t indwrwater; /* ALT_QSPI_INDWRWATER */
\r
5881 volatile ALT_QSPI_INDWRSTADDR_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */
\r
5882 volatile ALT_QSPI_INDWRCNT_t indwrcnt; /* ALT_QSPI_INDWRCNT */
\r
5883 volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */
\r
5884 volatile ALT_QSPI_FLSHCMD_t flashcmd; /* ALT_QSPI_FLSHCMD */
\r
5885 volatile ALT_QSPI_FLSHCMDADDR_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */
\r
5886 volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */
\r
5887 volatile ALT_QSPI_FLSHCMDRDDATALO_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */
\r
5888 volatile ALT_QSPI_FLSHCMDRDDATAUP_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */
\r
5889 volatile ALT_QSPI_FLSHCMDWRDATALO_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */
\r
5890 volatile ALT_QSPI_FLSHCMDWRDATAUP_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */
\r
5891 volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */
\r
5892 volatile ALT_QSPI_MODULEID_t moduleid; /* ALT_QSPI_MODULEID */
\r
5895 /* The typedef declaration for register group ALT_QSPI. */
\r
5896 typedef volatile struct ALT_QSPI_s ALT_QSPI_t;
\r
5897 /* The struct declaration for the raw register contents of register group ALT_QSPI. */
\r
5898 struct ALT_QSPI_raw_s
\r
5900 volatile uint32_t cfg; /* ALT_QSPI_CFG */
\r
5901 volatile uint32_t devrd; /* ALT_QSPI_DEVRD */
\r
5902 volatile uint32_t devwr; /* ALT_QSPI_DEVWR */
\r
5903 volatile uint32_t delay; /* ALT_QSPI_DELAY */
\r
5904 volatile uint32_t rddatacap; /* ALT_QSPI_RDDATACAP */
\r
5905 volatile uint32_t devsz; /* ALT_QSPI_DEVSZ */
\r
5906 volatile uint32_t srampart; /* ALT_QSPI_SRAMPART */
\r
5907 volatile uint32_t indaddrtrig; /* ALT_QSPI_INDADDRTRIG */
\r
5908 volatile uint32_t dmaper; /* ALT_QSPI_DMAPER */
\r
5909 volatile uint32_t remapaddr; /* ALT_QSPI_REMAPADDR */
\r
5910 volatile uint32_t modebit; /* ALT_QSPI_MODBIT */
\r
5911 volatile uint32_t sramfill; /* ALT_QSPI_SRAMFILL */
\r
5912 volatile uint32_t txthresh; /* ALT_QSPI_TXTHRESH */
\r
5913 volatile uint32_t rxthresh; /* ALT_QSPI_RXTHRESH */
\r
5914 volatile uint32_t _pad_0x38_0x3f[2]; /* *UNDEFINED* */
\r
5915 volatile uint32_t irqstat; /* ALT_QSPI_IRQSTAT */
\r
5916 volatile uint32_t irqmask; /* ALT_QSPI_IRQMSK */
\r
5917 volatile uint32_t _pad_0x48_0x4f[2]; /* *UNDEFINED* */
\r
5918 volatile uint32_t lowwrprot; /* ALT_QSPI_LOWWRPROT */
\r
5919 volatile uint32_t uppwrprot; /* ALT_QSPI_UPPWRPROT */
\r
5920 volatile uint32_t wrprot; /* ALT_QSPI_WRPROT */
\r
5921 volatile uint32_t _pad_0x5c_0x5f; /* *UNDEFINED* */
\r
5922 volatile uint32_t indrd; /* ALT_QSPI_INDRD */
\r
5923 volatile uint32_t indrdwater; /* ALT_QSPI_INDRDWATER */
\r
5924 volatile uint32_t indrdstaddr; /* ALT_QSPI_INDRDSTADDR */
\r
5925 volatile uint32_t indrdcnt; /* ALT_QSPI_INDRDCNT */
\r
5926 volatile uint32_t indwr; /* ALT_QSPI_INDWR */
\r
5927 volatile uint32_t indwrwater; /* ALT_QSPI_INDWRWATER */
\r
5928 volatile uint32_t indwrstaddr; /* ALT_QSPI_INDWRSTADDR */
\r
5929 volatile uint32_t indwrcnt; /* ALT_QSPI_INDWRCNT */
\r
5930 volatile uint32_t _pad_0x80_0x8f[4]; /* *UNDEFINED* */
\r
5931 volatile uint32_t flashcmd; /* ALT_QSPI_FLSHCMD */
\r
5932 volatile uint32_t flashcmdaddr; /* ALT_QSPI_FLSHCMDADDR */
\r
5933 volatile uint32_t _pad_0x98_0x9f[2]; /* *UNDEFINED* */
\r
5934 volatile uint32_t flashcmdrddatalo; /* ALT_QSPI_FLSHCMDRDDATALO */
\r
5935 volatile uint32_t flashcmdrddataup; /* ALT_QSPI_FLSHCMDRDDATAUP */
\r
5936 volatile uint32_t flashcmdwrdatalo; /* ALT_QSPI_FLSHCMDWRDATALO */
\r
5937 volatile uint32_t flashcmdwrdataup; /* ALT_QSPI_FLSHCMDWRDATAUP */
\r
5938 volatile uint32_t _pad_0xb0_0xfb[19]; /* *UNDEFINED* */
\r
5939 volatile uint32_t moduleid; /* ALT_QSPI_MODULEID */
\r
5942 /* The typedef declaration for the raw register contents of register group ALT_QSPI. */
\r
5943 typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t;
\r
5944 #endif /* __ASSEMBLY__ */
\r
5947 #ifdef __cplusplus
\r
5949 #endif /* __cplusplus */
\r
5950 #endif /* __ALTERA_ALT_QSPI_H__ */
\r