Added project for Altera Cyclone V SoC, currently running from internal RAM.

[freertos] / FreeRTOS / Demo / CORTEX_A9_Cyclone_V_SoC_DK / Altera_Code / HardwareLibrary / include / socal / alt_qspi.h

/*******************************************************************************\r
*                                                                              *\r
* Copyright 2013 Altera Corporation. All Rights Reserved.                      *\r
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\r
/* Altera - ALT_QSPI */\r
\r
#ifndef __ALTERA_ALT_QSPI_H__\r
#define __ALTERA_ALT_QSPI_H__\r
\r
#ifdef __cplusplus\r
extern "C"\r
{\r
#endif  /* __cplusplus */\r
\r
/*\r
 * Component : QSPI Flash Controller Module Registers - ALT_QSPI\r
 * QSPI Flash Controller Module Registers\r
 * \r
 * Registers in the QSPI Flash Controller module accessible via its APB slave\r
 * \r
 */\r
/*\r
 * Register : QSPI Configuration Register - cfg\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset | Description                               \r
 * :--------|:-------|:------|:-------------------------------------------\r
 *  [0]     | RW     | 0x0   | QSPI Enable                               \r
 *  [1]     | RW     | 0x0   | Clock Polarity                            \r
 *  [2]     | RW     | 0x0   | Select Clock Phase                        \r
 *  [6:3]   | ???    | 0x0   | *UNDEFINED*                               \r
 *  [7]     | RW     | 0x0   | Enable Direct Access Controller           \r
 *  [8]     | RW     | 0x0   | Legacy IP Mode Enable                     \r
 *  [9]     | RW     | 0x0   | Peripheral select decode                  \r
 *  [13:10] | RW     | 0x0   | Peripheral Chip Select Lines              \r
 *  [14]    | RW     | 0x0   | Write Protect Flash Pin                   \r
 *  [15]    | RW     | 0x0   | Enable DMA Peripheral Interface           \r
 *  [16]    | RW     | 0x0   | Enable AHB Address Re-mapping             \r
 *  [17]    | RW     | 0x0   | Enter XIP Mode on next READ               \r
 *  [18]    | RW     | 0x0   | Enter XIP Mode Immediately                \r
 *  [22:19] | RW     | 0xf   | Master Mode Baud Rate Divisor             \r
 *  [30:23] | ???    | 0x0   | *UNDEFINED*                               \r
 *  [31]    | R      | 0x0   | Serial interface and QSPI pipeline is IDLE\r
 * \r
 */\r
/*\r
 * Field : QSPI Enable - en\r
 * \r
 * If this bit is disabled, the QSPI will finish the current transfer of the data\r
 * word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output\r
 * enables are inactive and all pins are set to input mode.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                  | Value | Description     \r
 * :----------------------|:------|:-----------------\r
 *  ALT_QSPI_CFG_EN_E_DIS | 0x0   | Disable the QSPI\r
 *  ALT_QSPI_CFG_EN_E_EN  | 0x1   | Enable the QSPI \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_EN\r
 * \r
 * Disable the QSPI\r
 */\r
#define ALT_QSPI_CFG_EN_E_DIS   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_EN\r
 * \r
 * Enable the QSPI\r
 */\r
#define ALT_QSPI_CFG_EN_E_EN    0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field. */\r
#define ALT_QSPI_CFG_EN_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field. */\r
#define ALT_QSPI_CFG_EN_MSB        0\r
/* The width in bits of the ALT_QSPI_CFG_EN register field. */\r
#define ALT_QSPI_CFG_EN_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_EN register field value. */\r
#define ALT_QSPI_CFG_EN_SET_MSK    0x00000001\r
/* The mask used to clear the ALT_QSPI_CFG_EN register field value. */\r
#define ALT_QSPI_CFG_EN_CLR_MSK    0xfffffffe\r
/* The reset value of the ALT_QSPI_CFG_EN register field. */\r
#define ALT_QSPI_CFG_EN_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_EN field value from a register. */\r
#define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)\r
/* Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)\r
\r
/*\r
 * Field : Clock Polarity - selclkpol\r
 * \r
 * Controls spiclk modes of operation.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                          | Value | Description                \r
 * :------------------------------|:------|:----------------------------\r
 *  ALT_QSPI_CFG_SELCLKPOL_E_LOW  | 0x1   | SPI clock is quiescent low \r
 *  ALT_QSPI_CFG_SELCLKPOL_E_HIGH | 0x0   | SPI clock is quiescent high\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL\r
 * \r
 * SPI clock is quiescent low\r
 */\r
#define ALT_QSPI_CFG_SELCLKPOL_E_LOW    0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL\r
 * \r
 * SPI clock is quiescent high\r
 */\r
#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH   0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */\r
#define ALT_QSPI_CFG_SELCLKPOL_LSB        1\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field. */\r
#define ALT_QSPI_CFG_SELCLKPOL_MSB        1\r
/* The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field. */\r
#define ALT_QSPI_CFG_SELCLKPOL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value. */\r
#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK    0x00000002\r
/* The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value. */\r
#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK    0xfffffffd\r
/* The reset value of the ALT_QSPI_CFG_SELCLKPOL register field. */\r
#define ALT_QSPI_CFG_SELCLKPOL_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register. */\r
#define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)\r
/* Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)\r
\r
/*\r
 * Field : Select Clock Phase - selclkphase\r
 * \r
 * Selects whether the clock is in an active or inactive phase outside the SPI\r
 * word.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                             | Value | Description               \r
 * :---------------------------------|:------|:---------------------------\r
 *  ALT_QSPI_CFG_SELCLKPHASE_E_ACT   | 0x0   | SPI clock is quiescent low\r
 *  ALT_QSPI_CFG_SELCLKPHASE_E_INACT | 0x1   | Clock Inactive            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE\r
 * \r
 * SPI clock is quiescent low\r
 */\r
#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT      0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE\r
 * \r
 * Clock Inactive\r
 */\r
#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT    0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */\r
#define ALT_QSPI_CFG_SELCLKPHASE_LSB        2\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field. */\r
#define ALT_QSPI_CFG_SELCLKPHASE_MSB        2\r
/* The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field. */\r
#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value. */\r
#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK    0x00000004\r
/* The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value. */\r
#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK    0xfffffffb\r
/* The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field. */\r
#define ALT_QSPI_CFG_SELCLKPHASE_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register. */\r
#define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)\r
/* Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)\r
\r
/*\r
 * Field : Enable Direct Access Controller - endiracc\r
 * \r
 * If disabled, the Direct Access Controller becomes inactive once the current\r
 * transfer of the data word (FF_W) is complete. When the Direct Access Controller\r
 * and Indirect Access Controller are both disabled, all AHB requests are completed\r
 * with an error response.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                        | Value | Description               \r
 * :----------------------------|:------|:---------------------------\r
 *  ALT_QSPI_CFG_ENDIRACC_E_DIS | 0x0   | Disable Direct Access Ctrl\r
 *  ALT_QSPI_CFG_ENDIRACC_E_EN  | 0x1   | Enable Direct Access Ctrl \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC\r
 * \r
 * Disable Direct Access Ctrl\r
 */\r
#define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENDIRACC\r
 * \r
 * Enable Direct Access Ctrl\r
 */\r
#define ALT_QSPI_CFG_ENDIRACC_E_EN  0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */\r
#define ALT_QSPI_CFG_ENDIRACC_LSB        7\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field. */\r
#define ALT_QSPI_CFG_ENDIRACC_MSB        7\r
/* The width in bits of the ALT_QSPI_CFG_ENDIRACC register field. */\r
#define ALT_QSPI_CFG_ENDIRACC_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value. */\r
#define ALT_QSPI_CFG_ENDIRACC_SET_MSK    0x00000080\r
/* The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value. */\r
#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK    0xffffff7f\r
/* The reset value of the ALT_QSPI_CFG_ENDIRACC register field. */\r
#define ALT_QSPI_CFG_ENDIRACC_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register. */\r
#define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)\r
/* Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)\r
\r
/*\r
 * Field : Legacy IP Mode Enable - enlegacyip\r
 * \r
 * This bit can select the Direct Access Controller/Indirect Access Controller or\r
 * legacy mode.If legacy mode is selected, any write to the controller via the AHB\r
 * interface is serialized and sent to the FLASH device. Any valid AHB read will\r
 * pop the internal RX-FIFO, retrieving data that was forwarded by the external\r
 * FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and\r
 * controlled via the HSIZE input.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                             | Value | Description                          \r
 * :---------------------------------|:------|:--------------------------------------\r
 *  ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD | 0x1   | Legacy Mode                          \r
 *  ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD  | 0x0   | Use Direct/Indirect Access Controller\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP\r
 * \r
 * Legacy Mode\r
 */\r
#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD    0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP\r
 * \r
 * Use Direct/Indirect Access Controller\r
 */\r
#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD     0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */\r
#define ALT_QSPI_CFG_ENLEGACYIP_LSB        8\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field. */\r
#define ALT_QSPI_CFG_ENLEGACYIP_MSB        8\r
/* The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field. */\r
#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value. */\r
#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK    0x00000100\r
/* The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value. */\r
#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK    0xfffffeff\r
/* The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field. */\r
#define ALT_QSPI_CFG_ENLEGACYIP_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register. */\r
#define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)\r
/* Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)\r
\r
/*\r
 * Field : Peripheral select decode - perseldec\r
 * \r
 * Select between '1 of 4 selects' or 'external 4-to-16 decode'. The\r
 * qspi_n_ss_out[3:0] output signals are controlled.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                      \r
 * :----------------------------------|:------|:----------------------------------\r
 *  ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 | 0x1   | Select external 4-to-16 decode   \r
 *  ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4  | 0x0   | Selects 1 of 4 qspi_n_ss_out[3:0]\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC\r
 * \r
 * Select external 4-to-16 decode\r
 */\r
#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16   0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_PERSELDEC\r
 * \r
 * Selects 1 of 4 qspi_n_ss_out[3:0]\r
 */\r
#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */\r
#define ALT_QSPI_CFG_PERSELDEC_LSB        9\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field. */\r
#define ALT_QSPI_CFG_PERSELDEC_MSB        9\r
/* The width in bits of the ALT_QSPI_CFG_PERSELDEC register field. */\r
#define ALT_QSPI_CFG_PERSELDEC_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value. */\r
#define ALT_QSPI_CFG_PERSELDEC_SET_MSK    0x00000200\r
/* The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value. */\r
#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK    0xfffffdff\r
/* The reset value of the ALT_QSPI_CFG_PERSELDEC register field. */\r
#define ALT_QSPI_CFG_PERSELDEC_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register. */\r
#define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)\r
/* Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)\r
\r
/*\r
 * Field : Peripheral Chip Select Lines - percslines\r
 * \r
 * Peripheral chip select line output decode type. As per perseldec, if perseldec =\r
 * 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The\r
 * asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0]\r
 * require an external 4 to 16 decoder.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */\r
#define ALT_QSPI_CFG_PERCSLINES_LSB        10\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field. */\r
#define ALT_QSPI_CFG_PERCSLINES_MSB        13\r
/* The width in bits of the ALT_QSPI_CFG_PERCSLINES register field. */\r
#define ALT_QSPI_CFG_PERCSLINES_WIDTH      4\r
/* The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value. */\r
#define ALT_QSPI_CFG_PERCSLINES_SET_MSK    0x00003c00\r
/* The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value. */\r
#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK    0xffffc3ff\r
/* The reset value of the ALT_QSPI_CFG_PERCSLINES register field. */\r
#define ALT_QSPI_CFG_PERCSLINES_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register. */\r
#define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)\r
/* Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)\r
\r
/*\r
 * Field : Write Protect Flash Pin - wp\r
 * \r
 * This bit controls the write protect pin of the flash devices. The signal\r
 * qspi_mo2_wpn needs to be resynchronized to the generated memory clock as\r
 * necessary.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                         | Value | Description          \r
 * :-----------------------------|:------|:----------------------\r
 *  ALT_QSPI_CFG_WP_E_WRPROTON   | 0x1   | Enable Write Protect \r
 *  ALT_QSPI_CFG_WP_E_WRTPROTOFF | 0x0   | Disable Write Protect\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_WP\r
 * \r
 * Enable Write Protect\r
 */\r
#define ALT_QSPI_CFG_WP_E_WRPROTON      0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_WP\r
 * \r
 * Disable Write Protect\r
 */\r
#define ALT_QSPI_CFG_WP_E_WRTPROTOFF    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field. */\r
#define ALT_QSPI_CFG_WP_LSB        14\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field. */\r
#define ALT_QSPI_CFG_WP_MSB        14\r
/* The width in bits of the ALT_QSPI_CFG_WP register field. */\r
#define ALT_QSPI_CFG_WP_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_WP register field value. */\r
#define ALT_QSPI_CFG_WP_SET_MSK    0x00004000\r
/* The mask used to clear the ALT_QSPI_CFG_WP register field value. */\r
#define ALT_QSPI_CFG_WP_CLR_MSK    0xffffbfff\r
/* The reset value of the ALT_QSPI_CFG_WP register field. */\r
#define ALT_QSPI_CFG_WP_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_WP field value from a register. */\r
#define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)\r
/* Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)\r
\r
/*\r
 * Field : Enable DMA Peripheral Interface - endma\r
 * \r
 * Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer\r
 * requests via the DMA peripheral interface.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                     | Value | Description     \r
 * :-------------------------|:------|:-----------------\r
 *  ALT_QSPI_CFG_ENDMA_E_EN  | 0x1   | Enable DMA Mode \r
 *  ALT_QSPI_CFG_ENDMA_E_DIS | 0x0   | Disable DMA Mode\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENDMA\r
 * \r
 * Enable DMA Mode\r
 */\r
#define ALT_QSPI_CFG_ENDMA_E_EN     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENDMA\r
 * \r
 * Disable DMA Mode\r
 */\r
#define ALT_QSPI_CFG_ENDMA_E_DIS    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field. */\r
#define ALT_QSPI_CFG_ENDMA_LSB        15\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field. */\r
#define ALT_QSPI_CFG_ENDMA_MSB        15\r
/* The width in bits of the ALT_QSPI_CFG_ENDMA register field. */\r
#define ALT_QSPI_CFG_ENDMA_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_ENDMA register field value. */\r
#define ALT_QSPI_CFG_ENDMA_SET_MSK    0x00008000\r
/* The mask used to clear the ALT_QSPI_CFG_ENDMA register field value. */\r
#define ALT_QSPI_CFG_ENDMA_CLR_MSK    0xffff7fff\r
/* The reset value of the ALT_QSPI_CFG_ENDMA register field. */\r
#define ALT_QSPI_CFG_ENDMA_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_ENDMA field value from a register. */\r
#define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)\r
/* Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)\r
\r
/*\r
 * Field : Enable AHB Address Re-mapping - enahbremap\r
 * \r
 * (Direct Access Mode Only) When enabled, the incoming AHB address will be adapted\r
 * and sent to the FLASH device as (address + N), where N is the value stored in\r
 * the remap address register.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                          | Value | Description           \r
 * :------------------------------|:------|:-----------------------\r
 *  ALT_QSPI_CFG_ENAHBREMAP_E_EN  | 0x1   | Enable AHB Re-mapping \r
 *  ALT_QSPI_CFG_ENAHBREMAP_E_DIS | 0x0   | Disable AHB Re-mapping\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP\r
 * \r
 * Enable AHB Re-mapping\r
 */\r
#define ALT_QSPI_CFG_ENAHBREMAP_E_EN    0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP\r
 * \r
 * Disable AHB Re-mapping\r
 */\r
#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS   0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */\r
#define ALT_QSPI_CFG_ENAHBREMAP_LSB        16\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field. */\r
#define ALT_QSPI_CFG_ENAHBREMAP_MSB        16\r
/* The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field. */\r
#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value. */\r
#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK    0x00010000\r
/* The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value. */\r
#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK    0xfffeffff\r
/* The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field. */\r
#define ALT_QSPI_CFG_ENAHBREMAP_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register. */\r
#define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)\r
/* Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)\r
\r
/*\r
 * Field : Enter XIP Mode on next READ - enterxipnextrd\r
 * \r
 * If XIP is enabled, then setting to disabled will cause the controller to exit\r
 * XIP mode on the next READ instruction. If XIP is disabled, then setting to\r
 * enabled will inform the controller that the device is ready to enter XIP on the\r
 * next READ instruction. The controller will therefore send the appropriate\r
 * command sequence, including mode bits to cause the device to enter XIP mode. Use\r
 * this register after the controller has ensured the FLASH device has been\r
 * configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit\r
 * should be set to 0. This will take effect in the attached device only AFTER the\r
 * next READ instruction is executed. Software should therefore ensure that at\r
 * least one READ instruction is requested after resetting this bit before it can\r
 * be sure XIP mode in the device is exited.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                            \r
 * :----------------------------------|:------|:----------------------------------------\r
 *  ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN  | 0x1   | Enter XIP Mode on next READ instruction\r
 *  ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS | 0x0   | Exit XIP Mode on next READ instruction \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD\r
 * \r
 * Enter XIP Mode on next READ instruction\r
 */\r
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN    0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD\r
 * \r
 * Exit XIP Mode on next READ instruction\r
 */\r
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS   0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */\r
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB        17\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */\r
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB        17\r
/* The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */\r
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */\r
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK    0x00020000\r
/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value. */\r
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK    0xfffdffff\r
/* The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field. */\r
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register. */\r
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)\r
/* Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)\r
\r
/*\r
 * Field : Enter XIP Mode Immediately - enterxipimm\r
 * \r
 * If XIP is enabled, then setting to disabled will cause the controller to exit\r
 * XIP mode on the next READ instruction. If XIP is disabled, then setting enable\r
 * will operate the device in XIP mode immediately. Use this register when the\r
 * external device wakes up in XIP mode (as per the contents of its non- volatile\r
 * configuration register). The controller will assume the next READ instruction\r
 * will be passed to the device as an XIP instruction, and therefore will not\r
 * require the READ opcode to be transferred. Note: To exit XIP mode, this bit\r
 * should be set to 0. This will take effect in the attached device only after the\r
 * next READ instruction is executed. Software therefore should ensure that at\r
 * least one READ instruction is requested after resetting this bit in order to be\r
 * sure that XIP mode is exited.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                           | Value | Description                           \r
 * :-------------------------------|:------|:---------------------------------------\r
 *  ALT_QSPI_CFG_ENTERXIPIMM_E_EN  | 0x1   | Enter XIP Mode immediately            \r
 *  ALT_QSPI_CFG_ENTERXIPIMM_E_DIS | 0x0   | Exit XIP Mode on next READ instruction\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM\r
 * \r
 * Enter XIP Mode immediately\r
 */\r
#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN   0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM\r
 * \r
 * Exit XIP Mode on next READ instruction\r
 */\r
#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS  0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */\r
#define ALT_QSPI_CFG_ENTERXIPIMM_LSB        18\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field. */\r
#define ALT_QSPI_CFG_ENTERXIPIMM_MSB        18\r
/* The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field. */\r
#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value. */\r
#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK    0x00040000\r
/* The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value. */\r
#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK    0xfffbffff\r
/* The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field. */\r
#define ALT_QSPI_CFG_ENTERXIPIMM_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register. */\r
#define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)\r
/* Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)\r
\r
/*\r
 * Field : Master Mode Baud Rate Divisor - bauddiv\r
 * \r
 * SPI baud rate = ref_clk / (2 * baud_rate_divisor)\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                          | Value | Description     \r
 * :------------------------------|:------|:-----------------\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD2  | 0x0   | Baud Rate Div/2 \r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD4  | 0x1   | Baud Rate Div/4 \r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD6  | 0x2   | Baud Rate Div/6 \r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD8  | 0x3   | Baud Rate Div/8 \r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD10 | 0x4   | Baud Rate Div/10\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD12 | 0x5   | Baud Rate Div/12\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD14 | 0x6   | Baud Rate Div/14\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD16 | 0x7   | Baud Rate Div/16\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD18 | 0x8   | Baud Rate Div/18\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD20 | 0x9   | Baud Rate Div/20\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD22 | 0xa   | Baud Rate Div/22\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD24 | 0xb   | Baud Rate Div/24\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD26 | 0xc   | Baud Rate Div/26\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD28 | 0xd   | Baud Rate Div/28\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD30 | 0xe   | Baud Rate Div/30\r
 *  ALT_QSPI_CFG_BAUDDIV_E_BAUD32 | 0xf   | Baud Rate Div/32\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/2\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2    0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/4\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4    0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/6\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6    0x2\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/8\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8    0x3\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/10\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10   0x4\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/12\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12   0x5\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/14\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14   0x6\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/16\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16   0x7\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/18\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18   0x8\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/20\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20   0x9\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/22\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22   0xa\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/24\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24   0xb\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/26\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26   0xc\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/28\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28   0xd\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/30\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30   0xe\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_BAUDDIV\r
 * \r
 * Baud Rate Div/32\r
 */\r
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32   0xf\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */\r
#define ALT_QSPI_CFG_BAUDDIV_LSB        19\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field. */\r
#define ALT_QSPI_CFG_BAUDDIV_MSB        22\r
/* The width in bits of the ALT_QSPI_CFG_BAUDDIV register field. */\r
#define ALT_QSPI_CFG_BAUDDIV_WIDTH      4\r
/* The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value. */\r
#define ALT_QSPI_CFG_BAUDDIV_SET_MSK    0x00780000\r
/* The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value. */\r
#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK    0xff87ffff\r
/* The reset value of the ALT_QSPI_CFG_BAUDDIV register field. */\r
#define ALT_QSPI_CFG_BAUDDIV_RESET      0xf\r
/* Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register. */\r
#define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)\r
/* Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)\r
\r
/*\r
 * Field : Serial interface and QSPI pipeline is IDLE - idle\r
 * \r
 * This is a STATUS read-only bit. Note this is a retimed signal, so there will be\r
 * some inherent delay on the generation of this status signal.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                       | Value | Description  \r
 * :---------------------------|:------|:--------------\r
 *  ALT_QSPI_CFG_IDLE_E_SET    | 0x1   | Idle Mode    \r
 *  ALT_QSPI_CFG_IDLE_E_NOTSET | 0x0   | Non-Idle Mode\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_IDLE\r
 * \r
 * Idle Mode\r
 */\r
#define ALT_QSPI_CFG_IDLE_E_SET     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_CFG_IDLE\r
 * \r
 * Non-Idle Mode\r
 */\r
#define ALT_QSPI_CFG_IDLE_E_NOTSET  0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field. */\r
#define ALT_QSPI_CFG_IDLE_LSB        31\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field. */\r
#define ALT_QSPI_CFG_IDLE_MSB        31\r
/* The width in bits of the ALT_QSPI_CFG_IDLE register field. */\r
#define ALT_QSPI_CFG_IDLE_WIDTH      1\r
/* The mask used to set the ALT_QSPI_CFG_IDLE register field value. */\r
#define ALT_QSPI_CFG_IDLE_SET_MSK    0x80000000\r
/* The mask used to clear the ALT_QSPI_CFG_IDLE register field value. */\r
#define ALT_QSPI_CFG_IDLE_CLR_MSK    0x7fffffff\r
/* The reset value of the ALT_QSPI_CFG_IDLE register field. */\r
#define ALT_QSPI_CFG_IDLE_RESET      0x0\r
/* Extracts the ALT_QSPI_CFG_IDLE field value from a register. */\r
#define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)\r
/* Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register. */\r
#define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_CFG.\r
 */\r
struct ALT_QSPI_CFG_s\r
{\r
    uint32_t        en             :  1;  /* QSPI Enable */\r
    uint32_t        selclkpol      :  1;  /* Clock Polarity */\r
    uint32_t        selclkphase    :  1;  /* Select Clock Phase */\r
    uint32_t                       :  4;  /* *UNDEFINED* */\r
    uint32_t        endiracc       :  1;  /* Enable Direct Access Controller */\r
    uint32_t        enlegacyip     :  1;  /* Legacy IP Mode Enable */\r
    uint32_t        perseldec      :  1;  /* Peripheral select decode */\r
    uint32_t        percslines     :  4;  /* Peripheral Chip Select Lines */\r
    uint32_t        wp             :  1;  /* Write Protect Flash Pin */\r
    uint32_t        endma          :  1;  /* Enable DMA Peripheral Interface */\r
    uint32_t        enahbremap     :  1;  /* Enable AHB Address Re-mapping */\r
    uint32_t        enterxipnextrd :  1;  /* Enter XIP Mode on next READ */\r
    uint32_t        enterxipimm    :  1;  /* Enter XIP Mode Immediately */\r
    uint32_t        bauddiv        :  4;  /* Master Mode Baud Rate Divisor */\r
    uint32_t                       :  8;  /* *UNDEFINED* */\r
    const uint32_t  idle           :  1;  /* Serial interface and QSPI pipeline is IDLE */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_CFG. */\r
typedef volatile struct ALT_QSPI_CFG_s  ALT_QSPI_CFG_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_CFG register from the beginning of the component. */\r
#define ALT_QSPI_CFG_OFST        0x0\r
\r
/*\r
 * Register : Device Read Instruction Register - devrd\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset | Description                \r
 * :--------|:-------|:------|:----------------------------\r
 *  [7:0]   | RW     | 0x3   | Read Opcode in non-XIP mode\r
 *  [9:8]   | RW     | 0x0   | Instruction Transfer Width \r
 *  [11:10] | ???    | 0x0   | *UNDEFINED*                \r
 *  [13:12] | RW     | 0x0   | Address Transfer Width     \r
 *  [15:14] | ???    | 0x0   | *UNDEFINED*                \r
 *  [17:16] | RW     | 0x0   | Data Transfer Width        \r
 *  [19:18] | ???    | 0x0   | *UNDEFINED*                \r
 *  [20]    | RW     | 0x0   | Mode Bit Enable            \r
 *  [23:21] | ???    | 0x0   | *UNDEFINED*                \r
 *  [28:24] | RW     | 0x0   | Dummy Read Clock Cycles    \r
 *  [31:29] | ???    | 0x0   | *UNDEFINED*                \r
 * \r
 */\r
/*\r
 * Field : Read Opcode in non-XIP mode - rdopcode\r
 * \r
 * Read Opcode to use when not in XIP mode\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                             | Value | Description                \r
 * :---------------------------------|:------|:----------------------------\r
 *  ALT_QSPI_DEVRD_RDOPCODE_E_RD     | 0x3   | Read Opcode in Non-XIP mode\r
 *  ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD | 0xb   | Fast Read in Non-XIP mode  \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE\r
 * \r
 * Read Opcode in Non-XIP mode\r
 */\r
#define ALT_QSPI_DEVRD_RDOPCODE_E_RD        0x3\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE\r
 * \r
 * Fast Read in Non-XIP mode\r
 */\r
#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD    0xb\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */\r
#define ALT_QSPI_DEVRD_RDOPCODE_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field. */\r
#define ALT_QSPI_DEVRD_RDOPCODE_MSB        7\r
/* The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field. */\r
#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH      8\r
/* The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value. */\r
#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK    0x000000ff\r
/* The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value. */\r
#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK    0xffffff00\r
/* The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field. */\r
#define ALT_QSPI_DEVRD_RDOPCODE_RESET      0x3\r
/* Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register. */\r
#define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)\r
/* Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)\r
\r
/*\r
 * Field : Instruction Transfer Width - instwidth\r
 * \r
 * Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions\r
 * sent to SPI flash device (not just read instructions).\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                                     \r
 * :----------------------------------|:------|:-------------------------------------------------\r
 *  ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE | 0x0   | Instruction transferred on DQ0. Supported by all\r
 * :                                  |       | SPI flash devices.                              \r
 *  ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL   | 0x1   | Instruction transferred on DQ0 and DQ1.         \r
 * :                                  |       | Supported by all SPI flash devices that support \r
 * :                                  |       | the Dual SP (DIO-SPI) Protocol.                 \r
 *  ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD   | 0x2   | Instruction transferred on DQ0, DQ1, DQ2, and   \r
 * :                                  |       | DQ3. Supported by all SPI flash devices that    \r
 * :                                  |       | support the Quad SP (QIO-SPI) Protocol.         \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH\r
 * \r
 * Instruction transferred on DQ0. Supported by all SPI flash devices.\r
 */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH\r
 * \r
 * Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that\r
 * support the Dual SP (DIO-SPI) Protocol.\r
 */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH\r
 * \r
 * Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash\r
 * devices that support the Quad SP (QIO-SPI) Protocol.\r
 */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD     0x2\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_LSB        8\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field. */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_MSB        9\r
/* The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field. */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH      2\r
/* The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value. */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK    0x00000300\r
/* The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value. */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK    0xfffffcff\r
/* The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field. */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_RESET      0x0\r
/* Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register. */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)\r
/* Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)\r
\r
/*\r
 * Field : Address Transfer Width - addrwidth\r
 * \r
 * Sets read address transfer width (1, 2, or 4 bits).\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                                     \r
 * :----------------------------------|:------|:-------------------------------------------------\r
 *  ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE | 0x0   | Read address transferred on DQ0. Supported by   \r
 * :                                  |       | all SPI flash devices                           \r
 *  ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL   | 0x1   | Read address transferred on DQ0 and DQ1.        \r
 * :                                  |       | Supported by some SPI flash devices that support\r
 * :                                  |       | the Extended SPI Protocol and by all SPI flash  \r
 * :                                  |       | devices that support the Dual SP (DIO-SPI)      \r
 * :                                  |       | Protocol.                                       \r
 *  ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD   | 0x2   | Read address transferred on DQ0, DQ1, DQ2, and  \r
 * :                                  |       | DQ3. Supported by some SPI flash devices that   \r
 * :                                  |       | support the Extended SPI Protocol and by all SPI\r
 * :                                  |       | flash devices that support the Quad SP (QIO-SPI)\r
 * :                                  |       | Protocol.                                       \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH\r
 * \r
 * Read address transferred on DQ0. Supported by all SPI flash devices\r
 */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH\r
 * \r
 * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices\r
 * that support the Extended SPI Protocol and by all SPI flash devices that support\r
 * the Dual SP (DIO-SPI) Protocol.\r
 */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH\r
 * \r
 * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash\r
 * devices that support the Extended SPI Protocol and by all SPI flash devices that\r
 * support the Quad SP (QIO-SPI) Protocol.\r
 */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD     0x2\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB        12\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB        13\r
/* The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH      2\r
/* The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK    0x00003000\r
/* The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value. */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK    0xffffcfff\r
/* The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field. */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET      0x0\r
/* Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register. */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)\r
/* Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)\r
\r
/*\r
 * Field : Data Transfer Width - datawidth\r
 * \r
 * Sets read data transfer width (1, 2, or 4 bits).\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                                     \r
 * :----------------------------------|:------|:-------------------------------------------------\r
 *  ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE | 0x0   | Read data transferred on DQ0. Supported by all  \r
 * :                                  |       | SPI flash devices                               \r
 *  ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL   | 0x1   | Read data transferred on DQ0 and DQ1. Supported \r
 * :                                  |       | by some SPI flash devices that support the      \r
 * :                                  |       | Extended SPI Protocol and by all SPI flash      \r
 * :                                  |       | devices that support the Dual SP (DIO-SPI)      \r
 * :                                  |       | Protocol.                                       \r
 *  ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD   | 0x2   | Read data transferred on DQ0, DQ1, DQ2, and DQ3.\r
 * :                                  |       | Supported by some SPI flash devices that support\r
 * :                                  |       | the Extended SPI Protocol and by all SPI flash  \r
 * :                                  |       | devices that support the Quad SP (QIO-SPI)      \r
 * :                                  |       | Protocol.                                       \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH\r
 * \r
 * Read data transferred on DQ0. Supported by all SPI flash devices\r
 */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH\r
 * \r
 * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that\r
 * support the Extended SPI Protocol and by all SPI flash devices that support the\r
 * Dual SP (DIO-SPI) Protocol.\r
 */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH\r
 * \r
 * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash\r
 * devices that support the Extended SPI Protocol and by all SPI flash devices that\r
 * support the Quad SP (QIO-SPI) Protocol.\r
 */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD     0x2\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_LSB        16\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field. */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_MSB        17\r
/* The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field. */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH      2\r
/* The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value. */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK    0x00030000\r
/* The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value. */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK    0xfffcffff\r
/* The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field. */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_RESET      0x0\r
/* Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register. */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)\r
/* Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)\r
\r
/*\r
 * Field : Mode Bit Enable - enmodebits\r
 * \r
 * If this bit is set, the mode bits as defined in the Mode Bit Configuration\r
 * register are sent following the address bytes.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                               | Value | Description                   \r
 * :-----------------------------------|:------|:-------------------------------\r
 *  ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER | 0x0   | No Order                      \r
 *  ALT_QSPI_DEVRD_ENMODBITS_E_ORDER   | 0x1   | Mode Bits follow address bytes\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS\r
 * \r
 * No Order\r
 */\r
#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER  0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS\r
 * \r
 * Mode Bits follow address bytes\r
 */\r
#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER    0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */\r
#define ALT_QSPI_DEVRD_ENMODBITS_LSB        20\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field. */\r
#define ALT_QSPI_DEVRD_ENMODBITS_MSB        20\r
/* The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field. */\r
#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH      1\r
/* The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value. */\r
#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK    0x00100000\r
/* The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value. */\r
#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK    0xffefffff\r
/* The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field. */\r
#define ALT_QSPI_DEVRD_ENMODBITS_RESET      0x0\r
/* Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register. */\r
#define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20)\r
/* Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000)\r
\r
/*\r
 * Field : Dummy Read Clock Cycles - dummyrdclks\r
 * \r
 * Number of dummy clock cycles required by device for read instruction.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */\r
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB        24\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */\r
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB        28\r
/* The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */\r
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH      5\r
/* The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */\r
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK    0x1f000000\r
/* The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value. */\r
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK    0xe0ffffff\r
/* The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field. */\r
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET      0x0\r
/* Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register. */\r
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)\r
/* Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_DEVRD.\r
 */\r
struct ALT_QSPI_DEVRD_s\r
{\r
    uint32_t  rdopcode    :  8;  /* Read Opcode in non-XIP mode */\r
    uint32_t  instwidth   :  2;  /* Instruction Transfer Width */\r
    uint32_t              :  2;  /* *UNDEFINED* */\r
    uint32_t  addrwidth   :  2;  /* Address Transfer Width */\r
    uint32_t              :  2;  /* *UNDEFINED* */\r
    uint32_t  datawidth   :  2;  /* Data Transfer Width */\r
    uint32_t              :  2;  /* *UNDEFINED* */\r
    uint32_t  enmodebits  :  1;  /* Mode Bit Enable */\r
    uint32_t              :  3;  /* *UNDEFINED* */\r
    uint32_t  dummyrdclks :  5;  /* Dummy Read Clock Cycles */\r
    uint32_t              :  3;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_DEVRD. */\r
typedef volatile struct ALT_QSPI_DEVRD_s  ALT_QSPI_DEVRD_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component. */\r
#define ALT_QSPI_DEVRD_OFST        0x4\r
\r
/*\r
 * Register : Device Write Instruction Register - devwr\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset | Description             \r
 * :--------|:-------|:------|:-------------------------\r
 *  [7:0]   | RW     | 0x2   | Write Opcode            \r
 *  [11:8]  | ???    | 0x0   | *UNDEFINED*             \r
 *  [13:12] | RW     | 0x0   | Address Transfer Width  \r
 *  [15:14] | ???    | 0x0   | *UNDEFINED*             \r
 *  [17:16] | RW     | 0x0   | Data Transfer Width     \r
 *  [23:18] | ???    | 0x0   | *UNDEFINED*             \r
 *  [28:24] | RW     | 0x0   | Dummy Write Clock Cycles\r
 *  [31:29] | ???    | 0x0   | *UNDEFINED*             \r
 * \r
 */\r
/*\r
 * Field : Write Opcode - wropcode\r
 * \r
 * Write Opcode\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */\r
#define ALT_QSPI_DEVWR_WROPCODE_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field. */\r
#define ALT_QSPI_DEVWR_WROPCODE_MSB        7\r
/* The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field. */\r
#define ALT_QSPI_DEVWR_WROPCODE_WIDTH      8\r
/* The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value. */\r
#define ALT_QSPI_DEVWR_WROPCODE_SET_MSK    0x000000ff\r
/* The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value. */\r
#define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK    0xffffff00\r
/* The reset value of the ALT_QSPI_DEVWR_WROPCODE register field. */\r
#define ALT_QSPI_DEVWR_WROPCODE_RESET      0x2\r
/* Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register. */\r
#define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)\r
/* Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)\r
\r
/*\r
 * Field : Address Transfer Width - addrwidth\r
 * \r
 * Sets write address transfer width (1, 2, or 4 bits).\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                                     \r
 * :----------------------------------|:------|:-------------------------------------------------\r
 *  ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE | 0x0   | Write address transferred on DQ0. Supported by  \r
 * :                                  |       | all SPI flash devices                           \r
 *  ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL   | 0x1   | Read address transferred on DQ0 and DQ1.        \r
 * :                                  |       | Supported by some SPI flash devices that support\r
 * :                                  |       | the Extended SPI Protocol and by all SPI flash  \r
 * :                                  |       | devices that support the Dual SP (DIO-SPI)      \r
 * :                                  |       | Protocol.                                       \r
 *  ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD   | 0x2   | Read address transferred on DQ0, DQ1, DQ2, and  \r
 * :                                  |       | DQ3. Supported by some SPI flash devices that   \r
 * :                                  |       | support the Extended SPI Protocol and by all SPI\r
 * :                                  |       | flash devices that support the Quad SP (QIO-SPI)\r
 * :                                  |       | Protocol.                                       \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH\r
 * \r
 * Write address transferred on DQ0. Supported by all SPI flash devices\r
 */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH\r
 * \r
 * Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices\r
 * that support the Extended SPI Protocol and by all SPI flash devices that support\r
 * the Dual SP (DIO-SPI) Protocol.\r
 */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH\r
 * \r
 * Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash\r
 * devices that support the Extended SPI Protocol and by all SPI flash devices that\r
 * support the Quad SP (QIO-SPI) Protocol.\r
 */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD     0x2\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_LSB        12\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_MSB        13\r
/* The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH      2\r
/* The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK    0x00003000\r
/* The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value. */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK    0xffffcfff\r
/* The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field. */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_RESET      0x0\r
/* Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register. */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)\r
/* Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)\r
\r
/*\r
 * Field : Data Transfer Width - datawidth\r
 * \r
 * Sets write data transfer width (1, 2, or 4 bits).\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                                     \r
 * :----------------------------------|:------|:-------------------------------------------------\r
 *  ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE | 0x0   | Write data transferred on DQ0. Supported by all \r
 * :                                  |       | SPI flash devices                               \r
 *  ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL   | 0x1   | Read data transferred on DQ0 and DQ1. Supported \r
 * :                                  |       | by some SPI flash devices that support the      \r
 * :                                  |       | Extended SPI Protocol and by all SPI flash      \r
 * :                                  |       | devices that support the Dual SP (DIO-SPI)      \r
 * :                                  |       | Protocol.                                       \r
 *  ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD   | 0x2   | Read data transferred on DQ0, DQ1, DQ2, and DQ3.\r
 * :                                  |       | Supported by some SPI flash devices that support\r
 * :                                  |       | the Extended SPI Protocol and by all SPI flash  \r
 * :                                  |       | devices that support the Quad SP (QIO-SPI)      \r
 * :                                  |       | Protocol.                                       \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH\r
 * \r
 * Write data transferred on DQ0. Supported by all SPI flash devices\r
 */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH\r
 * \r
 * Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that\r
 * support the Extended SPI Protocol and by all SPI flash devices that support the\r
 * Dual SP (DIO-SPI) Protocol.\r
 */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH\r
 * \r
 * Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash\r
 * devices that support the Extended SPI Protocol and by all SPI flash devices that\r
 * support the Quad SP (QIO-SPI) Protocol.\r
 */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD     0x2\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_LSB        16\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field. */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_MSB        17\r
/* The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field. */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH      2\r
/* The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value. */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK    0x00030000\r
/* The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value. */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK    0xfffcffff\r
/* The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field. */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_RESET      0x0\r
/* Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register. */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)\r
/* Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)\r
\r
/*\r
 * Field : Dummy Write Clock Cycles - dummywrclks\r
 * \r
 * Number of dummy clock cycles required by device for write instruction.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */\r
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB        24\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */\r
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB        28\r
/* The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */\r
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH      5\r
/* The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */\r
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK    0x1f000000\r
/* The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value. */\r
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK    0xe0ffffff\r
/* The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field. */\r
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET      0x0\r
/* Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register. */\r
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)\r
/* Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_DEVWR.\r
 */\r
struct ALT_QSPI_DEVWR_s\r
{\r
    uint32_t  wropcode    :  8;  /* Write Opcode */\r
    uint32_t              :  4;  /* *UNDEFINED* */\r
    uint32_t  addrwidth   :  2;  /* Address Transfer Width */\r
    uint32_t              :  2;  /* *UNDEFINED* */\r
    uint32_t  datawidth   :  2;  /* Data Transfer Width */\r
    uint32_t              :  6;  /* *UNDEFINED* */\r
    uint32_t  dummywrclks :  5;  /* Dummy Write Clock Cycles */\r
    uint32_t              :  3;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_DEVWR. */\r
typedef volatile struct ALT_QSPI_DEVWR_s  ALT_QSPI_DEVWR_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component. */\r
#define ALT_QSPI_DEVWR_OFST        0x8\r
\r
/*\r
 * Register : QSPI Device Delay Register - delay\r
 * \r
 * This register is used to introduce relative delays into the generation of the\r
 * master output signals. All timings are defined in cycles of the qspi_clk.\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset | Description                             \r
 * :--------|:-------|:------|:-----------------------------------------\r
 *  [7:0]   | RW     | 0x0   | Clock Delay with qspi_n_ss_out          \r
 *  [15:8]  | RW     | 0x0   | Clock Delay for Last Transaction Bit    \r
 *  [23:16] | RW     | 0x0   | Clock Delay for Chip Select Deactivation\r
 *  [31:24] | RW     | 0x0   | Clock Delay for Chip Select Deassert    \r
 * \r
 */\r
/*\r
 * Field : Clock Delay with qspi_n_ss_out - init\r
 * \r
 * Delay in master reference clocks between setting qspi_n_ss_out low and first bit\r
 * transfer.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field. */\r
#define ALT_QSPI_DELAY_INIT_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field. */\r
#define ALT_QSPI_DELAY_INIT_MSB        7\r
/* The width in bits of the ALT_QSPI_DELAY_INIT register field. */\r
#define ALT_QSPI_DELAY_INIT_WIDTH      8\r
/* The mask used to set the ALT_QSPI_DELAY_INIT register field value. */\r
#define ALT_QSPI_DELAY_INIT_SET_MSK    0x000000ff\r
/* The mask used to clear the ALT_QSPI_DELAY_INIT register field value. */\r
#define ALT_QSPI_DELAY_INIT_CLR_MSK    0xffffff00\r
/* The reset value of the ALT_QSPI_DELAY_INIT register field. */\r
#define ALT_QSPI_DELAY_INIT_RESET      0x0\r
/* Extracts the ALT_QSPI_DELAY_INIT field value from a register. */\r
#define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)\r
/* Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register. */\r
#define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)\r
\r
/*\r
 * Field : Clock Delay for Last Transaction Bit - after\r
 * \r
 * Delay in master reference clocks between last bit of current transaction and\r
 * deasserting the device chip select (qspi_n_ss_out). By default, the chip select\r
 * will be deasserted on the cycle following the completion of the current\r
 * transaction.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field. */\r
#define ALT_QSPI_DELAY_AFTER_LSB        8\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field. */\r
#define ALT_QSPI_DELAY_AFTER_MSB        15\r
/* The width in bits of the ALT_QSPI_DELAY_AFTER register field. */\r
#define ALT_QSPI_DELAY_AFTER_WIDTH      8\r
/* The mask used to set the ALT_QSPI_DELAY_AFTER register field value. */\r
#define ALT_QSPI_DELAY_AFTER_SET_MSK    0x0000ff00\r
/* The mask used to clear the ALT_QSPI_DELAY_AFTER register field value. */\r
#define ALT_QSPI_DELAY_AFTER_CLR_MSK    0xffff00ff\r
/* The reset value of the ALT_QSPI_DELAY_AFTER register field. */\r
#define ALT_QSPI_DELAY_AFTER_RESET      0x0\r
/* Extracts the ALT_QSPI_DELAY_AFTER field value from a register. */\r
#define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)\r
/* Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register. */\r
#define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)\r
\r
/*\r
 * Field : Clock Delay for Chip Select Deactivation - btwn\r
 * \r
 * Delay in master reference clocks between one chip select being de-activated and\r
 * the activation of another. This is used to ensure a quiet period between the\r
 * selection of two different slaves and requires the transmit FIFO to be empty.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field. */\r
#define ALT_QSPI_DELAY_BTWN_LSB        16\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field. */\r
#define ALT_QSPI_DELAY_BTWN_MSB        23\r
/* The width in bits of the ALT_QSPI_DELAY_BTWN register field. */\r
#define ALT_QSPI_DELAY_BTWN_WIDTH      8\r
/* The mask used to set the ALT_QSPI_DELAY_BTWN register field value. */\r
#define ALT_QSPI_DELAY_BTWN_SET_MSK    0x00ff0000\r
/* The mask used to clear the ALT_QSPI_DELAY_BTWN register field value. */\r
#define ALT_QSPI_DELAY_BTWN_CLR_MSK    0xff00ffff\r
/* The reset value of the ALT_QSPI_DELAY_BTWN register field. */\r
#define ALT_QSPI_DELAY_BTWN_RESET      0x0\r
/* Extracts the ALT_QSPI_DELAY_BTWN field value from a register. */\r
#define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)\r
/* Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register. */\r
#define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)\r
\r
/*\r
 * Field : Clock Delay for Chip Select Deassert - nss\r
 * \r
 * Delay in master reference clocks for the length that the master mode chip select\r
 * outputs are de-asserted between transactions. The minimum delay is always\r
 * qspi_sck_out period to ensure the chip select is never re-asserted within an\r
 * qspi_sck_out period.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field. */\r
#define ALT_QSPI_DELAY_NSS_LSB        24\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field. */\r
#define ALT_QSPI_DELAY_NSS_MSB        31\r
/* The width in bits of the ALT_QSPI_DELAY_NSS register field. */\r
#define ALT_QSPI_DELAY_NSS_WIDTH      8\r
/* The mask used to set the ALT_QSPI_DELAY_NSS register field value. */\r
#define ALT_QSPI_DELAY_NSS_SET_MSK    0xff000000\r
/* The mask used to clear the ALT_QSPI_DELAY_NSS register field value. */\r
#define ALT_QSPI_DELAY_NSS_CLR_MSK    0x00ffffff\r
/* The reset value of the ALT_QSPI_DELAY_NSS register field. */\r
#define ALT_QSPI_DELAY_NSS_RESET      0x0\r
/* Extracts the ALT_QSPI_DELAY_NSS field value from a register. */\r
#define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)\r
/* Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register. */\r
#define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_DELAY.\r
 */\r
struct ALT_QSPI_DELAY_s\r
{\r
    uint32_t  init  :  8;  /* Clock Delay with qspi_n_ss_out */\r
    uint32_t  after :  8;  /* Clock Delay for Last Transaction Bit */\r
    uint32_t  btwn  :  8;  /* Clock Delay for Chip Select Deactivation */\r
    uint32_t  nss   :  8;  /* Clock Delay for Chip Select Deassert */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_DELAY. */\r
typedef volatile struct ALT_QSPI_DELAY_s  ALT_QSPI_DELAY_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_DELAY register from the beginning of the component. */\r
#define ALT_QSPI_DELAY_OFST        0xc\r
\r
/*\r
 * Register : Read Data Capture Register - rddatacap\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description\r
 * :-------|:-------|:------|:------------\r
 *  [0]    | RW     | 0x1   | Bypass     \r
 *  [4:1]  | RW     | 0x0   | Read Delay \r
 *  [31:5] | ???    | 0x0   | *UNDEFINED*\r
 * \r
 */\r
/*\r
 * Field : Bypass - byp\r
 * \r
 * Controls bypass of the adapted loopback clock circuit\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                  \r
 * :----------------------------------|:------|:------------------------------\r
 *  ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS | 0x0   | No Bypass                    \r
 *  ALT_QSPI_RDDATACAP_BYP_E_BYPASS   | 0x1   | Bypass loopback clock circuit\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP\r
 * \r
 * No Bypass\r
 */\r
#define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_RDDATACAP_BYP\r
 * \r
 * Bypass loopback clock circuit\r
 */\r
#define ALT_QSPI_RDDATACAP_BYP_E_BYPASS     0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */\r
#define ALT_QSPI_RDDATACAP_BYP_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_BYP register field. */\r
#define ALT_QSPI_RDDATACAP_BYP_MSB        0\r
/* The width in bits of the ALT_QSPI_RDDATACAP_BYP register field. */\r
#define ALT_QSPI_RDDATACAP_BYP_WIDTH      1\r
/* The mask used to set the ALT_QSPI_RDDATACAP_BYP register field value. */\r
#define ALT_QSPI_RDDATACAP_BYP_SET_MSK    0x00000001\r
/* The mask used to clear the ALT_QSPI_RDDATACAP_BYP register field value. */\r
#define ALT_QSPI_RDDATACAP_BYP_CLR_MSK    0xfffffffe\r
/* The reset value of the ALT_QSPI_RDDATACAP_BYP register field. */\r
#define ALT_QSPI_RDDATACAP_BYP_RESET      0x1\r
/* Extracts the ALT_QSPI_RDDATACAP_BYP field value from a register. */\r
#define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)\r
/* Produces a ALT_QSPI_RDDATACAP_BYP register field value suitable for setting the register. */\r
#define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)\r
\r
/*\r
 * Field : Read Delay - delay\r
 * \r
 * Delay the read data capturing logic by the programmed number of qspi_clk cycles\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */\r
#define ALT_QSPI_RDDATACAP_DELAY_LSB        1\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_RDDATACAP_DELAY register field. */\r
#define ALT_QSPI_RDDATACAP_DELAY_MSB        4\r
/* The width in bits of the ALT_QSPI_RDDATACAP_DELAY register field. */\r
#define ALT_QSPI_RDDATACAP_DELAY_WIDTH      4\r
/* The mask used to set the ALT_QSPI_RDDATACAP_DELAY register field value. */\r
#define ALT_QSPI_RDDATACAP_DELAY_SET_MSK    0x0000001e\r
/* The mask used to clear the ALT_QSPI_RDDATACAP_DELAY register field value. */\r
#define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK    0xffffffe1\r
/* The reset value of the ALT_QSPI_RDDATACAP_DELAY register field. */\r
#define ALT_QSPI_RDDATACAP_DELAY_RESET      0x0\r
/* Extracts the ALT_QSPI_RDDATACAP_DELAY field value from a register. */\r
#define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)\r
/* Produces a ALT_QSPI_RDDATACAP_DELAY register field value suitable for setting the register. */\r
#define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_RDDATACAP.\r
 */\r
struct ALT_QSPI_RDDATACAP_s\r
{\r
    uint32_t  byp   :  1;  /* Bypass */\r
    uint32_t  delay :  4;  /* Read Delay */\r
    uint32_t        : 27;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_RDDATACAP. */\r
typedef volatile struct ALT_QSPI_RDDATACAP_s  ALT_QSPI_RDDATACAP_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_RDDATACAP register from the beginning of the component. */\r
#define ALT_QSPI_RDDATACAP_OFST        0x10\r
\r
/*\r
 * Register : Device Size Register - devsz\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset | Description                    \r
 * :--------|:-------|:------|:--------------------------------\r
 *  [3:0]   | RW     | 0x2   | Number of address Bytes        \r
 *  [15:4]  | RW     | 0x100 | Number of Bytes per Device Page\r
 *  [20:16] | RW     | 0x10  | Number of Bytes per Block      \r
 *  [31:21] | ???    | 0x0   | *UNDEFINED*                    \r
 * \r
 */\r
/*\r
 * Field : Number of address Bytes - numaddrbytes\r
 * \r
 * Number of address bytes. A value of 0 indicates 1 byte.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */\r
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */\r
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB        3\r
/* The width in bits of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */\r
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH      4\r
/* The mask used to set the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */\r
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK    0x0000000f\r
/* The mask used to clear the ALT_QSPI_DEVSZ_NUMADDRBYTES register field value. */\r
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK    0xfffffff0\r
/* The reset value of the ALT_QSPI_DEVSZ_NUMADDRBYTES register field. */\r
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET      0x2\r
/* Extracts the ALT_QSPI_DEVSZ_NUMADDRBYTES field value from a register. */\r
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)\r
/* Produces a ALT_QSPI_DEVSZ_NUMADDRBYTES register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)\r
\r
/*\r
 * Field : Number of Bytes per Device Page - bytesperdevicepage\r
 * \r
 * Number of bytes per device page. This is required by the controller for\r
 * performing FLASH writes up to and across page boundaries.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */\r
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB        4\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */\r
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB        15\r
/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */\r
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH      12\r
/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */\r
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK    0x0000fff0\r
/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value. */\r
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK    0xffff000f\r
/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field. */\r
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET      0x100\r
/* Extracts the ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE field value from a register. */\r
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)\r
/* Produces a ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)\r
\r
/*\r
 * Field : Number of Bytes per Block - bytespersubsector\r
 * \r
 * Number of bytes per Block. This is required by the controller for performing the\r
 * write protection logic. The number of bytes per block must be a power of 2\r
 * number.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */\r
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB        16\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */\r
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB        20\r
/* The width in bits of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */\r
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH      5\r
/* The mask used to set the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */\r
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK    0x001f0000\r
/* The mask used to clear the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value. */\r
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK    0xffe0ffff\r
/* The reset value of the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field. */\r
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET      0x10\r
/* Extracts the ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR field value from a register. */\r
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)\r
/* Produces a ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR register field value suitable for setting the register. */\r
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_DEVSZ.\r
 */\r
struct ALT_QSPI_DEVSZ_s\r
{\r
    uint32_t  numaddrbytes       :  4;  /* Number of address Bytes */\r
    uint32_t  bytesperdevicepage : 12;  /* Number of Bytes per Device Page */\r
    uint32_t  bytespersubsector  :  5;  /* Number of Bytes per Block */\r
    uint32_t                     : 11;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_DEVSZ. */\r
typedef volatile struct ALT_QSPI_DEVSZ_s  ALT_QSPI_DEVSZ_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_DEVSZ register from the beginning of the component. */\r
#define ALT_QSPI_DEVSZ_OFST        0x14\r
\r
/*\r
 * Register : SRAM Partition Register - srampart\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description                 \r
 * :-------|:-------|:------|:-----------------------------\r
 *  [6:0]  | RW     | 0x40  | Indirect Read Partition Size\r
 *  [31:7] | ???    | 0x0   | *UNDEFINED*                 \r
 * \r
 */\r
/*\r
 * Field : Indirect Read Partition Size - addr\r
 * \r
 * Defines the size of the indirect read partition in the SRAM, in units of SRAM\r
 * locations. By default, half of the SRAM is reserved for indirect read operations\r
 * and half for indirect write operations.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */\r
#define ALT_QSPI_SRAMPART_ADDR_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMPART_ADDR register field. */\r
#define ALT_QSPI_SRAMPART_ADDR_MSB        6\r
/* The width in bits of the ALT_QSPI_SRAMPART_ADDR register field. */\r
#define ALT_QSPI_SRAMPART_ADDR_WIDTH      7\r
/* The mask used to set the ALT_QSPI_SRAMPART_ADDR register field value. */\r
#define ALT_QSPI_SRAMPART_ADDR_SET_MSK    0x0000007f\r
/* The mask used to clear the ALT_QSPI_SRAMPART_ADDR register field value. */\r
#define ALT_QSPI_SRAMPART_ADDR_CLR_MSK    0xffffff80\r
/* The reset value of the ALT_QSPI_SRAMPART_ADDR register field. */\r
#define ALT_QSPI_SRAMPART_ADDR_RESET      0x40\r
/* Extracts the ALT_QSPI_SRAMPART_ADDR field value from a register. */\r
#define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0)\r
/* Produces a ALT_QSPI_SRAMPART_ADDR register field value suitable for setting the register. */\r
#define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_SRAMPART.\r
 */\r
struct ALT_QSPI_SRAMPART_s\r
{\r
    uint32_t  addr :  7;  /* Indirect Read Partition Size */\r
    uint32_t       : 25;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_SRAMPART. */\r
typedef volatile struct ALT_QSPI_SRAMPART_s  ALT_QSPI_SRAMPART_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_SRAMPART register from the beginning of the component. */\r
#define ALT_QSPI_SRAMPART_OFST        0x18\r
\r
/*\r
 * Register : Indirect AHB Address Trigger Register - indaddrtrig\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description    \r
 * :-------|:-------|:------|:----------------\r
 *  [31:0] | RW     | 0x0   | Trigger Address\r
 * \r
 */\r
/*\r
 * Field : Trigger Address - addr\r
 * \r
 * This is the base address that will be used by the AHB controller. When the\r
 * incoming AHB read access address matches a range of addresses from this trigger\r
 * address to the trigger address + 15, then the AHB request will be completed by\r
 * fetching data from the Indirect Controllers SRAM.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */\r
#define ALT_QSPI_INDADDRTRIG_ADDR_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDADDRTRIG_ADDR register field. */\r
#define ALT_QSPI_INDADDRTRIG_ADDR_MSB        31\r
/* The width in bits of the ALT_QSPI_INDADDRTRIG_ADDR register field. */\r
#define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH      32\r
/* The mask used to set the ALT_QSPI_INDADDRTRIG_ADDR register field value. */\r
#define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_INDADDRTRIG_ADDR register field value. */\r
#define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_INDADDRTRIG_ADDR register field. */\r
#define ALT_QSPI_INDADDRTRIG_ADDR_RESET      0x0\r
/* Extracts the ALT_QSPI_INDADDRTRIG_ADDR field value from a register. */\r
#define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_INDADDRTRIG_ADDR register field value suitable for setting the register. */\r
#define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_INDADDRTRIG.\r
 */\r
struct ALT_QSPI_INDADDRTRIG_s\r
{\r
    uint32_t  addr : 32;  /* Trigger Address */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_INDADDRTRIG. */\r
typedef volatile struct ALT_QSPI_INDADDRTRIG_s  ALT_QSPI_INDADDRTRIG_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_INDADDRTRIG register from the beginning of the component. */\r
#define ALT_QSPI_INDADDRTRIG_OFST        0x1c\r
\r
/*\r
 * Register : DMA Peripheral Register - dmaper\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset | Description           \r
 * :--------|:-------|:------|:-----------------------\r
 *  [3:0]   | RW     | 0x0   | Number of Single Bytes\r
 *  [7:4]   | ???    | 0x0   | *UNDEFINED*           \r
 *  [11:8]  | RW     | 0x0   | Number of Burst Bytes \r
 *  [31:12] | ???    | 0x0   | *UNDEFINED*           \r
 * \r
 */\r
/*\r
 * Field : Number of Single Bytes - numsglreqbytes\r
 * \r
 * Number of bytes in a single type request on the DMA peripheral request. A\r
 * programmed value of 0 represents a single byte. This should be setup before\r
 * starting the indirect read or write operation. The actual number of bytes used\r
 * is 2**(value in this register) which will simplify implementation.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */\r
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */\r
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB        3\r
/* The width in bits of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */\r
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH      4\r
/* The mask used to set the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */\r
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK    0x0000000f\r
/* The mask used to clear the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value. */\r
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK    0xfffffff0\r
/* The reset value of the ALT_QSPI_DMAPER_NUMSGLREQBYTES register field. */\r
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET      0x0\r
/* Extracts the ALT_QSPI_DMAPER_NUMSGLREQBYTES field value from a register. */\r
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)\r
/* Produces a ALT_QSPI_DMAPER_NUMSGLREQBYTES register field value suitable for setting the register. */\r
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)\r
\r
/*\r
 * Field : Number of Burst Bytes - numburstreqbytes\r
 * \r
 * Number of bytes in a burst type request on the DMA peripheral request. A\r
 * programmed value of 0 represents a single byte. This should be setup before\r
 * starting the indirect read or write operation. The actual number of bytes used\r
 * is 2**(value in this register) which will simplify implementation.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */\r
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB        8\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */\r
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB        11\r
/* The width in bits of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */\r
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH      4\r
/* The mask used to set the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */\r
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK    0x00000f00\r
/* The mask used to clear the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value. */\r
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK    0xfffff0ff\r
/* The reset value of the ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field. */\r
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET      0x0\r
/* Extracts the ALT_QSPI_DMAPER_NUMBURSTREQBYTES field value from a register. */\r
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)\r
/* Produces a ALT_QSPI_DMAPER_NUMBURSTREQBYTES register field value suitable for setting the register. */\r
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_DMAPER.\r
 */\r
struct ALT_QSPI_DMAPER_s\r
{\r
    uint32_t  numsglreqbytes   :  4;  /* Number of Single Bytes */\r
    uint32_t                   :  4;  /* *UNDEFINED* */\r
    uint32_t  numburstreqbytes :  4;  /* Number of Burst Bytes */\r
    uint32_t                   : 20;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_DMAPER. */\r
typedef volatile struct ALT_QSPI_DMAPER_s  ALT_QSPI_DMAPER_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_DMAPER register from the beginning of the component. */\r
#define ALT_QSPI_DMAPER_OFST        0x20\r
\r
/*\r
 * Register : Remap Address Register - remapaddr\r
 * \r
 * This register is used to remap an incoming AHB address to a different address\r
 * used by the FLASH device.\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description         \r
 * :-------|:-------|:------|:---------------------\r
 *  [31:0] | RW     | 0x0   | Remap Address Offset\r
 * \r
 */\r
/*\r
 * Field : Remap Address Offset - value\r
 * \r
 * This offset is added to the incoming AHB address to determine the address used\r
 * by the FLASH device.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */\r
#define ALT_QSPI_REMAPADDR_VALUE_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_REMAPADDR_VALUE register field. */\r
#define ALT_QSPI_REMAPADDR_VALUE_MSB        31\r
/* The width in bits of the ALT_QSPI_REMAPADDR_VALUE register field. */\r
#define ALT_QSPI_REMAPADDR_VALUE_WIDTH      32\r
/* The mask used to set the ALT_QSPI_REMAPADDR_VALUE register field value. */\r
#define ALT_QSPI_REMAPADDR_VALUE_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_REMAPADDR_VALUE register field value. */\r
#define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_REMAPADDR_VALUE register field. */\r
#define ALT_QSPI_REMAPADDR_VALUE_RESET      0x0\r
/* Extracts the ALT_QSPI_REMAPADDR_VALUE field value from a register. */\r
#define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_REMAPADDR_VALUE register field value suitable for setting the register. */\r
#define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_REMAPADDR.\r
 */\r
struct ALT_QSPI_REMAPADDR_s\r
{\r
    uint32_t  value : 32;  /* Remap Address Offset */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_REMAPADDR. */\r
typedef volatile struct ALT_QSPI_REMAPADDR_s  ALT_QSPI_REMAPADDR_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_REMAPADDR register from the beginning of the component. */\r
#define ALT_QSPI_REMAPADDR_OFST        0x24\r
\r
/*\r
 * Register : Mode Bit Register - modebit\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description\r
 * :-------|:-------|:------|:------------\r
 *  [7:0]  | RW     | 0x0   | Mode       \r
 *  [31:8] | ???    | 0x0   | *UNDEFINED*\r
 * \r
 */\r
/*\r
 * Field : Mode - mode\r
 * \r
 * These are the 8 mode bits that are sent to the device following the address\r
 * bytes if mode bit transmission has been enabled.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODBIT_MOD register field. */\r
#define ALT_QSPI_MODBIT_MOD_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODBIT_MOD register field. */\r
#define ALT_QSPI_MODBIT_MOD_MSB        7\r
/* The width in bits of the ALT_QSPI_MODBIT_MOD register field. */\r
#define ALT_QSPI_MODBIT_MOD_WIDTH      8\r
/* The mask used to set the ALT_QSPI_MODBIT_MOD register field value. */\r
#define ALT_QSPI_MODBIT_MOD_SET_MSK    0x000000ff\r
/* The mask used to clear the ALT_QSPI_MODBIT_MOD register field value. */\r
#define ALT_QSPI_MODBIT_MOD_CLR_MSK    0xffffff00\r
/* The reset value of the ALT_QSPI_MODBIT_MOD register field. */\r
#define ALT_QSPI_MODBIT_MOD_RESET      0x0\r
/* Extracts the ALT_QSPI_MODBIT_MOD field value from a register. */\r
#define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0)\r
/* Produces a ALT_QSPI_MODBIT_MOD register field value suitable for setting the register. */\r
#define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_MODBIT.\r
 */\r
struct ALT_QSPI_MODBIT_s\r
{\r
    uint32_t  mode :  8;  /* Mode */\r
    uint32_t       : 24;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_MODBIT. */\r
typedef volatile struct ALT_QSPI_MODBIT_s  ALT_QSPI_MODBIT_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_MODBIT register from the beginning of the component. */\r
#define ALT_QSPI_MODBIT_OFST        0x28\r
\r
/*\r
 * Register : SRAM Fill Register - sramfill\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset | Description                                                       \r
 * :--------|:-------|:------|:-------------------------------------------------------------------\r
 *  [15:0]  | R      | 0x0   | SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS \r
 *  [31:16] | R      | 0x0   | SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS\r
 * \r
 */\r
/*\r
 * Field : SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS - indrdpart\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */\r
#define ALT_QSPI_SRAMFILL_INDRDPART_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDRDPART register field. */\r
#define ALT_QSPI_SRAMFILL_INDRDPART_MSB        15\r
/* The width in bits of the ALT_QSPI_SRAMFILL_INDRDPART register field. */\r
#define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH      16\r
/* The mask used to set the ALT_QSPI_SRAMFILL_INDRDPART register field value. */\r
#define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK    0x0000ffff\r
/* The mask used to clear the ALT_QSPI_SRAMFILL_INDRDPART register field value. */\r
#define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK    0xffff0000\r
/* The reset value of the ALT_QSPI_SRAMFILL_INDRDPART register field. */\r
#define ALT_QSPI_SRAMFILL_INDRDPART_RESET      0x0\r
/* Extracts the ALT_QSPI_SRAMFILL_INDRDPART field value from a register. */\r
#define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)\r
/* Produces a ALT_QSPI_SRAMFILL_INDRDPART register field value suitable for setting the register. */\r
#define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)\r
\r
/*\r
 * Field : SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS - indwrpart\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */\r
#define ALT_QSPI_SRAMFILL_INDWRPART_LSB        16\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_SRAMFILL_INDWRPART register field. */\r
#define ALT_QSPI_SRAMFILL_INDWRPART_MSB        31\r
/* The width in bits of the ALT_QSPI_SRAMFILL_INDWRPART register field. */\r
#define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH      16\r
/* The mask used to set the ALT_QSPI_SRAMFILL_INDWRPART register field value. */\r
#define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK    0xffff0000\r
/* The mask used to clear the ALT_QSPI_SRAMFILL_INDWRPART register field value. */\r
#define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK    0x0000ffff\r
/* The reset value of the ALT_QSPI_SRAMFILL_INDWRPART register field. */\r
#define ALT_QSPI_SRAMFILL_INDWRPART_RESET      0x0\r
/* Extracts the ALT_QSPI_SRAMFILL_INDWRPART field value from a register. */\r
#define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)\r
/* Produces a ALT_QSPI_SRAMFILL_INDWRPART register field value suitable for setting the register. */\r
#define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_SRAMFILL.\r
 */\r
struct ALT_QSPI_SRAMFILL_s\r
{\r
    const uint32_t  indrdpart : 16;  /* SRAM Fill Level (Indirect Read Partition). In units of SRAM WORDS */\r
    const uint32_t  indwrpart : 16;  /* SRAM Fill Level (Indirect Write Partition). In units of SRAM WORDS */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_SRAMFILL. */\r
typedef volatile struct ALT_QSPI_SRAMFILL_s  ALT_QSPI_SRAMFILL_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_SRAMFILL register from the beginning of the component. */\r
#define ALT_QSPI_SRAMFILL_OFST        0x2c\r
\r
/*\r
 * Register : TX Threshold Register - txthresh\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description\r
 * :-------|:-------|:------|:------------\r
 *  [3:0]  | RW     | 0x1   | Level      \r
 *  [31:4] | ???    | 0x0   | *UNDEFINED*\r
 * \r
 */\r
/*\r
 * Field : Level - level\r
 * \r
 * Defines the level at which the transmit FIFO not full interrupt is generated\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */\r
#define ALT_QSPI_TXTHRESH_LEVEL_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_TXTHRESH_LEVEL register field. */\r
#define ALT_QSPI_TXTHRESH_LEVEL_MSB        3\r
/* The width in bits of the ALT_QSPI_TXTHRESH_LEVEL register field. */\r
#define ALT_QSPI_TXTHRESH_LEVEL_WIDTH      4\r
/* The mask used to set the ALT_QSPI_TXTHRESH_LEVEL register field value. */\r
#define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK    0x0000000f\r
/* The mask used to clear the ALT_QSPI_TXTHRESH_LEVEL register field value. */\r
#define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK    0xfffffff0\r
/* The reset value of the ALT_QSPI_TXTHRESH_LEVEL register field. */\r
#define ALT_QSPI_TXTHRESH_LEVEL_RESET      0x1\r
/* Extracts the ALT_QSPI_TXTHRESH_LEVEL field value from a register. */\r
#define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)\r
/* Produces a ALT_QSPI_TXTHRESH_LEVEL register field value suitable for setting the register. */\r
#define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_TXTHRESH.\r
 */\r
struct ALT_QSPI_TXTHRESH_s\r
{\r
    uint32_t  level :  4;  /* Level */\r
    uint32_t        : 28;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_TXTHRESH. */\r
typedef volatile struct ALT_QSPI_TXTHRESH_s  ALT_QSPI_TXTHRESH_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_TXTHRESH register from the beginning of the component. */\r
#define ALT_QSPI_TXTHRESH_OFST        0x30\r
\r
/*\r
 * Register : RX Threshold Register - rxthresh\r
 * \r
 * Device Instruction Register\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description\r
 * :-------|:-------|:------|:------------\r
 *  [3:0]  | RW     | 0x1   | Level      \r
 *  [31:4] | ???    | 0x0   | *UNDEFINED*\r
 * \r
 */\r
/*\r
 * Field : Level - level\r
 * \r
 * Defines the level at which the receive FIFO not empty interrupt is generated\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */\r
#define ALT_QSPI_RXTHRESH_LEVEL_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_RXTHRESH_LEVEL register field. */\r
#define ALT_QSPI_RXTHRESH_LEVEL_MSB        3\r
/* The width in bits of the ALT_QSPI_RXTHRESH_LEVEL register field. */\r
#define ALT_QSPI_RXTHRESH_LEVEL_WIDTH      4\r
/* The mask used to set the ALT_QSPI_RXTHRESH_LEVEL register field value. */\r
#define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK    0x0000000f\r
/* The mask used to clear the ALT_QSPI_RXTHRESH_LEVEL register field value. */\r
#define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK    0xfffffff0\r
/* The reset value of the ALT_QSPI_RXTHRESH_LEVEL register field. */\r
#define ALT_QSPI_RXTHRESH_LEVEL_RESET      0x1\r
/* Extracts the ALT_QSPI_RXTHRESH_LEVEL field value from a register. */\r
#define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)\r
/* Produces a ALT_QSPI_RXTHRESH_LEVEL register field value suitable for setting the register. */\r
#define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_RXTHRESH.\r
 */\r
struct ALT_QSPI_RXTHRESH_s\r
{\r
    uint32_t  level :  4;  /* Level */\r
    uint32_t        : 28;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_RXTHRESH. */\r
typedef volatile struct ALT_QSPI_RXTHRESH_s  ALT_QSPI_RXTHRESH_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_RXTHRESH register from the beginning of the component. */\r
#define ALT_QSPI_RXTHRESH_OFST        0x34\r
\r
/*\r
 * Register : Interrupt Status Register - irqstat\r
 * \r
 * The status fields in this register are set when the described event occurs and\r
 * the interrupt is enabled in the mask register. When any of these bit fields are\r
 * set, the interrupt output is asserted high. The fields are each cleared by\r
 * writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when\r
 * legacy SPI mode is active.\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset | Description                        \r
 * :--------|:-------|:------|:------------------------------------\r
 *  [0]     | ???    | 0x0   | *UNDEFINED*                        \r
 *  [1]     | RW     | 0x0   | Underflow Detected                 \r
 *  [2]     | RW     | 0x0   | Indirect Operation Complete        \r
 *  [3]     | RW     | 0x0   | Indirect Read Reject               \r
 *  [4]     | RW     | 0x0   | Protected Area Write Attempt       \r
 *  [5]     | RW     | 0x0   | Illegal AHB Access Detected        \r
 *  [6]     | RW     | 0x0   | Transfer Watermark Reached         \r
 *  [7]     | RW     | 0x0   | Receive Overflow                   \r
 *  [8]     | RW     | 0x1   | Transmit FIFO Compared to Threshold\r
 *  [9]     | RW     | 0x0   | Transmit FIFO Full                 \r
 *  [10]    | RW     | 0x0   | Receive FIFO Compared to Threshold \r
 *  [11]    | RW     | 0x0   | Receive FIFO Full                  \r
 *  [12]    | RW     | 0x0   | Indirect Read Partition overflow   \r
 *  [31:13] | ???    | 0x0   | *UNDEFINED*                        \r
 * \r
 */\r
/*\r
 * Field : Underflow Detected - underflowdet\r
 * \r
 * An underflow is detected when an attempt to transfer data is made when the\r
 * transmit FIFO is empty. This may occur when the AHB write data is being supplied\r
 * too slowly to keep up with the requested write operation. This bit is reset only\r
 * by a system reset and cleared only when the register is read.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                        | Value | Description \r
 * :--------------------------------------------|:------|:-------------\r
 *  ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW   | 0x1   | Underflow   \r
 *  ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW | 0x0   | No Underflow\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET\r
 * \r
 * Underflow\r
 */\r
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW   0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET\r
 * \r
 * No Underflow\r
 */\r
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */\r
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB        1\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */\r
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB        1\r
/* The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */\r
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */\r
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK    0x00000002\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value. */\r
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK    0xfffffffd\r
/* The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field. */\r
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register. */\r
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)\r
/* Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)\r
\r
/*\r
 * Field : Indirect Operation Complete - indopdone\r
 * \r
 * Controller has completed last triggered indirect operation\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                      | Value | Description                 \r
 * :------------------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP   | 0x1   | Completed Indirect Operation\r
 *  ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP | 0x0   | No Indirect Operation       \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE\r
 * \r
 * Completed Indirect Operation\r
 */\r
#define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE\r
 * \r
 * No Indirect Operation\r
 */\r
#define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP   0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */\r
#define ALT_QSPI_IRQSTAT_INDOPDONE_LSB        2\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */\r
#define ALT_QSPI_IRQSTAT_INDOPDONE_MSB        2\r
/* The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */\r
#define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */\r
#define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK    0x00000004\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value. */\r
#define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK    0xfffffffb\r
/* The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field. */\r
#define ALT_QSPI_IRQSTAT_INDOPDONE_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register. */\r
#define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)\r
/* Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)\r
\r
/*\r
 * Field : Indirect Read Reject - indrdreject\r
 * \r
 * Indirect operation was requested but could not be accepted. Two indirect\r
 * operations already in storage.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                         | Value | Description                 \r
 * :---------------------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ   | 0x1   | Indirect Operation Requested\r
 *  ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ | 0x0   | No Indirect Operation       \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT\r
 * \r
 * Indirect Operation Requested\r
 */\r
#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ      0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT\r
 * \r
 * No Indirect Operation\r
 */\r
#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */\r
#define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB        3\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */\r
#define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB        3\r
/* The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */\r
#define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */\r
#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK    0x00000008\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value. */\r
#define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK    0xfffffff7\r
/* The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field. */\r
#define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register. */\r
#define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)\r
/* Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)\r
\r
/*\r
 * Field : Protected Area Write Attempt - protwrattempt\r
 * \r
 * Write to protected area was attempted and rejected.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                      | Value | Description                    \r
 * :------------------------------------------|:------|:--------------------------------\r
 *  ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT   | 0x1   | Write Attempt to protected area\r
 *  ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT | 0x0   | No Write Attempt               \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT\r
 * \r
 * Write Attempt to protected area\r
 */\r
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT\r
 * \r
 * No Write Attempt\r
 */\r
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT   0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */\r
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB        4\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */\r
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB        4\r
/* The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */\r
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */\r
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK    0x00000010\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value. */\r
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK    0xffffffef\r
/* The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field. */\r
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register. */\r
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)\r
/* Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)\r
\r
/*\r
 * Field : Illegal AHB Access Detected - illegalacc\r
 * \r
 * Illegal AHB access has been detected. AHB wrapping bursts and the use of\r
 * SPLIT/RETRY accesses will cause this error interrupt to trigger.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                       | Value | Description           \r
 * :-------------------------------------------|:------|:-----------------------\r
 *  ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB   | 0x1   | Illegal AHB attempt   \r
 *  ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB | 0x0   | No Illegal AHB attempt\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC\r
 * \r
 * Illegal AHB attempt\r
 */\r
#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB    0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC\r
 * \r
 * No Illegal AHB attempt\r
 */\r
#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB  0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */\r
#define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB        5\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */\r
#define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB        5\r
/* The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */\r
#define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */\r
#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK    0x00000020\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value. */\r
#define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK    0xffffffdf\r
/* The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field. */\r
#define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register. */\r
#define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)\r
/* Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)\r
\r
/*\r
 * Field : Transfer Watermark Reached - indxfrlvl\r
 * \r
 * Indirect Transfer Watermark Level Reached\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                    | Value | Description           \r
 * :----------------------------------------|:------|:-----------------------\r
 *  ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL  | 0x1   | Water level reached   \r
 *  ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL | 0x0   | No water level reached\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL\r
 * \r
 * Water level reached\r
 */\r
#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL  0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL\r
 * \r
 * No water level reached\r
 */\r
#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */\r
#define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB        6\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */\r
#define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB        6\r
/* The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */\r
#define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */\r
#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK    0x00000040\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value. */\r
#define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK    0xffffffbf\r
/* The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field. */\r
#define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register. */\r
#define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)\r
/* Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)\r
\r
/*\r
 * Field : Receive Overflow - rxover\r
 * \r
 * This should only occur in Legacy SPI mode. Set if an attempt is made to push the\r
 * RX FIFO when it is full. This bit is reset only by a system reset and cleared\r
 * only when this register is read. If a new push to the RX FIFO occurs coincident\r
 * with a register read this flag will remain set. 0 : no overflow has been\r
 * detected. 1 : an overflow has occurred.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                | Value | Description        \r
 * :------------------------------------|:------|:--------------------\r
 *  ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER   | 0x1   | Receive Overflow   \r
 *  ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER | 0x0   | No Receive Overflow\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER\r
 * \r
 * Receive Overflow\r
 */\r
#define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER   0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER\r
 * \r
 * No Receive Overflow\r
 */\r
#define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */\r
#define ALT_QSPI_IRQSTAT_RXOVER_LSB        7\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field. */\r
#define ALT_QSPI_IRQSTAT_RXOVER_MSB        7\r
/* The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field. */\r
#define ALT_QSPI_IRQSTAT_RXOVER_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value. */\r
#define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK    0x00000080\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value. */\r
#define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK    0xffffff7f\r
/* The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field. */\r
#define ALT_QSPI_IRQSTAT_RXOVER_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register. */\r
#define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)\r
/* Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)\r
\r
/*\r
 * Field : Transmit FIFO Compared to Threshold - txthreshcmp\r
 * \r
 * Indicates the number of entries in the transmit FIFO with respect to the\r
 * threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                 \r
 * :----------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT | 0x0   | FIFO has > TXTHRESH entries \r
 *  ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE | 0x1   | FIFO has <= TXTHRESH entries\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP\r
 * \r
 * FIFO has > TXTHRESH entries\r
 */\r
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP\r
 * \r
 * FIFO has <= TXTHRESH entries\r
 */\r
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE   0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB        8\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB        8\r
/* The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */\r
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK    0x00000100\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value. */\r
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK    0xfffffeff\r
/* The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET      0x1\r
/* Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register. */\r
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)\r
/* Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)\r
\r
/*\r
 * Field : Transmit FIFO Full - txfull\r
 * \r
 * Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy\r
 * mode.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description           \r
 * :----------------------------------|:------|:-----------------------\r
 *  ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL | 0x0   | Transmit FIFO Not Full\r
 *  ALT_QSPI_IRQSTAT_TXFULL_E_FULL    | 0x1   | Transmit FIFO Full    \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL\r
 * \r
 * Transmit FIFO Not Full\r
 */\r
#define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL\r
 * \r
 * Transmit FIFO Full\r
 */\r
#define ALT_QSPI_IRQSTAT_TXFULL_E_FULL      0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */\r
#define ALT_QSPI_IRQSTAT_TXFULL_LSB        9\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field. */\r
#define ALT_QSPI_IRQSTAT_TXFULL_MSB        9\r
/* The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field. */\r
#define ALT_QSPI_IRQSTAT_TXFULL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value. */\r
#define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK    0x00000200\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value. */\r
#define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK    0xfffffdff\r
/* The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field. */\r
#define ALT_QSPI_IRQSTAT_TXFULL_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register. */\r
#define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)\r
/* Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)\r
\r
/*\r
 * Field : Receive FIFO Compared to Threshold - rxthreshcmp\r
 * \r
 * Indicates the number of entries in the receive FIFO with respect to the\r
 * threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                 \r
 * :----------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE | 0x0   | FIFO has <= RXTHRESH entries\r
 *  ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT | 0x1   | FIFO has > RXTHRESH entries \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP\r
 * \r
 * FIFO has <= RXTHRESH entries\r
 */\r
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP\r
 * \r
 * FIFO has > RXTHRESH entries\r
 */\r
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT   0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB        10\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB        10\r
/* The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */\r
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK    0x00000400\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value. */\r
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK    0xfffffbff\r
/* The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register. */\r
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)\r
/* Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)\r
\r
/*\r
 * Field : Receive FIFO Full - rxfull\r
 * \r
 * Indicates that the receive FIFO is full or not. Only relevant in SPI legacy\r
 * mode.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description          \r
 * :----------------------------------|:------|:----------------------\r
 *  ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL | 0x0   | Receive FIFO Not Full\r
 *  ALT_QSPI_IRQSTAT_RXFULL_E_FULL    | 0x1   | Receive FIFO Full    \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL\r
 * \r
 * Receive FIFO Not Full\r
 */\r
#define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL\r
 * \r
 * Receive FIFO Full\r
 */\r
#define ALT_QSPI_IRQSTAT_RXFULL_E_FULL      0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */\r
#define ALT_QSPI_IRQSTAT_RXFULL_LSB        11\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field. */\r
#define ALT_QSPI_IRQSTAT_RXFULL_MSB        11\r
/* The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field. */\r
#define ALT_QSPI_IRQSTAT_RXFULL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value. */\r
#define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK    0x00000800\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value. */\r
#define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK    0xfffff7ff\r
/* The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field. */\r
#define ALT_QSPI_IRQSTAT_RXFULL_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register. */\r
#define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)\r
/* Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)\r
\r
/*\r
 * Field : Indirect Read Partition overflow - indsramfull\r
 * \r
 * Indirect Read Partition of SRAM is full and unable to immediately complete\r
 * indirect operation\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                         | Value | Description     \r
 * :---------------------------------------------|:------|:-----------------\r
 *  ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL    | 0x1   | SRAM is full    \r
 *  ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL | 0x0   | SRAM is not full\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL\r
 * \r
 * SRAM is full\r
 */\r
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL       0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL\r
 * \r
 * SRAM is not full\r
 */\r
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */\r
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB        12\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */\r
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB        12\r
/* The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */\r
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */\r
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK    0x00001000\r
/* The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value. */\r
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK    0xffffefff\r
/* The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field. */\r
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register. */\r
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)\r
/* Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_IRQSTAT.\r
 */\r
struct ALT_QSPI_IRQSTAT_s\r
{\r
    uint32_t                :  1;  /* *UNDEFINED* */\r
    uint32_t  underflowdet  :  1;  /* Underflow Detected */\r
    uint32_t  indopdone     :  1;  /* Indirect Operation Complete */\r
    uint32_t  indrdreject   :  1;  /* Indirect Read Reject */\r
    uint32_t  protwrattempt :  1;  /* Protected Area Write Attempt */\r
    uint32_t  illegalacc    :  1;  /* Illegal AHB Access Detected */\r
    uint32_t  indxfrlvl     :  1;  /* Transfer Watermark Reached */\r
    uint32_t  rxover        :  1;  /* Receive Overflow */\r
    uint32_t  txthreshcmp   :  1;  /* Transmit FIFO Compared to Threshold */\r
    uint32_t  txfull        :  1;  /* Transmit FIFO Full */\r
    uint32_t  rxthreshcmp   :  1;  /* Receive FIFO Compared to Threshold */\r
    uint32_t  rxfull        :  1;  /* Receive FIFO Full */\r
    uint32_t  indsramfull   :  1;  /* Indirect Read Partition overflow */\r
    uint32_t                : 19;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_IRQSTAT. */\r
typedef volatile struct ALT_QSPI_IRQSTAT_s  ALT_QSPI_IRQSTAT_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component. */\r
#define ALT_QSPI_IRQSTAT_OFST        0x40\r
\r
/*\r
 * Register : Interrupt Mask - irqmask\r
 * \r
 * If disabled, the interrupt for the corresponding interrupt status register bit\r
 * is disabled. If enabled, the interrupt for the corresponding interrupt status\r
 * register bit is enabled.\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset | Description                          \r
 * :--------|:-------|:------|:--------------------------------------\r
 *  [0]     | ???    | 0x0   | *UNDEFINED*                          \r
 *  [1]     | RW     | 0x0   | Underflow Detected Mask              \r
 *  [2]     | RW     | 0x0   | Mask                                 \r
 *  [3]     | RW     | 0x0   | Indirect Read Reject Mask            \r
 *  [4]     | RW     | 0x0   | Protected Area Write Attempt Mask    \r
 *  [5]     | RW     | 0x0   | Illegal Access Detected Mask         \r
 *  [6]     | RW     | 0x0   | Transfer Watermark Breach Mask       \r
 *  [7]     | RW     | 0x0   | Receive Overflow Mask                \r
 *  [8]     | RW     | 0x0   | Transmit FIFO Threshold Compare Mask \r
 *  [9]     | RW     | 0x0   | Transmit FIFO Full Mask              \r
 *  [10]    | RW     | 0x0   | Receive FIFO Threshold Compare Mask  \r
 *  [11]    | RW     | 0x0   | Receive FIFO full Mask               \r
 *  [12]    | RW     | 0x0   | Indirect Read Partition overflow mask\r
 *  [31:13] | ???    | 0x0   | *UNDEFINED*                          \r
 * \r
 */\r
/*\r
 * Field : Underflow Detected Mask - underflowdet\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                | Value | Description                 \r
 * :------------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END  0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */\r
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB        1\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */\r
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB        1\r
/* The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */\r
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */\r
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK    0x00000002\r
/* The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value. */\r
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK    0xfffffffd\r
/* The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field. */\r
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register. */\r
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)\r
/* Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)\r
\r
/*\r
 * Field : Mask - indopdone\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                             | Value | Description                 \r
 * :---------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_INDOPDONE_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_INDOPDONE_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD    0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_INDOPDONE_E_END     0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */\r
#define ALT_QSPI_IRQMSK_INDOPDONE_LSB        2\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field. */\r
#define ALT_QSPI_IRQMSK_INDOPDONE_MSB        2\r
/* The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field. */\r
#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value. */\r
#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK    0x00000004\r
/* The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value. */\r
#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK    0xfffffffb\r
/* The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field. */\r
#define ALT_QSPI_IRQMSK_INDOPDONE_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register. */\r
#define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)\r
/* Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)\r
\r
/*\r
 * Field : Indirect Read Reject Mask - indrdreject\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                               | Value | Description                 \r
 * :-----------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_INDRDREJECT_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD  0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END   0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */\r
#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB        3\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */\r
#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB        3\r
/* The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */\r
#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */\r
#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK    0x00000008\r
/* The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value. */\r
#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK    0xfffffff7\r
/* The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field. */\r
#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register. */\r
#define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)\r
/* Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)\r
\r
/*\r
 * Field : Protected Area Write Attempt Mask - protwrattempt\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                 | Value | Description                 \r
 * :-------------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD    0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END     0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */\r
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB        4\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */\r
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB        4\r
/* The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */\r
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */\r
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK    0x00000010\r
/* The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value. */\r
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK    0xffffffef\r
/* The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field. */\r
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register. */\r
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)\r
/* Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)\r
\r
/*\r
 * Field : Illegal Access Detected Mask - illegalacc\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                 \r
 * :----------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_ILLEGALACC_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END    0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */\r
#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB        5\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */\r
#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB        5\r
/* The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */\r
#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */\r
#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK    0x00000020\r
/* The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value. */\r
#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK    0xffffffdf\r
/* The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field. */\r
#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register. */\r
#define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)\r
/* Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)\r
\r
/*\r
 * Field : Transfer Watermark Breach Mask - indxfrlvl\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                             | Value | Description                 \r
 * :---------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_INDXFRLVL_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD    0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END     0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */\r
#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB        6\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */\r
#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB        6\r
/* The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */\r
#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */\r
#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK    0x00000040\r
/* The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value. */\r
#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK    0xffffffbf\r
/* The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field. */\r
#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register. */\r
#define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)\r
/* Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)\r
\r
/*\r
 * Field : Receive Overflow Mask - rxover\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                          | Value | Description                 \r
 * :------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_RXOVER_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_RXOVER_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_RXOVER_E_DISD   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_RXOVER_E_END    0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */\r
#define ALT_QSPI_IRQMSK_RXOVER_LSB        7\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field. */\r
#define ALT_QSPI_IRQMSK_RXOVER_MSB        7\r
/* The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field. */\r
#define ALT_QSPI_IRQMSK_RXOVER_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value. */\r
#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK    0x00000080\r
/* The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value. */\r
#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK    0xffffff7f\r
/* The reset value of the ALT_QSPI_IRQMSK_RXOVER register field. */\r
#define ALT_QSPI_IRQMSK_RXOVER_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register. */\r
#define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)\r
/* Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080)\r
\r
/*\r
 * Field : Transmit FIFO Threshold Compare Mask - txthreshcmp\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                               | Value | Description                 \r
 * :-----------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD  0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END   0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB        8\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB        8\r
/* The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */\r
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK    0x00000100\r
/* The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value. */\r
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK    0xfffffeff\r
/* The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register. */\r
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)\r
/* Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)\r
\r
/*\r
 * Field : Transmit FIFO Full Mask - txfull\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                          | Value | Description                 \r
 * :------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_TXFULL_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_TXFULL_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_TXFULL_E_DISD   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_TXFULL_E_END    0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */\r
#define ALT_QSPI_IRQMSK_TXFULL_LSB        9\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field. */\r
#define ALT_QSPI_IRQMSK_TXFULL_MSB        9\r
/* The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field. */\r
#define ALT_QSPI_IRQMSK_TXFULL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value. */\r
#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK    0x00000200\r
/* The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value. */\r
#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK    0xfffffdff\r
/* The reset value of the ALT_QSPI_IRQMSK_TXFULL register field. */\r
#define ALT_QSPI_IRQMSK_TXFULL_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register. */\r
#define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)\r
/* Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200)\r
\r
/*\r
 * Field : Receive FIFO Threshold Compare Mask - rxthreshcmp\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                               | Value | Description                 \r
 * :-----------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD  0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END   0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB        10\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB        10\r
/* The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */\r
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK    0x00000400\r
/* The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value. */\r
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK    0xfffffbff\r
/* The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field. */\r
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register. */\r
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)\r
/* Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)\r
\r
/*\r
 * Field : Receive FIFO full Mask - rxfull\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                          | Value | Description                 \r
 * :------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_RXFULL_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_RXFULL_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_RXFULL_E_DISD   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_RXFULL_E_END    0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */\r
#define ALT_QSPI_IRQMSK_RXFULL_LSB        11\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field. */\r
#define ALT_QSPI_IRQMSK_RXFULL_MSB        11\r
/* The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field. */\r
#define ALT_QSPI_IRQMSK_RXFULL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value. */\r
#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK    0x00000800\r
/* The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value. */\r
#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK    0xfffff7ff\r
/* The reset value of the ALT_QSPI_IRQMSK_RXFULL register field. */\r
#define ALT_QSPI_IRQMSK_RXFULL_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register. */\r
#define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)\r
/* Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800)\r
\r
/*\r
 * Field : Indirect Read Partition overflow mask - indsramfull\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                               | Value | Description                 \r
 * :-----------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD | 0x0   | Disable Interrupt by Masking\r
 *  ALT_QSPI_IRQMSK_INDSRAMFULL_E_END  | 0x1   | Enable Interrupt            \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL\r
 * \r
 * Disable Interrupt by Masking\r
 */\r
#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD  0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL\r
 * \r
 * Enable Interrupt\r
 */\r
#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END   0x1\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */\r
#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB        12\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */\r
#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB        12\r
/* The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */\r
#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */\r
#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK    0x00001000\r
/* The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value. */\r
#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK    0xffffefff\r
/* The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field. */\r
#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET      0x0\r
/* Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register. */\r
#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)\r
/* Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register. */\r
#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_IRQMSK.\r
 */\r
struct ALT_QSPI_IRQMSK_s\r
{\r
    uint32_t                :  1;  /* *UNDEFINED* */\r
    uint32_t  underflowdet  :  1;  /* Underflow Detected Mask */\r
    uint32_t  indopdone     :  1;  /* Mask */\r
    uint32_t  indrdreject   :  1;  /* Indirect Read Reject Mask */\r
    uint32_t  protwrattempt :  1;  /* Protected Area Write Attempt Mask */\r
    uint32_t  illegalacc    :  1;  /* Illegal Access Detected Mask */\r
    uint32_t  indxfrlvl     :  1;  /* Transfer Watermark Breach Mask */\r
    uint32_t  rxover        :  1;  /* Receive Overflow Mask */\r
    uint32_t  txthreshcmp   :  1;  /* Transmit FIFO Threshold Compare Mask */\r
    uint32_t  txfull        :  1;  /* Transmit FIFO Full Mask */\r
    uint32_t  rxthreshcmp   :  1;  /* Receive FIFO Threshold Compare Mask */\r
    uint32_t  rxfull        :  1;  /* Receive FIFO full Mask */\r
    uint32_t  indsramfull   :  1;  /* Indirect Read Partition overflow mask */\r
    uint32_t                : 19;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_IRQMSK. */\r
typedef volatile struct ALT_QSPI_IRQMSK_s  ALT_QSPI_IRQMSK_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component. */\r
#define ALT_QSPI_IRQMSK_OFST        0x44\r
\r
/*\r
 * Register : Lower Write Protection Register - lowwrprot\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description \r
 * :-------|:-------|:------|:-------------\r
 *  [31:0] | RW     | 0x0   | Block Number\r
 * \r
 */\r
/*\r
 * Field : Block Number - subsector\r
 * \r
 * The block number that defines the lower block in the range of blocks that is to\r
 * be locked from writing. The definition of a block in terms of number of bytes is\r
 * programmable via the Device Size Configuration register.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */\r
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */\r
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB        31\r
/* The width in bits of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */\r
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH      32\r
/* The mask used to set the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */\r
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_LOWWRPROT_SUBSECTOR register field value. */\r
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_LOWWRPROT_SUBSECTOR register field. */\r
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET      0x0\r
/* Extracts the ALT_QSPI_LOWWRPROT_SUBSECTOR field value from a register. */\r
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_LOWWRPROT_SUBSECTOR register field value suitable for setting the register. */\r
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_LOWWRPROT.\r
 */\r
struct ALT_QSPI_LOWWRPROT_s\r
{\r
    uint32_t  subsector : 32;  /* Block Number */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_LOWWRPROT. */\r
typedef volatile struct ALT_QSPI_LOWWRPROT_s  ALT_QSPI_LOWWRPROT_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_LOWWRPROT register from the beginning of the component. */\r
#define ALT_QSPI_LOWWRPROT_OFST        0x50\r
\r
/*\r
 * Register : Upper Write Protection Register - uppwrprot\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description \r
 * :-------|:-------|:------|:-------------\r
 *  [31:0] | RW     | 0x0   | Block Number\r
 * \r
 */\r
/*\r
 * Field : Block Number - subsector\r
 * \r
 * The block number that defines the upper block in the range of blocks that is to\r
 * be locked from writing. The definition of a block in terms of number of bytes is\r
 * programmable via the Device Size Configuration register.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */\r
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */\r
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB        31\r
/* The width in bits of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */\r
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH      32\r
/* The mask used to set the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */\r
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_UPPWRPROT_SUBSECTOR register field value. */\r
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_UPPWRPROT_SUBSECTOR register field. */\r
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET      0x0\r
/* Extracts the ALT_QSPI_UPPWRPROT_SUBSECTOR field value from a register. */\r
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_UPPWRPROT_SUBSECTOR register field value suitable for setting the register. */\r
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_UPPWRPROT.\r
 */\r
struct ALT_QSPI_UPPWRPROT_s\r
{\r
    uint32_t  subsector : 32;  /* Block Number */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_UPPWRPROT. */\r
typedef volatile struct ALT_QSPI_UPPWRPROT_s  ALT_QSPI_UPPWRPROT_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_UPPWRPROT register from the beginning of the component. */\r
#define ALT_QSPI_UPPWRPROT_OFST        0x54\r
\r
/*\r
 * Register : Write Protection Register - wrprot\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description                   \r
 * :-------|:-------|:------|:-------------------------------\r
 *  [0]    | RW     | 0x0   | Write Protection Inversion Bit\r
 *  [1]    | RW     | 0x0   | Write Protection Enable Bit   \r
 *  [31:2] | ???    | 0x0   | *UNDEFINED*                   \r
 * \r
 */\r
/*\r
 * Field : Write Protection Inversion Bit - inv\r
 * \r
 * When enabled, the protection region defined in the lower and upper write\r
 * protection registers is inverted meaning it is the region that the system is\r
 * permitted to write to. When disabled, the protection region defined in the lower\r
 * and upper write protection registers is the region that the system is not\r
 * permitted to write to.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                      | Value | Description             \r
 * :--------------------------|:------|:-------------------------\r
 *  ALT_QSPI_WRPROT_INV_E_EN  | 0x1   | Write Region allowed    \r
 *  ALT_QSPI_WRPROT_INV_E_DIS | 0x0   | Write Region not allowed\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_WRPROT_INV\r
 * \r
 * Write Region allowed\r
 */\r
#define ALT_QSPI_WRPROT_INV_E_EN    0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_WRPROT_INV\r
 * \r
 * Write Region not allowed\r
 */\r
#define ALT_QSPI_WRPROT_INV_E_DIS   0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_INV register field. */\r
#define ALT_QSPI_WRPROT_INV_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_INV register field. */\r
#define ALT_QSPI_WRPROT_INV_MSB        0\r
/* The width in bits of the ALT_QSPI_WRPROT_INV register field. */\r
#define ALT_QSPI_WRPROT_INV_WIDTH      1\r
/* The mask used to set the ALT_QSPI_WRPROT_INV register field value. */\r
#define ALT_QSPI_WRPROT_INV_SET_MSK    0x00000001\r
/* The mask used to clear the ALT_QSPI_WRPROT_INV register field value. */\r
#define ALT_QSPI_WRPROT_INV_CLR_MSK    0xfffffffe\r
/* The reset value of the ALT_QSPI_WRPROT_INV register field. */\r
#define ALT_QSPI_WRPROT_INV_RESET      0x0\r
/* Extracts the ALT_QSPI_WRPROT_INV field value from a register. */\r
#define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)\r
/* Produces a ALT_QSPI_WRPROT_INV register field value suitable for setting the register. */\r
#define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)\r
\r
/*\r
 * Field : Write Protection Enable Bit - en\r
 * \r
 * When enabled, any AHB write access with an address within the protection region\r
 * defined in the lower and upper write protection registers is rejected. An AHB\r
 * error response is generated and an interrupt source triggered. When disabled,\r
 * the protection region is disabled.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                     | Value | Description               \r
 * :-------------------------|:------|:---------------------------\r
 *  ALT_QSPI_WRPROT_EN_E_EN  | 0x1   | AHB Write Access rejected \r
 *  ALT_QSPI_WRPROT_EN_E_DIS | 0x0   | Protection Region Disabled\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_WRPROT_EN\r
 * \r
 * AHB Write Access rejected\r
 */\r
#define ALT_QSPI_WRPROT_EN_E_EN     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_WRPROT_EN\r
 * \r
 * Protection Region Disabled\r
 */\r
#define ALT_QSPI_WRPROT_EN_E_DIS    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_WRPROT_EN register field. */\r
#define ALT_QSPI_WRPROT_EN_LSB        1\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_WRPROT_EN register field. */\r
#define ALT_QSPI_WRPROT_EN_MSB        1\r
/* The width in bits of the ALT_QSPI_WRPROT_EN register field. */\r
#define ALT_QSPI_WRPROT_EN_WIDTH      1\r
/* The mask used to set the ALT_QSPI_WRPROT_EN register field value. */\r
#define ALT_QSPI_WRPROT_EN_SET_MSK    0x00000002\r
/* The mask used to clear the ALT_QSPI_WRPROT_EN register field value. */\r
#define ALT_QSPI_WRPROT_EN_CLR_MSK    0xfffffffd\r
/* The reset value of the ALT_QSPI_WRPROT_EN register field. */\r
#define ALT_QSPI_WRPROT_EN_RESET      0x0\r
/* Extracts the ALT_QSPI_WRPROT_EN field value from a register. */\r
#define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)\r
/* Produces a ALT_QSPI_WRPROT_EN register field value suitable for setting the register. */\r
#define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_WRPROT.\r
 */\r
struct ALT_QSPI_WRPROT_s\r
{\r
    uint32_t  inv :  1;  /* Write Protection Inversion Bit */\r
    uint32_t  en  :  1;  /* Write Protection Enable Bit */\r
    uint32_t      : 30;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_WRPROT. */\r
typedef volatile struct ALT_QSPI_WRPROT_s  ALT_QSPI_WRPROT_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_WRPROT register from the beginning of the component. */\r
#define ALT_QSPI_WRPROT_OFST        0x58\r
\r
/*\r
 * Register : Indirect Read Transfer Register - indrd\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset   | Description                    \r
 * :-------|:-------|:--------|:--------------------------------\r
 *  [0]    | RW     | 0x0     | Start Indirect Read            \r
 *  [1]    | RW     | 0x0     | Cancel Indirect Read           \r
 *  [2]    | R      | Unknown | Indirect Read Status           \r
 *  [3]    | RW     | Unknown | SRAM Full                      \r
 *  [4]    | R      | Unknown | Queued Indirect Read Operations\r
 *  [5]    | RW     | Unknown | Indirect Completion Status     \r
 *  [7:6]  | R      | Unknown | Completed Indirect Operations  \r
 *  [31:8] | ???    | 0x0     | *UNDEFINED*                    \r
 * \r
 */\r
/*\r
 * Field : Start Indirect Read - start\r
 * \r
 * When this bit is enabled, it will trigger an indirect read operation. The\r
 * assumption is that the indirect start address and the indirect number of bytes\r
 * register is setup before triggering the indirect read operation.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                        | Value | Description          \r
 * :----------------------------|:------|:----------------------\r
 *  ALT_QSPI_INDRD_START_E_END  | 0x1   | Trigger Indirect Read\r
 *  ALT_QSPI_INDRD_START_E_DISD | 0x0   | No Indirect Read     \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_START\r
 * \r
 * Trigger Indirect Read\r
 */\r
#define ALT_QSPI_INDRD_START_E_END  0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_START\r
 * \r
 * No Indirect Read\r
 */\r
#define ALT_QSPI_INDRD_START_E_DISD 0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field. */\r
#define ALT_QSPI_INDRD_START_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field. */\r
#define ALT_QSPI_INDRD_START_MSB        0\r
/* The width in bits of the ALT_QSPI_INDRD_START register field. */\r
#define ALT_QSPI_INDRD_START_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDRD_START register field value. */\r
#define ALT_QSPI_INDRD_START_SET_MSK    0x00000001\r
/* The mask used to clear the ALT_QSPI_INDRD_START register field value. */\r
#define ALT_QSPI_INDRD_START_CLR_MSK    0xfffffffe\r
/* The reset value of the ALT_QSPI_INDRD_START register field. */\r
#define ALT_QSPI_INDRD_START_RESET      0x0\r
/* Extracts the ALT_QSPI_INDRD_START field value from a register. */\r
#define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)\r
/* Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register. */\r
#define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)\r
\r
/*\r
 * Field : Cancel Indirect Read - cancel\r
 * \r
 * This bit will cancel all ongoing indirect read operations.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                             | Value | Description                \r
 * :---------------------------------|:------|:----------------------------\r
 *  ALT_QSPI_INDRD_CANCEL_E_CANCEL   | 0x1   | Cancel Indirect Read       \r
 *  ALT_QSPI_INDRD_CANCEL_E_NOACTION | 0x0   | Do Not Cancel Indirect Read\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_CANCEL\r
 * \r
 * Cancel Indirect Read\r
 */\r
#define ALT_QSPI_INDRD_CANCEL_E_CANCEL      0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_CANCEL\r
 * \r
 * Do Not Cancel Indirect Read\r
 */\r
#define ALT_QSPI_INDRD_CANCEL_E_NOACTION    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field. */\r
#define ALT_QSPI_INDRD_CANCEL_LSB        1\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field. */\r
#define ALT_QSPI_INDRD_CANCEL_MSB        1\r
/* The width in bits of the ALT_QSPI_INDRD_CANCEL register field. */\r
#define ALT_QSPI_INDRD_CANCEL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDRD_CANCEL register field value. */\r
#define ALT_QSPI_INDRD_CANCEL_SET_MSK    0x00000002\r
/* The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value. */\r
#define ALT_QSPI_INDRD_CANCEL_CLR_MSK    0xfffffffd\r
/* The reset value of the ALT_QSPI_INDRD_CANCEL register field. */\r
#define ALT_QSPI_INDRD_CANCEL_RESET      0x0\r
/* Extracts the ALT_QSPI_INDRD_CANCEL field value from a register. */\r
#define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)\r
/* Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register. */\r
#define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)\r
\r
/*\r
 * Field : Indirect Read Status - rd_status\r
 * \r
 * Indirect read operation in progress (status)\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                  \r
 * :----------------------------------|:------|:------------------------------\r
 *  ALT_QSPI_INDRD_RD_STAT_E_RDOP     | 0x1   | Read Operation in progress   \r
 *  ALT_QSPI_INDRD_RD_STAT_E_NOACTION | 0x0   | No read operation in progress\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT\r
 * \r
 * Read Operation in progress\r
 */\r
#define ALT_QSPI_INDRD_RD_STAT_E_RDOP       0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_RD_STAT\r
 * \r
 * No read operation in progress\r
 */\r
#define ALT_QSPI_INDRD_RD_STAT_E_NOACTION   0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */\r
#define ALT_QSPI_INDRD_RD_STAT_LSB        2\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field. */\r
#define ALT_QSPI_INDRD_RD_STAT_MSB        2\r
/* The width in bits of the ALT_QSPI_INDRD_RD_STAT register field. */\r
#define ALT_QSPI_INDRD_RD_STAT_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value. */\r
#define ALT_QSPI_INDRD_RD_STAT_SET_MSK    0x00000004\r
/* The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value. */\r
#define ALT_QSPI_INDRD_RD_STAT_CLR_MSK    0xfffffffb\r
/* The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN. */\r
#define ALT_QSPI_INDRD_RD_STAT_RESET      0x0\r
/* Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register. */\r
#define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2)\r
/* Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register. */\r
#define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004)\r
\r
/*\r
 * Field : SRAM Full - sram_full\r
 * \r
 * SRAM full and unable to immediately complete an indirect operation. Write a 1 to\r
 * this field to clear it. ; indirect operation (status)\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                | Value | Description                       \r
 * :------------------------------------|:------|:-----------------------------------\r
 *  ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL | 0x1   | Sram Full- Cant complete operation\r
 *  ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION | 0x0   | SRram Not Full                    \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL\r
 * \r
 * Sram Full- Cant complete operation\r
 */\r
#define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL\r
 * \r
 * SRram Not Full\r
 */\r
#define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */\r
#define ALT_QSPI_INDRD_SRAM_FULL_LSB        3\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field. */\r
#define ALT_QSPI_INDRD_SRAM_FULL_MSB        3\r
/* The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field. */\r
#define ALT_QSPI_INDRD_SRAM_FULL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value. */\r
#define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK    0x00000008\r
/* The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value. */\r
#define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK    0xfffffff7\r
/* The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN. */\r
#define ALT_QSPI_INDRD_SRAM_FULL_RESET      0x0\r
/* Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register. */\r
#define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)\r
/* Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register. */\r
#define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)\r
\r
/*\r
 * Field : Queued Indirect Read Operations - rd_queued\r
 * \r
 * Two indirect read operations have been queued\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                    | Value | Description         \r
 * :----------------------------------------|:------|:---------------------\r
 *  ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD | 0x1   | Queued Indirect Read\r
 *  ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION     | 0x0   | No Queued Read      \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED\r
 * \r
 * Queued Indirect Read\r
 */\r
#define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED\r
 * \r
 * No Queued Read\r
 */\r
#define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION     0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */\r
#define ALT_QSPI_INDRD_RD_QUEUED_LSB        4\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field. */\r
#define ALT_QSPI_INDRD_RD_QUEUED_MSB        4\r
/* The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field. */\r
#define ALT_QSPI_INDRD_RD_QUEUED_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value. */\r
#define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK    0x00000010\r
/* The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value. */\r
#define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK    0xffffffef\r
/* The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN. */\r
#define ALT_QSPI_INDRD_RD_QUEUED_RESET      0x0\r
/* Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register. */\r
#define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)\r
/* Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register. */\r
#define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)\r
\r
/*\r
 * Field : Indirect Completion Status - ind_ops_done_status\r
 * \r
 * This field is set to 1 when an indirect operation has completed. Write a 1 to\r
 * this field to clear it.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                        | Value | Description                   \r
 * :--------------------------------------------|:------|:-------------------------------\r
 *  ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP  | 0x1   | Indirect Op Complete operation\r
 *  ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION | 0x0   | Indirect Op Not Complete      \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT\r
 * \r
 * Indirect Op Complete operation\r
 */\r
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP  0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT\r
 * \r
 * Indirect Op Not Complete\r
 */\r
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */\r
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB        5\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */\r
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB        5\r
/* The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field. */\r
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */\r
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK    0x00000020\r
/* The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value. */\r
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK    0xffffffdf\r
/* The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN. */\r
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET      0x0\r
/* Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register. */\r
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5)\r
/* Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register. */\r
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020)\r
\r
/*\r
 * Field : Completed Indirect Operations - num_ind_ops_done\r
 * \r
 * This field contains the number of indirect operations which have been completed.\r
 * This is used in conjunction with the indirect completion status field (bit 5).\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */\r
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB        6\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */\r
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB        7\r
/* The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field. */\r
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH      2\r
/* The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */\r
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK    0x000000c0\r
/* The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value. */\r
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK    0xffffff3f\r
/* The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN. */\r
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET      0x0\r
/* Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register. */\r
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)\r
/* Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register. */\r
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_INDRD.\r
 */\r
struct ALT_QSPI_INDRD_s\r
{\r
    uint32_t        start               :  1;  /* Start Indirect Read */\r
    uint32_t        cancel              :  1;  /* Cancel Indirect Read */\r
    const uint32_t  rd_status           :  1;  /* Indirect Read Status */\r
    uint32_t        sram_full           :  1;  /* SRAM Full */\r
    const uint32_t  rd_queued           :  1;  /* Queued Indirect Read Operations */\r
    uint32_t        ind_ops_done_status :  1;  /* Indirect Completion Status */\r
    const uint32_t  num_ind_ops_done    :  2;  /* Completed Indirect Operations */\r
    uint32_t                            : 24;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_INDRD. */\r
typedef volatile struct ALT_QSPI_INDRD_s  ALT_QSPI_INDRD_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_INDRD register from the beginning of the component. */\r
#define ALT_QSPI_INDRD_OFST        0x60\r
\r
/*\r
 * Register : Indirect Read Transfer Watermark Register - indrdwater\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description    \r
 * :-------|:-------|:------|:----------------\r
 *  [31:0] | RW     | 0x0   | Watermark Value\r
 * \r
 */\r
/*\r
 * Field : Watermark Value - level\r
 * \r
 * This represents the minimum fill level of the SRAM before a DMA peripheral\r
 * access is permitted. When the SRAM fill level passes the watermark, an interrupt\r
 * is also generated. This field can be disabled by writing a value of all zeroes.\r
 * The units of this register are BYTES\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */\r
#define ALT_QSPI_INDRDWATER_LEVEL_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDWATER_LEVEL register field. */\r
#define ALT_QSPI_INDRDWATER_LEVEL_MSB        31\r
/* The width in bits of the ALT_QSPI_INDRDWATER_LEVEL register field. */\r
#define ALT_QSPI_INDRDWATER_LEVEL_WIDTH      32\r
/* The mask used to set the ALT_QSPI_INDRDWATER_LEVEL register field value. */\r
#define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_INDRDWATER_LEVEL register field value. */\r
#define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_INDRDWATER_LEVEL register field. */\r
#define ALT_QSPI_INDRDWATER_LEVEL_RESET      0x0\r
/* Extracts the ALT_QSPI_INDRDWATER_LEVEL field value from a register. */\r
#define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_INDRDWATER_LEVEL register field value suitable for setting the register. */\r
#define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_INDRDWATER.\r
 */\r
struct ALT_QSPI_INDRDWATER_s\r
{\r
    uint32_t  level : 32;  /* Watermark Value */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_INDRDWATER. */\r
typedef volatile struct ALT_QSPI_INDRDWATER_s  ALT_QSPI_INDRDWATER_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_INDRDWATER register from the beginning of the component. */\r
#define ALT_QSPI_INDRDWATER_OFST        0x64\r
\r
/*\r
 * Register : Indirect Read Transfer Start Address Register - indrdstaddr\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description                     \r
 * :-------|:-------|:------|:---------------------------------\r
 *  [31:0] | RW     | 0x0   | Start Address of Indirect Access\r
 * \r
 */\r
/*\r
 * Field : Start Address of Indirect Access - addr\r
 * \r
 * This is the start address from which the indirect access will commence its READ\r
 * operation.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */\r
#define ALT_QSPI_INDRDSTADDR_ADDR_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDSTADDR_ADDR register field. */\r
#define ALT_QSPI_INDRDSTADDR_ADDR_MSB        31\r
/* The width in bits of the ALT_QSPI_INDRDSTADDR_ADDR register field. */\r
#define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH      32\r
/* The mask used to set the ALT_QSPI_INDRDSTADDR_ADDR register field value. */\r
#define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_INDRDSTADDR_ADDR register field value. */\r
#define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_INDRDSTADDR_ADDR register field. */\r
#define ALT_QSPI_INDRDSTADDR_ADDR_RESET      0x0\r
/* Extracts the ALT_QSPI_INDRDSTADDR_ADDR field value from a register. */\r
#define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_INDRDSTADDR_ADDR register field value suitable for setting the register. */\r
#define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_INDRDSTADDR.\r
 */\r
struct ALT_QSPI_INDRDSTADDR_s\r
{\r
    uint32_t  addr : 32;  /* Start Address of Indirect Access */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_INDRDSTADDR. */\r
typedef volatile struct ALT_QSPI_INDRDSTADDR_s  ALT_QSPI_INDRDSTADDR_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_INDRDSTADDR register from the beginning of the component. */\r
#define ALT_QSPI_INDRDSTADDR_OFST        0x68\r
\r
/*\r
 * Register : Indirect Read Transfer Number Bytes Register - indrdcnt\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description   \r
 * :-------|:-------|:------|:---------------\r
 *  [31:0] | RW     | 0x0   | Indirect Count\r
 * \r
 */\r
/*\r
 * Field : Indirect Count - value\r
 * \r
 * This is the number of bytes that the indirect access will consume. This can be\r
 * bigger than the configured size of SRAM.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */\r
#define ALT_QSPI_INDRDCNT_VALUE_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDRDCNT_VALUE register field. */\r
#define ALT_QSPI_INDRDCNT_VALUE_MSB        31\r
/* The width in bits of the ALT_QSPI_INDRDCNT_VALUE register field. */\r
#define ALT_QSPI_INDRDCNT_VALUE_WIDTH      32\r
/* The mask used to set the ALT_QSPI_INDRDCNT_VALUE register field value. */\r
#define ALT_QSPI_INDRDCNT_VALUE_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_INDRDCNT_VALUE register field value. */\r
#define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_INDRDCNT_VALUE register field. */\r
#define ALT_QSPI_INDRDCNT_VALUE_RESET      0x0\r
/* Extracts the ALT_QSPI_INDRDCNT_VALUE field value from a register. */\r
#define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_INDRDCNT_VALUE register field value suitable for setting the register. */\r
#define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_INDRDCNT.\r
 */\r
struct ALT_QSPI_INDRDCNT_s\r
{\r
    uint32_t  value : 32;  /* Indirect Count */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_INDRDCNT. */\r
typedef volatile struct ALT_QSPI_INDRDCNT_s  ALT_QSPI_INDRDCNT_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_INDRDCNT register from the beginning of the component. */\r
#define ALT_QSPI_INDRDCNT_OFST        0x6c\r
\r
/*\r
 * Register : Indirect Write Transfer Register - indwr\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset   | Description                     \r
 * :-------|:-------|:--------|:---------------------------------\r
 *  [0]    | RW     | 0x0     | Start Indirect Write            \r
 *  [1]    | RW     | 0x0     | Cancel Indirect Write           \r
 *  [2]    | R      | Unknown | Indirect Write Status           \r
 *  [3]    | R      | 0x0     | Reserved                        \r
 *  [4]    | R      | Unknown | Queued Indirect Write Operations\r
 *  [5]    | RW     | Unknown | Indirect Completion Status      \r
 *  [7:6]  | R      | Unknown | Completed Indirect Operations   \r
 *  [31:8] | ???    | 0x0     | *UNDEFINED*                     \r
 * \r
 */\r
/*\r
 * Field : Start Indirect Write - start\r
 * \r
 * Writing a 1 to this bit will trigger an indirect write operation. The assumption\r
 * is that the indirect start address and the indirect number of bytes register is\r
 * setup before triggering the indirect write operation.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                        | Value | Description                     \r
 * :----------------------------|:------|:---------------------------------\r
 *  ALT_QSPI_INDWR_START_E_END  | 0x1   | Trigger indirect write operation\r
 *  ALT_QSPI_INDWR_START_E_DISD | 0x0   | No Action                       \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDWR_START\r
 * \r
 * Trigger indirect write operation\r
 */\r
#define ALT_QSPI_INDWR_START_E_END  0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDWR_START\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_INDWR_START_E_DISD 0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field. */\r
#define ALT_QSPI_INDWR_START_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field. */\r
#define ALT_QSPI_INDWR_START_MSB        0\r
/* The width in bits of the ALT_QSPI_INDWR_START register field. */\r
#define ALT_QSPI_INDWR_START_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDWR_START register field value. */\r
#define ALT_QSPI_INDWR_START_SET_MSK    0x00000001\r
/* The mask used to clear the ALT_QSPI_INDWR_START register field value. */\r
#define ALT_QSPI_INDWR_START_CLR_MSK    0xfffffffe\r
/* The reset value of the ALT_QSPI_INDWR_START register field. */\r
#define ALT_QSPI_INDWR_START_RESET      0x0\r
/* Extracts the ALT_QSPI_INDWR_START field value from a register. */\r
#define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)\r
/* Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register. */\r
#define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)\r
\r
/*\r
 * Field : Cancel Indirect Write - cancel\r
 * \r
 * Writing a 1 to this bit will cancel all ongoing indirect write operations.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                               | Value | Description                    \r
 * :-----------------------------------|:------|:--------------------------------\r
 *  ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR | 0x1   | Cancel Indirect write operation\r
 *  ALT_QSPI_INDWR_CANCEL_E_NOACTION   | 0x0   | No Action                      \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDWR_CANCEL\r
 * \r
 * Cancel Indirect write operation\r
 */\r
#define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR  0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDWR_CANCEL\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_INDWR_CANCEL_E_NOACTION    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field. */\r
#define ALT_QSPI_INDWR_CANCEL_LSB        1\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field. */\r
#define ALT_QSPI_INDWR_CANCEL_MSB        1\r
/* The width in bits of the ALT_QSPI_INDWR_CANCEL register field. */\r
#define ALT_QSPI_INDWR_CANCEL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDWR_CANCEL register field value. */\r
#define ALT_QSPI_INDWR_CANCEL_SET_MSK    0x00000002\r
/* The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value. */\r
#define ALT_QSPI_INDWR_CANCEL_CLR_MSK    0xfffffffd\r
/* The reset value of the ALT_QSPI_INDWR_CANCEL register field. */\r
#define ALT_QSPI_INDWR_CANCEL_RESET      0x0\r
/* Extracts the ALT_QSPI_INDWR_CANCEL field value from a register. */\r
#define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)\r
/* Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register. */\r
#define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)\r
\r
/*\r
 * Field : Indirect Write Status - rdstat\r
 * \r
 * Indirect write operation in progress (status)\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description             \r
 * :----------------------------------|:------|:-------------------------\r
 *  ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT | 0x1   | Indirect write operation\r
 *  ALT_QSPI_INDWR_RDSTAT_E_NOACTION  | 0x0   | No Action               \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT\r
 * \r
 * Indirect write operation\r
 */\r
#define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT   0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDWR_RDSTAT\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_INDWR_RDSTAT_E_NOACTION    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */\r
#define ALT_QSPI_INDWR_RDSTAT_LSB        2\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field. */\r
#define ALT_QSPI_INDWR_RDSTAT_MSB        2\r
/* The width in bits of the ALT_QSPI_INDWR_RDSTAT register field. */\r
#define ALT_QSPI_INDWR_RDSTAT_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value. */\r
#define ALT_QSPI_INDWR_RDSTAT_SET_MSK    0x00000004\r
/* The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value. */\r
#define ALT_QSPI_INDWR_RDSTAT_CLR_MSK    0xfffffffb\r
/* The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN. */\r
#define ALT_QSPI_INDWR_RDSTAT_RESET      0x0\r
/* Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register. */\r
#define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)\r
/* Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register. */\r
#define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)\r
\r
/*\r
 * Field : Reserved - sramfull\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */\r
#define ALT_QSPI_INDWR_SRAMFULL_LSB        3\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field. */\r
#define ALT_QSPI_INDWR_SRAMFULL_MSB        3\r
/* The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field. */\r
#define ALT_QSPI_INDWR_SRAMFULL_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value. */\r
#define ALT_QSPI_INDWR_SRAMFULL_SET_MSK    0x00000008\r
/* The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value. */\r
#define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK    0xfffffff7\r
/* The reset value of the ALT_QSPI_INDWR_SRAMFULL register field. */\r
#define ALT_QSPI_INDWR_SRAMFULL_RESET      0x0\r
/* Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register. */\r
#define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3)\r
/* Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register. */\r
#define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008)\r
\r
/*\r
 * Field : Queued Indirect Write Operations - rdqueued\r
 * \r
 * Two indirect write operations have been queued\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                               | Value | Description                 \r
 * :-----------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_INDWR_RDQUEUED_E_INDWROP  | 0x1   | Two Indirect write operation\r
 *  ALT_QSPI_INDWR_RDQUEUED_E_NOACTION | 0x0   | No Action                   \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED\r
 * \r
 * Two Indirect write operation\r
 */\r
#define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP   0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION  0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */\r
#define ALT_QSPI_INDWR_RDQUEUED_LSB        4\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field. */\r
#define ALT_QSPI_INDWR_RDQUEUED_MSB        4\r
/* The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field. */\r
#define ALT_QSPI_INDWR_RDQUEUED_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value. */\r
#define ALT_QSPI_INDWR_RDQUEUED_SET_MSK    0x00000010\r
/* The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value. */\r
#define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK    0xffffffef\r
/* The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN. */\r
#define ALT_QSPI_INDWR_RDQUEUED_RESET      0x0\r
/* Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register. */\r
#define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)\r
/* Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register. */\r
#define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)\r
\r
/*\r
 * Field : Indirect Completion Status - inddone\r
 * \r
 * This field is set to 1 when an indirect operation has completed. Write a 1 to\r
 * this field to clear it.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                               | Value | Description                 \r
 * :-----------------------------------|:------|:-----------------------------\r
 *  ALT_QSPI_INDWR_INDDONE_E_INDCOMPST | 0x1   | Indirect operation completed\r
 *  ALT_QSPI_INDWR_INDDONE_E_NOACTION  | 0x0   | No Action                   \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDWR_INDDONE\r
 * \r
 * Indirect operation completed\r
 */\r
#define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST  0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_INDWR_INDDONE\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_INDWR_INDDONE_E_NOACTION   0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field. */\r
#define ALT_QSPI_INDWR_INDDONE_LSB        5\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field. */\r
#define ALT_QSPI_INDWR_INDDONE_MSB        5\r
/* The width in bits of the ALT_QSPI_INDWR_INDDONE register field. */\r
#define ALT_QSPI_INDWR_INDDONE_WIDTH      1\r
/* The mask used to set the ALT_QSPI_INDWR_INDDONE register field value. */\r
#define ALT_QSPI_INDWR_INDDONE_SET_MSK    0x00000020\r
/* The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value. */\r
#define ALT_QSPI_INDWR_INDDONE_CLR_MSK    0xffffffdf\r
/* The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN. */\r
#define ALT_QSPI_INDWR_INDDONE_RESET      0x0\r
/* Extracts the ALT_QSPI_INDWR_INDDONE field value from a register. */\r
#define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)\r
/* Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register. */\r
#define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)\r
\r
/*\r
 * Field : Completed Indirect Operations - indcnt\r
 * \r
 * This field contains the count of indirect operations which have been completed.\r
 * This is used in conjunction with the indirect completion status field (bit 5).\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field. */\r
#define ALT_QSPI_INDWR_INDCNT_LSB        6\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field. */\r
#define ALT_QSPI_INDWR_INDCNT_MSB        7\r
/* The width in bits of the ALT_QSPI_INDWR_INDCNT register field. */\r
#define ALT_QSPI_INDWR_INDCNT_WIDTH      2\r
/* The mask used to set the ALT_QSPI_INDWR_INDCNT register field value. */\r
#define ALT_QSPI_INDWR_INDCNT_SET_MSK    0x000000c0\r
/* The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value. */\r
#define ALT_QSPI_INDWR_INDCNT_CLR_MSK    0xffffff3f\r
/* The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN. */\r
#define ALT_QSPI_INDWR_INDCNT_RESET      0x0\r
/* Extracts the ALT_QSPI_INDWR_INDCNT field value from a register. */\r
#define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)\r
/* Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register. */\r
#define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_INDWR.\r
 */\r
struct ALT_QSPI_INDWR_s\r
{\r
    uint32_t        start    :  1;  /* Start Indirect Write */\r
    uint32_t        cancel   :  1;  /* Cancel Indirect Write */\r
    const uint32_t  rdstat   :  1;  /* Indirect Write Status */\r
    const uint32_t  sramfull :  1;  /* Reserved */\r
    const uint32_t  rdqueued :  1;  /* Queued Indirect Write Operations */\r
    uint32_t        inddone  :  1;  /* Indirect Completion Status */\r
    const uint32_t  indcnt   :  2;  /* Completed Indirect Operations */\r
    uint32_t                 : 24;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_INDWR. */\r
typedef volatile struct ALT_QSPI_INDWR_s  ALT_QSPI_INDWR_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_INDWR register from the beginning of the component. */\r
#define ALT_QSPI_INDWR_OFST        0x70\r
\r
/*\r
 * Register : Indirect Write Transfer Watermark Register - indwrwater\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset      | Description    \r
 * :-------|:-------|:-----------|:----------------\r
 *  [31:0] | RW     | 0xffffffff | Watermark Value\r
 * \r
 */\r
/*\r
 * Field : Watermark Value - level\r
 * \r
 * This represents the maximum fill level of the SRAM before a DMA peripheral\r
 * access is permitted. When the SRAM fill level falls below the watermark, an\r
 * interrupt is also generated. This field can be disabled by writing a value of\r
 * all ones. The units of this register are bytes.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */\r
#define ALT_QSPI_INDWRWATER_LEVEL_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRWATER_LEVEL register field. */\r
#define ALT_QSPI_INDWRWATER_LEVEL_MSB        31\r
/* The width in bits of the ALT_QSPI_INDWRWATER_LEVEL register field. */\r
#define ALT_QSPI_INDWRWATER_LEVEL_WIDTH      32\r
/* The mask used to set the ALT_QSPI_INDWRWATER_LEVEL register field value. */\r
#define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_INDWRWATER_LEVEL register field value. */\r
#define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_INDWRWATER_LEVEL register field. */\r
#define ALT_QSPI_INDWRWATER_LEVEL_RESET      0xffffffff\r
/* Extracts the ALT_QSPI_INDWRWATER_LEVEL field value from a register. */\r
#define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_INDWRWATER_LEVEL register field value suitable for setting the register. */\r
#define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_INDWRWATER.\r
 */\r
struct ALT_QSPI_INDWRWATER_s\r
{\r
    uint32_t  level : 32;  /* Watermark Value */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_INDWRWATER. */\r
typedef volatile struct ALT_QSPI_INDWRWATER_s  ALT_QSPI_INDWRWATER_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_INDWRWATER register from the beginning of the component. */\r
#define ALT_QSPI_INDWRWATER_OFST        0x74\r
\r
/*\r
 * Register : Indirect Write Transfer Start Address Register - indwrstaddr\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description             \r
 * :-------|:-------|:------|:-------------------------\r
 *  [31:0] | RW     | 0x0   | Start of Indirect Access\r
 * \r
 */\r
/*\r
 * Field : Start of Indirect Access - addr\r
 * \r
 * This is the start address from which the indirect access will commence its write\r
 * operation.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */\r
#define ALT_QSPI_INDWRSTADDR_ADDR_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRSTADDR_ADDR register field. */\r
#define ALT_QSPI_INDWRSTADDR_ADDR_MSB        31\r
/* The width in bits of the ALT_QSPI_INDWRSTADDR_ADDR register field. */\r
#define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH      32\r
/* The mask used to set the ALT_QSPI_INDWRSTADDR_ADDR register field value. */\r
#define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_INDWRSTADDR_ADDR register field value. */\r
#define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_INDWRSTADDR_ADDR register field. */\r
#define ALT_QSPI_INDWRSTADDR_ADDR_RESET      0x0\r
/* Extracts the ALT_QSPI_INDWRSTADDR_ADDR field value from a register. */\r
#define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_INDWRSTADDR_ADDR register field value suitable for setting the register. */\r
#define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_INDWRSTADDR.\r
 */\r
struct ALT_QSPI_INDWRSTADDR_s\r
{\r
    uint32_t  addr : 32;  /* Start of Indirect Access */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_INDWRSTADDR. */\r
typedef volatile struct ALT_QSPI_INDWRSTADDR_s  ALT_QSPI_INDWRSTADDR_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_INDWRSTADDR register from the beginning of the component. */\r
#define ALT_QSPI_INDWRSTADDR_OFST        0x78\r
\r
/*\r
 * Register : Indirect Write Transfer Count Register - indwrcnt\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description             \r
 * :-------|:-------|:------|:-------------------------\r
 *  [31:0] | RW     | 0x0   | Indirect Number of Bytes\r
 * \r
 */\r
/*\r
 * Field : Indirect Number of Bytes - value\r
 * \r
 * This is the number of bytes that the indirect access will consume. This can be\r
 * bigger than the configured size of SRAM.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */\r
#define ALT_QSPI_INDWRCNT_VALUE_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_INDWRCNT_VALUE register field. */\r
#define ALT_QSPI_INDWRCNT_VALUE_MSB        31\r
/* The width in bits of the ALT_QSPI_INDWRCNT_VALUE register field. */\r
#define ALT_QSPI_INDWRCNT_VALUE_WIDTH      32\r
/* The mask used to set the ALT_QSPI_INDWRCNT_VALUE register field value. */\r
#define ALT_QSPI_INDWRCNT_VALUE_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_INDWRCNT_VALUE register field value. */\r
#define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_INDWRCNT_VALUE register field. */\r
#define ALT_QSPI_INDWRCNT_VALUE_RESET      0x0\r
/* Extracts the ALT_QSPI_INDWRCNT_VALUE field value from a register. */\r
#define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_INDWRCNT_VALUE register field value suitable for setting the register. */\r
#define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_INDWRCNT.\r
 */\r
struct ALT_QSPI_INDWRCNT_s\r
{\r
    uint32_t  value : 32;  /* Indirect Number of Bytes */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_INDWRCNT. */\r
typedef volatile struct ALT_QSPI_INDWRCNT_s  ALT_QSPI_INDWRCNT_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_INDWRCNT register from the beginning of the component. */\r
#define ALT_QSPI_INDWRCNT_OFST        0x7c\r
\r
/*\r
 * Register : Flash Command Register - flashcmd\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset | Description               \r
 * :--------|:-------|:------|:---------------------------\r
 *  [0]     | RW     | 0x0   | Execute Command           \r
 *  [1]     | R      | 0x0   | Command Execution Status  \r
 *  [6:2]   | ???    | 0x0   | *UNDEFINED*               \r
 *  [11:7]  | RW     | 0x0   | Number of Dummy Bytes     \r
 *  [14:12] | RW     | 0x0   | Number of Write Data Bytes\r
 *  [15]    | RW     | 0x0   | Write Data Enable         \r
 *  [17:16] | RW     | 0x0   | Number of Address Bytes   \r
 *  [18]    | RW     | 0x0   | Mode Bit Enable           \r
 *  [19]    | RW     | 0x0   | Command Address Enable    \r
 *  [22:20] | RW     | 0x0   | Number of Read Data Bytes \r
 *  [23]    | RW     | 0x0   | Read Data Enable          \r
 *  [31:24] | RW     | 0x0   | Command Opcode            \r
 * \r
 */\r
/*\r
 * Field : Execute Command - execcmd\r
 * \r
 * Execute the command.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                | Value | Description    \r
 * :------------------------------------|:------|:----------------\r
 *  ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE  | 0x1   | Execute Command\r
 *  ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION | 0x0   | No Action      \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD\r
 * \r
 * Execute Command\r
 */\r
#define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE  0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_EXECCMD\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */\r
#define ALT_QSPI_FLSHCMD_EXECCMD_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_EXECCMD register field. */\r
#define ALT_QSPI_FLSHCMD_EXECCMD_MSB        0\r
/* The width in bits of the ALT_QSPI_FLSHCMD_EXECCMD register field. */\r
#define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH      1\r
/* The mask used to set the ALT_QSPI_FLSHCMD_EXECCMD register field value. */\r
#define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK    0x00000001\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_EXECCMD register field value. */\r
#define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK    0xfffffffe\r
/* The reset value of the ALT_QSPI_FLSHCMD_EXECCMD register field. */\r
#define ALT_QSPI_FLSHCMD_EXECCMD_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_EXECCMD field value from a register. */\r
#define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)\r
/* Produces a ALT_QSPI_FLSHCMD_EXECCMD register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)\r
\r
/*\r
 * Field : Command Execution Status - cmdexecstat\r
 * \r
 * Command execution in progress.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                       | Value | Description             \r
 * :-------------------------------------------|:------|:-------------------------\r
 *  ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT | 0x1   | Command Execution Status\r
 *  ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION    | 0x0   | No Action               \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT\r
 * \r
 * Command Execution Status\r
 */\r
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT  0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_CMDEXECSTAT\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION     0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */\r
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB        1\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */\r
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB        1\r
/* The width in bits of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */\r
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH      1\r
/* The mask used to set the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */\r
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK    0x00000002\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value. */\r
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK    0xfffffffd\r
/* The reset value of the ALT_QSPI_FLSHCMD_CMDEXECSTAT register field. */\r
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_CMDEXECSTAT field value from a register. */\r
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)\r
/* Produces a ALT_QSPI_FLSHCMD_CMDEXECSTAT register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)\r
\r
/*\r
 * Field : Number of Dummy Bytes - numdummybytes\r
 * \r
 * Set to the number of dummy bytes required This should be setup before triggering\r
 * the command via the execute field of this register.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB        7\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB        11\r
/* The width in bits of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH      5\r
/* The mask used to set the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */\r
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK    0x00000f80\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value. */\r
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK    0xfffff07f\r
/* The reset value of the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_NUMDUMMYBYTES field value from a register. */\r
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)\r
/* Produces a ALT_QSPI_FLSHCMD_NUMDUMMYBYTES register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)\r
\r
/*\r
 * Field : Number of Write Data Bytes - numwrdatabytes\r
 * \r
 * Up to 8 Data bytes may be written using this command.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                      | Value | Description \r
 * :------------------------------------------|:------|:-------------\r
 *  ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 | 0x0   | Write 1 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 | 0x1   | Write 2 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 | 0x2   | Write 3 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 | 0x3   | Write 4 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 | 0x4   | Write 5 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 | 0x5   | Write 6 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 | 0x6   | Write 7 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 | 0x7   | Write 8 Byte\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES\r
 * \r
 * Write 1 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES\r
 * \r
 * Write 2 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2   0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES\r
 * \r
 * Write 3 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3   0x2\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES\r
 * \r
 * Write 4 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4   0x3\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES\r
 * \r
 * Write 5 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5   0x4\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES\r
 * \r
 * Write 6 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6   0x5\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES\r
 * \r
 * Write 7 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7   0x6\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMWRDATABYTES\r
 * \r
 * Write 8 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8   0x7\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB        12\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB        14\r
/* The width in bits of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH      3\r
/* The mask used to set the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK    0x00007000\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value. */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK    0xffff8fff\r
/* The reset value of the ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_NUMWRDATABYTES field value from a register. */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)\r
/* Produces a ALT_QSPI_FLSHCMD_NUMWRDATABYTES register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)\r
\r
/*\r
 * Field : Write Data Enable - enwrdata\r
 * \r
 * Set to 1 if the command specified in the command opcode field requires write\r
 * data bytes to be sent to the device.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                    | Value | Description                      \r
 * :----------------------------------------|:------|:----------------------------------\r
 *  ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES | 0x1   | Command requires write data bytes\r
 *  ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION    | 0x0   | No Action                        \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA\r
 * \r
 * Command requires write data bytes\r
 */\r
#define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENWRDATA\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */\r
#define ALT_QSPI_FLSHCMD_ENWRDATA_LSB        15\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */\r
#define ALT_QSPI_FLSHCMD_ENWRDATA_MSB        15\r
/* The width in bits of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */\r
#define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH      1\r
/* The mask used to set the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */\r
#define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK    0x00008000\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_ENWRDATA register field value. */\r
#define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK    0xffff7fff\r
/* The reset value of the ALT_QSPI_FLSHCMD_ENWRDATA register field. */\r
#define ALT_QSPI_FLSHCMD_ENWRDATA_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_ENWRDATA field value from a register. */\r
#define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)\r
/* Produces a ALT_QSPI_FLSHCMD_ENWRDATA register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)\r
\r
/*\r
 * Field : Number of Address Bytes - numaddrbytes\r
 * \r
 * Set to the number of address bytes required (the address itself is programmed in\r
 * the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the\r
 * command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address\r
 * bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                      | Value | Description          \r
 * :------------------------------------------|:------|:----------------------\r
 *  ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 | 0x0   | Write 1 Address Byte \r
 *  ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 | 0x1   | Write 2 Address Bytes\r
 *  ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 | 0x2   | Write 3 Address Bytes\r
 *  ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 | 0x3   | Write 4 Address Bytes\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES\r
 * \r
 * Write 1 Address Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES\r
 * \r
 * Write 2 Address Bytes\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2   0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES\r
 * \r
 * Write 3 Address Bytes\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3   0x2\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMADDRBYTES\r
 * \r
 * Write 4 Address Bytes\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4   0x3\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB        16\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB        17\r
/* The width in bits of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH      2\r
/* The mask used to set the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK    0x00030000\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value. */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK    0xfffcffff\r
/* The reset value of the ALT_QSPI_FLSHCMD_NUMADDRBYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_NUMADDRBYTES field value from a register. */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)\r
/* Produces a ALT_QSPI_FLSHCMD_NUMADDRBYTES register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)\r
\r
/*\r
 * Field : Mode Bit Enable - enmodebit\r
 * \r
 * Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration\r
 * register are sent following the address bytes.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                             | Value | Description                   \r
 * :---------------------------------|:------|:-------------------------------\r
 *  ALT_QSPI_FLSHCMD_ENMODBIT_E_END  | 0x1   | Mode Bit follows address bytes\r
 *  ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD | 0x0   | No Action                     \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT\r
 * \r
 * Mode Bit follows address bytes\r
 */\r
#define ALT_QSPI_FLSHCMD_ENMODBIT_E_END     0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENMODBIT\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */\r
#define ALT_QSPI_FLSHCMD_ENMODBIT_LSB        18\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */\r
#define ALT_QSPI_FLSHCMD_ENMODBIT_MSB        18\r
/* The width in bits of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */\r
#define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH      1\r
/* The mask used to set the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */\r
#define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK    0x00040000\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_ENMODBIT register field value. */\r
#define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK    0xfffbffff\r
/* The reset value of the ALT_QSPI_FLSHCMD_ENMODBIT register field. */\r
#define ALT_QSPI_FLSHCMD_ENMODBIT_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_ENMODBIT field value from a register. */\r
#define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18)\r
/* Produces a ALT_QSPI_FLSHCMD_ENMODBIT register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000)\r
\r
/*\r
 * Field : Command Address Enable - encmdaddr\r
 * \r
 * If enabled, the command specified in bits 31:24 requires an address. This should\r
 * be setup before triggering the command via writing a 1 to the execute field.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                              | Value | Description                           \r
 * :----------------------------------|:------|:---------------------------------------\r
 *  ALT_QSPI_FLSHCMD_ENCMDADDR_E_END  | 0x1   | Command in bits 31:24 requires address\r
 *  ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD | 0x0   | No Action                             \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR\r
 * \r
 * Command in bits 31:24 requires address\r
 */\r
#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END    0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENCMDADDR\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD   0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */\r
#define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB        19\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */\r
#define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB        19\r
/* The width in bits of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */\r
#define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH      1\r
/* The mask used to set the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */\r
#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK    0x00080000\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_ENCMDADDR register field value. */\r
#define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK    0xfff7ffff\r
/* The reset value of the ALT_QSPI_FLSHCMD_ENCMDADDR register field. */\r
#define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_ENCMDADDR field value from a register. */\r
#define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)\r
/* Produces a ALT_QSPI_FLSHCMD_ENCMDADDR register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)\r
\r
/*\r
 * Field : Number of Read Data Bytes - numrddatabytes\r
 * \r
 * Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for\r
 * 8 bytes.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                      | Value | Description\r
 * :------------------------------------------|:------|:------------\r
 *  ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 | 0x0   | Read 1 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 | 0x1   | Read 2 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 | 0x2   | Read 3 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 | 0x3   | Read 4 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 | 0x4   | Read 5 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 | 0x5   | Read 6 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 | 0x6   | Read 7 Byte\r
 *  ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 | 0x7   | Read 8 Byte\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES\r
 * \r
 * Read 1 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1   0x0\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES\r
 * \r
 * Read 2 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2   0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES\r
 * \r
 * Read 3 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3   0x2\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES\r
 * \r
 * Read 4 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4   0x3\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES\r
 * \r
 * Read 5 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5   0x4\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES\r
 * \r
 * Read 6 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6   0x5\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES\r
 * \r
 * Read 7 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7   0x6\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_NUMRDDATABYTES\r
 * \r
 * Read 8 Byte\r
 */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8   0x7\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB        20\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB        22\r
/* The width in bits of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH      3\r
/* The mask used to set the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK    0x00700000\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value. */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK    0xff8fffff\r
/* The reset value of the ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field. */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_NUMRDDATABYTES field value from a register. */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)\r
/* Produces a ALT_QSPI_FLSHCMD_NUMRDDATABYTES register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)\r
\r
/*\r
 * Field : Read Data Enable - enrddata\r
 * \r
 * If enabled, the command specified in the command opcode field (bits 31:24)\r
 * requires read data bytes to be received from the device.\r
 * \r
 * Field Enumeration Values:\r
 * \r
 *  Enum                                 | Value | Description               \r
 * :-------------------------------------|:------|:---------------------------\r
 *  ALT_QSPI_FLSHCMD_ENRDDATA_E_EN       | 0x1   | Command Requires read data\r
 *  ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION | 0x0   | No Action                 \r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA\r
 * \r
 * Command Requires read data\r
 */\r
#define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN          0x1\r
/*\r
 * Enumerated value for register field ALT_QSPI_FLSHCMD_ENRDDATA\r
 * \r
 * No Action\r
 */\r
#define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION    0x0\r
\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */\r
#define ALT_QSPI_FLSHCMD_ENRDDATA_LSB        23\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */\r
#define ALT_QSPI_FLSHCMD_ENRDDATA_MSB        23\r
/* The width in bits of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */\r
#define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH      1\r
/* The mask used to set the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */\r
#define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK    0x00800000\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_ENRDDATA register field value. */\r
#define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK    0xff7fffff\r
/* The reset value of the ALT_QSPI_FLSHCMD_ENRDDATA register field. */\r
#define ALT_QSPI_FLSHCMD_ENRDDATA_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_ENRDDATA field value from a register. */\r
#define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)\r
/* Produces a ALT_QSPI_FLSHCMD_ENRDDATA register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)\r
\r
/*\r
 * Field : Command Opcode - cmdopcode\r
 * \r
 * The command opcode field should be setup before triggering the command. For\r
 * example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of\r
 * this register launches the command. NOTE : Using this approach to issue commands\r
 * to the device will make use of the instruction type of the device instruction\r
 * configuration register. If this field is set to 2'b00, then the command opcode,\r
 * command address, command dummy bytes and command data will all be transferred in\r
 * a serial fashion. If this field is set to 2'b01, then the command opcode,\r
 * command address, command dummy bytes and command data will all be transferred in\r
 * parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command\r
 * opcode, command address, command dummy bytes and command data will all be\r
 * transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */\r
#define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB        24\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */\r
#define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB        31\r
/* The width in bits of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */\r
#define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH      8\r
/* The mask used to set the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */\r
#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK    0xff000000\r
/* The mask used to clear the ALT_QSPI_FLSHCMD_CMDOPCODE register field value. */\r
#define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK    0x00ffffff\r
/* The reset value of the ALT_QSPI_FLSHCMD_CMDOPCODE register field. */\r
#define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMD_CMDOPCODE field value from a register. */\r
#define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)\r
/* Produces a ALT_QSPI_FLSHCMD_CMDOPCODE register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_FLSHCMD.\r
 */\r
struct ALT_QSPI_FLSHCMD_s\r
{\r
    uint32_t        execcmd        :  1;  /* Execute Command */\r
    const uint32_t  cmdexecstat    :  1;  /* Command Execution Status */\r
    uint32_t                       :  5;  /* *UNDEFINED* */\r
    uint32_t        numdummybytes  :  5;  /* Number of Dummy Bytes */\r
    uint32_t        numwrdatabytes :  3;  /* Number of Write Data Bytes */\r
    uint32_t        enwrdata       :  1;  /* Write Data Enable */\r
    uint32_t        numaddrbytes   :  2;  /* Number of Address Bytes */\r
    uint32_t        enmodebit      :  1;  /* Mode Bit Enable */\r
    uint32_t        encmdaddr      :  1;  /* Command Address Enable */\r
    uint32_t        numrddatabytes :  3;  /* Number of Read Data Bytes */\r
    uint32_t        enrddata       :  1;  /* Read Data Enable */\r
    uint32_t        cmdopcode      :  8;  /* Command Opcode */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_FLSHCMD. */\r
typedef volatile struct ALT_QSPI_FLSHCMD_s  ALT_QSPI_FLSHCMD_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_FLSHCMD register from the beginning of the component. */\r
#define ALT_QSPI_FLSHCMD_OFST        0x90\r
\r
/*\r
 * Register : Flash Command Address Registers - flashcmdaddr\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description    \r
 * :-------|:-------|:------|:----------------\r
 *  [31:0] | RW     | 0x0   | Command Address\r
 * \r
 */\r
/*\r
 * Field : Command Address - addr\r
 * \r
 * This should be setup before triggering the command with execute field (bit 0) of\r
 * the Flash Command Control register. It is the address used by the command\r
 * specified in the opcode field (bits 31:24) of the Flash Command Control\r
 * register.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */\r
#define ALT_QSPI_FLSHCMDADDR_ADDR_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */\r
#define ALT_QSPI_FLSHCMDADDR_ADDR_MSB        31\r
/* The width in bits of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */\r
#define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH      32\r
/* The mask used to set the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */\r
#define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_FLSHCMDADDR_ADDR register field value. */\r
#define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_FLSHCMDADDR_ADDR register field. */\r
#define ALT_QSPI_FLSHCMDADDR_ADDR_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMDADDR_ADDR field value from a register. */\r
#define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_FLSHCMDADDR_ADDR register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_FLSHCMDADDR.\r
 */\r
struct ALT_QSPI_FLSHCMDADDR_s\r
{\r
    uint32_t  addr : 32;  /* Command Address */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_FLSHCMDADDR. */\r
typedef volatile struct ALT_QSPI_FLSHCMDADDR_s  ALT_QSPI_FLSHCMDADDR_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_FLSHCMDADDR register from the beginning of the component. */\r
#define ALT_QSPI_FLSHCMDADDR_OFST        0x94\r
\r
/*\r
 * Register : Flash Command Read Data Register (Lower) - flashcmdrddatalo\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description                   \r
 * :-------|:-------|:------|:-------------------------------\r
 *  [31:0] | RW     | 0x0   | Command Read Data (Lower byte)\r
 * \r
 */\r
/*\r
 * Field : Command Read Data (Lower byte) - data\r
 * \r
 * This is the data that is returned by the flash device for any status or\r
 * configuration read operation carried out by triggering the event in the control\r
 * register. The register will be valid when the polling bit in the control\r
 * register is low.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */\r
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */\r
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB        31\r
/* The width in bits of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */\r
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH      32\r
/* The mask used to set the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */\r
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATALO_DATA register field value. */\r
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_FLSHCMDRDDATALO_DATA register field. */\r
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMDRDDATALO_DATA field value from a register. */\r
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_FLSHCMDRDDATALO_DATA register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_FLSHCMDRDDATALO.\r
 */\r
struct ALT_QSPI_FLSHCMDRDDATALO_s\r
{\r
    uint32_t  data : 32;  /* Command Read Data (Lower byte) */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATALO. */\r
typedef volatile struct ALT_QSPI_FLSHCMDRDDATALO_s  ALT_QSPI_FLSHCMDRDDATALO_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_FLSHCMDRDDATALO register from the beginning of the component. */\r
#define ALT_QSPI_FLSHCMDRDDATALO_OFST        0xa0\r
\r
/*\r
 * Register : Flash Command Read Data Register (Upper) - flashcmdrddataup\r
 * \r
 * Device Instruction Register\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description                   \r
 * :-------|:-------|:------|:-------------------------------\r
 *  [31:0] | RW     | 0x0   | Command Read Data (Upper byte)\r
 * \r
 */\r
/*\r
 * Field : Command Read Data (Upper byte) - data\r
 * \r
 * This is the data that is returned by the FLASH device for any status or\r
 * configuration read operation carried out by triggering the event in the control\r
 * register. The register will be valid when the polling bit in the control\r
 * register is low.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */\r
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */\r
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB        31\r
/* The width in bits of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */\r
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH      32\r
/* The mask used to set the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */\r
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value. */\r
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_FLSHCMDRDDATAUP_DATA register field. */\r
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMDRDDATAUP_DATA field value from a register. */\r
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_FLSHCMDRDDATAUP_DATA register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_FLSHCMDRDDATAUP.\r
 */\r
struct ALT_QSPI_FLSHCMDRDDATAUP_s\r
{\r
    uint32_t  data : 32;  /* Command Read Data (Upper byte) */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_FLSHCMDRDDATAUP. */\r
typedef volatile struct ALT_QSPI_FLSHCMDRDDATAUP_s  ALT_QSPI_FLSHCMDRDDATAUP_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_FLSHCMDRDDATAUP register from the beginning of the component. */\r
#define ALT_QSPI_FLSHCMDRDDATAUP_OFST        0xa4\r
\r
/*\r
 * Register : Flash Command Write Data Register (Lower) - flashcmdwrdatalo\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description                  \r
 * :-------|:-------|:------|:------------------------------\r
 *  [31:0] | RW     | 0x0   | Command Write Data Lower Byte\r
 * \r
 */\r
/*\r
 * Field : Command Write Data Lower Byte - data\r
 * \r
 * This is the command write data lower byte. This should be setup before\r
 * triggering the command with execute field (bit 0) of the Flash Command Control\r
 * register. It is the data that is to be written to the flash for any status or\r
 * configuration write operation carried out by triggering the event in the Flash\r
 * Command Control register.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */\r
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */\r
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB        31\r
/* The width in bits of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */\r
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH      32\r
/* The mask used to set the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */\r
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATALO_DATA register field value. */\r
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_FLSHCMDWRDATALO_DATA register field. */\r
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMDWRDATALO_DATA field value from a register. */\r
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_FLSHCMDWRDATALO_DATA register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_FLSHCMDWRDATALO.\r
 */\r
struct ALT_QSPI_FLSHCMDWRDATALO_s\r
{\r
    uint32_t  data : 32;  /* Command Write Data Lower Byte */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATALO. */\r
typedef volatile struct ALT_QSPI_FLSHCMDWRDATALO_s  ALT_QSPI_FLSHCMDWRDATALO_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_FLSHCMDWRDATALO register from the beginning of the component. */\r
#define ALT_QSPI_FLSHCMDWRDATALO_OFST        0xa8\r
\r
/*\r
 * Register : Flash Command Write Data Register (Upper) - flashcmdwrdataup\r
 * \r
 * Register Layout\r
 * \r
 *  Bits   | Access | Reset | Description                  \r
 * :-------|:-------|:------|:------------------------------\r
 *  [31:0] | RW     | 0x0   | ALT_QSPI_FLSHCMDWRDATAUP_DATA\r
 * \r
 */\r
/*\r
 * Field : data\r
 * \r
 * This is the command write data upper byte. This should be setup before\r
 * triggering the command with execute field (bit 0) of the Flash Command Control\r
 * register. It is the data that is to be written to the flash for any status or\r
 * configuration write operation carried out by triggering the event in the Flash\r
 * Command Control register.\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */\r
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */\r
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB        31\r
/* The width in bits of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */\r
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH      32\r
/* The mask used to set the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */\r
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK    0xffffffff\r
/* The mask used to clear the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value. */\r
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK    0x00000000\r
/* The reset value of the ALT_QSPI_FLSHCMDWRDATAUP_DATA register field. */\r
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET      0x0\r
/* Extracts the ALT_QSPI_FLSHCMDWRDATAUP_DATA field value from a register. */\r
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)\r
/* Produces a ALT_QSPI_FLSHCMDWRDATAUP_DATA register field value suitable for setting the register. */\r
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_FLSHCMDWRDATAUP.\r
 */\r
struct ALT_QSPI_FLSHCMDWRDATAUP_s\r
{\r
    uint32_t  data : 32;  /* ALT_QSPI_FLSHCMDWRDATAUP_DATA */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_FLSHCMDWRDATAUP. */\r
typedef volatile struct ALT_QSPI_FLSHCMDWRDATAUP_s  ALT_QSPI_FLSHCMDWRDATAUP_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_FLSHCMDWRDATAUP register from the beginning of the component. */\r
#define ALT_QSPI_FLSHCMDWRDATAUP_OFST        0xac\r
\r
/*\r
 * Register : Module ID Register - moduleid\r
 * \r
 * Register Layout\r
 * \r
 *  Bits    | Access | Reset  | Description     \r
 * :--------|:-------|:-------|:-----------------\r
 *  [24:0]  | R      | 0x1001 | Module ID number\r
 *  [31:25] | ???    | 0x0    | *UNDEFINED*     \r
 * \r
 */\r
/*\r
 * Field : Module ID number - value\r
 * \r
 * Field Access Macros:\r
 * \r
 */\r
/* The Least Significant Bit (LSB) position of the ALT_QSPI_MODULEID_VALUE register field. */\r
#define ALT_QSPI_MODULEID_VALUE_LSB        0\r
/* The Most Significant Bit (MSB) position of the ALT_QSPI_MODULEID_VALUE register field. */\r
#define ALT_QSPI_MODULEID_VALUE_MSB        24\r
/* The width in bits of the ALT_QSPI_MODULEID_VALUE register field. */\r
#define ALT_QSPI_MODULEID_VALUE_WIDTH      25\r
/* The mask used to set the ALT_QSPI_MODULEID_VALUE register field value. */\r
#define ALT_QSPI_MODULEID_VALUE_SET_MSK    0x01ffffff\r
/* The mask used to clear the ALT_QSPI_MODULEID_VALUE register field value. */\r
#define ALT_QSPI_MODULEID_VALUE_CLR_MSK    0xfe000000\r
/* The reset value of the ALT_QSPI_MODULEID_VALUE register field. */\r
#define ALT_QSPI_MODULEID_VALUE_RESET      0x1001\r
/* Extracts the ALT_QSPI_MODULEID_VALUE field value from a register. */\r
#define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)\r
/* Produces a ALT_QSPI_MODULEID_VALUE register field value suitable for setting the register. */\r
#define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register ALT_QSPI_MODULEID.\r
 */\r
struct ALT_QSPI_MODULEID_s\r
{\r
    const uint32_t  value : 25;  /* Module ID number */\r
    uint32_t              :  7;  /* *UNDEFINED* */\r
};\r
\r
/* The typedef declaration for register ALT_QSPI_MODULEID. */\r
typedef volatile struct ALT_QSPI_MODULEID_s  ALT_QSPI_MODULEID_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
/* The byte offset of the ALT_QSPI_MODULEID register from the beginning of the component. */\r
#define ALT_QSPI_MODULEID_OFST        0xfc\r
\r
#ifndef __ASSEMBLY__\r
/*\r
 * WARNING: The C register and register group struct declarations are provided for\r
 * convenience and illustrative purposes. They should, however, be used with\r
 * caution as the C language standard provides no guarantees about the alignment or\r
 * atomicity of device memory accesses. The recommended practice for writing\r
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and\r
 * alt_write_word() functions.\r
 * \r
 * The struct declaration for register group ALT_QSPI.\r
 */\r
struct ALT_QSPI_s\r
{\r
    volatile ALT_QSPI_CFG_t              cfg;                 /* ALT_QSPI_CFG */\r
    volatile ALT_QSPI_DEVRD_t            devrd;               /* ALT_QSPI_DEVRD */\r
    volatile ALT_QSPI_DEVWR_t            devwr;               /* ALT_QSPI_DEVWR */\r
    volatile ALT_QSPI_DELAY_t            delay;               /* ALT_QSPI_DELAY */\r
    volatile ALT_QSPI_RDDATACAP_t        rddatacap;           /* ALT_QSPI_RDDATACAP */\r
    volatile ALT_QSPI_DEVSZ_t            devsz;               /* ALT_QSPI_DEVSZ */\r
    volatile ALT_QSPI_SRAMPART_t         srampart;            /* ALT_QSPI_SRAMPART */\r
    volatile ALT_QSPI_INDADDRTRIG_t      indaddrtrig;         /* ALT_QSPI_INDADDRTRIG */\r
    volatile ALT_QSPI_DMAPER_t           dmaper;              /* ALT_QSPI_DMAPER */\r
    volatile ALT_QSPI_REMAPADDR_t        remapaddr;           /* ALT_QSPI_REMAPADDR */\r
    volatile ALT_QSPI_MODBIT_t           modebit;             /* ALT_QSPI_MODBIT */\r
    volatile ALT_QSPI_SRAMFILL_t         sramfill;            /* ALT_QSPI_SRAMFILL */\r
    volatile ALT_QSPI_TXTHRESH_t         txthresh;            /* ALT_QSPI_TXTHRESH */\r
    volatile ALT_QSPI_RXTHRESH_t         rxthresh;            /* ALT_QSPI_RXTHRESH */\r
    volatile uint32_t                    _pad_0x38_0x3f[2];   /* *UNDEFINED* */\r
    volatile ALT_QSPI_IRQSTAT_t          irqstat;             /* ALT_QSPI_IRQSTAT */\r
    volatile ALT_QSPI_IRQMSK_t           irqmask;             /* ALT_QSPI_IRQMSK */\r
    volatile uint32_t                    _pad_0x48_0x4f[2];   /* *UNDEFINED* */\r
    volatile ALT_QSPI_LOWWRPROT_t        lowwrprot;           /* ALT_QSPI_LOWWRPROT */\r
    volatile ALT_QSPI_UPPWRPROT_t        uppwrprot;           /* ALT_QSPI_UPPWRPROT */\r
    volatile ALT_QSPI_WRPROT_t           wrprot;              /* ALT_QSPI_WRPROT */\r
    volatile uint32_t                    _pad_0x5c_0x5f;      /* *UNDEFINED* */\r
    volatile ALT_QSPI_INDRD_t            indrd;               /* ALT_QSPI_INDRD */\r
    volatile ALT_QSPI_INDRDWATER_t       indrdwater;          /* ALT_QSPI_INDRDWATER */\r
    volatile ALT_QSPI_INDRDSTADDR_t      indrdstaddr;         /* ALT_QSPI_INDRDSTADDR */\r
    volatile ALT_QSPI_INDRDCNT_t         indrdcnt;            /* ALT_QSPI_INDRDCNT */\r
    volatile ALT_QSPI_INDWR_t            indwr;               /* ALT_QSPI_INDWR */\r
    volatile ALT_QSPI_INDWRWATER_t       indwrwater;          /* ALT_QSPI_INDWRWATER */\r
    volatile ALT_QSPI_INDWRSTADDR_t      indwrstaddr;         /* ALT_QSPI_INDWRSTADDR */\r
    volatile ALT_QSPI_INDWRCNT_t         indwrcnt;            /* ALT_QSPI_INDWRCNT */\r
    volatile uint32_t                    _pad_0x80_0x8f[4];   /* *UNDEFINED* */\r
    volatile ALT_QSPI_FLSHCMD_t          flashcmd;            /* ALT_QSPI_FLSHCMD */\r
    volatile ALT_QSPI_FLSHCMDADDR_t      flashcmdaddr;        /* ALT_QSPI_FLSHCMDADDR */\r
    volatile uint32_t                    _pad_0x98_0x9f[2];   /* *UNDEFINED* */\r
    volatile ALT_QSPI_FLSHCMDRDDATALO_t  flashcmdrddatalo;    /* ALT_QSPI_FLSHCMDRDDATALO */\r
    volatile ALT_QSPI_FLSHCMDRDDATAUP_t  flashcmdrddataup;    /* ALT_QSPI_FLSHCMDRDDATAUP */\r
    volatile ALT_QSPI_FLSHCMDWRDATALO_t  flashcmdwrdatalo;    /* ALT_QSPI_FLSHCMDWRDATALO */\r
    volatile ALT_QSPI_FLSHCMDWRDATAUP_t  flashcmdwrdataup;    /* ALT_QSPI_FLSHCMDWRDATAUP */\r
    volatile uint32_t                    _pad_0xb0_0xfb[19];  /* *UNDEFINED* */\r
    volatile ALT_QSPI_MODULEID_t         moduleid;            /* ALT_QSPI_MODULEID */\r
};\r
\r
/* The typedef declaration for register group ALT_QSPI. */\r
typedef volatile struct ALT_QSPI_s  ALT_QSPI_t;\r
/* The struct declaration for the raw register contents of register group ALT_QSPI. */\r
struct ALT_QSPI_raw_s\r
{\r
    volatile uint32_t  cfg;                 /* ALT_QSPI_CFG */\r
    volatile uint32_t  devrd;               /* ALT_QSPI_DEVRD */\r
    volatile uint32_t  devwr;               /* ALT_QSPI_DEVWR */\r
    volatile uint32_t  delay;               /* ALT_QSPI_DELAY */\r
    volatile uint32_t  rddatacap;           /* ALT_QSPI_RDDATACAP */\r
    volatile uint32_t  devsz;               /* ALT_QSPI_DEVSZ */\r
    volatile uint32_t  srampart;            /* ALT_QSPI_SRAMPART */\r
    volatile uint32_t  indaddrtrig;         /* ALT_QSPI_INDADDRTRIG */\r
    volatile uint32_t  dmaper;              /* ALT_QSPI_DMAPER */\r
    volatile uint32_t  remapaddr;           /* ALT_QSPI_REMAPADDR */\r
    volatile uint32_t  modebit;             /* ALT_QSPI_MODBIT */\r
    volatile uint32_t  sramfill;            /* ALT_QSPI_SRAMFILL */\r
    volatile uint32_t  txthresh;            /* ALT_QSPI_TXTHRESH */\r
    volatile uint32_t  rxthresh;            /* ALT_QSPI_RXTHRESH */\r
    volatile uint32_t  _pad_0x38_0x3f[2];   /* *UNDEFINED* */\r
    volatile uint32_t  irqstat;             /* ALT_QSPI_IRQSTAT */\r
    volatile uint32_t  irqmask;             /* ALT_QSPI_IRQMSK */\r
    volatile uint32_t  _pad_0x48_0x4f[2];   /* *UNDEFINED* */\r
    volatile uint32_t  lowwrprot;           /* ALT_QSPI_LOWWRPROT */\r
    volatile uint32_t  uppwrprot;           /* ALT_QSPI_UPPWRPROT */\r
    volatile uint32_t  wrprot;              /* ALT_QSPI_WRPROT */\r
    volatile uint32_t  _pad_0x5c_0x5f;      /* *UNDEFINED* */\r
    volatile uint32_t  indrd;               /* ALT_QSPI_INDRD */\r
    volatile uint32_t  indrdwater;          /* ALT_QSPI_INDRDWATER */\r
    volatile uint32_t  indrdstaddr;         /* ALT_QSPI_INDRDSTADDR */\r
    volatile uint32_t  indrdcnt;            /* ALT_QSPI_INDRDCNT */\r
    volatile uint32_t  indwr;               /* ALT_QSPI_INDWR */\r
    volatile uint32_t  indwrwater;          /* ALT_QSPI_INDWRWATER */\r
    volatile uint32_t  indwrstaddr;         /* ALT_QSPI_INDWRSTADDR */\r
    volatile uint32_t  indwrcnt;            /* ALT_QSPI_INDWRCNT */\r
    volatile uint32_t  _pad_0x80_0x8f[4];   /* *UNDEFINED* */\r
    volatile uint32_t  flashcmd;            /* ALT_QSPI_FLSHCMD */\r
    volatile uint32_t  flashcmdaddr;        /* ALT_QSPI_FLSHCMDADDR */\r
    volatile uint32_t  _pad_0x98_0x9f[2];   /* *UNDEFINED* */\r
    volatile uint32_t  flashcmdrddatalo;    /* ALT_QSPI_FLSHCMDRDDATALO */\r
    volatile uint32_t  flashcmdrddataup;    /* ALT_QSPI_FLSHCMDRDDATAUP */\r
    volatile uint32_t  flashcmdwrdatalo;    /* ALT_QSPI_FLSHCMDWRDATALO */\r
    volatile uint32_t  flashcmdwrdataup;    /* ALT_QSPI_FLSHCMDWRDATAUP */\r
    volatile uint32_t  _pad_0xb0_0xfb[19];  /* *UNDEFINED* */\r
    volatile uint32_t  moduleid;            /* ALT_QSPI_MODULEID */\r
};\r
\r
/* The typedef declaration for the raw register contents of register group ALT_QSPI. */\r
typedef volatile struct ALT_QSPI_raw_s  ALT_QSPI_raw_t;\r
#endif  /* __ASSEMBLY__ */\r
\r
\r
#ifdef __cplusplus\r
}\r
#endif  /* __cplusplus */\r
#endif  /* __ALTERA_ALT_QSPI_H__ */\r
\r