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31 ******************************************************************************/
32 /****************************************************************************/
36 * @addtogroup devcfg_v3_1
39 * This file contains the implementation of the interface reset functionality
41 * MODIFICATION HISTORY:
43 * Ver Who Date Changes
44 * ----- --- -------- ---------------------------------------------
45 * 2.04a kpc 10/07/13 First release
48 ******************************************************************************/
50 /***************************** Include Files *********************************/
52 #include "xdevcfg_hw.h"
54 /************************** Constant Definitions *****************************/
56 /**************************** Type Definitions *******************************/
58 /***************** Macros (Inline Functions) Definitions *********************/
60 /************************** Function Prototypes ******************************/
62 /************************** Variable Definitions *****************************/
64 /*****************************************************************************/
66 * This function perform the reset sequence to the given devcfg interface by
67 * configuring the appropriate control bits in the devcfg specifc registers
68 * the devcfg reset squence involves the following steps
69 * Disable all the interuupts
71 * Update relevant config registers with reset values
72 * Disbale the looopback mode and pcap rate enable
74 * @param BaseAddress of the interface
79 * This function will not modify the slcr registers that are relavant for
81 ******************************************************************************/
82 void XDcfg_ResetHw(u32 BaseAddr)
86 /* Mask the interrupts */
87 XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
89 /* Clear the interuupt status */
90 Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
91 XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
92 /* Clear the source address register */
93 XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0);
94 /* Clear the destination address register */
95 XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0);
96 /* Clear the source length register */
97 XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0);
98 /* Clear the destination length register */
99 XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0);
100 /* Clear the loopback enable bit */
101 Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET);
102 Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK;
103 XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
104 /*Reset the configuration register to reset value */
105 XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
106 XDCFG_CONFIG_RESET_VALUE);
107 /*Disable the PCAP rate enable bit */
108 Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
109 Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;
110 XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);