#define configUSE_APPLICATION_TASK_TAG 0\r
#define configUSE_COUNTING_SEMAPHORES 1\r
#define configUSE_QUEUE_SETS 1\r
+#define configSUPPORT_STATIC_ALLOCATION 1\r
\r
/* Co-routine definitions. */\r
#define configUSE_CO_ROUTINES 0\r
#define XSCUTIMER_CLOCK_HZ ( XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 2UL )\r
\r
static XScuTimer xTimer;\r
+XScuGic xInterruptController; /* Interrupt controller instance */\r
\r
/*\r
* The application must provide a function that configures a peripheral to\r
*/\r
void vConfigureTickInterrupt( void )\r
{\r
-static XScuGic xInterruptController; /* Interrupt controller instance */\r
BaseType_t xStatus;\r
extern void FreeRTOS_Tick_Handler( void );\r
XScuTimer_Config *pxTimerConfig;\r
#include "EventGroupsDemo.h"\r
#include "TaskNotify.h"\r
#include "IntSemTest.h"\r
+#include "StaticAllocation.h"\r
\r
/* Priorities for the demo application tasks. */\r
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
vStartEventGroupTasks();\r
vStartTaskNotifyTask();\r
vStartInterruptSemaphoreTasks();\r
-\r
+ vStartStaticallyAllocatedTasks();\r
\r
/* Start the tasks that implements the command console on the UART, as\r
described above. */\r
ulErrorFound |= 1UL << 14UL;\r
}\r
\r
+ if( xAreStaticAllocationTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= 1UL << 15UL;\r
+ }\r
+\r
/* Check that the register test 1 task is still running. */\r
if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
{\r
- ulErrorFound |= 1UL << 15UL;\r
+ ulErrorFound |= 1UL << 16UL;\r
}\r
ulLastRegTest1Value = ulRegTest1LoopCounter;\r
\r
/* Check that the register test 2 task is still running. */\r
if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
{\r
- ulErrorFound |= 1UL << 16UL;\r
+ ulErrorFound |= 1UL << 17UL;\r
}\r
ulLastRegTest2Value = ulRegTest2LoopCounter;\r
\r
XScuWdt_SetTimerMode( &xWatchDogInstance );\r
XScuWdt_Start( &xWatchDogInstance );\r
}\r
+/*-----------------------------------------------------------*/\r
\r
+void vApplicationGetIdleTaskMemory( DummyTCB_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint16_t *pusIdleTaskStackSize )\r
+{\r
+ /* configUSE_STATIC_ALLOCATION is set to 1, so the application has the\r
+ opportunity to supply the buffers that will be used by the Idle task as its\r
+ stack and to hold its TCB. If these are set to NULL then the buffers will\r
+ be allocated dynamically, just as if xTaskCreate() had been called. */\r
+ *ppxIdleTaskTCBBuffer = NULL;\r
+ *ppxIdleTaskStackBuffer = NULL;\r
+ *pusIdleTaskStackSize = configMINIMAL_STACK_SIZE; /* In words. NOT in bytes! */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationGetTimerTaskMemory( DummyTCB_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint16_t *pusTimerTaskStackSize )\r
+{\r
+ /* configUSE_STATIC_ALLOCATION is set to 1, so the application has the\r
+ opportunity to supply the buffers that will be used by the Timer/RTOS daemon\r
+ task as its stack and to hold its TCB. If these are set to NULL then the\r
+ buffers will be allocated dynamically, just as if xTaskCreate() had been\r
+ called. */\r
+ *ppxTimerTaskTCBBuffer = NULL;\r
+ *ppxTimerTaskStackBuffer = NULL;\r
+ *pusTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; /* In words. NOT in bytes! */\r
+}\r
\r
\r
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xadcps.h
+* @addtogroup xadcps_v2_0
+* @{
+* @details
*
* The XAdcPs driver supports the Xilinx XADC/ADC device.
*
#endif
#endif /* End of protection macro. */
+/** @} */
/**
*
* @file xadcps_hw.h
+* @addtogroup xadcps_v2_0
+* @{
*
* This header file contains identifiers and basic driver functions (or
* macros) that can be used to access the XADC device through the Device
#endif
#endif /* End of protection macro. */
+/** @} */
/**
*
* @file xcanps.h
+* @addtogroup canps_v2_0
+* @{
+* @details
*
* The Xilinx CAN driver component. This component supports the Xilinx
* CAN Controller.
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xcanps_hw.h
+* @addtogroup canps_v2_0
+* @{
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_0
+* @{
+* @details
*
* dummy file
*
******************************************************************************/
+/** @} */
/**
*
* @file xdevcfg.h
+* @addtogroup devcfg_v3_1
+* @{
+* @details
*
* The is the main header file for the Device Configuration Interface of the Zynq
* device. The device configuration interface has three main functionality.
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_1
+* @{
*
* This file contains the hardware interface to the Device Config Interface.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xdmaps.h
+* @addtogroup dmaps_v2_0
+* @{
+* @details
*
*
* <pre>
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_0
+* @{
*
* This header file contains the hardware interface of an XDmaPs device.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xemacps.h
+* @addtogroup emacps_v2_0
+* @{
+* @details
*
* The Xilinx Embedded Processor Block Ethernet driver.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xemacps_bd.h
+* @addtogroup emacps_v2_0
+* @{
*
* This header provides operations to manage buffer descriptors in support
* of scatter-gather DMA.
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xemacps_bdring.h
+* @addtogroup emacps_v2_0
+* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
* DMA functionalities.
#endif /* end of protection macros */
+/** @} */
/**
*
* @file xemacps_hw.h
+* @addtogroup emacps_v2_0
+* @{
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xgpiops.h
+* @addtogroup gpiops_v2_1
+* @{
+* @details
*
* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
* Controller.
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xgpiops_hw.h
+* @addtogroup gpiops_v2_1
+* @{
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
#endif /* __cplusplus */
#endif /* XGPIOPS_HW_H */
+/** @} */
/**
*
* @file xiicps.h
+* @addtogroup iicps_v2_1
+* @{
+* @details
*
* This is an implementation of IIC driver in the PS block. The device can
* be either a master or a slave on the IIC bus. This implementation supports
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xiicps_hw.h
+* @addtogroup iicps_v2_1
+* @{
*
* This header file contains the hardware definition for an IIC device.
* It includes register definitions and interface functions to read/write
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xqspips.h
+* @addtogroup qspips_v3_0
+* @{
+* @details
*
* This file contains the implementation of the XQspiPs driver. It supports only
* master mode. User documentation for the driver functions is contained in this
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xqspips_hw.h
+* @addtogroup qspips_v3_0
+* @{
*
* This header file contains the identifiers and basic HW access driver
* functions (or macros) that can be used to access the device. Other driver
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xscugic.h
+* @addtogroup scugic_v2_1
+* @{
+* @details
*
* The generic interrupt controller driver component.
*
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xscugic_hw.h
+* @addtogroup scugic_v2_1
+* @{
*
* This header file contains identifiers and HW access functions (or
* macros) that can be used to access the device. The user should refer to the
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xscutimer.h
+* @addtogroup scutimer_v2_0
+* @{
+* @details
*
* The timer driver supports the Cortex A9 private timer.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_0
+* @{
*
* This file contains the hardware interface to the Timer.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xscuwdt.h
+* @addtogroup scuwdt_v2_0
+* @{
+* @details
*
* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
* watchdog timer hardware.
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_0
+* @{
*
* This file contains the hardware interface to the Xilinx SCU private Watch Dog
* Timer (XSCUWDT).
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xsdps.h
+* @addtogroup sdps_v2_1
+* @{
+* @details
*
* This file contains the implementation of XSdPs driver.
* This driver is used initialize read from and write to the SD card.
#endif
#endif /* SD_H_ */
+/** @} */
/**
*
* @file xsdps_hw.h
+* @addtogroup sdps_v2_1
+* @{
*
* This header file contains the identifiers and basic HW access driver
* functions (or macros) that can be used to access the device. Other driver
#endif
#endif /* SD_HW_H_ */
+/** @} */
/**
*
* @file xttcps.h
+* @addtogroup ttcps_v2_0
+* @{
+* @details
*
* This is the driver for one 16-bit timer counter in the Triple Timer Counter
* (TTC) module in the Ps block.
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xttcps_hw.h
+* @addtogroup ttcps_v2_0
+* @{
*
* This file defines the hardware interface to one of the three timer counters
* in the Ps block.
}
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xuartps.h
+* @addtogroup uartps_v2_1
+* @{
+* @details
*
* This driver supports the following features:
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xuartps_hw.h
+* @addtogroup uartps_v2_1
+* @{
*
* This header file contains the hardware interface of an XUartPs device.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xusbps.h
+* @addtogroup usbps_v2_1
+* @{
+* @details
*
* This file contains the implementation of the XUsbPs driver. It is the
* driver for an USB controller in DEVICE or HOST mode.
#endif
#endif /* XUSBPS_H */
+/** @} */
/**
*
* @file xusbps_endpoint.h
+* @addtogroup usbps_v2_1
+* @{
*
* This is an internal file containung the definitions for endpoints. It is
* included by the xusbps_endpoint.c which is implementing the endpoint
#endif
#endif /* XUSBPS_ENDPOINT_H */
+/** @} */
/**
*
* @file xusbps_hw.h
+* @addtogroup usbps_v2_1
+* @{
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. High-level driver functions
#endif
#endif /* XUSBPS_L_H */
+/** @} */
/**
*
* @file xcanps.c
+* @addtogroup canps_v2_0
+* @{
*
* Functions in this file are the minimum required functions for the XCanPs
* driver. See xcanps.h for a detailed description of the driver.
Xil_AssertVoidAlways();
}
+/** @} */
/**
*
* @file xcanps.h
+* @addtogroup canps_v2_0
+* @{
+* @details
*
* The Xilinx CAN driver component. This component supports the Xilinx
* CAN Controller.
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xcanps_hw.c
+* @addtogroup canps_v2_0
+* @{
*
* This file contains the implementation of the canps interface reset sequence
*
{
XCanPs_WriteReg(BaseAddr, XCANPS_SRR_OFFSET, \
XCANPS_SRR_SRST_MASK);
-}
\ No newline at end of file
+}
+/** @} */
\ No newline at end of file
/**
*
* @file xcanps_hw.h
+* @addtogroup canps_v2_0
+* @{
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xcanps_intr.c
+* @addtogroup canps_v2_0
+* @{
*
* This file contains functions related to CAN interrupt handling.
*
return (XST_SUCCESS);
}
+/** @} */
/**
*
* @file xcanps_selftest.c
+* @addtogroup canps_v2_0
+* @{
*
* This file contains a diagnostic self-test function for the XCanPs driver.
*
}
+/** @} */
/**
*
* @file xcanps_sinit.c
+* @addtogroup canps_v2_0
+* @{
*
* This file contains the implementation of the XCanPs driver's static
* initialization functionality.
return CfgPtr;
}
+/** @} */
/**
*
* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_0
+* @{
+* @details
*
* dummy file
*
******************************************************************************/
+/** @} */
/**
*
* @file xdevcfg.c
+* @addtogroup devcfg_v3_1
+* @{
*
* This file contains the implementation of the interface functions for XDcfg
* driver. Refer to the header file xdevcfg.h for more detailed information.
return XST_SUCCESS;
}
+/** @} */
/**
*
* @file xdevcfg.h
+* @addtogroup devcfg_v3_1
+* @{
+* @details
*
* The is the main header file for the Device Configuration Interface of the Zynq
* device. The device configuration interface has three main functionality.
#endif
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xdevcfg_hw.c
+* @addtogroup devcfg_v3_1
+* @{
*
* This file contains the implementation of the interface reset functionality
* <pre>
XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);
}
+/** @} */
/**
*
* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_1
+* @{
*
* This file contains the hardware interface to the Device Config Interface.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xdevcfg_intr.c
+* @addtogroup devcfg_v3_1
+* @{
*
* Contains the implementation of interrupt related functions of the XDcfg
* driver.
InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
InstancePtr->CallBackRef = CallBackRef;
}
+/** @} */
/**
*
* @file xdevcfg_selftest.c
+* @addtogroup devcfg_v3_1
+* @{
*
* Contains diagnostic self-test functions for the XDcfg driver.
*
return Status;
}
+/** @} */
/**
*
* @file xdevcfg_sinit.c
+* @addtogroup devcfg_v3_1
+* @{
*
* This file contains method for static initialization (compile-time) of the
* driver.
return (CfgPtr);
}
+/** @} */
/**
*
* @file xdmaps.c
+* @addtogroup dmaps_v2_0
+* @{
*
* This file contains the implementation of the interface functions for XDmaPs
* driver. Refer to the header file xdmaps.h for more detailed information.
}
+/** @} */
/**
*
* @file xdmaps.h
+* @addtogroup dmaps_v2_0
+* @{
+* @details
*
*
* <pre>
#endif
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xdmaps_hw.c
+* @addtogroup dmaps_v2_0
+* @{
*
* This file contains the implementation of the interface reset functionality
* for XDmaPs driver.
+/** @} */
/**
*
* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_0
+* @{
*
* This header file contains the hardware interface of an XDmaPs device.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xdmaps_selftest.c
+* @addtogroup dmaps_v2_0
+* @{
*
* This file contains the self-test functions for the XDmaPs driver.
*
}
return XST_SUCCESS;
}
+/** @} */
/**
*
* @file xdmaps_sinit.c
+* @addtogroup dmaps_v2_0
+* @{
*
* The implementation of the XDmaPs driver's static initialzation
* functionality.
return CfgPtr;
}
+/** @} */
/**
*
* @file xemacps.c
+* @addtogroup emacps_v2_0
+* @{
*
* The XEmacPs driver. Functions in this file are the minimum required functions
* for this driver. See xemacps.h for a detailed description of the driver.
{
Xil_AssertVoidAlways();
}
+/** @} */
/**
*
* @file xemacps.h
+* @addtogroup emacps_v2_0
+* @{
+* @details
*
* The Xilinx Embedded Processor Block Ethernet driver.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xemacps_bd.h
+* @addtogroup emacps_v2_0
+* @{
*
* This header provides operations to manage buffer descriptors in support
* of scatter-gather DMA.
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xemacps_bdring.c
+* @addtogroup emacps_v2_0
+* @{
*
* This file implements buffer descriptor ring related functions.
*
/* No problems found */
return (XST_SUCCESS);
}
+/** @} */
/**
*
* @file xemacps_bdring.h
+* @addtogroup emacps_v2_0
+* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
* DMA functionalities.
#endif /* end of protection macros */
+/** @} */
/**
*
* @file xemacps_control.c
+* @addtogroup emacps_v2_0
+* @{
*
* Functions in this file implement general purpose command and control related
* functionality. See xemacps.h for a detailed description of the driver.
Reg |= RegUpdateVal;
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
Reg);
-}
\ No newline at end of file
+}
+/** @} */
\ No newline at end of file
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xemacps_hw.c
+* @addtogroup emacps_v2_0
+* @{
*
* This file contains the implementation of the ethernet interface reset sequence
*
+/** @} */
/**
*
* @file xemacps_hw.h
+* @addtogroup emacps_v2_0
+* @{
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xemacps_intr.c
+* @addtogroup emacps_v2_0
+* @{
*
* Functions in this file implement general purpose interrupt processing related
* functionality. See xemacps.h for a detailed description of the driver.
}
}
+/** @} */
/**
*
* @file xemacps_sinit.c
+* @addtogroup emacps_v2_0
+* @{
*
* This file contains lookup method by device ID when success, it returns
* pointer to config table to be used to initialize the device.
return (CfgPtr);
}
+/** @} */
/**
*
* @file xgpiops.c
+* @addtogroup gpiops_v2_1
+* @{
*
* The XGpioPs driver. Functions in this file are the minimum required functions
* for this driver. See xgpiops.h for a detailed description of the driver.
(XGpioPsPinTable[*BankNumber - 1] + 1);
}
}
+/** @} */
/**
*
* @file xgpiops.h
+* @addtogroup gpiops_v2_1
+* @{
+* @details
*
* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
* Controller.
#endif
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xgpiops_hw.c
+* @addtogroup gpiops_v2_1
+* @{
*
* This file contains low level GPIO functions.
*
}
+/** @} */
/**
*
* @file xgpiops_hw.h
+* @addtogroup gpiops_v2_1
+* @{
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
#endif /* __cplusplus */
#endif /* XGPIOPS_HW_H */
+/** @} */
/**
*
* @file xgpiops_intr.c
+* @addtogroup gpiops_v2_1
+* @{
*
* This file contains functions related to GPIO interrupt handling.
*
Xil_AssertVoidAlways();
}
+/** @} */
/**
*
* @file xgpiops_selftest.c
+* @addtogroup gpiops_v2_1
+* @{
*
* This file contains a diagnostic self-test function for the XGpioPs driver.
*
return Status;
}
+/** @} */
/**
*
* @file xgpiops_sinit.c
+* @addtogroup gpiops_v2_1
+* @{
*
* This file contains the implementation of the XGpioPs driver's static
* initialization functionality.
return CfgPtr;
}
+/** @} */
/**
*
* @file xiicps.c
+* @addtogroup iicps_v2_1
+* @{
*
* Contains implementation of required functions for the XIicPs driver.
* See xiicps.h for detailed description of the device and driver.
return InstancePtr->SendByteCount;
}
+/** @} */
/**
*
* @file xiicps.h
+* @addtogroup iicps_v2_1
+* @{
+* @details
*
* This is an implementation of IIC driver in the PS block. The device can
* be either a master or a slave on the IIC bus. This implementation supports
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xiicps_hw.c
+* @addtogroup iicps_v2_1
+* @{
*
* Contains implementation of required functions for providing the reset sequence
* to the i2c interface
XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0);
}
+/** @} */
/**
*
* @file xiicps_hw.h
+* @addtogroup iicps_v2_1
+* @{
*
* This header file contains the hardware definition for an IIC device.
* It includes register definitions and interface functions to read/write
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xiicps_intr.c
+* @addtogroup iicps_v2_1
+* @{
*
* Contains functions of the XIicPs driver for interrupt-driven transfers.
* See xiicps.h for a detailed description of the device and driver.
InstancePtr->StatusHandler = FuncPtr;
InstancePtr->CallBackRef = CallBackRef;
}
+/** @} */
/**
*
* @file xiicps_master.c
+* @addtogroup iicps_v2_1
+* @{
*
* Handles master mode transfers.
*
+/** @} */
/**
*
* @file xiicps_options.c
+* @addtogroup iicps_v2_1
+* @{
*
* Contains functions for the configuration of the XIccPs driver.
*
return ActualFscl;
}
+/** @} */
/**
*
* @file xiicps_selftest.c
+* @addtogroup iicps_v2_1
+* @{
*
* This component contains the implementation of selftest functions for the
* XIicPs driver component.
return XST_SUCCESS;
}
+/** @} */
/**
*
* @file xiicps_sinit.c
+* @addtogroup iicps_v2_1
+* @{
*
* The implementation of the XIicPs component's static initialization
* functionality.
return CfgPtr;
}
+/** @} */
/*****************************************************************************/
/**
* @file xiicps_slave.c
+* @addtogroup iicps_v2_1
+* @{
*
* Handles slave transfers
*
return InstancePtr->RecvByteCount;
}
+/** @} */
/**
*
* @file xqspips.c
+* @addtogroup qspips_v3_0
+* @{
*
* Contains implements the interface functions of the XQspiPs driver.
* See xqspips.h for a detailed description of the device and driver.
InstancePtr->RequestedBytes = 0;
}
}
+/** @} */
/**
*
* @file xqspips.h
+* @addtogroup qspips_v3_0
+* @{
+* @details
*
* This file contains the implementation of the XQspiPs driver. It supports only
* master mode. User documentation for the driver functions is contained in this
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xqspips_hw.c
+* @addtogroup qspips_v3_0
+* @{
*
* Contains low level functions, primarily reset related.
*
}
+/** @} */
/**
*
* @file xqspips_hw.h
+* @addtogroup qspips_v3_0
+* @{
*
* This header file contains the identifiers and basic HW access driver
* functions (or macros) that can be used to access the device. Other driver
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xqspips_options.c
+* @addtogroup qspips_v3_0
+* @{
*
* Contains functions for the configuration of the XQspiPs driver component.
*
*DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
XQSPIPS_DR_NSS_SHIFT);
}
+/** @} */
/**
*
* @file xqspips_selftest.c
+* @addtogroup qspips_v3_0
+* @{
*
* This file contains the implementation of selftest function for the QSPI
* device.
return XST_SUCCESS;
}
+/** @} */
/**
*
* @file xqspips_sinit.c
+* @addtogroup qspips_v3_0
+* @{
*
* The implementation of the XQspiPs component's static initialization
* functionality.
}
return CfgPtr;
}
+/** @} */
/**
*
* @file xscugic.c
+* @addtogroup scugic_v2_1
+* @{
*
* Contains required functions for the XScuGic driver for the Interrupt
* Controller. See xscugic.h for a detailed description of the driver.
*Trigger = RegValue & XSCUGIC_INT_CFG_MASK;
}
+/** @} */
/**
*
* @file xscugic.h
+* @addtogroup scugic_v2_1
+* @{
+* @details
*
* The generic interrupt controller driver component.
*
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xscugic_hw.c
+* @addtogroup scugic_v2_1
+* @{
*
* This file contains low-level driver functions that can be used to access the
* device. The user should refer to the hardware device specification for more
*Trigger = RegValue & XSCUGIC_INT_CFG_MASK;
}
+/** @} */
/**
*
* @file xscugic_hw.h
+* @addtogroup scugic_v2_1
+* @{
*
* This header file contains identifiers and HW access functions (or
* macros) that can be used to access the device. The user should refer to the
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xscugic_intr.c
+* @addtogroup scugic_v2_1
+* @{
*
* This file contains the interrupt processing for the driver for the Xilinx
* Interrupt Controller. The interrupt processing is partitioned separately such
* Return from the interrupt. Change security domains could happen here.
*/
}
+/** @} */
/**
*
* @file xscugic_selftest.c
+* @addtogroup scugic_v2_1
+* @{
*
* Contains diagnostic self-test functions for the XScuGic driver.
* <pre>
return XST_SUCCESS;
}
+/** @} */
/**
*
* @file xscugic_sinit.c
+* @addtogroup scugic_v2_1
+* @{
*
* Contains static init functions for the XScuGic driver for the Interrupt
* Controller. See xscugic.h for a detailed description of the driver.
return CfgPtr;
}
+/** @} */
/**
*
* @file xscutimer.c
+* @addtogroup scutimer_v2_0
+* @{
*
* Contains the implementation of interface functions of the SCU Timer driver.
* See xscutimer.h for a description of the driver.
return (ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
}
+/** @} */
/**
*
* @file xscutimer.h
+* @addtogroup scutimer_v2_0
+* @{
+* @details
*
* The timer driver supports the Cortex A9 private timer.
*
#endif
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_0
+* @{
*
* This file contains the hardware interface to the Timer.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xscutimer_selftest.c
+* @addtogroup scutimer_v2_0
+* @{
*
* Contains diagnostic self-test functions for the XScuTimer driver.
*
return XST_SUCCESS;
}
+/** @} */
/**
*
* @file xscutimer_sinit.c
+* @addtogroup scutimer_v2_0
+* @{
*
* This file contains method for static initialization (compile-time) of the
* driver.
return (CfgPtr);
}
+/** @} */
/**
*
* @file xscuwdt.c
+* @addtogroup scuwdt_v2_0
+* @{
*
* Contains the implementation of interface functions of the XScuWdt driver.
* See xscuwdt.h for a description of the driver.
*/
InstancePtr->IsStarted = 0;
}
+/** @} */
/**
*
* @file xscuwdt.h
+* @addtogroup scuwdt_v2_0
+* @{
+* @details
*
* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
* watchdog timer hardware.
#endif
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_0
+* @{
*
* This file contains the hardware interface to the Xilinx SCU private Watch Dog
* Timer (XSCUWDT).
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xscuwdt_selftest.c
+* @addtogroup scuwdt_v2_0
+* @{
*
* Contains diagnostic self-test functions for the XScuWdt driver.
*
return XST_SUCCESS;
}
+/** @} */
/**
*
* @file xscuwdt_sinit.c
+* @addtogroup scuwdt_v2_0
+* @{
*
* This file contains method for static initialization (compile-time) of the
* driver.
return (CfgPtr);
}
+/** @} */
/**
*
* @file xsdps.c
+* @addtogroup sdps_v2_1
+* @{
*
* Contains the interface functions of the XSdPs driver.
* See xsdps.h for a detailed description of the device and driver.
}
+/** @} */
/**
*
* @file xsdps.h
+* @addtogroup sdps_v2_1
+* @{
+* @details
*
* This file contains the implementation of XSdPs driver.
* This driver is used initialize read from and write to the SD card.
#endif
#endif /* SD_H_ */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xsdps_hw.h
+* @addtogroup sdps_v2_1
+* @{
*
* This header file contains the identifiers and basic HW access driver
* functions (or macros) that can be used to access the device. Other driver
#endif
#endif /* SD_HW_H_ */
+/** @} */
/**
*
* @file xsdps_options.c
+* @addtogroup sdps_v2_1
+* @{
*
* Contains API's for changing the various options in host and card.
* See xsdps.h for a detailed description of the device and driver.
}
+/** @} */
/**
*
* @file xsdps_sinit.c
+* @addtogroup sdps_v2_1
+* @{
*
* The implementation of the XSdPs component's static initialization
* functionality.
return CfgPtr;
}
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xttcps.c
+* @addtogroup ttcps_v2_0
+* @{
*
* This file contains the implementation of the XTtcPs driver. This driver
* controls the operation of one timer counter in the Triple Timer Counter (TTC)
return;
}
+/** @} */
/**
*
* @file xttcps.h
+* @addtogroup ttcps_v2_0
+* @{
+* @details
*
* This is the driver for one 16-bit timer counter in the Triple Timer Counter
* (TTC) module in the Ps block.
#endif
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xttcps_hw.h
+* @addtogroup ttcps_v2_0
+* @{
*
* This file defines the hardware interface to one of the three timer counters
* in the Ps block.
}
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xttcps_options.c
+* @addtogroup ttcps_v2_0
+* @{
*
* This file contains functions to get or set option features for the device.
*
return OptionsFlag;
}
+/** @} */
/**
*
* @file xttcps_selftest.c
+* @addtogroup ttcps_v2_0
+* @{
*
* This file contains the implementation of self test function for the
* XTtcPs driver.
return XST_SUCCESS;
}
+/** @} */
/**
*
* @file xttcps_sinit.c
+* @addtogroup ttcps_v2_0
+* @{
*
* The implementation of the XTtcPs driver's static initialization functionality.
*
return CfgPtr;
}
+/** @} */
/**
*
* @file xuartps.c
+* @addtogroup uartps_v2_1
+* @{
*
* This file contains the implementation of the interface functions for XUartPs
* driver. Refer to the header file xuartps.h for more detailed information.
*/
Xil_AssertVoidAlways();
}
+/** @} */
/**
*
* @file xuartps.h
+* @addtogroup uartps_v2_1
+* @{
+* @details
*
* This driver supports the following features:
*
#endif
#endif /* end of protection macro */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xuartps_hw.c
+* @addtogroup uartps_v2_1
+* @{
*
*
* <pre>
}
+/** @} */
/**
*
* @file xuartps_hw.h
+* @addtogroup uartps_v2_1
+* @{
*
* This header file contains the hardware interface of an XUartPs device.
*
#endif
#endif /* end of protection macro */
+/** @} */
/**
*
* @file xuartps_intr.c
+* @addtogroup uartps_v2_1
+* @{
*
* This file contains the functions for interrupt handling
*
}
+/** @} */
/**
*
* @file xuartps_options.c
+* @addtogroup uartps_v2_1
+* @{
*
* The implementation of the options functions for the XUartPs driver.
*
(ModeRegister & XUARTPS_MR_PARITY_MASK) >>
XUARTPS_MR_PARITY_SHIFT;
}
+/** @} */
/**
*
* @file xuartps_selftest.c
+* @addtogroup uartps_v2_1
+* @{
*
* This file contains the self-test functions for the XUartPs driver.
*
return Status;
}
+/** @} */
/**
*
* @file xuartps_sinit.c
+* @addtogroup uartps_v2_1
+* @{
*
* The implementation of the XUartPs driver's static initialzation
* functionality.
return CfgPtr;
}
+/** @} */
/******************************************************************************/
/**
* @file xusbps.c
+* @addtogroup usbps_v2_1
+* @{
*
* The XUsbPs driver. Functions in this file are the minimum required
* functions for this driver. See xusbps.h for a detailed description of the
return XST_SUCCESS;
}
+/** @} */
/**
*
* @file xusbps.h
+* @addtogroup usbps_v2_1
+* @{
+* @details
*
* This file contains the implementation of the XUsbPs driver. It is the
* driver for an USB controller in DEVICE or HOST mode.
#endif
#endif /* XUSBPS_H */
+/** @} */
/******************************************************************************/
/**
* @file xusbps_endpoint.c
+* @addtogroup usbps_v2_1
+* @{
*
* Endpoint specific function implementations.
*
return XST_SUCCESS;
}
+/** @} */
/**
*
* @file xusbps_endpoint.h
+* @addtogroup usbps_v2_1
+* @{
*
* This is an internal file containung the definitions for endpoints. It is
* included by the xusbps_endpoint.c which is implementing the endpoint
#endif
#endif /* XUSBPS_ENDPOINT_H */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xusbps_hw.c
+* @addtogroup usbps_v2_1
+* @{
*
* The implementation of the XUsbPs interface reset functionality
*
+/** @} */
/**
*
* @file xusbps_hw.h
+* @addtogroup usbps_v2_1
+* @{
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the device. High-level driver functions
#endif
#endif /* XUSBPS_L_H */
+/** @} */
/******************************************************************************/
/**
* @file xusbps_intr.c
+* @addtogroup usbps_v2_1
+* @{
*
* This file contains the functions that are related to interrupt processing
* for the EPB USB driver.
}
+/** @} */
/**
*
* @file xusbps_sinit.c
+* @addtogroup usbps_v2_1
+* @{
*
* The implementation of the XUsbPs driver's static initialzation
* functionality.
return CfgPtr;
}
+/** @} */
/**
*
* @file xadcps.c
+* @addtogroup xadcps_v2_0
+* @{
*
* This file contains the driver API functions that can be used to access
* the XADC device.
}
+/** @} */
/**
*
* @file xadcps.h
+* @addtogroup xadcps_v2_0
+* @{
+* @details
*
* The XAdcPs driver supports the Xilinx XADC/ADC device.
*
#endif
#endif /* End of protection macro. */
+/** @} */
*\r
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-*XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
*\r
/**
*
* @file xadcps_hw.h
+* @addtogroup xadcps_v2_0
+* @{
*
* This header file contains identifiers and basic driver functions (or
* macros) that can be used to access the XADC device through the Device
#endif
#endif /* End of protection macro. */
+/** @} */
/**
*
* @file xadcps_intr.c
+* @addtogroup xadcps_v2_0
+* @{
*
* This file contains interrupt handling API functions of the XADC
* device.
RegValue);
}
+/** @} */
/**
*
* @file xadcps_selftest.c
+* @addtogroup xadcps_v2_0
+* @{
*
* This file contains a diagnostic self test function for the XAdcPs driver.
* The self test function does a simple read/write test of the Alarm Threshold
*/
return Status;
}
+/** @} */
/**
*
* @file xadcps_sinit.c
+* @addtogroup xadcps_v2_0
+* @{
*
* This file contains the implementation of the XAdcPs driver's static
* initialization functionality.
return CfgPtr;
}
+/** @} */
\r
- PARAMETER NAME = C:\E\Dev\workspaces\XilinxSDK\FreeRTOS_Demo\RTOSDemo_bsp\system.mss\r
-\r
PARAMETER VERSION = 2.2.0\r
\r
\r
/* Demo program include files. */\r
#include "StaticAllocation.h"\r
\r
+/* Exclude the entire file if configSUPPORT_STATIC_ALLOCATION is 0. */\r
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )\r
+\r
#define staticTASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
\r
/*\r
\r
return xReturn;\r
}\r
+/*-----------------------------------------------------------*/\r
\r
+/* Exclude the entire file if configSUPPORT_STATIC_ALLOCATION is 0. */\r
+#endif /* configSUPPORT_STATIC_ALLOCATION == 1 */\r
87: privileged Vs unprivileged linkage and placement. */\r
88: #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */\r
89: \r
-90: #if ( INCLUDE_xEventGroupSetBitFromISR == 1 ) && ( configUSE_TIMERS == 0 )\r
+90: #if ( INCLUDE_xEventGroupSetBitsFromISR == 1 ) && ( configUSE_TIMERS == 0 )\r
91: #error configUSE_TIMERS must be set to 1 to make the xEventGroupSetBitFromISR() function available.\r
92: #endif\r
93: \r
-94: #if ( INCLUDE_xEventGroupSetBitFromISR == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 0 )\r
+94: #if ( INCLUDE_xEventGroupSetBitsFromISR == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 0 )\r
95: #error INCLUDE_xTimerPendFunctionCall must also be set to one to make the xEventGroupSetBitFromISR() function available.\r
96: #endif\r
97: \r
*pusIdleTaskStackSize = configMINIMAL_STACK_SIZE; /* In words. NOT in bytes! */\r
}\r
/*-----------------------------------------------------------*/\r
-DummyTCB_t xTimerTaskTCB;\r
+\r
void vApplicationGetTimerTaskMemory( DummyTCB_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint16_t *pusTimerTaskStackSize )\r
{\r
/* The buffers used by the Timer/Daemon task must be static so they are\r
persistent, and so exist after this function returns. */\r
-//static DummyTCB_t xTimerTaskTCB;\r
+static DummyTCB_t xTimerTaskTCB;\r
static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];\r
\r
/* configUSE_STATIC_ALLOCATION is set to 1, so the application has the\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS\r
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET\r
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES\r
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#ifndef configSETUP_TICK_INTERRUPT\r
+ #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif /* configSETUP_TICK_INTERRUPT */\r
+\r
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0\r
+#endif\r
+\r
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+ /* Check the configuration. */\r
+ #if( configMAX_PRIORITIES > 32 )\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+ #endif\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+/* In case security extensions are implemented. */\r
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\r
+#endif\r
+\r
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in\r
+portmacro.h. */\r
+#ifndef configCLEAR_TICK_INTERRUPT\r
+ #define configCLEAR_TICK_INTERRUPT()\r
+#endif\r
+\r
+/* A critical section is exited when the critical section nesting count reaches\r
+this value. */\r
+#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )\r
+\r
+/* In all GICs 255 can be written to the priority mask register to unmask all\r
+(but the lowest) interrupt priority. */\r
+#define portUNMASK_VALUE ( 0xFFUL )\r
+\r
+/* Tasks are not created with a floating point context, but can be given a\r
+floating point context after they have been created. A variable is stored as\r
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\r
+does not have an FPU context, or any other value if the task does have an FPU\r
+context. */\r
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )\r
+\r
+/* Constants required to setup the initial task context. */\r
+#define portEL3 ( ( StackType_t ) 0x0c )\r
+#define portSP_ELx ( ( StackType_t ) 0x01 )\r
+#define portSP_EL0 ( ( StackType_t ) 0x00 )\r
+\r
+/* At the time of writing, the BSP only supports EL3. */\r
+#define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )\r
+\r
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary\r
+point is zero. */\r
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )\r
+\r
+/* Masks all bits in the APSR other than the mode bits. */\r
+#define portAPSR_MODE_BITS_MASK ( 0x0C )\r
+\r
+/* The I bit in the DAIF bits. */\r
+#define portDAIF_I ( 0x80 )\r
+\r
+/* Macro to unmask all interrupt priorities. */\r
+#define portCLEAR_INTERRUPT_MASK() \\r
+{ \\r
+ portDISABLE_INTERRUPTS(); \\r
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \\r
+ __asm volatile ( "DSB SY \n" \\r
+ "ISB SY \n" ); \\r
+ portENABLE_INTERRUPTS(); \\r
+}\r
+\r
+/* Hardware specifics used when sanity checking the configuration. */\r
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL\r
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
+#define portBIT_0_SET ( ( uint8_t ) 0x01 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts the first task executing. This function is necessarily written in\r
+ * assembly code so is implemented in portASM.s.\r
+ */\r
+extern void vPortRestoreTaskContext( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* A variable is used to keep track of the critical section nesting. This\r
+variable has to be stored as part of the task context and must be initialised to\r
+a non zero value to ensure interrupts don't inadvertently become unmasked before\r
+the scheduler starts. As it is stored as part of the task context it will\r
+automatically be set to 0 when the first task is started. */\r
+volatile uint64_t ullCriticalNesting = 9999ULL;\r
+\r
+/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero\r
+then floating point context must be saved and restored for the task. */\r
+uint64_t ullPortTaskHasFPUContext = pdFALSE;\r
+\r
+/* Set to 1 to pend a context switch from an ISR. */\r
+uint64_t ullPortYieldRequired = pdFALSE;\r
+\r
+/* Counts the interrupt nesting depth. A context switch is only performed if\r
+if the nesting depth is 0. */\r
+uint64_t ullPortInterruptNesting = 0;\r
+\r
+/* Used in the ASM code. */\r
+__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;\r
+__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;\r
+__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;\r
+__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+{\r
+ /* Setup the initial stack of the task. The stack is set exactly as\r
+ expected by the portRESTORE_CONTEXT() macro. */\r
+\r
+ /* First all the general purpose registers. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x0101010101010101ULL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x0303030303030303ULL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x0202020202020202ULL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x0505050505050505ULL; /* R5 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x0404040404040404ULL; /* R4 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x0707070707070707ULL; /* R7 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x0606060606060606ULL; /* R6 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x0909090909090909ULL; /* R9 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x0808080808080808ULL; /* R8 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x1111111111111111ULL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x1010101010101010ULL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x1313131313131313ULL; /* R13 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x1212121212121212ULL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x1515151515151515ULL; /* R15 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x1414141414141414ULL; /* R14 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x1717171717171717ULL; /* R17 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x1616161616161616ULL; /* R16 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x1919191919191919ULL; /* R19 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x1818181818181818ULL; /* R18 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2121212121212121ULL; /* R21 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2020202020202020ULL; /* R20 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2323232323232323ULL; /* R23 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2222222222222222ULL; /* R22 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2525252525252525ULL; /* R25 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2424242424242424ULL; /* R24 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2727272727272727ULL; /* R27 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2626262626262626ULL; /* R26 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2929292929292929ULL; /* R29 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x2828282828282828ULL; /* R28 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = portINITIAL_PSTATE;\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */\r
+ pxTopOfStack--;\r
+\r
+ /* The task will start with a critical nesting count of 0 as interrupts are\r
+ enabled. */\r
+ *pxTopOfStack = portNO_CRITICAL_NESTING;\r
+ pxTopOfStack--;\r
+\r
+ /* The task will start without a floating point context. A task that uses\r
+ the floating point hardware must call vPortTaskUsesFPU() before executing\r
+ any floating point instructions. */\r
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+uint32_t ulAPSR;\r
+\r
+ #if( configASSERT_DEFINED == 1 )\r
+ {\r
+ volatile uint32_t ulOriginalPriority;\r
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );\r
+ volatile uint8_t ucMaxPriorityValue;\r
+\r
+ /* Determine how many priority bits are implemented in the GIC.\r
+\r
+ Save the interrupt priority value that is about to be clobbered. */\r
+ ulOriginalPriority = *pucFirstUserPriorityRegister;\r
+\r
+ /* Determine the number of priority bits available. First write to\r
+ all possible bits. */\r
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
+\r
+ /* Read the value back to see how many bits stuck. */\r
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
+\r
+ /* Shift to the least significant bits. */\r
+ while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )\r
+ {\r
+ ucMaxPriorityValue >>= ( uint8_t ) 0x01;\r
+ }\r
+\r
+ /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read\r
+ value. */\r
+ configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );\r
+\r
+ /* Restore the clobbered interrupt priority register to its original\r
+ value. */\r
+ *pucFirstUserPriorityRegister = ulOriginalPriority;\r
+ }\r
+ #endif /* conifgASSERT_DEFINED */\r
+\r
+\r
+ /* At the time of writing, the BSP only supports EL3. */\r
+ __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );\r
+ ulAPSR &= portAPSR_MODE_BITS_MASK;\r
+ configASSERT( ulAPSR == portEL3 );\r
+\r
+ if( ulAPSR == portEL3 )\r
+ {\r
+ /* Only continue if the binary point value is set to its lowest possible\r
+ setting. See the comments in vPortValidateInterruptPriority() below for\r
+ more information. */\r
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\r
+\r
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )\r
+ {\r
+ /* Interrupts are turned off in the CPU itself to ensure a tick does\r
+ not execute while the scheduler is being started. Interrupts are\r
+ automatically turned back on in the CPU when the first task starts\r
+ executing. */\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ /* Start the timer that generates the tick ISR. */\r
+ configSETUP_TICK_INTERRUPT();\r
+\r
+ /* Start the first task executing. */\r
+ vPortRestoreTaskContext();\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( ullCriticalNesting == 1000ULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ /* Mask interrupts up to the max syscall interrupt priority. */\r
+ uxPortSetInterruptMask();\r
+\r
+ /* Now interrupts are disabled ullCriticalNesting can be accessed\r
+ directly. Increment ullCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ullCriticalNesting++;\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( ullCriticalNesting == 1ULL )\r
+ {\r
+ configASSERT( ullPortInterruptNesting == 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ullCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as the critical section is being\r
+ exited. */\r
+ ullCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then all interrupt\r
+ priorities must be re-enabled. */\r
+ if( ullCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Critical nesting has reached zero so all interrupt priorities\r
+ should be unmasked. */\r
+ portCLEAR_INTERRUPT_MASK();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void FreeRTOS_Tick_Handler( void )\r
+{\r
+ /* Must be the lowest possible priority. */\r
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\r
+\r
+ /* Interrupts should not be enabled before this point. */\r
+ #if( configASSERT_DEFINED == 1 )\r
+ {\r
+ uint32_t ulMaskBits;\r
+\r
+ __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) );\r
+ configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );\r
+ }\r
+ #endif /* configASSERT_DEFINED */\r
+\r
+ /* Set interrupt mask before altering scheduler structures. The tick\r
+ handler runs at the lowest priority, so interrupts cannot already be masked,\r
+ so there is no need to save and restore the current mask value. It is\r
+ necessary to turn off interrupts in the CPU itself while the ICCPMR is being\r
+ updated. */\r
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
+ __asm volatile ( "dsb sy \n"\r
+ "isb sy \n" );\r
+\r
+ /* Ok to enable interrupts after the interrupt source has been cleared. */\r
+ configCLEAR_TICK_INTERRUPT();\r
+ portENABLE_INTERRUPTS();\r
+\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ ullPortYieldRequired = pdTRUE;\r
+ }\r
+\r
+ /* Ensure all interrupt priorities are active again. */\r
+ portCLEAR_INTERRUPT_MASK();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortTaskUsesFPU( void )\r
+{\r
+ /* A task is registering the fact that it needs an FPU context. Set the\r
+ FPU flag (which is saved as part of the task context). */\r
+ ullPortTaskHasFPUContext = pdTRUE;\r
+\r
+ /* Consider initialising the FPSR here - but probably not necessary in\r
+ AArch64. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )\r
+{\r
+ if( uxNewMaskValue == pdFALSE )\r
+ {\r
+ portCLEAR_INTERRUPT_MASK();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+UBaseType_t uxPortSetInterruptMask( void )\r
+{\r
+uint32_t ulReturn;\r
+\r
+ /* Interrupt in the CPU must be turned off while the ICCPMR is being\r
+ updated. */\r
+ portDISABLE_INTERRUPTS();\r
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )\r
+ {\r
+ /* Interrupts were already masked. */\r
+ ulReturn = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ ulReturn = pdFALSE;\r
+ portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
+ __asm volatile ( "dsb sy \n"\r
+ "isb sy \n" );\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ return ulReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+ void vPortValidateInterruptPriority( void )\r
+ {\r
+ /* The following assertion will fail if a service routine (ISR) for\r
+ an interrupt that has been assigned a priority above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
+ from interrupts that have been assigned a priority at or below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Numerically low interrupt priority numbers represent logically high\r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
+ interrupt entry is as fast and simple as possible. */\r
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\r
+\r
+ /* Priority grouping: The interrupt controller (GIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
+ define the interrupt's pre-emption priority bits and bits that define\r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
+ to be pre-emption priority bits. The following assertion will fail if\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ The priority grouping is configured by the GIC's binary point register\r
+ (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest\r
+ possible value (which may be above 0). */\r
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\r
+ }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+ .text\r
+\r
+ /* Variables and functions. */\r
+ .extern ullMaxAPIPriorityMask\r
+ .extern pxCurrentTCB\r
+ .extern vTaskSwitchContext\r
+ .extern vApplicationIRQHandler\r
+ .extern ullPortInterruptNesting\r
+ .extern ullPortTaskHasFPUContext\r
+ .extern ullCriticalNesting\r
+ .extern ullPortYieldRequired\r
+ .extern ullICCEOIR\r
+ .extern ullICCIAR\r
+ .extern _freertos_vector_table\r
+\r
+ .global FreeRTOS_IRQ_Handler\r
+ .global FreeRTOS_SWI_Handler\r
+ .global vPortRestoreTaskContext\r
+\r
+\r
+.macro portSAVE_CONTEXT\r
+\r
+ /* Switch to use the EL0 stack pointer. */\r
+ MSR SPSEL, #0\r
+\r
+ /* Save the entire context. */\r
+ STP X0, X1, [SP, #-0x10]!\r
+ STP X2, X3, [SP, #-0x10]!\r
+ STP X4, X5, [SP, #-0x10]!\r
+ STP X6, X7, [SP, #-0x10]!\r
+ STP X8, X9, [SP, #-0x10]!\r
+ STP X10, X11, [SP, #-0x10]!\r
+ STP X12, X13, [SP, #-0x10]!\r
+ STP X14, X15, [SP, #-0x10]!\r
+ STP X16, X17, [SP, #-0x10]!\r
+ STP X18, X19, [SP, #-0x10]!\r
+ STP X20, X21, [SP, #-0x10]!\r
+ STP X22, X23, [SP, #-0x10]!\r
+ STP X24, X25, [SP, #-0x10]!\r
+ STP X26, X27, [SP, #-0x10]!\r
+ STP X28, X29, [SP, #-0x10]!\r
+ STP X30, XZR, [SP, #-0x10]!\r
+\r
+ /* Save the SPSR. */\r
+ MRS X3, SPSR_EL3\r
+\r
+ /* Save the ELR. */\r
+ MRS X2, ELR_EL3\r
+\r
+ STP X2, X3, [SP, #-0x10]!\r
+\r
+ /* Save the critical section nesting depth. */\r
+ LDR X0, ullCriticalNestingConst\r
+ LDR X3, [X0]\r
+\r
+ /* Save the FPU context indicator. */\r
+ LDR X0, ullPortTaskHasFPUContextConst\r
+ LDR X2, [X0]\r
+\r
+ /* Save the FPU context, if any (32 128-bit registers). */\r
+ CMP X2, #0\r
+ B.EQ 1f\r
+ STP Q0, Q1, [SP,#-0x20]!\r
+ STP Q2, Q3, [SP,#-0x20]!\r
+ STP Q4, Q5, [SP,#-0x20]!\r
+ STP Q6, Q7, [SP,#-0x20]!\r
+ STP Q8, Q9, [SP,#-0x20]!\r
+ STP Q10, Q11, [SP,#-0x20]!\r
+ STP Q12, Q13, [SP,#-0x20]!\r
+ STP Q14, Q15, [SP,#-0x20]!\r
+ STP Q16, Q17, [SP,#-0x20]!\r
+ STP Q18, Q19, [SP,#-0x20]!\r
+ STP Q20, Q21, [SP,#-0x20]!\r
+ STP Q22, Q23, [SP,#-0x20]!\r
+ STP Q24, Q25, [SP,#-0x20]!\r
+ STP Q26, Q27, [SP,#-0x20]!\r
+ STP Q28, Q29, [SP,#-0x20]!\r
+ STP Q30, Q31, [SP,#-0x20]!\r
+\r
+1:\r
+ /* Store the critical nesting count and FPU context indicator. */\r
+ STP X2, X3, [SP, #-0x10]!\r
+\r
+ LDR X0, pxCurrentTCBConst\r
+ LDR X1, [X0]\r
+ MOV X0, SP /* Move SP into X0 for saving. */\r
+ STR X0, [X1]\r
+\r
+ /* Switch to use the ELx stack pointer. */\r
+ MSR SPSEL, #1\r
+\r
+ .endm\r
+\r
+; /**********************************************************************/\r
+\r
+.macro portRESTORE_CONTEXT\r
+\r
+ /* Switch to use the EL0 stack pointer. */\r
+ MSR SPSEL, #0\r
+\r
+ /* Set the SP to point to the stack of the task being restored. */\r
+ LDR X0, pxCurrentTCBConst\r
+ LDR X1, [X0]\r
+ LDR X0, [X1]\r
+ MOV SP, X0\r
+\r
+ LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */\r
+\r
+ /* Set the PMR register to be correct for the current critical nesting\r
+ depth. */\r
+ LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */\r
+ MOV X1, #255 /* X1 holds the unmask value. */\r
+ LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */\r
+ CMP X3, #0\r
+ LDR X5, [X4] /* X5 holds the address of the ICCPMR register. */\r
+ B.EQ 1f\r
+ LDR X6, ullMaxAPIPriorityMaskConst\r
+ LDR X1, [X6] /* X1 holds the mask value. */\r
+1:\r
+ STR W1, [X5] /* Write the mask value to ICCPMR. */\r
+ DSB SY /* _RB_Barriers probably not required here. */\r
+ ISB SY\r
+ STR X3, [X0] /* Restore the task's critical nesting count. */\r
+\r
+ /* Restore the FPU context indicator. */\r
+ LDR X0, ullPortTaskHasFPUContextConst\r
+ STR X2, [X0]\r
+\r
+ /* Restore the FPU context, if any. */\r
+ CMP X2, #0\r
+ B.EQ 1f\r
+ LDP Q30, Q31, [SP], #0x20\r
+ LDP Q28, Q29, [SP], #0x20\r
+ LDP Q26, Q27, [SP], #0x20\r
+ LDP Q24, Q25, [SP], #0x20\r
+ LDP Q22, Q23, [SP], #0x20\r
+ LDP Q20, Q21, [SP], #0x20\r
+ LDP Q18, Q19, [SP], #0x20\r
+ LDP Q16, Q17, [SP], #0x20\r
+ LDP Q14, Q15, [SP], #0x20\r
+ LDP Q12, Q13, [SP], #0x20\r
+ LDP Q10, Q11, [SP], #0x20\r
+ LDP Q8, Q9, [SP], #0x20\r
+ LDP Q6, Q7, [SP], #0x20\r
+ LDP Q4, Q5, [SP], #0x20\r
+ LDP Q2, Q3, [SP], #0x20\r
+ LDP Q0, Q1, [SP], #0x20\r
+1:\r
+ LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */\r
+\r
+ /* Restore the SPSR. */\r
+ MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */\r
+\r
+ /* Restore the ELR. */\r
+ MSR ELR_EL3, X2\r
+\r
+ LDP X30, XZR, [SP], #0x10\r
+ LDP X28, X29, [SP], #0x10\r
+ LDP X26, X27, [SP], #0x10\r
+ LDP X24, X25, [SP], #0x10\r
+ LDP X22, X23, [SP], #0x10\r
+ LDP X20, X21, [SP], #0x10\r
+ LDP X18, X19, [SP], #0x10\r
+ LDP X16, X17, [SP], #0x10\r
+ LDP X14, X15, [SP], #0x10\r
+ LDP X12, X13, [SP], #0x10\r
+ LDP X10, X11, [SP], #0x10\r
+ LDP X8, X9, [SP], #0x10\r
+ LDP X6, X7, [SP], #0x10\r
+ LDP X4, X5, [SP], #0x10\r
+ LDP X2, X3, [SP], #0x10\r
+ LDP X0, X1, [SP], #0x10\r
+\r
+ /* Switch to use the ELx stack pointer. _RB_ Might not be required. */\r
+ MSR SPSEL, #1\r
+\r
+ ERET\r
+\r
+ .endm\r
+\r
+\r
+/******************************************************************************\r
+ * FreeRTOS_SWI_Handler handler is used to perform a context switch.\r
+ *****************************************************************************/\r
+.align 8\r
+.type FreeRTOS_SWI_Handler, %function\r
+FreeRTOS_SWI_Handler:\r
+ /* Save the context of the current task and select a new task to run. */\r
+ portSAVE_CONTEXT\r
+\r
+ MRS X0, ESR_EL3\r
+ LSR X1, X0, #26\r
+ CMP X1, #0x17 /* 0x17 = SMC instruction. */\r
+ B.NE FreeRTOS_Abort\r
+ BL vTaskSwitchContext\r
+\r
+ portRESTORE_CONTEXT\r
+\r
+FreeRTOS_Abort:\r
+ /* Full ESR is in X0, exception class code is in X1. */\r
+ B .\r
+\r
+/******************************************************************************\r
+ * vPortRestoreTaskContext is used to start the scheduler.\r
+ *****************************************************************************/\r
+.align 8\r
+.type vPortRestoreTaskContext, %function\r
+vPortRestoreTaskContext:\r
+.set freertos_vector_base, _freertos_vector_table\r
+\r
+ /* Install the FreeRTOS interrupt handlers. */\r
+ LDR X1, =freertos_vector_base\r
+ MSR VBAR_EL3, X1\r
+ DSB SY\r
+ ISB SY\r
+\r
+ /* Start the first task. */\r
+ portRESTORE_CONTEXT\r
+\r
+\r
+/******************************************************************************\r
+ * FreeRTOS_IRQ_Handler handles IRQ entry and exit.\r
+ *****************************************************************************/\r
+.align 8\r
+.type FreeRTOS_IRQ_Handler, %function\r
+FreeRTOS_IRQ_Handler:\r
+ /* Save volatile registers. */\r
+ STP X0, X1, [SP, #-0x10]!\r
+ STP X2, X3, [SP, #-0x10]!\r
+ STP X4, X5, [SP, #-0x10]!\r
+ STP X6, X7, [SP, #-0x10]!\r
+ STP X8, X9, [SP, #-0x10]!\r
+ STP X10, X11, [SP, #-0x10]!\r
+ STP X12, X13, [SP, #-0x10]!\r
+ STP X14, X15, [SP, #-0x10]!\r
+ STP X16, X17, [SP, #-0x10]!\r
+ STP X18, X19, [SP, #-0x10]!\r
+ STP X29, X30, [SP, #-0x10]!\r
+\r
+ /* Save the SPSR and ELR. */\r
+ MRS X3, SPSR_EL3\r
+ MRS X2, ELR_EL3\r
+ STP X2, X3, [SP, #-0x10]!\r
+\r
+ /* Increment the interrupt nesting counter. */\r
+ LDR X5, ullPortInterruptNestingConst\r
+ LDR X1, [X5] /* Old nesting count in X1. */\r
+ ADD X6, X1, #1\r
+ STR X6, [X5] /* Address of nesting count variable in X5. */\r
+\r
+ /* Maintain the interrupt nesting information across the function call. */\r
+ STP X1, X5, [SP, #-0x10]!\r
+\r
+ /* Read value from the interrupt acknowledge register, which is stored in W0\r
+ for future parameter and interrupt clearing use. */\r
+ LDR X2, ullICCIARConst\r
+ LDR X3, [X2]\r
+ LDR W0, [X3] /* ICCIAR in W0 as parameter. */\r
+\r
+ /* Maintain the ICCIAR value across the function call. */\r
+ STP X0, X1, [SP, #-0x10]!\r
+\r
+ /* Call the C handler. */\r
+ BL vApplicationIRQHandler\r
+\r
+ /* Disable interrupts. */\r
+ MSR DAIFSET, #2\r
+ DSB SY\r
+ ISB SY\r
+\r
+ /* Restore the ICCIAR value. */\r
+ LDP X0, X1, [SP], #0x10\r
+\r
+ /* End IRQ processing by writing ICCIAR to the EOI register. */\r
+ LDR X4, ullICCEOIRConst\r
+ LDR X4, [X4]\r
+ STR W0, [X4]\r
+\r
+ /* Restore the critical nesting count. */\r
+ LDP X1, X5, [SP], #0x10\r
+ STR X1, [X5]\r
+\r
+ /* Has interrupt nesting unwound? */\r
+ CMP X1, #0\r
+ B.NE Exit_IRQ_No_Context_Switch\r
+\r
+ /* Is a context switch required? */\r
+ LDR X0, ullPortYieldRequiredConst\r
+ LDR X1, [X0]\r
+ CMP X1, #0\r
+ B.EQ Exit_IRQ_No_Context_Switch\r
+\r
+ /* Reset ullPortYieldRequired to 0. */\r
+ MOV X2, #0\r
+ STR X2, [X0]\r
+\r
+ /* Restore volatile registers. */\r
+ LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */\r
+ MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */\r
+ MSR ELR_EL3, X4\r
+ DSB SY\r
+ ISB SY\r
+\r
+ LDP X29, X30, [SP], #0x10\r
+ LDP X18, X19, [SP], #0x10\r
+ LDP X16, X17, [SP], #0x10\r
+ LDP X14, X15, [SP], #0x10\r
+ LDP X12, X13, [SP], #0x10\r
+ LDP X10, X11, [SP], #0x10\r
+ LDP X8, X9, [SP], #0x10\r
+ LDP X6, X7, [SP], #0x10\r
+ LDP X4, X5, [SP], #0x10\r
+ LDP X2, X3, [SP], #0x10\r
+ LDP X0, X1, [SP], #0x10\r
+\r
+ /* Save the context of the current task and select a new task to run. */\r
+ portSAVE_CONTEXT\r
+ BL vTaskSwitchContext\r
+ portRESTORE_CONTEXT\r
+\r
+Exit_IRQ_No_Context_Switch:\r
+ /* Restore volatile registers. */\r
+ LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */\r
+ MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */\r
+ MSR ELR_EL3, X4\r
+ DSB SY\r
+ ISB SY\r
+\r
+ LDP X29, X30, [SP], #0x10\r
+ LDP X18, X19, [SP], #0x10\r
+ LDP X16, X17, [SP], #0x10\r
+ LDP X14, X15, [SP], #0x10\r
+ LDP X12, X13, [SP], #0x10\r
+ LDP X10, X11, [SP], #0x10\r
+ LDP X8, X9, [SP], #0x10\r
+ LDP X6, X7, [SP], #0x10\r
+ LDP X4, X5, [SP], #0x10\r
+ LDP X2, X3, [SP], #0x10\r
+ LDP X0, X1, [SP], #0x10\r
+\r
+ ERET\r
+\r
+\r
+\r
+\r
+.align 8\r
+pxCurrentTCBConst: .dword pxCurrentTCB\r
+ullCriticalNestingConst: .dword ullCriticalNesting\r
+ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext\r
+\r
+ullICCPMRConst: .dword ullICCPMR\r
+ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask\r
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler\r
+ullPortInterruptNestingConst: .dword ullPortInterruptNesting\r
+ullPortYieldRequiredConst: .dword ullPortYieldRequired\r
+ullICCIARConst: .dword ullICCIAR\r
+ullICCEOIRConst: .dword ullICCEOIR\r
+\r
+\r
+\r
+.end\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE size_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef portBASE_TYPE BaseType_t;\r
+typedef uint64_t UBaseType_t;\r
+\r
+typedef uint64_t TickType_t;\r
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )\r
+\r
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+not need to be guarded with a critical section. */\r
+#define portTICK_TYPE_IS_ATOMIC 1\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 16\r
+#define portPOINTER_SIZE_TYPE uint64_t\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+\r
+/* Called at the end of an ISR that can cause a context switch. */\r
+#define portEND_SWITCHING_ISR( xSwitchRequired )\\r
+{ \\r
+extern uint64_t ullPortYieldRequired; \\r
+ \\r
+ if( xSwitchRequired != pdFALSE ) \\r
+ { \\r
+ ullPortYieldRequired = pdTRUE; \\r
+ } \\r
+}\r
+\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+#define portYIELD() __asm volatile ( "SMC 0" )\r
+\r
+/*-----------------------------------------------------------\r
+ * Critical section control\r
+ *----------------------------------------------------------*/\r
+\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+extern UBaseType_t uxPortSetInterruptMask( void );\r
+extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );\r
+extern void vPortInstallFreeRTOSVectorTable( void );\r
+\r
+#define portDISABLE_INTERRUPTS() \\r
+ __asm volatile ( "MSR DAIFSET, #2" ); \\r
+ __asm volatile ( "DSB SY" ); \\r
+ __asm volatile ( "ISB SY" );\r
+\r
+#define portENABLE_INTERRUPTS() \\r
+ __asm volatile ( "MSR DAIFCLR, #2" ); \\r
+ __asm volatile ( "DSB SY" ); \\r
+ __asm volatile ( "ISB SY" );\r
+\r
+\r
+/* These macros do not globally disable/enable interrupts. They do mask off\r
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\r
+#define portENTER_CRITICAL() vPortEnterCritical();\r
+#define portEXIT_CRITICAL() vPortExitCritical();\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. These are\r
+not required for this port but included in case common demo code that uses these\r
+macros is used. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+/* Prototype of the FreeRTOS tick handler. This must be installed as the\r
+handler for whichever peripheral is used to generate the RTOS tick. */\r
+void FreeRTOS_Tick_Handler( void );\r
+\r
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\r
+before any floating point instructions are executed. */\r
+void vPortTaskUsesFPU( void );\r
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\r
+\r
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\r
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\r
+\r
+/* Architecture specific optimisations. */\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+ /* Store/clear the ready priorities in a bit map. */\r
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+ /*-----------------------------------------------------------*/\r
+\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+#ifdef configASSERT\r
+ void vPortValidateInterruptPriority( void );\r
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()\r
+#endif /* configASSERT */\r
+\r
+#define portNOP() __asm volatile( "NOP" )\r
+#define portINLINE __inline\r
+\r
+#ifdef __cplusplus\r
+ } /* extern C */\r
+#endif\r
+\r
+\r
+/* The number of bits to shift for an interrupt priority is dependent on the\r
+number of bits implemented by the interrupt controller. */\r
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16\r
+ #define portPRIORITY_SHIFT 4\r
+ #define portMAX_BINARY_POINT_VALUE 3\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32\r
+ #define portPRIORITY_SHIFT 3\r
+ #define portMAX_BINARY_POINT_VALUE 2\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64\r
+ #define portPRIORITY_SHIFT 2\r
+ #define portMAX_BINARY_POINT_VALUE 1\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128\r
+ #define portPRIORITY_SHIFT 1\r
+ #define portMAX_BINARY_POINT_VALUE 0\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256\r
+ #define portPRIORITY_SHIFT 0\r
+ #define portMAX_BINARY_POINT_VALUE 0\r
+#else\r
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware\r
+#endif\r
+\r
+/* Interrupt controller access addresses. */\r
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )\r
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )\r
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )\r
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )\r
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )\r
+\r
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )\r
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )\r
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )\r
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )\r
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )\r
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )\r
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
projects / freertos / commitdiff