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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xgpiops_hw.c
  36 * @addtogroup gpiops_v2_1
  37 * @{
  38 *
  39 * This file contains low level GPIO functions.
  40 *
  41 * <pre>
  42 * MODIFICATION HISTORY:
  43 *
  44 * Ver   Who  Date     Changes
  45 * ----- ---- -------- -----------------------------------------------
  46 * 1.02a hk   08/22/13 First Release
  47 *
  48 * </pre>
  49 *
  50 ******************************************************************************/
  51
  52 /***************************** Include Files *********************************/
  53
  54 #include "xgpiops_hw.h"
  55 #include "xgpiops.h"
  56
  57 /************************** Constant Definitions *****************************/
  58
  59 /**************************** Type Definitions *******************************/
  60
  61 /***************** Macros (Inline Functions) Definitions *********************/
  62
  63 /************************** Variable Definitions *****************************/
  64
  65 /************************** Function Prototypes ******************************/
  66
  67
  68 /*****************************************************************************/
  69 /*
  70 *
  71 * This function resets the GPIO module by writing reset values to
  72 * all registers
  73 *
  74 * @param        Base address of GPIO module
  75 *
  76 * @return       None
  77 *
  78 * @note         None.
  79 *
  80 ******************************************************************************/
  81 void XGpioPs_ResetHw(u32 BaseAddress)
  82 {
  83         u32 BankCount;
  84
  85         /*
  86          * Write reset values to all mask data registers
  87          */
  88         for(BankCount = 2; BankCount < XGPIOPS_MAX_BANKS; BankCount++) {
  89
  90                 XGpioPs_WriteReg(BaseAddress,
  91                                 ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
  92                                  XGPIOPS_DATA_LSW_OFFSET), 0x0);
  93                 XGpioPs_WriteReg(BaseAddress,
  94                                 ((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
  95                                  XGPIOPS_DATA_MSW_OFFSET), 0x0);
  96         }
  97         /*
  98          * Write reset values to all output data registers
  99          */
 100         for(BankCount = 2; BankCount < XGPIOPS_MAX_BANKS; BankCount++) {
 101
 102                 XGpioPs_WriteReg(BaseAddress,
 103                                 ((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
 104                                  XGPIOPS_DATA_OFFSET), 0x0);
 105         }
 106
 107         /*
 108          * Reset all registers of all 4 banks
 109          */
 110         for(BankCount = 0; BankCount < XGPIOPS_MAX_BANKS; BankCount++) {
 111
 112                 XGpioPs_WriteReg(BaseAddress,
 113                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 114                                  XGPIOPS_DIRM_OFFSET), 0x0);
 115                 XGpioPs_WriteReg(BaseAddress,
 116                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 117                                  XGPIOPS_OUTEN_OFFSET), 0x0);
 118                 XGpioPs_WriteReg(BaseAddress,
 119                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 120                                  XGPIOPS_INTMASK_OFFSET), 0x0);
 121                 XGpioPs_WriteReg(BaseAddress,
 122                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 123                                  XGPIOPS_INTEN_OFFSET), 0x0);
 124                 XGpioPs_WriteReg(BaseAddress,
 125                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 126                                  XGPIOPS_INTDIS_OFFSET), 0x0);
 127                 XGpioPs_WriteReg(BaseAddress,
 128                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 129                                  XGPIOPS_INTSTS_OFFSET), 0x0);
 130                 XGpioPs_WriteReg(BaseAddress,
 131                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 132                                  XGPIOPS_INTPOL_OFFSET), 0x0);
 133                 XGpioPs_WriteReg(BaseAddress,
 134                                 ((BankCount * XGPIOPS_REG_MASK_OFFSET) +
 135                                  XGPIOPS_INTANY_OFFSET), 0x0);
 136         }
 137
 138         /*
 139          * Bank 0 Int type
 140          */
 141         XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
 142                         XGPIOPS_INTTYPE_BANK0_RESET);
 143         /*
 144          * Bank 1 Int type
 145          */
 146         XGpioPs_WriteReg(BaseAddress,
 147                         (XGPIOPS_REG_MASK_OFFSET + XGPIOPS_INTTYPE_OFFSET),
 148                         XGPIOPS_INTTYPE_BANK1_RESET);
 149         /*
 150          * Bank 2 Int type
 151          */
 152         XGpioPs_WriteReg(BaseAddress,
 153                         ((2*XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
 154                         XGPIOPS_INTTYPE_BANK2_RESET);
 155         /*
 156          * Bank 3 Int type
 157          */
 158         XGpioPs_WriteReg(BaseAddress,
 159                         ((3*XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
 160                         XGPIOPS_INTTYPE_BANK3_RESET);
 161
 162 }
 163
 164
 165 /** @} */