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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup scugic_v2_1
39 * This header file contains identifiers and HW access functions (or
40 * macros) that can be used to access the device. The user should refer to the
41 * hardware device specification for more details of the device operation.
42 * The driver functions/APIs are defined in xscugic.h.
44 * This GIC device has two parts, a distributor and CPU interface(s). Each part
45 * has separate register definition sections.
49 * MODIFICATION HISTORY:
51 * Ver Who Date Changes
52 * ----- ---- -------- -----------------------------------------------------
53 * 1.00a drg 01/19/10 First release
54 * 1.01a sdm 11/09/11 "xil_exception.h" added as include.
55 * Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
56 * added to enable or disable interrupts based on
57 * Distributor Register base address. Normally users use
58 * XScuGic instance and call XScuGic_Enable or
59 * XScuGic_Disable to enable/disable interrupts. These
60 * new macros are provided when user does not want to
61 * use an instance pointer but still wants to enable or
63 * Function prototypes for functions (present in newly
64 * added file xscugic_hw.c) are added.
65 * 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
67 * 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
68 * XScuGic_SetPriTrigTypeByDistAddr and
69 * XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
73 ******************************************************************************/
75 #ifndef XSCUGIC_HW_H /* prevent circular inclusions */
76 #define XSCUGIC_HW_H /* by using protection macros */
82 /***************************** Include Files *********************************/
84 #include "xil_types.h"
85 #include "xil_assert.h"
87 #include "xil_exception.h"
89 /************************** Constant Definitions *****************************/
92 * The maximum number of interrupts supported by the hardware.
94 #define XSCUGIC_MAX_NUM_INTR_INPUTS 95
97 * The maximum priority value that can be used in the GIC.
99 #define XSCUGIC_MAX_INTR_PRIO_VAL 248
100 #define XSCUGIC_INTR_PRIO_MASK 0xF8
102 /** @name Distributor Interface Register Map
104 * Define the offsets from the base address for all Distributor registers of
105 * the interrupt controller, some registers may be reserved in the hardware
109 #define XSCUGIC_DIST_EN_OFFSET 0x00000000 /**< Distributor Enable
111 #define XSCUGIC_IC_TYPE_OFFSET 0x00000004 /**< Interrupt Controller
113 #define XSCUGIC_DIST_IDENT_OFFSET 0x00000008 /**< Implementor ID
115 #define XSCUGIC_SECURITY_OFFSET 0x00000080 /**< Interrupt Security
117 #define XSCUGIC_ENABLE_SET_OFFSET 0x00000100 /**< Enable Set
119 #define XSCUGIC_DISABLE_OFFSET 0x00000180 /**< Enable Clear Register */
120 #define XSCUGIC_PENDING_SET_OFFSET 0x00000200 /**< Pending Set
122 #define XSCUGIC_PENDING_CLR_OFFSET 0x00000280 /**< Pending Clear
124 #define XSCUGIC_ACTIVE_OFFSET 0x00000300 /**< Active Status Register */
125 #define XSCUGIC_PRIORITY_OFFSET 0x00000400 /**< Priority Level Register */
126 #define XSCUGIC_SPI_TARGET_OFFSET 0x00000800 /**< SPI Target
127 Register 0x800-0x8FB */
128 #define XSCUGIC_INT_CFG_OFFSET 0x00000C00 /**< Interrupt Configuration
129 Register 0xC00-0xCFC */
130 #define XSCUGIC_PPI_STAT_OFFSET 0x00000D00 /**< PPI Status Register */
131 #define XSCUGIC_SPI_STAT_OFFSET 0x00000D04 /**< SPI Status Register
133 #define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80 /**< AHB Configuration
135 #define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00 /**< Software Triggered
136 Interrupt Register */
137 #define XSCUGIC_PERPHID_OFFSET 0x00000FD0 /**< Peripheral ID Reg */
138 #define XSCUGIC_PCELLID_OFFSET 0x00000FF0 /**< Pcell ID Register */
141 /** @name Distributor Enable Register
142 * Controls if the distributor response to external interrupt inputs.
145 #define XSCUGIC_EN_INT_MASK 0x00000001 /**< Interrupt In Enable */
148 /** @name Interrupt Controller Type Register
151 #define XSCUGIC_LSPI_MASK 0x0000F800 /**< Number of Lockable
154 #define XSCUGIC_DOMAIN_MASK 0x00000400 /**< Number os Security domains*/
155 #define XSCUGIC_CPU_NUM_MASK 0x000000E0 /**< Number of CPU Interfaces */
156 #define XSCUGIC_NUM_INT_MASK 0x0000001F /**< Number of Interrupt IDs */
159 /** @name Implementor ID Register
160 * Implementor and revision information.
163 #define XSCUGIC_REV_MASK 0x00FFF000 /**< Revision Number */
164 #define XSCUGIC_IMPL_MASK 0x00000FFF /**< Implementor */
167 /** @name Interrupt Security Registers
168 * Each bit controls the security level of an interrupt, either secure or non
169 * secure. These registers can only be accessed using secure read and write.
170 * There are registers for each of the CPU interfaces at offset 0x080. A
171 * register set for the SPI interrupts is available to all CPU interfaces.
172 * There are up to 32 of these registers staring at location 0x084.
175 #define XSCUGIC_INT_NS_MASK 0x00000001 /**< Each bit corresponds to an
179 /** @name Enable Set Register
180 * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
181 * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
183 * There are registers for each of the CPU interfaces at offset 0x100. With up
184 * to 8 registers aliased to the same address. A register set for the SPI
185 * interrupts is available to all CPU interfaces.
186 * There are up to 32 of these registers staring at location 0x104.
189 #define XSCUGIC_INT_EN_MASK 0x00000001 /**< Each bit corresponds to an
193 /** @name Enable Clear Register
194 * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
195 * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
196 * sets the corresponding bit to 0.
197 * There are registers for each of the CPU interfaces at offset 0x180. With up
198 * to 8 registers aliased to the same address.
199 * A register set for the SPI interrupts is available to all CPU interfaces.
200 * There are up to 32 of these registers staring at location 0x184.
203 #define XSCUGIC_INT_CLR_MASK 0x00000001 /**< Each bit corresponds to an
207 /** @name Pending Set Register
208 * Each bit controls the Pending or Active and Pending state of an interrupt, a
209 * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
210 * an interrupt to the pending state.
211 * There are registers for each of the CPU interfaces at offset 0x200. With up
212 * to 8 registers aliased to the same address.
213 * A register set for the SPI interrupts is available to all CPU interfaces.
214 * There are up to 32 of these registers staring at location 0x204.
217 #define XSCUGIC_PEND_SET_MASK 0x00000001 /**< Each bit corresponds to an
221 /** @name Pending Clear Register
222 * Each bit can clear the Pending or Active and Pending state of an interrupt, a
223 * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
224 * clears the pending state of an interrupt.
225 * There are registers for each of the CPU interfaces at offset 0x280. With up
226 * to 8 registers aliased to the same address.
227 * A register set for the SPI interrupts is available to all CPU interfaces.
228 * There are up to 32 of these registers staring at location 0x284.
231 #define XSCUGIC_PEND_CLR_MASK 0x00000001 /**< Each bit corresponds to an
235 /** @name Active Status Register
236 * Each bit provides the Active status of an interrupt, a
237 * 0 is not Active, a 1 is Active. This is a read only register.
238 * There are registers for each of the CPU interfaces at offset 0x300. With up
239 * to 8 registers aliased to each address.
240 * A register set for the SPI interrupts is available to all CPU interfaces.
241 * There are up to 32 of these registers staring at location 0x380.
244 #define XSCUGIC_ACTIVE_MASK 0x00000001 /**< Each bit corresponds to an
248 /** @name Priority Level Register
249 * Each byte in a Priority Level Register sets the priority level of an
250 * interrupt. Reading the register provides the priority level of an interrupt.
251 * There are registers for each of the CPU interfaces at offset 0x400 through
252 * 0x41C. With up to 8 registers aliased to each address.
253 * 0 is highest priority, 0xFF is lowest.
254 * A register set for the SPI interrupts is available to all CPU interfaces.
255 * There are up to 255 of these registers staring at location 0x420.
258 #define XSCUGIC_PRIORITY_MASK 0x000000FF /**< Each Byte corresponds to an
260 #define XSCUGIC_PRIORITY_MAX 0x000000FF /**< Highest value of a priority
261 actually the lowest priority*/
264 /** @name SPI Target Register 0x800-0x8FB
265 * Each byte references a separate SPI and programs which of the up to 8 CPU
266 * interfaces are sent a Pending interrupt.
267 * There are registers for each of the CPU interfaces at offset 0x800 through
268 * 0x81C. With up to 8 registers aliased to each address.
269 * A register set for the SPI interrupts is available to all CPU interfaces.
270 * There are up to 255 of these registers staring at location 0x820.
272 * This driver does not support multiple CPU interfaces. These are included
273 * for complete documentation.
276 #define XSCUGIC_SPI_CPU7_MASK 0x00000080 /**< CPU 7 Mask*/
277 #define XSCUGIC_SPI_CPU6_MASK 0x00000040 /**< CPU 6 Mask*/
278 #define XSCUGIC_SPI_CPU5_MASK 0x00000020 /**< CPU 5 Mask*/
279 #define XSCUGIC_SPI_CPU4_MASK 0x00000010 /**< CPU 4 Mask*/
280 #define XSCUGIC_SPI_CPU3_MASK 0x00000008 /**< CPU 3 Mask*/
281 #define XSCUGIC_SPI_CPU2_MASK 0x00000003 /**< CPU 2 Mask*/
282 #define XSCUGIC_SPI_CPU1_MASK 0x00000002 /**< CPU 1 Mask*/
283 #define XSCUGIC_SPI_CPU0_MASK 0x00000001 /**< CPU 0 Mask*/
286 /** @name Interrupt Configuration Register 0xC00-0xCFC
287 * The interrupt configuration registers program an SFI to be active HIGH level
288 * sensitive or rising edge sensitive.
289 * Each bit pair describes the configuration for an INT_ID.
290 * SFI Read Only b10 always
291 * PPI Read Only depending on how the PPIs are configured.
292 * b01 Active HIGH level sensitive
293 * b11 Rising edge sensitive
294 * SPI LSB is read only.
295 * b01 Active HIGH level sensitive
296 * b11 Rising edge sensitive/
297 * There are registers for each of the CPU interfaces at offset 0xC00 through
298 * 0xC04. With up to 8 registers aliased to each address.
299 * A register set for the SPI interrupts is available to all CPU interfaces.
300 * There are up to 255 of these registers staring at location 0xC08.
303 #define XSCUGIC_INT_CFG_MASK 0x00000003 /**< */
306 /** @name PPI Status Register
307 * Enables an external AMBA master to access the status of the PPI inputs.
308 * A CPU can only read the status of its local PPI signals and cannot read the
309 * status for other CPUs.
310 * This register is aliased for each CPU interface.
313 #define XSCUGIC_PPI_C15_MASK 0x00008000 /**< PPI Status */
314 #define XSCUGIC_PPI_C14_MASK 0x00004000 /**< PPI Status */
315 #define XSCUGIC_PPI_C13_MASK 0x00002000 /**< PPI Status */
316 #define XSCUGIC_PPI_C12_MASK 0x00001000 /**< PPI Status */
317 #define XSCUGIC_PPI_C11_MASK 0x00000800 /**< PPI Status */
318 #define XSCUGIC_PPI_C10_MASK 0x00000400 /**< PPI Status */
319 #define XSCUGIC_PPI_C09_MASK 0x00000200 /**< PPI Status */
320 #define XSCUGIC_PPI_C08_MASK 0x00000100 /**< PPI Status */
321 #define XSCUGIC_PPI_C07_MASK 0x00000080 /**< PPI Status */
322 #define XSCUGIC_PPI_C06_MASK 0x00000040 /**< PPI Status */
323 #define XSCUGIC_PPI_C05_MASK 0x00000020 /**< PPI Status */
324 #define XSCUGIC_PPI_C04_MASK 0x00000010 /**< PPI Status */
325 #define XSCUGIC_PPI_C03_MASK 0x00000008 /**< PPI Status */
326 #define XSCUGIC_PPI_C02_MASK 0x00000004 /**< PPI Status */
327 #define XSCUGIC_PPI_C01_MASK 0x00000002 /**< PPI Status */
328 #define XSCUGIC_PPI_C00_MASK 0x00000001 /**< PPI Status */
331 /** @name SPI Status Register 0xd04-0xd7C
332 * Enables an external AMBA master to access the status of the SPI inputs.
333 * There are up to 63 registers if the maximum number of SPI inputs are
337 #define XSCUGIC_SPI_N_MASK 0x00000001 /**< Each bit corresponds to an SPI
341 /** @name AHB Configuration Register
342 * Provides the status of the CFGBIGEND input signal and allows the endianess
343 * of the GIC to be set.
346 #define XSCUGIC_AHB_END_MASK 0x00000004 /**< 0-GIC uses little Endian,
347 1-GIC uses Big Endian */
348 #define XSCUGIC_AHB_ENDOVR_MASK 0x00000002 /**< 0-Uses CFGBIGEND control,
349 1-use the AHB_END bit */
350 #define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001 /**< State of CFGBIGEND */
354 /** @name Software Triggered Interrupt Register
355 * Controls issueing of software interrupts.
358 #define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000
359 #define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000 /**< Target List filter
360 b00-Use the target List
361 b01-All CPUs except requester
364 #define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000 /**< CPU Target list */
365 #define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000 /**< 0= Use a secure interrupt */
366 #define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000F /**< Set to the INTID
367 signaled to the CPU*/
370 /** @name CPU Interface Register Map
372 * Define the offsets from the base address for all CPU registers of the
373 * interrupt controller, some registers may be reserved in the hardware device.
376 #define XSCUGIC_CONTROL_OFFSET 0x00000000 /**< CPU Interface Control
378 #define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004 /**< Priority Mask Reg */
379 #define XSCUGIC_BIN_PT_OFFSET 0x00000008 /**< Binary Point Register */
380 #define XSCUGIC_INT_ACK_OFFSET 0x0000000C /**< Interrupt ACK Reg */
381 #define XSCUGIC_EOI_OFFSET 0x00000010 /**< End of Interrupt Reg */
382 #define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014 /**< Running Priority Reg */
383 #define XSCUGIC_HI_PEND_OFFSET 0x00000018 /**< Highest Pending Interrupt
385 #define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001C /**< Aliased non-Secure
386 Binary Point Register */
388 /**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
393 /** @name Control Register
394 * CPU Interface Control register definitions
395 * All bits are defined here although some are not available in the non-secure
399 #define XSCUGIC_CNTR_SBPR_MASK 0x00000010 /**< Secure Binary Pointer,
400 0=separate registers,
401 1=both use bin_pt_s */
402 #define XSCUGIC_CNTR_FIQEN_MASK 0x00000008 /**< Use nFIQ_C for secure
405 1=Use FIQ for secure, IRQ for non*/
406 #define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004 /**< Ack control for secure or non secure */
407 #define XSCUGIC_CNTR_EN_NS_MASK 0x00000002 /**< Non Secure enable */
408 #define XSCUGIC_CNTR_EN_S_MASK 0x00000001 /**< Secure enable, 0=Disabled, 1=Enabled */
411 /** @name Priority Mask Register
412 * Priority Mask register definitions
413 * The CPU interface does not send interrupt if the level of the interrupt is
414 * lower than the level of the register.
417 #define XSCUGIC_PRIORITY_MASK 0x000000FF /**< All interrupts */
420 /** @name Binary Point Register
421 * Binary Point register definitions
425 #define XSCUGIC_BIN_PT_MASK 0x00000007 /**< Binary point mask value
426 Value Secure Non-secure
438 /** @name Interrupt Acknowledge Register
439 * Interrupt Acknowledge register definitions
440 * Identifies the current Pending interrupt, and the CPU ID for software
443 #define XSCUGIC_ACK_INTID_MASK 0x000003FF /**< Interrupt ID */
444 #define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */
447 /** @name End of Interrupt Register
448 * End of Interrupt register definitions
449 * Allows the CPU to signal the GIC when it completes an interrupt service
452 #define XSCUGIC_EOI_INTID_MASK 0x000003FF /**< Interrupt ID */
456 /** @name Running Priority Register
457 * Running Priority register definitions
458 * Identifies the interrupt priority level of the highest priority active
461 #define XSCUGIC_RUN_PRIORITY_MASK 0x00000FF /**< Interrupt Priority */
465 * Highest Pending Interrupt register definitions
466 * Identifies the interrupt priority of the highest priority pending interupt
468 #define XSCUGIC_PEND_INTID_MASK 0x000003FF /**< Pending Interrupt ID */
469 #define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */
472 /***************** Macros (Inline Functions) Definitions *********************/
474 /****************************************************************************/
477 * Read the Interrupt Configuration Register offset for an interrupt id.
479 * @param InterruptID is the interrupt number.
481 * @return The 32-bit value of the offset
485 *****************************************************************************/
486 #define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
487 (XSCUGIC_INT_CFG_OFFSET + ((InterruptID/16) * 4))
489 /****************************************************************************/
492 * Read the Interrupt Priority Register offset for an interrupt id.
494 * @param InterruptID is the interrupt number.
496 * @return The 32-bit value of the offset
500 *****************************************************************************/
501 #define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
502 (XSCUGIC_PRIORITY_OFFSET + ((InterruptID/4) * 4))
504 /****************************************************************************/
507 * Read the SPI Target Register offset for an interrupt id.
509 * @param InterruptID is the interrupt number.
511 * @return The 32-bit value of the offset
515 *****************************************************************************/
516 #define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
517 (XSCUGIC_SPI_TARGET_OFFSET + ((InterruptID/4) * 4))
519 /****************************************************************************/
522 * Read the Interrupt Clear-Enable Register offset for an interrupt ID
524 * @param Register is the register offset for the clear/enable bank.
525 * @param InterruptID is the interrupt number.
527 * @return The 32-bit value of the offset
531 *****************************************************************************/
532 #define XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(Register, InterruptID) \
533 (Register + ((InterruptID/32) * 4))
535 /****************************************************************************/
538 * Read the given Intc register.
540 * @param BaseAddress is the base address of the device.
541 * @param RegOffset is the register offset to be read
543 * @return The 32-bit value of the register
547 * u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
549 *****************************************************************************/
550 #define XScuGic_ReadReg(BaseAddress, RegOffset) \
551 (Xil_In32((BaseAddress) + (RegOffset)))
554 /****************************************************************************/
557 * Write the given Intc register.
559 * @param BaseAddress is the base address of the device.
560 * @param RegOffset is the register offset to be written
561 * @param Data is the 32-bit value to write to the register
567 * void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
569 *****************************************************************************/
570 #define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
571 (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)Data)))
574 /****************************************************************************/
577 * Enable specific interrupt(s) in the interrupt controller.
579 * @param DistBaseAddress is the Distributor Register base address of the
581 * @param Int_Id is the ID of the interrupt source and should be in the
582 * range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
586 * @note C-style signature:
587 * void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id);
589 *****************************************************************************/
590 #define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
591 XScuGic_WriteReg((DistBaseAddress), \
592 XSCUGIC_ENABLE_SET_OFFSET + ((Int_Id / 32) * 4), \
593 (1 << (Int_Id % 32)))
595 /****************************************************************************/
598 * Disable specific interrupt(s) in the interrupt controller.
600 * @param DistBaseAddress is the Distributor Register base address of the
602 * @param Int_Id is the ID of the interrupt source and should be in the
603 * range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
608 * @note C-style signature:
609 * void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id);
611 *****************************************************************************/
612 #define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
613 XScuGic_WriteReg((DistBaseAddress), \
614 XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32) * 4), \
615 (1 << (Int_Id % 32)))
618 /************************** Function Prototypes ******************************/
620 void XScuGic_DeviceInterruptHandler(void *DeviceId);
621 int XScuGic_DeviceInitialize(u32 DeviceId);
622 void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId,
623 Xil_InterruptHandler Handler, void *CallBackRef);
624 void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
625 u8 Priority, u8 Trigger);
626 void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
627 u8 *Priority, u8 *Trigger);
628 /************************** Variable Definitions *****************************/
633 #endif /* end of protection macro */