4 * \brief Chip-specific system clock management functions.
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6 * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.
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12 * Redistribution and use in source and binary forms, with or without
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13 * modification, are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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22 * 3. The name of Atmel may not be used to endorse or promote products derived
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23 * from this software without specific prior written permission.
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25 * 4. This software may only be redistributed and used in connection with an
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26 * Atmel microcontroller product.
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28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 * POSSIBILITY OF SUCH DAMAGE.
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44 #ifndef CHIP_SYSCLK_H_INCLUDED
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45 #define CHIP_SYSCLK_H_INCLUDED
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47 #if (SAM3S8 || SAM3SD8)
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56 * \page sysclk_quickstart Quick Start Guide for the System Clock Management service (SAM3S)
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58 * This is the quick start guide for the \ref sysclk_group "System Clock Management"
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59 * service, with step-by-step instructions on how to configure and use the service for
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60 * specific use cases.
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62 * \section sysclk_quickstart_usecases System Clock Management use cases
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63 * - \ref sysclk_quickstart_basic
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64 * - \ref sysclk_quickstart_use_case_2
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66 * \section sysclk_quickstart_basic Basic usage of the System Clock Management service
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67 * This section will present a basic use case for the System Clock Management service.
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68 * This use case will configure the main system clock to 64MHz, using an internal PLL
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69 * module to multiply the frequency of a crystal attached to the microcontroller.
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71 * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites
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74 * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code
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75 * Add to the application initialization code:
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80 * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow
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81 * -# Configure the system clocks according to the settings in conf_clock.h:
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82 * \code sysclk_init(); \endcode
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84 * \subsection sysclk_quickstart_use_case_1_example_code Example code
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85 * Add or uncomment the following in your conf_clock.h header file, commenting out all other
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86 * definitions of the same symbol(s):
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88 * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
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90 * // Fpll0 = (Fclk * PLL_mul) / PLL_div
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91 * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
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92 * #define CONFIG_PLL0_MUL (64000000UL / BOARD_FREQ_MAINCK_XTAL)
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93 * #define CONFIG_PLL0_DIV 1
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95 * // Fbus = Fsys / BUS_div
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96 * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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99 * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow
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100 * -# Configure the main system clock to use the output of the PLL module as its source:
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101 * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode
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102 * -# Configure the PLL module to use the fast external fast crystal oscillator as its source:
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103 * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode
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104 * -# Configure the PLL module to multiply the external fast crystal oscillator frequency up to 64MHz:
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106 * #define CONFIG_PLL0_MUL (64000000UL / BOARD_FREQ_MAINCK_XTAL)
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107 * #define CONFIG_PLL0_DIV 1
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109 * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the board \c conf_board.h configuration
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110 * file as the frequency of the fast crystal attached to the microcontroller.
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111 * -# Configure the main clock to run at the full 64MHz, disable scaling of the main system clock speed:
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113 * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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115 * \note Some dividers are powers of two, while others are integer division factors. Refer to the
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116 * formulas in the conf_clock.h template commented above each division define.
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120 * \page sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock Management (SAM3S)
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122 * \section sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock Management
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123 * This section will present a more advanced use case for the System Clock Management service.
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124 * This use case will configure the main system clock to 64MHz, using an internal PLL
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125 * module to multiply the frequency of a crystal attached to the microcontroller. The USB clock
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126 * will be configured via a separate PLL module.
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128 * \subsection sysclk_quickstart_use_case_2_prereq Prerequisites
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131 * \subsection sysclk_quickstart_use_case_2_setup_steps Initialization code
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132 * Add to the application initialization code:
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137 * \subsection sysclk_quickstart_use_case_2_setup_steps_workflow Workflow
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138 * -# Configure the system clocks according to the settings in conf_clock.h:
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139 * \code sysclk_init(); \endcode
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141 * \subsection sysclk_quickstart_use_case_2_example_code Example code
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142 * Add or uncomment the following in your conf_clock.h header file, commenting out all other
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143 * definitions of the same symbol(s):
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145 * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
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147 * // Fpll0 = (Fclk * PLL_mul) / PLL_div
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148 * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
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149 * #define CONFIG_PLL0_MUL (64000000UL / BOARD_FREQ_MAINCK_XTAL)
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150 * #define CONFIG_PLL0_DIV 1
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152 * // Fbus = Fsys / BUS_div
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153 * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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155 * // Fusb = Fsys / USB_div
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156 * #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
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157 * #define CONFIG_USBCLK_DIV 1
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159 * // Fpll1 = (Fclk * PLL_mul) / PLL_div
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160 * #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL
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161 * #define CONFIG_PLL1_MUL (48000000UL / BOARD_FREQ_MAINCK_XTAL)
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162 * #define CONFIG_PLL1_DIV 1
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165 * \subsection sysclk_quickstart_use_case_2_example_workflow Workflow
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166 * -# Configure the main system clock to use the output of the PLL0 module as its source:
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167 * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode
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168 * -# Configure the PLL0 module to use the fast external fast crystal oscillator as its source:
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169 * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode
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170 * -# Configure the PLL0 module to multiply the external fast crystal oscillator frequency up to 64MHz:
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172 * #define CONFIG_PLL0_MUL (64000000UL / BOARD_FREQ_MAINCK_XTAL)
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173 * #define CONFIG_PLL0_DIV 1
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175 * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the board \c conf_board.h configuration
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176 * file as the frequency of the fast crystal attached to the microcontroller.
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177 * -# Configure the main clock to run at the full 64MHz, disable scaling of the main system clock speed:
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179 * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
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181 * \note Some dividers are powers of two, while others are integer division factors. Refer to the
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182 * formulas in the conf_clock.h template commented above each division define.
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183 * -# Configure the USB module clock to use the output of the PLL1 module as its source:
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184 * \code #define CONFIG_SYSCLK_SOURCE USBCLK_SRC_PLL1 \endcode
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185 * -# Configure the PLL1 module to use the fast external fast crystal oscillator as its source:
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186 * \code #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL \endcode
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187 * -# Configure the PLL1 module to multiply the external fast crystal oscillator frequency up to 48MHz:
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189 * #define CONFIG_PLL1_MUL (48000000UL / BOARD_FREQ_MAINCK_XTAL)
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190 * #define CONFIG_PLL1_DIV 1
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203 * \weakgroup sysclk_group
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207 //! \name Configuration Symbols
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210 * \def CONFIG_SYSCLK_SOURCE
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211 * \brief Initial/static main system clock source
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213 * The main system clock will be configured to use this clock during
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216 #ifndef CONFIG_SYSCLK_SOURCE
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217 # define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
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220 * \def CONFIG_SYSCLK_PRES
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221 * \brief Initial CPU clock divider (mck)
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223 * The MCK will run at
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225 * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz}
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227 * after initialization.
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229 #ifndef CONFIG_SYSCLK_PRES
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230 # define CONFIG_SYSCLK_PRES 0
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235 //! \name Master Clock Sources (MCK)
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237 #define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock
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238 #define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock
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239 #define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock
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240 #define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock
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241 #define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock
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242 #define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock
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243 #define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock
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244 #define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock
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245 #define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock
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246 #define SYSCLK_SRC_PLLBCK 9 //!< Use PLLBCK as master source clock
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249 //! \name Master Clock Prescalers (MCK)
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251 #define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1
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252 #define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2
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253 #define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4
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254 #define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8
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255 #define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16
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256 #define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32
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257 #define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64
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258 #define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3
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261 //! \name USB Clock Sources
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263 #define USBCLK_SRC_PLL0 0 //!< Use PLLA
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264 #define USBCLK_SRC_PLL1 1 //!< Use PLLB
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268 * \def CONFIG_USBCLK_SOURCE
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269 * \brief Configuration symbol for the USB generic clock source
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271 * Sets the clock source to use for the USB. The source must also be properly
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274 * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if
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275 * USB is not required.
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278 # define CONFIG_USBCLK_SOURCE
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282 * \def CONFIG_USBCLK_DIV
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283 * \brief Configuration symbol for the USB generic clock divider setting
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285 * Sets the clock division for the USB generic clock. If a USB clock source is
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286 * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be
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290 # define CONFIG_USBCLK_DIV
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294 * \name Querying the system clock
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296 * The following functions may be used to query the current frequency of
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297 * the system clock and the CPU and bus clocks derived from it.
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298 * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be
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299 * available on all platforms, although some platforms may define
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300 * additional accessors for various chip-internal bus clocks. These are
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301 * usually not intended to be queried directly by generic code.
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306 * \brief Return the current rate in Hz of the main system clock
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308 * \todo This function assumes that the main clock source never changes
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309 * once it's been set up, and that PLL0 always runs at the compile-time
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310 * configured default rate. While this is probably the most common
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311 * configuration, which we want to support as a special case for
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312 * performance reasons, we will at some point need to support more
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313 * dynamic setups as well.
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315 #if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
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316 extern uint32_t sysclk_initialized;
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318 static inline uint32_t sysclk_get_main_hz(void)
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320 #if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
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321 if (!sysclk_initialized ) {
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322 return OSC_MAINCK_4M_RC_HZ;
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326 /* Config system clock setting */
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327 switch (CONFIG_SYSCLK_SOURCE) {
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328 case SYSCLK_SRC_SLCK_RC:
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329 return OSC_SLCK_32K_RC_HZ;
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331 case SYSCLK_SRC_SLCK_XTAL:
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332 return OSC_SLCK_32K_XTAL_HZ;
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334 case SYSCLK_SRC_SLCK_BYPASS:
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335 return OSC_SLCK_32K_BYPASS_HZ;
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338 case SYSCLK_SRC_MAINCK_4M_RC:
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339 return OSC_MAINCK_4M_RC_HZ;
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341 case SYSCLK_SRC_MAINCK_8M_RC:
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342 return OSC_MAINCK_8M_RC_HZ;
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344 case SYSCLK_SRC_MAINCK_12M_RC:
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345 return OSC_MAINCK_12M_RC_HZ;
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347 case SYSCLK_SRC_MAINCK_XTAL:
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348 return OSC_MAINCK_XTAL_HZ;
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350 case SYSCLK_SRC_MAINCK_BYPASS:
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351 return OSC_MAINCK_BYPASS_HZ;
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353 #ifdef CONFIG_PLL0_SOURCE
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354 case SYSCLK_SRC_PLLACK:
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355 return pll_get_default_rate(0);
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358 #ifdef CONFIG_PLL1_SOURCE
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359 case SYSCLK_SRC_PLLBCK:
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360 return pll_get_default_rate(1);
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364 /* unhandled_case(CONFIG_SYSCLK_SOURCE); */
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370 * \brief Return the current rate in Hz of the CPU clock
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372 * \todo This function assumes that the CPU always runs at the system
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373 * clock frequency. We want to support at least two more scenarios:
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374 * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus
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375 * clock dividers (which may change at run time). Ditto for all the bus
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378 * \return Frequency of the CPU clock, in Hz.
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380 static inline uint32_t sysclk_get_cpu_hz(void)
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382 /* CONFIG_SYSCLK_PRES is the register value for setting the expected */
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383 /* prescaler, not an immediate value. */
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384 return sysclk_get_main_hz() / ((CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos) + 1);
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388 * \brief Retrieves the current rate in Hz of the peripheral clocks.
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390 * \return Frequency of the peripheral clocks, in Hz.
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392 static inline uint32_t sysclk_get_peripheral_hz(void)
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394 /* CONFIG_SYSCLK_PRES is the register value for setting the expected */
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395 /* prescaler, not an immediate value. */
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396 return sysclk_get_main_hz() / ((CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos) + 1);
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401 //! \name Enabling and disabling synchronous clocks
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405 * \brief Enable a peripheral's clock.
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407 * \param ul_id Id (number) of the peripheral clock.
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409 static inline void sysclk_enable_peripheral_clock(uint32_t ul_id)
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411 pmc_enable_periph_clk(ul_id);
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415 * \brief Disable a peripheral's clock.
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417 * \param ul_id Id (number) of the peripheral clock.
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419 static inline void sysclk_disable_peripheral_clock(uint32_t ul_id)
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421 pmc_disable_periph_clk(ul_id);
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426 //! \name System Clock Source and Prescaler configuration
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429 extern void sysclk_set_prescalers(uint32_t ul_pres);
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430 extern void sysclk_set_source(uint32_t ul_src);
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434 extern void sysclk_enable_usb(void);
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435 extern void sysclk_disable_usb(void);
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437 extern void sysclk_init(void);
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449 #endif /* CHIP_SYSCLK_H_INCLUDED */
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