--- /dev/null
+REM This file should be executed from the command line prior to the first\r
+REM build. It will be necessary to refresh the Eclipse project once the\r
+REM .bat file has been executed (normally just press F5 to refresh).\r
+\r
+REM Copies all the required files from their location within the standard\r
+REM FreeRTOS directory structure to under the Eclipse project directory.\r
+REM This permits the Eclipse project to be used in 'managed' mode and without\r
+REM having to setup any linked resources.\r
+\r
+REM Standard paths\r
+SET FREERTOS_SOURCE=..\..\Source\r
+SET COMMON_SOURCE=..\Common\minimal\r
+SET COMMON_INCLUDE=..\Common\include\r
+\r
+REM Have the files already been copied?\r
+IF EXIST src\asf\thirdparty\FreeRTOS Goto END\r
+\r
+ REM Create the required directory structure.\r
+ MD src\asf\thirdparty\FreeRTOS\r
+ MD src\asf\thirdparty\FreeRTOS\include\r
+ MD src\asf\thirdparty\FreeRTOS\portable\r
+ MD src\asf\thirdparty\FreeRTOS\portable\GCC\r
+ MD src\asf\thirdparty\FreeRTOS\portable\GCC\ARM_CM3\r
+ MD src\asf\thirdparty\FreeRTOS\portable\MemMang \r
+ MD src\Common-Demo-Source\include\r
+ \r
+ REM Copy the core kernel files into the project directory\r
+ copy %FREERTOS_SOURCE%\tasks.c src\asf\thirdparty\FreeRTOS\r
+ copy %FREERTOS_SOURCE%\queue.c src\asf\thirdparty\FreeRTOS\r
+ copy %FREERTOS_SOURCE%\list.c src\asf\thirdparty\FreeRTOS\r
+ copy %FREERTOS_SOURCE%\timers.c src\asf\thirdparty\FreeRTOS\r
+\r
+ REM Copy the common header files into the project directory\r
+ copy %FREERTOS_SOURCE%\include\*.* src\asf\thirdparty\FreeRTOS\include\r
+ \r
+ REM Copy the portable layer files into the project directory\r
+ copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM3\*.* src\asf\thirdparty\FreeRTOS\portable\GCC\ARM_CM3\r
+ \r
+ REM Copy the memory allocation files into the project directory\r
+ copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c src\asf\thirdparty\FreeRTOS\portable\MemMang\r
+\r
+ REM Copy the files that define the common demo tasks.\r
+ copy %COMMON_SOURCE%\dynamic.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\BlockQ.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\flash_timer.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\death.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\blocktim.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\semtest.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\PollQ.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\GenQTest.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\recmutex.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\countsem.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\integer.c src\Common-Demo-Source\r
+ \r
+ REM Copy the common demo file headers.\r
+ copy %COMMON_INCLUDE%\*.h src\Common-Demo-Source\include\r
+ \r
+: END\r
--- /dev/null
+\r
+Microsoft Visual Studio Solution File, Format Version 11.00\r
+# Atmel Studio Solution File, Format Version 11.00\r
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "RTOSDemo", "RTOSDemo.cproj", "{4C68CA75-30F2-4325-8B61-35952638D586}"\r
+EndProject\r
+Global\r
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution\r
+ Debug|ARM = Debug|ARM\r
+ EndGlobalSection\r
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution\r
+ {4C68CA75-30F2-4325-8B61-35952638D586}.Debug|ARM.ActiveCfg = Debug|ARM\r
+ {4C68CA75-30F2-4325-8B61-35952638D586}.Debug|ARM.Build.0 = Debug|ARM\r
+ EndGlobalSection\r
+ GlobalSection(SolutionProperties) = preSolution\r
+ HideSolutionNode = FALSE\r
+ EndGlobalSection\r
+EndGlobal\r
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>\r
+<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003" DefaultTargets="Build">\r
+ <PropertyGroup>\r
+ <SchemaVersion>2.0</SchemaVersion>\r
+ <ProjectVersion>6.0</ProjectVersion>\r
+ <ProjectGuid>{4c68ca75-30f2-4325-8b61-35952638d586}</ProjectGuid>\r
+ <Name>$(MSBuildProjectName)</Name>\r
+ <AssemblyName>$(MSBuildProjectName)</AssemblyName>\r
+ <RootNamespace>$(MSBuildProjectName)</RootNamespace>\r
+ <AsfVersion>3.3.0</AsfVersion>\r
+ <AsfFrameworkConfig>\r
+ <framework-data>\r
+ <options>\r
+ <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.services.basic.gpio" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.drivers.pio" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.services.basic.clock" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.drivers.usart" value="Add" config="" content-id="Atmel.ASF" />\r
+ </options>\r
+ <configurations>\r
+ <configuration key="config.sam.pio.pio_handler" value="yes" default="yes" content-id="Atmel.ASF" />\r
+ </configurations>\r
+ <files>\r
+ <file path="src/asf.h" framework="" version="3.3.0" source="./common/applications/user_application/sam3sd8c_sam3s_ek2/as5_arm_template/asf.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/main.c" framework="" version="3.3.0" source="common/applications/user_application/main.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/config/conf_board.h" framework="" version="3.3.0" source="common/applications/user_application/sam3sd8c_sam3s_ek2/conf_board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/boards/board.h" framework="" version="3.3.0" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/gpio/gpio.h" framework="" version="3.3.0" source="common/services/gpio/gpio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/gpio/sam_ioport/sam_gpio.h" framework="" version="3.3.0" source="common/services/gpio/sam_ioport/sam_gpio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/interrupt.h" framework="" version="3.3.0" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="3.3.0" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="3.3.0" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/parts.h" framework="" version="3.3.0" source="common/utils/parts.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/boards/sam3s_ek2/init.c" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/init.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/boards/sam3s_ek2/led.h" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/led.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/boards/sam3s_ek2/sam3s_ek2.h" framework="" version="3.3.0" source="sam/boards/sam3s_ek2/sam3s_ek2.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio.c" framework="" version="3.3.0" source="sam/drivers/pio/pio.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio.h" framework="" version="3.3.0" source="sam/drivers/pio/pio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio_handler.c" framework="" version="3.3.0" source="sam/drivers/pio/pio_handler.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio_handler.h" framework="" version="3.3.0" source="sam/drivers/pio/pio_handler.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_acc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_acc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_adc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_adc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_chipid.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_chipid.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_crccu.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_crccu.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_dacc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_dacc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_efc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_efc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_gpbr.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_gpbr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_hsmci.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_hsmci.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_matrix.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_matrix.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pdc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pdc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pio.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pmc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_pwm.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_pwm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rstc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rstc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rtc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_rtt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_rtt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_smc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_smc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_spi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_spi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_ssc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_ssc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_supc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_supc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_tc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_tc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_twi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_twi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_uart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_uart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_udp.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_udp.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_usart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_usart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/component/component_wdt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/component/component_wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_acc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_acc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_adc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_adc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_chipid.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_chipid.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_crccu.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_crccu.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_dacc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_dacc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_efc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_efc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_gpbr.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_gpbr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_hsmci.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_hsmci.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_matrix.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_matrix.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pioa.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pioa.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_piob.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_piob.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pioc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pioc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pmc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_pwm.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_pwm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rstc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rstc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rtc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_rtt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_rtt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_smc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_smc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_spi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_spi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_ssc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_ssc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_supc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_supc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_tc0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_tc0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_tc1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_tc1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_twi0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_twi0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_twi1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_twi1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_uart0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_uart0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_uart1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_uart1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_udp.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_udp.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_usart2.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_usart2.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/instance/instance_wdt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/instance/instance_wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/pio/pio_sam3sd8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/pio/pio_sam3sd8c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3s8/include/sam3s8.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3s8/include/sam3s8.h" changed="False" content-id="Atmel.ASF" />\r
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+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Include\core_cmFunc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Include\core_cmInstr.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\README.txt">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\license.txt">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\config\conf_board.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ </ItemGroup>\r
+ <ItemGroup>\r
+ <Folder Include="src\" />\r
+ <Folder Include="src\asf\" />\r
+ <Folder Include="src\asf\common\" />\r
+ <Folder Include="src\asf\common\boards\" />\r
+ <Folder Include="src\asf\common\services\" />\r
+ <Folder Include="src\asf\common\services\clock\" />\r
+ <Folder Include="src\asf\common\services\clock\sam3s\" />\r
+ <Folder Include="src\asf\common\services\gpio\" />\r
+ <Folder Include="src\asf\common\services\gpio\sam_ioport\" />\r
+ <Folder Include="src\asf\common\utils\" />\r
+ <Folder Include="src\asf\common\utils\interrupt\" />\r
+ <Folder Include="src\asf\sam\" />\r
+ <Folder Include="src\asf\sam\boards\" />\r
+ <Folder Include="src\asf\sam\boards\sam3s_ek2\" />\r
+ <Folder Include="src\asf\sam\drivers\" />\r
+ <Folder Include="src\asf\sam\drivers\pio\" />\r
+ <Folder Include="src\asf\sam\drivers\pmc\" />\r
+ <Folder Include="src\asf\sam\drivers\usart\" />\r
+ <Folder Include="src\asf\sam\utils\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3s8\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3s8\include\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3s8\include\component\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3s8\include\instance\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3s8\include\pio\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3s8\source\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3s8\source\templates\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3s8\source\templates\gcc\" />\r
+ <Folder Include="src\asf\sam\utils\header_files\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\sam3s\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\sam3s\sam3sd8\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\sam3s\sam3sd8\gcc\" />\r
+ <Folder Include="src\asf\sam\utils\make\" />\r
+ <Folder Include="src\asf\sam\utils\preprocessor\" />\r
+ <Folder Include="src\asf\thirdparty\" />\r
+ <Folder Include="src\asf\thirdparty\CMSIS\" />\r
+ <Folder Include="src\asf\thirdparty\CMSIS\Include\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\include\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\portable\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\portable\GCC\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\portable\GCC\ARM_CM3\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\portable\MemMang\" />\r
+ <Folder Include="src\Common-Demo-Source\" />\r
+ <Folder Include="src\Common-Demo-Source\include\" />\r
+ <Folder Include="src\config\" />\r
+ </ItemGroup>\r
+ <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />\r
+</Project>
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+/*\r
+ * This version of comtest. c is for use on systems that have limited stack\r
+ * space and no display facilities. The complete version can be found in\r
+ * the Demo/Common/Full directory.\r
+ *\r
+ * Creates two tasks that operate on an interrupt driven serial port. A\r
+ * loopback connector should be used so that everything that is transmitted is\r
+ * also received. The serial port does not use any flow control. On a\r
+ * standard 9way 'D' connector pins two and three should be connected together.\r
+ *\r
+ * The first task posts a sequence of characters to the Tx queue, toggling an\r
+ * LED on each successful post. At the end of the sequence it sleeps for a\r
+ * pseudo-random period before resending the same sequence.\r
+ *\r
+ * The UART Tx end interrupt is enabled whenever data is available in the Tx\r
+ * queue. The Tx end ISR removes a single character from the Tx queue and\r
+ * passes it to the UART for transmission.\r
+ *\r
+ * The second task blocks on the Rx queue waiting for a character to become\r
+ * available. When the UART Rx end interrupt receives a character it places\r
+ * it in the Rx queue, waking the second task. The second task checks that the\r
+ * characters removed from the Rx queue form the same sequence as those posted\r
+ * to the Tx queue, and toggles an LED for each correct character.\r
+ *\r
+ * The receiving task is spawned with a higher priority than the transmitting\r
+ * task. The receiver will therefore wake every time a character is\r
+ * transmitted so neither the Tx or Rx queue should ever hold more than a few\r
+ * characters.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "demo_serial.h"\r
+#include "comtest2.h"\r
+#include "partest.h"\r
+\r
+#define comSTACK_SIZE configMINIMAL_STACK_SIZE\r
+#define comTX_LED_OFFSET ( 0 )\r
+#define comRX_LED_OFFSET ( 1 )\r
+#define comTOTAL_PERMISSIBLE_ERRORS ( 2 )\r
+\r
+/* The Tx task will transmit the sequence of characters at a pseudo random\r
+interval. This is the maximum and minimum block time between sends. */\r
+#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x96 )\r
+#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0x32 )\r
+#define comOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* We should find that each character can be queued for Tx immediately and we\r
+don't have to block to send. */\r
+#define comNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/* The Rx task will block on the Rx queue for a long period. */\r
+#define comRX_BLOCK_TIME ( ( portTickType ) 0xffff )\r
+\r
+/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */\r
+#define comFIRST_BYTE ( 'A' )\r
+#define comLAST_BYTE ( 'X' )\r
+\r
+#define comBUFFER_LEN ( ( unsigned portBASE_TYPE ) ( comLAST_BYTE - comFIRST_BYTE ) + ( unsigned portBASE_TYPE ) 1 )\r
+#define comINITIAL_RX_COUNT_VALUE ( 0 )\r
+\r
+/* Handle to the com port used by both tasks. */\r
+static xComPortHandle xPort = NULL;\r
+\r
+/* The transmit task as described at the top of the file. */\r
+static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters );\r
+\r
+/* The receive task as described at the top of the file. */\r
+static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters );\r
+\r
+/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will\r
+toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED\r
+( uxBaseLED + comTX_LED_OFFSET ). */\r
+static unsigned portBASE_TYPE uxBaseLED = 0;\r
+\r
+/* Check variable used to ensure no error have occurred. The Rx task will\r
+increment this variable after every successfully received sequence. If at any\r
+time the sequence is incorrect the the variable will stop being incremented. */\r
+static volatile unsigned portBASE_TYPE uxRxLoops = comINITIAL_RX_COUNT_VALUE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned long ulBaudRate, unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* Initialise the com port then spawn the Rx and Tx tasks. */\r
+ uxBaseLED = uxLED;\r
+ xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN );\r
+\r
+ /* The Tx task is spawned with a lower priority than the Rx task. */\r
+ xTaskCreate( vComTxTask, ( signed char * ) "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( vComRxTask, ( signed char * ) "COMRx", comSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vComTxTask, pvParameters )\r
+{\r
+signed char cByteToSend;\r
+portTickType xTimeToWait;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Simply transmit a sequence of characters from comFIRST_BYTE to\r
+ comLAST_BYTE. */\r
+ for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ )\r
+ {\r
+ if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS )\r
+ {\r
+ vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );\r
+ }\r
+ }\r
+\r
+ /* Turn the LED off while we are not doing anything. */\r
+ vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE );\r
+\r
+ /* We have posted all the characters in the string - wait before\r
+ re-sending. Wait a pseudo-random time as this will provide a better\r
+ test. */\r
+ xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xTimeToWait %= comTX_MAX_BLOCK_TIME;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xTimeToWait < comTX_MIN_BLOCK_TIME )\r
+ {\r
+ xTimeToWait = comTX_MIN_BLOCK_TIME;\r
+ }\r
+\r
+ vTaskDelay( xTimeToWait );\r
+ }\r
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vComRxTask, pvParameters )\r
+{\r
+signed char cExpectedByte, cByteRxed;\r
+portBASE_TYPE xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* We expect to receive the characters from comFIRST_BYTE to\r
+ comLAST_BYTE in an incrementing order. Loop to receive each byte. */\r
+ for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ )\r
+ {\r
+ /* Block on the queue that contains received bytes until a byte is\r
+ available. */\r
+ if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) )\r
+ {\r
+ /* Was this the byte we were expecting? If so, toggle the LED,\r
+ otherwise we are out on sync and should break out of the loop\r
+ until the expected character sequence is about to restart. */\r
+ if( cByteRxed == cExpectedByte )\r
+ {\r
+ vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );\r
+ }\r
+ else\r
+ {\r
+ xResyncRequired = pdTRUE;\r
+ break; /*lint !e960 Non-switch break allowed. */\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Turn the LED off while we are not doing anything. */\r
+ vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE );\r
+\r
+ /* Did we break out of the loop because the characters were received in\r
+ an unexpected order? If so wait here until the character sequence is\r
+ about to restart. */\r
+ if( xResyncRequired == pdTRUE )\r
+ {\r
+ while( cByteRxed != comLAST_BYTE )\r
+ {\r
+ /* Block until the next char is available. */\r
+ xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME );\r
+ }\r
+\r
+ /* Note that an error occurred which caused us to have to resync.\r
+ We use this to stop incrementing the loop counter so\r
+ sAreComTestTasksStillRunning() will return false - indicating an\r
+ error. */\r
+ xErrorOccurred++;\r
+\r
+ /* We have now resynced with the Tx task and can continue. */\r
+ xResyncRequired = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS )\r
+ {\r
+ /* Increment the count of successful loops. As error\r
+ occurring (i.e. an unexpected character being received) will\r
+ prevent this counter being incremented for the rest of the\r
+ execution. Don't worry about mutual exclusion on this\r
+ variable - it doesn't really matter as we just want it\r
+ to change. */\r
+ uxRxLoops++;\r
+ }\r
+ }\r
+ }\r
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xAreComTestTasksStillRunning( void )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* If the count of successful reception loops has not changed than at\r
+ some time an error occurred (i.e. a character was received out of sequence)\r
+ and we will return false. */\r
+ if( uxRxLoops == comINITIAL_RX_COUNT_VALUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ /* Reset the count of successful Rx loops. When this function is called\r
+ again we expect this to have been incremented. */\r
+ uxRxLoops = comINITIAL_RX_COUNT_VALUE;\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef SERIAL_COMMS_H\r
+#define SERIAL_COMMS_H\r
+\r
+typedef void * xComPortHandle;\r
+\r
+typedef enum\r
+{ \r
+ serCOM1, \r
+ serCOM2, \r
+ serCOM3, \r
+ serCOM4, \r
+ serCOM5, \r
+ serCOM6, \r
+ serCOM7, \r
+ serCOM8 \r
+} eCOMPort;\r
+\r
+typedef enum \r
+{ \r
+ serNO_PARITY, \r
+ serODD_PARITY, \r
+ serEVEN_PARITY, \r
+ serMARK_PARITY, \r
+ serSPACE_PARITY \r
+} eParity;\r
+\r
+typedef enum \r
+{ \r
+ serSTOP_1, \r
+ serSTOP_2 \r
+} eStopBits;\r
+\r
+typedef enum \r
+{ \r
+ serBITS_5, \r
+ serBITS_6, \r
+ serBITS_7, \r
+ serBITS_8 \r
+} eDataBits;\r
+\r
+typedef enum \r
+{ \r
+ ser50, \r
+ ser75, \r
+ ser110, \r
+ ser134, \r
+ ser150, \r
+ ser200,\r
+ ser300, \r
+ ser600, \r
+ ser1200, \r
+ ser1800, \r
+ ser2400, \r
+ ser4800,\r
+ ser9600, \r
+ ser19200, \r
+ ser38400, \r
+ ser57600, \r
+ ser115200\r
+} eBaud;\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength );\r
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength );\r
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength );\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime );\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime );\r
+portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort );\r
+void vSerialClose( xComPortHandle xPort );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, training, latest information,\r
+ license and contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+ the code with commercial support, indemnification, and middleware, under\r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under\r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*\r
+ * The following #error directive is to remind users that a batch file must be\r
+ * executed prior to this project being built. Once it has been executed\r
+ * remove the #error line below.\r
+ */\r
+#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+extern uint32_t SystemCoreClock;\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x0f\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 10\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, training, latest information,\r
+ license and contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+ the code with commercial support, indemnification, and middleware, under\r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under\r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include <board.h>\r
+#include <gpio.h>\r
+\r
+/* The number of LEDs available to the user on the evaluation kit. */\r
+#define partestNUM_LEDS ( 3UL )\r
+\r
+/* One of the LEDs is wired in the inverse to the others as it is also used as\r
+the power LED. */\r
+#define partstsINVERTED_LED ( 0UL )\r
+\r
+/* The index of the pins to which the LEDs are connected. The ordering of the\r
+LEDs in this array is intentional and matches the order they appear on the\r
+hardware. */\r
+static const uint32_t ulLED[] = { LED2_GPIO, LED0_GPIO, LED1_GPIO };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+unsigned long ul;\r
+\r
+ for( ul = 0; ul < partestNUM_LEDS; ul++ )\r
+ {\r
+ /* Configure the LED, before ensuring it starts in the off state. */\r
+ gpio_configure_pin( ulLED[ ul ], ( PIO_OUTPUT_1 | PIO_DEFAULT ) );\r
+ vParTestSetLED( ul, pdFALSE );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED < partestNUM_LEDS )\r
+ {\r
+ if( uxLED == partstsINVERTED_LED )\r
+ {\r
+ xValue = !xValue;\r
+ }\r
+\r
+ if( xValue != pdFALSE )\r
+ {\r
+ /* Turn the LED on. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ gpio_set_pin_low( ulLED[ uxLED ]);\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LED off. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ gpio_set_pin_high( ulLED[ uxLED ]);\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < partestNUM_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ gpio_toggle_pin( ulLED[ uxLED ] );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Autogenerated API include file for the Atmel Software Framework (ASF)\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef ASF_H\r
+#define ASF_H\r
+\r
+/*\r
+ * This file includes all API header files for the selected drivers from ASF.\r
+ * Note: There might be duplicate includes required by more than one driver.\r
+ *\r
+ * The file is automatically generated and will be re-written when\r
+ * running the ASF driver selector tool. Any changes will be discarded.\r
+ */\r
+\r
+// From module: Common SAM compiler driver\r
+#include <compiler.h>\r
+#include <status_codes.h>\r
+\r
+// From module: GPIO - General purpose Input/Output\r
+#include <gpio.h>\r
+\r
+// From module: Generic board support\r
+#include <board.h>\r
+\r
+// From module: Interrupt management - SAM3 implementation\r
+#include <interrupt.h>\r
+\r
+// From module: PIO - Parallel Input/Output Controller\r
+#include <pio.h>\r
+\r
+// From module: PMC - Power Management Controller\r
+#include <pmc.h>\r
+#include <sleep.h>\r
+\r
+// From module: Part identification macros\r
+#include <parts.h>\r
+\r
+// From module: System Clock Control - SAM3SD implementation\r
+#include <sysclk.h>\r
+\r
+// From module: USART - Univ. Syn Async Rec/Trans\r
+#include <usart.h>\r
+\r
+// From module: pio_handler support enabled\r
+#include <pio_handler.h>\r
+\r
+#endif // ASF_H\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Standard board header file.\r
+ *\r
+ * This file includes the appropriate board header file according to the\r
+ * defined board (parameter BOARD).\r
+ *\r
+ * Copyright (c) 2009-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+/**\r
+ * \defgroup group_common_boards Generic board support\r
+ *\r
+ * The generic board support module includes board-specific definitions\r
+ * and function prototypes, such as the board initialization function.\r
+ *\r
+ * \{\r
+ */\r
+\r
+#include "compiler.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/*! \name Base Boards\r
+ */\r
+//! @{\r
+#define EVK1100 1 //!< AT32UC3A EVK1100 board.\r
+#define EVK1101 2 //!< AT32UC3B EVK1101 board.\r
+#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board.\r
+#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.\r
+#define EVK1105 5 //!< AT32UC3A EVK1105 board.\r
+#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.\r
+#define UC3L_EK 7 //!< AT32UC3L-EK board.\r
+#define XPLAIN 8 //!< ATxmega128A1 Xplain board.\r
+#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.\r
+#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.\r
+#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.\r
+#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.\r
+#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.\r
+#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.\r
+#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.\r
+#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.\r
+#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board\r
+#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board\r
+#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board\r
+#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.\r
+#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.\r
+#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.\r
+#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.\r
+#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.\r
+#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.\r
+#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards\r
+#define RZ600 31 //!< AT32UC3A RZ600 MCU board\r
+#define SAM3S_EK 32 //!< SAM3S-EK board.\r
+#define SAM3U_EK 33 //!< SAM3U-EK board.\r
+#define SAM3X_EK 34 //!< SAM3X-EK board.\r
+#define SAM3N_EK 35 //!< SAM3N-EK board.\r
+#define SAM3S_EK2 36 //!< SAM3S-EK2 board.\r
+#define SAM4S_EK 37 //!< SAM4S-EK board.\r
+#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.\r
+#define STK600_MEGA 39 //!< STK600 MEGA board.\r
+#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.\r
+#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.\r
+#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.\r
+#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.\r
+#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board\r
+#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices\r
+#define AVR_SIMULATOR_UC3 98 //!< AVR SIMULATOR for AVR UC3 device family.\r
+#define USER_BOARD 99 //!< User-reserved board (if any).\r
+#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader)\r
+//! @}\r
+\r
+/*! \name Extension Boards\r
+ */\r
+//! @{\r
+#define EXT1102 1 //!< AT32UC3B EXT1102 board\r
+#define MC300 2 //!< AT32UC3 MC300 board\r
+#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1\r
+#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2\r
+#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board\r
+#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board\r
+#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"\r
+#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600\r
+#define RZ600_AT86RF230B 9 //!< AT86RF231 RF board in RZ600\r
+#define RZ600_AT86RF212 10 //!< AT86RF231 RF board in RZ600\r
+#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard\r
+#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board\r
+#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).\r
+//! @}\r
+\r
+#if BOARD == EVK1100\r
+# include "evk1100/evk1100.h"\r
+#elif BOARD == EVK1101\r
+# include "evk1101/evk1101.h"\r
+#elif BOARD == UC3C_EK\r
+# include "uc3c_ek/uc3c_ek.h"\r
+#elif BOARD == EVK1104\r
+# include "evk1104/evk1104.h"\r
+#elif BOARD == EVK1105\r
+# include "evk1105/evk1105.h"\r
+#elif BOARD == STK600_RCUC3L0\r
+# include "stk600/rcuc3l0/stk600_rcuc3l0.h"\r
+#elif BOARD == UC3L_EK\r
+# include "uc3l_ek/uc3l_ek.h"\r
+#elif BOARD == STK600_RCUC3L4\r
+# include "stk600/rcuc3l4/stk600_rcuc3l4.h"\r
+#elif BOARD == XPLAIN\r
+# include "xplain/xplain.h"\r
+#elif BOARD == STK600_MEGA\r
+ /*No header-file to include*/\r
+#elif BOARD == STK600_RC044X\r
+# include "stk600/rc044x/stk600_rc044x.h"\r
+#elif BOARD == STK600_RC064X\r
+# include "stk600/rc064x/stk600_rc064x.h"\r
+#elif BOARD == STK600_RC100X\r
+# include "stk600/rc100x/stk600_rc100x.h"\r
+#elif BOARD == UC3_A3_XPLAINED\r
+# include "uc3_a3_xplained/uc3_a3_xplained.h"\r
+#elif BOARD == UC3_L0_XPLAINED\r
+# include "uc3_l0_xplained/uc3_l0_xplained.h"\r
+#elif BOARD == STK600_RCUC3B0\r
+# include "stk600/rcuc3b0/stk600_rcuc3b0.h"\r
+#elif BOARD == STK600_RCUC3D\r
+# include "stk600/rcuc3d/stk600_rcuc3d.h"\r
+#elif BOARD == STK600_RCUC3C0\r
+# include "stk600/rcuc3c0/stk600_rcuc3c0.h"\r
+#elif BOARD == XMEGA_B1_XPLAINED\r
+# include "xmega_b1_xplained/xmega_b1_xplained.h"\r
+#elif BOARD == STK600_RC064X_LCDX\r
+# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"\r
+#elif BOARD == STK600_RC100X_LCDX\r
+# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"\r
+#elif BOARD == XMEGA_A1_XPLAINED\r
+# include "xmega_a1_xplained/xmega_a1_xplained.h"\r
+#elif BOARD == UC3_L0_XPLAINED_BC\r
+# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"\r
+#elif BOARD == SAM3S_EK\r
+# include "sam3s_ek/sam3s_ek.h"\r
+# include "system_sam3s.h"\r
+#elif BOARD == SAM3S_EK2\r
+# include "sam3s_ek2/sam3s_ek2.h"\r
+# include "system_sam3sd8.h"\r
+#elif BOARD == SAM3U_EK\r
+# include "sam3u_ek/sam3u_ek.h"\r
+# include "system_sam3u.h"\r
+#elif BOARD == SAM3X_EK\r
+# include "sam3x_ek/sam3x_ek.h"\r
+# include "system_sam3x.h"\r
+#elif BOARD == SAM3N_EK\r
+# include "sam3n_ek/sam3n_ek.h"\r
+# include "system_sam3n.h"\r
+#elif BOARD == SAM4S_EK\r
+# include "sam4s_ek/sam4s_ek.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == SAM4S_XPLAINED\r
+# include "sam4s_xplained/sam4s_xplained.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == MEGA_1284P_XPLAINED\r
+ /*No header-file to include*/\r
+#elif BOARD == ARDUINO_DUE_X\r
+# include "arduino_due_x/arduino_due_x.h"\r
+# include "system_sam3x.h"\r
+#elif BOARD == MEGA1284P_XPLAINED_BC\r
+# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"\r
+#elif BOARD == UC3_L0_QT600\r
+# include "uc3_l0_qt600/uc3_l0_qt600.h"\r
+#elif BOARD == XMEGA_A3BU_XPLAINED\r
+# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"\r
+#elif BOARD == UC3B_BOARD_CONTROLLER\r
+# include "uc3b_board_controller/uc3b_board_controller.h"\r
+#elif BOARD == RZ600\r
+# include "rz600/rz600.h"\r
+#elif BOARD == STK600_RCUC3A0\r
+# include "stk600/rcuc3a0/stk600_rcuc3a0.h"\r
+#elif BOARD == ATXMEGA128A1_QT600\r
+# include "atxmega128a1_qt600/atxmega128a1_qt600.h"\r
+#elif BOARD == STK600_RCUC3L3\r
+ #include "stk600/rcuc3l3/stk600_rcuc3l3.h"\r
+#elif BOARD == SIMULATOR_XMEGA_A1\r
+# include "simulator/xmega_a1/simulator_xmega_a1.h"\r
+#elif BOARD == AVR_SIMULATOR_UC3\r
+# include "avr_simulator_uc3/avr_simulator_uc3.h"\r
+#elif BOARD == USER_BOARD\r
+ // User-reserved area: #include the header file of your board here (if any).\r
+# include "user_board.h"\r
+#elif BOARD == DUMMY_BOARD\r
+# include "dummy/dummy_board.h"\r
+#else\r
+# error No known AVR board defined\r
+#endif\r
+\r
+#if (defined EXT_BOARD)\r
+# if EXT_BOARD == MC300\r
+# include "mc300/mc300.h"\r
+# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)\r
+# include "sensors_xplained/sensors_xplained.h"\r
+# elif EXT_BOARD == RZ600_AT86RF231\r
+# include "at86rf231/at86rf231.h"\r
+# elif EXT_BOARD == RZ600_AT86RF230B\r
+# include "at86rf230b/at86rf230b.h"\r
+# elif EXT_BOARD == RZ600_AT86RF212\r
+# include "at86rf212/at86rf212.h"\r
+# elif EXT_BOARD == SECURITY_XPLAINED\r
+# include "security_xplained.h"\r
+# elif EXT_BOARD == USER_EXT_BOARD\r
+ // User-reserved area: #include the header file of your extension board here\r
+ // (if any).\r
+# endif\r
+#endif\r
+\r
+\r
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+/*! \brief This function initializes the board target resources\r
+ *\r
+ * This function should be called to ensure proper initialization of the target\r
+ * board hardware connected to the part.\r
+ */\r
+extern void board_init(void);\r
+\r
+#endif // #ifdef __AVR32_ABI_COMPILER__\r
+#else\r
+/*! \brief This function initializes the board target resources\r
+ *\r
+ * This function should be called to ensure proper initialization of the target\r
+ * board hardware connected to the part.\r
+ */\r
+extern void board_init(void);\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _BOARD_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Generic clock management\r
+ *\r
+ * Copyright (c) 2010-2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef CLK_GENCLK_H_INCLUDED\r
+#define CLK_GENCLK_H_INCLUDED\r
+\r
+#include "parts.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/genclk.h"\r
+#elif SAM3U\r
+# include "sam3u/genclk.h"\r
+#elif SAM3N\r
+# include "sam3n/genclk.h"\r
+#elif SAM3XA\r
+# include "sam3x/genclk.h"\r
+#elif SAM4S\r
+# include "sam4s/genclk.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/genclk.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/genclk.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/genclk.h"\r
+#elif UC3C\r
+# include "uc3c/genclk.h"\r
+#elif UC3D\r
+# include "uc3d/genclk.h"\r
+#elif UC3L\r
+# include "uc3l/genclk.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup genclk_group Generic Clock Management\r
+ *\r
+ * Generic clocks are configurable clocks which run outside the system\r
+ * clock domain. They are often connected to peripherals which have an\r
+ * asynchronous component running independently of the bus clock, e.g.\r
+ * USB controllers, low-power timers and RTCs, etc.\r
+ *\r
+ * Note that not all platforms have support for generic clocks; on such\r
+ * platforms, this API will not be available.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \def GENCLK_DIV_MAX\r
+ * \brief Maximum divider supported by the generic clock implementation\r
+ */\r
+/**\r
+ * \enum genclk_source\r
+ * \brief Generic clock source ID\r
+ *\r
+ * Each generic clock may be generated from a different clock source.\r
+ * These are the available alternatives provided by the chip.\r
+ */\r
+\r
+//! \name Generic clock configuration\r
+//@{\r
+/**\r
+ * \struct genclk_config\r
+ * \brief Hardware representation of a set of generic clock parameters\r
+ */\r
+/**\r
+ * \fn void genclk_config_defaults(struct genclk_config *cfg,\r
+ * unsigned int id)\r
+ * \brief Initialize \a cfg to the default configuration for the clock\r
+ * identified by \a id.\r
+ */\r
+/**\r
+ * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id)\r
+ * \brief Read the currently active configuration of the clock\r
+ * identified by \a id into \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_config_write(const struct genclk_config *cfg,\r
+ * unsigned int id)\r
+ * \brief Activate the configuration \a cfg on the clock identified by\r
+ * \a id.\r
+ */\r
+/**\r
+ * \fn void genclk_config_set_source(struct genclk_config *cfg,\r
+ * enum genclk_source src)\r
+ * \brief Select a new source clock \a src in configuration \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_config_set_divider(struct genclk_config *cfg,\r
+ * unsigned int divider)\r
+ * \brief Set a new \a divider in configuration \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_enable_source(enum genclk_source src)\r
+ * \brief Enable the source clock \a src used by a generic clock.\r
+ */\r
+ //@}\r
+\r
+//! \name Enabling and disabling Generic Clocks\r
+//@{\r
+/**\r
+ * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id)\r
+ * \brief Activate the configuration \a cfg on the clock identified by\r
+ * \a id and enable it.\r
+ */\r
+/**\r
+ * \fn void genclk_disable(unsigned int id)\r
+ * \brief Disable the generic clock identified by \a id.\r
+ */\r
+//@}\r
+\r
+/**\r
+ * \brief Enable the configuration defined by \a src and \a divider\r
+ * for the generic clock identified by \a id.\r
+ *\r
+ * \param id The ID of the generic clock.\r
+ * \param src The source clock of the generic clock.\r
+ * \param divider The divider used to generate the generic clock.\r
+ */\r
+static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider)\r
+{\r
+ struct genclk_config gcfg;\r
+\r
+ genclk_config_defaults(&gcfg, id);\r
+ genclk_enable_source(src);\r
+ genclk_config_set_source(&gcfg, src);\r
+ genclk_config_set_divider(&gcfg, divider);\r
+ genclk_enable(&gcfg, id);\r
+}\r
+\r
+//! @}\r
+\r
+#endif /* CLK_GENCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Oscillator management\r
+ *\r
+ * Copyright (c) 2010 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef OSC_H_INCLUDED\r
+#define OSC_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/osc.h"\r
+#elif SAM3XA\r
+# include "sam3x/osc.h"\r
+#elif SAM3U\r
+# include "sam3u/osc.h"\r
+#elif SAM3N\r
+# include "sam3n/osc.h"\r
+#elif SAM4S\r
+# include "sam4s/osc.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/osc.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/osc.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/osc.h"\r
+#elif UC3C\r
+# include "uc3c/osc.h"\r
+#elif UC3D\r
+# include "uc3d/osc.h"\r
+#elif UC3L\r
+# include "uc3l/osc.h"\r
+#elif XMEGA\r
+# include "xmega/osc.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup osc_group Oscillator Management\r
+ *\r
+ * This group contains functions and definitions related to configuring\r
+ * and enabling/disabling on-chip oscillators. Internal RC-oscillators,\r
+ * external crystal oscillators and external clock generators are\r
+ * supported by this module. What all of these have in common is that\r
+ * they swing at a fixed, nominal frequency which is normally not\r
+ * adjustable.\r
+ *\r
+ * \par Example: Enabling an oscillator\r
+ *\r
+ * The following example demonstrates how to enable the external\r
+ * oscillator on XMEGA A and wait for it to be ready to use. The\r
+ * oscillator identifiers are platform-specific, so while the same\r
+ * procedure is used on all platforms, the parameter to osc_enable()\r
+ * will be different from device to device.\r
+ * \code\r
+ osc_enable(OSC_ID_XOSC);\r
+ osc_wait_ready(OSC_ID_XOSC); \endcode\r
+ *\r
+ * \section osc_group_board Board-specific Definitions\r
+ * If external oscillators are used, the board code must provide the\r
+ * following definitions for each of those:\r
+ * - \b BOARD_<osc name>_HZ: The nominal frequency of the oscillator.\r
+ * - \b BOARD_<osc name>_STARTUP_US: The startup time of the\r
+ * oscillator in microseconds.\r
+ * - \b BOARD_<osc name>_TYPE: The type of oscillator connected, i.e.\r
+ * whether it's a crystal or external clock, and sometimes what kind\r
+ * of crystal it is. The meaning of this value is platform-specific.\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name Oscillator Management\r
+//@{\r
+/**\r
+ * \fn void osc_enable(uint8_t id)\r
+ * \brief Enable oscillator \a id\r
+ *\r
+ * The startup time and mode value is automatically determined based on\r
+ * definitions in the board code.\r
+ */\r
+/**\r
+ * \fn void osc_disable(uint8_t id)\r
+ * \brief Disable oscillator \a id\r
+ */\r
+/**\r
+ * \fn osc_is_ready(uint8_t id)\r
+ * \brief Determine whether oscillator \a id is ready.\r
+ * \retval true Oscillator \a id is running and ready to use as a clock\r
+ * source.\r
+ * \retval false Oscillator \a id is not running.\r
+ */\r
+/**\r
+ * \fn uint32_t osc_get_rate(uint8_t id)\r
+ * \brief Return the frequency of oscillator \a id in Hz\r
+ */\r
+\r
+#ifndef __ASSEMBLY__\r
+\r
+/**\r
+ * \brief Wait until the oscillator identified by \a id is ready\r
+ *\r
+ * This function will busy-wait for the oscillator identified by \a id\r
+ * to become stable and ready to use as a clock source.\r
+ *\r
+ * \param id A number identifying the oscillator to wait for.\r
+ */\r
+static inline void osc_wait_ready(uint8_t id)\r
+{\r
+ while (!osc_is_ready(id)) {\r
+ /* Do nothing */\r
+ }\r
+}\r
+\r
+#endif /* __ASSEMBLY__ */\r
+\r
+//@}\r
+\r
+//! @}\r
+\r
+#endif /* OSC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief PLL management\r
+ *\r
+ * Copyright (c) 2010-2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef CLK_PLL_H_INCLUDED\r
+#define CLK_PLL_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/pll.h"\r
+#elif SAM3XA\r
+# include "sam3x/pll.h"\r
+#elif SAM3U\r
+# include "sam3u/pll.h"\r
+#elif SAM3N\r
+# include "sam3n/pll.h"\r
+#elif SAM4S\r
+# include "sam4s/pll.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/pll.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/pll.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/pll.h"\r
+#elif UC3C\r
+# include "uc3c/pll.h"\r
+#elif UC3D\r
+# include "uc3d/pll.h"\r
+#elif (UC3L0128 || UC3L0256 || UC3L3_L4)\r
+# include "uc3l/pll.h"\r
+#elif XMEGA\r
+# include "xmega/pll.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup pll_group PLL Management\r
+ *\r
+ * This group contains functions and definitions related to configuring\r
+ * and enabling/disabling on-chip PLLs. A PLL will take an input signal\r
+ * (the \em source), optionally divide the frequency by a configurable\r
+ * \em divider, and then multiply the frequency by a configurable \em\r
+ * multiplier.\r
+ *\r
+ * Some devices don't support input dividers; specifying any other\r
+ * divisor than 1 on these devices will result in an assertion failure.\r
+ * Other devices may have various restrictions to the frequency range of\r
+ * the input and output signals.\r
+ *\r
+ * \par Example: Setting up PLL0 with default parameters\r
+ *\r
+ * The following example shows how to configure and enable PLL0 using\r
+ * the default parameters specified using the configuration symbols\r
+ * listed above.\r
+ * \code\r
+ pll_enable_config_defaults(0); \endcode\r
+ *\r
+ * To configure, enable PLL0 using the default parameters and to disable\r
+ * a specific feature like Wide Bandwidth Mode (a UC3A3-specific\r
+ * PLL option.), you can use this initialization process.\r
+ * \code\r
+ struct pll_config pllcfg;\r
+ if (pll_is_locked(pll_id)) {\r
+ return; // Pll already running\r
+ }\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0); \endcode\r
+ *\r
+ * When the last function call returns, PLL0 is ready to be used as the\r
+ * main system clock source.\r
+ *\r
+ * \section pll_group_config Configuration Symbols\r
+ *\r
+ * Each PLL has a set of default parameters determined by the following\r
+ * configuration symbols in the application's configuration file:\r
+ * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the\r
+ * input of PLL \a n. Must be one of the values defined by the\r
+ * #pll_source enum.\r
+ * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL\r
+ * \a n.\r
+ * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n.\r
+ *\r
+ * These configuration symbols determine the result of calling\r
+ * pll_config_defaults() and pll_get_default_rate().\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name Chip-specific PLL characteristics\r
+//@{\r
+/**\r
+ * \def PLL_MAX_STARTUP_CYCLES\r
+ * \brief Maximum PLL startup time in number of slow clock cycles\r
+ */\r
+/**\r
+ * \def NR_PLLS\r
+ * \brief Number of on-chip PLLs\r
+ */\r
+\r
+/**\r
+ * \def PLL_MIN_HZ\r
+ * \brief Minimum frequency that the PLL can generate\r
+ */\r
+/**\r
+ * \def PLL_MAX_HZ\r
+ * \brief Maximum frequency that the PLL can generate\r
+ */\r
+/**\r
+ * \def PLL_NR_OPTIONS\r
+ * \brief Number of PLL option bits\r
+ */\r
+//@}\r
+\r
+/**\r
+ * \enum pll_source\r
+ * \brief PLL clock source\r
+ */\r
+\r
+//! \name PLL configuration\r
+//@{\r
+\r
+/**\r
+ * \struct pll_config\r
+ * \brief Hardware-specific representation of PLL configuration.\r
+ *\r
+ * This structure contains one or more device-specific values\r
+ * representing the current PLL configuration. The contents of this\r
+ * structure is typically different from platform to platform, and the\r
+ * user should not access any fields except through the PLL\r
+ * configuration API.\r
+ */\r
+\r
+/**\r
+ * \fn void pll_config_init(struct pll_config *cfg,\r
+ * enum pll_source src, unsigned int div, unsigned int mul)\r
+ * \brief Initialize PLL configuration from standard parameters.\r
+ *\r
+ * \note This function may be defined inline because it is assumed to be\r
+ * called very few times, and usually with constant parameters. Inlining\r
+ * it will in such cases reduce the code size significantly.\r
+ *\r
+ * \param cfg The PLL configuration to be initialized.\r
+ * \param src The oscillator to be used as input to the PLL.\r
+ * \param div PLL input divider.\r
+ * \param mul PLL loop divider (i.e. multiplier).\r
+ *\r
+ * \return A configuration which will make the PLL run at\r
+ * (\a mul / \a div) times the frequency of \a src\r
+ */\r
+/**\r
+ * \def pll_config_defaults(cfg, pll_id)\r
+ * \brief Initialize PLL configuration using default parameters.\r
+ *\r
+ * After this function returns, \a cfg will contain a configuration\r
+ * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV)\r
+ * times the frequency of CONFIG_PLLx_SOURCE.\r
+ *\r
+ * \param cfg The PLL configuration to be initialized.\r
+ * \param pll_id Use defaults for this PLL.\r
+ */\r
+/**\r
+ * \def pll_get_default_rate(pll_id)\r
+ * \brief Get the default rate in Hz of \a pll_id\r
+ */\r
+/**\r
+ * \fn void pll_config_set_option(struct pll_config *cfg,\r
+ * unsigned int option)\r
+ * \brief Set the PLL option bit \a option in the configuration \a cfg.\r
+ *\r
+ * \param cfg The PLL configuration to be changed.\r
+ * \param option The PLL option bit to be set.\r
+ */\r
+/**\r
+ * \fn void pll_config_clear_option(struct pll_config *cfg,\r
+ * unsigned int option)\r
+ * \brief Clear the PLL option bit \a option in the configuration \a cfg.\r
+ *\r
+ * \param cfg The PLL configuration to be changed.\r
+ * \param option The PLL option bit to be cleared.\r
+ */\r
+/**\r
+ * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id)\r
+ * \brief Read the currently active configuration of \a pll_id.\r
+ *\r
+ * \param cfg The configuration object into which to store the currently\r
+ * active configuration.\r
+ * \param pll_id The ID of the PLL to be accessed.\r
+ */\r
+/**\r
+ * \fn void pll_config_write(const struct pll_config *cfg,\r
+ * unsigned int pll_id)\r
+ * \brief Activate the configuration \a cfg on \a pll_id\r
+ *\r
+ * \param cfg The configuration object representing the PLL\r
+ * configuration to be activated.\r
+ * \param pll_id The ID of the PLL to be updated.\r
+ */\r
+\r
+//@}\r
+\r
+//! \name Interaction with the PLL hardware\r
+//@{\r
+/**\r
+ * \fn void pll_enable(const struct pll_config *cfg,\r
+ * unsigned int pll_id)\r
+ * \brief Activate the configuration \a cfg and enable PLL \a pll_id.\r
+ *\r
+ * \param cfg The PLL configuration to be activated.\r
+ * \param pll_id The ID of the PLL to be enabled.\r
+ */\r
+/**\r
+ * \fn void pll_disable(unsigned int pll_id)\r
+ * \brief Disable the PLL identified by \a pll_id.\r
+ *\r
+ * After this function is called, the PLL identified by \a pll_id will\r
+ * be disabled. The PLL configuration stored in hardware may be affected\r
+ * by this, so if the caller needs to restore the same configuration\r
+ * later, it should either do a pll_config_read() before disabling the\r
+ * PLL, or remember the last configuration written to the PLL.\r
+ *\r
+ * \param pll_id The ID of the PLL to be disabled.\r
+ */\r
+/**\r
+ * \fn bool pll_is_locked(unsigned int pll_id)\r
+ * \brief Determine whether the PLL is locked or not.\r
+ *\r
+ * \param pll_id The ID of the PLL to check.\r
+ *\r
+ * \retval true The PLL is locked and ready to use as a clock source\r
+ * \retval false The PLL is not yet locked, or has not been enabled.\r
+ */\r
+/**\r
+ * \fn void pll_enable_source(enum pll_source src)\r
+ * \brief Enable the source of the pll.\r
+ * The source is enabled, if the source is not already running.\r
+ *\r
+ * \param src The ID of the PLL source to enable.\r
+ */\r
+/**\r
+ * \fn void pll_enable_config_defaults(unsigned int pll_id)\r
+ * \brief Enable the pll with the default configuration.\r
+ * PLL is enabled, if the PLL is not already locked.\r
+ *\r
+ * \param pll_id The ID of the PLL to enable.\r
+ */\r
+\r
+/**\r
+ * \brief Wait for PLL \a pll_id to become locked\r
+ *\r
+ * \todo Use a timeout to avoid waiting forever and hanging the system\r
+ *\r
+ * \param pll_id The ID of the PLL to wait for.\r
+ *\r
+ * \retval STATUS_OK The PLL is now locked.\r
+ * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.\r
+ */\r
+static inline int pll_wait_for_lock(unsigned int pll_id)\r
+{\r
+ Assert(pll_id < NR_PLLS);\r
+\r
+ while (!pll_is_locked(pll_id)) {\r
+ /* Do nothing */\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+//@}\r
+//! @}\r
+\r
+#endif /* CLK_PLL_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific generic clock management.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_GENCLK_H_INCLUDED\r
+#define CHIP_GENCLK_H_INCLUDED\r
+\r
+#if (SAM3S8 || SAM3SD8)\r
+# include <osc.h>\r
+# include <pll.h>\r
+#else\r
+# include <osc.h>\r
+# include <pll.h>\r
+#endif\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup genclk_group\r
+ * @{\r
+ */\r
+\r
+//! \name Programmable Clock Identifiers (PCK)\r
+//@{\r
+#define GENCLK_PCK_0 0 //!< PCK0 ID\r
+#define GENCLK_PCK_1 1 //!< PCK1 ID\r
+#define GENCLK_PCK_2 2 //!< PCK2 ID\r
+//@}\r
+\r
+//! \name Programmable Clock Sources (PCK)\r
+//@{\r
+\r
+enum genclk_source {\r
+ GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock\r
+ GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock\r
+};\r
+\r
+//@}\r
+\r
+//! \name Programmable Clock Prescalers (PCK)\r
+//@{\r
+\r
+enum genclk_divider {\r
+ GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1\r
+ GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2\r
+ GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4\r
+ GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8\r
+ GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16\r
+ GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32\r
+ GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64\r
+};\r
+\r
+//@}\r
+\r
+struct genclk_config {\r
+ uint32_t ctrl;\r
+};\r
+\r
+static inline void genclk_config_defaults(struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ ul_id = ul_id;\r
+ p_cfg->ctrl = 0;\r
+}\r
+\r
+static inline void genclk_config_read(struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ p_cfg->ctrl = PMC->PMC_PCK[ul_id];\r
+}\r
+\r
+static inline void genclk_config_write(const struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
+}\r
+\r
+//! \name Programmable Clock Source and Prescaler configuration\r
+//@{\r
+\r
+static inline void genclk_config_set_source(struct genclk_config *p_cfg,\r
+ enum genclk_source e_src)\r
+{\r
+ p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);\r
+\r
+ switch (e_src) {\r
+ case GENCLK_PCK_SRC_SLCK_RC:\r
+ case GENCLK_PCK_SRC_SLCK_XTAL:\r
+ case GENCLK_PCK_SRC_SLCK_BYPASS:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_SLOW_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_XTAL:\r
+ case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_MAIN_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_PLLACK:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_PLLA_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_PLLBCK:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_PLLB_CLK);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void genclk_config_set_divider(struct genclk_config *p_cfg,\r
+ uint32_t e_divider)\r
+{\r
+ p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;\r
+ p_cfg->ctrl |= e_divider; \r
+}\r
+\r
+//@}\r
+\r
+static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)\r
+{\r
+ PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
+ pmc_enable_pck(ul_id);\r
+}\r
+\r
+static inline void genclk_disable(uint32_t ul_id)\r
+{\r
+ pmc_disable_pck(ul_id);\r
+}\r
+\r
+static inline void genclk_enable_source(enum genclk_source e_src)\r
+{\r
+ switch (e_src) {\r
+ case GENCLK_PCK_SRC_SLCK_RC:\r
+ if (!osc_is_ready(OSC_SLCK_32K_RC)) {\r
+ osc_enable(OSC_SLCK_32K_RC);\r
+ osc_wait_ready(OSC_SLCK_32K_RC);\r
+ } \r
+ break;\r
+ \r
+ case GENCLK_PCK_SRC_SLCK_XTAL:\r
+ if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {\r
+ osc_enable(OSC_SLCK_32K_XTAL);\r
+ osc_wait_ready(OSC_SLCK_32K_XTAL);\r
+ }\r
+ break;\r
+ \r
+ case GENCLK_PCK_SRC_SLCK_BYPASS:\r
+ if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {\r
+ osc_enable(OSC_SLCK_32K_BYPASS);\r
+ osc_wait_ready(OSC_SLCK_32K_BYPASS); \r
+ } \r
+ break;\r
+ \r
+ case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_4M_RC)) {\r
+ osc_enable(OSC_MAINCK_4M_RC);\r
+ osc_wait_ready(OSC_MAINCK_4M_RC); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_8M_RC)) {\r
+ osc_enable(OSC_MAINCK_8M_RC);\r
+ osc_wait_ready(OSC_MAINCK_8M_RC); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_12M_RC)) {\r
+ osc_enable(OSC_MAINCK_12M_RC);\r
+ osc_wait_ready(OSC_MAINCK_12M_RC); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_XTAL:\r
+ if (!osc_is_ready(OSC_MAINCK_XTAL)) {\r
+ osc_enable(OSC_MAINCK_XTAL);\r
+ osc_wait_ready(OSC_MAINCK_XTAL); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
+ if (!osc_is_ready(OSC_MAINCK_BYPASS)) {\r
+ osc_enable(OSC_MAINCK_BYPASS);\r
+ osc_wait_ready(OSC_MAINCK_BYPASS); \r
+ } \r
+ break;\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case GENCLK_PCK_SRC_PLLACK:\r
+ pll_enable_config_defaults(0); \r
+ break; \r
+#endif\r
+\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case GENCLK_PCK_SRC_PLLBCK:\r
+ pll_enable_config_defaults(1); \r
+ break; \r
+#endif \r
+\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_GENCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific oscillator management functions.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_OSC_H_INCLUDED\r
+#define CHIP_OSC_H_INCLUDED\r
+\r
+#include "board.h"\r
+#include "pmc.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup osc_group\r
+ * @{\r
+ */\r
+\r
+//! \name Oscillator identifiers\r
+//@{\r
+#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator.\r
+#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator.\r
+#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator.\r
+#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator.\r
+#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator.\r
+#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator.\r
+#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator.\r
+#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator.\r
+//@}\r
+\r
+//! \name Oscillator clock speed in hertz\r
+//@{\r
+#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator.\r
+#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator.\r
+#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator.\r
+#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator.\r
+#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator.\r
+#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator.\r
+#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator.\r
+#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator.\r
+//@}\r
+\r
+static inline void osc_enable(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ break;\r
+\r
+ case OSC_SLCK_32K_XTAL:\r
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_SLCK_32K_BYPASS:\r
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS);\r
+ break;\r
+\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ break;\r
+\r
+ case OSC_MAINCK_8M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ break;\r
+\r
+ case OSC_MAINCK_12M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ break;\r
+\r
+\r
+ case OSC_MAINCK_XTAL:\r
+ pmc_switch_mainck_to_xtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_MAINCK_BYPASS:\r
+ pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void osc_disable(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ case OSC_SLCK_32K_XTAL:\r
+ case OSC_SLCK_32K_BYPASS:\r
+ break;\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ case OSC_MAINCK_8M_RC:\r
+ case OSC_MAINCK_12M_RC:\r
+ pmc_osc_disable_fastrc();\r
+ break;\r
+\r
+ case OSC_MAINCK_XTAL:\r
+ pmc_osc_disable_xtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_MAINCK_BYPASS:\r
+ pmc_osc_disable_xtal(PMC_OSC_BYPASS);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline bool osc_is_ready(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ return 1;\r
+\r
+ case OSC_SLCK_32K_XTAL:\r
+ case OSC_SLCK_32K_BYPASS:\r
+ return pmc_osc_is_ready_32kxtal();\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ case OSC_MAINCK_8M_RC:\r
+ case OSC_MAINCK_12M_RC:\r
+ case OSC_MAINCK_XTAL:\r
+ case OSC_MAINCK_BYPASS:\r
+ return pmc_osc_is_ready_mainck();\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+static inline uint32_t osc_get_rate(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ return OSC_SLCK_32K_RC_HZ;\r
+\r
+#ifdef BOARD_FREQ_SLCK_XTAL\r
+ case OSC_SLCK_32K_XTAL:\r
+ return BOARD_FREQ_SLCK_XTAL;\r
+#endif\r
+\r
+#ifdef BOARD_FREQ_SLCK_BYPASS\r
+ case OSC_SLCK_32K_BYPASS:\r
+ return BOARD_FREQ_SLCK_BYPASS;\r
+#endif\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+\r
+ case OSC_MAINCK_8M_RC:\r
+ return OSC_MAINCK_8M_RC_HZ;\r
+\r
+ case OSC_MAINCK_12M_RC:\r
+ return OSC_MAINCK_12M_RC_HZ;\r
+\r
+#ifdef BOARD_FREQ_MAINCK_XTAL\r
+ case OSC_MAINCK_XTAL:\r
+ return BOARD_FREQ_MAINCK_XTAL;\r
+#endif\r
+\r
+#ifdef BOARD_FREQ_MAINCK_BYPASS\r
+ case OSC_MAINCK_BYPASS:\r
+ return BOARD_FREQ_MAINCK_BYPASS;\r
+#endif\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_OSC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific PLL definitions.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_PLL_H_INCLUDED\r
+#define CHIP_PLL_H_INCLUDED\r
+\r
+#include <osc.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup pll_group\r
+ * @{\r
+ */\r
+\r
+#define PLL_OUTPUT_MIN_HZ 60000000\r
+#define PLL_OUTPUT_MAX_HZ 130000000\r
+\r
+#define PLL_INPUT_MIN_HZ 3500000\r
+#define PLL_INPUT_MAX_HZ 20000000\r
+\r
+#define NR_PLLS 2\r
+#define PLLA_ID 0\r
+#define PLLB_ID 1\r
+\r
+#define PLL_COUNT 0x3fU\r
+\r
+enum pll_source {\r
+ PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator.\r
+ PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator.\r
+ PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator.\r
+ PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator.\r
+ PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator.\r
+ PLL_NR_SOURCES, //!< Number of PLL sources.\r
+};\r
+\r
+struct pll_config {\r
+ uint32_t ctrl;\r
+};\r
+\r
+#define pll_get_default_rate(pll_id) \\r
+ ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \\r
+ * CONFIG_PLL##pll_id##_MUL) \\r
+ / CONFIG_PLL##pll_id##_DIV)\r
+\r
+/**\r
+ * \note The SAM3S PLL hardware interprets mul as mul+1. For readability the hardware mul+1\r
+ * is hidden in this implementation. Use mul as mul effective value.\r
+ */\r
+static inline void pll_config_init(struct pll_config *p_cfg,\r
+ enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)\r
+{\r
+ uint32_t vco_hz;\r
+\r
+ Assert(e_src < PLL_NR_SOURCES);\r
+\r
+ /* Calculate internal VCO frequency */\r
+ vco_hz = osc_get_rate(e_src) / ul_div;\r
+ Assert(vco_hz >= PLL_INPUT_MIN_HZ);\r
+ Assert(vco_hz <= PLL_INPUT_MAX_HZ);\r
+ \r
+ vco_hz *= ul_mul;\r
+ Assert(vco_hz >= PLL_OUTPUT_MIN_HZ);\r
+ Assert(vco_hz <= PLL_OUTPUT_MAX_HZ);\r
+\r
+ /* PMC hardware will automatically make it mul+1 */\r
+ p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) | CKGR_PLLAR_PLLACOUNT(PLL_COUNT);\r
+}\r
+\r
+#define pll_config_defaults(cfg, pll_id) \\r
+ pll_config_init(cfg, \\r
+ CONFIG_PLL##pll_id##_SOURCE, \\r
+ CONFIG_PLL##pll_id##_DIV, \\r
+ CONFIG_PLL##pll_id##_MUL)\r
+\r
+static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+\r
+ if (ul_pll_id == PLLA_ID)\r
+ p_cfg->ctrl = PMC->CKGR_PLLAR;\r
+ else\r
+ p_cfg->ctrl = PMC->CKGR_PLLBR;\r
+}\r
+\r
+static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID) {\r
+ pmc_disable_pllack(); // Always stop PLL first!\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;\r
+ } else {\r
+ pmc_disable_pllbck();\r
+ PMC->CKGR_PLLBR = p_cfg->ctrl;\r
+ }\r
+}\r
+\r
+static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID) {\r
+ pmc_disable_pllack(); // Always stop PLL first!\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;\r
+ } else {\r
+ pmc_disable_pllbck();\r
+ PMC->CKGR_PLLBR = p_cfg->ctrl;\r
+ }\r
+}\r
+\r
+/** \r
+ * \note This will only disable the selected PLL, not the underlying oscillator (mainck).\r
+ */\r
+static inline void pll_disable(uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID)\r
+ pmc_disable_pllack();\r
+ else\r
+ pmc_disable_pllbck();\r
+}\r
+\r
+static inline uint32_t pll_is_locked(uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID)\r
+ return pmc_is_locked_pllack();\r
+ else\r
+ return pmc_is_locked_pllbck();\r
+}\r
+\r
+static inline void pll_enable_source(enum pll_source e_src)\r
+{\r
+ switch (e_src) {\r
+ case PLL_SRC_MAINCK_4M_RC:\r
+ case PLL_SRC_MAINCK_8M_RC:\r
+ case PLL_SRC_MAINCK_12M_RC:\r
+ case PLL_SRC_MAINCK_XTAL:\r
+ case PLL_SRC_MAINCK_BYPASS:\r
+ osc_enable(e_src);\r
+ osc_wait_ready(e_src);\r
+ break;\r
+\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void pll_enable_config_defaults(unsigned int ul_pll_id)\r
+{\r
+ struct pll_config pllcfg;\r
+\r
+ if (pll_is_locked(ul_pll_id)) {\r
+ return; // Pll already running\r
+ }\r
+ switch (ul_pll_id) {\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case 0:\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_init(&pllcfg,\r
+ CONFIG_PLL0_SOURCE,\r
+ CONFIG_PLL0_DIV,\r
+ CONFIG_PLL0_MUL);\r
+ break;\r
+#endif\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case 1:\r
+ pll_enable_source(CONFIG_PLL1_SOURCE);\r
+ pll_config_init(&pllcfg,\r
+ CONFIG_PLL1_SOURCE,\r
+ CONFIG_PLL1_DIV,\r
+ CONFIG_PLL1_MUL);\r
+ break;\r
+#endif\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+ pll_enable(&pllcfg, ul_pll_id);\r
+ while (!pll_is_locked(ul_pll_id));\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_PLL_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific system clock management functions.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include <sysclk.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup sysclk_group\r
+ * @{\r
+ */\r
+\r
+#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+/**\r
+ * \brief boolean signalling that the sysclk_init is done.\r
+ */\r
+uint32_t sysclk_initialized = 0;\r
+#endif\r
+\r
+/**\r
+ * \brief Set system clock prescaler configuration\r
+ *\r
+ * This function will change the system clock prescaler configuration to\r
+ * match the parameters.\r
+ *\r
+ * \note The parameters to this function are device-specific.\r
+ *\r
+ * \param cpu_shift The CPU clock will be divided by \f$2^{mck\_pres}\f$\r
+ */\r
+void sysclk_set_prescalers(uint32_t ul_pres)\r
+{\r
+ pmc_mck_set_prescaler(ul_pres);\r
+ SystemCoreClockUpdate();\r
+}\r
+\r
+/**\r
+ * \brief Change the source of the main system clock.\r
+ *\r
+ * \param src The new system clock source. Must be one of the constants\r
+ * from the <em>System Clock Sources</em> section.\r
+ */\r
+void sysclk_set_source(uint32_t ul_src)\r
+{\r
+ switch (ul_src) {\r
+ case SYSCLK_SRC_SLCK_RC:\r
+ case SYSCLK_SRC_SLCK_XTAL:\r
+ case SYSCLK_SRC_SLCK_BYPASS:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_4M_RC:\r
+ case SYSCLK_SRC_MAINCK_8M_RC:\r
+ case SYSCLK_SRC_MAINCK_12M_RC:\r
+ case SYSCLK_SRC_MAINCK_XTAL:\r
+ case SYSCLK_SRC_MAINCK_BYPASS:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_PLLACK:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_PLLBCK:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_PLLB_CLK);\r
+ break;\r
+ }\r
+\r
+ SystemCoreClockUpdate();\r
+}\r
+\r
+#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)\r
+/**\r
+ * \brief Enable USB clock.\r
+ *\r
+ * \note The SAM3S UDP hardware interprets div as div+1. For readability the hardware div+1\r
+ * is hidden in this implementation. Use div as div effective value.\r
+ *\r
+ * \param pll_id Source of the USB clock.\r
+ * \param div Actual clock divisor. Must be superior to 0.\r
+ */\r
+void sysclk_enable_usb(void)\r
+{\r
+ Assert(CONFIG_USBCLK_DIV > 0);\r
+\r
+ switch (CONFIG_USBCLK_SOURCE) {\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case USBCLK_SRC_PLL0: {\r
+ struct pll_config pllcfg;\r
+\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0);\r
+ pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1);\r
+ pmc_enable_udpck();\r
+ break;\r
+ }\r
+#endif\r
+\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case USBCLK_SRC_PLL1: {\r
+ struct pll_config pllcfg;\r
+\r
+ pll_enable_source(CONFIG_PLL1_SOURCE);\r
+ pll_config_defaults(&pllcfg, 1);\r
+ pll_enable(&pllcfg, 1);\r
+ pll_wait_for_lock(1);\r
+ pmc_switch_udpck_to_pllbck(CONFIG_USBCLK_DIV - 1);\r
+ pmc_enable_udpck();\r
+ break;\r
+ }\r
+#endif\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable the USB clock.\r
+ *\r
+ * \note This implementation does not switch off the PLL, it just turns off the USB clock.\r
+ */\r
+void sysclk_disable_usb(void)\r
+{\r
+ pmc_disable_udpck();\r
+}\r
+#endif // CONFIG_USBCLK_SOURCE\r
+\r
+void sysclk_init(void)\r
+{\r
+ struct pll_config pllcfg;\r
+\r
+ /* Set a flash wait state depending on the new cpu frequency */\r
+ system_init_flash(sysclk_get_cpu_hz());\r
+\r
+ /* Config system clock setting */\r
+ switch (CONFIG_SYSCLK_SOURCE) {\r
+ case SYSCLK_SRC_SLCK_RC:\r
+ osc_enable(OSC_SLCK_32K_RC);\r
+ osc_wait_ready(OSC_SLCK_32K_RC); \r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ break;\r
+ \r
+ case SYSCLK_SRC_SLCK_XTAL:\r
+ osc_enable(OSC_SLCK_32K_XTAL);\r
+ osc_wait_ready(OSC_SLCK_32K_XTAL); \r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ break;\r
+ \r
+ case SYSCLK_SRC_SLCK_BYPASS:\r
+ osc_enable(OSC_SLCK_32K_BYPASS);\r
+ osc_wait_ready(OSC_SLCK_32K_BYPASS); \r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ break;\r
+ \r
+ case SYSCLK_SRC_MAINCK_4M_RC:\r
+ /* Already running from SYSCLK_SRC_MAINCK_4M_RC */\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_8M_RC:\r
+ osc_enable(OSC_MAINCK_8M_RC);\r
+ osc_wait_ready(OSC_MAINCK_8M_RC); \r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_12M_RC:\r
+ osc_enable(OSC_MAINCK_12M_RC);\r
+ osc_wait_ready(OSC_MAINCK_12M_RC); \r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+\r
+ case SYSCLK_SRC_MAINCK_XTAL:\r
+ osc_enable(OSC_MAINCK_XTAL);\r
+ osc_wait_ready(OSC_MAINCK_XTAL); \r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_BYPASS:\r
+ osc_enable(OSC_MAINCK_BYPASS);\r
+ osc_wait_ready(OSC_MAINCK_BYPASS); \r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case SYSCLK_SRC_PLLACK:\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0);\r
+ pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);\r
+ break; \r
+#endif \r
+\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case SYSCLK_SRC_PLLBCK:\r
+ pll_enable_source(CONFIG_PLL1_SOURCE);\r
+ pll_config_defaults(&pllcfg, 1);\r
+ pll_enable(&pllcfg, 1);\r
+ pll_wait_for_lock(1);\r
+ pmc_switch_mck_to_pllbck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+#endif \r
+ }\r
+\r
+ /* Update the SystemFrequency variable */\r
+ SystemCoreClockUpdate();\r
+ \r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+ /* Signal that the internal frequencies are setup */\r
+ sysclk_initialized = 1;\r
+#endif\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific system clock management functions.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_SYSCLK_H_INCLUDED\r
+#define CHIP_SYSCLK_H_INCLUDED\r
+\r
+#if (SAM3S8 || SAM3SD8)\r
+# include <osc.h>\r
+# include <pll.h>\r
+#else\r
+# include <osc.h>\r
+# include <pll.h>\r
+#endif\r
+\r
+/**\r
+ * \page sysclk_quickstart Quick Start Guide for the System Clock Management service (SAM3S)\r
+ *\r
+ * This is the quick start guide for the \ref sysclk_group "System Clock Management"\r
+ * service, with step-by-step instructions on how to configure and use the service for\r
+ * specific use cases.\r
+ *\r
+ * \section sysclk_quickstart_usecases System Clock Management use cases\r
+ * - \ref sysclk_quickstart_basic\r
+ * - \ref sysclk_quickstart_use_case_2\r
+ *\r
+ * \section sysclk_quickstart_basic Basic usage of the System Clock Management service\r
+ * This section will present a basic use case for the System Clock Management service.\r
+ * This use case will configure the main system clock to 64MHz, using an internal PLL\r
+ * module to multiply the frequency of a crystal attached to the microcontroller.\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites\r
+ * - None\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow\r
+ * -# Configure the system clocks according to the settings in conf_clock.h:\r
+ * \code sysclk_init(); \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_example_code Example code\r
+ * Add or uncomment the following in your conf_clock.h header file, commenting out all other\r
+ * definitions of the same symbol(s):\r
+ * \code\r
+ * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+ *\r
+ * // Fpll0 = (Fclk * PLL_mul) / PLL_div\r
+ * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+ * #define CONFIG_PLL0_MUL (64000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1\r
+ *\r
+ * // Fbus = Fsys / BUS_div\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow\r
+ * -# Configure the main system clock to use the output of the PLL module as its source:\r
+ * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode\r
+ * -# Configure the PLL module to use the fast external fast crystal oscillator as its source:\r
+ * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode\r
+ * -# Configure the PLL module to multiply the external fast crystal oscillator frequency up to 64MHz:\r
+ * \code\r
+ * #define CONFIG_PLL0_MUL (64000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1 \r
+ * \endcode\r
+ * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the board \c conf_board.h configuration\r
+ * file as the frequency of the fast crystal attached to the microcontroller.\r
+ * -# Configure the main clock to run at the full 64MHz, disable scaling of the main system clock speed:\r
+ * \code\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ * \note Some dividers are powers of two, while others are integer division factors. Refer to the\r
+ * formulas in the conf_clock.h template commented above each division define.\r
+ */\r
+\r
+/**\r
+ * \page sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock Management (SAM3S)\r
+ *\r
+ * \section sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock Management\r
+ * This section will present a more advanced use case for the System Clock Management service.\r
+ * This use case will configure the main system clock to 64MHz, using an internal PLL\r
+ * module to multiply the frequency of a crystal attached to the microcontroller. The USB clock\r
+ * will be configured via a separate PLL module.\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_prereq Prerequisites\r
+ * - None\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_setup_steps_workflow Workflow\r
+ * -# Configure the system clocks according to the settings in conf_clock.h:\r
+ * \code sysclk_init(); \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_example_code Example code\r
+ * Add or uncomment the following in your conf_clock.h header file, commenting out all other\r
+ * definitions of the same symbol(s):\r
+ * \code\r
+ * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+ *\r
+ * // Fpll0 = (Fclk * PLL_mul) / PLL_div\r
+ * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+ * #define CONFIG_PLL0_MUL (64000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1\r
+ *\r
+ * // Fbus = Fsys / BUS_div\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ *\r
+ * // Fusb = Fsys / USB_div\r
+ * #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1\r
+ * #define CONFIG_USBCLK_DIV 1\r
+ *\r
+ * // Fpll1 = (Fclk * PLL_mul) / PLL_div\r
+ * #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL\r
+ * #define CONFIG_PLL1_MUL (48000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL1_DIV 1\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_example_workflow Workflow\r
+ * -# Configure the main system clock to use the output of the PLL0 module as its source:\r
+ * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode\r
+ * -# Configure the PLL0 module to use the fast external fast crystal oscillator as its source:\r
+ * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode\r
+ * -# Configure the PLL0 module to multiply the external fast crystal oscillator frequency up to 64MHz:\r
+ * \code\r
+ * #define CONFIG_PLL0_MUL (64000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1 \r
+ * \endcode\r
+ * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the board \c conf_board.h configuration\r
+ * file as the frequency of the fast crystal attached to the microcontroller.\r
+ * -# Configure the main clock to run at the full 64MHz, disable scaling of the main system clock speed:\r
+ * \code\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ * \note Some dividers are powers of two, while others are integer division factors. Refer to the\r
+ * formulas in the conf_clock.h template commented above each division define.\r
+ * -# Configure the USB module clock to use the output of the PLL1 module as its source:\r
+ * \code #define CONFIG_SYSCLK_SOURCE USBCLK_SRC_PLL1 \endcode\r
+ * -# Configure the PLL1 module to use the fast external fast crystal oscillator as its source:\r
+ * \code #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL \endcode\r
+ * -# Configure the PLL1 module to multiply the external fast crystal oscillator frequency up to 48MHz:\r
+ * \code\r
+ * #define CONFIG_PLL1_MUL (48000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL1_DIV 1 \r
+ * \endcode\r
+ */\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup sysclk_group\r
+ * @{\r
+ */\r
+ \r
+//! \name Configuration Symbols\r
+//@{\r
+/**\r
+ * \def CONFIG_SYSCLK_SOURCE\r
+ * \brief Initial/static main system clock source\r
+ *\r
+ * The main system clock will be configured to use this clock during\r
+ * initialization.\r
+ */\r
+#ifndef CONFIG_SYSCLK_SOURCE\r
+# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC\r
+#endif\r
+/**\r
+ * \def CONFIG_SYSCLK_PRES\r
+ * \brief Initial CPU clock divider (mck)\r
+ *\r
+ * The MCK will run at\r
+ * \f[\r
+ * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz}\r
+ * \f]\r
+ * after initialization.\r
+ */\r
+#ifndef CONFIG_SYSCLK_PRES\r
+# define CONFIG_SYSCLK_PRES 0\r
+#endif\r
+\r
+//@}\r
+\r
+//! \name Master Clock Sources (MCK)\r
+//@{\r
+#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock\r
+#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock\r
+#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock\r
+#define SYSCLK_SRC_PLLBCK 9 //!< Use PLLBCK as master source clock\r
+//@}\r
+\r
+//! \name Master Clock Prescalers (MCK)\r
+//@{\r
+#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1\r
+#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2\r
+#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4\r
+#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8\r
+#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16\r
+#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32\r
+#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64\r
+#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3\r
+//@}\r
+\r
+//! \name USB Clock Sources\r
+//@{\r
+#define USBCLK_SRC_PLL0 0 //!< Use PLLA\r
+#define USBCLK_SRC_PLL1 1 //!< Use PLLB\r
+//@}\r
+\r
+/**\r
+ * \def CONFIG_USBCLK_SOURCE\r
+ * \brief Configuration symbol for the USB generic clock source\r
+ *\r
+ * Sets the clock source to use for the USB. The source must also be properly\r
+ * configured.\r
+ *\r
+ * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if\r
+ * USB is not required.\r
+ */\r
+#ifdef __DOXYGEN__\r
+# define CONFIG_USBCLK_SOURCE\r
+#endif\r
+\r
+/**\r
+ * \def CONFIG_USBCLK_DIV\r
+ * \brief Configuration symbol for the USB generic clock divider setting\r
+ *\r
+ * Sets the clock division for the USB generic clock. If a USB clock source is\r
+ * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be\r
+ * defined.\r
+ */\r
+#ifdef __DOXYGEN__\r
+# define CONFIG_USBCLK_DIV\r
+#endif\r
+\r
+/**\r
+ * \name Querying the system clock\r
+ *\r
+ * The following functions may be used to query the current frequency of\r
+ * the system clock and the CPU and bus clocks derived from it.\r
+ * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be\r
+ * available on all platforms, although some platforms may define\r
+ * additional accessors for various chip-internal bus clocks. These are\r
+ * usually not intended to be queried directly by generic code.\r
+ */\r
+//@{\r
+\r
+/**\r
+ * \brief Return the current rate in Hz of the main system clock\r
+ *\r
+ * \todo This function assumes that the main clock source never changes\r
+ * once it's been set up, and that PLL0 always runs at the compile-time\r
+ * configured default rate. While this is probably the most common\r
+ * configuration, which we want to support as a special case for\r
+ * performance reasons, we will at some point need to support more\r
+ * dynamic setups as well.\r
+ */\r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+extern uint32_t sysclk_initialized;\r
+#endif\r
+static inline uint32_t sysclk_get_main_hz(void)\r
+{\r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+ if (!sysclk_initialized ) {\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+ }\r
+#endif\r
+\r
+ /* Config system clock setting */\r
+ switch (CONFIG_SYSCLK_SOURCE) {\r
+ case SYSCLK_SRC_SLCK_RC:\r
+ return OSC_SLCK_32K_RC_HZ;\r
+ \r
+ case SYSCLK_SRC_SLCK_XTAL:\r
+ return OSC_SLCK_32K_XTAL_HZ;\r
+ \r
+ case SYSCLK_SRC_SLCK_BYPASS:\r
+ return OSC_SLCK_32K_BYPASS_HZ;\r
+\r
+\r
+ case SYSCLK_SRC_MAINCK_4M_RC:\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_8M_RC:\r
+ return OSC_MAINCK_8M_RC_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_12M_RC:\r
+ return OSC_MAINCK_12M_RC_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_XTAL:\r
+ return OSC_MAINCK_XTAL_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_BYPASS:\r
+ return OSC_MAINCK_BYPASS_HZ;\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case SYSCLK_SRC_PLLACK:\r
+ return pll_get_default_rate(0); \r
+#endif\r
+\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case SYSCLK_SRC_PLLBCK:\r
+ return pll_get_default_rate(1); \r
+#endif\r
+ \r
+ default:\r
+ /* unhandled_case(CONFIG_SYSCLK_SOURCE); */\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Return the current rate in Hz of the CPU clock\r
+ *\r
+ * \todo This function assumes that the CPU always runs at the system\r
+ * clock frequency. We want to support at least two more scenarios:\r
+ * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus\r
+ * clock dividers (which may change at run time). Ditto for all the bus\r
+ * clocks.\r
+ *\r
+ * \return Frequency of the CPU clock, in Hz.\r
+ */\r
+static inline uint32_t sysclk_get_cpu_hz(void)\r
+{\r
+ /* CONFIG_SYSCLK_PRES is the register value for setting the expected */\r
+ /* prescaler, not an immediate value. */\r
+ return sysclk_get_main_hz() / ((CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos) + 1);\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the current rate in Hz of the peripheral clocks.\r
+ *\r
+ * \return Frequency of the peripheral clocks, in Hz.\r
+ */\r
+static inline uint32_t sysclk_get_peripheral_hz(void)\r
+{\r
+ /* CONFIG_SYSCLK_PRES is the register value for setting the expected */\r
+ /* prescaler, not an immediate value. */\r
+ return sysclk_get_main_hz() / ((CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos) + 1);\r
+}\r
+\r
+//@}\r
+\r
+//! \name Enabling and disabling synchronous clocks\r
+//@{\r
+\r
+/**\r
+ * \brief Enable a peripheral's clock.\r
+ *\r
+ * \param ul_id Id (number) of the peripheral clock.\r
+ */\r
+static inline void sysclk_enable_peripheral_clock(uint32_t ul_id)\r
+{\r
+ pmc_enable_periph_clk(ul_id);\r
+}\r
+\r
+/**\r
+ * \brief Disable a peripheral's clock.\r
+ *\r
+ * \param ul_id Id (number) of the peripheral clock.\r
+ */\r
+static inline void sysclk_disable_peripheral_clock(uint32_t ul_id)\r
+{\r
+ pmc_disable_periph_clk(ul_id);\r
+}\r
+\r
+//@}\r
+\r
+//! \name System Clock Source and Prescaler configuration\r
+//@{\r
+\r
+extern void sysclk_set_prescalers(uint32_t ul_pres);\r
+extern void sysclk_set_source(uint32_t ul_src);\r
+\r
+//@}\r
+\r
+extern void sysclk_enable_usb(void);\r
+extern void sysclk_disable_usb(void);\r
+\r
+extern void sysclk_init(void);\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_SYSCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief System clock management\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SYSCLK_H_INCLUDED\r
+#define SYSCLK_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/sysclk.h"\r
+#elif SAM3U\r
+# include "sam3u/sysclk.h"\r
+#elif SAM3N\r
+# include "sam3n/sysclk.h"\r
+#elif SAM3XA\r
+# include "sam3x/sysclk.h"\r
+#elif SAM4S\r
+# include "sam4s/sysclk.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/sysclk.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/sysclk.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/sysclk.h"\r
+#elif UC3C\r
+# include "uc3c/sysclk.h"\r
+#elif UC3D\r
+# include "uc3d/sysclk.h"\r
+#elif UC3L\r
+# include "uc3l/sysclk.h"\r
+#elif XMEGA\r
+# include "xmega/sysclk.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \defgroup clk_group Clock Management\r
+ */\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup sysclk_group System Clock Management\r
+ *\r
+ * See \ref sysclk_quickstart.\r
+ *\r
+ * The <em>sysclk</em> API covers the <em>system clock</em> and all\r
+ * clocks derived from it. The system clock is a chip-internal clock on\r
+ * which all <em>synchronous clocks</em>, i.e. CPU and bus/peripheral\r
+ * clocks, are based. The system clock is typically generated from one\r
+ * of a variety of sources, which may include crystal and RC oscillators\r
+ * as well as PLLs. The clocks derived from the system clock are\r
+ * sometimes also known as <em>synchronous clocks</em>, since they\r
+ * always run synchronously with respect to each other, as opposed to\r
+ * <em>generic clocks</em> which may run from different oscillators or\r
+ * PLLs.\r
+ *\r
+ * Most applications should simply call sysclk_init() to initialize\r
+ * everything related to the system clock and its source (oscillator,\r
+ * PLL or DFLL), and leave it at that. More advanced applications, and\r
+ * platform-specific drivers, may require additional services from the\r
+ * clock system, some of which may be platform-specific.\r
+ *\r
+ * \section sysclk_group_platform Platform Dependencies\r
+ *\r
+ * The sysclk API is partially chip- or platform-specific. While all\r
+ * platforms provide mostly the same functionality, there are some\r
+ * variations around how different bus types and clock tree structures\r
+ * are handled.\r
+ *\r
+ * The following functions are available on all platforms with the same\r
+ * parameters and functionality. These functions may be called freely by\r
+ * portable applications, drivers and services:\r
+ * - sysclk_init()\r
+ * - sysclk_set_source()\r
+ * - sysclk_get_main_hz()\r
+ * - sysclk_get_cpu_hz()\r
+ * - sysclk_get_peripheral_bus_hz()\r
+ *\r
+ * The following functions are available on all platforms, but there may\r
+ * be variations in the function signature (i.e. parameters) and\r
+ * behavior. These functions are typically called by platform-specific\r
+ * parts of drivers, and applications that aren't intended to be\r
+ * portable:\r
+ * - sysclk_enable_peripheral_clock()\r
+ * - sysclk_disable_peripheral_clock()\r
+ * - sysclk_enable_module()\r
+ * - sysclk_disable_module()\r
+ * - sysclk_module_is_enabled()\r
+ * - sysclk_set_prescalers()\r
+ *\r
+ * All other functions should be considered platform-specific.\r
+ * Enabling/disabling clocks to specific peripherals as well as\r
+ * determining the speed of these clocks should be done by calling\r
+ * functions provided by the driver for that peripheral.\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name System Clock Initialization\r
+//@{\r
+/**\r
+ * \fn void sysclk_init(void)\r
+ * \brief Initialize the synchronous clock system.\r
+ *\r
+ * This function will initialize the system clock and its source. This\r
+ * includes:\r
+ * - Mask all synchronous clocks except for any clocks which are\r
+ * essential for normal operation (for example internal memory\r
+ * clocks).\r
+ * - Set up the system clock prescalers as specified by the\r
+ * application's configuration file.\r
+ * - Enable the clock source specified by the application's\r
+ * configuration file (oscillator or PLL) and wait for it to become\r
+ * stable.\r
+ * - Set the main system clock source to the clock specified by the\r
+ * application's configuration file.\r
+ *\r
+ * Since all non-essential peripheral clocks are initially disabled, it\r
+ * is the responsibility of the peripheral driver to re-enable any\r
+ * clocks that are needed for normal operation.\r
+ */\r
+//@}\r
+\r
+//! @}\r
+\r
+#endif /* SYSCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Common GPIO API.\r
+ *\r
+ * Copyright (c) 2010 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef _GPIO_H_\r
+#define _GPIO_H_\r
+\r
+#include <parts.h>\r
+\r
+#if ( SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S )\r
+# include "sam_ioport/sam_gpio.h"\r
+#elif XMEGA\r
+# include "xmega_ioport/xmega_gpio.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+\r
+/**\r
+ * \defgroup gpio_group General Purpose Input/Output\r
+ *\r
+ * This is the common API for GPIO. Additional features are available\r
+ * in the documentation of the specific modules.\r
+ *\r
+ * \section io_group_platform Platform Dependencies\r
+ *\r
+ * The following functions are available on all platforms, but there may\r
+ * be variations in the function signature (i.e. parameters) and\r
+ * behaviour. These functions are typically called by platform-specific\r
+ * parts of drivers, and applications that aren't intended to be\r
+ * portable:\r
+ * - gpio_pin_is_low()\r
+ * - gpio_pin_is_high()\r
+ * - gpio_set_pin_high()\r
+ * - gpio_set_pin_group_high()\r
+ * - gpio_set_pin_low()\r
+ * - gpio_set_pin_group_low()\r
+ * - gpio_toggle_pin()\r
+ * - gpio_toggle_pin_group()\r
+ * - gpio_configure_pin()\r
+ * - gpio_configure_group()\r
+ */\r
+\r
+#endif // _GPIO_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief GPIO service for SAM.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SAM_GPIO_H_INCLUDED\r
+#define SAM_GPIO_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+#include "pio.h"\r
+\r
+#define gpio_pin_is_low(io_id) \\r
+ (pio_get_pin_value(io_id) ? 0 : 1)\r
+\r
+#define gpio_pin_is_high(io_id) \\r
+ (pio_get_pin_value(io_id) ? 1 : 0)\r
+\r
+#define gpio_set_pin_high(io_id) \\r
+ pio_set_pin_high(io_id)\r
+\r
+#define gpio_set_pin_low(io_id) \\r
+ pio_set_pin_low(io_id)\r
+\r
+#define gpio_toggle_pin(io_id) \\r
+ pio_toggle_pin(io_id)\r
+\r
+#define gpio_configure_pin(io_id,io_flags) \\r
+ pio_configure_pin(io_id,io_flags)\r
+\r
+#define gpio_configure_group(port_id,port_mask,io_flags) \\r
+ pio_configure_pin_group(port_id,port_mask,io_flags)\r
+\r
+#define gpio_set_pin_group_high(port_id,mask) \\r
+ pio_set_pin_group_high(port_id,mask)\r
+\r
+#define gpio_set_pin_group_low(port_id,mask) \\r
+ pio_set_pin_group_low(port_id,mask)\r
+\r
+#define gpio_toggle_pin_group(port_id,mask) \\r
+ pio_toggle_pin_group(port_id,mask)\r
+\r
+#endif /* SAM_GPIO_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for 8- and 32-bit AVR\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef UTILS_INTERRUPT_H\r
+#define UTILS_INTERRUPT_H\r
+\r
+#include <parts.h>\r
+\r
+#if XMEGA || MEGA\r
+# include "interrupt/interrupt_avr8.h"\r
+#elif UC3\r
+# include "interrupt/interrupt_avr32.h"\r
+#elif SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S\r
+# include "interrupt/interrupt_sam_nvic.h"\r
+#else\r
+# error Unsupported device.\r
+#endif\r
+\r
+/**\r
+ * \defgroup interrupt_group Global interrupt management\r
+ *\r
+ * This is a driver for global enabling and disabling of interrupts.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if defined(__DOXYGEN__)\r
+/**\r
+ * \def CONFIG_INTERRUPT_FORCE_INTC\r
+ * \brief Force usage of the ASF INTC driver\r
+ *\r
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.\r
+ * This is useful to ensure compatibilty accross compilers and shall be used only when required\r
+ * by the application needs.\r
+ */\r
+# define CONFIG_INTERRUPT_FORCE_INTC\r
+#endif\r
+\r
+//! \name Global interrupt flags\r
+//@{\r
+/**\r
+ * \typedef irqflags_t\r
+ * \brief Type used for holding state of interrupt flag\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_enable\r
+ * \brief Enable interrupts globally\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_disable\r
+ * \brief Disable interrupts globally\r
+ */\r
+\r
+/**\r
+ * \fn irqflags_t cpu_irq_save(void)\r
+ * \brief Get and clear the global interrupt flags\r
+ *\r
+ * Use in conjunction with \ref cpu_irq_restore.\r
+ *\r
+ * \return Current state of interrupt flags.\r
+ *\r
+ * \note This function leaves interrupts disabled.\r
+ */\r
+\r
+/**\r
+ * \fn void cpu_irq_restore(irqflags_t flags)\r
+ * \brief Restore global interrupt flags\r
+ *\r
+ * Use in conjunction with \ref cpu_irq_save.\r
+ *\r
+ * \param flags State to set interrupt flag to.\r
+ */\r
+\r
+/**\r
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+ * \brief Check if interrupts are globally enabled in supplied flags\r
+ *\r
+ * \param flags Currents state of interrupt flags.\r
+ *\r
+ * \return True if interrupts are enabled.\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_is_enabled\r
+ * \brief Check if interrupts are globally enabled\r
+ *\r
+ * \return True if interrupts are enabled.\r
+ */\r
+//@}\r
+\r
+//! @}\r
+\r
+/**\r
+ * \ingroup interrupt_group\r
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions\r
+ */\r
+\r
+#endif /* UTILS_INTERRUPT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "interrupt_sam_nvic.h"\r
+\r
+//! Global NVIC interrupt enable status (by default it's enabled)\r
+bool g_interrupt_enabled = true;\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef UTILS_INTERRUPT_INTERRUPT_H\r
+#define UTILS_INTERRUPT_INTERRUPT_H\r
+\r
+#include <compiler.h>\r
+#include <parts.h>\r
+\r
+/**\r
+ * \weakgroup interrupt_group\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Interrupt Service Routine definition\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Define service routine\r
+ *\r
+ * \note For NVIC devices the interrupt service routines are predefined to\r
+ * add to vector table in binary generation, so there is no service\r
+ * register at run time. The routine collections are in exceptions.h.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ * ISR(foo_irq_handler)\r
+ * {\r
+ * // Function definition\r
+ * ...\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \param func Name for the function.\r
+ */\r
+# define ISR(func) \\r
+ void func (void)\r
+\r
+/**\r
+ * \brief Initialize interrupt vectors\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to initialize them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * This must be called prior to \ref irq_register_handler.\r
+ */\r
+# define irq_initialize_vectors() \\r
+ do { \\r
+ } while(0)\r
+\r
+/**\r
+ * \brief Register handler for interrupt\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to register them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ * irq_initialize_vectors();\r
+ * irq_register_handler(foo_irq_handler);\r
+ * \endcode\r
+ *\r
+ * \note The function \a func must be defined with the \ref ISR macro.\r
+ * \note The functions prototypes can be found in the device exception header\r
+ * files (exceptions.h).\r
+ */\r
+# define irq_register_handler(...) \\r
+ do { \\r
+ } while(0)\r
+\r
+//@}\r
+\r
+# define cpu_irq_enable() \\r
+ do { \\r
+ g_interrupt_enabled = true; \\r
+ __DMB(); \\r
+ __enable_irq(); \\r
+ } while (0)\r
+# define cpu_irq_disable() \\r
+ do { \\r
+ __disable_irq(); \\r
+ __DMB(); \\r
+ g_interrupt_enabled = false; \\r
+ } while (0)\r
+\r
+typedef uint32_t irqflags_t;\r
+extern bool g_interrupt_enabled;\r
+\r
+static inline irqflags_t cpu_irq_save(void)\r
+{\r
+ irqflags_t flags = g_interrupt_enabled;\r
+ cpu_irq_disable();\r
+ return flags;\r
+}\r
+\r
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+{\r
+ return (flags);\r
+}\r
+\r
+static inline void cpu_irq_restore(irqflags_t flags)\r
+{\r
+ if (cpu_irq_is_enabled_flags(flags))\r
+ cpu_irq_enable();\r
+}\r
+\r
+#define cpu_irq_is_enabled() g_interrupt_enabled\r
+\r
+/**\r
+ * \weakgroup interrupt_deprecated_group\r
+ * @{\r
+ */\r
+\r
+#define Enable_global_interrupt() cpu_irq_enable()\r
+#define Disable_global_interrupt() cpu_irq_disable()\r
+#define Is_global_interrupt_enabled() cpu_irq_is_enabled()\r
+\r
+//@}\r
+\r
+//@}\r
+\r
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Atmel part identification macros\r
+ *\r
+ * Copyright (C) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef ATMEL_PARTS_H\r
+#define ATMEL_PARTS_H\r
+\r
+/**\r
+ * \defgroup part_macros_group Atmel part identification macros\r
+ *\r
+ * This collection of macros identify which series and families that the various\r
+ * Atmel parts belong to. These can be used to select part-dependent sections of\r
+ * code at compile time.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Convenience macros for part checking\r
+ * @{\r
+ */\r
+//! Check GCC and IAR part definition for 8-bit AVR\r
+#define AVR8_PART_IS_DEFINED(part) \\r
+ (defined(__ ## part ## __) || defined(__AVR_ ## part ## __))\r
+\r
+//! Check GCC and IAR part definition for 32-bit AVR\r
+#define AVR32_PART_IS_DEFINED(part) \\r
+ (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))\r
+\r
+//! Check GCC and IAR part definition for SAM\r
+#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup uc3_part_macros_group AVR UC3 parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name AVR UC3 A series\r
+ * @{\r
+ */\r
+#define UC3A0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A0128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A0256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A0512) \\r
+ )\r
+\r
+#define UC3A1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A1128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A1256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A1512) \\r
+ )\r
+\r
+#define UC3A3 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A364) || \\r
+ AVR32_PART_IS_DEFINED(UC3A364S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3128S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3256S) \\r
+ )\r
+\r
+#define UC3A4 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A464) || \\r
+ AVR32_PART_IS_DEFINED(UC3A464S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4128S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4256S) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 B series\r
+ * @{\r
+ */\r
+#define UC3B0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3B064) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0128) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0256) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0512) \\r
+ )\r
+\r
+#define UC3B1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3B164) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1128) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1256) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1512) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 C series\r
+ * @{\r
+ */\r
+#define UC3C0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C064C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0512C) \\r
+ )\r
+\r
+#define UC3C1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C164C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1512C) \\r
+ )\r
+\r
+#define UC3C2 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C264C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2512C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 D series\r
+ * @{\r
+ */\r
+#define UC3D3 ( \\r
+ AVR32_PART_IS_DEFINED(UC64D3) || \\r
+ AVR32_PART_IS_DEFINED(UC128D3) \\r
+ )\r
+\r
+#define UC3D4 ( \\r
+ AVR32_PART_IS_DEFINED(UC64D4) || \\r
+ AVR32_PART_IS_DEFINED(UC128D4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 L series\r
+ * @{\r
+ */\r
+#define UC3L0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L016) || \\r
+ AVR32_PART_IS_DEFINED(UC3L032) || \\r
+ AVR32_PART_IS_DEFINED(UC3L064) \\r
+ )\r
+\r
+#define UC3L0128 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L0128) \\r
+ )\r
+\r
+#define UC3L0256 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L0256) \\r
+ )\r
+\r
+#define UC3L3 ( \\r
+ AVR32_PART_IS_DEFINED(UC64L3U) || \\r
+ AVR32_PART_IS_DEFINED(UC128L3U) || \\r
+ AVR32_PART_IS_DEFINED(UC256L3U) \\r
+ )\r
+\r
+#define UC3L4 ( \\r
+ AVR32_PART_IS_DEFINED(UC64L4U) || \\r
+ AVR32_PART_IS_DEFINED(UC128L4U) || \\r
+ AVR32_PART_IS_DEFINED(UC256L4U) \\r
+ )\r
+\r
+#define UC3L3_L4 (UC3L3 || UC3L4)\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 families\r
+ * @{\r
+ */\r
+/** AVR UC3 A family */\r
+#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)\r
+\r
+/** AVR UC3 B family */\r
+#define UC3B (UC3B0 || UC3B1)\r
+\r
+/** AVR UC3 C family */\r
+#define UC3C (UC3C0 || UC3C1 || UC3C2)\r
+\r
+/** AVR UC3 D family */\r
+#define UC3D (UC3D3 || UC3D4)\r
+\r
+/** AVR UC3 L family */\r
+#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)\r
+/** @} */\r
+\r
+/** AVR UC3 product line */\r
+#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup xmega_part_macros_group AVR XMEGA parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name AVR XMEGA A series\r
+ * @{\r
+ */\r
+#define XMEGA_A1 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A1) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A1) \\r
+ )\r
+\r
+#define XMEGA_A3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3) \\r
+ )\r
+\r
+#define XMEGA_A3B ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3B) \\r
+ )\r
+\r
+#define XMEGA_A4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16A4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32A4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA AU series\r
+ * @{\r
+ */\r
+#define XMEGA_A1U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A1U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A1U) \\r
+ )\r
+\r
+#define XMEGA_A3U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3U) \\r
+ )\r
+\r
+#define XMEGA_A3BU ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3BU) \\r
+ )\r
+\r
+#define XMEGA_A4U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A4U) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA B series\r
+ * @{\r
+ */\r
+#define XMEGA_B1 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64B1) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128B1) \\r
+ )\r
+\r
+#define XMEGA_B3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64B3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128B3) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA C series\r
+ * @{\r
+ */\r
+#define XMEGA_C3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega384C3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256C3) \\r
+ )\r
+\r
+#define XMEGA_C4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega32C4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega16C4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA D series\r
+ * @{\r
+ */\r
+#define XMEGA_D3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega384D3) \\r
+ )\r
+\r
+#define XMEGA_D4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega64D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128D4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA families\r
+ * @{\r
+ */\r
+/** AVR XMEGA A family */\r
+#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)\r
+\r
+/** AVR XMEGA AU family */\r
+#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)\r
+\r
+/** AVR XMEGA B family */\r
+#define XMEGA_B (XMEGA_B1 || XMEGA_B3)\r
+\r
+/** AVR XMEGA C family */\r
+#define XMEGA_C (XMEGA_C3 || XMEGA_C4)\r
+\r
+/** AVR XMEGA D family */\r
+#define XMEGA_D (XMEGA_D3 || XMEGA_D4)\r
+/** @} */\r
+\r
+/** AVR XMEGA product line */\r
+#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup mega_part_macros_group megaAVR parts\r
+ *\r
+ * \note These megaAVR groupings are based on the groups in AVR Libc for the\r
+ * part header files. They are not names of official megaAVR device series or\r
+ * families.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name ATmegaxx0/xx1 subgroups\r
+ * @{\r
+ */\r
+#define MEGA_XX0 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega640) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1280) || \\r
+ AVR8_PART_IS_DEFINED(ATmega2560) \\r
+ )\r
+\r
+#define MEGA_XX1 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega1281) || \\r
+ AVR8_PART_IS_DEFINED(ATmega2561) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name megaAVR groups\r
+ * @{\r
+ */\r
+/** ATmegaxx0/xx1 group */\r
+#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)\r
+\r
+/** ATmegaxx4 group */\r
+#define MEGA_XX4 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega164A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1284P) \\r
+ )\r
+\r
+/** ATmegaxx4 group */\r
+#define MEGA_XX4_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega164A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1284P) \\r
+ )\r
+\r
+/** ATmegaxx8 group */\r
+#define MEGA_XX8 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega48) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328P) \\r
+ )\r
+\r
+/** ATmegaxx8A/P/PA group */\r
+#define MEGA_XX8_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega48A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328P) \\r
+ )\r
+\r
+/** ATmegaxx group */\r
+#define MEGA_XX ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) \\r
+ )\r
+\r
+/** ATmegaxxA/P/PA group */\r
+#define MEGA_XX_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) \\r
+ )\r
+\r
+/** Unspecified group */\r
+#define MEGA_UNSPECIFIED ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega169P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega169PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329PA) \\r
+ )\r
+/** @} */\r
+\r
+/** megaAVR product line */\r
+#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_UNSPECIFIED)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup sam_part_macros_group SAM parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name SAM3S series\r
+ * @{\r
+ */\r
+#define SAM3S1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S1A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S1B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S1C) \\r
+ )\r
+\r
+#define SAM3S2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S2A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S2B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S2C) \\r
+ )\r
+\r
+#define SAM3S4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S4A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S4B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S4C) \\r
+ )\r
+\r
+#define SAM3S8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S8B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S8C) \\r
+ )\r
+\r
+#define SAM3SD8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3SD8B) || \\r
+ SAM_PART_IS_DEFINED(SAM3SD8C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3U series\r
+ * @{\r
+ */\r
+#define SAM3U1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U1C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U1E) \\r
+ )\r
+\r
+#define SAM3U2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U2C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U2E) \\r
+ )\r
+\r
+#define SAM3U4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U4C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U4E) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3N series\r
+ * @{\r
+ */\r
+#define SAM3N1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N1A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N1B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N1C) \\r
+ )\r
+\r
+#define SAM3N2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N2A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N2B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N2C) \\r
+ )\r
+\r
+#define SAM3N4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N4A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N4B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N4C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3X series\r
+ * @{\r
+ */\r
+#define SAM3X4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3X4C) || \\r
+ SAM_PART_IS_DEFINED(SAM3X4E) \\r
+ )\r
+\r
+#define SAM3X8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3X8C) || \\r
+ SAM_PART_IS_DEFINED(SAM3X8E) || \\r
+ SAM_PART_IS_DEFINED(SAM3X8H) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3A series\r
+ * @{\r
+ */\r
+#define SAM3A4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3A4C) \\r
+ )\r
+\r
+#define SAM3A8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3A8C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM4S series\r
+ * @{\r
+ */\r
+#define SAM4S8 ( \\r
+ SAM_PART_IS_DEFINED(SAM4S8B) || \\r
+ SAM_PART_IS_DEFINED(SAM4S8C) \\r
+ )\r
+\r
+#define SAM4S16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4S16B) || \\r
+ SAM_PART_IS_DEFINED(SAM4S16C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM families\r
+ * @{\r
+ */\r
+/** SAM3S Family */\r
+#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)\r
+\r
+/** SAM3U Family */\r
+#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)\r
+\r
+/** SAM3N Family */\r
+#define SAM3N (SAM3N1 || SAM3N2 || SAM3N4)\r
+\r
+/** SAM3XA Family */\r
+#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)\r
+\r
+/** SAM4S Family */\r
+#define SAM4S (SAM4S8 || SAM4S16)\r
+/** @} */\r
+\r
+/** SAM product line */\r
+#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S)\r
+\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+#endif /* ATMEL_PARTS_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM3S-EK2 board init.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "compiler.h"\r
+#include "board.h"\r
+#include "conf_board.h"\r
+#include "gpio.h"\r
+\r
+void board_init(void)\r
+{\r
+#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT \r
+ /* Disable the watchdog */\r
+ WDT->WDT_MR = WDT_MR_WDDIS;\r
+#endif\r
+\r
+ /* Configure LED pins */\r
+ gpio_configure_pin(LED0_GPIO, LED0_FLAGS);\r
+ gpio_configure_pin(LED1_GPIO, LED1_FLAGS);\r
+ \r
+ /* Configure Push Button pins */\r
+ gpio_configure_pin(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS);\r
+ gpio_configure_pin(GPIO_PUSH_BUTTON_2, GPIO_PUSH_BUTTON_2_FLAGS);\r
+ \r
+#ifdef CONF_BOARD_UART_CONSOLE\r
+ /* Configure UART pins */\r
+ gpio_configure_group(PINS_UART_PIO, PINS_UART, PINS_UART_FLAGS);\r
+#endif\r
+\r
+ /* Configure ADC example pins */\r
+#ifdef CONF_BOARD_ADC\r
+ /* TC TIOA configuration */\r
+ gpio_configure_pin(PIN_TC0_TIOA0,PIN_TC0_TIOA0_FLAGS);\r
+ \r
+ /* ADC Trigger configuration */\r
+ gpio_configure_pin(PINS_ADC_TRIG, PINS_ADC_TRIG_FLAG);\r
+\r
+ /* PWMH0 configuration */\r
+ gpio_configure_pin(PIN_PWMC_PWMH0_TRIG, PIN_PWMC_PWMH0_TRIG_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED0\r
+ /* Configure PWM LED0 pin */\r
+ gpio_configure_pin(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED1\r
+ /* Configure PWM LED1 pin */\r
+ gpio_configure_pin(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED2\r
+ /* Configure PWM LED2 pin */\r
+ gpio_configure_pin(PIN_PWM_LED2_GPIO, PIN_PWM_LED2_FLAGS);\r
+#endif\r
+\r
+ /* Configure SPI pins */\r
+#ifdef CONF_BOARD_SPI\r
+ gpio_configure_pin(SPI_MISO_GPIO, SPI_MISO_FLAGS);\r
+ gpio_configure_pin(SPI_MOSI_GPIO, SPI_MOSI_FLAGS);\r
+ gpio_configure_pin(SPI_SPCK_GPIO, SPI_SPCK_FLAGS);\r
+ \r
+ /**\r
+ * For NPCS 1, 2, and 3, different PINs can be used to access the same NPCS line.\r
+ * Depending on the application requirements, the default PIN may not be available. \r
+ * Hence a different PIN should be selected using the CONF_BOARD_SPI_NPCS_GPIO and \r
+ * CONF_BOARD_SPI_NPCS_FLAGS macros.\r
+ */\r
+ \r
+ #ifdef CONF_BOARD_SPI_NPCS0\r
+ gpio_configure_pin(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS);\r
+ #endif\r
+\r
+ #ifdef CONF_BOARD_SPI_NPCS1\r
+ #if defined(CONF_BOARD_SPI_NPCS1_GPIO) && defined(CONF_BOARD_SPI_NPCS1_FLAGS)\r
+ gpio_configure_pin(CONF_BOARD_SPI_NPCS1_GPIO, CONF_BOARD_SPI_NPCS1_FLAGS);\r
+ #else\r
+ gpio_configure_pin(SPI_NPCS1_PA31_GPIO, SPI_NPCS1_PA31_FLAGS);\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef CONF_BOARD_SPI_NPCS2\r
+ #if defined(CONF_BOARD_SPI_NPCS2_GPIO) && defined(CONF_BOARD_SPI_NPCS2_FLAGS)\r
+ gpio_configure_pin(CONF_BOARD_SPI_NPCS2_GPIO, CONF_BOARD_SPI_NPCS2_FLAGS);\r
+ #else\r
+ gpio_configure_pin(SPI_NPCS2_PA30_GPIO, SPI_NPCS2_PA30_FLAGS);\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef CONF_BOARD_SPI_NPCS3\r
+ #if defined(CONF_BOARD_SPI_NPCS3_GPIO) && defined(CONF_BOARD_SPI_NPCS3_FLAGS)\r
+ gpio_configure_pin(CONF_BOARD_SPI_NPCS3_GPIO, CONF_BOARD_SPI_NPCS3_FLAGS);\r
+ #else\r
+ gpio_configure_pin(SPI_NPCS3_PA22_GPIO, SPI_NPCS3_PA22_FLAGS);\r
+ #endif\r
+ #endif\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_RXD\r
+ /* Configure USART RXD pin */\r
+ gpio_configure_pin(PIN_USART1_RXD_IDX, PIN_USART1_RXD_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_TXD\r
+ /* Configure USART TXD pin */\r
+ gpio_configure_pin(PIN_USART1_TXD_IDX, PIN_USART1_TXD_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_CTS\r
+ /* Configure USART CTS pin */\r
+ gpio_configure_pin(PIN_USART1_CTS_IDX, PIN_USART1_CTS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_RTS\r
+ /* Configure USART RTS pin */\r
+ gpio_configure_pin(PIN_USART1_RTS_IDX, PIN_USART1_RTS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_SCK\r
+ /* Configure USART synchronous communication SCK pin */\r
+ gpio_configure_pin(PIN_USART1_SCK_IDX, PIN_USART1_SCK_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADM3312_EN\r
+ /* Configure ADM33312 enable pin */\r
+ gpio_configure_pin(PIN_USART1_EN_IDX, PIN_USART1_EN_FLAGS);\r
+ gpio_set_pin_low(PIN_USART1_EN_IDX);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_TFDU4300_SD\r
+ /* Configure IrDA transceiver shutdown pin */\r
+ gpio_configure_pin(PIN_IRDA_SD_IDX, PIN_IRDA_SD_FLAGS);\r
+ gpio_set_pin_low(PIN_IRDA_SD_IDX);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADM3485_RE\r
+ /* Configure RS485 transceiver RE pin */\r
+ gpio_configure_pin(PIN_RE_IDX, PIN_RE_FLAGS);\r
+ gpio_set_pin_low(PIN_RE_IDX);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ILI9325\r
+ /* Configure LCD EBI pins */\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D0, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D1, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D2, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D3, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D4, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D5, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D6, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D7, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NRD, PIN_EBI_NRD_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NWE, PIN_EBI_NWE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NCS1, PIN_EBI_NCS1_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_LCD_RS, PIN_EBI_LCD_RS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_AAT3155\r
+ /* Configure Backlight control pin */\r
+ gpio_configure_pin(BOARD_BACKLIGHT, BOARD_BACKLIGHT_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADS7843\r
+ /* Configure Touchscreen SPI pins */\r
+ gpio_configure_pin(PIN_TSC_IRQ_IDX,PIN_TSC_IRQ_FLAG);\r
+ gpio_configure_pin(SPI_MISO_GPIO, SPI_MISO_FLAGS);\r
+ gpio_configure_pin(SPI_MOSI_GPIO, SPI_MOSI_FLAGS);\r
+ gpio_configure_pin(SPI_SPCK_GPIO, SPI_SPCK_FLAGS);\r
+ gpio_configure_pin(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS);\r
+ gpio_configure_pin(PIN_TSC_BUSY_IDX, PIN_TSC_BUSY_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_MMA7341L\r
+ /* Configure MMA7341L mode set control pin */\r
+ gpio_configure_pin(PIN_MMA7341L_MODE, PIN_MMA7341L_MODE_FLAG);\r
+ /* Configure MMA7341L x,y,z axis output voltage pin */\r
+ gpio_configure_pin(PIN_MMA7341L_X_AXIS, PIN_MMA7341L_X_AXIS_FLAG);\r
+ gpio_configure_pin(PIN_MMA7341L_Y_AXIS, PIN_MMA7341L_Y_AXIS_FLAG);\r
+ gpio_configure_pin(PIN_MMA7341L_Z_AXIS, PIN_MMA7341L_Z_AXIS_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ISO7816_RST\r
+ /* Configure ISO7816 card reset pin */\r
+ gpio_configure_pin(PIN_ISO7816_RST_IDX, PIN_ISO7816_RST_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ISO7816\r
+ /* Configure ISO7816 interface TXD & SCK pin */\r
+ gpio_configure_pin(PIN_USART1_TXD_IDX, PIN_USART1_TXD_FLAGS);\r
+ gpio_configure_pin(PIN_USART1_SCK_IDX, PIN_USART1_SCK_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_NAND\r
+ gpio_configure_pin(PIN_EBI_NANDOE, PIN_EBI_NANDOE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDWE, PIN_EBI_NANDWE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDCLE, PIN_EBI_NANDCLE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDALE, PIN_EBI_NANDALE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_0, PIN_EBI_NANDIO_0_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_1, PIN_EBI_NANDIO_1_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_2, PIN_EBI_NANDIO_2_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_3, PIN_EBI_NANDIO_3_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_4, PIN_EBI_NANDIO_4_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_5, PIN_EBI_NANDIO_5_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_6, PIN_EBI_NANDIO_6_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_7, PIN_EBI_NANDIO_7_FLAGS);\r
+ gpio_configure_pin(PIN_NF_CE_IDX, PIN_NF_CE_FLAGS);\r
+ gpio_configure_pin(PIN_NF_RB_IDX, PIN_NF_RB_FLAGS);\r
+#endif\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM3S-EK2 LEDs support package.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _LED_H_\r
+#define _LED_H_\r
+\r
+#include "gpio.h"\r
+\r
+/*! \brief Turns off the specified LEDs.\r
+ *\r
+ * \param led_gpio LED to turn off (LEDx_GPIO).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+#define LED_Off(led_gpio) gpio_set_pin_high(led_gpio)\r
+\r
+/*! \brief Turns on the specified LEDs.\r
+ *\r
+ * \param led_gpio LED to turn on (LEDx_GPIO).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+#define LED_On(led_gpio) gpio_set_pin_low(led_gpio)\r
+\r
+/*! \brief Toggles the specified LEDs.\r
+ *\r
+ * \param led_gpio LED to toggle (LEDx_GPIO).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+#define LED_Toggle(led_gpio) gpio_toggle_pin(led_gpio)\r
+\r
+#endif // _LED_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM3S-EK2 Board Definition.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S_EK2_H_\r
+#define _SAM3S_EK2_H_\r
+\r
+#include "compiler.h"\r
+#include "system_sam3sd8.h"\r
+#include "exceptions.h"\r
+\r
+/*\r
+#define BOARD_REV_A\r
+*/\r
+#define BOARD_REV_B\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam3s_ek_opfreq "SAM3S-EK2 - Operating frequencies"\r
+ * This page lists several definition related to the board operating frequency\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_FREQ_*\r
+ * - \ref BOARD_MCK\r
+ */\r
+\r
+/** Board oscillator settings */\r
+#define BOARD_FREQ_SLCK_XTAL (32768U)\r
+#define BOARD_FREQ_SLCK_BYPASS (32768U)\r
+#define BOARD_FREQ_MAINCK_XTAL (12000000U)\r
+#define BOARD_FREQ_MAINCK_BYPASS (12000000U)\r
+\r
+/** Master clock frequency */\r
+#define BOARD_MCK CHIP_FREQ_CPU_MAX\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam3s_ek_board_info "SAM3S-EK2 - Board informations"\r
+ * This page lists several definition related to the board description.\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_NAME\r
+ */\r
+\r
+/** Name of the board */\r
+#define BOARD_NAME "SAM3S-EK2"\r
+/** Board definition */\r
+#define sam3sek2\r
+/** Family definition (already defined) */\r
+#define sam3sd8\r
+/** Core definition */\r
+#define cortexm3\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam3s_ek_piodef "SAM3S-EK - PIO definitions"\r
+ * This pages lists all the pio definitions. The constants\r
+ * are named using the following convention: PIN_* for a constant which defines\r
+ * a single Pin instance (but may include several PIOs sharing the same\r
+ * controller), and PINS_* for a list of Pin instances.\r
+ *\r
+ * ADC\r
+ * - \ref PIN_ADC0_AD0\r
+ * - \ref PIN_ADC0_AD1\r
+ * - \ref PIN_ADC0_AD2\r
+ * - \ref PIN_ADC0_AD3\r
+ * - \ref PIN_ADC0_AD4\r
+ * - \ref PIN_ADC0_AD5\r
+ * - \ref PIN_ADC0_AD6\r
+ * - \ref PIN_ADC0_AD7\r
+ * - \ref PINS_ADC\r
+ *\r
+ * UART\r
+ * - \ref PINS_UART\r
+ *\r
+ * EBI\r
+ * - \ref PIN_EBI_DATA_BUS\r
+ * - \ref PIN_EBI_NRD\r
+ * - \ref PIN_EBI_NWE\r
+ * - \ref PIN_EBI_NCS0\r
+ * - \ref PIN_EBI_PSRAM_ADDR_BUS\r
+ * - \ref PIN_EBI_PSRAM_NBS\r
+ * - \ref PIN_EBI_A1\r
+ * - \ref PIN_EBI_NCS1\r
+ * - \ref PIN_EBI_LCD_RS\r
+ *\r
+ * LEDs\r
+ * - \ref PIN_LED_0\r
+ * - \ref PIN_LED_1\r
+ * - \ref PIN_LED_2\r
+ * - \ref PINS_LEDS\r
+ *\r
+ * HSMCI\r
+ * - \ref PINS_HSMCI\r
+ *\r
+ * Push buttons\r
+ * - \ref PIN_PUSHBUTTON_1\r
+ * - \ref PIN_PUSHBUTTON_2\r
+ * - \ref PINS_PUSHBUTTONS\r
+ * - \ref PUSHBUTTON_BP1\r
+ * - \ref PUSHBUTTON_BP2\r
+ *\r
+ * PWMC\r
+ * - \ref PIN_PWMC_PWMH0\r
+ * - \ref PIN_PWMC_PWML0\r
+ * - \ref PIN_PWMC_PWMH1\r
+ * - \ref PIN_PWMC_PWML1\r
+ * - \ref PIN_PWMC_PWMH2\r
+ * - \ref PIN_PWMC_PWML2\r
+ * - \ref PIN_PWMC_PWMH3\r
+ * - \ref PIN_PWMC_PWML3\r
+ * - \ref PIN_PWM_LED0\r
+ * - \ref PIN_PWM_LED1\r
+ * - \ref PIN_PWM_LED2\r
+ * - \ref CHANNEL_PWM_LED0\r
+ * - \ref CHANNEL_PWM_LED1\r
+ * - \ref CHANNEL_PWM_LED2\r
+ *\r
+ * SPI\r
+ * - \ref PIN_SPI_MISO\r
+ * - \ref PIN_SPI_MOSI\r
+ * - \ref PIN_SPI_SPCK\r
+ * - \ref PINS_SPI\r
+ * - \ref PIN_SPI_NPCS0_PA11\r
+ *\r
+ * SSC\r
+ * - \ref PIN_SSC_TD\r
+ * - \ref PIN_SSC_TK\r
+ * - \ref PIN_SSC_TF\r
+ * - \ref PINS_SSC_CODEC\r
+ *\r
+ * PCK0\r
+ * - \ref PIN_PCK0\r
+ *\r
+ * PIO PARALLEL CAPTURE\r
+ * - \ref PIN_PIODCEN1\r
+ * - \ref PIN_PIODCEN2\r
+ *\r
+ * TWI\r
+ * - \ref TWI_V3XX\r
+ * - \ref PIN_TWI_TWD0\r
+ * - \ref PIN_TWI_TWCK0\r
+ * - \ref PINS_TWI0\r
+ * - \ref PIN_TWI_TWD1\r
+ * - \ref PIN_TWI_TWCK1\r
+ * - \ref PINS_TWI1\r
+ *\r
+ * USART0\r
+ * - \ref PIN_USART0_RXD\r
+ * - \ref PIN_USART0_TXD\r
+ * - \ref PIN_USART0_CTS\r
+ * - \ref PIN_USART0_RTS\r
+ * - \ref PIN_USART0_SCK\r
+ *\r
+ * USB\r
+ * - \ref PIN_USB_VBUS\r
+ *\r
+ * NandFlash\r
+ * - \ref PIN_EBI_NANDOE\r
+ * - \ref PIN_EBI_NANDWE\r
+ * - \ref PIN_EBI_NANDCLE\r
+ * - \ref PIN_EBI_NANDALE\r
+ * - \ref PIN_EBI_NANDIO\r
+ * - \ref BOARD_NF_CE_PIN\r
+ * - \ref BOARD_NF_RB_PIN\r
+ * - \ref PINS_NANDFLASH\r
+ *\r
+ * QTouch\r
+ * PIO definitions for Slider\r
+ * \ref SLIDER_IOMASK_SNS\r
+ * \ref SLIDER_IOMASK_SNSK\r
+ * \ref PINS_SLIDER_SNS\r
+ * \ref PINS_SLIDER_SNSK\r
+ *\r
+ * PIO definitions for keys\r
+ * \ref KEY_IOMASK_SNS\r
+ * \ref KEY_IOMASK_SNSK\r
+ * \ref PINS_KEY_SNS\r
+ * \ref PINS_KEY_SNSK\r
+ *\r
+ * PIOS for QTouch\r
+ * \ref PINS_QTOUCH\r
+ */\r
+\r
+/** ADC_AD0 pin definition. */\r
+#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD1 pin definition. */\r
+#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD2 pin definition. */\r
+#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD3 pin definition. */\r
+#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD4 pin definition. */\r
+#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD5 pin definition. */\r
+#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD6 pin definition. */\r
+#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD7 pin definition. */\r
+#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/** Pins ADC */\r
+#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7\r
+#define PINS_ADC_TRIG PIO_PA8_IDX\r
+#define PINS_ADC_TRIG_FLAG (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+/** Startup time max, return from Idle mode (in µs) */\r
+#define ADC_STARTUP_TIME_MAX 15\r
+/** Track and hold Acquisition Time min (in ns) */\r
+#define ADC_TRACK_HOLD_TIME_MIN 1200\r
+/** ADC clock frequency */\r
+#define BOARD_ADC_FREQ (6000000)\r
+\r
+/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */\r
+#define PINS_UART (PIO_PA9A_URXD0 | PIO_PA10A_UTXD0)\r
+#define PINS_UART_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+#define PINS_UART_MASK PIO_PA9A_URXD0|PIO_PA10A_UTXD0\r
+#define PINS_UART_PIO PIOA\r
+#define PINS_UART_ID ID_PIOA\r
+#define PINS_UART_TYPE PIO_PERIPH_A\r
+#define PINS_UART_ATTR PIO_DEFAULT\r
+\r
+/** EBI Data Bus pins */\r
+#define PIN_EBI_DATA_BUS_D0 PIO_PC0_IDX\r
+#define PIN_EBI_DATA_BUS_D1 PIO_PC1_IDX\r
+#define PIN_EBI_DATA_BUS_D2 PIO_PC2_IDX\r
+#define PIN_EBI_DATA_BUS_D3 PIO_PC3_IDX\r
+#define PIN_EBI_DATA_BUS_D4 PIO_PC4_IDX\r
+#define PIN_EBI_DATA_BUS_D5 PIO_PC5_IDX\r
+#define PIN_EBI_DATA_BUS_D6 PIO_PC6_IDX\r
+#define PIN_EBI_DATA_BUS_D7 PIO_PC7_IDX\r
+#define PIN_EBI_DATA_BUS_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_DATA_BUS_MASK 0xFF\r
+#define PIN_EBI_DATA_BUS_PIO PIOC\r
+#define PIN_EBI_DATA_BUS_ID ID_PIOC\r
+#define PIN_EBI_DATA_BUS_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_DATA_BUS_ATTR PIO_PULLUP\r
+/** EBI NRD pin */\r
+#define PIN_EBI_NRD PIO_PC11_IDX\r
+#define PIN_EBI_NRD_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_NRD_MASK 1 << 11\r
+#define PIN_EBI_NRD_PIO PIOC\r
+#define PIN_EBI_NRD_ID ID_PIOC\r
+#define PIN_EBI_NRD_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_NRD_ATTR PIO_PULLUP\r
+/** EBI NWE pin */\r
+#define PIN_EBI_NWE PIO_PC8_IDX\r
+#define PIN_EBI_NWE_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_NWE_MASK 1 << 8\r
+#define PIN_EBI_NWE_PIO PIOC\r
+#define PIN_EBI_NWE_ID ID_PIOC\r
+#define PIN_EBI_NWE_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_NWE_ATTR PIO_PULLUP\r
+/** EBI NCS0 pin */\r
+#define PIN_EBI_NCS0 PIO_PC14_IDX\r
+#define PIN_EBI_NCS0_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_NCS0_MASK 1 << 14\r
+#define PIN_EBI_NCS0_PIO PIOC\r
+#define PIN_EBI_NCS0_ID ID_PIOC\r
+#define PIN_EBI_NCS0_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_NCS0_ATTR PIO_PULLUP\r
+/** EBI address bus pins */\r
+#define PIN_EBI_ADDR_BUS_A0 PIO_PC18_IDX\r
+#define PIN_EBI_ADDR_BUS_A1 PIO_PC19_IDX\r
+#define PIN_EBI_ADDR_BUS_A2 PIO_PC20_IDX\r
+#define PIN_EBI_ADDR_BUS_A3 PIO_PC21_IDX\r
+#define PIN_EBI_ADDR_BUS_A4 PIO_PC22_IDX\r
+#define PIN_EBI_ADDR_BUS_A5 PIO_PC23_IDX\r
+#define PIN_EBI_ADDR_BUS_A6 PIO_PC24_IDX\r
+#define PIN_EBI_ADDR_BUS_A7 PIO_PC25_IDX\r
+#define PIN_EBI_ADDR_BUS_A8 PIO_PC26_IDX\r
+#define PIN_EBI_ADDR_BUS_A9 PIO_PC27_IDX\r
+#define PIN_EBI_ADDR_BUS_A10 PIO_PC28_IDX\r
+#define PIN_EBI_ADDR_BUS_A11 PIO_PC29_IDX\r
+#define PIN_EBI_ADDR_BUS_A12 PIO_PC30_IDX\r
+#define PIN_EBI_ADDR_BUS_A13 PIO_PC31_IDX\r
+#define PIN_EBI_ADDR_BUS_FLAG1 PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_ADDR_BUS_A14 PIO_PA18_IDX\r
+#define PIN_EBI_ADDR_BUS_A15 PIO_PA19_IDX\r
+#define PIN_EBI_ADDR_BUS_A16 PIO_PA20_IDX\r
+#define PIN_EBI_ADDR_BUS_A17 PIO_PA0_IDX\r
+#define PIN_EBI_ADDR_BUS_A18 PIO_PA1_IDX\r
+#define PIN_EBI_ADDR_BUS_A19 PIO_PA23_IDX\r
+#define PIN_EBI_ADDR_BUS_A20 PIO_PA24_IDX\r
+#define PIN_EBI_ADDR_BUS_FLAG2 PIO_PERIPH_C | PIO_PULLUP\r
+/** EBI pin for LCD CS */\r
+#define PIN_EBI_NCS1 PIO_PC15_IDX\r
+#define PIN_EBI_NCS1_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_NCS1_MASK 1 << 15\r
+#define PIN_EBI_NCS1_PIO PIOC\r
+#define PIN_EBI_NCS1_ID ID_PIOC\r
+#define PIN_EBI_NCS1_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_NCS1_ATTR PIO_PULLUP\r
+/** EBI pin for LCD RS */\r
+#define PIN_EBI_LCD_RS PIO_PC19_IDX\r
+#define PIN_EBI_LCD_RS_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_LCD_RS_MASK 1 << 19\r
+#define PIN_EBI_LCD_RS_PIO PIOC\r
+#define PIN_EBI_LCD_RS_ID ID_PIOC\r
+#define PIN_EBI_LCD_RS_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_LCD_RS_ATTR PIO_PULLUP\r
+\r
+#define LED_BLUE 0\r
+#define LED_GREEN 1\r
+#define LED_RED 2\r
+\r
+#ifdef BOARD_REV_A\r
+/** LED #0 pin definition (BLUE). */\r
+#define LED_0_NAME "blue LED D2"\r
+#define LED0_GPIO (PIO_PC20_IDX)\r
+#define LED0_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+#define PIN_LED_0 {PIO_PC20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#define PIN_LED_0_MASK PIO_PC20\r
+#define PIN_LED_0_PIO PIOC\r
+#define PIN_LED_0_ID ID_PIOC\r
+#define PIN_LED_0_TYPE PIO_OUTPUT_1\r
+#define PIN_LED_0_ATTR PIO_DEFAULT\r
+\r
+/** LED #1 pin definition (GREEN). */\r
+#define LED_1_NAME "green LED D3"\r
+#define LED1_GPIO (PIO_PC21_IDX)\r
+#define LED1_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+#define PIN_LED_1 {PIO_PC21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/** LED #2 pin definition (RED). */\r
+#define LED2_GPIO (PIO_PC22_IDX)\r
+#define LED2_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+#define PIN_LED_2 {PIO_PC22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#endif\r
+\r
+#ifdef BOARD_REV_B\r
+/** LED #0 pin definition (BLUE). */\r
+#define LED_0_NAME "blue LED D2"\r
+#define LED0_GPIO (PIO_PA19_IDX)\r
+#define LED0_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+#define PIN_LED_0 {PIO_PA19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#define PIN_LED_0_MASK PIO_PA19\r
+#define PIN_LED_0_PIO PIOA\r
+#define PIN_LED_0_ID ID_PIOA\r
+#define PIN_LED_0_TYPE PIO_OUTPUT_1\r
+#define PIN_LED_0_ATTR PIO_DEFAULT\r
+\r
+/** LED #1 pin definition (GREEN). */\r
+#define LED_1_NAME "green LED D3"\r
+#define LED1_GPIO (PIO_PA20_IDX)\r
+#define LED1_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+#define PIN_LED_1 {PIO_PA20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#define PIN_LED_1_MASK PIO_PA20\r
+#define PIN_LED_1_PIO PIOA\r
+#define PIN_LED_1_ID ID_PIOA\r
+#define PIN_LED_1_TYPE PIO_OUTPUT_1\r
+#define PIN_LED_1_ATTR PIO_DEFAULT\r
+\r
+/** LED #2 pin definition (RED). */\r
+#define LED2_GPIO (PIO_PC20_IDX)\r
+#define LED2_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+#define PIN_LED_2 {PIO_PC20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+\r
+#endif\r
+\r
+/** List of all LEDs definitions. */\r
+#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2\r
+\r
+/** HSMCI pins definition. */\r
+#define PINS_HSMCI {0x3fUL << 26, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP}\r
+/** HSMCI pin Card Detect. */\r
+#ifdef BOARD_REV_A\r
+#define PIN_HSMCI_CD {PIO_PA15, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#endif\r
+\r
+#ifdef BOARD_REV_B\r
+#define PIN_HSMCI_CD {PIO_PA6, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#endif\r
+\r
+/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */\r
+#define PUSHBUTTON_1_NAME "USRPB1"\r
+#define GPIO_PUSH_BUTTON_1 (PIO_PB3_IDX)\r
+#define GPIO_PUSH_BUTTON_1_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)\r
+\r
+#define PIN_PUSHBUTTON_1 {PIO_PB3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}\r
+#define PIN_PUSHBUTTON_1_MASK PIO_PB3\r
+#define PIN_PUSHBUTTON_1_PIO PIOB\r
+#define PIN_PUSHBUTTON_1_ID ID_PIOB\r
+#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT\r
+#define PIN_PUSHBUTTON_1_ATTR PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE\r
+\r
+/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */\r
+#define PUSHBUTTON_2_NAME "USRPB2"\r
+#define GPIO_PUSH_BUTTON_2 (PIO_PC12_IDX)\r
+#define GPIO_PUSH_BUTTON_2_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE)\r
+\r
+#define PIN_PUSHBUTTON_2 {PIO_PC12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}\r
+#define PIN_PUSHBUTTON_2_MASK PIO_PC12\r
+#define PIN_PUSHBUTTON_2_PIO PIOC\r
+#define PIN_PUSHBUTTON_2_ID ID_PIOC\r
+#define PIN_PUSHBUTTON_2_TYPE PIO_INPUT\r
+#define PIN_PUSHBUTTON_2_ATTR PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE\r
+\r
+/** List of all push button definitions. */\r
+#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2\r
+\r
+/** Push button #1 index. */\r
+#define PUSHBUTTON_BP1 0\r
+/** Push button #2 index. */\r
+#define PUSHBUTTON_BP2 1\r
+\r
+#define PIN_TC0_TIOA0 (PIO_PA0_IDX)\r
+#define PIN_TC0_TIOA0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+#define PIN_TC0_TIOA1 (PIO_PA15_IDX)\r
+#define PIN_TC0_TIOA1_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+#define PIN_TC0_TIOA1_PIO PIOA\r
+#define PIN_TC0_TIOA1_MASK PIO_PA15\r
+#define PIN_TC0_TIOA1_ID ID_PIOA\r
+#define PIN_TC0_TIOA1_TYPE PIO_PERIPH_B\r
+#define PIN_TC0_TIOA1_ATTR PIO_DEFAULT\r
+\r
+#define PIN_TC0_TIOA2 (PIO_PA26_IDX)\r
+#define PIN_TC0_TIOA2_FLAGS (PIO_INPUT | PIO_DEFAULT)\r
+\r
+#define PIN_TC0_TIOA2_PIO PIOA\r
+#define PIN_TC0_TIOA2_MASK PIO_PA26\r
+#define PIN_TC0_TIOA2_ID ID_PIOA\r
+#define PIN_TC0_TIOA2_TYPE PIO_INPUT\r
+#define PIN_TC0_TIOA2_ATTR PIO_DEFAULT\r
+\r
+/** PWMC PWM0 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH0 {PIO_PC18B_PWMH0, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_PWMC_PWMH0_TRIG PIO_PC18_IDX\r
+#define PIN_PWMC_PWMH0_TRIG_FLAG PIO_PERIPH_B | PIO_DEFAULT\r
+/** PWMC PWM0 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML0 {PIO_PA19B_PWML0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PWMC PWM1 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH1 {PIO_PC19B_PWMH1, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PWMC PWM1 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML1 {PIO_PA20B_PWML1, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PWMC PWM2 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH2 {PIO_PC20B_PWMH2, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PWMC PWM2 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML2 {PIO_PA16C_PWML2, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}\r
+/** PWMC PWM3 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH3 {PIO_PC21B_PWMH3, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PWMC PWM3 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML3 {PIO_PA15C_PWML3, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}\r
+/** PWM pins definition for LED0 */\r
+#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0\r
+/** PWM pins definition for LED1 */\r
+#define PIN_PWM_LED1 PIN_PWMC_PWMH1, PIN_PWMC_PWML1\r
+/** PWM pins definition for LED2 */\r
+#define PIN_PWM_LED2 PIN_PWMC_PWMH2, PIN_PWMC_PWML2\r
+/** PWM channel for LED0 */\r
+#define CHANNEL_PWM_LED0 0\r
+/** PWM channel for LED1 */\r
+#define CHANNEL_PWM_LED1 1\r
+/** PWM channel for LED2 */\r
+#define CHANNEL_PWM_LED2 2\r
+\r
+/** PWM LED0 pin definitions. */\r
+#define PIN_PWM_LED0_GPIO PIO_PA19_IDX\r
+#define PIN_PWM_LED0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define PIN_PWM_LED0_CHANNEL PWM_CHANNEL_0\r
+\r
+/** PWM LED1 pin definitions. */\r
+#define PIN_PWM_LED1_GPIO PIO_PA20_IDX\r
+#define PIN_PWM_LED1_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define PIN_PWM_LED1_CHANNEL PWM_CHANNEL_1\r
+\r
+/** PWM LED2 pin definitions. */\r
+#define PIN_PWM_LED2_GPIO PIO_PC20_IDX\r
+#define PIN_PWM_LED2_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+/** SPI MISO pin definition. */\r
+#define PIN_SPI_MISO {PIO_PA12A_MISO, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SPI MOSI pin definition. */\r
+#define PIN_SPI_MOSI {PIO_PA13A_MOSI, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SPI SPCK pin definition. */\r
+#define PIN_SPI_SPCK {PIO_PA14A_SPCK, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SPI chip select pin definition. */\r
+#define PIN_SPI_NPCS0_PA11 {PIO_PA11A_NPCS0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** List of SPI pin definitions (MISO, MOSI & SPCK). */\r
+#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK\r
+/** SPI MISO pin definition. */\r
+#define SPI_MISO_GPIO (PIO_PA12_IDX)\r
+#define SPI_MISO_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** SPI MOSI pin definition. */\r
+#define SPI_MOSI_GPIO (PIO_PA13_IDX)\r
+#define SPI_MOSI_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** SPI SPCK pin definition. */\r
+#define SPI_SPCK_GPIO (PIO_PA14_IDX)\r
+#define SPI_SPCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/** SPI chip select 0 pin definition. (Only one configuration is possible) */\r
+#define SPI_NPCS0_GPIO (PIO_PA11_IDX)\r
+#define SPI_NPCS0_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** SPI chip select 1 pin definition. (multiple configurations are possible) */\r
+#define SPI_NPCS1_PA9_GPIO (PIO_PA9_IDX)\r
+#define SPI_NPCS1_PA9_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define SPI_NPCS1_PA31_GPIO (PIO_PA31_IDX)\r
+#define SPI_NPCS1_PA31_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define SPI_NPCS1_PB14_GPIO (PIO_PB14_IDX)\r
+#define SPI_NPCS1_PB14_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define SPI_NPCS1_PC4_GPIO (PIO_PC4_IDX)\r
+#define SPI_NPCS1_PC4_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+/** SPI chip select 2 pin definition. (multiple configurations are possible) */\r
+#define SPI_NPCS2_PA10_GPIO (PIO_PA10_IDX)\r
+#define SPI_NPCS2_PA10_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define SPI_NPCS2_PA30_GPIO (PIO_PA30_IDX)\r
+#define SPI_NPCS2_PA30_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define SPI_NPCS2_PB2_GPIO (PIO_PB2_IDX)\r
+#define SPI_NPCS2_PB2_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+/** SPI chip select 3 pin definition. (multiple configurations are possible) */\r
+#define SPI_NPCS3_PA3_GPIO (PIO_PA3_IDX)\r
+#define SPI_NPCS3_PA3_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define SPI_NPCS3_PA5_GPIO (PIO_PA5_IDX)\r
+#define SPI_NPCS3_PA5_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define SPI_NPCS3_PA22_GPIO (PIO_PA22_IDX)\r
+#define SPI_NPCS3_PA22_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+/** SSC pin Transmitter Data (TD) */\r
+#define PIN_SSC_TD {PIO_PA17A_TD, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SSC pin Transmitter Clock (TK) */\r
+#define PIN_SSC_TK {PIO_PA16A_TK, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SSC pin Transmitter FrameSync (TF) */\r
+#define PIN_SSC_TF {PIO_PA15A_TF, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SSC pins definition for codec. */\r
+#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF\r
+\r
+/** PCK0 */\r
+#define PIN_PCK0 (PIO_PA6_IDX)\r
+#define PIN_PCK0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+#define PIN_PCK_0_MASK PIO_PA6\r
+#define PIN_PCK_0_PIO PIOA\r
+#define PIN_PCK_0_ID ID_PIOA\r
+#define PIN_PCK_0_TYPE PIO_PERIPH_B\r
+#define PIN_PCK_0_ATTR PIO_DEFAULT\r
+#define PIN_PCK1 {PIO_PA17B_PCK1,PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_PCK_1_MASK PIO_PA17\r
+#define PIN_PCK_1_PIO PIOA\r
+#define PIN_PCK_1_ID ID_PIOA\r
+#define PIN_PCK_1_TYPE PIO_PERIPH_B\r
+#define PIN_PCK_1_ATTR PIO_DEFAULT\r
+\r
+/** PIO PARALLEL CAPTURE */\r
+/** Parallel Capture Mode Data Enable1 */\r
+#define PIN_PIODCEN1 PIO_PA15\r
+/** Parallel Capture Mode Data Enable2 */\r
+#define PIN_PIODCEN2 PIO_PA16\r
+\r
+/** TWI ver 3.xx */\r
+#define TWI_V3XX\r
+/** TWI0 data pin */\r
+#define PIN_TWI_TWD0 {PIO_PA3A_TWD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI0 clock pin */\r
+#define PIN_TWI_TWCK0 {PIO_PA4A_TWCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI0 pins */\r
+#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0\r
+/** TWI1 data pin */\r
+#define PIN_TWI_TWD1 {PIO_PB4A_TWD1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI1 clock pin */\r
+#define PIN_TWI_TWCK1 {PIO_PB5A_TWCK1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI1 pins */\r
+#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1\r
+\r
+/** USART0 pin RX */\r
+#define PIN_USART0_RXD {PIO_PA5A_RXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_RXD_IDX (PIO_PA5_IDX)\r
+#define PIN_USART0_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART0 pin TX */\r
+#define PIN_USART0_TXD {PIO_PA6A_TXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_TXD_IDX (PIO_PA6_IDX)\r
+#define PIN_USART0_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART0 pin CTS */\r
+#define PIN_USART0_CTS {PIO_PA8A_CTS0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_CTS_IDX (PIO_PA8_IDX)\r
+#define PIN_USART0_CTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART0 pin RTS */\r
+#define PIN_USART0_RTS {PIO_PA7A_RTS0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_RTS_IDX (PIO_PA7_IDX)\r
+#define PIN_USART0_RTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART0 pin SCK */\r
+#define PIN_USART0_SCK {PIO_PA2B_SCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_SCK_IDX (PIO_PA2_IDX)\r
+#define PIN_USART0_SCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/** USART1 pin RX */\r
+#define PIN_USART1_RXD {PIO_PA21A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_RXD_IDX (PIO_PA21_IDX)\r
+#define PIN_USART1_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART1 pin TX */\r
+#define PIN_USART1_TXD {PIO_PA22A_TXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_TXD_IDX (PIO_PA22_IDX)\r
+#define PIN_USART1_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART1 pin CTS */\r
+#define PIN_USART1_CTS {PIO_PA25A_CTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_CTS_IDX (PIO_PA25_IDX)\r
+#define PIN_USART1_CTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART1 pin RTS */\r
+#define PIN_USART1_RTS {PIO_PA24A_RTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_RTS_IDX (PIO_PA24_IDX)\r
+#define PIN_USART1_RTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART1 pin ENABLE */\r
+#define PIN_USART1_EN {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+#define PIN_USART1_EN_IDX (PIO_PA23_IDX)\r
+#define PIN_USART1_EN_FLAGS (PIO_OUTPUT_0 | PIO_DEFAULT)\r
+/** USART1 pin SCK */\r
+#define PIN_USART1_SCK {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_SCK_IDX (PIO_PA23_IDX)\r
+#define PIN_USART1_SCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/** USB VBus monitoring pin definition. */\r
+#ifdef BOARD_REV_A\r
+#define PIN_USB_VBUS {PIO_PC23, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP}\r
+#endif\r
+\r
+#ifdef BOARD_REV_B\r
+#define PIN_USB_VBUS {PIO_PC21, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP}\r
+#endif\r
+\r
+/** NandFlash pins definition: OE. */\r
+#define PIN_EBI_NANDOE (PIO_PC9_IDX)\r
+#define PIN_EBI_NANDOE_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+/** NandFlash pins definition: WE. */\r
+#define PIN_EBI_NANDWE (PIO_PC10_IDX)\r
+#define PIN_EBI_NANDWE_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+/** NandFlash pins definition: CLE. */\r
+#define PIN_EBI_NANDCLE (PIO_PC17_IDX)\r
+#define PIN_EBI_NANDCLE_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+/** NandFlash pins definition: ALE. */\r
+#define PIN_EBI_NANDALE (PIO_PC16_IDX)\r
+#define PIN_EBI_NANDALE_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+/** NandFlash pins definition: DATA. */\r
+#define PIN_EBI_NANDIO_0 (PIO_PC0_IDX)\r
+#define PIN_EBI_NANDIO_0_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_1 (PIO_PC1_IDX)\r
+#define PIN_EBI_NANDIO_1_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_2 (PIO_PC2_IDX)\r
+#define PIN_EBI_NANDIO_2_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_3 (PIO_PC3_IDX)\r
+#define PIN_EBI_NANDIO_3_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_4 (PIO_PC4_IDX)\r
+#define PIN_EBI_NANDIO_4_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_5 (PIO_PC5_IDX)\r
+#define PIN_EBI_NANDIO_5_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_6 (PIO_PC6_IDX)\r
+#define PIN_EBI_NANDIO_6_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_7 (PIO_PC7_IDX)\r
+#define PIN_EBI_NANDIO_7_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+/** Nandflash chip enable pin definition. */\r
+#define PIN_NF_CE_IDX (PIO_PC14_IDX)\r
+#define PIN_NF_CE_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+/** Nandflash ready/busy pin definition. */\r
+#define PIN_NF_RB_IDX (PIO_PC18_IDX)\r
+#define PIN_NF_RB_FLAGS (PIO_INPUT | PIO_PULLUP)\r
+\r
+/* Chip select number for nand */\r
+#define BOARD_NAND_CS 0\r
+\r
+/* PIO definitions for Slider */\r
+#define SLIDER_IOMASK_SNS (uint32_t)(PIO_PA0 | PIO_PA2 | PIO_PA4)\r
+#define SLIDER_IOMASK_SNSK (uint32_t)(PIO_PA1 | PIO_PA3 | PIO_PA5)\r
+#define PINS_SLIDER_SNS {SLIDER_IOMASK_SNS, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+#define PINS_SLIDER_SNSK {SLIDER_IOMASK_SNSK, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/* PIO definitions for keys */\r
+#define KEY_IOMASK_SNS (uint32_t)(PIO_PC22 | PIO_PC24 | PIO_PC26 | PIO_PC28 | PIO_PC30)\r
+#define KEY_IOMASK_SNSK (uint32_t)(PIO_PC23 | PIO_PC25 | PIO_PC27 | PIO_PC29 | PIO_PC31)\r
+#define PINS_KEY_SNS {KEY_IOMASK_SNS, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+#define PINS_KEY_SNSK {KEY_IOMASK_SNSK, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/* PIOS for QTouch */\r
+#define PINS_QTOUCH PINS_SLIDER_SNS, PINS_SLIDER_SNSK, PINS_KEY_SNS, PINS_KEY_SNSK\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam3s_ek_usb "SAM3S-EK - USB device"\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_USB_BMATTRIBUTES\r
+ * - \ref CHIP_USB_UDP\r
+ * - \ref CHIP_USB_PULLUP_INTERNAL\r
+ * - \ref CHIP_USB_NUMENDPOINTS\r
+ * - \ref CHIP_USB_ENDPOINTS_MAXPACKETSIZE\r
+ * - \ref CHIP_USB_ENDPOINTS_BANKS\r
+ */\r
+\r
+/** USB attributes configuration descriptor (bus or self powered, remote wakeup) */\r
+#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP\r
+\r
+/** Indicates chip has an UDP Full Speed. */\r
+#define CHIP_USB_UDP\r
+\r
+/** Indicates chip has an internal pull-up. */\r
+#define CHIP_USB_PULLUP_INTERNAL\r
+\r
+/** Number of USB endpoints */\r
+#define CHIP_USB_NUMENDPOINTS 8\r
+\r
+/** Endpoints max packet size */\r
+#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \\r
+ ((i == 0) ? 64 : \\r
+ ((i == 1) ? 64 : \\r
+ ((i == 2) ? 64 : \\r
+ ((i == 3) ? 64 : \\r
+ ((i == 4) ? 512 : \\r
+ ((i == 5) ? 512 : \\r
+ ((i == 6) ? 64 : \\r
+ ((i == 7) ? 64 : 0 ))))))))\r
+\r
+/** Endpoints Number of Bank */\r
+#define CHIP_USB_ENDPOINTS_BANKS(i) \\r
+ ((i == 0) ? 1 : \\r
+ ((i == 1) ? 2 : \\r
+ ((i == 2) ? 2 : \\r
+ ((i == 3) ? 1 : \\r
+ ((i == 4) ? 2 : \\r
+ ((i == 5) ? 2 : \\r
+ ((i == 6) ? 2 : \\r
+ ((i == 7) ? 2 : 0 ))))))))\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam3s_ek_extcomp "SAM3S-EK - External components"\r
+ * This page lists the definitions related to external on-board components\r
+ * located in the board.h file for the SAM3S-EK.\r
+ *\r
+ * SD Card\r
+ * - \ref BOARD_SD_PINS\r
+ * - \ref BOARD_SD_PIN_CD\r
+ *\r
+ * LCD\r
+ * - \ref BOARD_LCD_ILI9325\r
+ * - \ref BOARD_LCD_PINS\r
+ * - \ref BOARD_BACKLIGHT_PIN\r
+ * - \ref BOARD_LCD_BASE\r
+ * - \ref BOARD_LCD_RS\r
+ *\r
+ * TouchScreen\r
+ * - \ref BOARD_TSC_ADS7843\r
+ * - \ref PIN_TCS_IRQ\r
+ * - \ref PIN_TCS_BUSY\r
+ * - \ref BOARD_TSC_SPI_BASE\r
+ * - \ref BOARD_TSC_SPI_ID\r
+ * - \ref BOARD_TSC_SPI_PINS\r
+ * - \ref BOARD_TSC_NPCS\r
+ * - \ref BOARD_TSC_NPCS_PIN\r
+ *\r
+ * SmartCard\r
+ * - \ref SMARTCARD_CONNECT_PIN\r
+ * - \ref PIN_ISO7816_RSTMC\r
+ * - \ref PINS_ISO7816\r
+ */\r
+\r
+/** HSMCI pins that shall be configured to access the SD card. */\r
+#define BOARD_SD_PINS PINS_HSMCI\r
+/** HSMCI Card Detect pin. */\r
+#define BOARD_SD_PIN_CD PIN_HSMCI_CD\r
+\r
+/** Indicates board has an ILI9325 external component to manage LCD. */\r
+#define BOARD_LCD_ILI9325\r
+\r
+/** Backlight pin definition. */\r
+#define BOARD_BACKLIGHT PIO_PC13_IDX\r
+#define BOARD_BACKLIGHT_FLAG PIO_OUTPUT_0 | PIO_DEFAULT\r
+#define BOARD_BACKLIGHT_PIN {PIO_PC13, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT}\r
+#define PIN_BOARD_BACKLIGHT_MASK PIO_PC13\r
+#define PIN_BOARD_BACKLIGHT_PIO PIOC\r
+#define PIN_BOARD_BACKLIGHT_ID ID_PIOC\r
+#define PIN_BOARD_BACKLIGHT_TYPE PIO_OUTPUT_0\r
+#define PIN_BOARD_BACKLIGHT_ATTR PIO_PULLUP\r
+/** Define ILI9325 base address. */\r
+#define BOARD_LCD_BASE 0x61000000\r
+/** Define ILI9325 register select signal. */\r
+#define BOARD_LCD_RS (1 << 1)\r
+\r
+/** Indicates board has an ADS7843 external component to manage Touch Screen */\r
+#define BOARD_TSC_ADS7843\r
+\r
+/** Definition of MMA7341L x,y,z axis channel number */\r
+#define MMA7341L_ADC_CHANNEL_X 2\r
+#define MMA7341L_ADC_CHANNEL_Y 6\r
+#define MMA7341L_ADC_CHANNEL_Z 7\r
+\r
+/** MMA7341L mode set pin definition. */\r
+#define PIN_MMA7341L_MODE PIO_PC13_IDX\r
+#define PIN_MMA7341L_MODE_FLAG PIO_OUTPUT_1 | PIO_DEFAULT\r
+\r
+/** MMA7341L X,Y,Z axis pin definition. */\r
+#define PIN_MMA7341L_X_AXIS PIO_PB3_IDX\r
+#define PIN_MMA7341L_X_AXIS_FLAG PIO_INPUT | PIO_DEFAULT\r
+#define PIN_MMA7341L_Y_AXIS PIO_PC17_IDX\r
+#define PIN_MMA7341L_Y_AXIS_FLAG PIO_INPUT | PIO_DEFAULT\r
+#define PIN_MMA7341L_Z_AXIS PIO_PC18_IDX\r
+#define PIN_MMA7341L_Z_AXIS_FLAG PIO_INPUT | PIO_DEFAULT\r
+\r
+/** Touchscreen controller IRQ pin definition. */\r
+#ifdef BOARD_REV_A\r
+#define PIN_TSC_IRQ_IDX PIO_PA4_IDX\r
+#define PIN_TSC_IRQ_FLAG PIO_INPUT | PIO_PULLUP\r
+#define PIN_TSC_IRQ {PIO_PA4, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#define PIN_TSC_IRQ_MASK PIO_PA4\r
+#define PIN_TSC_IRQ_PIO PIOA\r
+#define PIN_TSC_IRQ_ID ID_PIOA\r
+#define PIN_TSC_IRQ_TYPE PIO_INPUT\r
+#define PIN_TSC_IRQ_ATTR PIO_PULLUP\r
+#define PIN_TSC_IRQ_WUP_ID (1 << 3)\r
+/** Touchscreen controller Busy pin definition. */\r
+#define PIN_TSC_BUSY_IDX PIO_PA5_IDX\r
+#define PIN_TSC_BUSY_FLAG PIO_INPUT | PIO_PULLUP\r
+#define PIN_TSC_BUSY {PIO_PA5, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#define PIN_TSC_BUSY_MASK PIO_PA5\r
+#define PIN_TSC_BUSY_PIO PIOA\r
+#define PIN_TSC_BUSY_ID ID_PIOA\r
+#define PIN_TSC_BUSY_TYPE PIO_INPUT\r
+#define PIN_TSC_BUSY_ATTR PIO_PULLUP\r
+#endif\r
+\r
+#ifdef BOARD_REV_B\r
+#define PIN_TSC_IRQ_IDX PIO_PA16_IDX\r
+#define PIN_TSC_IRQ_FLAG PIO_INPUT | PIO_PULLUP\r
+#define PIN_TSC_IRQ {PIO_PA16, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#define PIN_TSC_IRQ_MASK PIO_PA16\r
+#define PIN_TSC_IRQ_PIO PIOA\r
+#define PIN_TSC_IRQ_ID ID_PIOA\r
+#define PIN_TSC_IRQ_TYPE PIO_INPUT\r
+#define PIN_TSC_IRQ_ATTR PIO_PULLUP\r
+#define PIN_TSC_IRQ_WUP_ID (1 << 15)\r
+/** Touchscreen controller Busy pin definition. */\r
+#define PIN_TSC_BUSY_IDX PIO_PA17_IDX\r
+#define PIN_TSC_BUSY_FLAG PIO_INPUT | PIO_PULLUP\r
+#define PIN_TSC_BUSY {PIO_PA17, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#define PIN_TSC_BUSY_MASK PIO_PA17\r
+#define PIN_TSC_BUSY_PIO PIOA\r
+#define PIN_TSC_BUSY_ID ID_PIOA\r
+#define PIN_TSC_BUSY_TYPE PIO_INPUT\r
+#define PIN_TSC_BUSY_ATTR PIO_PULLUP\r
+#endif\r
+\r
+/** Base address of SPI peripheral connected to the touchscreen controller. */\r
+#define BOARD_TSC_SPI_BASE SPI\r
+/** Identifier of SPI peripheral connected to the touchscreen controller. */\r
+#define BOARD_TSC_SPI_ID ID_SPI\r
+/** Pins of the SPI peripheral connected to the touchscreen controller. */\r
+#define BOARD_TSC_SPI_PINS PINS_SPI\r
+/** Chip select connected to the touchscreen controller. */\r
+#define BOARD_TSC_NPCS 0\r
+/** Chip select pin connected to the touchscreen controller. */\r
+#define BOARD_TSC_NPCS_PIN PIN_SPI_NPCS0_PA11\r
+\r
+/// Smartcard detection pin\r
+//#define SMARTCARD_CONNECT_PIN {1 << 13, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/// PIN used for reset the smartcard\r
+#define PIN_ISO7816_RSTMC {1 << 11, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+/// Pins used for connect the smartcard\r
+#define PINS_ISO7816 PIN_USART1_TXD, PIN_USART1_SCK, PIN_ISO7816_RSTMC\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam3s_ek_mem "SAM3S-EK - Memories"\r
+ * This page lists definitions related to internal & external on-board memories.\r
+ *\r
+ * \section NandFlash\r
+ * - \ref BOARD_NF_COMMAND_ADDR\r
+ * - \ref BOARD_NF_ADDRESS_ADDR\r
+ * - \ref BOARD_NF_DATA_ADDR\r
+ *\r
+ * \section NorFlash\r
+ * - \ref BOARD_NORFLASH_ADDR\r
+ * - \ref BOARD_NORFLASH_DFT_BUS_SIZE\r
+ */\r
+\r
+/** Address for transferring command bytes to the nandflash. */\r
+#define BOARD_NF_COMMAND_ADDR 0x60400000\r
+/** Address for transferring address bytes to the nandflash. */\r
+#define BOARD_NF_ADDRESS_ADDR 0x60200000\r
+/** Address for transferring data bytes to the nandflash. */\r
+#define BOARD_NF_DATA_ADDR 0x60000000\r
+/* Bus width for NAND */\r
+#define CONF_NF_BUSWIDTH 8\r
+/* Access timing for NAND */\r
+#define CONF_NF_SETUP_TIMING (SMC_SETUP_NWE_SETUP(0) \\r
+ | SMC_SETUP_NCS_WR_SETUP(1) \\r
+ | SMC_SETUP_NRD_SETUP(0) \\r
+ | SMC_SETUP_NCS_RD_SETUP(1))\r
+#define CONF_NF_PULSE_TIMING (SMC_PULSE_NWE_PULSE(2) \\r
+ | SMC_PULSE_NCS_WR_PULSE(3) \\r
+ | SMC_PULSE_NRD_PULSE(4) \\r
+ | SMC_PULSE_NCS_RD_PULSE(4))\r
+#define CONF_NF_CYCLE_TIMING (SMC_CYCLE_NWE_CYCLE(4) \\r
+ | SMC_CYCLE_NRD_CYCLE(7))\r
+\r
+/** Address for transferring command bytes to the norflash. */\r
+#define BOARD_NORFLASH_ADDR 0x63000000\r
+/** Default NOR bus size after power up reset */\r
+#define BOARD_NORFLASH_DFT_BUS_SIZE 8\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam3s_ek_chipdef "SAM3S-EK - Individual chip definition"\r
+ * This page lists the definitions related to different chip's definition\r
+ * located in the board.h file for the SAM3S-EK.\r
+ *\r
+ * \section USART\r
+ * - \ref BOARD_PIN_USART_RXD\r
+ * - \ref BOARD_PIN_USART_TXD\r
+ * - \ref BOARD_PIN_USART_CTS\r
+ * - \ref BOARD_PIN_USART_RTS\r
+ * - \ref BOARD_PIN_USART_EN\r
+ * - \ref BOARD_USART_BASE\r
+ * - \ref BOARD_ID_USART\r
+ */\r
+\r
+/** Rtc */\r
+#define BOARD_RTC_ID ID_RTC\r
+\r
+/** TWI ID for EEPROM application to use */\r
+#define BOARD_ID_TWI_EEPROM ID_TWI1\r
+/** TWI Base for TWI EEPROM application to use */\r
+#define BOARD_BASE_TWI_EEPROM TWI1\r
+/** TWI pins for EEPROM application to use */\r
+#define BOARD_PINS_TWI_EEPROM PINS_TWI1\r
+\r
+/** USART RX pin for application */\r
+#define BOARD_PIN_USART_RXD PIN_USART1_RXD\r
+/** USART TX pin for application */\r
+#define BOARD_PIN_USART_TXD PIN_USART1_TXD\r
+/** USART CTS pin for application */\r
+#define BOARD_PIN_USART_CTS PIN_USART1_CTS\r
+/** USART RTS pin for application */\r
+#define BOARD_PIN_USART_RTS PIN_USART1_RTS\r
+/** USART ENABLE pin for application */\r
+#define BOARD_PIN_USART_EN PIN_USART1_EN\r
+/** USART Base for application */\r
+#define BOARD_USART_BASE USART1\r
+/** USART ID for application */\r
+#define BOARD_ID_USART ID_USART1\r
+\r
+#define CONSOLE_UART UART0\r
+#define CONSOLE_UART_ID ID_UART0\r
+\r
+/* RE pin. */\r
+#define PIN_RE_IDX PIN_USART1_CTS_IDX\r
+#define PIN_RE_FLAGS (PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/* IRDA SD pin. */\r
+#define PIN_IRDA_SD_IDX PIN_USART1_CTS_IDX\r
+#define PIN_IRDA_SD_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+/* TXD pin configuration. */\r
+#define PIN_USART_TXD_IDX PIN_USART1_TXD_IDX\r
+#define PIN_USART_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define PIN_USART_TXD_IO_FLAGS (PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/* ISO7816 example relate PIN definition. */\r
+#define ISO7816_USART_ID ID_USART1\r
+#define ISO7816_USART USART1\r
+#define PIN_ISO7816_RST_IDX PIO_PA15_IDX\r
+#define PIN_ISO7816_RST_FLAG (PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+#endif // _SAM3S_EK2_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) Controller driver for SAM.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "pio.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * The Parallel Input/Output Controller (PIO) manages up to 32 fully\r
+ * programmable input/output lines. Each I/O line may be dedicated as a\r
+ * general-purpose I/O or be assigned to a function of an embedded peripheral.\r
+ * This assures effective optimization of the pins of a product.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef FREQ_SLOW_CLOCK_EXT\r
+/* External slow clock frequency (hz) */\r
+#define FREQ_SLOW_CLOCK_EXT 32768\r
+#endif\r
+\r
+/**\r
+ * \brief Configure PIO internal pull-up.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be\r
+ * configured.\r
+ */\r
+void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_up_enable)\r
+{\r
+ /* Enable the pull-up(s) if necessary */\r
+ if (ul_pull_up_enable) {\r
+ p_pio->PIO_PUER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_PUDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure Glitch or Debouncing filter for the specified input(s).\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_cut_off Cuts off frequency for debouncing filter.\r
+ */\r
+void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_cut_off)\r
+{\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ /* Set Debouncing, 0 bit field no effect */\r
+ p_pio->PIO_IFSCER = ul_mask;\r
+#elif (SAM3XA || SAM3U)\r
+ /* Set Debouncing, 0 bit field no effect */\r
+ p_pio->PIO_DIFSR = ul_mask;\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ /* The debouncing filter can filter a pulse of less than 1/2 Period of a\r
+ programmable Divided Slow Clock:\r
+ Tdiv_slclk = ((DIV+1)*2).Tslow_clock */\r
+ p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT /\r
+ (2 * (ul_cut_off))) - 1);\r
+}\r
+\r
+/**\r
+ * \brief Set a high output level on all the PIOs defined in ul_mask.\r
+ * This has no immediate effects on PIOs that are not output, but the PIO\r
+ * controller will save the value if they are changed to outputs.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_SODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Set a low output level on all the PIOs defined in ul_mask.\r
+ * This has no immediate effects on PIOs that are not output, but the PIO\r
+ * controller will save the value if they are changed to outputs.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_clear(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_CODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if one or more PIOs of the given Pin instance currently have\r
+ * a high level; otherwise returns 0. This method returns the actual value that\r
+ * is being read on the pin. To return the supposed output value of a pin, use\r
+ * pio_get_output_data_status() instead.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ *\r
+ * \retval 1 at least one PIO currently has a high level.\r
+ * \retval 0 all PIOs have a low level.\r
+ */\r
+uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask)\r
+{\r
+ uint32_t ul_reg;\r
+\r
+ if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) {\r
+ ul_reg = p_pio->PIO_ODSR;\r
+ } else {\r
+ ul_reg = p_pio->PIO_PDSR;\r
+ }\r
+\r
+ if ((ul_reg & ul_mask) == 0) {\r
+ return 0;\r
+ } else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure IO of a PIO controller as being controlled by a specific\r
+ * peripheral.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask)\r
+{\r
+ uint32_t ul_sr;\r
+\r
+ /* Disable interrupts on the pin(s) */\r
+ p_pio->PIO_IDR = ul_mask;\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_B:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_C:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_D:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);\r
+ break;\r
+\r
+ // other types are invalid in this function\r
+ case PIO_INPUT:\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ case PIO_NOT_A_PIN:\r
+ return;\r
+ }\r
+#elif (SAM3XA|| SAM3U)\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ ul_sr = p_pio->PIO_ABSR;\r
+ p_pio->PIO_ABSR &= (~ul_mask & ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_B:\r
+ ul_sr = p_pio->PIO_ABSR;\r
+ p_pio->PIO_ABSR = (ul_mask | ul_sr);\r
+ break;\r
+\r
+ // other types are invalid in this function\r
+ case PIO_INPUT:\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ case PIO_NOT_A_PIN:\r
+ return;\r
+ }\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ // Remove the pins from under the control of PIO\r
+ p_pio->PIO_PDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Configure one or more pin(s) or a PIO controller as inputs.\r
+ * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can\r
+ * be enabled.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask indicating which pin(s) to configure as input(s).\r
+ * \param ul_attribute PIO attribute(s).\r
+ */\r
+void pio_set_input(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attribute)\r
+{\r
+ pio_disable_interrupt(p_pio, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP);\r
+\r
+ /* Enable Input Filter if necessary */\r
+ if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) {\r
+ p_pio->PIO_IFER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_IFDR = ul_mask;\r
+ }\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ /* Enable de-glitch or de-bounce if necessary */\r
+ if (ul_attribute & PIO_DEGLITCH) {\r
+ p_pio->PIO_IFSCDR = ul_mask;\r
+ } else {\r
+ if (ul_attribute & PIO_DEBOUNCE) {\r
+ p_pio->PIO_IFSCER = ul_mask;\r
+ }\r
+ }\r
+#elif (SAM3XA|| SAM3U)\r
+ /* Enable de-glitch or de-bounce if necessary */\r
+ if (ul_attribute & PIO_DEGLITCH) {\r
+ p_pio->PIO_SCIFSR = ul_mask;\r
+ } else {\r
+ if (ul_attribute & PIO_DEBOUNCE) {\r
+ p_pio->PIO_SCIFSR = ul_mask;\r
+ }\r
+ }\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ /* Configure pin as input */\r
+ p_pio->PIO_ODR = ul_mask;\r
+ p_pio->PIO_PER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Configure one or more pin(s) of a PIO controller as outputs, with\r
+ * the given default value. Optionally, the multi-drive feature can be enabled\r
+ * on the pin(s).\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask indicating which pin(s) to configure.\r
+ * \param ul_default_level Default level on the pin(s).\r
+ * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as\r
+ * open-drain.\r
+ * \param ul_pull_up_enable Indicates if the pin shall have its pull-up\r
+ * activated.\r
+ */\r
+void pio_set_output(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_default_level,\r
+ const uint32_t ul_multidrive_enable,\r
+ const uint32_t ul_pull_up_enable)\r
+{\r
+ pio_disable_interrupt(p_pio, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, ul_pull_up_enable);\r
+\r
+ /* Enable multi-drive if necessary */\r
+ if (ul_multidrive_enable) {\r
+ p_pio->PIO_MDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_MDDR = ul_mask;\r
+ }\r
+\r
+ /* Set default value */\r
+ if (ul_default_level) {\r
+ p_pio->PIO_SODR = ul_mask;\r
+ } else {\r
+ p_pio->PIO_CODR = ul_mask;\r
+ }\r
+\r
+ /* Configure pin(s) as output(s) */\r
+ p_pio->PIO_OER = ul_mask;\r
+ p_pio->PIO_PER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_attribute Pins attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute)\r
+{\r
+ /* Configure pins */\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ case PIO_PERIPH_B:\r
+# if (SAM3S || SAM3N || SAM4S)\r
+ case PIO_PERIPH_C:\r
+ case PIO_PERIPH_D:\r
+# endif\r
+ pio_set_peripheral(p_pio, ul_type, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP));\r
+ break;\r
+\r
+ case PIO_INPUT:\r
+ pio_set_input(p_pio, ul_mask, ul_attribute);\r
+ break;\r
+\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1),\r
+ (ul_attribute & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if one or more PIOs of the given Pin are configured to\r
+ * output a high level (even if they are not output).\r
+ * To get the actual value of the pin, use PIO_Get() instead.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s).\r
+ *\r
+ * \retval 1 At least one PIO is configured to output a high level.\r
+ * \retval 0 All PIOs are configured to output a low level.\r
+ */\r
+uint32_t pio_get_output_data_status(const Pio *p_pio,\r
+ const uint32_t ul_mask)\r
+{\r
+ if ((p_pio->PIO_ODSR & ul_mask) == 0) {\r
+ return 0;\r
+ } else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure PIO pin multi-driver.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be\r
+ * configured.\r
+ */\r
+void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_multi_driver_enable)\r
+{\r
+ /* Enable the multi-driver if necessary */\r
+ if (ul_multi_driver_enable) {\r
+ p_pio->PIO_MDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_MDDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get multi-driver status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The multi-driver mask value.\r
+ */\r
+uint32_t pio_get_multi_driver_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_MDSR;\r
+}\r
+\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+/**\r
+ * \brief Configure PIO pin internal pull-down.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall\r
+ * be configured.\r
+ */\r
+void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_down_enable)\r
+{\r
+ /* Enable the pull-down if necessary */\r
+ if (ul_pull_down_enable) {\r
+ p_pio->PIO_PPDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_PPDDR = ul_mask;\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable PIO output write for synchronous data output.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_OWER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable PIO output write.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_OWDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO output write status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The output write mask value.\r
+ */\r
+uint32_t pio_get_output_write_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_OWSR;\r
+}\r
+\r
+/**\r
+ * \brief Synchronously write on output pins.\r
+ * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are\r
+ * written.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_ODSR = ul_mask;\r
+}\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+/**\r
+ * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is\r
+ * active.\r
+ * Disabling the Schmitt Trigger is requested when using the QTouch Library.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_SCHMITT = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Get PIO pin schmitt trigger status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The schmitt trigger mask value.\r
+ */\r
+uint32_t pio_get_schmitt_trigger(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_SCHMITT;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Configure the given interrupt source.\r
+ * Interrupt can be configured to trigger on rising edge, falling edge,\r
+ * high level, low level or simply on level change.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt source bit map.\r
+ * \param ul_attr Interrupt source attributes.\r
+ */\r
+void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attr)\r
+{\r
+ /* Configure additional interrupt mode registers. */\r
+ if (ul_attr & PIO_IT_AIME) {\r
+ /* Enable additional interrupt mode. */\r
+ p_pio->PIO_AIMER = ul_mask;\r
+\r
+ /* If bit field of the selected pin is 1, set as\r
+ Rising Edge/High level detection event. */\r
+ if (ul_attr & PIO_IT_RE_OR_HL) {\r
+ /* Rising Edge or High Level */\r
+ p_pio->PIO_REHLSR = ul_mask;\r
+ } else {\r
+ /* Falling Edge or Low Level */\r
+ p_pio->PIO_FELLSR = ul_mask;\r
+ }\r
+\r
+ /* If bit field of the selected pin is 1, set as\r
+ edge detection source. */\r
+ if (ul_attr & PIO_IT_EDGE) {\r
+ /* Edge select */\r
+ p_pio->PIO_ESR = ul_mask;\r
+ } else {\r
+ /* Level select */\r
+ p_pio->PIO_LSR = ul_mask;\r
+ }\r
+ } else {\r
+ /* Disable additional interrupt mode. */\r
+ p_pio->PIO_AIMDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable the given interrupt source.\r
+ * The PIO must be configured as an NVIC interrupt source as well.\r
+ * The status register of the corresponding PIO controller is cleared\r
+ * prior to enabling the interrupt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_ISR;\r
+ p_pio->PIO_IER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable a given interrupt source, with no added side effects.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_IDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt status mask value.\r
+ */\r
+uint32_t pio_get_interrupt_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_ISR;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt mask.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pio_get_interrupt_mask(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Set additional interrupt mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ * \param ul_attribute Pin(s) attributes.\r
+ */\r
+void pio_set_additional_interrupt_mode(Pio *p_pio,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute)\r
+{\r
+ /* Enables additional interrupt mode if needed */\r
+ if (ul_attribute & PIO_IT_AIME) {\r
+ /* Enables additional interrupt mode */\r
+ p_pio->PIO_AIMER = ul_mask;\r
+\r
+ /* Configures the Polarity of the event detection */\r
+ /* (Rising/Falling Edge or High/Low Level) */\r
+ if (ul_attribute & PIO_IT_RE_OR_HL) {\r
+ /* Rising Edge or High Level */\r
+ p_pio->PIO_REHLSR = ul_mask;\r
+ } else {\r
+ /* Falling Edge or Low Level */\r
+ p_pio->PIO_FELLSR = ul_mask;\r
+ }\r
+\r
+ /* Configures the type of event detection (Edge or Level) */\r
+ if (ul_attribute & PIO_IT_EDGE) {\r
+ /* Edge select */\r
+ p_pio->PIO_ESR = ul_mask;\r
+ } else {\r
+ /* Level select */\r
+ p_pio->PIO_LSR = ul_mask;\r
+ }\r
+ } else {\r
+ /* Disable additional interrupt mode */\r
+ p_pio->PIO_AIMDR = ul_mask;\r
+ }\r
+}\r
+\r
+#define PIO_WPMR_WPKEY_VALUE PIO_WPMR_WPKEY(0x50494Fu)\r
+\r
+/**\r
+ * \brief Enable or disable write protect of PIO registers.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_enable 1 to enable, 0 to disable.\r
+ */\r
+void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable)\r
+{\r
+ p_pio->PIO_WPMR = PIO_WPMR_WPKEY_VALUE | ul_enable;\r
+}\r
+\r
+/**\r
+ * \brief Read write protect status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return Return write protect status.\r
+ */\r
+uint32_t pio_get_writeprotect_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_WPSR;\r
+}\r
+\r
+#define PIO_DELTA ((uint32_t) PIOB - (uint32_t) PIOA)\r
+\r
+/**\r
+ * \brief Return the value of a pin.\r
+ *\r
+ * \param ul_pin The pin number.\r
+ *\r
+ * \return The pin value.\r
+ *\r
+ * \note If pin is output: a pull-up or pull-down could hide the actual value.\r
+ * The function \ref pio_get can be called to get the actual pin output\r
+ * level.\r
+ * \note If pin is input: PIOx must be clocked to sample the signal.\r
+ * See PMC driver.\r
+ */\r
+uint32_t pio_get_pin_value(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO pin to 1.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called beforehand.\r
+ */\r
+void pio_set_pin_high(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO pin to 0.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called before.\r
+ */\r
+void pio_set_pin_low(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+/**\r
+ * \brief Toggle a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called before.\r
+ */\r
+void pio_toggle_pin(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) {\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);\r
+ } else {\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param ul_pin Bitmask of one or more pin(s) to configure.\r
+ * \param ul_flags Pins attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+\r
+ /* Configure pins */\r
+ switch (ul_flags & PIO_TYPE_Msk) {\r
+ case PIO_TYPE_PIO_PERIPH_A:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_B:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+# if (SAM3S || SAM3N || SAM4S)\r
+ case PIO_TYPE_PIO_PERIPH_C:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_D:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+# endif\r
+\r
+ case PIO_TYPE_PIO_INPUT:\r
+ pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags);\r
+ break;\r
+\r
+ case PIO_TYPE_PIO_OUTPUT_0:\r
+ case PIO_TYPE_PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, (1 << (ul_pin & 0x1F)),\r
+ ((ul_flags & PIO_TYPE_PIO_OUTPUT_1)\r
+ == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,\r
+ (ul_flags & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_flags & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO port to 1.\r
+ *\r
+ * \param p_pio Base address of the PIO port.\r
+ * \param ul_mask Bitmask of one or more pin(s) to toggle.\r
+ */\r
+void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO port to 0.\r
+ *\r
+ * \param p_pio Base address of the PIO port.\r
+ * \param ul_mask Bitmask of one or more pin(s) to toggle.\r
+ */\r
+void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Toggle a GPIO group.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ if (p_pio->PIO_ODSR & ul_mask) {\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = ul_mask;\r
+ } else {\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_flags Pin(s) attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure_pin_group(Pio *p_pio,\r
+ uint32_t ul_mask, const uint32_t ul_flags)\r
+{\r
+ /* Configure pins */\r
+ switch (ul_flags & PIO_TYPE_Msk) {\r
+ case PIO_TYPE_PIO_PERIPH_A:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_B:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+# if (SAM3S || SAM3N || SAM4S)\r
+ case PIO_TYPE_PIO_PERIPH_C:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_D:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+# endif\r
+\r
+ case PIO_TYPE_PIO_INPUT:\r
+ pio_set_input(p_pio, ul_mask, ul_flags);\r
+ break;\r
+\r
+ case PIO_TYPE_PIO_OUTPUT_0:\r
+ case PIO_TYPE_PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, ul_mask,\r
+ ((ul_flags & PIO_TYPE_PIO_OUTPUT_1)\r
+ == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,\r
+ (ul_flags & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_flags & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Enable interrupt for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref gpio_configure_pin must be called before.\r
+ */\r
+void pio_enable_pin_interrupt(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ p_pio->PIO_IER = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Disable interrupt for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref gpio_configure_pin must be called before.\r
+ */\r
+void pio_disable_pin_interrupt(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ p_pio->PIO_IDR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return GPIO port for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return Pointer to \ref Pio struct for GPIO port.\r
+ */\r
+Pio *pio_get_pin_group(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ return p_pio;\r
+}\r
+\r
+/**\r
+ * \brief Return GPIO port peripheral ID for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return GPIO port peripheral ID.\r
+ */\r
+uint32_t pio_get_pin_group_id(uint32_t ul_pin)\r
+{\r
+ uint32_t ul_id = ID_PIOA + (ul_pin >> 5);\r
+ return ul_id;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return GPIO port pin mask for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return GPIO port pin mask.\r
+ */\r
+uint32_t pio_get_pin_group_mask(uint32_t ul_pin)\r
+{\r
+ uint32_t ul_mask = 1 << (ul_pin & 0x1F);\r
+ return ul_mask;\r
+}\r
+\r
+\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Configure PIO capture mode.\r
+ * \note PIO capture mode will be disabled automatically.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mode Bitmask of one or more modes.\r
+ */\r
+void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode)\r
+{\r
+ ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */\r
+ p_pio->PIO_PCMR = ul_mode;\r
+}\r
+\r
+/**\r
+ * \brief Enable PIO capture mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ */\r
+void pio_capture_enable(Pio *p_pio)\r
+{\r
+ p_pio->PIO_PCMR |= PIO_PCMR_PCEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable PIO capture mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ */\r
+void pio_capture_disable(Pio *p_pio)\r
+{\r
+ p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN);\r
+}\r
+\r
+/**\r
+ * \brief Read from Capture Reception Holding Register.\r
+ * Data presence should be tested before any read attempt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param pul_data Pointer to store the data.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 I/O Failure, Capture data is not ready.\r
+ */\r
+uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data)\r
+{\r
+ /* Check if the data is ready */\r
+ if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) {\r
+ return 1;\r
+ }\r
+\r
+ /* Read data */\r
+ *pul_data = p_pio->PIO_PCRHR;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable the given interrupt source of PIO capture. The status\r
+ * register of the corresponding PIO capture controller is cleared prior\r
+ * to enabling the interrupt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_PCISR;\r
+ p_pio->PIO_PCIER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable a given interrupt source of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_PCIDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt status of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt status mask value.\r
+ */\r
+uint32_t pio_capture_get_interrupt_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_PCISR;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt mask of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_PCIMR;\r
+}\r
+\r
+/**\r
+ * \brief Get PDC registers base address.\r
+ *\r
+ * \param p_pio Pointer to an PIO peripheral.\r
+ *\r
+ * \return PIOA PDC register base address.\r
+ */\r
+Pdc *pio_capture_get_pdc_base(const Pio *p_pio)\r
+{\r
+ p_pio = p_pio; /* Stop warning */\r
+ return PDC_PIOA;\r
+}\r
+#endif\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) Controller driver for SAM.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef PIO_H_INCLUDED\r
+#define PIO_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/* GPIO Support */\r
+#define PIO_TYPE_Pos 27\r
+/* PIO Type Mask */\r
+#define PIO_TYPE_Msk (0xFu << PIO_TYPE_Pos)\r
+/* The pin is not a function pin. */\r
+#define PIO_TYPE_NOT_A_PIN (0x0u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral A. */\r
+#define PIO_TYPE_PIO_PERIPH_A (0x1u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral B. */\r
+#define PIO_TYPE_PIO_PERIPH_B (0x2u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral C. */\r
+#define PIO_TYPE_PIO_PERIPH_C (0x3u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral D. */\r
+#define PIO_TYPE_PIO_PERIPH_D (0x4u << PIO_TYPE_Pos)\r
+/* The pin is an input. */\r
+#define PIO_TYPE_PIO_INPUT (0x5u << PIO_TYPE_Pos)\r
+/* The pin is an output and has a default level of 0. */\r
+#define PIO_TYPE_PIO_OUTPUT_0 (0x6u << PIO_TYPE_Pos)\r
+/* The pin is an output and has a default level of 1. */\r
+#define PIO_TYPE_PIO_OUTPUT_1 (0x7u << PIO_TYPE_Pos)\r
+\r
+typedef enum _pio_type {\r
+ PIO_NOT_A_PIN = PIO_TYPE_NOT_A_PIN,\r
+ PIO_PERIPH_A = PIO_TYPE_PIO_PERIPH_A,\r
+ PIO_PERIPH_B = PIO_TYPE_PIO_PERIPH_B,\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ PIO_PERIPH_C = PIO_TYPE_PIO_PERIPH_C,\r
+ PIO_PERIPH_D = PIO_TYPE_PIO_PERIPH_D,\r
+#endif\r
+ PIO_INPUT = PIO_TYPE_PIO_INPUT,\r
+ PIO_OUTPUT_0 = PIO_TYPE_PIO_OUTPUT_0,\r
+ PIO_OUTPUT_1 = PIO_TYPE_PIO_OUTPUT_1\r
+} pio_type_t;\r
+\r
+/* Default pin configuration (no attribute). */\r
+#define PIO_DEFAULT (0u << 0)\r
+/* The internal pin pull-up is active. */\r
+#define PIO_PULLUP (1u << 0)\r
+/* The internal glitch filter is active. */\r
+#define PIO_DEGLITCH (1u << 1)\r
+/* The pin is open-drain. */\r
+#define PIO_OPENDRAIN (1u << 2)\r
+\r
+/* The internal debouncing filter is active. */\r
+#define PIO_DEBOUNCE (1u << 3)\r
+\r
+/* Enable additional interrupt modes. */\r
+#define PIO_IT_AIME (1u << 4)\r
+\r
+/* Interrupt High Level/Rising Edge detection is active. */\r
+#define PIO_IT_RE_OR_HL (1u << 5)\r
+/* Interrupt Edge detection is active. */\r
+#define PIO_IT_EDGE (1u << 6)\r
+\r
+/* Low level interrupt is active */\r
+#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME)\r
+/* High level interrupt is active */\r
+#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME)\r
+/* Falling edge interrupt is active */\r
+#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME)\r
+/* Rising edge interrupt is active */\r
+#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME)\r
+\r
+/*\r
+ * The #attribute# field is a bitmask that can either be set to PIO_DEFAULT,\r
+ * or combine (using bitwise OR '|') any number of the following constants:\r
+ * - PIO_PULLUP\r
+ * - PIO_DEGLITCH\r
+ * - PIO_DEBOUNCE\r
+ * - PIO_OPENDRAIN\r
+ * - PIO_IT_LOW_LEVEL\r
+ * - PIO_IT_HIGH_LEVEL\r
+ * - PIO_IT_FALL_EDGE\r
+ * - PIO_IT_RISE_EDGE\r
+ */\r
+void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_up_enable);\r
+void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_cut_off);\r
+void pio_set(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_clear(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask);\r
+void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask);\r
+void pio_set_input(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attribute);\r
+void pio_set_output(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_default_level,\r
+ const uint32_t ul_multidrive_enable,\r
+ const uint32_t ul_pull_up_enable);\r
+uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute);\r
+uint32_t pio_get_output_data_status(const Pio *p_pio,\r
+ const uint32_t ul_mask);\r
+void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_multi_driver_enable);\r
+uint32_t pio_get_multi_driver_status(const Pio *p_pio);\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_down_enable);\r
+#endif\r
+\r
+void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get_output_write_status(const Pio *p_pio);\r
+void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask);\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get_schmitt_trigger(const Pio *p_pio);\r
+#endif\r
+\r
+void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, const uint32_t ul_attr);\r
+void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get_interrupt_status(const Pio *p_pio);\r
+uint32_t pio_get_interrupt_mask(const Pio *p_pio);\r
+void pio_set_additional_interrupt_mode(Pio *p_pio,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute);\r
+void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable);\r
+uint32_t pio_get_writeprotect_status(const Pio *p_pio);\r
+\r
+#if (SAM3S || SAM4S)\r
+void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode);\r
+void pio_capture_enable(Pio *p_pio);\r
+void pio_capture_disable(Pio *p_pio);\r
+uint32_t pio_capture_read(const Pio *p_pio, uint32_t * pul_data);\r
+void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_capture_disable_interrupt(Pio * p_pio, const uint32_t ul_mask);\r
+uint32_t pio_capture_get_interrupt_status(const Pio *p_pio);\r
+uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio);\r
+Pdc *pio_capture_get_pdc_base(const Pio *p_pio);\r
+#endif\r
+\r
+/* GPIO Support */\r
+uint32_t pio_get_pin_value(uint32_t pin);\r
+void pio_set_pin_high(uint32_t pin);\r
+void pio_set_pin_low(uint32_t pin);\r
+void pio_toggle_pin(uint32_t pin);\r
+void pio_enable_pin_interrupt(uint32_t pin);\r
+void pio_disable_pin_interrupt(uint32_t pin);\r
+Pio *pio_get_pin_group(uint32_t pin);\r
+uint32_t pio_get_pin_group_id(uint32_t pin);\r
+uint32_t pio_get_pin_group_mask(uint32_t pin);\r
+uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags);\r
+void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask);\r
+void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask);\r
+void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask);\r
+uint32_t pio_configure_pin_group(Pio *p_pio, uint32_t ul_mask, const uint32_t ul_flags);\r
+\r
+/**\r
+ * \page sam_pio_quickstart Quick Start Guide for the SAM PIO driver\r
+ *\r
+ * This is the quick start guide for the \ref sam_drivers_pio_group "PIO Driver",\r
+ * with step-by-step instructions on how to configure and use the driver for\r
+ * specific use cases.\r
+ *\r
+ * The section described below can be compiled into e.g. the main application\r
+ * loop or any other function that will need to interface with the IO port.\r
+ *\r
+ * \section sam_pio_usecases PIO use cases\r
+ * - \ref sam_pio_quickstart_basic\r
+ * - \ref sam_pio_quickstart_use_case_2\r
+ *\r
+ * \section sam_pio_quickstart_basic Basic usage of the PIO driver\r
+ * This section will present a basic use case for the PIO driver. This use case\r
+ * will configure pin 23 on port A as output and pin 16 as an input with pullup,\r
+ * and then toggle the output pin's value to match that of the input pin.\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_prereq Prerequisites\r
+ * - \ref group_pmc "Power Management Controller driver"\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * pmc_enable_periph_clk(ID_PIOA);\r
+ *\r
+ * pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE);\r
+ * pio_set_input(PIOA, PIO_PA16, PIO_PULLUP);\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_setup_steps_workflow Workflow\r
+ * -# Enable the module clock to the PIOA peripheral:\r
+ * \code pmc_enable_periph_clk(ID_PIOA); \endcode\r
+ * -# Set pin 23 direction on PIOA as output, default low level:\r
+ * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode\r
+ * -# Set pin 16 direction on PIOA as input, with pullup:\r
+ * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_example_code Example code\r
+ * Set the state of output pin 23 to match input pin 16:\r
+ * \code\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_example_workflow Workflow\r
+ * -# We check the value of the pin:\r
+ * \code\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * \endcode\r
+ * -# Then we set the new output value based on the read pin value:\r
+ * \code\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * \endcode\r
+ */\r
+\r
+/**\r
+ * \page sam_pio_quickstart_use_case_2 Advanced use case - Interrupt driven edge detection\r
+ *\r
+ * \section sam_pio_quickstart_use_case_2 Advanced Use Case 1\r
+ * This section will present a more advanced use case for the PIO driver. This use case\r
+ * will configure pin 23 on port A as output and pin 16 as an input with pullup,\r
+ * and then toggle the output pin's value to match that of the input pin using the interrupt\r
+ * controller within the device.\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_prereq Prerequisites\r
+ * - \ref group_pmc "Power Management Controller driver"\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * pmc_enable_periph_clk(ID_PIOA);\r
+ *\r
+ * pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE);\r
+ * pio_set_input(PIOA, PIO_PA16, PIO_PULLUP);\r
+ *\r
+ * pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler);\r
+ * pio_enable_interrupt(PIOA, PIO_PA16);\r
+ *\r
+ * NVIC_EnableIRQ(PIOA_IRQn);\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_setup_steps_workflow Workflow\r
+ * -# Enable the module clock to the PIOA peripheral:\r
+ * \code pmc_enable_periph_clk(ID_PIOA); \endcode\r
+ * -# Set pin 23 direction on PIOA as output, default low level:\r
+ * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode\r
+ * -# Set pin 16 direction on PIOA as input, with pullup:\r
+ * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode\r
+ * -# Configure the input pin 16 interrupt mode and handler:\r
+ * \code pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); \endcode\r
+ * -# Enable the interrupt for the configured input pin:\r
+ * \code pio_enable_interrupt(PIOA, PIO_PA16); \endcode\r
+ * -# Enable interrupt handling from the PIOA module:\r
+ * \code NVIC_EnableIRQ(PIOA_IRQn); \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_example_code Example code\r
+ * Add the following function to your application:\r
+ * \code\r
+ * void pin_edge_handler(void)\r
+ * {\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_example_workflow Workflow\r
+ * -# We check the value of the pin:\r
+ * \code\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * \endcode\r
+ * -# Then we set the new output value based on the read pin value:\r
+ * \code\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * \endcode\r
+ */\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* PIO_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) interrupt handler for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "exceptions.h"\r
+#include "pio.h"\r
+#include "pio_handler.h"\r
+\r
+/** \r
+ * Maximum number of interrupt sources that can be defined. This\r
+ * constant can be increased, but the current value is the smallest possible one\r
+ * that will be compatible with all existing projects.\r
+ */\r
+#define MAX_INTERRUPT_SOURCES 7\r
+\r
+/**\r
+ * Describes a PIO interrupt source, including the PIO instance triggering the\r
+ * interrupt and the associated interrupt handler.\r
+ */\r
+struct s_interrupt_source {\r
+ uint32_t id;\r
+ uint32_t mask;\r
+ uint32_t attr;\r
+\r
+ /* Interrupt handler. */\r
+ void (*handler) (const uint32_t, const uint32_t);\r
+};\r
+\r
+\r
+/* List of interrupt sources. */\r
+static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES];\r
+\r
+/* Number of currently defined interrupt sources. */\r
+static uint32_t gs_ul_nb_sources = 0;\r
+\r
+/**\r
+ * \brief Process an interrupt request on the given PIO controller.\r
+ *\r
+ * \param p_pio PIO controller base address.\r
+ * \param ul_id PIO controller ID.\r
+ */\r
+void pio_handler_process(Pio *p_pio, uint32_t ul_id)\r
+{\r
+ uint32_t status;\r
+ uint32_t i;\r
+\r
+ /* Read PIO controller status */\r
+ status = pio_get_interrupt_status(p_pio);\r
+ status &= pio_get_interrupt_mask(p_pio);\r
+\r
+ /* Check pending events */\r
+ if (status != 0) {\r
+ /* Find triggering source */\r
+ i = 0;\r
+ while (status != 0) {\r
+ /* Source is configured on the same controller */\r
+ if (gs_interrupt_sources[i].id == ul_id) {\r
+ /* Source has PIOs whose statuses have changed */\r
+ if ((status & gs_interrupt_sources[i].mask) != 0) {\r
+ gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id,\r
+ gs_interrupt_sources[i].mask);\r
+ status &= ~(gs_interrupt_sources[i].mask);\r
+ }\r
+ }\r
+ i++;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set an interrupt handler for the provided pins.\r
+ * The provided handler will be called with the triggering pin as its parameter \r
+ * as soon as an interrupt is detected. \r
+ *\r
+ * \param p_pio PIO controller base address.\r
+ * \param ul_id PIO ID.\r
+ * \param ul_mask Pins (bit mask) to configure.\r
+ * \param ul_attr Pins attribute to configure.\r
+ * \param p_handler Interrupt handler function pointer.\r
+ *\r
+ * \return 0 if successful, 1 if the maximum number of sources has been defined.\r
+ */\r
+uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,\r
+ uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t))\r
+{\r
+ struct s_interrupt_source *pSource;\r
+\r
+ if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES)\r
+ return 1;\r
+\r
+ /* Define new source */\r
+ pSource = &(gs_interrupt_sources[gs_ul_nb_sources]);\r
+ pSource->id = ul_id;\r
+ pSource->mask = ul_mask;\r
+ pSource->attr = ul_attr;\r
+ pSource->handler = p_handler;\r
+ gs_ul_nb_sources++;\r
+\r
+ /* Configure interrupt mode */\r
+ pio_configure_interrupt(p_pio, ul_mask, ul_attr);\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller A interrupt handler.\r
+ * Redefined PIOA interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOA_Handler(void)\r
+{\r
+ pio_handler_process(PIOA, ID_PIOA);\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller B interrupt handler\r
+ * Redefined PIOB interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOB_Handler(void)\r
+{\r
+ pio_handler_process(PIOB, ID_PIOB);\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller C interrupt handler.\r
+ * Redefined PIOC interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOC_Handler(void)\r
+{\r
+ pio_handler_process(PIOC, ID_PIOC);\r
+}\r
+\r
+#if SAM3XA\r
+/**\r
+ * \brief Parallel IO Controller D interrupt handler.\r
+ * Redefined PIOD interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOD_Handler(void)\r
+{\r
+ pio_handler_process(PIOD, ID_PIOD);\r
+}\r
+\r
+#ifdef _SAM3XA_PIOE_INSTANCE_\r
+/**\r
+ * \brief Parallel IO Controller E interrupt handler.\r
+ * Redefined PIOE interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOE_Handler(void)\r
+{\r
+ pio_handler_process(PIOE, ID_PIOE);\r
+}\r
+#endif\r
+\r
+#ifdef _SAM3XA_PIOF_INSTANCE_\r
+/**\r
+ * \brief Parallel IO Controller F interrupt handler.\r
+ * Redefined PIOF interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOF_Handler(void)\r
+{\r
+ pio_handler_process(PIOF, ID_PIOF);\r
+}\r
+#endif\r
+#endif\r
+\r
+/**\r
+ * \brief Initialize PIO interrupt management logic.\r
+ *\r
+ * \note The desired priority of PIO must be provided.\r
+ * Calling this function multiple times result in the reset of currently\r
+ * configured interrupt on the provided PIO.\r
+ *\r
+ * \param p_pio PIO controller base address.\r
+ * \param ul_irqn NVIC line number.\r
+ * \param ul_priority PIO controller interrupts priority.\r
+ */\r
+void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority)\r
+{\r
+ /* Configure PIO interrupt sources */\r
+ pio_get_interrupt_status(p_pio);\r
+ pio_disable_interrupt(p_pio, 0xFFFFFFFF);\r
+ NVIC_DisableIRQ(ul_irqn);\r
+ NVIC_ClearPendingIRQ(ul_irqn);\r
+ NVIC_SetPriority(ul_irqn, ul_priority);\r
+ NVIC_EnableIRQ(ul_irqn);\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) interrupt handler for SAM.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef PIO_HANDLER_H_INCLUDED\r
+#define PIO_HANDLER_H_INCLUDED\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+void pio_handler_process(Pio *p_pio, uint32_t ul_id);\r
+void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority);\r
+uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,\r
+ uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t));\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* PIO_HANDLER_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Power Management Controller (PMC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "pmc.h"\r
+\r
+#if (SAM3N)\r
+# define MAX_PERIPH_ID 31\r
+#elif (SAM3XA)\r
+# define MAX_PERIPH_ID 44\r
+#elif (SAM3U)\r
+# define MAX_PERIPH_ID 29\r
+#elif (SAM3S || SAM4S)\r
+# define MAX_PERIPH_ID 34\r
+#endif\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_pmc_group Power Management Controller (PMC)\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * The Power Management Controller (PMC) optimizes power consumption by controlling\r
+ * all system and user peripheral clocks. The PMC enables/disables the clock inputs\r
+ * to many of the peripherals and the Cortex-M Processor.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Set the prescaler of the MCK.\r
+ *\r
+ * \param ul_pres Prescaler value.\r
+ */\r
+void pmc_mck_set_prescaler(uint32_t ul_pres)\r
+{\r
+ PMC->PMC_MCKR =\r
+ (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+/**\r
+ * \brief Set the source of the MCK.\r
+ *\r
+ * \param ul_source Source selection value.\r
+ */\r
+void pmc_mck_set_source(uint32_t ul_source)\r
+{\r
+ PMC->PMC_MCKR =\r
+ (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to slow clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_SLOW_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to main clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_MAIN_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_PLLA_CLK;\r
+\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch master clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_PLLB_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Switch master clock source selection to UPLL clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_UPLL_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Switch slow clock source selection to external 32k (Xtal or Bypass).\r
+ *\r
+ * \note This function disables the PLLs.\r
+ *\r
+ * \note Switching SCLK back to 32krc is only possible by shutting down the VDDIO\r
+ * power supply.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ */\r
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)\r
+{\r
+ /* Set Bypass mode if required */\r
+ if (ul_bypass == 1) {\r
+ SUPC->SUPC_MR |= SUPC_MR_KEY(SUPC_KEY_VALUE) |\r
+ SUPC_MR_OSCBYPASS;\r
+ }\r
+\r
+ SUPC->SUPC_CR |= SUPC_CR_KEY(SUPC_KEY_VALUE) | SUPC_CR_XTALSEL;\r
+}\r
+\r
+/**\r
+ * \brief Check if the external 32k Xtal is ready.\r
+ *\r
+ * \retval 1 External 32k Xtal is ready.\r
+ * \retval 0 External 32k Xtal is not ready.\r
+ */\r
+uint32_t pmc_osc_is_ready_32kxtal(void)\r
+{\r
+ return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)\r
+ && (PMC->PMC_SR & PMC_SR_OSCSELS));\r
+}\r
+\r
+/**\r
+ * \brief Switch main clock source selection to internal fast RC.\r
+ *\r
+ * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ * \retval 2 Invalid frequency.\r
+ */\r
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)\r
+{\r
+ uint32_t ul_needXTEN = 0;\r
+\r
+ /* Enable Fast RC oscillator but DO NOT switch to RC now */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN |\r
+ ul_moscrcf;\r
+ } else {\r
+ ul_needXTEN = 1;\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN |\r
+ CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(PMC_XTAL_STARTUP_TIME) |\r
+ ul_moscrcf;\r
+ }\r
+\r
+ /* Wait the Fast RC to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+\r
+ /* Switch to Fast RC */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | PMC_CKGR_MOR_KEY_VALUE;\r
+\r
+ /* Disable xtal oscillator */\r
+ if (ul_needXTEN) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable fast RC oscillator.\r
+ *\r
+ * \param ul_rc Fast RC oscillator(4/8/12Mhz).\r
+ */\r
+void pmc_osc_enable_fastrc(uint32_t ul_rc)\r
+{\r
+ /* Enable Fast RC oscillator but DO NOT switch to RC now. Keep MOSCSEL to 1 */\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL |\r
+ CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCRCEN | ul_rc;\r
+ /* Wait the Fast RC to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+}\r
+\r
+/**\r
+ * \brief Disable the internal fast RC.\r
+ */\r
+void pmc_osc_disable_fastrc(void)\r
+{\r
+ /* Disable Fast RC oscillator */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & ~CKGR_MOR_MOSCRCF_Msk)\r
+ | PMC_CKGR_MOR_KEY_VALUE;\r
+}\r
+\r
+/**\r
+ * \brief Switch main clock source selection to external Xtal/Bypass.\r
+ * The function may switch MCK to SCLK if MCK source is MAINCK to avoid any\r
+ * system crash.\r
+ *\r
+ * \note If used in Xtal mode, the Xtal is automatically enabled.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass)\r
+{\r
+ /* Enable Main Xtal oscillator */\r
+ if (ul_bypass) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTBY |\r
+ CKGR_MOR_MOSCSEL;\r
+ } else {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTEN |\r
+ CKGR_MOR_MOSCXTST(PMC_XTAL_STARTUP_TIME);\r
+ /* Wait the Xtal to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));\r
+\r
+ PMC->CKGR_MOR |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable the external Xtal.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ */\r
+void pmc_osc_disable_xtal(uint32_t ul_bypass)\r
+{\r
+ /* Disable xtal oscillator */\r
+ if (ul_bypass) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ } else {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one\r
+ * of Xtal, bypass or internal RC.\r
+ *\r
+ * \retval 1 Xtal is ready.\r
+ * \retval 0 Xtal is not ready.\r
+ */\r
+uint32_t pmc_osc_is_ready_mainck(void)\r
+{\r
+ return PMC->PMC_SR & PMC_SR_MOSCSELS;\r
+}\r
+\r
+/**\r
+ * \brief Enable PLLA clock.\r
+ *\r
+ * \param mula PLLA multiplier.\r
+ * \param pllacount PLLA counter.\r
+ * \param diva Divider.\r
+ */\r
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)\r
+{\r
+ /* first disable the PLL to unlock the lock!*/\r
+ pmc_disable_pllack();\r
+\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |\r
+ CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);\r
+ while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);\r
+}\r
+\r
+/**\r
+ * \brief Disable PLLA clock.\r
+ */\r
+void pmc_disable_pllack(void)\r
+{\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);\r
+}\r
+\r
+/**\r
+ * \brief Is PLLA locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_pllack(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKA);\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Enable PLLB clock.\r
+ *\r
+ * \param mulb PLLB multiplier.\r
+ * \param pllbcount PLLB counter.\r
+ * \param divb Divider.\r
+ */\r
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)\r
+{\r
+ /* first disable the PLL to unlock the lock!*/\r
+ pmc_disable_pllbck();\r
+\r
+ PMC->CKGR_PLLBR =\r
+ CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)\r
+ | CKGR_PLLBR_MULB(mulb);\r
+ while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);\r
+}\r
+\r
+/**\r
+ * \brief Disable PLLB clock.\r
+ */\r
+void pmc_disable_pllbck(void)\r
+{\r
+ PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);\r
+}\r
+\r
+/**\r
+ * \brief Is PLLB locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_pllbck(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKB);\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Enable UPLL clock.\r
+ */\r
+void pmc_enable_upll_clock(void)\r
+{\r
+ PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;\r
+\r
+ /* Wait UTMI PLL Lock Status */\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));\r
+}\r
+\r
+/**\r
+ * \brief Disable UPLL clock.\r
+ */\r
+void pmc_disable_upll_clock(void)\r
+{\r
+ PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;\r
+}\r
+\r
+/**\r
+ * \brief Is UPLL locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_upll(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKU);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable the specified peripheral clock.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Invalid parameter.\r
+ */\r
+uint32_t pmc_enable_periph_clk(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 1;\r
+ }\r
+\r
+ if (ul_id < 32) {\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {\r
+ PMC->PMC_PCER0 = 1 << ul_id;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {\r
+ PMC->PMC_PCER1 = 1 << ul_id;\r
+ }\r
+#endif\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Disable the specified peripheral clock.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Invalid parameter.\r
+ */\r
+uint32_t pmc_disable_periph_clk(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 1;\r
+ }\r
+\r
+ if (ul_id < 32) {\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {\r
+ PMC->PMC_PCDR0 = 1 << ul_id;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {\r
+ PMC->PMC_PCDR1 = 1 << ul_id;\r
+ }\r
+#endif\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable all peripheral clocks.\r
+ */\r
+void pmc_enable_all_periph_clk(void)\r
+{\r
+ PMC->PMC_PCER0 = PMC_MASK_STATUS0;\r
+ while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ PMC->PMC_PCER1 = PMC_MASK_STATUS1;\r
+ while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Disable all peripheral clocks.\r
+ */\r
+void pmc_disable_all_periph_clk(void)\r
+{\r
+ PMC->PMC_PCDR0 = PMC_MASK_STATUS0;\r
+ while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ PMC->PMC_PCDR1 = PMC_MASK_STATUS1;\r
+ while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Check if the specified peripheral clock is enabled.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Peripheral clock is disabled or unknown.\r
+ * \retval 1 Peripheral clock is enabled.\r
+ */\r
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 0;\r
+ }\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ if (ul_id < 32) {\r
+#endif\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id))) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id))) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Set the prescaler for the specified programmable clock.\r
+ *\r
+ * \param ul_id Peripheral ID.\r
+ * \param ul_pres Prescaler value.\r
+ */\r
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ PMC->PMC_PCK[ul_id] =\r
+ (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;\r
+ while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))\r
+ && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));\r
+}\r
+\r
+/**\r
+ * \brief Set the source oscillator for the specified programmable clock.\r
+ *\r
+ * \param ul_id Peripheral ID.\r
+ * \param ul_source Source selection value.\r
+ */\r
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)\r
+{\r
+ PMC->PMC_PCK[ul_id] =\r
+ (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;\r
+ while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))\r
+ && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to slow clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to main clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch programmable clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Switch programmable clock source selection to UPLL clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable the specified programmable clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ */\r
+void pmc_enable_pck(uint32_t ul_id)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;\r
+}\r
+\r
+/**\r
+ * \brief Disable the specified programmable clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ */\r
+void pmc_disable_pck(uint32_t ul_id)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;\r
+}\r
+\r
+/**\r
+ * \brief Enable all programmable clocks.\r
+ */\r
+void pmc_enable_all_pck(void)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;\r
+}\r
+\r
+/**\r
+ * \brief Disable all programmable clocks.\r
+ */\r
+void pmc_disable_all_pck(void)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;\r
+}\r
+\r
+/**\r
+ * \brief Check if the specified programmable clock is enabled.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ *\r
+ * \retval 0 Programmable clock is disabled or unknown.\r
+ * \retval 1 Programmable clock is enabled.\r
+ */\r
+uint32_t pmc_is_pck_enabled(uint32_t ul_id)\r
+{\r
+ if (ul_id > 2) {\r
+ return 0;\r
+ }\r
+\r
+ return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));\r
+}\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);\r
+}\r
+#endif\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to UPLL clock.\r
+ *\r
+ * \param dw_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);\r
+}\r
+#endif\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+/**\r
+ * \brief Enable UDP (USB) clock.\r
+ */\r
+void pmc_enable_udpck(void)\r
+{\r
+# if (SAM3S || SAM4S)\r
+ PMC->PMC_SCER = PMC_SCER_UDP;\r
+# else\r
+ PMC->PMC_SCER = PMC_SCER_UOTGCLK;\r
+# endif\r
+}\r
+\r
+/**\r
+ * \brief Disable UDP (USB) clock.\r
+ */\r
+void pmc_disable_udpck(void)\r
+{\r
+# if (SAM3S || SAM4S)\r
+ PMC->PMC_SCDR = PMC_SCDR_UDP;\r
+# else\r
+ PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;\r
+# endif\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable PMC interrupts.\r
+ *\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void pmc_enable_interrupt(uint32_t ul_sources)\r
+{\r
+ PMC->PMC_IER = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Disable PMC interrupts.\r
+ *\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void pmc_disable_interrupt(uint32_t ul_sources)\r
+{\r
+ PMC->PMC_IDR = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Get PMC interrupt mask.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pmc_get_interrupt_mask(void)\r
+{\r
+ return PMC->PMC_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Get current status.\r
+ *\r
+ * \return The current PMC status.\r
+ */\r
+uint32_t pmc_get_status(void)\r
+{\r
+ return PMC->PMC_SR;\r
+}\r
+\r
+/**\r
+ * \brief Set the wake-up inputs for fast startup mode registers (event generation).\r
+ *\r
+ * \param ul_inputs Wake up inputs to enable.\r
+ */\r
+void pmc_set_fast_startup_input(uint32_t ul_inputs)\r
+{\r
+ ul_inputs &= PMC_FAST_STARTUP_Msk;\r
+ PMC->PMC_FSMR |= ul_inputs;\r
+}\r
+\r
+/**\r
+ * \brief Clear the wake-up inputs for fast startup mode registers (remove event generation).\r
+ *\r
+ * \param ul_inputs Wake up inputs to disable.\r
+ */\r
+void pmc_clr_fast_startup_input(uint32_t ul_inputs)\r
+{\r
+ ul_inputs &= PMC_FAST_STARTUP_Msk;\r
+ PMC->PMC_FSMR &= ~ul_inputs;\r
+}\r
+\r
+/**\r
+ * \brief Enable Sleep Mode.\r
+ * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0)\r
+ *\r
+ * \param uc_type 0 for wait for interrupt, 1 for wait for event.\r
+ */\r
+void pmc_enable_sleepmode(uint8_t uc_type)\r
+{\r
+ PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode\r
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep\r
+\r
+ if (uc_type == 0) {\r
+ __WFI();\r
+ } else {\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable Wait Mode.\r
+ * Enter condition: WFE + (SLEEPDEEP bit = 0) + (LPM bit = 1)\r
+ */\r
+void pmc_enable_waitmode(void)\r
+{\r
+ uint32_t i;\r
+\r
+ PMC->PMC_FSMR |= PMC_FSMR_LPM; // Enter Wait mode\r
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep\r
+ __WFE();\r
+\r
+ /* Waiting for MOSCRCEN bit cleared is strongly recommended\r
+ * to ensure that the core will not execute undesired instructions\r
+ */\r
+ for (i = 0; i < 500; i++) {\r
+ __NOP();\r
+ }\r
+ while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));\r
+}\r
+\r
+/**\r
+ * \brief Enable Backup Mode.\r
+ * Enter condition: WFE + (SLEEPDEEP bit = 1)\r
+ */\r
+void pmc_enable_backupmode(void)\r
+{\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ __WFE();\r
+}\r
+\r
+/**\r
+ * \brief Enable Clock Failure Detector.\r
+ */\r
+void pmc_enable_clock_failure_detector(void)\r
+{\r
+ uint32_t ul_reg = PMC->CKGR_MOR;\r
+\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_CFDEN | ul_reg;\r
+}\r
+\r
+/**\r
+ * \brief Disable Clock Failure Detector.\r
+ */\r
+void pmc_disable_clock_failure_detector(void)\r
+{\r
+ uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);\r
+\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | ul_reg;\r
+}\r
+\r
+/**\r
+ * \brief Enable or disable write protect of PMC registers.\r
+ *\r
+ * \param ul_enable 1 to enable, 0 to disable.\r
+ */\r
+void pmc_set_writeprotect(uint32_t ul_enable)\r
+{\r
+ if (ul_enable) {\r
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE | PMC_WPMR_WPEN;\r
+ } else {\r
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Return write protect status.\r
+ *\r
+ * \retval 0 Protection disabled.\r
+ * \retval 1 Protection enabled.\r
+ */\r
+uint32_t pmc_get_writeprotect_status(void)\r
+{\r
+ return PMC->PMC_WPMR & PMC_WPMR_WPEN;\r
+}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Power Management Controller (PMC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef PMC_H_INCLUDED\r
+#define PMC_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/** Bit mask for peripheral clocks (PCER0) */\r
+#define PMC_MASK_STATUS0 (0xFFFFFFFC)\r
+\r
+/** Bit mask for peripheral clocks (PCER1) */\r
+#define PMC_MASK_STATUS1 (0xFFFFFFFF)\r
+\r
+/** Loop counter timeout value */\r
+#define PMC_TIMEOUT (2048)\r
+\r
+/** Key to unlock CKGR_MOR register */\r
+#define PMC_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37)\r
+\r
+/** Key used to write SUPC registers */\r
+#define SUPC_KEY_VALUE ((uint32_t) 0xA5)\r
+\r
+/** PMC xtal startup time */\r
+#define PMC_XTAL_STARTUP_TIME (0x3F)\r
+\r
+/** Mask to access fast startup input */\r
+#define PMC_FAST_STARTUP_Msk (0x7FFFFu)\r
+\r
+/** PMC_WPMR Write Protect KEY, unlock it */\r
+#define PMC_WPMR_WPKEY_VALUE PMC_WPMR_WPKEY((uint32_t) 0x504D43)\r
+\r
+/** Using external oscillator */\r
+#define PMC_OSC_XTAL 0\r
+\r
+/** Oscillator in bypass mode */\r
+#define PMC_OSC_BYPASS 1\r
+\r
+#define PMC_PCK_0 0 /* PCK0 ID */\r
+#define PMC_PCK_1 1 /* PCK1 ID */\r
+#define PMC_PCK_2 2 /* PCK2 ID */\r
+\r
+/**\r
+ * \name Master clock (MCK) Source and Prescaler configuration\r
+ *\r
+ * The following functions may be used to select the clock source and\r
+ * prescaler for the master clock.\r
+ */\r
+//@{\r
+\r
+void pmc_mck_set_prescaler(uint32_t ul_pres);\r
+void pmc_mck_set_source(uint32_t ul_source);\r
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres);\r
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres);\r
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres);\r
+#if (SAM3S || SAM4S)\r
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres);\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Slow clock (SLCK) oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass);\r
+uint32_t pmc_osc_is_ready_32kxtal(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Main Clock (MAINCK) oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf);\r
+void pmc_osc_enable_fastrc(uint32_t ul_rc);\r
+void pmc_osc_disable_fastrc(void);\r
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass);\r
+void pmc_osc_disable_xtal(uint32_t ul_bypass);\r
+uint32_t pmc_osc_is_ready_mainck(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name PLL oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva);\r
+void pmc_disable_pllack(void);\r
+uint32_t pmc_is_locked_pllack(void);\r
+\r
+#if (SAM3S || SAM4S)\r
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb);\r
+void pmc_disable_pllbck(void);\r
+uint32_t pmc_is_locked_pllbck(void);\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+void pmc_enable_upll_clock(void);\r
+void pmc_disable_upll_clock(void);\r
+uint32_t pmc_is_locked_upll(void);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Peripherals clock configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+uint32_t pmc_enable_periph_clk(uint32_t ul_id);\r
+uint32_t pmc_disable_periph_clk(uint32_t ul_id);\r
+void pmc_enable_all_periph_clk(void);\r
+void pmc_disable_all_periph_clk(void);\r
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Programmable clock Source and Prescaler configuration\r
+ *\r
+ * The following functions may be used to select the clock source and\r
+ * prescaler for the specified programmable clock.\r
+ */\r
+//@{\r
+\r
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres);\r
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source);\r
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres);\r
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres);\r
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres);\r
+#if (SAM3S || SAM4S)\r
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres);\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres);\r
+#endif\r
+void pmc_enable_pck(uint32_t ul_id);\r
+void pmc_disable_pck(uint32_t ul_id);\r
+void pmc_enable_all_pck(void);\r
+void pmc_disable_all_pck(void);\r
+uint32_t pmc_is_pck_enabled(uint32_t ul_id);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name USB clock configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3S || SAM4S)\r
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3XA)\r
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+void pmc_enable_udpck(void);\r
+void pmc_disable_udpck(void);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Interrupt and status management\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_interrupt(uint32_t ul_sources);\r
+void pmc_disable_interrupt(uint32_t ul_sources);\r
+uint32_t pmc_get_interrupt_mask(void);\r
+uint32_t pmc_get_status(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Power management\r
+ *\r
+ * The following functions are used to configure sleep mode and additional \r
+ * wake up inputs.\r
+ */\r
+//@{\r
+\r
+void pmc_set_fast_startup_input(uint32_t ul_inputs);\r
+void pmc_clr_fast_startup_input(uint32_t ul_inputs);\r
+void pmc_enable_sleepmode(uint8_t uc_type);\r
+void pmc_enable_waitmode(void);\r
+void pmc_enable_backupmode(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Failure detector\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_clock_failure_detector(void);\r
+void pmc_disable_clock_failure_detector(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Write protection\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_set_writeprotect(uint32_t ul_enable);\r
+uint32_t pmc_get_writeprotect_status(void);\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+//! @}\r
+\r
+/**\r
+ * \page sam_pmc_quickstart Quick start guide for the SAM PMC module\r
+ *\r
+ * This is the quick start guide for the \ref pmc_group "PMC module", with\r
+ * step-by-step instructions on how to configure and use the driver in a\r
+ * selection of use cases.\r
+ *\r
+ * The use cases contain several code fragments. The code fragments in the\r
+ * steps for setup can be copied into a custom initialization function, while\r
+ * the steps for usage can be copied into, e.g., the main application function.\r
+ *\r
+ * \section pmc_use_cases PMC use cases\r
+ * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources\r
+ * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks\r
+ *\r
+ * \section pmc_basic_use_case Basic use case - Switch Main Clock sources\r
+ * In this use case, the PMC module is configured for a variety of system clock\r
+ * sources and speeds. A LED is used to visually indicate the current clock\r
+ * speed as the source is switched.\r
+ *\r
+ * \section pmc_basic_use_case_setup Setup\r
+ *\r
+ * \subsection pmc_basic_use_case_setup_prereq Prerequisites\r
+ * -# \ref gpio_group "General Purpose I/O Management (gpio)"\r
+ *\r
+ * \subsection pmc_basic_use_case_setup_code Code\r
+ * The following function needs to be added to the user application, to flash a\r
+ * board LED a variable number of times at a rate given in CPU ticks.\r
+ * \r
+ * \code\r
+ * #define FLASH_TICK_COUNT 0x00012345\r
+ *\r
+ * void flash_led(uint32_t tick_count, uint8_t flash_count)\r
+ * {\r
+ * SysTick->CTRL = SysTick_CTRL_ENABLE_Msk;\r
+ * SysTick->LOAD = tick_count;\r
+ * \r
+ * while (flash_count--)\r
+ * {\r
+ * gpio_toggle_pin(LED0_GPIO);\r
+ * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));\r
+ * gpio_toggle_pin(LED0_GPIO);\r
+ * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));\r
+ * }\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \section pmc_basic_use_case_usage Use case\r
+ *\r
+ * \subsection pmc_basic_use_case_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * for (;;)\r
+ * {\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_xtal(0);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_basic_use_case_usage_flow Workflow\r
+ * -# Wrap the code in an infinite loop:\r
+ * \code\r
+ * for (;;)\r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the external crystal oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_xtal(0);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ */\r
+\r
+/**\r
+ * \page pmc_use_case_2 Use case #2 - Configure Programmable Clocks\r
+ * In this use case, the PMC module is configured to start the Slow Clock from\r
+ * an attached 32KHz crystal, and start one of the Programmable Clock modules\r
+ * sourced from the Slow Clock divided down with a prescale factor of 64.\r
+ *\r
+ * \section pmc_use_case_2_setup Setup\r
+ *\r
+ * \subsection pmc_use_case_2_setup_prereq Prerequisites\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ *\r
+ * \subsection pmc_use_case_2_setup_code Code\r
+ * The following code must be added to the user application:\r
+ * \code\r
+ * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_use_case_2_setup_code_workflow Workflow\r
+ * -# Configure the PCK1 pin to output on a specific port pin (in this case,\r
+ * PIOA pin 17) of the microcontroller.\r
+ * \code\r
+ * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);\r
+ * \endcode\r
+ * \note The peripheral selection and pin will vary according to your selected\r
+ * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O\r
+ * Lines" of your device's datasheet.\r
+ *\r
+ * \section pmc_use_case_2_usage Use case\r
+ * The generated PCK1 clock output can be viewed on an oscilloscope attached to\r
+ * the correct pin of the microcontroller.\r
+ *\r
+ * \subsection pmc_use_case_2_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);\r
+ * pmc_enable_pck(PMC_PCK_1);\r
+ *\r
+ * for (;;)\r
+ * {\r
+ * // Do Nothing\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_use_case_2_usage_flow Workflow\r
+ * -# Switch the Slow Clock source input to an external 32KHz crystal:\r
+ * \code\r
+ * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ * \endcode\r
+ * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock,\r
+ * with a prescaler of 64:\r
+ * \code\r
+ * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);\r
+ * \endcode\r
+ * -# Enable Programmable Clock module PCK1:\r
+ * \code\r
+ * pmc_enable_pck(PMC_PCK_1);\r
+ * \endcode\r
+ * -# Enter an infinite loop:\r
+ * \code\r
+ * for (;;)\r
+ * {\r
+ * // Do Nothing\r
+ * }\r
+ * \endcode\r
+ */\r
+\r
+#endif /* PMC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Sleep mode access\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SLEEP_H\r
+#define SLEEP_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <compiler.h>\r
+\r
+/**\r
+ * \defgroup sleep_group Power Manager (PM)\r
+ *\r
+ * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr service.\r
+ *\r
+ * \note To minimize the code overhead, these functions do not feature\r
+ * interrupt-protected access since they are likely to be called inside\r
+ * interrupt handlers or in applications where such protection is not\r
+ * necessary. If such protection is needed, it must be ensured by the calling\r
+ * code.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if defined(__DOXYGEN__)\r
+/**\r
+ * \brief Sets the MCU in the specified sleep mode\r
+ * \param sleep_mode Sleep mode to set.\r
+ */\r
+#endif\r
+\r
+#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S) // SAM3 and SAM4 series\r
+# include "pmc.h"\r
+\r
+# define SAM_PM_SMODE_ACTIVE 0\r
+# define SAM_PM_SMODE_SLEEP_WFE 1\r
+# define SAM_PM_SMODE_SLEEP_WFI 2\r
+# define SAM_PM_SMODE_WAIT 3\r
+# define SAM_PM_SMODE_BACKUP 4\r
+\r
+/* (SCR) Sleep deep bit */\r
+#define SCR_SLEEPDEEP (0x1 << 2)\r
+\r
+/**\r
+ * Save clock settings and shutdown PLLs\r
+ */\r
+static inline void pmc_save_clock_settings(\r
+ uint32_t *p_osc_setting,\r
+ uint32_t *p_pll0_setting,\r
+ uint32_t *p_pll1_setting,\r
+ uint32_t *p_mck_setting)\r
+{\r
+ if (p_osc_setting) {\r
+ *p_osc_setting = PMC->CKGR_MOR;\r
+ }\r
+ if (p_pll0_setting) {\r
+ *p_pll0_setting = PMC->CKGR_PLLAR;\r
+ }\r
+ if (p_pll1_setting) {\r
+#if SAM3S||SAM4S\r
+ *p_pll1_setting = PMC->CKGR_PLLBR;\r
+#elif SAM3U||SAM3XA\r
+ *p_pll1_setting = PMC->CKGR_UCKR;\r
+#else\r
+ *p_pll1_setting = 0;\r
+#endif\r
+ }\r
+ if (p_mck_setting) {\r
+ *p_mck_setting = PMC->PMC_MCKR;\r
+ }\r
+\r
+ // Switch MCK to Main clock (internal or external 12MHz) for fast wakeup\r
+ // If MAIN_CLK is already the source, just skip\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_MAIN_CLK) {\r
+ return;\r
+ }\r
+ // If we have to enable the MAIN_CLK\r
+ if ((PMC->PMC_SR & PMC_SR_MOSCXTS) == 0) {\r
+ // Intend to use internal RC as source of MAIN_CLK\r
+ pmc_osc_enable_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ }\r
+ pmc_switch_mck_to_mainck(PMC_MCKR_PRES_CLK_1);\r
+}\r
+\r
+/**\r
+ * Restore clock settings\r
+ */\r
+static inline void pmc_restore_clock_setting(\r
+ uint32_t osc_setting,\r
+ uint32_t pll0_setting,\r
+ uint32_t pll1_setting,\r
+ uint32_t mck_setting)\r
+{\r
+ uint32_t mckr;\r
+ if ((pll0_setting & CKGR_PLLAR_MULA_Msk) &&\r
+ pll0_setting != PMC->CKGR_PLLAR) {\r
+ PMC->CKGR_PLLAR = 0;\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA));\r
+ }\r
+#if SAM3S||SAM4S\r
+ if ((pll1_setting & CKGR_PLLBR_MULB_Msk) &&\r
+ pll1_setting != PMC->CKGR_PLLBR) {\r
+ PMC->CKGR_PLLBR = 0;\r
+ PMC->CKGR_PLLBR = pll1_setting ;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKB));\r
+ }\r
+#elif SAM3U||SAM3XA\r
+ if ((pll1_setting & CKGR_UCKR_UPLLEN) &&\r
+ pll1_setting != PMC->CKGR_UCKR) {\r
+ PMC->CKGR_UCKR = 0;\r
+ PMC->CKGR_UCKR = pll1_setting;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));\r
+ }\r
+#else\r
+ UNUSED(pll1_setting);\r
+#endif\r
+ /* Switch to faster clock */\r
+ mckr = PMC->PMC_MCKR;\r
+ // Set PRES\r
+ PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk)\r
+ | (mck_setting & PMC_MCKR_PRES_Msk);\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+ // Set CSS and others\r
+ PMC->PMC_MCKR = mck_setting;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+ /* Shutdown fastrc */\r
+ if (0 == (osc_setting & CKGR_MOR_MOSCRCEN)) {\r
+ pmc_osc_disable_fastrc();\r
+ }\r
+}\r
+\r
+static inline void pmc_sleep(int sleep_mode)\r
+{\r
+ switch (sleep_mode) {\r
+ case SAM_PM_SMODE_SLEEP_WFI:\r
+ case SAM_PM_SMODE_SLEEP_WFE:\r
+ PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM;\r
+ SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;\r
+ cpu_irq_enable();\r
+ if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI)\r
+ __WFI();\r
+ else\r
+ __WFE();\r
+ break;\r
+\r
+ case SAM_PM_SMODE_WAIT: {\r
+ uint32_t mor, pllr0, pllr1, mckr;\r
+ pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr);\r
+\r
+ PMC->PMC_FSMR |= PMC_FSMR_LPM;\r
+ SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP ;\r
+ cpu_irq_enable();\r
+ __WFE();\r
+\r
+ cpu_irq_disable();\r
+ pmc_restore_clock_setting(mor, pllr0, pllr1, mckr);\r
+ cpu_irq_enable();\r
+ break;\r
+ }\r
+\r
+ case SAM_PM_SMODE_BACKUP:\r
+ SCB->SCR |= SCR_SLEEPDEEP ;\r
+ cpu_irq_enable();\r
+ __WFE() ;\r
+ break;\r
+ }\r
+}\r
+\r
+#endif\r
+\r
+//! @}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* SLEEP_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+ \r
+#include "usart.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous Receiver Transmitter (USART)\r
+ *\r
+ * The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex \r
+ * universal synchronous asynchronous serial link. Data frame format is widely programmable\r
+ * (data length, parity, number of stop bits) to support a maximum of standards. The receiver\r
+ * implements parity error, framing error and overrun error detection. The receiver time-out enables\r
+ * handling variable-length frames and the transmitter timeguard facilitates communications with\r
+ * slow remote devices. Multidrop communications are also supported through address bit handling\r
+ * in reception and transmission.\r
+ * The driver supports the following modes: RS232, RS485, SPI, IrDA, ISO7816, MODEM,\r
+ * Hardware handshaking and LIN.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/* The write protect key value. */\r
+#define US_WPKEY_VALUE 0x555341\r
+\r
+/* The CD value scope programmed in MR register. */\r
+#define MIN_CD_VALUE 0x01\r
+#define MIN_CD_VALUE_SPI 0x04\r
+#define MAX_CD_VALUE US_BRGR_CD_Msk\r
+\r
+/* Define the default time-out value for USART. */\r
+#define USART_DEFAULT_TIMEOUT 1000\r
+\r
+/* The receiver sampling divide of baudrate clock. */\r
+#define HIGH_FRQ_SAMPLE_DIV 16\r
+#define LOW_FRQ_SAMPLE_DIV 8\r
+\r
+/* Max transmitter timeguard. */\r
+#define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk\r
+\r
+/* The non-existent parity error number. */\r
+#define USART_PARITY_ERROR 5\r
+\r
+/* ISO7816 protocol type. */\r
+#define ISO7816_T_0 0\r
+#define ISO7816_T_1 1\r
+\r
+/**\r
+ * \brief Calculate a clock divider(CD) and a fractional part (FP) for the \r
+ * USART asynchronous modes to generate a baudrate as close as possible to \r
+ * the baudrate set point.\r
+ *\r
+ * \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8))\r
+ * (Over being 16 or 8). The maximal oversampling is selected if it allows to \r
+ * generate a baudrate close to the set point.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_async_baudrate(Usart *p_usart,\r
+ uint32_t baudrate, uint32_t ul_mck)\r
+{\r
+ uint32_t over;\r
+ uint32_t cd_fp;\r
+ uint32_t cd;\r
+ uint32_t fp;\r
+\r
+ /* Calculate the receiver sampling divide of baudrate clock. */\r
+ if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) {\r
+ over = HIGH_FRQ_SAMPLE_DIV;\r
+ } else {\r
+ over = LOW_FRQ_SAMPLE_DIV;\r
+ }\r
+\r
+ /* Calculate the clock divider according to the fraction calculated formula. */\r
+ cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate);\r
+ cd = cd_fp >> 3;\r
+ fp = cd_fp & 0x07;\r
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the OVER bit in MR register. */\r
+ if (over == 8) {\r
+ p_usart->US_MR |= US_MR_OVER;\r
+ }\r
+\r
+ /* Configure the baudrate generate register. */\r
+ p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Calculate a clock divider for the USART synchronous master modes\r
+ * to generate a baudrate as close as possible to the baudrate set point.\r
+ *\r
+ * \note Synchronous baudrate calculation: baudrate = ul_mck / cd\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_sync_master_baudrate(Usart *p_usart,\r
+ uint32_t baudrate, uint32_t ul_mck)\r
+{\r
+ uint32_t cd;\r
+\r
+ /* Calculate the clock divider according to the formula in synchronous mode. */\r
+ cd = (ul_mck + baudrate / 2) / baudrate;\r
+\r
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the baudrate generate register. */\r
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;\r
+\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |\r
+ US_MR_USCLKS_MCK | US_MR_SYNC;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Select the SCK pin as the source of baud rate for the USART\r
+ * synchronous slave modes.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+static void usart_set_sync_slave_baudrate(Usart *p_usart)\r
+{\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |\r
+ US_MR_USCLKS_SCK | US_MR_SYNC;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to \r
+ * generate an ISO7816 clock as close as possible to the clock set point.\r
+ *\r
+ * \note ISO7816 clock calculation: Clock = ul_mck / cd\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param clock ISO7816 clock set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 ISO7816 clock is successfully initialized.\r
+ * \retval 1 ISO7816 clock set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_iso7816_clock(Usart *p_usart,\r
+ uint32_t clock, uint32_t ul_mck)\r
+{\r
+ uint32_t cd;\r
+\r
+ /* Calculate the clock divider according to the formula in ISO7816 mode. */\r
+ cd = (ul_mck + clock / 2) / clock;\r
+\r
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC |\r
+ US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO;\r
+\r
+ /* Configure the baudrate generate register. */\r
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to\r
+ * generate a baud rate as close as possible to the baud rate set point.\r
+ *\r
+ * \note Baud rate calculation:\r
+ * \f$ Baudrate = \frac{SelectedClock}{CD} \f$.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_spi_master_baudrate(Usart *p_usart,\r
+ uint32_t baudrate, uint32_t ul_mck)\r
+{\r
+ uint32_t cd;\r
+\r
+ /* Calculate the clock divider according to the formula in SPI mode. */\r
+ cd = (ul_mck + baudrate / 2) / baudrate;\r
+\r
+ if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Select the SCK pin as the source of baudrate for the USART SPI slave \r
+ * mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+static void usart_set_spi_slave_baudrate(Usart *p_usart)\r
+{\r
+ p_usart->US_MR &= ~US_MR_USCLKS_Msk;\r
+ p_usart->US_MR |= US_MR_USCLKS_SCK;\r
+}\r
+\r
+/**\r
+ * \brief Reset the USART and disable TX and RX.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset(Usart *p_usart)\r
+{\r
+ /* Disable the Write Protect. Some register can't be written if the write protect is enabled. */\r
+ usart_disable_writeprotect(p_usart);\r
+\r
+ /* Reset mode and other registers that could cause unpredictable behavior after reset. */\r
+ p_usart->US_MR = 0;\r
+ p_usart->US_RTOR = 0;\r
+ p_usart->US_TTGR = 0;\r
+\r
+ /* Disable TX and RX, reset status bits and turn off RTS and DTR if exist. */\r
+ usart_reset_tx(p_usart);\r
+ usart_reset_rx(p_usart);\r
+ usart_reset_status(p_usart);\r
+ usart_drive_RTS_pin_high(p_usart);\r
+#if (SAM3S || SAM4S || SAM3U)\r
+ usart_drive_DTR_pin_high(p_usart);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in RS232 mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_rs232(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ ul_reg_val = 0;\r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ usart_set_async_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length, parity type, channel mode and stop bit length. */\r
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |\r
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;\r
+ \r
+ /* Configure the USART mode as normal mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_NORMAL;\r
+ \r
+ p_usart->US_MR |= ul_reg_val;\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in hardware handshaking mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_hw_handshaking(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set hardware handshaking mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_HW_HANDSHAKING;\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S || SAM3U)\r
+/**\r
+ * \brief Configure USART to work in modem mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_modem(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* SAM3S || SAM4S series support MODEM mode only on USART1, and \r
+ SAM3U series support MODEM mode only on USART0. */\r
+#if (SAM3S || SAM4S)\r
+ if (p_usart != USART1) {\r
+ return 1;\r
+ }\r
+#elif (SAM3U)\r
+ if (p_usart != USART0) {\r
+ return 1;\r
+ }\r
+#endif\r
+\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set MODEM mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_MODEM;\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Configure USART to work in SYNC mode and act as a master.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_sync_master(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ ul_reg_val = 0;\r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ usart_set_sync_master_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length, parity type, channel mode and stop bit length. */\r
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |\r
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;\r
+ \r
+ /* Set normal mode and output clock on the SCK pin as synchronous master. */\r
+ ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO;\r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in SYNC mode and act as a slave.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_sync_slave(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt)\r
+{\r
+ static uint32_t ul_reg_val;\r
+ \r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ usart_set_sync_slave_baudrate(p_usart);\r
+ \r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length, parity type, channel mode and stop bit length. */\r
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |\r
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;\r
+\r
+ /* Set normal mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_NORMAL;\r
+ p_usart->US_MR |= ul_reg_val; \r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in RS485 mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_rs485(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set RS485 mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_RS485;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in IrDA mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_irda(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set IrDA filter. */\r
+ p_usart->US_IF = p_usart_opt->irda_filter;\r
+\r
+ /* Set IrDA mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_IRDA;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in ISO7816 mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_iso7816(Usart *p_usart,\r
+ const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+ \r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ \r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) &&\r
+ (p_usart_opt->parity_type != US_MR_PAR_ODD))) {\r
+ return 1;\r
+ }\r
+ \r
+ if (p_usart_opt->protocol_type == ISO7816_T_0) {\r
+ ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT |\r
+ (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos);\r
+\r
+ if (p_usart_opt->bit_order) {\r
+ ul_reg_val |= US_MR_MSBF;\r
+ }\r
+ } else if (p_usart_opt->protocol_type == ISO7816_T_1) {\r
+ /* Only LSBF is used in the T=1 protocol, and max_iterations field is only used in T=0 mode.*/\r
+ if (p_usart_opt->bit_order || p_usart_opt->max_iterations) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */\r
+ ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT;\r
+ } else {\r
+ return 1;\r
+ }\r
+\r
+ /* Set up the baudrate. */\r
+ if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */\r
+ p_usart->US_FIDI = p_usart_opt->fidi_ratio;\r
+\r
+ /* Set ISO7816 parity type in the MODE register. */\r
+ ul_reg_val |= p_usart_opt->parity_type;\r
+ \r
+ if (p_usart_opt->inhibit_nack) {\r
+ ul_reg_val |= US_MR_INACK;\r
+ }\r
+ if (p_usart_opt->dis_suc_nack) {\r
+ ul_reg_val |= US_MR_DSNACK;\r
+ }\r
+ \r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in SPI mode and act as a master.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_spi_master(Usart *p_usart,\r
+ const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+ \r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ (p_usart_opt->spi_mode > SPI_MODE_3) ||\r
+ usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length bit in MR register. */\r
+ ul_reg_val |= p_usart_opt->char_length;\r
+ \r
+ /* Set SPI master mode and channel mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO |\r
+ p_usart_opt->channel_mode;\r
+ \r
+ switch (p_usart_opt->spi_mode) {\r
+ case SPI_MODE_0:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_1:\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_2:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val |= US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_3:\r
+ ul_reg_val |= US_MR_CPOL;\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ \r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in SPI mode and act as a slave.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_spi_slave(Usart *p_usart,\r
+ const usart_spi_opt_t *p_usart_opt)\r
+{\r
+ static uint32_t ul_reg_val;\r
+\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ usart_set_spi_slave_baudrate(p_usart);\r
+ \r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ p_usart_opt->spi_mode > SPI_MODE_3) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length bit in MR register. */\r
+ ul_reg_val |= p_usart_opt->char_length;\r
+ \r
+ /* Set SPI slave mode and channel mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode;\r
+ \r
+ switch (p_usart_opt->spi_mode) {\r
+ case SPI_MODE_0:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_1:\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_2:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val |= US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_3:\r
+ ul_reg_val |= US_MR_CPOL;\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+#if SAM3XA\r
+/**\r
+ * \brief Configure USART to work in LIN mode and act as a LIN master.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_lin_master(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ /* Set up the baudrate. */\r
+ if (usart_set_async_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set LIN master mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_LIN_MASTER; \r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in LIN mode and act as a LIN slave.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_lin_slave(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ /* Set up the baudrate. */\r
+ if (usart_set_async_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set LIN slave mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_LIN_SLAVE;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Abort the current LIN transmission.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_abort_tx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_LINABT;\r
+}\r
+\r
+/**\r
+ * \brief Send a wakeup signal on the LIN bus.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_send_wakeup_signal(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_LINWKUP;\r
+}\r
+\r
+/**\r
+ * \brief Configure the LIN node action, which should be one of PUBLISH,\r
+ * SUBSCRIBE or IGNORE.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE.\r
+ */\r
+void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) |\r
+ (uc_action << US_LINMR_NACT_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Disable the parity check during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_parity(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_PARDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the parity check during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_parity(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_PARDIS;\r
+}\r
+\r
+/**\r
+ * \brief Disable the checksum during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_checksum(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_CHKDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the checksum during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_checksum(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_CHKDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the checksum type during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic checksum.\r
+ */\r
+void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) |\r
+ (uc_type << 4);\r
+}\r
+\r
+/**\r
+ * \brief Configure the data length mode during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_mode Indicate the checksum type: 0 if the data length is defined by the \r
+ * DLC of LIN mode register or 1 if the data length is defined by the bit 5 and 6 of \r
+ * the identifier.\r
+ */\r
+void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) |\r
+ (uc_mode << 5);\r
+}\r
+\r
+/**\r
+ * \brief Disable the frame slot mode during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_frame_slot(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_FSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the frame slot mode during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_frame_slot(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_FSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the wakeup signal type during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_type Indicate the checksum type: 0 if the wakeup signal is a LIN 2.0 \r
+ * wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal.\r
+ */\r
+void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) |\r
+ (uc_type << 7);\r
+}\r
+\r
+/**\r
+ * \brief Configure the response data length if the data length is defined by\r
+ * the DLC field during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_len Indicate the response data length.\r
+ */\r
+void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) |\r
+ (uc_len << US_LINMR_DLC_Pos);\r
+}\r
+\r
+/**\r
+ * \brief The LIN mode register is not written by the PDC.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_pdc_mode(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_PDCM;\r
+}\r
+\r
+/**\r
+ * \brief The LIN mode register (except this flag) is written by the PDC.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_pdc_mode(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_PDCM;\r
+}\r
+\r
+/**\r
+ * \brief Configure the LIN identifier when USART works in LIN master mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_id The identifier to be transmitted.\r
+ */\r
+void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id)\r
+{\r
+ p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) |\r
+ US_LINIR_IDCHR(uc_id);\r
+}\r
+\r
+/**\r
+ * \brief Read the identifier when USART works in LIN mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return The last identifier received in LIN slave mode or the last identifier \r
+ * transmitted in LIN master mode. \r
+ */\r
+uint8_t usart_lin_read_identifier(Usart *p_usart)\r
+{\r
+ return (p_usart->US_LINMR & US_LINIR_IDCHR_Msk);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable USART transmitter.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_enable_tx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_TXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable USART transmitter.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_disable_tx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Immediately stop and disable USART transmitter.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_tx(Usart *p_usart)\r
+{\r
+ /* Reset transmitter */\r
+ p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the transmit timeguard register.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param timeguard The value of transmit timeguard.\r
+ */\r
+void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard)\r
+{\r
+ p_usart->US_TTGR = timeguard;\r
+}\r
+\r
+/**\r
+ * \brief Enable USART receiver.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_enable_rx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable USART receiver.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_disable_rx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Immediately stop and disable USART receiver.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_rx(Usart *p_usart)\r
+{\r
+ /* Reset Receiver */\r
+ p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the receive timeout register.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param timeout The value of receive timeout.\r
+ */\r
+void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout)\r
+{\r
+ p_usart->US_RTOR = timeout;\r
+}\r
+\r
+/**\r
+ * \brief Enable USART interrupts.\r
+ *\r
+ * \param p_usart Pointer to a USART peripheral.\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources)\r
+{\r
+ p_usart->US_IER = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Disable USART interrupts.\r
+ *\r
+ * \param p_usart Pointer to a USART peripheral.\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources)\r
+{\r
+ p_usart->US_IDR = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Read USART interrupt mask.\r
+ *\r
+ * \param p_usart Pointer to a USART peripheral.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t usart_get_interrupt_mask(Usart *p_usart)\r
+{\r
+ return p_usart->US_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Get current status.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return The current USART status.\r
+ */\r
+uint32_t usart_get_status(Usart *p_usart)\r
+{\r
+ return p_usart->US_CSR;\r
+}\r
+\r
+/**\r
+ * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_status(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RSTSTA;\r
+}\r
+\r
+/**\r
+ * \brief Start transmission of a break.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_start_tx_break(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_STTBRK;\r
+}\r
+\r
+/**\r
+ * \brief Stop transmission of a break.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_stop_tx_break(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_STPBRK;\r
+}\r
+\r
+/**\r
+ * \brief Start waiting for a character before clocking the timeout count.\r
+ * Reset the status bit TIMEOUT in US_CSR. \r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_start_rx_timeout(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_STTTO;\r
+}\r
+\r
+/**\r
+ * \brief In Multidrop mode only, the next character written to the US_THR\r
+ * is sent with the address bit set. \r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param ul_addr The address to be sent out.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr)\r
+{\r
+ if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) {\r
+ return 1;\r
+ }\r
+ \r
+ p_usart->US_CR = US_CR_SENDA;\r
+ \r
+ if (usart_write(p_usart, ul_addr)) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_iterations(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RSTIT;\r
+}\r
+\r
+/**\r
+ * \brief Reset NACK in US_CSR.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_nack(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RSTNACK;\r
+}\r
+\r
+/**\r
+ * \brief Restart the receive timeout.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_restart_rx_timeout(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RETTO;\r
+}\r
+\r
+#if (SAM3S || SAM4S || SAM3U)\r
+/**\r
+ * \brief Drive the pin DTR to 0.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_DTR_pin_low(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_DTREN;\r
+}\r
+\r
+/**\r
+ * \brief Drive the pin DTR to 1.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_DTR_pin_high(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_DTRDIS;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Drive the pin RTS to 0.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_RTS_pin_low(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RTSEN;\r
+}\r
+\r
+/**\r
+ * \brief Drive the pin RTS to 1.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_RTS_pin_high(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RTSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_spi_force_chip_select(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_FCS;\r
+}\r
+\r
+/**\r
+ * \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_spi_release_chip_select(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RCS;\r
+}\r
+\r
+/**\r
+ * \brief Check if Transmit is Ready.\r
+ * Check if data have been loaded in USART_THR and are waiting to be loaded \r
+ * into the Transmit Shift Register (TSR).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 No data is in the Transmit Holding Register.\r
+ * \retval 0 There is data in the Transmit Holding Register.\r
+ */\r
+uint32_t usart_is_tx_ready(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_TXRDY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if Transmit Holding Register is empty.\r
+ * Check if the last data written in USART_THR have been loaded in TSR and the last\r
+ * data loaded in TSR have been transmitted.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Transmitter is empty.\r
+ * \retval 0 Transmitter is not empty.\r
+ */\r
+uint32_t usart_is_tx_empty(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if the received data are ready.\r
+ * Check if Data have been received and loaded into USART_RHR.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Some data has been received.\r
+ * \retval 0 No data has been received.\r
+ */\r
+uint32_t usart_is_rx_ready(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_RXRDY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if one receive buffer is filled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Receive is complete.\r
+ * \retval 0 Receive is still pending.\r
+ */\r
+uint32_t usart_is_rx_buf_end(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_ENDRX) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if one transmit buffer is empty.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Transmit is complete.\r
+ * \retval 0 Transmit is still pending.\r
+ */\r
+uint32_t usart_is_tx_buf_end(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_ENDTX) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if both receive buffers are full.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Receive buffers are full.\r
+ * \retval 0 Receive buffers are not full.\r
+ */\r
+uint32_t usart_is_rx_buf_full(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_RXBUFF) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if both transmit buffers are empty.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Transmit buffers are empty.\r
+ * \retval 0 Transmit buffers are not empty.\r
+ */\r
+uint32_t usart_is_tx_buf_empty(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_TXBUFE) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Write to USART Transmit Holding Register.\r
+ *\r
+ * \note Before writing user should check if tx is ready (or empty).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Data to be sent.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_write(Usart *p_usart, uint32_t c)\r
+{\r
+ if (!(p_usart->US_CSR & US_CSR_TXRDY)) {\r
+ return 1;\r
+ }\r
+\r
+ p_usart->US_THR = US_THR_TXCHR(c);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Write to USART Transmit Holding Register.\r
+ *\r
+ * \note Before writing user should check if tx is ready (or empty).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Data to be sent.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_putchar(Usart *p_usart, uint32_t c)\r
+{\r
+ uint32_t timeout = USART_DEFAULT_TIMEOUT;\r
+\r
+ while (!(p_usart->US_CSR & US_CSR_TXRDY)) {\r
+ if (!timeout--) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ p_usart->US_THR = US_THR_TXCHR(c);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Write one-line string through USART.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param string Pointer to one-line string to be sent.\r
+ */\r
+void usart_write_line(Usart *p_usart, const char *string)\r
+{\r
+ while (*string != '\0') {\r
+ usart_putchar(p_usart, *string++);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Read from USART Receive Holding Register.\r
+ *\r
+ * \note Before reading user should check if rx is ready.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Pointer where the one-byte received data will be stored.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 if no data is available or errors.\r
+ */\r
+uint32_t usart_read(Usart *p_usart, uint32_t *c)\r
+{\r
+ if (!(p_usart->US_CSR & US_CSR_RXRDY)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Read character */\r
+ *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Read from USART Receive Holding Register.\r
+ * Before reading user should check if rx is ready.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Pointer where the one-byte received data will be stored.\r
+ *\r
+ * \retval 0 Data has been received.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_getchar(Usart *p_usart, uint32_t *c)\r
+{\r
+ uint32_t timeout = USART_DEFAULT_TIMEOUT;\r
+\r
+ /* If the receiver is empty, wait until it's not empty or timeout has reached. */\r
+ while (!(p_usart->US_CSR & US_CSR_RXRDY)) {\r
+ if (!timeout--) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ /* Read character */\r
+ *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Get Transmit address for DMA operation.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return Transmit address for DMA access.\r
+ */\r
+uint32_t *usart_get_tx_access(Usart *p_usart)\r
+{\r
+ return (uint32_t *)&(p_usart->US_THR);\r
+}\r
+\r
+/**\r
+ * \brief Get Receive address for DMA operation.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return Receive address for DMA access.\r
+ */\r
+uint32_t *usart_get_rx_access(Usart *p_usart)\r
+{\r
+ return (uint32_t *)&(p_usart->US_RHR);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Get USART PDC base address.\r
+ *\r
+ * \param p_usart Pointer to a UART instance.\r
+ *\r
+ * \return USART PDC registers base for PDC driver to access.\r
+ */\r
+Pdc *usart_get_pdc_base(Usart *p_usart)\r
+{\r
+ Pdc *p_pdc_base;\r
+\r
+ p_pdc_base = (Pdc *) NULL;\r
+\r
+ if (p_usart == USART0) {\r
+ p_pdc_base = PDC_USART0;\r
+ return p_pdc_base;\r
+ }\r
+#if (SAM3S || SAM4S || SAM3XA || SAM3U)\r
+ else if (p_usart == USART1) {\r
+ p_pdc_base = PDC_USART1;\r
+ return p_pdc_base;\r
+ }\r
+#endif\r
+#if (SAM3SD8 || SAM3XA || SAM3U)\r
+ else if (p_usart == USART2) {\r
+ p_pdc_base = PDC_USART2;\r
+ return p_pdc_base;\r
+ }\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+ else if (p_usart == USART3) {\r
+ p_pdc_base = PDC_USART3;\r
+ return p_pdc_base;\r
+ }\r
+#endif\r
+\r
+ return p_pdc_base;\r
+}\r
+\r
+/**\r
+ * \brief Enable write protect of USART registers.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_enable_writeprotect(Usart *p_usart)\r
+{\r
+ p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY(US_WPKEY_VALUE);\r
+}\r
+\r
+/**\r
+ * \brief Disable write protect of USART registers.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_disable_writeprotect(Usart *p_usart)\r
+{\r
+ p_usart->US_WPMR = US_WPMR_WPKEY(US_WPKEY_VALUE);\r
+}\r
+\r
+/**\r
+ * \brief Get write protect status.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return 0 if the peripheral is not protected. \r
+ * \return 16-bit Write Protect Violation Status otherwise.\r
+ */\r
+uint32_t usart_get_writeprotect_status(Usart *p_usart)\r
+{\r
+ uint32_t reg_value;\r
+\r
+ reg_value = p_usart->US_WPSR;\r
+ if (reg_value & US_WPSR_WPVS) {\r
+ return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get the total number of errors that occur during an ISO7816 transfer.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return The number of errors that occurred.\r
+ */\r
+uint8_t usart_get_error_number(Usart *p_usart)\r
+{\r
+ return (p_usart->US_NER & US_NER_NB_ERRORS_Msk);\r
+}\r
+\r
+#if (SAM3S || SAM4S || SAM3U || SAM3XA)\r
+/**\r
+ * \brief Configure the transmitter preamble length when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_len The transmitter preamble length, which should be 0 ~ 15.\r
+ */\r
+void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) |\r
+ US_MAN_TX_PL(uc_len);\r
+}\r
+\r
+/**\r
+ * \brief Configure the transmitter preamble pattern when the Manchester \r
+ * encode/decode is enabled, which should be 0 ~ 3.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_pattern 0 if the preamble is composed of '1's;\r
+ * 1 if the preamble is composed of '0's;\r
+ * 2 if the preamble is composed of '01's;\r
+ * 3 if the preamble is composed of '10's.\r
+ */\r
+void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) |\r
+ (uc_pattern << US_MAN_TX_PP_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Configure the transmitter Manchester polarity when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_polarity Indicate the transmitter Manchester polarity, which \r
+ * should be 0 or 1.\r
+ */\r
+void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) |\r
+ (uc_polarity << 12);\r
+}\r
+\r
+/**\r
+ * \brief Configure the detected receiver preamble length when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_len The detected receiver preamble length, which should be 0 ~ 15.\r
+ */\r
+void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) |\r
+ US_MAN_RX_PL(uc_len);\r
+}\r
+\r
+/**\r
+ * \brief Configure the detected receiver preamble pattern when the Manchester \r
+ * encode/decode is enabled, which should be 0 ~ 3.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_pattern 0 if the preamble is composed of '1's;\r
+ * 1 if the preamble is composed of '0's;\r
+ * 2 if the preamble is composed of '01's;\r
+ * 3 if the preamble is composed of '10's.\r
+ */\r
+void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) |\r
+ (uc_pattern << US_MAN_RX_PP_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Configure the receiver Manchester polarity when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_polarity Indicate the receiver Manchester polarity, which should \r
+ * be 0 or 1.\r
+ */\r
+void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) |\r
+ (uc_polarity << 28);\r
+}\r
+\r
+/**\r
+ * \brief Enable drift compensation.\r
+ *\r
+ * \note The 16X clock mode must be enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_man_enable_drift_compensation(Usart *p_usart)\r
+{\r
+ p_usart->US_MAN |= US_MAN_DRIFT;\r
+}\r
+\r
+/**\r
+ * \brief Disable drift compensation.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_man_disable_drift_compensation(Usart *p_usart)\r
+{\r
+ p_usart->US_MAN &= ~US_MAN_DRIFT;\r
+}\r
+#endif\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef USART_H_INCLUDED\r
+#define USART_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/**\r
+ * \defgroup usart_group Universal Synchronous Asynchronous Receiver Transmitter (USART)\r
+ *\r
+ * See \ref sam_usart_quickstart.\r
+ *\r
+ * This is a low-level driver implementation for the SAM Universal\r
+ * Synchronous/Asynchronous Receiver/Transmitter.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/** Clock phase. */\r
+#define SPI_CPHA (1 << 0)\r
+\r
+/** Clock polarity. */\r
+#define SPI_CPOL (1 << 1)\r
+\r
+/** SPI mode definition. */\r
+#define SPI_MODE_0 (SPI_CPHA)\r
+#define SPI_MODE_1 0\r
+#define SPI_MODE_2 (SPI_CPOL | SPI_CPHA)\r
+#define SPI_MODE_3 (SPI_CPOL)\r
+\r
+//! Input parameters when initializing RS232 and similar modes.\r
+typedef struct {\r
+ //! Set baud rate of the USART (unused in slave modes).\r
+ uint32_t baudrate;\r
+ \r
+ //! Number of bits, which should be one of the following: US_MR_CHRL_5_BIT,\r
+ //! US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or US_MR_MODE9.\r
+ uint32_t char_length;\r
+ \r
+ //! Parity type, which should be one of the following: US_MR_PAR_EVEN, US_MR_PAR_ODD,\r
+ //! US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO or US_MR_PAR_MULTIDROP.\r
+ uint32_t parity_type;\r
+\r
+ //! Number of stop bits between two characters: US_MR_NBSTOP_1_BIT,\r
+ //! US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT.\r
+ //! \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only.\r
+ uint32_t stop_bits;\r
+\r
+ //! Run the channel in test mode, which should be one of following: US_MR_CHMODE_NORMAL,\r
+ //! US_MR_CHMODE_AUTOMATIC, US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK\r
+ uint32_t channel_mode;\r
+\r
+ //! Filter of IrDA mode, useless in other modes. \r
+ uint32_t irda_filter;\r
+} sam_usart_opt_t;\r
+\r
+//! Input parameters when initializing ISO7816 mode.\r
+typedef struct {\r
+ //! Set the frequency of the ISO7816 clock.\r
+ uint32_t iso7816_hz;\r
+ \r
+ //! The number of ISO7816 clock ticks in every bit period (1 to 2047, 0 = disable clock).\r
+ //! Baudrate rate = iso7816_hz / fidi_ratio\r
+ uint32_t fidi_ratio;\r
+\r
+ //! How to calculate the parity bit: US_MR_PAR_EVEN for normal mode or\r
+ //! US_MR_PAR_ODD for inverse mode.\r
+ uint32_t parity_type;\r
+\r
+ //! Inhibit Non Acknowledge:\r
+ //! - 0: the NACK is generated;\r
+ //! - 1: the NACK is not generated.\r
+ //!\r
+ //! \note This bit will be used only in ISO7816 mode, protocol T = 0 receiver.\r
+ uint32_t inhibit_nack;\r
+\r
+ //! Disable successive NACKs.\r
+ //! - 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character.\r
+ //! Successive parity errors are counted up to the value in the max_iterations field.\r
+ //! These parity errors generate a NACK on the ISO line. As soon as this value is reached,\r
+ //! No additional NACK is sent on the ISO line. The ITERATION flag is asserted.\r
+ uint32_t dis_suc_nack;\r
+\r
+ //! Max number of repetitions (0 to 7).\r
+ uint32_t max_iterations;\r
+\r
+ //! Bit order in transmitted characters:\r
+ //! - 0: LSB first;\r
+ //! - 1: MSB first.\r
+ uint32_t bit_order;\r
+ \r
+ //! Which protocol is used:\r
+ //! - 0: T = 0;\r
+ //! - 1: T = 1.\r
+ uint32_t protocol_type;\r
+} usart_iso7816_opt_t;\r
+\r
+//! Input parameters when initializing SPI mode.\r
+typedef struct {\r
+ //! Set the frequency of the SPI clock (unused in slave mode).\r
+ uint32_t baudrate;\r
+\r
+ //! Number of bits, which should be one of the following: US_MR_CHRL_5_BIT,\r
+ //! US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or US_MR_MODE9.\r
+ uint32_t char_length;\r
+\r
+ //! Which SPI mode to use, which should be one of the following:\r
+ //! SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3.\r
+ uint32_t spi_mode;\r
+\r
+ //! Run the channel in test mode, which should be one of following: US_MR_CHMODE_NORMAL,\r
+ //! US_MR_CHMODE_AUTOMATIC, US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK\r
+ uint32_t channel_mode;\r
+} usart_spi_opt_t;\r
+\r
+void usart_reset(Usart *p_usart);\r
+uint32_t usart_init_rs232(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_hw_handshaking(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+#if (SAM3S || SAM4S || SAM3U)\r
+uint32_t usart_init_modem(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+#endif\r
+uint32_t usart_init_sync_master(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_sync_slave(Usart *p_usart, const sam_usart_opt_t *p_usart_opt);\r
+uint32_t usart_init_rs485(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_irda(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_iso7816(Usart *p_usart, const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_spi_master(Usart *p_usart, const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_spi_slave(Usart *p_usart, const usart_spi_opt_t *p_usart_opt);\r
+#if SAM3XA\r
+uint32_t usart_init_lin_master(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_lin_slave(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+void usart_lin_abort_tx(Usart *p_usart);\r
+void usart_lin_send_wakeup_signal(Usart *p_usart);\r
+void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action);\r
+void usart_lin_disable_parity(Usart *p_usart);\r
+void usart_lin_enable_parity(Usart *p_usart);\r
+void usart_lin_disable_checksum(Usart *p_usart);\r
+void usart_lin_enable_checksum(Usart *p_usart);\r
+void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type);\r
+void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode);\r
+void usart_lin_disable_frame_slot(Usart *p_usart);\r
+void usart_lin_enable_frame_slot(Usart *p_usart);\r
+void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type);\r
+void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len);\r
+void usart_lin_disable_pdc_mode(Usart *p_usart);\r
+void usart_lin_enable_pdc_mode(Usart *p_usart);\r
+void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id);\r
+uint8_t usart_lin_read_identifier(Usart *p_usart);\r
+#endif\r
+void usart_enable_tx(Usart *p_usart);\r
+void usart_disable_tx(Usart *p_usart);\r
+void usart_reset_tx(Usart *p_usart);\r
+void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard);\r
+void usart_enable_rx(Usart *p_usart);\r
+void usart_disable_rx(Usart *p_usart);\r
+void usart_reset_rx(Usart *p_usart);\r
+void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout);\r
+void usart_enable_interrupt(Usart *p_usart,uint32_t ul_sources);\r
+void usart_disable_interrupt(Usart *p_usart,uint32_t ul_sources);\r
+uint32_t usart_get_interrupt_mask(Usart *p_usart);\r
+uint32_t usart_get_status(Usart *p_usart);\r
+void usart_reset_status(Usart *p_usart);\r
+void usart_start_tx_break(Usart *p_usart);\r
+void usart_stop_tx_break(Usart *p_usart);\r
+void usart_start_rx_timeout(Usart *p_usart);\r
+uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr);\r
+void usart_reset_iterations(Usart *p_usart);\r
+void usart_reset_nack(Usart *p_usart);\r
+void usart_restart_rx_timeout(Usart *p_usart);\r
+#if (SAM3S || SAM4S || SAM3U)\r
+void usart_drive_DTR_pin_low(Usart *p_usart);\r
+void usart_drive_DTR_pin_high(Usart *p_usart);\r
+#endif\r
+void usart_drive_RTS_pin_low(Usart *p_usart);\r
+void usart_drive_RTS_pin_high(Usart *p_usart);\r
+void usart_spi_force_chip_select(Usart *p_usart);\r
+void usart_spi_release_chip_select(Usart *p_usart);\r
+uint32_t usart_is_tx_ready(Usart *p_usart);\r
+uint32_t usart_is_tx_empty(Usart *p_usart);\r
+uint32_t usart_is_rx_ready(Usart *p_usart);\r
+uint32_t usart_is_rx_buf_end(Usart *p_usart);\r
+uint32_t usart_is_tx_buf_end(Usart *p_usart);\r
+uint32_t usart_is_rx_buf_full(Usart *p_usart);\r
+uint32_t usart_is_tx_buf_empty(Usart *p_usart);\r
+uint32_t usart_write(Usart *p_usart, uint32_t c);\r
+uint32_t usart_putchar(Usart *p_usart, uint32_t c);\r
+void usart_write_line(Usart *p_usart, const char *string);\r
+uint32_t usart_read(Usart *p_usart, uint32_t *c);\r
+uint32_t usart_getchar(Usart *p_usart, uint32_t *c);\r
+#if (SAM3XA || SAM3U)\r
+uint32_t * usart_get_tx_access(Usart *p_usart);\r
+uint32_t * usart_get_rx_access(Usart *p_usart);\r
+#endif\r
+Pdc *usart_get_pdc_base(Usart *p_usart);\r
+void usart_enable_writeprotect(Usart *p_usart);\r
+void usart_disable_writeprotect(Usart *p_usart);\r
+uint32_t usart_get_writeprotect_status(Usart *p_usart);\r
+uint8_t usart_get_error_number(Usart *p_usart);\r
+#if (SAM3S || SAM4S || SAM3U || SAM3XA)\r
+void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len);\r
+void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern);\r
+void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity);\r
+void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len);\r
+void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern);\r
+void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity);\r
+void usart_man_enable_drift_compensation(Usart *p_usart);\r
+void usart_man_disable_drift_compensation(Usart *p_usart);\r
+#endif\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+//! @}\r
+\r
+/**\r
+ * \page sam_usart_quickstart Quick start guide for the SAM USART module\r
+ *\r
+ * This is the quick start guide for the \ref usart_group "USART module", with\r
+ * step-by-step instructions on how to configure and use the driver in a\r
+ * selection of use cases.\r
+ *\r
+ * The use cases contain several code fragments. The code fragments in the\r
+ * steps for setup can be copied into a custom initialization function, while\r
+ * the steps for usage can be copied into, e.g., the main application function.\r
+ *\r
+ * \note Some SAM devices contain both USART and UART modules, with the latter\r
+ * being a subset in functionality of the former but physically separate\r
+ * peripherals. UART modules are compatible with the USART driver, but\r
+ * only for the functions and modes supported by the base UART driver.\r
+ *\r
+ * \section usart_basic_use_case Basic use case\r
+ * \section usart_use_cases USART use cases\r
+ * - \ref usart_basic_use_case\r
+ * - \subpage usart_use_case_1\r
+ * - \subpage usart_use_case_2\r
+ *\r
+ * \section usart_basic_use_case Basic use case - transmit a character\r
+ * In this use case, the USART module is configured for:\r
+ * - Using USART0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * \section usart_basic_use_case_setup Setup steps\r
+ *\r
+ * \subsection usart_basic_use_case_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclock)"\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ * -# \ref pmc_group "Power Management Controller (pmc)"\r
+ *\r
+ * \subsection usart_basic_use_case_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_usart.h file, but it can also be added to your main application file.)\r
+ * \code\r
+ * #define USART_SERIAL USART0\r
+ * #define USART_SERIAL_ID ID_USART0\r
+ * #define USART_SERIAL_PIO PINS_USART_PIO\r
+ * #define USART_SERIAL_TYPE PINS_USART_TYPE\r
+ * #define USART_SERIAL_PINS PINS_USART_PINS\r
+ * #define USART_SERIAL_MASK PINS_USART_MASK\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT\r
+ * #define USART_SERIAL_PARITY US_MR_PAR_NO\r
+ * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT\r
+ * \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_basic_use_case_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ * -# Configure the USART Tx and Rx pins as Outputs and Inputs respectively:\r
+ * \code\r
+ * pio_configure(PINS_UART_PIO, PINS_UART_TYPE, PINS_UART_MASK,\r
+ * PINS_UART_ATTR);\r
+ * \endcode\r
+ * -# Create USART options struct:\r
+ * \code\r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \endcode\r
+ * -# Enable the clock to the USART module:\r
+ * \code\r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \endcode\r
+ * -# Initialize the USART module in RS232 mode:\r
+ * \code\r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * \endcode\r
+ * -# Enable the Rx and Tx modes of the USART module:\r
+ * \code\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \section usart_basic_use_case_usage Usage steps\r
+ *\r
+ * \subsection usart_basic_use_case_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * usart_putchar(USART_SERIAL, 'a');\r
+ * \endcode\r
+ *\r
+ * \subsection usart_basic_use_case_usage_flow Workflow\r
+ * -# Send an 'a' character via USART\r
+ * \code usart_putchar(USART_SERIAL, 'a'); \endcode\r
+ */\r
+\r
+/**\r
+ * \page usart_use_case_1 USART receive character and echo back\r
+ *\r
+ * In this use case, the USART module is configured for:\r
+ * - Using USART0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * The use case waits for a received character on the configured USART and\r
+ * echoes the character back to the same USART.\r
+ *\r
+ * \section usart_use_case_1_setup Setup steps\r
+ *\r
+ * \subsection usart_use_case_1_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclock)"\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ * -# \ref pmc_group "Power Management Controller (pmc)"\r
+ *\r
+ * \subsection usart_use_case_1_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_usart.h file, but it can also be added to your main application file.):\r
+ * \code\r
+ * #define USART_SERIAL USART0\r
+ * #define USART_SERIAL_ID ID_USART0\r
+ * #define USART_SERIAL_PIO PINS_USART_PIO\r
+ * #define USART_SERIAL_TYPE PINS_USART_TYPE\r
+ * #define USART_SERIAL_PINS PINS_USART_PINS\r
+ * #define USART_SERIAL_MASK PINS_USART_MASK\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT\r
+ * #define USART_SERIAL_PARITY US_MR_PAR_NO\r
+ * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT\r
+ * \endcode\r
+ *\r
+ * A variable for the received byte must be added:\r
+ * \code\r
+ * uint32_t received_byte;\r
+ * \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_1_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ * -# Configure the USART Tx and Rx pins as Outputs and Inputs respectively:\r
+ * \code\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \endcode\r
+ * -# Create USART options struct:\r
+ * \code\r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \endcode\r
+ * -# Enable the clock to the USART module:\r
+ * \code pmc_enable_periph_clk(USART_SERIAL_ID); \endcode\r
+ * -# Initialize the USART module in RS232 mode:\r
+ * \code usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz()); \endcode\r
+ * -# Enable the Rx and Tx modes of the USART module:\r
+ * \code\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \section usart_use_case_1_usage Usage steps\r
+ *\r
+ * \subsection usart_use_case_1_usage_code Example code\r
+ * Add to, e.g., main loop in application C-file:\r
+ * \code\r
+ * received_byte = usart_getchar(USART_SERIAL);\r
+ * usart_putchar(USART_SERIAL, received_byte);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_1_usage_flow Workflow\r
+ * -# Wait for reception of a character:\r
+ * \code usart_getchar(USART_SERIAL, &received_byte); \endcode\r
+ * -# Echo the character back:\r
+ * \code usart_putchar(USART_SERIAL, received_byte); \endcode\r
+ */\r
+\r
+/**\r
+ * \page usart_use_case_2 USART receive character and echo back via interrupts\r
+ *\r
+ * In this use case, the USART module is configured for:\r
+ * - Using USART0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * The use case waits for a received character on the configured USART and\r
+ * echoes the character back to the same USART. The character reception is\r
+ * performed via an interrupt handler, rather than the polling method used\r
+ * in \ref usart_use_case_1.\r
+ *\r
+ * \section usart_use_case_2_setup Setup steps\r
+ *\r
+ * \subsection usart_use_case_2_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclock)"\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ * -# \ref pmc_group "Power Management Controller (pmc)"\r
+ *\r
+ * \subsection usart_use_case_2_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_usart.h file, but it can also be added to your main application file.):\r
+ * \code\r
+ * #define USART_SERIAL USART0\r
+ * #define USART_SERIAL_ID ID_USART0\r
+ * #define USART_SERIAL_ISR_HANDLER USART0_Handler\r
+ * #define USART_SERIAL_PIO PINS_USART_PIO\r
+ * #define USART_SERIAL_TYPE PINS_USART_TYPE\r
+ * #define USART_SERIAL_PINS PINS_USART_PINS\r
+ * #define USART_SERIAL_MASK PINS_USART_MASK\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT\r
+ * #define USART_SERIAL_PARITY US_MR_PAR_NO\r
+ * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT\r
+ * \endcode\r
+ *\r
+ * A variable for the received byte must be added:\r
+ * \code\r
+ * uint32_t received_byte;\r
+ * \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \r
+ * usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY);\r
+ * NVIC_EnableIRQ(USART_SERIAL_IRQ);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_2_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ * -# Configure the USART Tx and Rx pins as Outputs and Inputs respectively:\r
+ * \code\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \endcode\r
+ * -# Create USART options struct:\r
+ * \code\r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \endcode\r
+ * -# Enable the clock to the USART module:\r
+ * \code pmc_enable_periph_clk(USART_SERIAL_ID); \endcode\r
+ * -# Initialize the USART module in RS232 mode:\r
+ * \code usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz()); \endcode\r
+ * -# Enable the Rx and Tx modes of the USART module:\r
+ * \code\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ * -# Enable the USART character reception interrupt, and general interrupts for the USART module.\r
+ * \code\r
+ * usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY);\r
+ * NVIC_EnableIRQ(USART_SERIAL_IRQ);\r
+ * \endcode\r
+ * \section usart_use_case_2_usage Usage steps\r
+ *\r
+ * \subsection usart_use_case_2_usage_code Example code\r
+ * Add to your main application C-file the USART interrupt handler:\r
+ * \code\r
+ * void USART_SERIAL_ISR_HANDLER(void)\r
+ * {\r
+ * uint32_t dw_status = usart_get_status(USART_SERIAL);\r
+ * \r
+ * if (dw_status & US_CSR_RXRDY) {\r
+ * uint32_t received_byte;\r
+ * \r
+ * usart_read(USART_SERIAL, &received_byte);\r
+ * usart_write(USART_SERIAL, received_byte);\r
+ * }\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_2_usage_flow Workflow\r
+ * -# When the USART ISR fires, retrieve the USART module interrupt flags:\r
+ * \code uint32_t dw_status = usart_get_status(USART_SERIAL); \endcode\r
+ * -# Check if the USART Receive Character interrupt has fired:\r
+ * \code if (dw_status & US_CSR_RXRDY) \endcode\r
+ * -# If a character has been received, fetch it into a temporary variable:\r
+ * \code usart_read(USART_SERIAL, &received_byte); \endcode\r
+ * -# Echo the character back:\r
+ * \code usart_write(USART_SERIAL, received_byte); \endcode\r
+ */\r
+\r
+#endif /* USART_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_ACC_COMPONENT_\r
+#define _SAM3S8_ACC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_ACC Analog Comparator Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Acc hardware registers */\r
+typedef struct {\r
+ WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */\r
+ RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */\r
+ RoReg Reserved1[7];\r
+ WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */\r
+ WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */\r
+ RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved2[24];\r
+ RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */\r
+ RoReg Reserved3[19];\r
+ RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */\r
+} Acc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */\r
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */\r
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */\r
+#define ACC_MR_SELMINUS_Pos 0\r
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */\r
+#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */\r
+#define ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */\r
+#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */\r
+#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */\r
+#define ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */\r
+#define ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */\r
+#define ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */\r
+#define ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */\r
+#define ACC_MR_SELPLUS_Pos 4\r
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */\r
+#define ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */\r
+#define ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */\r
+#define ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */\r
+#define ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */\r
+#define ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */\r
+#define ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */\r
+#define ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */\r
+#define ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */\r
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */\r
+#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */\r
+#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */\r
+#define ACC_MR_EDGETYP_Pos 9\r
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */\r
+#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */\r
+#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */\r
+#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */\r
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */\r
+#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */\r
+#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */\r
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */\r
+#define ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */\r
+#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */\r
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */\r
+#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */\r
+#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */\r
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */\r
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */\r
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */\r
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */\r
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */\r
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */\r
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) */\r
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */\r
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */\r
+#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */\r
+#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */\r
+#define ACC_ACR_HYST_Pos 1\r
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */\r
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))\r
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */\r
+#define ACC_WPMR_WPKEY_Pos 8\r
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */\r
+#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))\r
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_ACC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_ADC_COMPONENT_\r
+#define _SAM3S8_ADC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_ADC Analog-to-digital Converter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Adc hardware registers */\r
+typedef struct {\r
+ WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */\r
+ RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */\r
+ RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */\r
+ RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */\r
+ WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */\r
+ WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */\r
+ RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */\r
+ RoReg Reserved1[1];\r
+ RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */\r
+ WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */\r
+ WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */\r
+ RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved2[2];\r
+ RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */\r
+ RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */\r
+ RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */\r
+ RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */\r
+ RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */\r
+ RoReg ADC_CDR[15]; /**< \brief (Adc Offset: 0x50) Channel Data Register */\r
+ RoReg Reserved3[2];\r
+ RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */\r
+ RoReg Reserved4[19];\r
+ RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved5[5];\r
+ RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */\r
+ RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */\r
+ RoReg Reserved7[2];\r
+ WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */\r
+ RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */\r
+} Adc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */\r
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */\r
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */\r
+#define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */\r
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */\r
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */\r
+#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */\r
+#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */\r
+#define ADC_MR_TRGSEL_Pos 1\r
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */\r
+#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */\r
+#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */\r
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */\r
+#define ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */\r
+#define ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */\r
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */\r
+#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */\r
+#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */\r
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */\r
+#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */\r
+#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */\r
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */\r
+#define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */\r
+#define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */\r
+#define ADC_MR_PRESCAL_Pos 8\r
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */\r
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))\r
+#define ADC_MR_STARTUP_Pos 16\r
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */\r
+#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */\r
+#define ADC_MR_SETTLING_Pos 20\r
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */\r
+#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */\r
+#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */\r
+#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */\r
+#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */\r
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */\r
+#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */\r
+#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */\r
+#define ADC_MR_TRACKTIM_Pos 24\r
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */\r
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))\r
+#define ADC_MR_TRANSFER_Pos 28\r
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */\r
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))\r
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */\r
+#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */\r
+#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */\r
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */\r
+#define ADC_SEQR1_USCH1_Pos 0\r
+#define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */\r
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))\r
+#define ADC_SEQR1_USCH2_Pos 4\r
+#define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */\r
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))\r
+#define ADC_SEQR1_USCH3_Pos 8\r
+#define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */\r
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))\r
+#define ADC_SEQR1_USCH4_Pos 12\r
+#define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */\r
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))\r
+#define ADC_SEQR1_USCH5_Pos 16\r
+#define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */\r
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))\r
+#define ADC_SEQR1_USCH6_Pos 20\r
+#define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */\r
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))\r
+#define ADC_SEQR1_USCH7_Pos 24\r
+#define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */\r
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))\r
+#define ADC_SEQR1_USCH8_Pos 28\r
+#define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */\r
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))\r
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */\r
+#define ADC_SEQR2_USCH9_Pos 0\r
+#define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */\r
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))\r
+#define ADC_SEQR2_USCH10_Pos 4\r
+#define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */\r
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))\r
+#define ADC_SEQR2_USCH11_Pos 8\r
+#define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */\r
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))\r
+#define ADC_SEQR2_USCH12_Pos 12\r
+#define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */\r
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))\r
+#define ADC_SEQR2_USCH13_Pos 16\r
+#define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */\r
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))\r
+#define ADC_SEQR2_USCH14_Pos 20\r
+#define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */\r
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))\r
+#define ADC_SEQR2_USCH15_Pos 24\r
+#define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */\r
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))\r
+#define ADC_SEQR2_USCH16_Pos 28\r
+#define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */\r
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))\r
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */\r
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */\r
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */\r
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */\r
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */\r
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */\r
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */\r
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */\r
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */\r
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */\r
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */\r
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */\r
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */\r
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */\r
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */\r
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */\r
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */\r
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */\r
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */\r
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */\r
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */\r
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */\r
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */\r
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */\r
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */\r
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */\r
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */\r
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */\r
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */\r
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */\r
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */\r
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */\r
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */\r
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */\r
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */\r
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */\r
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */\r
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */\r
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */\r
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */\r
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */\r
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */\r
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */\r
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */\r
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */\r
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */\r
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */\r
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */\r
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */\r
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */\r
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */\r
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */\r
+#define ADC_LCDR_LDATA_Pos 0\r
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */\r
+#define ADC_LCDR_CHNB_Pos 12\r
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */\r
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */\r
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */\r
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */\r
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */\r
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */\r
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */\r
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */\r
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */\r
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */\r
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */\r
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */\r
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */\r
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */\r
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */\r
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */\r
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */\r
+#define ADC_IER_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Calibration Sequence */\r
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */\r
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */\r
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */\r
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */\r
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */\r
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */\r
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */\r
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */\r
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */\r
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */\r
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */\r
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */\r
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */\r
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */\r
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */\r
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */\r
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */\r
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */\r
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */\r
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */\r
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */\r
+#define ADC_IDR_EOCAL (0x1u << 23) /**< \brief (ADC_IDR) End of Calibration Sequence */\r
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */\r
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */\r
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */\r
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */\r
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */\r
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */\r
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */\r
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */\r
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */\r
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */\r
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */\r
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */\r
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */\r
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */\r
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */\r
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */\r
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */\r
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */\r
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */\r
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */\r
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */\r
+#define ADC_IMR_EOCAL (0x1u << 23) /**< \brief (ADC_IMR) End of Calibration Sequence */\r
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */\r
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */\r
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */\r
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */\r
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */\r
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */\r
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */\r
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */\r
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */\r
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */\r
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */\r
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */\r
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */\r
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */\r
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */\r
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */\r
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */\r
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */\r
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */\r
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */\r
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */\r
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */\r
+#define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */\r
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */\r
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */\r
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */\r
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */\r
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */\r
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */\r
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */\r
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */\r
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */\r
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */\r
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */\r
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */\r
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */\r
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */\r
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */\r
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */\r
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */\r
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */\r
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */\r
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */\r
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */\r
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */\r
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */\r
+#define ADC_EMR_CMPMODE_Pos 0\r
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */\r
+#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */\r
+#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */\r
+#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */\r
+#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */\r
+#define ADC_EMR_CMPSEL_Pos 4\r
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */\r
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))\r
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */\r
+#define ADC_EMR_CMPFILTER_Pos 12\r
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */\r
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))\r
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */\r
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */\r
+#define ADC_CWR_LOWTHRES_Pos 0\r
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */\r
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))\r
+#define ADC_CWR_HIGHTHRES_Pos 16\r
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */\r
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))\r
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */\r
+#define ADC_CGR_GAIN0_Pos 0\r
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */\r
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))\r
+#define ADC_CGR_GAIN1_Pos 2\r
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */\r
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))\r
+#define ADC_CGR_GAIN2_Pos 4\r
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */\r
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))\r
+#define ADC_CGR_GAIN3_Pos 6\r
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */\r
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))\r
+#define ADC_CGR_GAIN4_Pos 8\r
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */\r
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))\r
+#define ADC_CGR_GAIN5_Pos 10\r
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */\r
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))\r
+#define ADC_CGR_GAIN6_Pos 12\r
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */\r
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))\r
+#define ADC_CGR_GAIN7_Pos 14\r
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */\r
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))\r
+#define ADC_CGR_GAIN8_Pos 16\r
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */\r
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))\r
+#define ADC_CGR_GAIN9_Pos 18\r
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */\r
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))\r
+#define ADC_CGR_GAIN10_Pos 20\r
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */\r
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))\r
+#define ADC_CGR_GAIN11_Pos 22\r
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */\r
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))\r
+#define ADC_CGR_GAIN12_Pos 24\r
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */\r
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))\r
+#define ADC_CGR_GAIN13_Pos 26\r
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */\r
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))\r
+#define ADC_CGR_GAIN14_Pos 28\r
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */\r
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))\r
+#define ADC_CGR_GAIN15_Pos 30\r
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */\r
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))\r
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */\r
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */\r
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */\r
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */\r
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */\r
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */\r
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */\r
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */\r
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */\r
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */\r
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */\r
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */\r
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */\r
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */\r
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */\r
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */\r
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */\r
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */\r
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */\r
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */\r
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */\r
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */\r
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */\r
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */\r
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */\r
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */\r
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */\r
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */\r
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */\r
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */\r
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */\r
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */\r
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */\r
+/* -------- ADC_CDR[15] : (ADC Offset: 0x50) Channel Data Register -------- */\r
+#define ADC_CDR_DATA_Pos 0\r
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[15]) Converted Data */\r
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */\r
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */\r
+#define ADC_ACR_IBCTL_Pos 8\r
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */\r
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))\r
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */\r
+#define ADC_WPMR_WPKEY_Pos 8\r
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */\r
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))\r
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */\r
+#define ADC_WPSR_WPVSRC_Pos 8\r
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */\r
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */\r
+#define ADC_RPR_RXPTR_Pos 0\r
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */\r
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))\r
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */\r
+#define ADC_RCR_RXCTR_Pos 0\r
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */\r
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))\r
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define ADC_RNPR_RXNPTR_Pos 0\r
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */\r
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))\r
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */\r
+#define ADC_RNCR_RXNCTR_Pos 0\r
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */\r
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))\r
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */\r
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */\r
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */\r
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */\r
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */\r
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */\r
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */\r
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_ADC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_CHIPID_COMPONENT_\r
+#define _SAM3S8_CHIPID_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Chip Identifier */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_CHIPID Chip Identifier */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Chipid hardware registers */\r
+typedef struct {\r
+ RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */\r
+ RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */\r
+} Chipid;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */\r
+#define CHIPID_CIDR_VERSION_Pos 0\r
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */\r
+#define CHIPID_CIDR_EPROC_Pos 5\r
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */\r
+#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */\r
+#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */\r
+#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */\r
+#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */\r
+#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */\r
+#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */\r
+#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */\r
+#define CHIPID_CIDR_NVPSIZ_Pos 8\r
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_Pos 12\r
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_Pos 16\r
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */\r
+#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */\r
+#define CHIPID_CIDR_ARCH_Pos 20\r
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */\r
+#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */\r
+#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */\r
+#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */\r
+#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */\r
+#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */\r
+#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */\r
+#define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */\r
+#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */\r
+#define CHIPID_CIDR_NVPTYP_Pos 28\r
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */\r
+#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */\r
+#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */\r
+#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */\r
+#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */\r
+#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */\r
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */\r
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */\r
+#define CHIPID_EXID_EXID_Pos 0\r
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_CHIPID_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_CRCCU_COMPONENT_\r
+#define _SAM3S8_CRCCU_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_CRCCU Cyclic Redundancy Check Calculation Unit */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Crccu hardware registers */\r
+typedef struct {\r
+ RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */\r
+ RoReg Reserved1[1];\r
+ WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */\r
+ WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */\r
+ RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */\r
+ WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */\r
+ WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */\r
+ RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */\r
+ RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */\r
+ RoReg Reserved2[4];\r
+ WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */\r
+ RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */\r
+ RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */\r
+ WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */\r
+ WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */\r
+ RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */\r
+ RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */\r
+} Crccu;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */\r
+#define CRCCU_DSCR_DSCR_Pos 9\r
+#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */\r
+#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))\r
+/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */\r
+#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */\r
+/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */\r
+#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */\r
+/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */\r
+#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */\r
+/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */\r
+#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */\r
+/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */\r
+#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */\r
+/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */\r
+#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */\r
+/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */\r
+#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */\r
+/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */\r
+#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */\r
+/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */\r
+#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */\r
+#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */\r
+#define CRCCU_MR_PTYPE_Pos 2\r
+#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */\r
+#define CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */\r
+#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */\r
+#define CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */\r
+#define CRCCU_MR_DIVIDER_Pos 4\r
+#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */\r
+#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))\r
+/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */\r
+#define CRCCU_SR_CRC_Pos 0\r
+#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */\r
+/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */\r
+#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */\r
+/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */\r
+#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */\r
+/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */\r
+#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */\r
+/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */\r
+#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_CRCCU_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_DACC_COMPONENT_\r
+#define _SAM3S8_DACC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_DACC Digital-to-Analog Converter Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Dacc hardware registers */\r
+typedef struct {\r
+ WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */\r
+ RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */\r
+ RoReg Reserved1[2];\r
+ WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */\r
+ WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */\r
+ RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */\r
+ RoReg Reserved2[1];\r
+ WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */\r
+ WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */\r
+ WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */\r
+ RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved3[24];\r
+ RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */\r
+ RoReg Reserved4[19];\r
+ RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */\r
+ RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */\r
+ RoReg Reserved5[7];\r
+ RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */\r
+ RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */\r
+ RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */\r
+} Dacc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */\r
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */\r
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */\r
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */\r
+#define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */\r
+#define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */\r
+#define DACC_MR_TRGSEL_Pos 1\r
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */\r
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))\r
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */\r
+#define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */\r
+#define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */\r
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */\r
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */\r
+#define DACC_MR_REFRESH_Pos 8\r
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */\r
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))\r
+#define DACC_MR_USER_SEL_Pos 16\r
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */\r
+#define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */\r
+#define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */\r
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */\r
+#define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */\r
+#define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */\r
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */\r
+#define DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */\r
+#define DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */\r
+#define DACC_MR_STARTUP_Pos 24\r
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */\r
+#define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */\r
+#define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */\r
+#define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */\r
+#define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */\r
+#define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */\r
+#define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */\r
+#define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */\r
+#define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */\r
+#define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */\r
+#define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */\r
+#define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */\r
+#define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */\r
+#define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */\r
+#define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */\r
+#define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */\r
+#define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */\r
+#define DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */\r
+#define DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */\r
+#define DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */\r
+#define DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */\r
+#define DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */\r
+#define DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */\r
+#define DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */\r
+#define DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */\r
+#define DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */\r
+#define DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */\r
+#define DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */\r
+#define DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */\r
+#define DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */\r
+#define DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */\r
+#define DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */\r
+#define DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */\r
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */\r
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */\r
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */\r
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */\r
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */\r
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */\r
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */\r
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */\r
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */\r
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */\r
+#define DACC_CDR_DATA_Pos 0\r
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */\r
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))\r
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */\r
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */\r
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */\r
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */\r
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */\r
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */\r
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */\r
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */\r
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */\r
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */\r
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */\r
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */\r
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */\r
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */\r
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */\r
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */\r
+#define DACC_ACR_IBCTLCH0_Pos 0\r
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */\r
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))\r
+#define DACC_ACR_IBCTLCH1_Pos 2\r
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */\r
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))\r
+#define DACC_ACR_IBCTLDACCORE_Pos 8\r
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */\r
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))\r
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */\r
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */\r
+#define DACC_WPMR_WPKEY_Pos 8\r
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */\r
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))\r
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */\r
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */\r
+#define DACC_WPSR_WPROTADDR_Pos 8\r
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */\r
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */\r
+#define DACC_TPR_TXPTR_Pos 0\r
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */\r
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))\r
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */\r
+#define DACC_TCR_TXCTR_Pos 0\r
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */\r
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))\r
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define DACC_TNPR_TXNPTR_Pos 0\r
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */\r
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))\r
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define DACC_TNCR_TXNCTR_Pos 0\r
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */\r
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))\r
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */\r
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */\r
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */\r
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */\r
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */\r
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */\r
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */\r
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_DACC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_EFC_COMPONENT_\r
+#define _SAM3S8_EFC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_EFC Embedded Flash Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Efc hardware registers */\r
+typedef struct {\r
+ RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */\r
+ WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */\r
+ RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */\r
+ RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */\r
+} Efc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */\r
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */\r
+#define EEFC_FMR_FWS_Pos 8\r
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */\r
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))\r
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */\r
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */\r
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */\r
+#define EEFC_FCR_FCMD_Pos 0\r
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */\r
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))\r
+#define EEFC_FCR_FARG_Pos 8\r
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */\r
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))\r
+#define EEFC_FCR_FKEY_Pos 24\r
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */\r
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))\r
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */\r
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */\r
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */\r
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */\r
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */\r
+#define EEFC_FRR_FVALUE_Pos 0\r
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_EFC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_GPBR_COMPONENT_\r
+#define _SAM3S8_GPBR_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_GPBR General Purpose Backup Register */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Gpbr hardware registers */\r
+typedef struct {\r
+ RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */\r
+} Gpbr;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */\r
+#define SYS_GPBR_GPBR_VALUE_Pos 0\r
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */\r
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_GPBR_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_HSMCI_COMPONENT_\r
+#define _SAM3S8_HSMCI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_HSMCI High Speed MultiMedia Card Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Hsmci hardware registers */\r
+typedef struct {\r
+ WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */\r
+ RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */\r
+ RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */\r
+ RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */\r
+ RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */\r
+ WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */\r
+ RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */\r
+ RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */\r
+ RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */\r
+ RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */\r
+ WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */\r
+ RoReg Reserved1[2];\r
+ RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */\r
+ WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */\r
+ WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */\r
+ RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */\r
+ RoReg Reserved2[1];\r
+ RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */\r
+ RoReg Reserved3[35];\r
+ RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */\r
+ RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */\r
+ RoReg Reserved4[5];\r
+ RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */\r
+ RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */\r
+ RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */\r
+ RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */\r
+ RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */\r
+ RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */\r
+ RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */\r
+ RoReg Reserved5[54];\r
+ RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */\r
+} Hsmci;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */\r
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */\r
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */\r
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */\r
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */\r
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */\r
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */\r
+#define HSMCI_MR_CLKDIV_Pos 0\r
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */\r
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))\r
+#define HSMCI_MR_PWSDIV_Pos 8\r
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */\r
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))\r
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */\r
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */\r
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */\r
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */\r
+#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */\r
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */\r
+#define HSMCI_DTOR_DTOCYC_Pos 0\r
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */\r
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))\r
+#define HSMCI_DTOR_DTOMUL_Pos 4\r
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */\r
+#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */\r
+#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */\r
+#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */\r
+#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */\r
+#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */\r
+#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */\r
+#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */\r
+#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */\r
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */\r
+#define HSMCI_SDCR_SDCSEL_Pos 0\r
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */\r
+#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */\r
+#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCBUS_Pos 6\r
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */\r
+#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */\r
+#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */\r
+#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */\r
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */\r
+#define HSMCI_ARGR_ARG_Pos 0\r
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */\r
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))\r
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */\r
+#define HSMCI_CMDR_CMDNB_Pos 0\r
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */\r
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))\r
+#define HSMCI_CMDR_RSPTYP_Pos 6\r
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */\r
+#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */\r
+#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */\r
+#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */\r
+#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */\r
+#define HSMCI_CMDR_SPCMD_Pos 8\r
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */\r
+#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */\r
+#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */\r
+#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */\r
+#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */\r
+#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */\r
+#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */\r
+#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */\r
+#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */\r
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */\r
+#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */\r
+#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */\r
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */\r
+#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */\r
+#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */\r
+#define HSMCI_CMDR_TRCMD_Pos 16\r
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */\r
+#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */\r
+#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */\r
+#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */\r
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */\r
+#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */\r
+#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */\r
+#define HSMCI_CMDR_TRTYP_Pos 19\r
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */\r
+#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */\r
+#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */\r
+#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */\r
+#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */\r
+#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */\r
+#define HSMCI_CMDR_IOSPCMD_Pos 24\r
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */\r
+#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */\r
+#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */\r
+#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */\r
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */\r
+#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */\r
+#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */\r
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */\r
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */\r
+#define HSMCI_BLKR_BCNT_Pos 0\r
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */\r
+#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */\r
+#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */\r
+#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */\r
+#define HSMCI_BLKR_BLKLEN_Pos 16\r
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */\r
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))\r
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */\r
+#define HSMCI_CSTOR_CSTOCYC_Pos 0\r
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */\r
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))\r
+#define HSMCI_CSTOR_CSTOMUL_Pos 4\r
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */\r
+#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */\r
+#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */\r
+#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */\r
+#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */\r
+#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */\r
+#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */\r
+#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */\r
+#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */\r
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */\r
+#define HSMCI_RSPR_RSP_Pos 0\r
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */\r
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */\r
+#define HSMCI_RDR_DATA_Pos 0\r
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */\r
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */\r
+#define HSMCI_TDR_DATA_Pos 0\r
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */\r
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))\r
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */\r
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */\r
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */\r
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */\r
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */\r
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */\r
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */\r
+#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */\r
+#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */\r
+#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */\r
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */\r
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */\r
+#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */\r
+#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */\r
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */\r
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */\r
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */\r
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */\r
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */\r
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */\r
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */\r
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */\r
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */\r
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */\r
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */\r
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */\r
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */\r
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */\r
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */\r
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */\r
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */\r
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */\r
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */\r
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */\r
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */\r
+#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */\r
+#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */\r
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */\r
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */\r
+#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */\r
+#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */\r
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */\r
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */\r
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */\r
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */\r
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */\r
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */\r
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */\r
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */\r
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */\r
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */\r
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */\r
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */\r
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */\r
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */\r
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */\r
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */\r
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */\r
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */\r
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */\r
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */\r
+#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */\r
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */\r
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */\r
+#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */\r
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */\r
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */\r
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */\r
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */\r
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */\r
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */\r
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */\r
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */\r
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */\r
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */\r
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */\r
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */\r
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */\r
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */\r
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */\r
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */\r
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */\r
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */\r
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */\r
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */\r
+#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */\r
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */\r
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */\r
+#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */\r
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */\r
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */\r
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */\r
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */\r
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */\r
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */\r
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */\r
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */\r
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */\r
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */\r
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */\r
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */\r
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */\r
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */\r
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */\r
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */\r
+#define HSMCI_WPMR_WP_KEY_Pos 8\r
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */\r
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))\r
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define HSMCI_WPSR_WP_VS_Pos 0\r
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */\r
+#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */\r
+#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */\r
+#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */\r
+#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */\r
+#define HSMCI_WPSR_WP_VSRC_Pos 8\r
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */\r
+/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */\r
+#define HSMCI_RPR_RXPTR_Pos 0\r
+#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */\r
+#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos)))\r
+/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */\r
+#define HSMCI_RCR_RXCTR_Pos 0\r
+#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */\r
+#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos)))\r
+/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */\r
+#define HSMCI_TPR_TXPTR_Pos 0\r
+#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */\r
+#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos)))\r
+/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */\r
+#define HSMCI_TCR_TXCTR_Pos 0\r
+#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */\r
+#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos)))\r
+/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define HSMCI_RNPR_RXNPTR_Pos 0\r
+#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */\r
+#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos)))\r
+/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */\r
+#define HSMCI_RNCR_RXNCTR_Pos 0\r
+#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */\r
+#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos)))\r
+/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define HSMCI_TNPR_TXNPTR_Pos 0\r
+#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */\r
+#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos)))\r
+/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define HSMCI_TNCR_TXNCTR_Pos 0\r
+#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */\r
+#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos)))\r
+/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */\r
+#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */\r
+#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */\r
+#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */\r
+#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */\r
+/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */\r
+#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */\r
+#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_HSMCI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_MATRIX_COMPONENT_\r
+#define _SAM3S8_MATRIX_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_MATRIX AHB Bus Matrix */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Matrix hardware registers */\r
+typedef struct {\r
+ RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */\r
+ RoReg Reserved1[12];\r
+ RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */\r
+ RoReg Reserved2[11];\r
+ RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */\r
+ RoReg Reserved3[1];\r
+ RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */\r
+ RoReg Reserved4[1];\r
+ RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */\r
+ RoReg Reserved5[1];\r
+ RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */\r
+ RoReg Reserved6[1];\r
+ RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */\r
+ RoReg Reserved7[1];\r
+ RoReg Reserved8[27];\r
+ RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */\r
+ RoReg Reserved9[1];\r
+ RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */\r
+ RoReg Reserved10[49];\r
+ RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */\r
+ RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */\r
+} Matrix;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */\r
+#define MATRIX_MCFG_ULBT_Pos 0\r
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */\r
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))\r
+/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */\r
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */\r
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */\r
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */\r
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))\r
+#define MATRIX_SCFG_ARBT_Pos 24\r
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */\r
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))\r
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */\r
+#define MATRIX_PRAS0_M0PR_Pos 0\r
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */\r
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))\r
+#define MATRIX_PRAS0_M1PR_Pos 4\r
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */\r
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))\r
+#define MATRIX_PRAS0_M2PR_Pos 8\r
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */\r
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))\r
+#define MATRIX_PRAS0_M3PR_Pos 12\r
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */\r
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))\r
+#define MATRIX_PRAS0_M4PR_Pos 16\r
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */\r
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))\r
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */\r
+#define MATRIX_PRAS1_M0PR_Pos 0\r
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */\r
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))\r
+#define MATRIX_PRAS1_M1PR_Pos 4\r
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */\r
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))\r
+#define MATRIX_PRAS1_M2PR_Pos 8\r
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */\r
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))\r
+#define MATRIX_PRAS1_M3PR_Pos 12\r
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */\r
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))\r
+#define MATRIX_PRAS1_M4PR_Pos 16\r
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */\r
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))\r
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */\r
+#define MATRIX_PRAS2_M0PR_Pos 0\r
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */\r
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))\r
+#define MATRIX_PRAS2_M1PR_Pos 4\r
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */\r
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))\r
+#define MATRIX_PRAS2_M2PR_Pos 8\r
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */\r
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))\r
+#define MATRIX_PRAS2_M3PR_Pos 12\r
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */\r
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))\r
+#define MATRIX_PRAS2_M4PR_Pos 16\r
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */\r
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))\r
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */\r
+#define MATRIX_PRAS3_M0PR_Pos 0\r
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */\r
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))\r
+#define MATRIX_PRAS3_M1PR_Pos 4\r
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */\r
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))\r
+#define MATRIX_PRAS3_M2PR_Pos 8\r
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */\r
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))\r
+#define MATRIX_PRAS3_M3PR_Pos 12\r
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */\r
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))\r
+#define MATRIX_PRAS3_M4PR_Pos 16\r
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */\r
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))\r
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */\r
+#define MATRIX_PRAS4_M0PR_Pos 0\r
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */\r
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))\r
+#define MATRIX_PRAS4_M1PR_Pos 4\r
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */\r
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))\r
+#define MATRIX_PRAS4_M2PR_Pos 8\r
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */\r
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))\r
+#define MATRIX_PRAS4_M3PR_Pos 12\r
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */\r
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))\r
+#define MATRIX_PRAS4_M4PR_Pos 16\r
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */\r
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))\r
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */\r
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */\r
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */\r
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */\r
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */\r
+#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */\r
+#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */\r
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */\r
+/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */\r
+#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */\r
+#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */\r
+#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */\r
+#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */\r
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */\r
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */\r
+#define MATRIX_WPMR_WPKEY_Pos 8\r
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */\r
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))\r
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */\r
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */\r
+#define MATRIX_WPSR_WPVSRC_Pos 8\r
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_MATRIX_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_PDC_COMPONENT_\r
+#define _SAM3S8_PDC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_PDC Peripheral DMA Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pdc hardware registers */\r
+typedef struct {\r
+ RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */\r
+ RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */\r
+ RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */\r
+ RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */\r
+ RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */\r
+ RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */\r
+ RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */\r
+ RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */\r
+ WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */\r
+ RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */\r
+} Pdc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */\r
+#define PERIPH_RPR_RXPTR_Pos 0\r
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */\r
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))\r
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */\r
+#define PERIPH_RCR_RXCTR_Pos 0\r
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */\r
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))\r
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */\r
+#define PERIPH_TPR_TXPTR_Pos 0\r
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */\r
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))\r
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */\r
+#define PERIPH_TCR_TXCTR_Pos 0\r
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */\r
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))\r
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */\r
+#define PERIPH_RNPR_RXNPTR_Pos 0\r
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */\r
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))\r
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */\r
+#define PERIPH_RNCR_RXNCTR_Pos 0\r
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */\r
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))\r
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */\r
+#define PERIPH_TNPR_TXNPTR_Pos 0\r
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */\r
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))\r
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */\r
+#define PERIPH_TNCR_TXNCTR_Pos 0\r
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */\r
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))\r
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */\r
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */\r
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */\r
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */\r
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */\r
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */\r
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */\r
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_PDC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_PIO_COMPONENT_\r
+#define _SAM3S8_PIO_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_PIO Parallel Input/Output Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pio hardware registers */\r
+typedef struct {\r
+ WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */\r
+ WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */\r
+ RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */\r
+ RoReg Reserved1[1];\r
+ WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */\r
+ WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */\r
+ RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */\r
+ RoReg Reserved2[1];\r
+ WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */\r
+ WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */\r
+ RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */\r
+ RoReg Reserved3[1];\r
+ WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */\r
+ WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */\r
+ RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */\r
+ RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */\r
+ WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */\r
+ WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */\r
+ RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */\r
+ RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */\r
+ WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */\r
+ WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */\r
+ RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */\r
+ RoReg Reserved4[1];\r
+ WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */\r
+ WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */\r
+ RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */\r
+ RoReg Reserved5[1];\r
+ RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */\r
+ RoReg Reserved6[2];\r
+ WoReg PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */\r
+ WoReg PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */\r
+ RoReg PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */\r
+ RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */\r
+ WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */\r
+ WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */\r
+ RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */\r
+ RoReg Reserved7[1];\r
+ WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */\r
+ WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */\r
+ RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */\r
+ RoReg Reserved8[1];\r
+ WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */\r
+ WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */\r
+ RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */\r
+ RoReg Reserved9[1];\r
+ WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */\r
+ WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */\r
+ RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */\r
+ RoReg Reserved10[1];\r
+ WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */\r
+ WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */\r
+ RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */\r
+ RoReg Reserved11[1];\r
+ RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */\r
+ RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */\r
+ RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */\r
+ RoReg Reserved12[5];\r
+ RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */\r
+ RoReg Reserved13[19];\r
+ RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */\r
+ WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */\r
+ WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */\r
+ RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */\r
+ RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */\r
+ RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */\r
+ RwReg PIO_RPR; /**< \brief (Pio Offset: 0x168) Receive Pointer Register */\r
+ RwReg PIO_RCR; /**< \brief (Pio Offset: 0x16C) Receive Counter Register */\r
+ RoReg Reserved14[2];\r
+ RwReg PIO_RNPR; /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */\r
+ RwReg PIO_RNCR; /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */\r
+ RoReg Reserved15[2];\r
+ WoReg PIO_PTCR; /**< \brief (Pio Offset: 0x188) Transfer Control Register */\r
+ RoReg PIO_PTSR; /**< \brief (Pio Offset: 0x18C) Transfer Status Register */\r
+} Pio;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */\r
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */\r
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */\r
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */\r
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */\r
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */\r
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */\r
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */\r
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */\r
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */\r
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */\r
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */\r
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */\r
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */\r
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */\r
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */\r
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */\r
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */\r
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */\r
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */\r
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */\r
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */\r
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */\r
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */\r
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */\r
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */\r
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */\r
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */\r
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */\r
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */\r
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */\r
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */\r
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */\r
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */\r
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */\r
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */\r
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */\r
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */\r
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */\r
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */\r
+#define PIO_SCDR_DIV_Pos 0\r
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) */\r
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))\r
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */\r
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */\r
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */\r
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */\r
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */\r
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */\r
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */\r
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */\r
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */\r
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */\r
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */\r
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */\r
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */\r
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */\r
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */\r
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */\r
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */\r
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */\r
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */\r
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */\r
+#define PIO_WPMR_WPKEY_Pos 8\r
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */\r
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))\r
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */\r
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */\r
+#define PIO_WPSR_WPVSRC_Pos 8\r
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */\r
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */\r
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) */\r
+/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */\r
+#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */\r
+#define PIO_PCMR_DSIZE_Pos 4\r
+#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */\r
+#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a BYTE (8-bit) */\r
+#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) */\r
+#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a WORD (32-bit) */\r
+#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */\r
+#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */\r
+#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */\r
+/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */\r
+#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */\r
+#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */\r
+#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */\r
+#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */\r
+/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */\r
+#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */\r
+#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */\r
+#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */\r
+#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */\r
+/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */\r
+#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */\r
+#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */\r
+#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */\r
+#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */\r
+/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */\r
+#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */\r
+#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */\r
+#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */\r
+#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */\r
+/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */\r
+#define PIO_PCRHR_RDATA_Pos 0\r
+#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */\r
+/* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */\r
+#define PIO_RPR_RXPTR_Pos 0\r
+#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */\r
+#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos)))\r
+/* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */\r
+#define PIO_RCR_RXCTR_Pos 0\r
+#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */\r
+#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos)))\r
+/* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */\r
+#define PIO_RNPR_RXNPTR_Pos 0\r
+#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */\r
+#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos)))\r
+/* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */\r
+#define PIO_RNCR_RXNCTR_Pos 0\r
+#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */\r
+#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos)))\r
+/* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */\r
+#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */\r
+#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */\r
+#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */\r
+#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */\r
+/* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */\r
+#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */\r
+#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_PIO_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_PMC_COMPONENT_\r
+#define _SAM3S8_PMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Power Management Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_PMC Power Management Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pmc hardware registers */\r
+typedef struct {\r
+ WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */\r
+ WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */\r
+ RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */\r
+ RoReg Reserved1[1];\r
+ WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */\r
+ WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */\r
+ RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */\r
+ RoReg Reserved2[1];\r
+ RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */\r
+ RwReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */\r
+ RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */\r
+ RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */\r
+ RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */\r
+ RoReg Reserved3[1];\r
+ RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */\r
+ RoReg Reserved4[1];\r
+ RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */\r
+ RoReg Reserved5[5];\r
+ WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */\r
+ WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */\r
+ RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */\r
+ RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */\r
+ RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */\r
+ RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */\r
+ WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */\r
+ RoReg Reserved6[26];\r
+ RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */\r
+ RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */\r
+ RoReg Reserved7[5];\r
+ WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */\r
+ WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */\r
+ RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */\r
+ RoReg Reserved8[1];\r
+ RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */\r
+} Pmc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */\r
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */\r
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */\r
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */\r
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */\r
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */\r
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */\r
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */\r
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */\r
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */\r
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */\r
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */\r
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */\r
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */\r
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */\r
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */\r
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */\r
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */\r
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */\r
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */\r
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */\r
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */\r
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */\r
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */\r
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */\r
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */\r
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */\r
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */\r
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */\r
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */\r
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */\r
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */\r
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */\r
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */\r
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */\r
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */\r
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */\r
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */\r
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */\r
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */\r
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */\r
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */\r
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */\r
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */\r
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */\r
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */\r
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */\r
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */\r
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */\r
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */\r
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */\r
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */\r
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */\r
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */\r
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */\r
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */\r
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */\r
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */\r
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */\r
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */\r
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */\r
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */\r
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */\r
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */\r
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */\r
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */\r
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */\r
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */\r
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */\r
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */\r
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */\r
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */\r
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */\r
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */\r
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */\r
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */\r
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */\r
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */\r
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */\r
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */\r
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */\r
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */\r
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */\r
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */\r
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */\r
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */\r
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */\r
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */\r
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */\r
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */\r
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */\r
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */\r
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */\r
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */\r
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */\r
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */\r
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */\r
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */\r
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */\r
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */\r
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */\r
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */\r
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */\r
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */\r
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */\r
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */\r
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */\r
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */\r
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */\r
+#define CKGR_MOR_MOSCRCF_Pos 4\r
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */\r
+#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */\r
+#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */\r
+#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */\r
+#define CKGR_MOR_MOSCXTST_Pos 8\r
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */\r
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))\r
+#define CKGR_MOR_KEY_Pos 16\r
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */\r
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))\r
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */\r
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */\r
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */\r
+#define CKGR_MCFR_MAINF_Pos 0\r
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */\r
+#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))\r
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */\r
+#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */\r
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */\r
+#define CKGR_PLLAR_DIVA_Pos 0\r
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */\r
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))\r
+#define CKGR_PLLAR_PLLACOUNT_Pos 8\r
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */\r
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))\r
+#define CKGR_PLLAR_MULA_Pos 16\r
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */\r
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))\r
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */\r
+/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */\r
+#define CKGR_PLLBR_DIVB_Pos 0\r
+#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */\r
+#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos)))\r
+#define CKGR_PLLBR_PLLBCOUNT_Pos 8\r
+#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */\r
+#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos)))\r
+#define CKGR_PLLBR_MULB_Pos 16\r
+#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */\r
+#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos)))\r
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */\r
+#define PMC_MCKR_CSS_Pos 0\r
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */\r
+#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */\r
+#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */\r
+#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */\r
+#define PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */\r
+#define PMC_MCKR_PRES_Pos 4\r
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */\r
+#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */\r
+#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */\r
+#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */\r
+#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */\r
+#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */\r
+#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */\r
+#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */\r
+#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */\r
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */\r
+#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */\r
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */\r
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */\r
+#define PMC_USB_USBDIV_Pos 8\r
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */\r
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))\r
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */\r
+#define PMC_PCK_CSS_Pos 0\r
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */\r
+#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */\r
+#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */\r
+#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */\r
+#define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */\r
+#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */\r
+#define PMC_PCK_PRES_Pos 4\r
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */\r
+#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */\r
+#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */\r
+#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */\r
+#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */\r
+#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */\r
+#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */\r
+#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */\r
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */\r
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */\r
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */\r
+#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */\r
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */\r
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */\r
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */\r
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */\r
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */\r
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */\r
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */\r
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */\r
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */\r
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */\r
+#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */\r
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */\r
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */\r
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */\r
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */\r
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */\r
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */\r
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */\r
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */\r
+#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */\r
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */\r
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */\r
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */\r
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */\r
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */\r
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */\r
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */\r
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */\r
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */\r
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */\r
+#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */\r
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */\r
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */\r
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */\r
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */\r
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */\r
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */\r
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */\r
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */\r
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */\r
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */\r
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */\r
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */\r
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */\r
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */\r
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */\r
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */\r
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */\r
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */\r
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */\r
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */\r
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */\r
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */\r
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */\r
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */\r
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */\r
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */\r
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */\r
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */\r
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */\r
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */\r
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */\r
+#define PMC_WPMR_WPKEY_Pos 8\r
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */\r
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))\r
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */\r
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */\r
+#define PMC_WPSR_WPVSRC_Pos 8\r
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */\r
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */\r
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */\r
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */\r
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */\r
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */\r
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */\r
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */\r
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */\r
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */\r
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */\r
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */\r
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */\r
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */\r
+#define PMC_OCR_CAL4_Pos 0\r
+#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */\r
+#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))\r
+#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */\r
+#define PMC_OCR_CAL8_Pos 8\r
+#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */\r
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))\r
+#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */\r
+#define PMC_OCR_CAL12_Pos 16\r
+#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */\r
+#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))\r
+#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_PMC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_PWM_COMPONENT_\r
+#define _SAM3S8_PWM_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_PWM Pulse Width Modulation Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief PwmCh_num hardware registers */\r
+typedef struct {\r
+ RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */\r
+ RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */\r
+ RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */\r
+ RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */\r
+ RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */\r
+ RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */\r
+ RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */\r
+ RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */\r
+} PwmCh_num;\r
+/** \brief PwmCmp hardware registers */\r
+typedef struct {\r
+ RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */\r
+ RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */\r
+ RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */\r
+ RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */\r
+} PwmCmp;\r
+/** \brief Pwm hardware registers */\r
+#define PWMCMP_NUMBER 8\r
+#define PWMCH_NUM_NUMBER 4\r
+typedef struct {\r
+ RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */\r
+ WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */\r
+ WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */\r
+ RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */\r
+ WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */\r
+ WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */\r
+ RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */\r
+ RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */\r
+ RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */\r
+ RoReg Reserved1[1];\r
+ RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */\r
+ RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */\r
+ WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */\r
+ WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */\r
+ WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */\r
+ RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */\r
+ RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */\r
+ RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */\r
+ RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */\r
+ WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */\r
+ WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */\r
+ WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */\r
+ WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */\r
+ RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */\r
+ RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */\r
+ WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */\r
+ RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */\r
+ RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */\r
+ RoReg Reserved2[3];\r
+ RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */\r
+ RoReg Reserved3[11];\r
+ RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */\r
+ RoReg Reserved4[12];\r
+ WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */\r
+ RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */\r
+ RoReg Reserved5[7];\r
+ RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */\r
+ RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */\r
+ RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */\r
+ RoReg Reserved7[2];\r
+ PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */\r
+ RoReg Reserved8[20];\r
+ PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */\r
+} Pwm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */\r
+#define PWM_CLK_DIVA_Pos 0\r
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */\r
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))\r
+#define PWM_CLK_PREA_Pos 8\r
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */\r
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))\r
+#define PWM_CLK_DIVB_Pos 16\r
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */\r
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))\r
+#define PWM_CLK_PREB_Pos 24\r
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */\r
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))\r
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */\r
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */\r
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */\r
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */\r
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */\r
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */\r
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */\r
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */\r
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */\r
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */\r
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */\r
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */\r
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */\r
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */\r
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */\r
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */\r
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */\r
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */\r
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */\r
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */\r
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */\r
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */\r
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */\r
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */\r
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */\r
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */\r
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */\r
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */\r
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */\r
+#define PWM_SCM_UPDM_Pos 16\r
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */\r
+#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */\r
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */\r
+#define PWM_SCM_PTRCS_Pos 21\r
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */\r
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))\r
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */\r
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */\r
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */\r
+#define PWM_SCUP_UPR_Pos 0\r
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */\r
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))\r
+#define PWM_SCUP_UPRCNT_Pos 4\r
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */\r
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))\r
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */\r
+#define PWM_SCUPUPD_UPRUPD_Pos 0\r
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */\r
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))\r
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */\r
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */\r
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */\r
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */\r
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */\r
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */\r
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */\r
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */\r
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */\r
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */\r
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */\r
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */\r
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */\r
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */\r
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */\r
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */\r
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */\r
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */\r
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */\r
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */\r
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */\r
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */\r
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */\r
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */\r
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */\r
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */\r
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */\r
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */\r
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */\r
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */\r
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */\r
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */\r
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */\r
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */\r
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */\r
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */\r
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */\r
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */\r
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */\r
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */\r
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */\r
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */\r
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */\r
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */\r
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */\r
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */\r
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */\r
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */\r
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */\r
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */\r
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */\r
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */\r
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */\r
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */\r
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */\r
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */\r
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */\r
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */\r
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */\r
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */\r
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */\r
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */\r
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */\r
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */\r
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */\r
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */\r
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */\r
+#define PWM_FMR_FPOL_Pos 0\r
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */\r
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))\r
+#define PWM_FMR_FMOD_Pos 8\r
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */\r
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))\r
+#define PWM_FMR_FFIL_Pos 16\r
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */\r
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))\r
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */\r
+#define PWM_FSR_FIV_Pos 0\r
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */\r
+#define PWM_FSR_FS_Pos 8\r
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */\r
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */\r
+#define PWM_FCR_FCLR_Pos 0\r
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */\r
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))\r
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */\r
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */\r
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */\r
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */\r
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */\r
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */\r
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */\r
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */\r
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */\r
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */\r
+#define PWM_FPE_FPE0_Pos 0\r
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))\r
+#define PWM_FPE_FPE1_Pos 8\r
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))\r
+#define PWM_FPE_FPE2_Pos 16\r
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))\r
+#define PWM_FPE_FPE3_Pos 24\r
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))\r
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */\r
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */\r
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */\r
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */\r
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */\r
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */\r
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */\r
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */\r
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */\r
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */\r
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */\r
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */\r
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */\r
+#define PWM_WPCR_WPCMD_Pos 0\r
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */\r
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))\r
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */\r
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */\r
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */\r
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */\r
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */\r
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */\r
+#define PWM_WPCR_WPKEY_Pos 8\r
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */\r
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))\r
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */\r
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */\r
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPVSRC_Pos 16\r
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */\r
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */\r
+#define PWM_TPR_TXPTR_Pos 0\r
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */\r
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))\r
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */\r
+#define PWM_TCR_TXCTR_Pos 0\r
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */\r
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))\r
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define PWM_TNPR_TXNPTR_Pos 0\r
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */\r
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))\r
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define PWM_TNCR_TXNCTR_Pos 0\r
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */\r
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))\r
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */\r
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */\r
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */\r
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */\r
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */\r
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */\r
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */\r
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */\r
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */\r
+#define PWM_CMPV_CV_Pos 0\r
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */\r
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))\r
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */\r
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */\r
+#define PWM_CMPVUPD_CVUPD_Pos 0\r
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */\r
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))\r
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */\r
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */\r
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */\r
+#define PWM_CMPM_CTR_Pos 4\r
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */\r
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))\r
+#define PWM_CMPM_CPR_Pos 8\r
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */\r
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))\r
+#define PWM_CMPM_CPRCNT_Pos 12\r
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */\r
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))\r
+#define PWM_CMPM_CUPR_Pos 16\r
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */\r
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))\r
+#define PWM_CMPM_CUPRCNT_Pos 20\r
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */\r
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))\r
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */\r
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */\r
+#define PWM_CMPMUPD_CTRUPD_Pos 4\r
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */\r
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))\r
+#define PWM_CMPMUPD_CPRUPD_Pos 8\r
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */\r
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))\r
+#define PWM_CMPMUPD_CUPRUPD_Pos 16\r
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */\r
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))\r
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */\r
+#define PWM_CMR_CPRE_Pos 0\r
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */\r
+#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */\r
+#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */\r
+#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */\r
+#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */\r
+#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */\r
+#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */\r
+#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */\r
+#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */\r
+#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */\r
+#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */\r
+#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */\r
+#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */\r
+#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */\r
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */\r
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */\r
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */\r
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */\r
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */\r
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */\r
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */\r
+#define PWM_CDTY_CDTY_Pos 0\r
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */\r
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))\r
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */\r
+#define PWM_CDTYUPD_CDTYUPD_Pos 0\r
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */\r
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))\r
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */\r
+#define PWM_CPRD_CPRD_Pos 0\r
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */\r
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))\r
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */\r
+#define PWM_CPRDUPD_CPRDUPD_Pos 0\r
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */\r
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))\r
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */\r
+#define PWM_CCNT_CNT_Pos 0\r
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */\r
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */\r
+#define PWM_DT_DTH_Pos 0\r
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */\r
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))\r
+#define PWM_DT_DTL_Pos 16\r
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */\r
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))\r
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */\r
+#define PWM_DTUPD_DTHUPD_Pos 0\r
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */\r
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))\r
+#define PWM_DTUPD_DTLUPD_Pos 16\r
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */\r
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_PWM_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_RSTC_COMPONENT_\r
+#define _SAM3S8_RSTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Reset Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_RSTC Reset Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rstc hardware registers */\r
+typedef struct {\r
+ WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */\r
+ RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */\r
+ RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */\r
+} Rstc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */\r
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */\r
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */\r
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */\r
+#define RSTC_CR_KEY_Pos 24\r
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */\r
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))\r
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */\r
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */\r
+#define RSTC_SR_RSTTYP_Pos 8\r
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */\r
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */\r
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */\r
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */\r
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */\r
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */\r
+#define RSTC_MR_ERSTL_Pos 8\r
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */\r
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))\r
+#define RSTC_MR_KEY_Pos 24\r
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */\r
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_RSTC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_RTC_COMPONENT_\r
+#define _SAM3S8_RTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Clock */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_RTC Real-time Clock */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rtc hardware registers */\r
+typedef struct {\r
+ RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */\r
+ RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */\r
+ RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */\r
+ RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */\r
+ RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */\r
+ RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */\r
+ RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */\r
+ WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */\r
+ WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */\r
+ WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */\r
+ RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */\r
+ RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */\r
+} Rtc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */\r
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */\r
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */\r
+#define RTC_CR_TIMEVSEL_Pos 8\r
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */\r
+#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */\r
+#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */\r
+#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */\r
+#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */\r
+#define RTC_CR_CALEVSEL_Pos 16\r
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */\r
+#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */\r
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */\r
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */\r
+#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */\r
+#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */\r
+#define RTC_MR_CORRECTION_Pos 8\r
+#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) */\r
+#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))\r
+#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */\r
+#define RTC_MR_OUT0_Pos 16\r
+#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 Output Source Selection */\r
+#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) no waveform, stuck at '0' */\r
+#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */\r
+#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) output toggles when alarm flag rises */\r
+#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) output is a copy of the alarm flag */\r
+#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) duty cycle programmable pulse */\r
+#define RTC_MR_OUT1_Pos 20\r
+#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */\r
+#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) no waveform, stuck at '0' */\r
+#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */\r
+#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) output toggles when alarm flag rises */\r
+#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) output is a copy of the alarm flag */\r
+#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) duty cycle programmable pulse */\r
+#define RTC_MR_THIGH_Pos 24\r
+#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */\r
+#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */\r
+#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */\r
+#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */\r
+#define RTC_MR_THIGH_H_967US (0x3u << 24) /**< \brief (RTC_MR) 967 \xb5 s */\r
+#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 \xb5 s */\r
+#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 \xb5 s */\r
+#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 \xb5 s */\r
+#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 \xb5 s */\r
+#define RTC_MR_TPERIOD_Pos 28\r
+#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */\r
+#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */\r
+#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */\r
+#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */\r
+#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */\r
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */\r
+#define RTC_TIMR_SEC_Pos 0\r
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */\r
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))\r
+#define RTC_TIMR_MIN_Pos 8\r
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */\r
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))\r
+#define RTC_TIMR_HOUR_Pos 16\r
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */\r
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))\r
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */\r
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */\r
+#define RTC_CALR_CENT_Pos 0\r
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */\r
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))\r
+#define RTC_CALR_YEAR_Pos 8\r
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */\r
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))\r
+#define RTC_CALR_MONTH_Pos 16\r
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */\r
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))\r
+#define RTC_CALR_DAY_Pos 21\r
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */\r
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))\r
+#define RTC_CALR_DATE_Pos 24\r
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */\r
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))\r
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */\r
+#define RTC_TIMALR_SEC_Pos 0\r
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */\r
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))\r
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */\r
+#define RTC_TIMALR_MIN_Pos 8\r
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */\r
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))\r
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */\r
+#define RTC_TIMALR_HOUR_Pos 16\r
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */\r
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))\r
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */\r
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */\r
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */\r
+#define RTC_CALALR_MONTH_Pos 16\r
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */\r
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))\r
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */\r
+#define RTC_CALALR_DATE_Pos 24\r
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */\r
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))\r
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */\r
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */\r
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */\r
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */\r
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */\r
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */\r
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */\r
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */\r
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */\r
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */\r
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */\r
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */\r
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */\r
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */\r
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */\r
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */\r
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */\r
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */\r
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */\r
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */\r
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */\r
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */\r
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */\r
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */\r
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */\r
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */\r
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */\r
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */\r
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */\r
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */\r
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */\r
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */\r
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */\r
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */\r
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */\r
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_RTC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_RTT_COMPONENT_\r
+#define _SAM3S8_RTT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_RTT Real-time Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rtt hardware registers */\r
+typedef struct {\r
+ RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */\r
+ RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */\r
+ RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */\r
+ RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */\r
+} Rtt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */\r
+#define RTT_MR_RTPRES_Pos 0\r
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */\r
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))\r
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */\r
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */\r
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */\r
+#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */\r
+#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */\r
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */\r
+#define RTT_AR_ALMV_Pos 0\r
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */\r
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))\r
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */\r
+#define RTT_VR_CRTV_Pos 0\r
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */\r
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */\r
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */\r
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_RTT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_SMC_COMPONENT_\r
+#define _SAM3S8_SMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Static Memory Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_SMC Static Memory Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief SmcCs_number hardware registers */\r
+typedef struct {\r
+ RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */\r
+ RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */\r
+ RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */\r
+ RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */\r
+} SmcCs_number;\r
+/** \brief Smc hardware registers */\r
+#define SMCCS_NUMBER_NUMBER 5\r
+typedef struct {\r
+ SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */\r
+ RoReg Reserved1[12];\r
+ RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */\r
+ WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */\r
+ WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */\r
+ RoReg Reserved2[22];\r
+ RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */\r
+ RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */\r
+} Smc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */\r
+#define SMC_SETUP_NWE_SETUP_Pos 0\r
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */\r
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))\r
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8\r
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */\r
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))\r
+#define SMC_SETUP_NRD_SETUP_Pos 16\r
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */\r
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))\r
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24\r
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */\r
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))\r
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */\r
+#define SMC_PULSE_NWE_PULSE_Pos 0\r
+#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */\r
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))\r
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8\r
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */\r
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))\r
+#define SMC_PULSE_NRD_PULSE_Pos 16\r
+#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */\r
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))\r
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24\r
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */\r
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))\r
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */\r
+#define SMC_CYCLE_NWE_CYCLE_Pos 0\r
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */\r
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))\r
+#define SMC_CYCLE_NRD_CYCLE_Pos 16\r
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */\r
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))\r
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */\r
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */\r
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */\r
+#define SMC_MODE_EXNW_MODE_Pos 4\r
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */\r
+#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */\r
+#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */\r
+#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */\r
+#define SMC_MODE_DBW_Pos 12\r
+#define SMC_MODE_DBW_Msk (0x3u << SMC_MODE_DBW_Pos) /**< \brief (SMC_MODE) Data Bus Width */\r
+#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */\r
+#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */\r
+#define SMC_MODE_DBW_32_BIT (0x2u << 12) /**< \brief (SMC_MODE) 32-bit bus */\r
+#define SMC_MODE_TDF_CYCLES_Pos 16\r
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */\r
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))\r
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */\r
+#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */\r
+#define SMC_MODE_PS_Pos 28\r
+#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */\r
+#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */\r
+#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */\r
+#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */\r
+#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */\r
+/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */\r
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */\r
+#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */\r
+#define SMC_KEY1_KEY1_Pos 0\r
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */\r
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))\r
+/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */\r
+#define SMC_KEY2_KEY2_Pos 0\r
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */\r
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))\r
+/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */\r
+#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */\r
+#define SMC_WPMR_WPKEY_Pos 8\r
+#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */\r
+#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))\r
+/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */\r
+#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */\r
+#define SMC_WPSR_WPVSRC_Pos 8\r
+#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_SMC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_SPI_COMPONENT_\r
+#define _SAM3S8_SPI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_SPI Serial Peripheral Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Spi hardware registers */\r
+typedef struct {\r
+ WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */\r
+ RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */\r
+ RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */\r
+ WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */\r
+ RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */\r
+ WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */\r
+ WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */\r
+ RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */\r
+ RoReg Reserved1[4];\r
+ RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */\r
+ RoReg Reserved2[41];\r
+ RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */\r
+ RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */\r
+ RoReg Reserved3[5];\r
+ RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */\r
+ RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */\r
+ RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */\r
+ RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */\r
+ RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */\r
+ RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */\r
+ RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */\r
+} Spi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */\r
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */\r
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */\r
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */\r
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */\r
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */\r
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */\r
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */\r
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */\r
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */\r
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */\r
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */\r
+#define SPI_MR_PCS_Pos 16\r
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */\r
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))\r
+#define SPI_MR_DLYBCS_Pos 24\r
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */\r
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))\r
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */\r
+#define SPI_RDR_RD_Pos 0\r
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_PCS_Pos 16\r
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */\r
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */\r
+#define SPI_TDR_TD_Pos 0\r
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))\r
+#define SPI_TDR_PCS_Pos 16\r
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */\r
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))\r
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */\r
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */\r
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */\r
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */\r
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */\r
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */\r
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */\r
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */\r
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */\r
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */\r
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */\r
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */\r
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */\r
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */\r
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */\r
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */\r
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */\r
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */\r
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */\r
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */\r
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */\r
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */\r
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */\r
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */\r
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */\r
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */\r
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */\r
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */\r
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */\r
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */\r
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */\r
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */\r
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */\r
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */\r
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */\r
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */\r
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */\r
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */\r
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */\r
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */\r
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */\r
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */\r
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */\r
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */\r
+#define SPI_CSR_BITS_Pos 4\r
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */\r
+#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */\r
+#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */\r
+#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */\r
+#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */\r
+#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */\r
+#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */\r
+#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */\r
+#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */\r
+#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */\r
+#define SPI_CSR_SCBR_Pos 8\r
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */\r
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))\r
+#define SPI_CSR_DLYBS_Pos 16\r
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */\r
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))\r
+#define SPI_CSR_DLYBCT_Pos 24\r
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */\r
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))\r
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */\r
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */\r
+#define SPI_WPMR_WPKEY_Pos 8\r
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */\r
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))\r
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */\r
+#define SPI_WPSR_WPVS_Pos 0\r
+#define SPI_WPSR_WPVS_Msk (0x1u << SPI_WPSR_WPVS_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Status */\r
+#define SPI_WPSR_WPVSRC_Pos 8\r
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */\r
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */\r
+#define SPI_RPR_RXPTR_Pos 0\r
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */\r
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))\r
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */\r
+#define SPI_RCR_RXCTR_Pos 0\r
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */\r
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))\r
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */\r
+#define SPI_TPR_TXPTR_Pos 0\r
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */\r
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))\r
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */\r
+#define SPI_TCR_TXCTR_Pos 0\r
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */\r
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))\r
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define SPI_RNPR_RXNPTR_Pos 0\r
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */\r
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))\r
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */\r
+#define SPI_RNCR_RXNCTR_Pos 0\r
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */\r
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))\r
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define SPI_TNPR_TXNPTR_Pos 0\r
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */\r
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))\r
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define SPI_TNCR_TXNCTR_Pos 0\r
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */\r
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))\r
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */\r
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */\r
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */\r
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */\r
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */\r
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */\r
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */\r
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_SPI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_SSC_COMPONENT_\r
+#define _SAM3S8_SSC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_SSC Synchronous Serial Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Ssc hardware registers */\r
+typedef struct {\r
+ WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */\r
+ RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */\r
+ RoReg Reserved1[2];\r
+ RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */\r
+ RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */\r
+ RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */\r
+ RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */\r
+ RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */\r
+ WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */\r
+ RoReg Reserved2[2];\r
+ RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */\r
+ RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */\r
+ RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */\r
+ RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */\r
+ RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */\r
+ WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */\r
+ WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */\r
+ RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */\r
+ RoReg Reserved3[37];\r
+ RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved4[5];\r
+ RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */\r
+ RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */\r
+ RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */\r
+ RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */\r
+ RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */\r
+ RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */\r
+ RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */\r
+} Ssc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */\r
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */\r
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */\r
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */\r
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */\r
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */\r
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */\r
+#define SSC_CMR_DIV_Pos 0\r
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */\r
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))\r
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */\r
+#define SSC_RCMR_CKS_Pos 0\r
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */\r
+#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */\r
+#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */\r
+#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */\r
+#define SSC_RCMR_CKO_Pos 2\r
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */\r
+#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */\r
+#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */\r
+#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */\r
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */\r
+#define SSC_RCMR_CKG_Pos 6\r
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */\r
+#define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */\r
+#define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */\r
+#define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */\r
+#define SSC_RCMR_START_Pos 8\r
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */\r
+#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */\r
+#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */\r
+#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */\r
+#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */\r
+#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */\r
+#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */\r
+#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */\r
+#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */\r
+#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */\r
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */\r
+#define SSC_RCMR_STTDLY_Pos 16\r
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */\r
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))\r
+#define SSC_RCMR_PERIOD_Pos 24\r
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */\r
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))\r
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */\r
+#define SSC_RFMR_DATLEN_Pos 0\r
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */\r
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))\r
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */\r
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */\r
+#define SSC_RFMR_DATNB_Pos 8\r
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */\r
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))\r
+#define SSC_RFMR_FSLEN_Pos 16\r
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */\r
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))\r
+#define SSC_RFMR_FSOS_Pos 20\r
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */\r
+#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */\r
+#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */\r
+#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */\r
+#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */\r
+#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */\r
+#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */\r
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */\r
+#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */\r
+#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */\r
+#define SSC_RFMR_FSLEN_EXT_Pos 28\r
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */\r
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))\r
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */\r
+#define SSC_TCMR_CKS_Pos 0\r
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */\r
+#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */\r
+#define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */\r
+#define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */\r
+#define SSC_TCMR_CKO_Pos 2\r
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */\r
+#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */\r
+#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */\r
+#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */\r
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */\r
+#define SSC_TCMR_CKG_Pos 6\r
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */\r
+#define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */\r
+#define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */\r
+#define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */\r
+#define SSC_TCMR_START_Pos 8\r
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */\r
+#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */\r
+#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */\r
+#define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */\r
+#define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */\r
+#define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */\r
+#define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */\r
+#define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */\r
+#define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */\r
+#define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */\r
+#define SSC_TCMR_STTDLY_Pos 16\r
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */\r
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))\r
+#define SSC_TCMR_PERIOD_Pos 24\r
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */\r
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))\r
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */\r
+#define SSC_TFMR_DATLEN_Pos 0\r
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */\r
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))\r
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */\r
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */\r
+#define SSC_TFMR_DATNB_Pos 8\r
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */\r
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))\r
+#define SSC_TFMR_FSLEN_Pos 16\r
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */\r
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))\r
+#define SSC_TFMR_FSOS_Pos 20\r
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */\r
+#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */\r
+#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */\r
+#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */\r
+#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */\r
+#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */\r
+#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */\r
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */\r
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */\r
+#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */\r
+#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */\r
+#define SSC_TFMR_FSLEN_EXT_Pos 28\r
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */\r
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))\r
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */\r
+#define SSC_RHR_RDAT_Pos 0\r
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */\r
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */\r
+#define SSC_THR_TDAT_Pos 0\r
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */\r
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))\r
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */\r
+#define SSC_RSHR_RSDAT_Pos 0\r
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */\r
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */\r
+#define SSC_TSHR_TSDAT_Pos 0\r
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */\r
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))\r
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */\r
+#define SSC_RC0R_CP0_Pos 0\r
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */\r
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))\r
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */\r
+#define SSC_RC1R_CP1_Pos 0\r
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */\r
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))\r
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */\r
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */\r
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */\r
+#define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */\r
+#define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */\r
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */\r
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */\r
+#define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */\r
+#define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) Receive Buffer Full */\r
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */\r
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */\r
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */\r
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */\r
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */\r
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */\r
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */\r
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */\r
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */\r
+#define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */\r
+#define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */\r
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */\r
+#define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */\r
+#define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */\r
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */\r
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */\r
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */\r
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */\r
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */\r
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */\r
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */\r
+#define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */\r
+#define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */\r
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */\r
+#define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */\r
+#define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */\r
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */\r
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */\r
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */\r
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */\r
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */\r
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */\r
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */\r
+#define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */\r
+#define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */\r
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */\r
+#define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */\r
+#define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */\r
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */\r
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */\r
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */\r
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */\r
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */\r
+#define SSC_WPMR_WPKEY_Pos 8\r
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */\r
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))\r
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */\r
+#define SSC_WPSR_WPVSRC_Pos 8\r
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */\r
+/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */\r
+#define SSC_RPR_RXPTR_Pos 0\r
+#define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */\r
+#define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos)))\r
+/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */\r
+#define SSC_RCR_RXCTR_Pos 0\r
+#define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */\r
+#define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos)))\r
+/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */\r
+#define SSC_TPR_TXPTR_Pos 0\r
+#define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */\r
+#define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos)))\r
+/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */\r
+#define SSC_TCR_TXCTR_Pos 0\r
+#define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */\r
+#define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos)))\r
+/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define SSC_RNPR_RXNPTR_Pos 0\r
+#define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */\r
+#define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos)))\r
+/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */\r
+#define SSC_RNCR_RXNCTR_Pos 0\r
+#define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */\r
+#define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos)))\r
+/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define SSC_TNPR_TXNPTR_Pos 0\r
+#define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */\r
+#define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos)))\r
+/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define SSC_TNCR_TXNCTR_Pos 0\r
+#define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */\r
+#define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos)))\r
+/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */\r
+#define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */\r
+#define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */\r
+#define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */\r
+#define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */\r
+/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */\r
+#define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */\r
+#define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_SSC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_SUPC_COMPONENT_\r
+#define _SAM3S8_SUPC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Supply Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_SUPC Supply Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Supc hardware registers */\r
+typedef struct {\r
+ WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */\r
+ RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */\r
+ RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */\r
+ RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */\r
+ RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */\r
+ RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */\r
+} Supc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */\r
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */\r
+#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */\r
+#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */\r
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */\r
+#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */\r
+#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */\r
+#define SUPC_CR_KEY_Pos 24\r
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */\r
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))\r
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */\r
+#define SUPC_SMMR_SMTH_Pos 0\r
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */\r
+#define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */\r
+#define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */\r
+#define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */\r
+#define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */\r
+#define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */\r
+#define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */\r
+#define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */\r
+#define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */\r
+#define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */\r
+#define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */\r
+#define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */\r
+#define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */\r
+#define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */\r
+#define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */\r
+#define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */\r
+#define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */\r
+#define SUPC_SMMR_SMSMPL_Pos 8\r
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */\r
+#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */\r
+#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */\r
+#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */\r
+#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */\r
+#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */\r
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */\r
+#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */\r
+#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */\r
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */\r
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */\r
+#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */\r
+#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */\r
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */\r
+#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */\r
+#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */\r
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */\r
+#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */\r
+#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */\r
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */\r
+#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */\r
+#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */\r
+#define SUPC_MR_KEY_Pos 24\r
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */\r
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))\r
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */\r
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */\r
+#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */\r
+#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */\r
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */\r
+#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */\r
+#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */\r
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */\r
+#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */\r
+#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */\r
+#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP0 */\r
+#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is not connected with low power debouncer. */\r
+#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is connected with low power debouncer and can force a core wake up. */\r
+#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP1 */\r
+#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) the WKUP1input pin is not connected with low power debouncer. */\r
+#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) the WKUP1 input pin is connected with low power debouncer and can force a core wake up. */\r
+#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low power Debouncer Clear */\r
+#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) a low power debounce event does not create an immediate clear on first half GPBR registers. */\r
+#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers. */\r
+#define SUPC_WUMR_WKUPDBC_Pos 12\r
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */\r
+#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */\r
+#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */\r
+#define SUPC_WUMR_LPDBC_Pos 16\r
+#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low Power DeBounCer Period */\r
+#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low power debouncer. */\r
+#define SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 2 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 3 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 4 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 5 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 6 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 7 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 8 RTCOUT0 periods */\r
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */\r
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */\r
+#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */\r
+#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */\r
+#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */\r
+#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */\r
+#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */\r
+#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */\r
+#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */\r
+#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */\r
+#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */\r
+#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */\r
+#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */\r
+#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */\r
+#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */\r
+#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */\r
+#define SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */\r
+#define SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Type 0 */\r
+#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Type 1 */\r
+#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Type 2 */\r
+#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Type 3 */\r
+#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Type 4 */\r
+#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Type 5 */\r
+#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Type 6 */\r
+#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Type 7 */\r
+#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Type 8 */\r
+#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Type 9 */\r
+#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Type 10 */\r
+#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Type 11 */\r
+#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Type 12 */\r
+#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Type 13 */\r
+#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Type 14 */\r
+#define SUPC_WUIR_WKUPT14_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Type 15 */\r
+#define SUPC_WUIR_WKUPT15_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */\r
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */\r
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */\r
+#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */\r
+#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */\r
+#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */\r
+#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */\r
+#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */\r
+#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */\r
+#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */\r
+#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */\r
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */\r
+#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */\r
+#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */\r
+#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP0 */\r
+#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP1 */\r
+#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */\r
+#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */\r
+#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */\r
+#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */\r
+#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */\r
+#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */\r
+#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */\r
+#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */\r
+#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */\r
+#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */\r
+#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */\r
+#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */\r
+#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */\r
+#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */\r
+#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */\r
+#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */\r
+#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_SUPC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_TC_COMPONENT_\r
+#define _SAM3S8_TC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Timer Counter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_TC Timer Counter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief TcChannel hardware registers */\r
+typedef struct {\r
+ RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */\r
+ RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */\r
+ RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */\r
+ RoReg Reserved1[1];\r
+ RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */\r
+ RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */\r
+ RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */\r
+ RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */\r
+ RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */\r
+ RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */\r
+ RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */\r
+ RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg Reserved2[4];\r
+} TcChannel;\r
+/** \brief Tc hardware registers */\r
+#define TCCHANNEL_NUMBER 3\r
+typedef struct {\r
+ TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */\r
+ WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */\r
+ RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */\r
+ WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */\r
+ WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */\r
+ RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */\r
+ RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */\r
+ RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */\r
+ RoReg Reserved1[2];\r
+ RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */\r
+} Tc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */\r
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */\r
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */\r
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */\r
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */\r
+#define TC_CMR_TCCLKS_Pos 0\r
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */\r
+#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */\r
+#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */\r
+#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */\r
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */\r
+#define TC_CMR_BURST_Pos 4\r
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */\r
+#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */\r
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */\r
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */\r
+#define TC_CMR_ETRGEDG_Pos 8\r
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */\r
+#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */\r
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */\r
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */\r
+#define TC_CMR_LDRA_Pos 16\r
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */\r
+#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_LDRB_Pos 18\r
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */\r
+#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */\r
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */\r
+#define TC_CMR_EEVTEDG_Pos 8\r
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */\r
+#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_EEVT_Pos 10\r
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */\r
+#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */\r
+#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */\r
+#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */\r
+#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */\r
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */\r
+#define TC_CMR_WAVSEL_Pos 13\r
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */\r
+#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */\r
+#define TC_CMR_ACPA_Pos 16\r
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */\r
+#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ACPC_Pos 18\r
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */\r
+#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_AEEVT_Pos 20\r
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */\r
+#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ASWTRG_Pos 22\r
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */\r
+#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPB_Pos 24\r
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */\r
+#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPC_Pos 26\r
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */\r
+#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BEEVT_Pos 28\r
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */\r
+#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BSWTRG_Pos 30\r
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */\r
+#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */\r
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */\r
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */\r
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */\r
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */\r
+#define TC_CV_CV_Pos 0\r
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */\r
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */\r
+#define TC_RA_RA_Pos 0\r
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */\r
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))\r
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */\r
+#define TC_RB_RB_Pos 0\r
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */\r
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))\r
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */\r
+#define TC_RC_RC_Pos 0\r
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */\r
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))\r
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */\r
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */\r
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */\r
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */\r
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */\r
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */\r
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */\r
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */\r
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */\r
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */\r
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */\r
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */\r
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */\r
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */\r
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */\r
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */\r
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */\r
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */\r
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */\r
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */\r
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */\r
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */\r
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */\r
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */\r
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */\r
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */\r
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */\r
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */\r
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */\r
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */\r
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */\r
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */\r
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */\r
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */\r
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */\r
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */\r
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */\r
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */\r
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */\r
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */\r
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */\r
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */\r
+#define TC_BMR_TC0XC0S_Pos 0\r
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */\r
+#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */\r
+#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */\r
+#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */\r
+#define TC_BMR_TC1XC1S_Pos 2\r
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */\r
+#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */\r
+#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */\r
+#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */\r
+#define TC_BMR_TC2XC2S_Pos 4\r
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */\r
+#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */\r
+#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */\r
+#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */\r
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */\r
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */\r
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */\r
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */\r
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */\r
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */\r
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */\r
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */\r
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */\r
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */\r
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */\r
+#define TC_BMR_MAXFILT_Pos 20\r
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */\r
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))\r
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */\r
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */\r
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */\r
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */\r
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */\r
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */\r
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */\r
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */\r
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */\r
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */\r
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */\r
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */\r
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */\r
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */\r
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */\r
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */\r
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */\r
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */\r
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */\r
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */\r
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */\r
+#define TC_WPMR_WPKEY_Pos 8\r
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */\r
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_TC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_TWI_COMPONENT_\r
+#define _SAM3S8_TWI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Two-wire Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_TWI Two-wire Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Twi hardware registers */\r
+typedef struct {\r
+ WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */\r
+ RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */\r
+ RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */\r
+ RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */\r
+ RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */\r
+ RoReg Reserved1[3];\r
+ RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */\r
+ WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */\r
+ WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */\r
+ RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */\r
+ WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */\r
+ RoReg Reserved2[50];\r
+ RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */\r
+ RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */\r
+ RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */\r
+ RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */\r
+ RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */\r
+ RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */\r
+ RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */\r
+} Twi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */\r
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */\r
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */\r
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */\r
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */\r
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */\r
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */\r
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */\r
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */\r
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */\r
+#define TWI_MMR_IADRSZ_Pos 8\r
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */\r
+#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */\r
+#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */\r
+#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */\r
+#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */\r
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */\r
+#define TWI_MMR_DADR_Pos 16\r
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */\r
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))\r
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */\r
+#define TWI_SMR_SADR_Pos 16\r
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */\r
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))\r
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */\r
+#define TWI_IADR_IADR_Pos 0\r
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */\r
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))\r
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */\r
+#define TWI_CWGR_CLDIV_Pos 0\r
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */\r
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))\r
+#define TWI_CWGR_CHDIV_Pos 8\r
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */\r
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))\r
+#define TWI_CWGR_CKDIV_Pos 16\r
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */\r
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))\r
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */\r
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */\r
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */\r
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */\r
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */\r
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */\r
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */\r
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */\r
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */\r
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */\r
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */\r
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */\r
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */\r
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */\r
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */\r
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */\r
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */\r
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */\r
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */\r
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */\r
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */\r
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */\r
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */\r
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */\r
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */\r
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */\r
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */\r
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */\r
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */\r
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */\r
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */\r
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */\r
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */\r
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */\r
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */\r
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */\r
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */\r
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */\r
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */\r
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */\r
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */\r
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */\r
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */\r
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */\r
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */\r
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */\r
+#define TWI_RHR_RXDATA_Pos 0\r
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */\r
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */\r
+#define TWI_THR_TXDATA_Pos 0\r
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */\r
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))\r
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */\r
+#define TWI_RPR_RXPTR_Pos 0\r
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */\r
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))\r
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */\r
+#define TWI_RCR_RXCTR_Pos 0\r
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */\r
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))\r
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */\r
+#define TWI_TPR_TXPTR_Pos 0\r
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */\r
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))\r
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */\r
+#define TWI_TCR_TXCTR_Pos 0\r
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */\r
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))\r
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define TWI_RNPR_RXNPTR_Pos 0\r
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */\r
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))\r
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */\r
+#define TWI_RNCR_RXNCTR_Pos 0\r
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */\r
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))\r
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define TWI_TNPR_TXNPTR_Pos 0\r
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */\r
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))\r
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define TWI_TNCR_TXNCTR_Pos 0\r
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */\r
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))\r
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */\r
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */\r
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */\r
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */\r
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */\r
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */\r
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */\r
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_TWI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_UART_COMPONENT_\r
+#define _SAM3S8_UART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_UART Universal Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Uart hardware registers */\r
+typedef struct {\r
+ WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */\r
+ RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */\r
+ WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */\r
+ WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */\r
+ RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */\r
+ RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */\r
+ RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */\r
+ WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */\r
+ RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */\r
+ RoReg Reserved1[55];\r
+ RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */\r
+ RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */\r
+ RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */\r
+ RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */\r
+ RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */\r
+ RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */\r
+ RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */\r
+} Uart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */\r
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */\r
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */\r
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */\r
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */\r
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */\r
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */\r
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */\r
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */\r
+#define UART_MR_PAR_Pos 9\r
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */\r
+#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */\r
+#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */\r
+#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */\r
+#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */\r
+#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */\r
+#define UART_MR_CHMODE_Pos 14\r
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */\r
+#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */\r
+#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */\r
+#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */\r
+#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */\r
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */\r
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */\r
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */\r
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */\r
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */\r
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */\r
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */\r
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */\r
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */\r
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */\r
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */\r
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */\r
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */\r
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */\r
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */\r
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */\r
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */\r
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */\r
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */\r
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */\r
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */\r
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */\r
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */\r
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */\r
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */\r
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */\r
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */\r
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */\r
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */\r
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */\r
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */\r
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */\r
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */\r
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */\r
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */\r
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */\r
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */\r
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */\r
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */\r
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */\r
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */\r
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */\r
+#define UART_RHR_RXCHR_Pos 0\r
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */\r
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */\r
+#define UART_THR_TXCHR_Pos 0\r
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */\r
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))\r
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define UART_BRGR_CD_Pos 0\r
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */\r
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))\r
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */\r
+#define UART_RPR_RXPTR_Pos 0\r
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */\r
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))\r
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */\r
+#define UART_RCR_RXCTR_Pos 0\r
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */\r
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))\r
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */\r
+#define UART_TPR_TXPTR_Pos 0\r
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */\r
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))\r
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */\r
+#define UART_TCR_TXCTR_Pos 0\r
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */\r
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))\r
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define UART_RNPR_RXNPTR_Pos 0\r
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */\r
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))\r
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */\r
+#define UART_RNCR_RXNCTR_Pos 0\r
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */\r
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))\r
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define UART_TNPR_TXNPTR_Pos 0\r
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */\r
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))\r
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define UART_TNCR_TXNCTR_Pos 0\r
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */\r
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))\r
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */\r
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */\r
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */\r
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */\r
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */\r
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */\r
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */\r
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_UART_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_UDP_COMPONENT_\r
+#define _SAM3S8_UDP_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR USB Device Port */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_UDP USB Device Port */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Udp hardware registers */\r
+typedef struct {\r
+ RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */\r
+ RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */\r
+ RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */\r
+ RoReg Reserved1[1];\r
+ WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */\r
+ WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */\r
+ RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */\r
+ RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */\r
+ WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */\r
+ RoReg Reserved2[1];\r
+ RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */\r
+ RoReg Reserved3[1];\r
+ RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */\r
+ RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */\r
+ RoReg Reserved4[1];\r
+ RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */\r
+} Udp;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */\r
+#define UDP_FRM_NUM_FRM_NUM_Pos 0\r
+#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */\r
+#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */\r
+#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */\r
+/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */\r
+#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */\r
+#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */\r
+#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */\r
+#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT) */\r
+#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */\r
+/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */\r
+#define UDP_FADDR_FADD_Pos 0\r
+#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */\r
+#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))\r
+#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */\r
+/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */\r
+#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */\r
+#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */\r
+#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */\r
+#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */\r
+#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */\r
+#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */\r
+#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */\r
+#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */\r
+#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */\r
+#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */\r
+#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER) */\r
+#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */\r
+#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */\r
+/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */\r
+#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */\r
+#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */\r
+#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */\r
+#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */\r
+#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */\r
+#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */\r
+#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */\r
+#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */\r
+#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */\r
+#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */\r
+#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR) */\r
+#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */\r
+#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */\r
+/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */\r
+#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */\r
+#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */\r
+#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */\r
+#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */\r
+#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */\r
+#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */\r
+#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */\r
+#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */\r
+#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */\r
+#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */\r
+#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR) */\r
+#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */\r
+#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */\r
+#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */\r
+/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */\r
+#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */\r
+#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */\r
+#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */\r
+#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */\r
+#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */\r
+#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */\r
+#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */\r
+#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */\r
+#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */\r
+#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */\r
+#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR) */\r
+#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */\r
+#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */\r
+#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */\r
+/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */\r
+#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */\r
+#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */\r
+#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR) */\r
+#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */\r
+#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */\r
+#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */\r
+/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */\r
+#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */\r
+#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */\r
+#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */\r
+#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */\r
+#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */\r
+#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */\r
+#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */\r
+#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */\r
+/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */\r
+#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */\r
+#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */\r
+#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */\r
+#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */\r
+#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */\r
+#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */\r
+#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */\r
+#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */\r
+#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */\r
+#define UDP_CSR_EPTYPE_Pos 8\r
+#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */\r
+#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */\r
+#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */\r
+#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */\r
+#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */\r
+#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */\r
+#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */\r
+#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */\r
+#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */\r
+#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */\r
+#define UDP_CSR_RXBYTECNT_Pos 16\r
+#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */\r
+#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))\r
+/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */\r
+#define UDP_FDR_FIFO_DATA_Pos 0\r
+#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */\r
+#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))\r
+/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */\r
+#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */\r
+#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pullup On */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_UDP_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_USART_COMPONENT_\r
+#define _SAM3S8_USART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_USART Universal Synchronous Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Usart hardware registers */\r
+typedef struct {\r
+ WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */\r
+ RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */\r
+ WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */\r
+ WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */\r
+ RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */\r
+ RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */\r
+ RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */\r
+ WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */\r
+ RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */\r
+ RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */\r
+ RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */\r
+ RoReg Reserved1[5];\r
+ RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */\r
+ RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */\r
+ RoReg Reserved2[1];\r
+ RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */\r
+ RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */\r
+ RoReg Reserved3[36];\r
+ RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved4[4];\r
+ RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */\r
+ RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */\r
+ RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */\r
+ RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */\r
+ RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */\r
+ RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */\r
+ RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */\r
+ RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */\r
+} Usart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */\r
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */\r
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */\r
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */\r
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */\r
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */\r
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */\r
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */\r
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */\r
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */\r
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */\r
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */\r
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */\r
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */\r
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */\r
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */\r
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */\r
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */\r
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */\r
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */\r
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */\r
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */\r
+#define US_MR_USART_MODE_Pos 0\r
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) */\r
+#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */\r
+#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */\r
+#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */\r
+#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */\r
+#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */\r
+#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */\r
+#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */\r
+#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */\r
+#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */\r
+#define US_MR_USCLKS_Pos 4\r
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */\r
+#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */\r
+#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */\r
+#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */\r
+#define US_MR_CHRL_Pos 6\r
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */\r
+#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */\r
+#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */\r
+#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */\r
+#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */\r
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */\r
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */\r
+#define US_MR_PAR_Pos 9\r
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */\r
+#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */\r
+#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */\r
+#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */\r
+#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */\r
+#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */\r
+#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */\r
+#define US_MR_NBSTOP_Pos 12\r
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */\r
+#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */\r
+#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */\r
+#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */\r
+#define US_MR_CHMODE_Pos 14\r
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */\r
+#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */\r
+#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */\r
+#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */\r
+#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */\r
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */\r
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */\r
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */\r
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */\r
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */\r
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */\r
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */\r
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */\r
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */\r
+#define US_MR_MAX_ITERATION_Pos 24\r
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) */\r
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))\r
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */\r
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */\r
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */\r
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */\r
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */\r
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */\r
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */\r
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */\r
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */\r
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */\r
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */\r
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */\r
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */\r
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */\r
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */\r
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */\r
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */\r
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */\r
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */\r
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */\r
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */\r
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */\r
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */\r
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */\r
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */\r
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */\r
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */\r
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */\r
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */\r
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */\r
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */\r
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */\r
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */\r
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */\r
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */\r
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */\r
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */\r
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */\r
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */\r
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */\r
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */\r
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */\r
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */\r
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */\r
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */\r
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */\r
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */\r
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */\r
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */\r
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */\r
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */\r
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */\r
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */\r
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */\r
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */\r
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */\r
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */\r
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */\r
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */\r
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */\r
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */\r
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */\r
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */\r
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */\r
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */\r
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */\r
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */\r
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */\r
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */\r
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */\r
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */\r
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */\r
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */\r
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */\r
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */\r
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */\r
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */\r
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */\r
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */\r
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */\r
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */\r
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */\r
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */\r
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */\r
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */\r
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */\r
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */\r
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */\r
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */\r
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */\r
+#define US_RHR_RXCHR_Pos 0\r
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */\r
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */\r
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */\r
+#define US_THR_TXCHR_Pos 0\r
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))\r
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */\r
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define US_BRGR_CD_Pos 0\r
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */\r
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))\r
+#define US_BRGR_FP_Pos 16\r
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */\r
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))\r
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */\r
+#define US_RTOR_TO_Pos 0\r
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */\r
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))\r
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */\r
+#define US_TTGR_TG_Pos 0\r
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */\r
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))\r
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */\r
+#define US_FIDI_FI_DI_RATIO_Pos 0\r
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */\r
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))\r
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */\r
+#define US_NER_NB_ERRORS_Pos 0\r
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */\r
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */\r
+#define US_IF_IRDA_FILTER_Pos 0\r
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */\r
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))\r
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */\r
+#define US_MAN_TX_PL_Pos 0\r
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */\r
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))\r
+#define US_MAN_TX_PP_Pos 8\r
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */\r
+#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */\r
+#define US_MAN_RX_PL_Pos 16\r
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */\r
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))\r
+#define US_MAN_RX_PP_Pos 24\r
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */\r
+#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */\r
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN) */\r
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */\r
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */\r
+#define US_WPMR_WPKEY_Pos 8\r
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */\r
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))\r
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */\r
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */\r
+#define US_WPSR_WPVSRC_Pos 8\r
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */\r
+/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */\r
+#define US_VERSION_VERSION_Pos 0\r
+#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) */\r
+#define US_VERSION_MFN_Pos 16\r
+#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) */\r
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */\r
+#define US_RPR_RXPTR_Pos 0\r
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */\r
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))\r
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */\r
+#define US_RCR_RXCTR_Pos 0\r
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */\r
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))\r
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */\r
+#define US_TPR_TXPTR_Pos 0\r
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */\r
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))\r
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */\r
+#define US_TCR_TXCTR_Pos 0\r
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */\r
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))\r
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define US_RNPR_RXNPTR_Pos 0\r
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */\r
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))\r
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */\r
+#define US_RNCR_RXNCTR_Pos 0\r
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */\r
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))\r
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define US_TNPR_TXNPTR_Pos 0\r
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */\r
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))\r
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define US_TNCR_TXNCTR_Pos 0\r
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */\r
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))\r
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */\r
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */\r
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */\r
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */\r
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */\r
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */\r
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */\r
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_USART_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_WDT_COMPONENT_\r
+#define _SAM3S8_WDT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Watchdog Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3S8_WDT Watchdog Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Wdt hardware registers */\r
+typedef struct {\r
+ WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */\r
+ RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */\r
+ RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */\r
+} Wdt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */\r
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */\r
+#define WDT_CR_KEY_Pos 24\r
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */\r
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))\r
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */\r
+#define WDT_MR_WDV_Pos 0\r
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */\r
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))\r
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */\r
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */\r
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */\r
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */\r
+#define WDT_MR_WDD_Pos 16\r
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */\r
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))\r
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */\r
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */\r
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */\r
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */\r
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3S8_WDT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_ACC_INSTANCE_\r
+#define _SAM3S8_ACC_INSTANCE_\r
+\r
+/* ========== Register definition for ACC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_ACC_CR (0x40040000U) /**< \brief (ACC) Control Register */\r
+#define REG_ACC_MR (0x40040004U) /**< \brief (ACC) Mode Register */\r
+#define REG_ACC_IER (0x40040024U) /**< \brief (ACC) Interrupt Enable Register */\r
+#define REG_ACC_IDR (0x40040028U) /**< \brief (ACC) Interrupt Disable Register */\r
+#define REG_ACC_IMR (0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */\r
+#define REG_ACC_ISR (0x40040030U) /**< \brief (ACC) Interrupt Status Register */\r
+#define REG_ACC_ACR (0x40040094U) /**< \brief (ACC) Analog Control Register */\r
+#define REG_ACC_WPMR (0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */\r
+#define REG_ACC_WPSR (0x400400E8U) /**< \brief (ACC) Write Protect Status Register */\r
+#else\r
+#define REG_ACC_CR (*(WoReg*)0x40040000U) /**< \brief (ACC) Control Register */\r
+#define REG_ACC_MR (*(RwReg*)0x40040004U) /**< \brief (ACC) Mode Register */\r
+#define REG_ACC_IER (*(WoReg*)0x40040024U) /**< \brief (ACC) Interrupt Enable Register */\r
+#define REG_ACC_IDR (*(WoReg*)0x40040028U) /**< \brief (ACC) Interrupt Disable Register */\r
+#define REG_ACC_IMR (*(RoReg*)0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */\r
+#define REG_ACC_ISR (*(RoReg*)0x40040030U) /**< \brief (ACC) Interrupt Status Register */\r
+#define REG_ACC_ACR (*(RwReg*)0x40040094U) /**< \brief (ACC) Analog Control Register */\r
+#define REG_ACC_WPMR (*(RwReg*)0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */\r
+#define REG_ACC_WPSR (*(RoReg*)0x400400E8U) /**< \brief (ACC) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_ACC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_ADC_INSTANCE_\r
+#define _SAM3S8_ADC_INSTANCE_\r
+\r
+/* ========== Register definition for ADC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_ADC_CR (0x40038000U) /**< \brief (ADC) Control Register */\r
+#define REG_ADC_MR (0x40038004U) /**< \brief (ADC) Mode Register */\r
+#define REG_ADC_SEQR1 (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */\r
+#define REG_ADC_SEQR2 (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */\r
+#define REG_ADC_CHER (0x40038010U) /**< \brief (ADC) Channel Enable Register */\r
+#define REG_ADC_CHDR (0x40038014U) /**< \brief (ADC) Channel Disable Register */\r
+#define REG_ADC_CHSR (0x40038018U) /**< \brief (ADC) Channel Status Register */\r
+#define REG_ADC_LCDR (0x40038020U) /**< \brief (ADC) Last Converted Data Register */\r
+#define REG_ADC_IER (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */\r
+#define REG_ADC_IDR (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */\r
+#define REG_ADC_IMR (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */\r
+#define REG_ADC_ISR (0x40038030U) /**< \brief (ADC) Interrupt Status Register */\r
+#define REG_ADC_OVER (0x4003803CU) /**< \brief (ADC) Overrun Status Register */\r
+#define REG_ADC_EMR (0x40038040U) /**< \brief (ADC) Extended Mode Register */\r
+#define REG_ADC_CWR (0x40038044U) /**< \brief (ADC) Compare Window Register */\r
+#define REG_ADC_CGR (0x40038048U) /**< \brief (ADC) Channel Gain Register */\r
+#define REG_ADC_COR (0x4003804CU) /**< \brief (ADC) Channel Offset Register */\r
+#define REG_ADC_CDR (0x40038050U) /**< \brief (ADC) Channel Data Register */\r
+#define REG_ADC_ACR (0x40038094U) /**< \brief (ADC) Analog Control Register */\r
+#define REG_ADC_WPMR (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */\r
+#define REG_ADC_WPSR (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */\r
+#define REG_ADC_RPR (0x40038100U) /**< \brief (ADC) Receive Pointer Register */\r
+#define REG_ADC_RCR (0x40038104U) /**< \brief (ADC) Receive Counter Register */\r
+#define REG_ADC_RNPR (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */\r
+#define REG_ADC_RNCR (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */\r
+#define REG_ADC_PTCR (0x40038120U) /**< \brief (ADC) Transfer Control Register */\r
+#define REG_ADC_PTSR (0x40038124U) /**< \brief (ADC) Transfer Status Register */\r
+#else\r
+#define REG_ADC_CR (*(WoReg*)0x40038000U) /**< \brief (ADC) Control Register */\r
+#define REG_ADC_MR (*(RwReg*)0x40038004U) /**< \brief (ADC) Mode Register */\r
+#define REG_ADC_SEQR1 (*(RwReg*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */\r
+#define REG_ADC_SEQR2 (*(RwReg*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */\r
+#define REG_ADC_CHER (*(WoReg*)0x40038010U) /**< \brief (ADC) Channel Enable Register */\r
+#define REG_ADC_CHDR (*(WoReg*)0x40038014U) /**< \brief (ADC) Channel Disable Register */\r
+#define REG_ADC_CHSR (*(RoReg*)0x40038018U) /**< \brief (ADC) Channel Status Register */\r
+#define REG_ADC_LCDR (*(RoReg*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */\r
+#define REG_ADC_IER (*(WoReg*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */\r
+#define REG_ADC_IDR (*(WoReg*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */\r
+#define REG_ADC_IMR (*(RoReg*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */\r
+#define REG_ADC_ISR (*(RoReg*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */\r
+#define REG_ADC_OVER (*(RoReg*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */\r
+#define REG_ADC_EMR (*(RwReg*)0x40038040U) /**< \brief (ADC) Extended Mode Register */\r
+#define REG_ADC_CWR (*(RwReg*)0x40038044U) /**< \brief (ADC) Compare Window Register */\r
+#define REG_ADC_CGR (*(RwReg*)0x40038048U) /**< \brief (ADC) Channel Gain Register */\r
+#define REG_ADC_COR (*(RwReg*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */\r
+#define REG_ADC_CDR (*(RoReg*)0x40038050U) /**< \brief (ADC) Channel Data Register */\r
+#define REG_ADC_ACR (*(RwReg*)0x40038094U) /**< \brief (ADC) Analog Control Register */\r
+#define REG_ADC_WPMR (*(RwReg*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */\r
+#define REG_ADC_WPSR (*(RoReg*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */\r
+#define REG_ADC_RPR (*(RwReg*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */\r
+#define REG_ADC_RCR (*(RwReg*)0x40038104U) /**< \brief (ADC) Receive Counter Register */\r
+#define REG_ADC_RNPR (*(RwReg*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */\r
+#define REG_ADC_RNCR (*(RwReg*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */\r
+#define REG_ADC_PTCR (*(WoReg*)0x40038120U) /**< \brief (ADC) Transfer Control Register */\r
+#define REG_ADC_PTSR (*(RoReg*)0x40038124U) /**< \brief (ADC) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_ADC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_CHIPID_INSTANCE_\r
+#define _SAM3S8_CHIPID_INSTANCE_\r
+\r
+/* ========== Register definition for CHIPID peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */\r
+#define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */\r
+#else\r
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */\r
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_CHIPID_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_CRCCU_INSTANCE_\r
+#define _SAM3S8_CRCCU_INSTANCE_\r
+\r
+/* ========== Register definition for CRCCU peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CRCCU_DSCR (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */\r
+#define REG_CRCCU_DMA_EN (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */\r
+#define REG_CRCCU_DMA_DIS (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */\r
+#define REG_CRCCU_DMA_SR (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */\r
+#define REG_CRCCU_DMA_IER (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */\r
+#define REG_CRCCU_DMA_IDR (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */\r
+#define REG_CRCCU_DMA_IMR (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */\r
+#define REG_CRCCU_DMA_ISR (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */\r
+#define REG_CRCCU_CR (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */\r
+#define REG_CRCCU_MR (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */\r
+#define REG_CRCCU_SR (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */\r
+#define REG_CRCCU_IER (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */\r
+#define REG_CRCCU_IDR (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */\r
+#define REG_CRCCU_IMR (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */\r
+#define REG_CRCCU_ISR (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */\r
+#else\r
+#define REG_CRCCU_DSCR (*(RwReg*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */\r
+#define REG_CRCCU_DMA_EN (*(WoReg*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */\r
+#define REG_CRCCU_DMA_DIS (*(WoReg*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */\r
+#define REG_CRCCU_DMA_SR (*(RoReg*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */\r
+#define REG_CRCCU_DMA_IER (*(WoReg*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */\r
+#define REG_CRCCU_DMA_IDR (*(WoReg*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */\r
+#define REG_CRCCU_DMA_IMR (*(RoReg*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */\r
+#define REG_CRCCU_DMA_ISR (*(RoReg*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */\r
+#define REG_CRCCU_CR (*(WoReg*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */\r
+#define REG_CRCCU_MR (*(RwReg*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */\r
+#define REG_CRCCU_SR (*(RoReg*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */\r
+#define REG_CRCCU_IER (*(WoReg*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */\r
+#define REG_CRCCU_IDR (*(WoReg*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */\r
+#define REG_CRCCU_IMR (*(RoReg*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */\r
+#define REG_CRCCU_ISR (*(RoReg*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_CRCCU_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_DACC_INSTANCE_\r
+#define _SAM3S8_DACC_INSTANCE_\r
+\r
+/* ========== Register definition for DACC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_DACC_CR (0x4003C000U) /**< \brief (DACC) Control Register */\r
+#define REG_DACC_MR (0x4003C004U) /**< \brief (DACC) Mode Register */\r
+#define REG_DACC_CHER (0x4003C010U) /**< \brief (DACC) Channel Enable Register */\r
+#define REG_DACC_CHDR (0x4003C014U) /**< \brief (DACC) Channel Disable Register */\r
+#define REG_DACC_CHSR (0x4003C018U) /**< \brief (DACC) Channel Status Register */\r
+#define REG_DACC_CDR (0x4003C020U) /**< \brief (DACC) Conversion Data Register */\r
+#define REG_DACC_IER (0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */\r
+#define REG_DACC_IDR (0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */\r
+#define REG_DACC_IMR (0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */\r
+#define REG_DACC_ISR (0x4003C030U) /**< \brief (DACC) Interrupt Status Register */\r
+#define REG_DACC_ACR (0x4003C094U) /**< \brief (DACC) Analog Current Register */\r
+#define REG_DACC_WPMR (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */\r
+#define REG_DACC_WPSR (0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */\r
+#define REG_DACC_TPR (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */\r
+#define REG_DACC_TCR (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */\r
+#define REG_DACC_TNPR (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */\r
+#define REG_DACC_TNCR (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */\r
+#define REG_DACC_PTCR (0x4003C120U) /**< \brief (DACC) Transfer Control Register */\r
+#define REG_DACC_PTSR (0x4003C124U) /**< \brief (DACC) Transfer Status Register */\r
+#else\r
+#define REG_DACC_CR (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */\r
+#define REG_DACC_MR (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */\r
+#define REG_DACC_CHER (*(WoReg*)0x4003C010U) /**< \brief (DACC) Channel Enable Register */\r
+#define REG_DACC_CHDR (*(WoReg*)0x4003C014U) /**< \brief (DACC) Channel Disable Register */\r
+#define REG_DACC_CHSR (*(RoReg*)0x4003C018U) /**< \brief (DACC) Channel Status Register */\r
+#define REG_DACC_CDR (*(WoReg*)0x4003C020U) /**< \brief (DACC) Conversion Data Register */\r
+#define REG_DACC_IER (*(WoReg*)0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */\r
+#define REG_DACC_IDR (*(WoReg*)0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */\r
+#define REG_DACC_IMR (*(RoReg*)0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */\r
+#define REG_DACC_ISR (*(RoReg*)0x4003C030U) /**< \brief (DACC) Interrupt Status Register */\r
+#define REG_DACC_ACR (*(RwReg*)0x4003C094U) /**< \brief (DACC) Analog Current Register */\r
+#define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */\r
+#define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */\r
+#define REG_DACC_TPR (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */\r
+#define REG_DACC_TCR (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */\r
+#define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */\r
+#define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */\r
+#define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */\r
+#define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_DACC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_EFC_INSTANCE_\r
+#define _SAM3S8_EFC_INSTANCE_\r
+\r
+/* ========== Register definition for EFC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_EFC_FMR (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */\r
+#define REG_EFC_FCR (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */\r
+#define REG_EFC_FSR (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */\r
+#define REG_EFC_FRR (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */\r
+#else\r
+#define REG_EFC_FMR (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */\r
+#define REG_EFC_FCR (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */\r
+#define REG_EFC_FSR (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */\r
+#define REG_EFC_FRR (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_EFC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_GPBR_INSTANCE_\r
+#define _SAM3S8_GPBR_INSTANCE_\r
+\r
+/* ========== Register definition for GPBR peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_GPBR_GPBR (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */\r
+#else\r
+#define REG_GPBR_GPBR (*(RwReg*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_GPBR_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_HSMCI_INSTANCE_\r
+#define _SAM3S8_HSMCI_INSTANCE_\r
+\r
+/* ========== Register definition for HSMCI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */\r
+#define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */\r
+#define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */\r
+#define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */\r
+#define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */\r
+#define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */\r
+#define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */\r
+#define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */\r
+#define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */\r
+#define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */\r
+#define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */\r
+#define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */\r
+#define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */\r
+#define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */\r
+#define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */\r
+#define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */\r
+#define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */\r
+#define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */\r
+#define REG_HSMCI_RPR (0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */\r
+#define REG_HSMCI_RCR (0x40000104U) /**< \brief (HSMCI) Receive Counter Register */\r
+#define REG_HSMCI_TPR (0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */\r
+#define REG_HSMCI_TCR (0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */\r
+#define REG_HSMCI_RNPR (0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */\r
+#define REG_HSMCI_RNCR (0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */\r
+#define REG_HSMCI_TNPR (0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */\r
+#define REG_HSMCI_TNCR (0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */\r
+#define REG_HSMCI_PTCR (0x40000120U) /**< \brief (HSMCI) Transfer Control Register */\r
+#define REG_HSMCI_PTSR (0x40000124U) /**< \brief (HSMCI) Transfer Status Register */\r
+#define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */\r
+#else\r
+#define REG_HSMCI_CR (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */\r
+#define REG_HSMCI_MR (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */\r
+#define REG_HSMCI_DTOR (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */\r
+#define REG_HSMCI_SDCR (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */\r
+#define REG_HSMCI_ARGR (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */\r
+#define REG_HSMCI_CMDR (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */\r
+#define REG_HSMCI_BLKR (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */\r
+#define REG_HSMCI_CSTOR (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */\r
+#define REG_HSMCI_RSPR (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */\r
+#define REG_HSMCI_RDR (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */\r
+#define REG_HSMCI_TDR (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */\r
+#define REG_HSMCI_SR (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */\r
+#define REG_HSMCI_IER (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */\r
+#define REG_HSMCI_IDR (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */\r
+#define REG_HSMCI_IMR (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */\r
+#define REG_HSMCI_CFG (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */\r
+#define REG_HSMCI_WPMR (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */\r
+#define REG_HSMCI_WPSR (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */\r
+#define REG_HSMCI_RPR (*(RwReg*)0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */\r
+#define REG_HSMCI_RCR (*(RwReg*)0x40000104U) /**< \brief (HSMCI) Receive Counter Register */\r
+#define REG_HSMCI_TPR (*(RwReg*)0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */\r
+#define REG_HSMCI_TCR (*(RwReg*)0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */\r
+#define REG_HSMCI_RNPR (*(RwReg*)0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */\r
+#define REG_HSMCI_RNCR (*(RwReg*)0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */\r
+#define REG_HSMCI_TNPR (*(RwReg*)0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */\r
+#define REG_HSMCI_TNCR (*(RwReg*)0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */\r
+#define REG_HSMCI_PTCR (*(WoReg*)0x40000120U) /**< \brief (HSMCI) Transfer Control Register */\r
+#define REG_HSMCI_PTSR (*(RoReg*)0x40000124U) /**< \brief (HSMCI) Transfer Status Register */\r
+#define REG_HSMCI_FIFO (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_HSMCI_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_MATRIX_INSTANCE_\r
+#define _SAM3S8_MATRIX_INSTANCE_\r
+\r
+/* ========== Register definition for MATRIX peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */\r
+#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */\r
+#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */\r
+#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */\r
+#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */\r
+#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */\r
+#define REG_MATRIX_PRAS4 (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */\r
+#define REG_CCFG_SYSIO (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */\r
+#define REG_CCFG_SMCNFCS (0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */\r
+#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */\r
+#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */\r
+#else\r
+#define REG_MATRIX_MCFG (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */\r
+#define REG_MATRIX_SCFG (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */\r
+#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */\r
+#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */\r
+#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */\r
+#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */\r
+#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */\r
+#define REG_CCFG_SYSIO (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */\r
+#define REG_CCFG_SMCNFCS (*(RwReg*)0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */\r
+#define REG_MATRIX_WPMR (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */\r
+#define REG_MATRIX_WPSR (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_MATRIX_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_PIOA_INSTANCE_\r
+#define _SAM3S8_PIOA_INSTANCE_\r
+\r
+/* ========== Register definition for PIOA peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */\r
+#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */\r
+#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */\r
+#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */\r
+#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */\r
+#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */\r
+#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */\r
+#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */\r
+#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */\r
+#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */\r
+#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */\r
+#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */\r
+#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */\r
+#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */\r
+#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */\r
+#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */\r
+#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */\r
+#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */\r
+#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */\r
+#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */\r
+#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */\r
+#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */\r
+#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */\r
+#define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */\r
+#define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */\r
+#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */\r
+#define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */\r
+#define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */\r
+#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */\r
+#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */\r
+#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */\r
+#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */\r
+#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */\r
+#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */\r
+#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */\r
+#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */\r
+#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */\r
+#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */\r
+#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */\r
+#define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */\r
+#define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */\r
+#define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */\r
+#define REG_PIOA_RPR (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */\r
+#define REG_PIOA_RCR (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */\r
+#define REG_PIOA_RNPR (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */\r
+#define REG_PIOA_RNCR (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */\r
+#define REG_PIOA_PTCR (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */\r
+#define REG_PIOA_PTSR (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */\r
+#else\r
+#define REG_PIOA_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */\r
+#define REG_PIOA_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */\r
+#define REG_PIOA_PSR (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */\r
+#define REG_PIOA_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */\r
+#define REG_PIOA_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */\r
+#define REG_PIOA_OSR (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */\r
+#define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */\r
+#define REG_PIOA_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */\r
+#define REG_PIOA_IFSR (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */\r
+#define REG_PIOA_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */\r
+#define REG_PIOA_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */\r
+#define REG_PIOA_ODSR (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */\r
+#define REG_PIOA_PDSR (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */\r
+#define REG_PIOA_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */\r
+#define REG_PIOA_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */\r
+#define REG_PIOA_IMR (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */\r
+#define REG_PIOA_ISR (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */\r
+#define REG_PIOA_MDER (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */\r
+#define REG_PIOA_MDDR (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */\r
+#define REG_PIOA_MDSR (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */\r
+#define REG_PIOA_PUDR (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */\r
+#define REG_PIOA_PUER (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */\r
+#define REG_PIOA_PUSR (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */\r
+#define REG_PIOA_ABCDSR (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */\r
+#define REG_PIOA_IFSCDR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOA_IFSCER (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOA_IFSCSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */\r
+#define REG_PIOA_SCDR (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOA_PPDDR (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */\r
+#define REG_PIOA_PPDER (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */\r
+#define REG_PIOA_PPDSR (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */\r
+#define REG_PIOA_OWER (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */\r
+#define REG_PIOA_OWDR (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */\r
+#define REG_PIOA_OWSR (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */\r
+#define REG_PIOA_AIMER (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOA_AIMDR (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOA_AIMMR (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOA_ESR (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */\r
+#define REG_PIOA_LSR (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */\r
+#define REG_PIOA_ELSR (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */\r
+#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */\r
+#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */\r
+#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */\r
+#define REG_PIOA_WPMR (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */\r
+#define REG_PIOA_WPSR (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */\r
+#define REG_PIOA_SCHMITT (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */\r
+#define REG_PIOA_PCMR (*(RwReg*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */\r
+#define REG_PIOA_PCIER (*(WoReg*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOA_PCIDR (*(WoReg*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOA_PCIMR (*(RoReg*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOA_PCISR (*(RoReg*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOA_PCRHR (*(RoReg*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */\r
+#define REG_PIOA_RPR (*(RwReg*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */\r
+#define REG_PIOA_RCR (*(RwReg*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */\r
+#define REG_PIOA_RNPR (*(RwReg*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */\r
+#define REG_PIOA_RNCR (*(RwReg*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */\r
+#define REG_PIOA_PTCR (*(WoReg*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */\r
+#define REG_PIOA_PTSR (*(RoReg*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_PIOA_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_PIOB_INSTANCE_\r
+#define _SAM3S8_PIOB_INSTANCE_\r
+\r
+/* ========== Register definition for PIOB peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */\r
+#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */\r
+#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */\r
+#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */\r
+#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */\r
+#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */\r
+#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */\r
+#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */\r
+#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */\r
+#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */\r
+#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */\r
+#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */\r
+#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */\r
+#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */\r
+#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */\r
+#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */\r
+#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */\r
+#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */\r
+#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */\r
+#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */\r
+#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */\r
+#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */\r
+#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */\r
+#define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */\r
+#define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */\r
+#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */\r
+#define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */\r
+#define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */\r
+#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */\r
+#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */\r
+#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */\r
+#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */\r
+#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */\r
+#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */\r
+#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */\r
+#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */\r
+#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */\r
+#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */\r
+#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */\r
+#define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */\r
+#define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */\r
+#define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */\r
+#else\r
+#define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */\r
+#define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */\r
+#define REG_PIOB_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */\r
+#define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */\r
+#define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */\r
+#define REG_PIOB_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */\r
+#define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */\r
+#define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */\r
+#define REG_PIOB_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */\r
+#define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */\r
+#define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */\r
+#define REG_PIOB_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */\r
+#define REG_PIOB_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */\r
+#define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */\r
+#define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */\r
+#define REG_PIOB_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */\r
+#define REG_PIOB_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */\r
+#define REG_PIOB_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */\r
+#define REG_PIOB_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */\r
+#define REG_PIOB_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */\r
+#define REG_PIOB_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */\r
+#define REG_PIOB_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */\r
+#define REG_PIOB_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */\r
+#define REG_PIOB_ABCDSR (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */\r
+#define REG_PIOB_IFSCDR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOB_IFSCER (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOB_IFSCSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */\r
+#define REG_PIOB_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOB_PPDDR (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */\r
+#define REG_PIOB_PPDER (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */\r
+#define REG_PIOB_PPDSR (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */\r
+#define REG_PIOB_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */\r
+#define REG_PIOB_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */\r
+#define REG_PIOB_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */\r
+#define REG_PIOB_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOB_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOB_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOB_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */\r
+#define REG_PIOB_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */\r
+#define REG_PIOB_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */\r
+#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */\r
+#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */\r
+#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */\r
+#define REG_PIOB_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */\r
+#define REG_PIOB_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */\r
+#define REG_PIOB_SCHMITT (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */\r
+#define REG_PIOB_PCMR (*(RwReg*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */\r
+#define REG_PIOB_PCIER (*(WoReg*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOB_PCIDR (*(WoReg*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOB_PCIMR (*(RoReg*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOB_PCISR (*(RoReg*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOB_PCRHR (*(RoReg*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_PIOB_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_PIOC_INSTANCE_\r
+#define _SAM3S8_PIOC_INSTANCE_\r
+\r
+/* ========== Register definition for PIOC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */\r
+#define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */\r
+#define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */\r
+#define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */\r
+#define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */\r
+#define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */\r
+#define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */\r
+#define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */\r
+#define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */\r
+#define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */\r
+#define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */\r
+#define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */\r
+#define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */\r
+#define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */\r
+#define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */\r
+#define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */\r
+#define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */\r
+#define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */\r
+#define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */\r
+#define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */\r
+#define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */\r
+#define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */\r
+#define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */\r
+#define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */\r
+#define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */\r
+#define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */\r
+#define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */\r
+#define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */\r
+#define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */\r
+#define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */\r
+#define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */\r
+#define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */\r
+#define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */\r
+#define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */\r
+#define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */\r
+#define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */\r
+#define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */\r
+#define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */\r
+#define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */\r
+#define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */\r
+#define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */\r
+#define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */\r
+#else\r
+#define REG_PIOC_PER (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */\r
+#define REG_PIOC_PDR (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */\r
+#define REG_PIOC_PSR (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */\r
+#define REG_PIOC_OER (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */\r
+#define REG_PIOC_ODR (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */\r
+#define REG_PIOC_OSR (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */\r
+#define REG_PIOC_IFER (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */\r
+#define REG_PIOC_IFDR (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */\r
+#define REG_PIOC_IFSR (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */\r
+#define REG_PIOC_SODR (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */\r
+#define REG_PIOC_CODR (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */\r
+#define REG_PIOC_ODSR (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */\r
+#define REG_PIOC_PDSR (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */\r
+#define REG_PIOC_IER (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */\r
+#define REG_PIOC_IDR (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */\r
+#define REG_PIOC_IMR (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */\r
+#define REG_PIOC_ISR (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */\r
+#define REG_PIOC_MDER (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */\r
+#define REG_PIOC_MDDR (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */\r
+#define REG_PIOC_MDSR (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */\r
+#define REG_PIOC_PUDR (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */\r
+#define REG_PIOC_PUER (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */\r
+#define REG_PIOC_PUSR (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */\r
+#define REG_PIOC_ABCDSR (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */\r
+#define REG_PIOC_IFSCDR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOC_IFSCER (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOC_IFSCSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */\r
+#define REG_PIOC_SCDR (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOC_PPDDR (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */\r
+#define REG_PIOC_PPDER (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */\r
+#define REG_PIOC_PPDSR (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */\r
+#define REG_PIOC_OWER (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */\r
+#define REG_PIOC_OWDR (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */\r
+#define REG_PIOC_OWSR (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */\r
+#define REG_PIOC_AIMER (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOC_AIMDR (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOC_AIMMR (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOC_ESR (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */\r
+#define REG_PIOC_LSR (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */\r
+#define REG_PIOC_ELSR (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */\r
+#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */\r
+#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */\r
+#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */\r
+#define REG_PIOC_WPMR (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */\r
+#define REG_PIOC_WPSR (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */\r
+#define REG_PIOC_SCHMITT (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */\r
+#define REG_PIOC_PCMR (*(RwReg*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */\r
+#define REG_PIOC_PCIER (*(WoReg*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOC_PCIDR (*(WoReg*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOC_PCIMR (*(RoReg*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOC_PCISR (*(RoReg*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOC_PCRHR (*(RoReg*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_PIOC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_PMC_INSTANCE_\r
+#define _SAM3S8_PMC_INSTANCE_\r
+\r
+/* ========== Register definition for PMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */\r
+#define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */\r
+#define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */\r
+#define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */\r
+#define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */\r
+#define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */\r
+#define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */\r
+#define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */\r
+#define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */\r
+#define REG_CKGR_PLLBR (0x400E042CU) /**< \brief (PMC) PLLB Register */\r
+#define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */\r
+#define REG_PMC_USB (0x400E0438U) /**< \brief (PMC) USB Clock Register */\r
+#define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */\r
+#define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */\r
+#define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */\r
+#define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */\r
+#define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */\r
+#define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */\r
+#define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */\r
+#define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */\r
+#define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */\r
+#define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */\r
+#define REG_PMC_PCER1 (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */\r
+#define REG_PMC_PCDR1 (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */\r
+#define REG_PMC_PCSR1 (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */\r
+#define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */\r
+#else\r
+#define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */\r
+#define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */\r
+#define REG_PMC_SCSR (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */\r
+#define REG_PMC_PCER0 (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */\r
+#define REG_PMC_PCDR0 (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */\r
+#define REG_PMC_PCSR0 (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */\r
+#define REG_CKGR_MOR (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */\r
+#define REG_CKGR_MCFR (*(RwReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */\r
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */\r
+#define REG_CKGR_PLLBR (*(RwReg*)0x400E042CU) /**< \brief (PMC) PLLB Register */\r
+#define REG_PMC_MCKR (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */\r
+#define REG_PMC_USB (*(RwReg*)0x400E0438U) /**< \brief (PMC) USB Clock Register */\r
+#define REG_PMC_PCK (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */\r
+#define REG_PMC_IER (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */\r
+#define REG_PMC_IDR (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */\r
+#define REG_PMC_SR (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */\r
+#define REG_PMC_IMR (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */\r
+#define REG_PMC_FSMR (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */\r
+#define REG_PMC_FSPR (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */\r
+#define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */\r
+#define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */\r
+#define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */\r
+#define REG_PMC_PCER1 (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */\r
+#define REG_PMC_PCDR1 (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */\r
+#define REG_PMC_PCSR1 (*(RoReg*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */\r
+#define REG_PMC_OCR (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_PMC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_PWM_INSTANCE_\r
+#define _SAM3S8_PWM_INSTANCE_\r
+\r
+/* ========== Register definition for PWM peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PWM_CLK (0x40020000U) /**< \brief (PWM) PWM Clock Register */\r
+#define REG_PWM_ENA (0x40020004U) /**< \brief (PWM) PWM Enable Register */\r
+#define REG_PWM_DIS (0x40020008U) /**< \brief (PWM) PWM Disable Register */\r
+#define REG_PWM_SR (0x4002000CU) /**< \brief (PWM) PWM Status Register */\r
+#define REG_PWM_IER1 (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */\r
+#define REG_PWM_IDR1 (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */\r
+#define REG_PWM_IMR1 (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */\r
+#define REG_PWM_ISR1 (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */\r
+#define REG_PWM_SCM (0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */\r
+#define REG_PWM_SCUC (0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */\r
+#define REG_PWM_SCUP (0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */\r
+#define REG_PWM_SCUPUPD (0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */\r
+#define REG_PWM_IER2 (0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */\r
+#define REG_PWM_IDR2 (0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */\r
+#define REG_PWM_IMR2 (0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */\r
+#define REG_PWM_ISR2 (0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */\r
+#define REG_PWM_OOV (0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */\r
+#define REG_PWM_OS (0x40020048U) /**< \brief (PWM) PWM Output Selection Register */\r
+#define REG_PWM_OSS (0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */\r
+#define REG_PWM_OSC (0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */\r
+#define REG_PWM_OSSUPD (0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */\r
+#define REG_PWM_OSCUPD (0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */\r
+#define REG_PWM_FMR (0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */\r
+#define REG_PWM_FSR (0x40020060U) /**< \brief (PWM) PWM Fault Status Register */\r
+#define REG_PWM_FCR (0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */\r
+#define REG_PWM_FPV (0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */\r
+#define REG_PWM_FPE (0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */\r
+#define REG_PWM_ELMR (0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */\r
+#define REG_PWM_SMMR (0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */\r
+#define REG_PWM_WPCR (0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */\r
+#define REG_PWM_WPSR (0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */\r
+#define REG_PWM_TPR (0x40020108U) /**< \brief (PWM) Transmit Pointer Register */\r
+#define REG_PWM_TCR (0x4002010CU) /**< \brief (PWM) Transmit Counter Register */\r
+#define REG_PWM_TNPR (0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */\r
+#define REG_PWM_TNCR (0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */\r
+#define REG_PWM_PTCR (0x40020120U) /**< \brief (PWM) Transfer Control Register */\r
+#define REG_PWM_PTSR (0x40020124U) /**< \brief (PWM) Transfer Status Register */\r
+#define REG_PWM_CMPV0 (0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */\r
+#define REG_PWM_CMPVUPD0 (0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */\r
+#define REG_PWM_CMPM0 (0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */\r
+#define REG_PWM_CMPMUPD0 (0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */\r
+#define REG_PWM_CMPV1 (0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */\r
+#define REG_PWM_CMPVUPD1 (0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */\r
+#define REG_PWM_CMPM1 (0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */\r
+#define REG_PWM_CMPMUPD1 (0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */\r
+#define REG_PWM_CMPV2 (0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */\r
+#define REG_PWM_CMPVUPD2 (0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */\r
+#define REG_PWM_CMPM2 (0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */\r
+#define REG_PWM_CMPMUPD2 (0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */\r
+#define REG_PWM_CMPV3 (0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */\r
+#define REG_PWM_CMPVUPD3 (0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */\r
+#define REG_PWM_CMPM3 (0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */\r
+#define REG_PWM_CMPMUPD3 (0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */\r
+#define REG_PWM_CMPV4 (0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */\r
+#define REG_PWM_CMPVUPD4 (0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */\r
+#define REG_PWM_CMPM4 (0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */\r
+#define REG_PWM_CMPMUPD4 (0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */\r
+#define REG_PWM_CMPV5 (0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */\r
+#define REG_PWM_CMPVUPD5 (0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */\r
+#define REG_PWM_CMPM5 (0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */\r
+#define REG_PWM_CMPMUPD5 (0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */\r
+#define REG_PWM_CMPV6 (0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */\r
+#define REG_PWM_CMPVUPD6 (0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */\r
+#define REG_PWM_CMPM6 (0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */\r
+#define REG_PWM_CMPMUPD6 (0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */\r
+#define REG_PWM_CMPV7 (0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */\r
+#define REG_PWM_CMPVUPD7 (0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */\r
+#define REG_PWM_CMPM7 (0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */\r
+#define REG_PWM_CMPMUPD7 (0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */\r
+#define REG_PWM_CMR0 (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */\r
+#define REG_PWM_CDTY0 (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+#define REG_PWM_CDTYUPD0 (0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+#define REG_PWM_CPRD0 (0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */\r
+#define REG_PWM_CPRDUPD0 (0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */\r
+#define REG_PWM_CCNT0 (0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */\r
+#define REG_PWM_DT0 (0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */\r
+#define REG_PWM_DTUPD0 (0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+#define REG_PWM_CMR1 (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */\r
+#define REG_PWM_CDTY1 (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+#define REG_PWM_CDTYUPD1 (0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+#define REG_PWM_CPRD1 (0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */\r
+#define REG_PWM_CPRDUPD1 (0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */\r
+#define REG_PWM_CCNT1 (0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */\r
+#define REG_PWM_DT1 (0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */\r
+#define REG_PWM_DTUPD1 (0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+#define REG_PWM_CMR2 (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */\r
+#define REG_PWM_CDTY2 (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+#define REG_PWM_CDTYUPD2 (0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+#define REG_PWM_CPRD2 (0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */\r
+#define REG_PWM_CPRDUPD2 (0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */\r
+#define REG_PWM_CCNT2 (0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */\r
+#define REG_PWM_DT2 (0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */\r
+#define REG_PWM_DTUPD2 (0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+#define REG_PWM_CMR3 (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */\r
+#define REG_PWM_CDTY3 (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+#define REG_PWM_CDTYUPD3 (0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+#define REG_PWM_CPRD3 (0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */\r
+#define REG_PWM_CPRDUPD3 (0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */\r
+#define REG_PWM_CCNT3 (0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */\r
+#define REG_PWM_DT3 (0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */\r
+#define REG_PWM_DTUPD3 (0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+#else\r
+#define REG_PWM_CLK (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Clock Register */\r
+#define REG_PWM_ENA (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */\r
+#define REG_PWM_DIS (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */\r
+#define REG_PWM_SR (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */\r
+#define REG_PWM_IER1 (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */\r
+#define REG_PWM_IDR1 (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */\r
+#define REG_PWM_IMR1 (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */\r
+#define REG_PWM_ISR1 (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */\r
+#define REG_PWM_SCM (*(RwReg*)0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */\r
+#define REG_PWM_SCUC (*(RwReg*)0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */\r
+#define REG_PWM_SCUP (*(RwReg*)0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */\r
+#define REG_PWM_SCUPUPD (*(WoReg*)0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */\r
+#define REG_PWM_IER2 (*(WoReg*)0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */\r
+#define REG_PWM_IDR2 (*(WoReg*)0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */\r
+#define REG_PWM_IMR2 (*(RoReg*)0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */\r
+#define REG_PWM_ISR2 (*(RoReg*)0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */\r
+#define REG_PWM_OOV (*(RwReg*)0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */\r
+#define REG_PWM_OS (*(RwReg*)0x40020048U) /**< \brief (PWM) PWM Output Selection Register */\r
+#define REG_PWM_OSS (*(WoReg*)0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */\r
+#define REG_PWM_OSC (*(WoReg*)0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */\r
+#define REG_PWM_OSSUPD (*(WoReg*)0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */\r
+#define REG_PWM_OSCUPD (*(WoReg*)0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */\r
+#define REG_PWM_FMR (*(RwReg*)0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */\r
+#define REG_PWM_FSR (*(RoReg*)0x40020060U) /**< \brief (PWM) PWM Fault Status Register */\r
+#define REG_PWM_FCR (*(WoReg*)0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */\r
+#define REG_PWM_FPV (*(RwReg*)0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */\r
+#define REG_PWM_FPE (*(RwReg*)0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */\r
+#define REG_PWM_ELMR (*(RwReg*)0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */\r
+#define REG_PWM_SMMR (*(RwReg*)0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */\r
+#define REG_PWM_WPCR (*(WoReg*)0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */\r
+#define REG_PWM_WPSR (*(RoReg*)0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */\r
+#define REG_PWM_TPR (*(RwReg*)0x40020108U) /**< \brief (PWM) Transmit Pointer Register */\r
+#define REG_PWM_TCR (*(RwReg*)0x4002010CU) /**< \brief (PWM) Transmit Counter Register */\r
+#define REG_PWM_TNPR (*(RwReg*)0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */\r
+#define REG_PWM_TNCR (*(RwReg*)0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */\r
+#define REG_PWM_PTCR (*(WoReg*)0x40020120U) /**< \brief (PWM) Transfer Control Register */\r
+#define REG_PWM_PTSR (*(RoReg*)0x40020124U) /**< \brief (PWM) Transfer Status Register */\r
+#define REG_PWM_CMPV0 (*(RwReg*)0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */\r
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */\r
+#define REG_PWM_CMPM0 (*(RwReg*)0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */\r
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */\r
+#define REG_PWM_CMPV1 (*(RwReg*)0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */\r
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */\r
+#define REG_PWM_CMPM1 (*(RwReg*)0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */\r
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */\r
+#define REG_PWM_CMPV2 (*(RwReg*)0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */\r
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */\r
+#define REG_PWM_CMPM2 (*(RwReg*)0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */\r
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */\r
+#define REG_PWM_CMPV3 (*(RwReg*)0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */\r
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */\r
+#define REG_PWM_CMPM3 (*(RwReg*)0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */\r
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */\r
+#define REG_PWM_CMPV4 (*(RwReg*)0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */\r
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */\r
+#define REG_PWM_CMPM4 (*(RwReg*)0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */\r
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */\r
+#define REG_PWM_CMPV5 (*(RwReg*)0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */\r
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */\r
+#define REG_PWM_CMPM5 (*(RwReg*)0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */\r
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */\r
+#define REG_PWM_CMPV6 (*(RwReg*)0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */\r
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */\r
+#define REG_PWM_CMPM6 (*(RwReg*)0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */\r
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */\r
+#define REG_PWM_CMPV7 (*(RwReg*)0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */\r
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */\r
+#define REG_PWM_CMPM7 (*(RwReg*)0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */\r
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */\r
+#define REG_PWM_CMR0 (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */\r
+#define REG_PWM_CDTY0 (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+#define REG_PWM_CPRD0 (*(RwReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */\r
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */\r
+#define REG_PWM_CCNT0 (*(RoReg*)0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */\r
+#define REG_PWM_DT0 (*(RwReg*)0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */\r
+#define REG_PWM_DTUPD0 (*(WoReg*)0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+#define REG_PWM_CMR1 (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */\r
+#define REG_PWM_CDTY1 (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+#define REG_PWM_CPRD1 (*(RwReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */\r
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */\r
+#define REG_PWM_CCNT1 (*(RoReg*)0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */\r
+#define REG_PWM_DT1 (*(RwReg*)0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */\r
+#define REG_PWM_DTUPD1 (*(WoReg*)0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+#define REG_PWM_CMR2 (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */\r
+#define REG_PWM_CDTY2 (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+#define REG_PWM_CPRD2 (*(RwReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */\r
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */\r
+#define REG_PWM_CCNT2 (*(RoReg*)0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */\r
+#define REG_PWM_DT2 (*(RwReg*)0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */\r
+#define REG_PWM_DTUPD2 (*(WoReg*)0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+#define REG_PWM_CMR3 (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */\r
+#define REG_PWM_CDTY3 (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+#define REG_PWM_CPRD3 (*(RwReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */\r
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */\r
+#define REG_PWM_CCNT3 (*(RoReg*)0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */\r
+#define REG_PWM_DT3 (*(RwReg*)0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */\r
+#define REG_PWM_DTUPD3 (*(WoReg*)0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_PWM_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_RSTC_INSTANCE_\r
+#define _SAM3S8_RSTC_INSTANCE_\r
+\r
+/* ========== Register definition for RSTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RSTC_CR (0x400E1400U) /**< \brief (RSTC) Control Register */\r
+#define REG_RSTC_SR (0x400E1404U) /**< \brief (RSTC) Status Register */\r
+#define REG_RSTC_MR (0x400E1408U) /**< \brief (RSTC) Mode Register */\r
+#else\r
+#define REG_RSTC_CR (*(WoReg*)0x400E1400U) /**< \brief (RSTC) Control Register */\r
+#define REG_RSTC_SR (*(RoReg*)0x400E1404U) /**< \brief (RSTC) Status Register */\r
+#define REG_RSTC_MR (*(RwReg*)0x400E1408U) /**< \brief (RSTC) Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_RSTC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_RTC_INSTANCE_\r
+#define _SAM3S8_RTC_INSTANCE_\r
+\r
+/* ========== Register definition for RTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RTC_CR (0x400E1460U) /**< \brief (RTC) Control Register */\r
+#define REG_RTC_MR (0x400E1464U) /**< \brief (RTC) Mode Register */\r
+#define REG_RTC_TIMR (0x400E1468U) /**< \brief (RTC) Time Register */\r
+#define REG_RTC_CALR (0x400E146CU) /**< \brief (RTC) Calendar Register */\r
+#define REG_RTC_TIMALR (0x400E1470U) /**< \brief (RTC) Time Alarm Register */\r
+#define REG_RTC_CALALR (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */\r
+#define REG_RTC_SR (0x400E1478U) /**< \brief (RTC) Status Register */\r
+#define REG_RTC_SCCR (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */\r
+#define REG_RTC_IER (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */\r
+#define REG_RTC_IDR (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */\r
+#define REG_RTC_IMR (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */\r
+#define REG_RTC_VER (0x400E148CU) /**< \brief (RTC) Valid Entry Register */\r
+#else\r
+#define REG_RTC_CR (*(RwReg*)0x400E1460U) /**< \brief (RTC) Control Register */\r
+#define REG_RTC_MR (*(RwReg*)0x400E1464U) /**< \brief (RTC) Mode Register */\r
+#define REG_RTC_TIMR (*(RwReg*)0x400E1468U) /**< \brief (RTC) Time Register */\r
+#define REG_RTC_CALR (*(RwReg*)0x400E146CU) /**< \brief (RTC) Calendar Register */\r
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */\r
+#define REG_RTC_CALALR (*(RwReg*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */\r
+#define REG_RTC_SR (*(RoReg*)0x400E1478U) /**< \brief (RTC) Status Register */\r
+#define REG_RTC_SCCR (*(WoReg*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */\r
+#define REG_RTC_IER (*(WoReg*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */\r
+#define REG_RTC_IDR (*(WoReg*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */\r
+#define REG_RTC_IMR (*(RoReg*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */\r
+#define REG_RTC_VER (*(RoReg*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_RTC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_RTT_INSTANCE_\r
+#define _SAM3S8_RTT_INSTANCE_\r
+\r
+/* ========== Register definition for RTT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RTT_MR (0x400E1430U) /**< \brief (RTT) Mode Register */\r
+#define REG_RTT_AR (0x400E1434U) /**< \brief (RTT) Alarm Register */\r
+#define REG_RTT_VR (0x400E1438U) /**< \brief (RTT) Value Register */\r
+#define REG_RTT_SR (0x400E143CU) /**< \brief (RTT) Status Register */\r
+#else\r
+#define REG_RTT_MR (*(RwReg*)0x400E1430U) /**< \brief (RTT) Mode Register */\r
+#define REG_RTT_AR (*(RwReg*)0x400E1434U) /**< \brief (RTT) Alarm Register */\r
+#define REG_RTT_VR (*(RoReg*)0x400E1438U) /**< \brief (RTT) Value Register */\r
+#define REG_RTT_SR (*(RoReg*)0x400E143CU) /**< \brief (RTT) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_RTT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_SMC_INSTANCE_\r
+#define _SAM3S8_SMC_INSTANCE_\r
+\r
+/* ========== Register definition for SMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SMC_SETUP0 (0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+#define REG_SMC_PULSE0 (0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+#define REG_SMC_CYCLE0 (0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+#define REG_SMC_MODE0 (0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */\r
+#define REG_SMC_SETUP1 (0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+#define REG_SMC_PULSE1 (0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+#define REG_SMC_CYCLE1 (0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+#define REG_SMC_MODE1 (0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */\r
+#define REG_SMC_SETUP2 (0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+#define REG_SMC_PULSE2 (0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+#define REG_SMC_CYCLE2 (0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+#define REG_SMC_MODE2 (0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */\r
+#define REG_SMC_SETUP3 (0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+#define REG_SMC_PULSE3 (0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+#define REG_SMC_CYCLE3 (0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+#define REG_SMC_MODE3 (0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */\r
+#define REG_SMC_SETUP4 (0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */\r
+#define REG_SMC_PULSE4 (0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */\r
+#define REG_SMC_CYCLE4 (0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */\r
+#define REG_SMC_MODE4 (0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */\r
+#define REG_SMC_OCMS (0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */\r
+#define REG_SMC_KEY1 (0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+#define REG_SMC_KEY2 (0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+#define REG_SMC_WPMR (0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */\r
+#define REG_SMC_WPSR (0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */\r
+#else\r
+#define REG_SMC_SETUP0 (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+#define REG_SMC_PULSE0 (*(RwReg*)0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+#define REG_SMC_MODE0 (*(RwReg*)0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */\r
+#define REG_SMC_SETUP1 (*(RwReg*)0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+#define REG_SMC_PULSE1 (*(RwReg*)0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+#define REG_SMC_CYCLE1 (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+#define REG_SMC_MODE1 (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */\r
+#define REG_SMC_SETUP2 (*(RwReg*)0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+#define REG_SMC_PULSE2 (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+#define REG_SMC_CYCLE2 (*(RwReg*)0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+#define REG_SMC_MODE2 (*(RwReg*)0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */\r
+#define REG_SMC_SETUP3 (*(RwReg*)0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+#define REG_SMC_PULSE3 (*(RwReg*)0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+#define REG_SMC_CYCLE3 (*(RwReg*)0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+#define REG_SMC_MODE3 (*(RwReg*)0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */\r
+#define REG_SMC_SETUP4 (*(RwReg*)0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */\r
+#define REG_SMC_PULSE4 (*(RwReg*)0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */\r
+#define REG_SMC_CYCLE4 (*(RwReg*)0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */\r
+#define REG_SMC_MODE4 (*(RwReg*)0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */\r
+#define REG_SMC_OCMS (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */\r
+#define REG_SMC_KEY1 (*(WoReg*)0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+#define REG_SMC_KEY2 (*(WoReg*)0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+#define REG_SMC_WPMR (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */\r
+#define REG_SMC_WPSR (*(RoReg*)0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_SMC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_SPI_INSTANCE_\r
+#define _SAM3S8_SPI_INSTANCE_\r
+\r
+/* ========== Register definition for SPI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SPI_CR (0x40008000U) /**< \brief (SPI) Control Register */\r
+#define REG_SPI_MR (0x40008004U) /**< \brief (SPI) Mode Register */\r
+#define REG_SPI_RDR (0x40008008U) /**< \brief (SPI) Receive Data Register */\r
+#define REG_SPI_TDR (0x4000800CU) /**< \brief (SPI) Transmit Data Register */\r
+#define REG_SPI_SR (0x40008010U) /**< \brief (SPI) Status Register */\r
+#define REG_SPI_IER (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */\r
+#define REG_SPI_IDR (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */\r
+#define REG_SPI_IMR (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */\r
+#define REG_SPI_CSR (0x40008030U) /**< \brief (SPI) Chip Select Register */\r
+#define REG_SPI_WPMR (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */\r
+#define REG_SPI_WPSR (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */\r
+#define REG_SPI_RPR (0x40008100U) /**< \brief (SPI) Receive Pointer Register */\r
+#define REG_SPI_RCR (0x40008104U) /**< \brief (SPI) Receive Counter Register */\r
+#define REG_SPI_TPR (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */\r
+#define REG_SPI_TCR (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */\r
+#define REG_SPI_RNPR (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */\r
+#define REG_SPI_RNCR (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */\r
+#define REG_SPI_TNPR (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */\r
+#define REG_SPI_TNCR (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */\r
+#define REG_SPI_PTCR (0x40008120U) /**< \brief (SPI) Transfer Control Register */\r
+#define REG_SPI_PTSR (0x40008124U) /**< \brief (SPI) Transfer Status Register */\r
+#else\r
+#define REG_SPI_CR (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */\r
+#define REG_SPI_MR (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */\r
+#define REG_SPI_RDR (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */\r
+#define REG_SPI_TDR (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */\r
+#define REG_SPI_SR (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */\r
+#define REG_SPI_IER (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */\r
+#define REG_SPI_IDR (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */\r
+#define REG_SPI_IMR (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */\r
+#define REG_SPI_CSR (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */\r
+#define REG_SPI_WPMR (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */\r
+#define REG_SPI_WPSR (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */\r
+#define REG_SPI_RPR (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */\r
+#define REG_SPI_RCR (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */\r
+#define REG_SPI_TPR (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */\r
+#define REG_SPI_TCR (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */\r
+#define REG_SPI_RNPR (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */\r
+#define REG_SPI_RNCR (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */\r
+#define REG_SPI_TNPR (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */\r
+#define REG_SPI_TNCR (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */\r
+#define REG_SPI_PTCR (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */\r
+#define REG_SPI_PTSR (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_SPI_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_SSC_INSTANCE_\r
+#define _SAM3S8_SSC_INSTANCE_\r
+\r
+/* ========== Register definition for SSC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */\r
+#define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */\r
+#define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */\r
+#define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */\r
+#define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */\r
+#define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */\r
+#define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */\r
+#define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */\r
+#define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */\r
+#define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */\r
+#define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */\r
+#define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */\r
+#define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */\r
+#define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */\r
+#define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */\r
+#define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */\r
+#define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */\r
+#define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */\r
+#define REG_SSC_RPR (0x40004100U) /**< \brief (SSC) Receive Pointer Register */\r
+#define REG_SSC_RCR (0x40004104U) /**< \brief (SSC) Receive Counter Register */\r
+#define REG_SSC_TPR (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */\r
+#define REG_SSC_TCR (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */\r
+#define REG_SSC_RNPR (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */\r
+#define REG_SSC_RNCR (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */\r
+#define REG_SSC_TNPR (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */\r
+#define REG_SSC_TNCR (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */\r
+#define REG_SSC_PTCR (0x40004120U) /**< \brief (SSC) Transfer Control Register */\r
+#define REG_SSC_PTSR (0x40004124U) /**< \brief (SSC) Transfer Status Register */\r
+#else\r
+#define REG_SSC_CR (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */\r
+#define REG_SSC_CMR (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */\r
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */\r
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */\r
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */\r
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */\r
+#define REG_SSC_RHR (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */\r
+#define REG_SSC_THR (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */\r
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */\r
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */\r
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */\r
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */\r
+#define REG_SSC_SR (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */\r
+#define REG_SSC_IER (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */\r
+#define REG_SSC_IDR (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */\r
+#define REG_SSC_IMR (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */\r
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */\r
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */\r
+#define REG_SSC_RPR (*(RwReg*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */\r
+#define REG_SSC_RCR (*(RwReg*)0x40004104U) /**< \brief (SSC) Receive Counter Register */\r
+#define REG_SSC_TPR (*(RwReg*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */\r
+#define REG_SSC_TCR (*(RwReg*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */\r
+#define REG_SSC_RNPR (*(RwReg*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */\r
+#define REG_SSC_RNCR (*(RwReg*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */\r
+#define REG_SSC_TNPR (*(RwReg*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */\r
+#define REG_SSC_TNCR (*(RwReg*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */\r
+#define REG_SSC_PTCR (*(WoReg*)0x40004120U) /**< \brief (SSC) Transfer Control Register */\r
+#define REG_SSC_PTSR (*(RoReg*)0x40004124U) /**< \brief (SSC) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_SSC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_SUPC_INSTANCE_\r
+#define _SAM3S8_SUPC_INSTANCE_\r
+\r
+/* ========== Register definition for SUPC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SUPC_CR (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */\r
+#define REG_SUPC_SMMR (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */\r
+#define REG_SUPC_MR (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */\r
+#define REG_SUPC_WUMR (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */\r
+#define REG_SUPC_WUIR (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */\r
+#define REG_SUPC_SR (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */\r
+#else\r
+#define REG_SUPC_CR (*(WoReg*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */\r
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */\r
+#define REG_SUPC_MR (*(RwReg*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */\r
+#define REG_SUPC_WUMR (*(RwReg*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */\r
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */\r
+#define REG_SUPC_SR (*(RoReg*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_SUPC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_TC0_INSTANCE_\r
+#define _SAM3S8_TC0_INSTANCE_\r
+\r
+/* ========== Register definition for TC0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC0_CCR0 (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */\r
+#define REG_TC0_CMR0 (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */\r
+#define REG_TC0_SMMR0 (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC0_CV0 (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */\r
+#define REG_TC0_RA0 (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */\r
+#define REG_TC0_RB0 (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */\r
+#define REG_TC0_RC0 (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */\r
+#define REG_TC0_SR0 (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */\r
+#define REG_TC0_IER0 (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC0_IDR0 (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC0_IMR0 (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC0_CCR1 (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */\r
+#define REG_TC0_CMR1 (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */\r
+#define REG_TC0_SMMR1 (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC0_CV1 (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */\r
+#define REG_TC0_RA1 (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */\r
+#define REG_TC0_RB1 (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */\r
+#define REG_TC0_RC1 (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */\r
+#define REG_TC0_SR1 (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */\r
+#define REG_TC0_IER1 (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC0_IDR1 (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC0_IMR1 (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC0_CCR2 (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */\r
+#define REG_TC0_CMR2 (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */\r
+#define REG_TC0_SMMR2 (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC0_CV2 (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */\r
+#define REG_TC0_RA2 (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */\r
+#define REG_TC0_RB2 (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */\r
+#define REG_TC0_RC2 (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */\r
+#define REG_TC0_SR2 (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */\r
+#define REG_TC0_IER2 (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC0_IDR2 (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC0_IMR2 (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC0_BCR (0x400100C0U) /**< \brief (TC0) Block Control Register */\r
+#define REG_TC0_BMR (0x400100C4U) /**< \brief (TC0) Block Mode Register */\r
+#define REG_TC0_QIER (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */\r
+#define REG_TC0_QIDR (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */\r
+#define REG_TC0_QIMR (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */\r
+#define REG_TC0_QISR (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */\r
+#define REG_TC0_FMR (0x400100D8U) /**< \brief (TC0) Fault Mode Register */\r
+#define REG_TC0_WPMR (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */\r
+#else\r
+#define REG_TC0_CCR0 (*(WoReg*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */\r
+#define REG_TC0_CMR0 (*(RwReg*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */\r
+#define REG_TC0_SMMR0 (*(RwReg*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC0_CV0 (*(RoReg*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */\r
+#define REG_TC0_RA0 (*(RwReg*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */\r
+#define REG_TC0_RB0 (*(RwReg*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */\r
+#define REG_TC0_RC0 (*(RwReg*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */\r
+#define REG_TC0_SR0 (*(RoReg*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */\r
+#define REG_TC0_IER0 (*(WoReg*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC0_IDR0 (*(WoReg*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC0_IMR0 (*(RoReg*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC0_CCR1 (*(WoReg*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */\r
+#define REG_TC0_CMR1 (*(RwReg*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */\r
+#define REG_TC0_SMMR1 (*(RwReg*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC0_CV1 (*(RoReg*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */\r
+#define REG_TC0_RA1 (*(RwReg*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */\r
+#define REG_TC0_RB1 (*(RwReg*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */\r
+#define REG_TC0_RC1 (*(RwReg*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */\r
+#define REG_TC0_SR1 (*(RoReg*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */\r
+#define REG_TC0_IER1 (*(WoReg*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC0_IDR1 (*(WoReg*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC0_IMR1 (*(RoReg*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC0_CCR2 (*(WoReg*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */\r
+#define REG_TC0_CMR2 (*(RwReg*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */\r
+#define REG_TC0_SMMR2 (*(RwReg*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC0_CV2 (*(RoReg*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */\r
+#define REG_TC0_RA2 (*(RwReg*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */\r
+#define REG_TC0_RB2 (*(RwReg*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */\r
+#define REG_TC0_RC2 (*(RwReg*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */\r
+#define REG_TC0_SR2 (*(RoReg*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */\r
+#define REG_TC0_IER2 (*(WoReg*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC0_IDR2 (*(WoReg*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC0_IMR2 (*(RoReg*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC0_BCR (*(WoReg*)0x400100C0U) /**< \brief (TC0) Block Control Register */\r
+#define REG_TC0_BMR (*(RwReg*)0x400100C4U) /**< \brief (TC0) Block Mode Register */\r
+#define REG_TC0_QIER (*(WoReg*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */\r
+#define REG_TC0_QIDR (*(WoReg*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */\r
+#define REG_TC0_QIMR (*(RoReg*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */\r
+#define REG_TC0_QISR (*(RoReg*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */\r
+#define REG_TC0_FMR (*(RwReg*)0x400100D8U) /**< \brief (TC0) Fault Mode Register */\r
+#define REG_TC0_WPMR (*(RwReg*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_TC0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_TC1_INSTANCE_\r
+#define _SAM3S8_TC1_INSTANCE_\r
+\r
+/* ========== Register definition for TC1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC1_CCR0 (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */\r
+#define REG_TC1_CMR0 (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */\r
+#define REG_TC1_SMMR0 (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC1_CV0 (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */\r
+#define REG_TC1_RA0 (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */\r
+#define REG_TC1_RB0 (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */\r
+#define REG_TC1_RC0 (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */\r
+#define REG_TC1_SR0 (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */\r
+#define REG_TC1_IER0 (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC1_IDR0 (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC1_IMR0 (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC1_CCR1 (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */\r
+#define REG_TC1_CMR1 (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */\r
+#define REG_TC1_SMMR1 (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC1_CV1 (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */\r
+#define REG_TC1_RA1 (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */\r
+#define REG_TC1_RB1 (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */\r
+#define REG_TC1_RC1 (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */\r
+#define REG_TC1_SR1 (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */\r
+#define REG_TC1_IER1 (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC1_IDR1 (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC1_IMR1 (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC1_CCR2 (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */\r
+#define REG_TC1_CMR2 (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */\r
+#define REG_TC1_SMMR2 (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC1_CV2 (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */\r
+#define REG_TC1_RA2 (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */\r
+#define REG_TC1_RB2 (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */\r
+#define REG_TC1_RC2 (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */\r
+#define REG_TC1_SR2 (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */\r
+#define REG_TC1_IER2 (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC1_IDR2 (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC1_IMR2 (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC1_BCR (0x400140C0U) /**< \brief (TC1) Block Control Register */\r
+#define REG_TC1_BMR (0x400140C4U) /**< \brief (TC1) Block Mode Register */\r
+#define REG_TC1_QIER (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */\r
+#define REG_TC1_QIDR (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */\r
+#define REG_TC1_QIMR (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */\r
+#define REG_TC1_QISR (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */\r
+#define REG_TC1_FMR (0x400140D8U) /**< \brief (TC1) Fault Mode Register */\r
+#define REG_TC1_WPMR (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */\r
+#else\r
+#define REG_TC1_CCR0 (*(WoReg*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */\r
+#define REG_TC1_CMR0 (*(RwReg*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */\r
+#define REG_TC1_SMMR0 (*(RwReg*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC1_CV0 (*(RoReg*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */\r
+#define REG_TC1_RA0 (*(RwReg*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */\r
+#define REG_TC1_RB0 (*(RwReg*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */\r
+#define REG_TC1_RC0 (*(RwReg*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */\r
+#define REG_TC1_SR0 (*(RoReg*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */\r
+#define REG_TC1_IER0 (*(WoReg*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC1_IDR0 (*(WoReg*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC1_IMR0 (*(RoReg*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC1_CCR1 (*(WoReg*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */\r
+#define REG_TC1_CMR1 (*(RwReg*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */\r
+#define REG_TC1_SMMR1 (*(RwReg*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC1_CV1 (*(RoReg*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */\r
+#define REG_TC1_RA1 (*(RwReg*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */\r
+#define REG_TC1_RB1 (*(RwReg*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */\r
+#define REG_TC1_RC1 (*(RwReg*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */\r
+#define REG_TC1_SR1 (*(RoReg*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */\r
+#define REG_TC1_IER1 (*(WoReg*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC1_IDR1 (*(WoReg*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC1_IMR1 (*(RoReg*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC1_CCR2 (*(WoReg*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */\r
+#define REG_TC1_CMR2 (*(RwReg*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */\r
+#define REG_TC1_SMMR2 (*(RwReg*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC1_CV2 (*(RoReg*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */\r
+#define REG_TC1_RA2 (*(RwReg*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */\r
+#define REG_TC1_RB2 (*(RwReg*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */\r
+#define REG_TC1_RC2 (*(RwReg*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */\r
+#define REG_TC1_SR2 (*(RoReg*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */\r
+#define REG_TC1_IER2 (*(WoReg*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC1_IDR2 (*(WoReg*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC1_IMR2 (*(RoReg*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC1_BCR (*(WoReg*)0x400140C0U) /**< \brief (TC1) Block Control Register */\r
+#define REG_TC1_BMR (*(RwReg*)0x400140C4U) /**< \brief (TC1) Block Mode Register */\r
+#define REG_TC1_QIER (*(WoReg*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */\r
+#define REG_TC1_QIDR (*(WoReg*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */\r
+#define REG_TC1_QIMR (*(RoReg*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */\r
+#define REG_TC1_QISR (*(RoReg*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */\r
+#define REG_TC1_FMR (*(RwReg*)0x400140D8U) /**< \brief (TC1) Fault Mode Register */\r
+#define REG_TC1_WPMR (*(RwReg*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_TC1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_TWI0_INSTANCE_\r
+#define _SAM3S8_TWI0_INSTANCE_\r
+\r
+/* ========== Register definition for TWI0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TWI0_CR (0x40018000U) /**< \brief (TWI0) Control Register */\r
+#define REG_TWI0_MMR (0x40018004U) /**< \brief (TWI0) Master Mode Register */\r
+#define REG_TWI0_SMR (0x40018008U) /**< \brief (TWI0) Slave Mode Register */\r
+#define REG_TWI0_IADR (0x4001800CU) /**< \brief (TWI0) Internal Address Register */\r
+#define REG_TWI0_CWGR (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */\r
+#define REG_TWI0_SR (0x40018020U) /**< \brief (TWI0) Status Register */\r
+#define REG_TWI0_IER (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */\r
+#define REG_TWI0_IDR (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */\r
+#define REG_TWI0_IMR (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */\r
+#define REG_TWI0_RHR (0x40018030U) /**< \brief (TWI0) Receive Holding Register */\r
+#define REG_TWI0_THR (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */\r
+#define REG_TWI0_RPR (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */\r
+#define REG_TWI0_RCR (0x40018104U) /**< \brief (TWI0) Receive Counter Register */\r
+#define REG_TWI0_TPR (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */\r
+#define REG_TWI0_TCR (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */\r
+#define REG_TWI0_RNPR (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */\r
+#define REG_TWI0_RNCR (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */\r
+#define REG_TWI0_TNPR (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */\r
+#define REG_TWI0_TNCR (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */\r
+#define REG_TWI0_PTCR (0x40018120U) /**< \brief (TWI0) Transfer Control Register */\r
+#define REG_TWI0_PTSR (0x40018124U) /**< \brief (TWI0) Transfer Status Register */\r
+#else\r
+#define REG_TWI0_CR (*(WoReg*)0x40018000U) /**< \brief (TWI0) Control Register */\r
+#define REG_TWI0_MMR (*(RwReg*)0x40018004U) /**< \brief (TWI0) Master Mode Register */\r
+#define REG_TWI0_SMR (*(RwReg*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */\r
+#define REG_TWI0_IADR (*(RwReg*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */\r
+#define REG_TWI0_CWGR (*(RwReg*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */\r
+#define REG_TWI0_SR (*(RoReg*)0x40018020U) /**< \brief (TWI0) Status Register */\r
+#define REG_TWI0_IER (*(WoReg*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */\r
+#define REG_TWI0_IDR (*(WoReg*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */\r
+#define REG_TWI0_IMR (*(RoReg*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */\r
+#define REG_TWI0_RHR (*(RoReg*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */\r
+#define REG_TWI0_THR (*(WoReg*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */\r
+#define REG_TWI0_RPR (*(RwReg*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */\r
+#define REG_TWI0_RCR (*(RwReg*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */\r
+#define REG_TWI0_TPR (*(RwReg*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */\r
+#define REG_TWI0_TCR (*(RwReg*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */\r
+#define REG_TWI0_RNPR (*(RwReg*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */\r
+#define REG_TWI0_RNCR (*(RwReg*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */\r
+#define REG_TWI0_TNPR (*(RwReg*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */\r
+#define REG_TWI0_TNCR (*(RwReg*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */\r
+#define REG_TWI0_PTCR (*(WoReg*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */\r
+#define REG_TWI0_PTSR (*(RoReg*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_TWI0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_TWI1_INSTANCE_\r
+#define _SAM3S8_TWI1_INSTANCE_\r
+\r
+/* ========== Register definition for TWI1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TWI1_CR (0x4001C000U) /**< \brief (TWI1) Control Register */\r
+#define REG_TWI1_MMR (0x4001C004U) /**< \brief (TWI1) Master Mode Register */\r
+#define REG_TWI1_SMR (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */\r
+#define REG_TWI1_IADR (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */\r
+#define REG_TWI1_CWGR (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */\r
+#define REG_TWI1_SR (0x4001C020U) /**< \brief (TWI1) Status Register */\r
+#define REG_TWI1_IER (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */\r
+#define REG_TWI1_IDR (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */\r
+#define REG_TWI1_IMR (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */\r
+#define REG_TWI1_RHR (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */\r
+#define REG_TWI1_THR (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */\r
+#define REG_TWI1_RPR (0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */\r
+#define REG_TWI1_RCR (0x4001C104U) /**< \brief (TWI1) Receive Counter Register */\r
+#define REG_TWI1_TPR (0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */\r
+#define REG_TWI1_TCR (0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */\r
+#define REG_TWI1_RNPR (0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */\r
+#define REG_TWI1_RNCR (0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */\r
+#define REG_TWI1_TNPR (0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */\r
+#define REG_TWI1_TNCR (0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */\r
+#define REG_TWI1_PTCR (0x4001C120U) /**< \brief (TWI1) Transfer Control Register */\r
+#define REG_TWI1_PTSR (0x4001C124U) /**< \brief (TWI1) Transfer Status Register */\r
+#else\r
+#define REG_TWI1_CR (*(WoReg*)0x4001C000U) /**< \brief (TWI1) Control Register */\r
+#define REG_TWI1_MMR (*(RwReg*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */\r
+#define REG_TWI1_SMR (*(RwReg*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */\r
+#define REG_TWI1_IADR (*(RwReg*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */\r
+#define REG_TWI1_CWGR (*(RwReg*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */\r
+#define REG_TWI1_SR (*(RoReg*)0x4001C020U) /**< \brief (TWI1) Status Register */\r
+#define REG_TWI1_IER (*(WoReg*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */\r
+#define REG_TWI1_IDR (*(WoReg*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */\r
+#define REG_TWI1_IMR (*(RoReg*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */\r
+#define REG_TWI1_RHR (*(RoReg*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */\r
+#define REG_TWI1_THR (*(WoReg*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */\r
+#define REG_TWI1_RPR (*(RwReg*)0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */\r
+#define REG_TWI1_RCR (*(RwReg*)0x4001C104U) /**< \brief (TWI1) Receive Counter Register */\r
+#define REG_TWI1_TPR (*(RwReg*)0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */\r
+#define REG_TWI1_TCR (*(RwReg*)0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */\r
+#define REG_TWI1_RNPR (*(RwReg*)0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */\r
+#define REG_TWI1_RNCR (*(RwReg*)0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */\r
+#define REG_TWI1_TNPR (*(RwReg*)0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */\r
+#define REG_TWI1_TNCR (*(RwReg*)0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */\r
+#define REG_TWI1_PTCR (*(WoReg*)0x4001C120U) /**< \brief (TWI1) Transfer Control Register */\r
+#define REG_TWI1_PTSR (*(RoReg*)0x4001C124U) /**< \brief (TWI1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_TWI1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_UART0_INSTANCE_\r
+#define _SAM3S8_UART0_INSTANCE_\r
+\r
+/* ========== Register definition for UART0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UART0_CR (0x400E0600U) /**< \brief (UART0) Control Register */\r
+#define REG_UART0_MR (0x400E0604U) /**< \brief (UART0) Mode Register */\r
+#define REG_UART0_IER (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */\r
+#define REG_UART0_IDR (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */\r
+#define REG_UART0_IMR (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */\r
+#define REG_UART0_SR (0x400E0614U) /**< \brief (UART0) Status Register */\r
+#define REG_UART0_RHR (0x400E0618U) /**< \brief (UART0) Receive Holding Register */\r
+#define REG_UART0_THR (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */\r
+#define REG_UART0_BRGR (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */\r
+#define REG_UART0_RPR (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */\r
+#define REG_UART0_RCR (0x400E0704U) /**< \brief (UART0) Receive Counter Register */\r
+#define REG_UART0_TPR (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */\r
+#define REG_UART0_TCR (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */\r
+#define REG_UART0_RNPR (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */\r
+#define REG_UART0_RNCR (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */\r
+#define REG_UART0_TNPR (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */\r
+#define REG_UART0_TNCR (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */\r
+#define REG_UART0_PTCR (0x400E0720U) /**< \brief (UART0) Transfer Control Register */\r
+#define REG_UART0_PTSR (0x400E0724U) /**< \brief (UART0) Transfer Status Register */\r
+#else\r
+#define REG_UART0_CR (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */\r
+#define REG_UART0_MR (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */\r
+#define REG_UART0_IER (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */\r
+#define REG_UART0_IDR (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */\r
+#define REG_UART0_IMR (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */\r
+#define REG_UART0_SR (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */\r
+#define REG_UART0_RHR (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */\r
+#define REG_UART0_THR (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */\r
+#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */\r
+#define REG_UART0_RPR (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */\r
+#define REG_UART0_RCR (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */\r
+#define REG_UART0_TPR (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */\r
+#define REG_UART0_TCR (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */\r
+#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */\r
+#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */\r
+#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */\r
+#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */\r
+#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */\r
+#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_UART0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_UART1_INSTANCE_\r
+#define _SAM3S8_UART1_INSTANCE_\r
+\r
+/* ========== Register definition for UART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UART1_CR (0x400E0800U) /**< \brief (UART1) Control Register */\r
+#define REG_UART1_MR (0x400E0804U) /**< \brief (UART1) Mode Register */\r
+#define REG_UART1_IER (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */\r
+#define REG_UART1_IDR (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */\r
+#define REG_UART1_IMR (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */\r
+#define REG_UART1_SR (0x400E0814U) /**< \brief (UART1) Status Register */\r
+#define REG_UART1_RHR (0x400E0818U) /**< \brief (UART1) Receive Holding Register */\r
+#define REG_UART1_THR (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */\r
+#define REG_UART1_BRGR (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */\r
+#define REG_UART1_RPR (0x400E0900U) /**< \brief (UART1) Receive Pointer Register */\r
+#define REG_UART1_RCR (0x400E0904U) /**< \brief (UART1) Receive Counter Register */\r
+#define REG_UART1_TPR (0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */\r
+#define REG_UART1_TCR (0x400E090CU) /**< \brief (UART1) Transmit Counter Register */\r
+#define REG_UART1_RNPR (0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */\r
+#define REG_UART1_RNCR (0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */\r
+#define REG_UART1_TNPR (0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */\r
+#define REG_UART1_TNCR (0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */\r
+#define REG_UART1_PTCR (0x400E0920U) /**< \brief (UART1) Transfer Control Register */\r
+#define REG_UART1_PTSR (0x400E0924U) /**< \brief (UART1) Transfer Status Register */\r
+#else\r
+#define REG_UART1_CR (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */\r
+#define REG_UART1_MR (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */\r
+#define REG_UART1_IER (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */\r
+#define REG_UART1_IDR (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */\r
+#define REG_UART1_IMR (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */\r
+#define REG_UART1_SR (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */\r
+#define REG_UART1_RHR (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */\r
+#define REG_UART1_THR (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */\r
+#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */\r
+#define REG_UART1_RPR (*(RwReg*)0x400E0900U) /**< \brief (UART1) Receive Pointer Register */\r
+#define REG_UART1_RCR (*(RwReg*)0x400E0904U) /**< \brief (UART1) Receive Counter Register */\r
+#define REG_UART1_TPR (*(RwReg*)0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */\r
+#define REG_UART1_TCR (*(RwReg*)0x400E090CU) /**< \brief (UART1) Transmit Counter Register */\r
+#define REG_UART1_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */\r
+#define REG_UART1_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */\r
+#define REG_UART1_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */\r
+#define REG_UART1_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */\r
+#define REG_UART1_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART1) Transfer Control Register */\r
+#define REG_UART1_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_UART1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_UDP_INSTANCE_\r
+#define _SAM3S8_UDP_INSTANCE_\r
+\r
+/* ========== Register definition for UDP peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UDP_FRM_NUM (0x40034000U) /**< \brief (UDP) Frame Number Register */\r
+#define REG_UDP_GLB_STAT (0x40034004U) /**< \brief (UDP) Global State Register */\r
+#define REG_UDP_FADDR (0x40034008U) /**< \brief (UDP) Function Address Register */\r
+#define REG_UDP_IER (0x40034010U) /**< \brief (UDP) Interrupt Enable Register */\r
+#define REG_UDP_IDR (0x40034014U) /**< \brief (UDP) Interrupt Disable Register */\r
+#define REG_UDP_IMR (0x40034018U) /**< \brief (UDP) Interrupt Mask Register */\r
+#define REG_UDP_ISR (0x4003401CU) /**< \brief (UDP) Interrupt Status Register */\r
+#define REG_UDP_ICR (0x40034020U) /**< \brief (UDP) Interrupt Clear Register */\r
+#define REG_UDP_RST_EP (0x40034028U) /**< \brief (UDP) Reset Endpoint Register */\r
+#define REG_UDP_CSR (0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */\r
+#define REG_UDP_FDR (0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */\r
+#define REG_UDP_TXVC (0x40034074U) /**< \brief (UDP) Transceiver Control Register */\r
+#else\r
+#define REG_UDP_FRM_NUM (*(RoReg*)0x40034000U) /**< \brief (UDP) Frame Number Register */\r
+#define REG_UDP_GLB_STAT (*(RwReg*)0x40034004U) /**< \brief (UDP) Global State Register */\r
+#define REG_UDP_FADDR (*(RwReg*)0x40034008U) /**< \brief (UDP) Function Address Register */\r
+#define REG_UDP_IER (*(WoReg*)0x40034010U) /**< \brief (UDP) Interrupt Enable Register */\r
+#define REG_UDP_IDR (*(WoReg*)0x40034014U) /**< \brief (UDP) Interrupt Disable Register */\r
+#define REG_UDP_IMR (*(RoReg*)0x40034018U) /**< \brief (UDP) Interrupt Mask Register */\r
+#define REG_UDP_ISR (*(RoReg*)0x4003401CU) /**< \brief (UDP) Interrupt Status Register */\r
+#define REG_UDP_ICR (*(WoReg*)0x40034020U) /**< \brief (UDP) Interrupt Clear Register */\r
+#define REG_UDP_RST_EP (*(RwReg*)0x40034028U) /**< \brief (UDP) Reset Endpoint Register */\r
+#define REG_UDP_CSR (*(RwReg*)0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */\r
+#define REG_UDP_FDR (*(RwReg*)0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */\r
+#define REG_UDP_TXVC (*(RwReg*)0x40034074U) /**< \brief (UDP) Transceiver Control Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_UDP_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_USART0_INSTANCE_\r
+#define _SAM3S8_USART0_INSTANCE_\r
+\r
+/* ========== Register definition for USART0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */\r
+#define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */\r
+#define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */\r
+#define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */\r
+#define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */\r
+#define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */\r
+#define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receiver Holding Register */\r
+#define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */\r
+#define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+#define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */\r
+#define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+#define REG_USART0_FIDI (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */\r
+#define REG_USART0_NER (0x40024044U) /**< \brief (USART0) Number of Errors Register */\r
+#define REG_USART0_IF (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */\r
+#define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */\r
+#define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */\r
+#define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */\r
+#define REG_USART0_VERSION (0x400240FCU) /**< \brief (USART0) Version Register */\r
+#define REG_USART0_RPR (0x40024100U) /**< \brief (USART0) Receive Pointer Register */\r
+#define REG_USART0_RCR (0x40024104U) /**< \brief (USART0) Receive Counter Register */\r
+#define REG_USART0_TPR (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */\r
+#define REG_USART0_TCR (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */\r
+#define REG_USART0_RNPR (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */\r
+#define REG_USART0_RNCR (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */\r
+#define REG_USART0_TNPR (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */\r
+#define REG_USART0_TNCR (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */\r
+#define REG_USART0_PTCR (0x40024120U) /**< \brief (USART0) Transfer Control Register */\r
+#define REG_USART0_PTSR (0x40024124U) /**< \brief (USART0) Transfer Status Register */\r
+#else\r
+#define REG_USART0_CR (*(WoReg*)0x40024000U) /**< \brief (USART0) Control Register */\r
+#define REG_USART0_MR (*(RwReg*)0x40024004U) /**< \brief (USART0) Mode Register */\r
+#define REG_USART0_IER (*(WoReg*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */\r
+#define REG_USART0_IDR (*(WoReg*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */\r
+#define REG_USART0_IMR (*(RoReg*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */\r
+#define REG_USART0_CSR (*(RoReg*)0x40024014U) /**< \brief (USART0) Channel Status Register */\r
+#define REG_USART0_RHR (*(RoReg*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */\r
+#define REG_USART0_THR (*(WoReg*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */\r
+#define REG_USART0_BRGR (*(RwReg*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+#define REG_USART0_RTOR (*(RwReg*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */\r
+#define REG_USART0_TTGR (*(RwReg*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+#define REG_USART0_FIDI (*(RwReg*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */\r
+#define REG_USART0_NER (*(RoReg*)0x40024044U) /**< \brief (USART0) Number of Errors Register */\r
+#define REG_USART0_IF (*(RwReg*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */\r
+#define REG_USART0_MAN (*(RwReg*)0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */\r
+#define REG_USART0_WPMR (*(RwReg*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */\r
+#define REG_USART0_WPSR (*(RoReg*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */\r
+#define REG_USART0_VERSION (*(RoReg*)0x400240FCU) /**< \brief (USART0) Version Register */\r
+#define REG_USART0_RPR (*(RwReg*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */\r
+#define REG_USART0_RCR (*(RwReg*)0x40024104U) /**< \brief (USART0) Receive Counter Register */\r
+#define REG_USART0_TPR (*(RwReg*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */\r
+#define REG_USART0_TCR (*(RwReg*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */\r
+#define REG_USART0_RNPR (*(RwReg*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */\r
+#define REG_USART0_RNCR (*(RwReg*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */\r
+#define REG_USART0_TNPR (*(RwReg*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */\r
+#define REG_USART0_TNCR (*(RwReg*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */\r
+#define REG_USART0_PTCR (*(WoReg*)0x40024120U) /**< \brief (USART0) Transfer Control Register */\r
+#define REG_USART0_PTSR (*(RoReg*)0x40024124U) /**< \brief (USART0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_USART0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_USART1_INSTANCE_\r
+#define _SAM3S8_USART1_INSTANCE_\r
+\r
+/* ========== Register definition for USART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */\r
+#define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */\r
+#define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */\r
+#define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */\r
+#define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */\r
+#define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */\r
+#define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receiver Holding Register */\r
+#define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */\r
+#define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+#define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */\r
+#define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+#define REG_USART1_FIDI (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */\r
+#define REG_USART1_NER (0x40028044U) /**< \brief (USART1) Number of Errors Register */\r
+#define REG_USART1_IF (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */\r
+#define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */\r
+#define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */\r
+#define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */\r
+#define REG_USART1_VERSION (0x400280FCU) /**< \brief (USART1) Version Register */\r
+#define REG_USART1_RPR (0x40028100U) /**< \brief (USART1) Receive Pointer Register */\r
+#define REG_USART1_RCR (0x40028104U) /**< \brief (USART1) Receive Counter Register */\r
+#define REG_USART1_TPR (0x40028108U) /**< \brief (USART1) Transmit Pointer Register */\r
+#define REG_USART1_TCR (0x4002810CU) /**< \brief (USART1) Transmit Counter Register */\r
+#define REG_USART1_RNPR (0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */\r
+#define REG_USART1_RNCR (0x40028114U) /**< \brief (USART1) Receive Next Counter Register */\r
+#define REG_USART1_TNPR (0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */\r
+#define REG_USART1_TNCR (0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */\r
+#define REG_USART1_PTCR (0x40028120U) /**< \brief (USART1) Transfer Control Register */\r
+#define REG_USART1_PTSR (0x40028124U) /**< \brief (USART1) Transfer Status Register */\r
+#else\r
+#define REG_USART1_CR (*(WoReg*)0x40028000U) /**< \brief (USART1) Control Register */\r
+#define REG_USART1_MR (*(RwReg*)0x40028004U) /**< \brief (USART1) Mode Register */\r
+#define REG_USART1_IER (*(WoReg*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */\r
+#define REG_USART1_IDR (*(WoReg*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */\r
+#define REG_USART1_IMR (*(RoReg*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */\r
+#define REG_USART1_CSR (*(RoReg*)0x40028014U) /**< \brief (USART1) Channel Status Register */\r
+#define REG_USART1_RHR (*(RoReg*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */\r
+#define REG_USART1_THR (*(WoReg*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */\r
+#define REG_USART1_BRGR (*(RwReg*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+#define REG_USART1_RTOR (*(RwReg*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */\r
+#define REG_USART1_TTGR (*(RwReg*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+#define REG_USART1_FIDI (*(RwReg*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */\r
+#define REG_USART1_NER (*(RoReg*)0x40028044U) /**< \brief (USART1) Number of Errors Register */\r
+#define REG_USART1_IF (*(RwReg*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */\r
+#define REG_USART1_MAN (*(RwReg*)0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */\r
+#define REG_USART1_WPMR (*(RwReg*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */\r
+#define REG_USART1_WPSR (*(RoReg*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */\r
+#define REG_USART1_VERSION (*(RoReg*)0x400280FCU) /**< \brief (USART1) Version Register */\r
+#define REG_USART1_RPR (*(RwReg*)0x40028100U) /**< \brief (USART1) Receive Pointer Register */\r
+#define REG_USART1_RCR (*(RwReg*)0x40028104U) /**< \brief (USART1) Receive Counter Register */\r
+#define REG_USART1_TPR (*(RwReg*)0x40028108U) /**< \brief (USART1) Transmit Pointer Register */\r
+#define REG_USART1_TCR (*(RwReg*)0x4002810CU) /**< \brief (USART1) Transmit Counter Register */\r
+#define REG_USART1_RNPR (*(RwReg*)0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */\r
+#define REG_USART1_RNCR (*(RwReg*)0x40028114U) /**< \brief (USART1) Receive Next Counter Register */\r
+#define REG_USART1_TNPR (*(RwReg*)0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */\r
+#define REG_USART1_TNCR (*(RwReg*)0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */\r
+#define REG_USART1_PTCR (*(WoReg*)0x40028120U) /**< \brief (USART1) Transfer Control Register */\r
+#define REG_USART1_PTSR (*(RoReg*)0x40028124U) /**< \brief (USART1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_USART1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_USART2_INSTANCE_\r
+#define _SAM3S8_USART2_INSTANCE_\r
+\r
+/* ========== Register definition for USART2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */\r
+#define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */\r
+#define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */\r
+#define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */\r
+#define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */\r
+#define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */\r
+#define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receiver Holding Register */\r
+#define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */\r
+#define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */\r
+#define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */\r
+#define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */\r
+#define REG_USART2_FIDI (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */\r
+#define REG_USART2_NER (0x4002C044U) /**< \brief (USART2) Number of Errors Register */\r
+#define REG_USART2_IF (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */\r
+#define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */\r
+#define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */\r
+#define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */\r
+#define REG_USART2_VERSION (0x4002C0FCU) /**< \brief (USART2) Version Register */\r
+#define REG_USART2_RPR (0x4002C100U) /**< \brief (USART2) Receive Pointer Register */\r
+#define REG_USART2_RCR (0x4002C104U) /**< \brief (USART2) Receive Counter Register */\r
+#define REG_USART2_TPR (0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */\r
+#define REG_USART2_TCR (0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */\r
+#define REG_USART2_RNPR (0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */\r
+#define REG_USART2_RNCR (0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */\r
+#define REG_USART2_TNPR (0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */\r
+#define REG_USART2_TNCR (0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */\r
+#define REG_USART2_PTCR (0x4002C120U) /**< \brief (USART2) Transfer Control Register */\r
+#define REG_USART2_PTSR (0x4002C124U) /**< \brief (USART2) Transfer Status Register */\r
+#else\r
+#define REG_USART2_CR (*(WoReg*)0x4002C000U) /**< \brief (USART2) Control Register */\r
+#define REG_USART2_MR (*(RwReg*)0x4002C004U) /**< \brief (USART2) Mode Register */\r
+#define REG_USART2_IER (*(WoReg*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */\r
+#define REG_USART2_IDR (*(WoReg*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */\r
+#define REG_USART2_IMR (*(RoReg*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */\r
+#define REG_USART2_CSR (*(RoReg*)0x4002C014U) /**< \brief (USART2) Channel Status Register */\r
+#define REG_USART2_RHR (*(RoReg*)0x4002C018U) /**< \brief (USART2) Receiver Holding Register */\r
+#define REG_USART2_THR (*(WoReg*)0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */\r
+#define REG_USART2_BRGR (*(RwReg*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */\r
+#define REG_USART2_RTOR (*(RwReg*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */\r
+#define REG_USART2_TTGR (*(RwReg*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */\r
+#define REG_USART2_FIDI (*(RwReg*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */\r
+#define REG_USART2_NER (*(RoReg*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */\r
+#define REG_USART2_IF (*(RwReg*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */\r
+#define REG_USART2_MAN (*(RwReg*)0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */\r
+#define REG_USART2_WPMR (*(RwReg*)0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */\r
+#define REG_USART2_WPSR (*(RoReg*)0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */\r
+#define REG_USART2_VERSION (*(RoReg*)0x4002C0FCU) /**< \brief (USART2) Version Register */\r
+#define REG_USART2_RPR (*(RwReg*)0x4002C100U) /**< \brief (USART2) Receive Pointer Register */\r
+#define REG_USART2_RCR (*(RwReg*)0x4002C104U) /**< \brief (USART2) Receive Counter Register */\r
+#define REG_USART2_TPR (*(RwReg*)0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */\r
+#define REG_USART2_TCR (*(RwReg*)0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */\r
+#define REG_USART2_RNPR (*(RwReg*)0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */\r
+#define REG_USART2_RNCR (*(RwReg*)0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */\r
+#define REG_USART2_TNPR (*(RwReg*)0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */\r
+#define REG_USART2_TNCR (*(RwReg*)0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */\r
+#define REG_USART2_PTCR (*(WoReg*)0x4002C120U) /**< \brief (USART2) Transfer Control Register */\r
+#define REG_USART2_PTSR (*(RoReg*)0x4002C124U) /**< \brief (USART2) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_USART2_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_WDT_INSTANCE_\r
+#define _SAM3S8_WDT_INSTANCE_\r
+\r
+/* ========== Register definition for WDT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_WDT_CR (0x400E1450U) /**< \brief (WDT) Control Register */\r
+#define REG_WDT_MR (0x400E1454U) /**< \brief (WDT) Mode Register */\r
+#define REG_WDT_SR (0x400E1458U) /**< \brief (WDT) Status Register */\r
+#else\r
+#define REG_WDT_CR (*(WoReg*)0x400E1450U) /**< \brief (WDT) Control Register */\r
+#define REG_WDT_MR (*(RwReg*)0x400E1454U) /**< \brief (WDT) Mode Register */\r
+#define REG_WDT_SR (*(RoReg*)0x400E1458U) /**< \brief (WDT) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3S8_WDT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3SD8C_PIO_\r
+#define _SAM3SD8C_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */\r
+#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */\r
+#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */\r
+#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */\r
+#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */\r
+#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */\r
+#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */\r
+#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */\r
+#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */\r
+#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */\r
+#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */\r
+#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */\r
+#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */\r
+#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */\r
+#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */\r
+#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */\r
+#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */\r
+#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */\r
+#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */\r
+#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */\r
+#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */\r
+#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */\r
+#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */\r
+#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */\r
+#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */\r
+#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */\r
+#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */\r
+#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */\r
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for SPI peripheral ========== */\r
+#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */\r
+#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */\r
+#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */\r
+#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */\r
+#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */\r
+#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */\r
+#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */\r
+#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */\r
+#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PC17B_CTS2 (1u << 17) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PC16B_RTS2 (1u << 16) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PC9B_RXD2 (1u << 9) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PC14B_SCK2 (1u << 14) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PC10B_TXD2 (1u << 10) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PC31_IDX 95\r
+\r
+#endif /* _SAM3SD8C_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3S8_\r
+#define _SAM3S8_\r
+\r
+#if defined __SAM3SD8B__\r
+ #include "sam3sd8b.h"\r
+#elif defined __SAM3SD8C__\r
+ #include "sam3sd8c.h"\r
+#elif defined __SAM3S8B__\r
+ #include "sam3s8b.h"\r
+#elif defined __SAM3S8C__\r
+ #include "sam3s8c.h"\r
+#else\r
+ #error Library does not support the specified device.\r
+#endif\r
+\r
+#endif /* _SAM3S8_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3SD8C_\r
+#define _SAM3SD8C_\r
+\r
+/** \addtogroup SAM3SD8C_definitions SAM3SD8C definitions\r
+ This file defines all structures and symbols for SAM3SD8C:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM3SD8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3SD8C_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */\r
+/****** SAM3SD8C specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM3SD8C Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM3SD8C Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM3SD8C Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM3SD8C Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM3SD8C Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM3SD8C Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAM3SD8C Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 8, /**< 8 SAM3SD8C UART 0 (UART0) */\r
+ UART1_IRQn = 9, /**< 9 SAM3SD8C UART 1 (UART1) */\r
+ SMC_IRQn = 10, /**< 10 SAM3SD8C Static Memory Controller (SMC) */\r
+ PIOA_IRQn = 11, /**< 11 SAM3SD8C Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 12, /**< 12 SAM3SD8C Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 13, /**< 13 SAM3SD8C Parallel I/O Controller C (PIOC) */\r
+ USART0_IRQn = 14, /**< 14 SAM3SD8C USART 0 (USART0) */\r
+ USART1_IRQn = 15, /**< 15 SAM3SD8C USART 1 (USART1) */\r
+ USART2_IRQn = 16, /**< 16 SAM3SD8C USART 2 (SAM3SD8 100 pins only) (USART2) */\r
+ HSMCI_IRQn = 18, /**< 18 SAM3SD8C Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAM3SD8C Two Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAM3SD8C Two Wire Interface 1 (TWI1) */\r
+ SPI_IRQn = 21, /**< 21 SAM3SD8C Serial Peripheral Interface (SPI) */\r
+ SSC_IRQn = 22, /**< 22 SAM3SD8C Synchronous Serial Controler (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAM3SD8C Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAM3SD8C Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAM3SD8C Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 26, /**< 26 SAM3SD8C Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 27, /**< 27 SAM3SD8C Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 28, /**< 28 SAM3SD8C Timer/Counter 5 (TC5) */\r
+ ADC_IRQn = 29, /**< 29 SAM3SD8C Analog To Digital Converter (ADC) */\r
+ DACC_IRQn = 30, /**< 30 SAM3SD8C Digital To Analog Converter (DACC) */\r
+ PWM_IRQn = 31, /**< 31 SAM3SD8C Pulse Width Modulation (PWM) */\r
+ CRCCU_IRQn = 32, /**< 32 SAM3SD8C CRC Calculation Unit (CRCCU) */\r
+ ACC_IRQn = 33, /**< 33 SAM3SD8C Analog Comparator (ACC) */\r
+ UDP_IRQn = 34 /**< 34 SAM3SD8C USB Device Port (UDP) */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pvReserved7;\r
+ void* pfnUART0_Handler; /* 8 UART 0 */\r
+ void* pfnUART1_Handler; /* 9 UART 1 */\r
+ void* pfnSMC_Handler; /* 10 Static Memory Controller */\r
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */\r
+ void* pfnUSART0_Handler; /* 14 USART 0 */\r
+ void* pfnUSART1_Handler; /* 15 USART 1 */\r
+ void* pfnUSART2_Handler; /* 16 USART 2 (SAM3SD8 100 pins only) */\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */\r
+ void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */\r
+ void* pfnADC_Handler; /* 29 Analog To Digital Converter */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM_Handler; /* 31 Pulse Width Modulation */\r
+ void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUDP_Handler; /* 34 USB Device Port */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void ADC_Handler ( void );\r
+void CRCCU_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SMC_Handler ( void );\r
+void SPI_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UDP_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM3_REV 0x0200 /**< SAM3SD8C core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAM3SD8C does provide a MPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM3SD8C uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm3.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam3sd8.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3SD8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3SD8C_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_crccu.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pdc.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_udp.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM3SD8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3SD8C_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_udp.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_crccu.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM3SD8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3SD8C_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */\r
+#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (16) /**< \brief USART 2 (SAM3SD8 100 pins only) (USART2) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */\r
+#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */\r
+#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_UDP (34) /**< \brief USB Device Port (UDP) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM3SD8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3SD8C_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */\r
+#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 (0x4002C100U) /**< \brief (PDC_USART2) Base Address */\r
+#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */\r
+#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */\r
+#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */\r
+#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 ((Pdc *)0x4002C100U) /**< \brief (PDC_USART2) Base Address */\r
+#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */\r
+#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */\r
+#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM3SD8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3SD8C_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sam3sd8c.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM3SD8C */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH0_SIZE (0x40000u)\r
+#define IFLASH0_PAGE_SIZE (256u)\r
+#define IFLASH0_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH0_NB_OF_PAGES (1024u)\r
+#define IFLASH0_NB_OF_LOCK_BITS (16u)\r
+#define IFLASH1_SIZE (0x40000u)\r
+#define IFLASH1_PAGE_SIZE (256u)\r
+#define IFLASH1_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH1_NB_OF_PAGES (1024u)\r
+#define IFLASH1_NB_OF_LOCK_BITS (16u)\r
+#define IRAM_SIZE (0x10000u)\r
+#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)\r
+\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#if defined IFLASH0_SIZE\r
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */\r
+#endif\r
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM3SD8C */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (64000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */\r
+#define CHIP_FREQ_FWS_0 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (35000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM3SD8C_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief This file contains the default exception handlers.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * This file provides basic support for Cortex-M processor based \r
+ * microcontrollers.\r
+ *\r
+ * \note\r
+ * The exception handler has weak aliases.\r
+ * As they are weak aliases, any function with the same name will override\r
+ * this definition.\r
+ *\r
+ */\r
+\r
+\r
+#include "exceptions.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#ifdef __GNUC__\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void HardFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void ADC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void CRCCU_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DACC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void EFC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void HSMCI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOA_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOB_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PMC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PWM_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RSTC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RTC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RTT_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SMC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SPI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SSC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SUPC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC2_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC3_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC4_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC5_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TWI0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TWI1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UART0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UART1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void USART0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void USART1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UDP_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void WDT_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* __GNUC__ */\r
+\r
+#ifdef __ICCARM__\r
+/* Cortex-M3 core handlers */\r
+#pragma weak Reset_Handler=Dummy_Handler\r
+#pragma weak NMI_Handler=Dummy_Handler\r
+#pragma weak HardFault_Handler=Dummy_Handler\r
+#pragma weak MemManage_Handler=Dummy_Handler\r
+#pragma weak BusFault_Handler=Dummy_Handler\r
+#pragma weak UsageFault_Handler=Dummy_Handler\r
+#pragma weak SVC_Handler=Dummy_Handler\r
+#pragma weak DebugMon_Handler=Dummy_Handler\r
+#pragma weak PendSV_Handler=Dummy_Handler\r
+#pragma weak SysTick_Handler=Dummy_Handler\r
+\r
+/* Peripherals handlers */\r
+#pragma weak ACC_Handler=Dummy_Handler\r
+#pragma weak ADC_Handler=Dummy_Handler\r
+#pragma weak CRCCU_Handler=Dummy_Handler\r
+#pragma weak DACC_Handler=Dummy_Handler\r
+#pragma weak EFC_Handler=Dummy_Handler\r
+#pragma weak HSMCI_Handler=Dummy_Handler\r
+#pragma weak PIOA_Handler=Dummy_Handler\r
+#pragma weak PIOB_Handler=Dummy_Handler\r
+#pragma weak PIOC_Handler=Dummy_Handler\r
+#pragma weak PMC_Handler=Dummy_Handler\r
+#pragma weak PWM_Handler=Dummy_Handler\r
+#pragma weak RSTC_Handler=Dummy_Handler\r
+#pragma weak RTC_Handler=Dummy_Handler\r
+#pragma weak RTT_Handler=Dummy_Handler\r
+#pragma weak SMC_Handler=Dummy_Handler\r
+#pragma weak SPI_Handler=Dummy_Handler\r
+#pragma weak SSC_Handler=Dummy_Handler\r
+#pragma weak SUPC_Handler=Dummy_Handler\r
+#pragma weak TC0_Handler=Dummy_Handler\r
+#pragma weak TC1_Handler=Dummy_Handler\r
+#pragma weak TC2_Handler=Dummy_Handler\r
+#pragma weak TC3_Handler=Dummy_Handler\r
+#pragma weak TC4_Handler=Dummy_Handler\r
+#pragma weak TC5_Handler=Dummy_Handler\r
+#pragma weak TWI0_Handler=Dummy_Handler\r
+#pragma weak TWI1_Handler=Dummy_Handler\r
+#pragma weak UART0_Handler=Dummy_Handler\r
+#pragma weak UART1_Handler=Dummy_Handler\r
+#pragma weak USART0_Handler=Dummy_Handler\r
+#pragma weak USART1_Handler=Dummy_Handler\r
+#pragma weak UDP_Handler=Dummy_Handler\r
+#pragma weak WDT_Handler=Dummy_Handler\r
+#endif /* __ICCARM__ */\r
+\r
+/**\r
+ * \brief Default interrupt handler for unused IRQs.\r
+ */\r
+void Dummy_Handler(void)\r
+{\r
+ while (1) {\r
+ }\r
+}\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief This file contains the interface for default exception handlers.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef EXCEPTIONS_H_INCLUDED\r
+#define EXCEPTIONS_H_INCLUDED\r
+\r
+#include "sam3s8.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+/* Function prototype for exception table items (interrupt handler). */\r
+typedef void (*IntFunc) (void);\r
+\r
+/* Default empty handler */\r
+void Dummy_Handler(void);\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#endif /* EXCEPTIONS_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Startup file for SAM3SD8.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "exceptions.h"\r
+#include "sam3s8.h"\r
+#include "system_sam3sd8.h"\r
+\r
+/* Initialize segments */\r
+extern uint32_t _sfixed;\r
+extern uint32_t _efixed;\r
+extern uint32_t _etext;\r
+extern uint32_t _srelocate;\r
+extern uint32_t _erelocate;\r
+extern uint32_t _szero;\r
+extern uint32_t _ezero;\r
+extern uint32_t _sstack;\r
+extern uint32_t _estack;\r
+\r
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */\r
+int main(void);\r
+/** \endcond */\r
+\r
+void __libc_init_array(void);\r
+\r
+/* Exception Table */\r
+__attribute__ ((section(".vectors")))\r
+IntFunc exception_table[] = {\r
+\r
+ /* Configure Initial Stack Pointer, using linker-generated symbols */\r
+ (IntFunc) (&_estack),\r
+ Reset_Handler,\r
+\r
+ NMI_Handler,\r
+ HardFault_Handler,\r
+ MemManage_Handler,\r
+ BusFault_Handler,\r
+ UsageFault_Handler,\r
+ 0, 0, 0, 0, /* Reserved */\r
+ SVC_Handler,\r
+ DebugMon_Handler,\r
+ 0, /* Reserved */\r
+ PendSV_Handler,\r
+ SysTick_Handler,\r
+\r
+ /* Configurable interrupts */\r
+ SUPC_Handler, /* 0 Supply Controller */\r
+ RSTC_Handler, /* 1 Reset Controller */\r
+ RTC_Handler, /* 2 Real Time Clock */\r
+ RTT_Handler, /* 3 Real Time Timer */\r
+ WDT_Handler, /* 4 Watchdog Timer */\r
+ PMC_Handler, /* 5 PMC */\r
+ EFC_Handler, /* 6 EFC */\r
+ Dummy_Handler, /* 7 Reserved */\r
+ UART0_Handler, /* 8 UART0 */\r
+ UART1_Handler, /* 9 UART1 */\r
+ SMC_Handler, /* 10 SMC */\r
+ PIOA_Handler, /* 11 Parallel IO Controller A */\r
+ PIOB_Handler, /* 12 Parallel IO Controller B */\r
+ PIOC_Handler, /* 13 Parallel IO Controller C */\r
+ USART0_Handler, /* 14 USART 0 */\r
+ USART1_Handler, /* 15 USART 1 */\r
+ Dummy_Handler, /* 16 Reserved */\r
+ Dummy_Handler, /* 17 Reserved */\r
+ HSMCI_Handler, /* 18 HSMCI */\r
+ TWI0_Handler, /* 19 TWI 0 */\r
+ TWI1_Handler, /* 20 TWI 1 */\r
+ SPI_Handler, /* 21 SPI */\r
+ SSC_Handler, /* 22 SSC */\r
+ TC0_Handler, /* 23 Timer Counter 0 */\r
+ TC1_Handler, /* 24 Timer Counter 1 */\r
+ TC2_Handler, /* 25 Timer Counter 2 */\r
+ TC3_Handler, /* 26 Timer Counter 3 */\r
+ TC4_Handler, /* 27 Timer Counter 4 */\r
+ TC5_Handler, /* 28 Timer Counter 5 */\r
+ ADC_Handler, /* 29 ADC controller */\r
+ DACC_Handler, /* 30 DACC controller */\r
+ PWM_Handler, /* 31 PWM */\r
+ CRCCU_Handler, /* 32 CRC Calculation Unit */\r
+ ACC_Handler, /* 33 Analog Comparator */\r
+ UDP_Handler, /* 34 USB Device Port */\r
+ Dummy_Handler /* 35 not used */\r
+};\r
+\r
+/* TEMPORARY PATCH FOR SCB */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+/**\r
+ * \brief This is the code that gets called on processor reset.\r
+ * To initialize the device, and call the main() routine.\r
+ */\r
+void Reset_Handler(void)\r
+{\r
+ uint32_t *pSrc, *pDest;\r
+\r
+ /* Initialize the relocate segment */\r
+ pSrc = &_etext;\r
+ pDest = &_srelocate;\r
+\r
+ if (pSrc != pDest) {\r
+ for (; pDest < &_erelocate;) {\r
+ *pDest++ = *pSrc++;\r
+ }\r
+ }\r
+\r
+ /* Clear the zero segment */\r
+ for (pDest = &_szero; pDest < &_ezero;) {\r
+ *pDest++ = 0;\r
+ }\r
+\r
+ /* Set the vector table base address */\r
+ pSrc = (uint32_t *) & _sfixed;\r
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);\r
+\r
+ if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {\r
+ SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;\r
+ }\r
+\r
+ /* Initialize the C library */\r
+ __libc_init_array();\r
+\r
+ /* Branch to main function */\r
+ main();\r
+\r
+ /* Infinite loop */\r
+ while (1);\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Provides the low-level initialization functions that called \r
+ * on chip startup.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "system_sam3sd8.h"\r
+#include "sam3s8.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+/* Clock settings (64MHz) */\r
+#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8UL))\r
+#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \\r
+ | CKGR_PLLAR_MULA(0x1fUL) \\r
+ | CKGR_PLLAR_PLLACOUNT(0x3fUL) \\r
+ | CKGR_PLLAR_DIVA(0x3UL))\r
+#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)\r
+\r
+#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37UL) /* Key to unlock MOR register */\r
+\r
+/* FIXME: should be generated by sock */\r
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+/**\r
+ * \brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemFrequency variable.\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* Set FWS according to SYS_BOARD_MCKR configuration */\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(3);\r
+\r
+ /* Initialize main oscillator */\r
+ if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |\r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {\r
+ }\r
+ }\r
+\r
+ /* Switch to 3-20MHz Xtal oscillator */\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | \r
+ CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;\r
+\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {\r
+ }\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ /* Initialize PLLA */\r
+ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {\r
+ }\r
+\r
+ /* Switch to main clock */\r
+ PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ /* Switch to PLLA */\r
+ PMC->PMC_MCKR = SYS_BOARD_MCKR;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ SystemCoreClock = CHIP_FREQ_CPU_MAX;\r
+}\r
+\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ /* Determine clock frequency according to clock register values */\r
+ switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {\r
+ case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */\r
+ if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_32K;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_SLCK_RC;\r
+ }\r
+ break;\r
+ case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */\r
+ case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {\r
+ SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> \r
+ CKGR_PLLAR_MULA_Pos) + 1U);\r
+ SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> \r
+ CKGR_PLLAR_DIVA_Pos));\r
+ } else {\r
+ SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >>\r
+ CKGR_PLLBR_MULB_Pos) + 1U);\r
+ SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >> \r
+ CKGR_PLLBR_DIVB_Pos));\r
+ }\r
+ break;\r
+ }\r
+\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {\r
+ SystemCoreClock /= 3U;\r
+ } else {\r
+ SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> \r
+ PMC_MCKR_PRES_Pos);\r
+ }\r
+}\r
+\r
+/** \r
+ * Initialize flash.\r
+ */\r
+void system_init_flash(uint32_t ul_clk)\r
+{\r
+ /* Set FWS for embedded Flash access according to operating frequency */\r
+ if (ul_clk < CHIP_FREQ_FWS_0) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(0);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_1) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(1);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_2) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(2);\r
+ } else {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(3);\r
+ }\r
+}\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Provides the low-level initialization functions that called \r
+ * on chip startup.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SYSTEM_SAM3SD8_H_INCLUDED\r
+#define SYSTEM_SAM3SD8_H_INCLUDED\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemCoreClock variable.\r
+ */\r
+void SystemInit(void);\r
+\r
+/**\r
+ * @brief Updates the SystemCoreClock with current core Clock \r
+ * retrieved from cpu registers.\r
+ */\r
+void SystemCoreClockUpdate(void);\r
+\r
+/** \r
+ * Initialize flash.\r
+ */\r
+void system_init_flash(uint32_t ul_clk);\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#endif /* SYSTEM_SAM3SD8_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Commonly used includes, types and macros.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef UTILS_COMPILER_H\r
+#define UTILS_COMPILER_H\r
+\r
+/**\r
+ * \defgroup group_sam_utils Compiler abstraction layer and code utilities\r
+ *\r
+ * Compiler abstraction layer and code utilities for AT91SAM.\r
+ * This module provides various abstraction layers and utilities to make code compatible between different compilers.\r
+ *\r
+ * \{\r
+ */\r
+#include <stddef.h>\r
+\r
+#if (defined __ICCARM__)\r
+# include <intrinsics.h>\r
+#endif\r
+\r
+#include <parts.h>\r
+#include "preprocessor.h"\r
+\r
+#include <io.h>\r
+\r
+//_____ D E C L A R A T I O N S ____________________________________________\r
+\r
+#ifndef __ASSEMBLY__ // Not defined for assembling.\r
+\r
+#include <stdio.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <stdlib.h>\r
+\r
+#ifdef __ICCARM__\r
+/*! \name Compiler Keywords\r
+ *\r
+ * Port of some keywords from GCC to IAR Embedded Workbench.\r
+ */\r
+//! @{\r
+#define __asm__ asm\r
+#define __inline__ inline\r
+#define __volatile__\r
+//! @}\r
+\r
+#endif\r
+\r
+/**\r
+ * \def UNUSED\r
+ * \brief Marking \a v as a unused parameter or value.\r
+ */\r
+#define UNUSED(v) (void)(v)\r
+\r
+/**\r
+ * \def unused\r
+ * \brief Marking \a v as a unused parameter or value.\r
+ */\r
+#define unused(v) do { (void)(v); } while(0)\r
+\r
+/**\r
+ * \def barrier\r
+ * \brief Memory barrier\r
+ */\r
+#define barrier() __DMB()\r
+\r
+/**\r
+ * \brief Emit the compiler pragma \a arg.\r
+ *\r
+ * \param arg The pragma directive as it would appear after \e \#pragma\r
+ * (i.e. not stringified).\r
+ */\r
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)\r
+\r
+/**\r
+ * \def COMPILER_PACK_SET(alignment)\r
+ * \brief Set maximum alignment for subsequent struct and union\r
+ * definitions to \a alignment.\r
+ */\r
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))\r
+\r
+/**\r
+ * \def COMPILER_PACK_RESET()\r
+ * \brief Set default alignment for subsequent struct and union\r
+ * definitions.\r
+ */\r
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())\r
+\r
+\r
+/**\r
+ * \brief Set aligned boundary.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))\r
+#elif (defined __ICCARM__)\r
+# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)\r
+#endif\r
+\r
+/**\r
+ * \brief Set word-aligned boundary.\r
+ */\r
+#if (defined __GNUC__) || defined(__CC_ARM)\r
+#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))\r
+#elif (defined __ICCARM__)\r
+#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)\r
+#endif\r
+\r
+/**\r
+ * \def __always_inline\r
+ * \brief The function should always be inlined.\r
+ *\r
+ * This annotation instructs the compiler to ignore its inlining\r
+ * heuristics and inline the function no matter how big it thinks it\r
+ * becomes.\r
+ */\r
+#if defined(__CC_ARM)\r
+# define __always_inline __forceinline\r
+#elif (defined __GNUC__)\r
+# define __always_inline __attribute__((__always_inline__)) inline\r
+#elif (defined __ICCARM__)\r
+# define __always_inline _Pragma("inline=forced")\r
+#endif\r
+\r
+/*! \brief This macro is used to test fatal errors.\r
+ *\r
+ * The macro tests if the expression is false. If it is, a fatal error is\r
+ * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO\r
+ * is defined, a unit test version of the macro is used, to allow execution\r
+ * of further tests after a false expression.\r
+ *\r
+ * \param expr Expression to evaluate and supposed to be nonzero.\r
+ */\r
+#if defined(_ASSERT_ENABLE_)\r
+# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)\r
+ // Assert() is defined in unit_test/suite.h\r
+# include "unit_test/suite.h"\r
+# else\r
+#undef TEST_SUITE_DEFINE_ASSERT_MACRO\r
+# define Assert(expr) \\r
+ {\\r
+ if (!(expr)) while (true);\\r
+ }\r
+# endif\r
+#else\r
+# define Assert(expr) ((void) 0)\r
+#endif\r
+\r
+/* Define attribute */\r
+#if defined ( __CC_ARM ) /* Keil µVision 4 */\r
+# define WEAK __attribute__ ((weak))\r
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */\r
+# define WEAK __weak\r
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */\r
+# define WEAK __attribute__ ((weak))\r
+#endif\r
+\r
+/* Define NO_INIT attribute */\r
+#if defined ( __CC_ARM )\r
+# define NO_INIT __attribute__((zero_init))\r
+#elif defined ( __ICCARM__ )\r
+# define NO_INIT __no_init\r
+#elif defined ( __GNUC__ )\r
+# define NO_INIT __attribute__((section(".no_init")))\r
+#endif\r
+\r
+#include "interrupt.h"\r
+\r
+/*! \name Usual Types\r
+ */\r
+//! @{\r
+typedef unsigned char Bool; //!< Boolean.\r
+#ifndef __cplusplus\r
+#if !defined(__bool_true_false_are_defined)\r
+typedef unsigned char bool; //!< Boolean.\r
+#endif\r
+#endif\r
+typedef int8_t S8 ; //!< 8-bit signed integer.\r
+typedef uint8_t U8 ; //!< 8-bit unsigned integer.\r
+typedef int16_t S16; //!< 16-bit signed integer.\r
+typedef uint16_t U16; //!< 16-bit unsigned integer.\r
+typedef uint16_t le16_t;\r
+typedef uint16_t be16_t;\r
+typedef int32_t S32; //!< 32-bit signed integer.\r
+typedef uint32_t U32; //!< 32-bit unsigned integer.\r
+typedef uint32_t le32_t;\r
+typedef uint32_t be32_t;\r
+typedef int64_t S64; //!< 64-bit signed integer.\r
+typedef uint64_t U64; //!< 64-bit unsigned integer.\r
+typedef float F32; //!< 32-bit floating-point number.\r
+typedef double F64; //!< 64-bit floating-point number.\r
+typedef uint32_t iram_size_t;\r
+//! @}\r
+\r
+\r
+/*! \name Status Types\r
+ */\r
+//! @{\r
+typedef bool Status_bool_t; //!< Boolean status.\r
+typedef U8 Status_t; //!< 8-bit-coded status.\r
+//! @}\r
+\r
+\r
+/*! \name Aliasing Aggregate Types\r
+ */\r
+//! @{\r
+\r
+//! 16-bit union.\r
+typedef union\r
+{\r
+ S16 s16 ;\r
+ U16 u16 ;\r
+ S8 s8 [2];\r
+ U8 u8 [2];\r
+} Union16;\r
+\r
+//! 32-bit union.\r
+typedef union\r
+{\r
+ S32 s32 ;\r
+ U32 u32 ;\r
+ S16 s16[2];\r
+ U16 u16[2];\r
+ S8 s8 [4];\r
+ U8 u8 [4];\r
+} Union32;\r
+\r
+//! 64-bit union.\r
+typedef union\r
+{\r
+ S64 s64 ;\r
+ U64 u64 ;\r
+ S32 s32[2];\r
+ U32 u32[2];\r
+ S16 s16[4];\r
+ U16 u16[4];\r
+ S8 s8 [8];\r
+ U8 u8 [8];\r
+} Union64;\r
+\r
+//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ S64 *s64ptr;\r
+ U64 *u64ptr;\r
+ S32 *s32ptr;\r
+ U32 *u32ptr;\r
+ S16 *s16ptr;\r
+ U16 *u16ptr;\r
+ S8 *s8ptr ;\r
+ U8 *u8ptr ;\r
+} UnionPtr;\r
+\r
+//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ volatile S64 *s64ptr;\r
+ volatile U64 *u64ptr;\r
+ volatile S32 *s32ptr;\r
+ volatile U32 *u32ptr;\r
+ volatile S16 *s16ptr;\r
+ volatile U16 *u16ptr;\r
+ volatile S8 *s8ptr ;\r
+ volatile U8 *u8ptr ;\r
+} UnionVPtr;\r
+\r
+//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ const S64 *s64ptr;\r
+ const U64 *u64ptr;\r
+ const S32 *s32ptr;\r
+ const U32 *u32ptr;\r
+ const S16 *s16ptr;\r
+ const U16 *u16ptr;\r
+ const S8 *s8ptr ;\r
+ const U8 *u8ptr ;\r
+} UnionCPtr;\r
+\r
+//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ const volatile S64 *s64ptr;\r
+ const volatile U64 *u64ptr;\r
+ const volatile S32 *s32ptr;\r
+ const volatile U32 *u32ptr;\r
+ const volatile S16 *s16ptr;\r
+ const volatile U16 *u16ptr;\r
+ const volatile S8 *s8ptr ;\r
+ const volatile U8 *u8ptr ;\r
+} UnionCVPtr;\r
+\r
+//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ S64 *s64ptr;\r
+ U64 *u64ptr;\r
+ S32 *s32ptr;\r
+ U32 *u32ptr;\r
+ S16 *s16ptr;\r
+ U16 *u16ptr;\r
+ S8 *s8ptr ;\r
+ U8 *u8ptr ;\r
+} StructPtr;\r
+\r
+//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ volatile S64 *s64ptr;\r
+ volatile U64 *u64ptr;\r
+ volatile S32 *s32ptr;\r
+ volatile U32 *u32ptr;\r
+ volatile S16 *s16ptr;\r
+ volatile U16 *u16ptr;\r
+ volatile S8 *s8ptr ;\r
+ volatile U8 *u8ptr ;\r
+} StructVPtr;\r
+\r
+//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ const S64 *s64ptr;\r
+ const U64 *u64ptr;\r
+ const S32 *s32ptr;\r
+ const U32 *u32ptr;\r
+ const S16 *s16ptr;\r
+ const U16 *u16ptr;\r
+ const S8 *s8ptr ;\r
+ const U8 *u8ptr ;\r
+} StructCPtr;\r
+\r
+//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ const volatile S64 *s64ptr;\r
+ const volatile U64 *u64ptr;\r
+ const volatile S32 *s32ptr;\r
+ const volatile U32 *u32ptr;\r
+ const volatile S16 *s16ptr;\r
+ const volatile U16 *u16ptr;\r
+ const volatile S8 *s8ptr ;\r
+ const volatile U8 *u8ptr ;\r
+} StructCVPtr;\r
+\r
+//! @}\r
+\r
+#endif // #ifndef __ASSEMBLY__\r
+\r
+/*! \name Usual Constants\r
+ */\r
+//! @{\r
+#define DISABLE 0\r
+#define ENABLE 1\r
+#ifndef __cplusplus\r
+#if !defined(__bool_true_false_are_defined)\r
+#define false 0\r
+#define true 1\r
+#endif\r
+#endif\r
+#define PASS 0\r
+#define FAIL 1\r
+#define LOW 0\r
+#define HIGH 1\r
+//! @}\r
+\r
+\r
+#ifndef __ASSEMBLY__ // not for assembling.\r
+\r
+//! \name Optimization Control\r
+//@{\r
+\r
+/**\r
+ * \def likely(exp)\r
+ * \brief The expression \a exp is likely to be true\r
+ */\r
+#ifndef likely\r
+# define likely(exp) (exp)\r
+#endif\r
+\r
+/**\r
+ * \def unlikely(exp)\r
+ * \brief The expression \a exp is unlikely to be true\r
+ */\r
+#ifndef unlikely\r
+# define unlikely(exp) (exp)\r
+#endif\r
+\r
+/**\r
+ * \def is_constant(exp)\r
+ * \brief Determine if an expression evaluates to a constant value.\r
+ *\r
+ * \param exp Any expression\r
+ *\r
+ * \return true if \a exp is constant, false otherwise.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define is_constant(exp) __builtin_constant_p(exp)\r
+#else\r
+# define is_constant(exp) (0)\r
+#endif\r
+\r
+//! @}\r
+\r
+/*! \name Bit-Field Handling\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reads the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read bits from.\r
+ * \param mask Bit-mask indicating bits to read.\r
+ *\r
+ * \return Read bits.\r
+ */\r
+#define Rd_bits( value, mask) ((value) & (mask))\r
+\r
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue to write bits to.\r
+ * \param mask Bit-mask indicating bits to write.\r
+ * \param bits Bits to write.\r
+ *\r
+ * \return Resulting value with written bits.\r
+ */\r
+#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\\r
+ ((bits ) & (mask)))\r
+\r
+/*! \brief Tests the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value of which to test bits.\r
+ * \param mask Bit-mask indicating bits to test.\r
+ *\r
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.\r
+ */\r
+#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)\r
+\r
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to clear bits.\r
+ * \param mask Bit-mask indicating bits to clear.\r
+ *\r
+ * \return Resulting value with cleared bits.\r
+ */\r
+#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))\r
+\r
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to set bits.\r
+ * \param mask Bit-mask indicating bits to set.\r
+ *\r
+ * \return Resulting value with set bits.\r
+ */\r
+#define Set_bits(lvalue, mask) ((lvalue) |= (mask))\r
+\r
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to toggle bits.\r
+ * \param mask Bit-mask indicating bits to toggle.\r
+ *\r
+ * \return Resulting value with toggled bits.\r
+ */\r
+#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))\r
+\r
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read a bit-field from.\r
+ * \param mask Bit-mask indicating the bit-field to read.\r
+ *\r
+ * \return Read bit-field.\r
+ */\r
+#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))\r
+\r
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue to write a bit-field to.\r
+ * \param mask Bit-mask indicating the bit-field to write.\r
+ * \param bitfield Bit-field to write.\r
+ *\r
+ * \return Resulting value with written bit-field.\r
+ */\r
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Zero-Bit Counting\r
+ *\r
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when\r
+ * applied to constant expressions (values known at compile time), so they are\r
+ * more optimized than the use of the corresponding assembly instructions and\r
+ * they can be used as constant expressions e.g. to initialize objects having\r
+ * static storage duration, and like the corresponding assembly instructions\r
+ * when applied to non-constant expressions (values unknown at compile time), so\r
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz\r
+ * ensure a possible and optimized behavior for both constant and non-constant\r
+ * expressions.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the leading zero bits.\r
+ *\r
+ * \return The count of leading zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define clz(u) __builtin_clz(u)\r
+#elif (defined __ICCARM__)\r
+# define clz(u) __CLZ(u)\r
+#else\r
+# define clz(u) (((u) == 0) ? 32 : \\r
+ ((u) & (1ul << 31)) ? 0 : \\r
+ ((u) & (1ul << 30)) ? 1 : \\r
+ ((u) & (1ul << 29)) ? 2 : \\r
+ ((u) & (1ul << 28)) ? 3 : \\r
+ ((u) & (1ul << 27)) ? 4 : \\r
+ ((u) & (1ul << 26)) ? 5 : \\r
+ ((u) & (1ul << 25)) ? 6 : \\r
+ ((u) & (1ul << 24)) ? 7 : \\r
+ ((u) & (1ul << 23)) ? 8 : \\r
+ ((u) & (1ul << 22)) ? 9 : \\r
+ ((u) & (1ul << 21)) ? 10 : \\r
+ ((u) & (1ul << 20)) ? 11 : \\r
+ ((u) & (1ul << 19)) ? 12 : \\r
+ ((u) & (1ul << 18)) ? 13 : \\r
+ ((u) & (1ul << 17)) ? 14 : \\r
+ ((u) & (1ul << 16)) ? 15 : \\r
+ ((u) & (1ul << 15)) ? 16 : \\r
+ ((u) & (1ul << 14)) ? 17 : \\r
+ ((u) & (1ul << 13)) ? 18 : \\r
+ ((u) & (1ul << 12)) ? 19 : \\r
+ ((u) & (1ul << 11)) ? 20 : \\r
+ ((u) & (1ul << 10)) ? 21 : \\r
+ ((u) & (1ul << 9)) ? 22 : \\r
+ ((u) & (1ul << 8)) ? 23 : \\r
+ ((u) & (1ul << 7)) ? 24 : \\r
+ ((u) & (1ul << 6)) ? 25 : \\r
+ ((u) & (1ul << 5)) ? 26 : \\r
+ ((u) & (1ul << 4)) ? 27 : \\r
+ ((u) & (1ul << 3)) ? 28 : \\r
+ ((u) & (1ul << 2)) ? 29 : \\r
+ ((u) & (1ul << 1)) ? 30 : \\r
+ 31)\r
+#endif\r
+\r
+/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the trailing zero bits.\r
+ *\r
+ * \return The count of trailing zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define ctz(u) __builtin_ctz(u)\r
+#else\r
+# define ctz(u) ((u) & (1ul << 0) ? 0 : \\r
+ (u) & (1ul << 1) ? 1 : \\r
+ (u) & (1ul << 2) ? 2 : \\r
+ (u) & (1ul << 3) ? 3 : \\r
+ (u) & (1ul << 4) ? 4 : \\r
+ (u) & (1ul << 5) ? 5 : \\r
+ (u) & (1ul << 6) ? 6 : \\r
+ (u) & (1ul << 7) ? 7 : \\r
+ (u) & (1ul << 8) ? 8 : \\r
+ (u) & (1ul << 9) ? 9 : \\r
+ (u) & (1ul << 10) ? 10 : \\r
+ (u) & (1ul << 11) ? 11 : \\r
+ (u) & (1ul << 12) ? 12 : \\r
+ (u) & (1ul << 13) ? 13 : \\r
+ (u) & (1ul << 14) ? 14 : \\r
+ (u) & (1ul << 15) ? 15 : \\r
+ (u) & (1ul << 16) ? 16 : \\r
+ (u) & (1ul << 17) ? 17 : \\r
+ (u) & (1ul << 18) ? 18 : \\r
+ (u) & (1ul << 19) ? 19 : \\r
+ (u) & (1ul << 20) ? 20 : \\r
+ (u) & (1ul << 21) ? 21 : \\r
+ (u) & (1ul << 22) ? 22 : \\r
+ (u) & (1ul << 23) ? 23 : \\r
+ (u) & (1ul << 24) ? 24 : \\r
+ (u) & (1ul << 25) ? 25 : \\r
+ (u) & (1ul << 26) ? 26 : \\r
+ (u) & (1ul << 27) ? 27 : \\r
+ (u) & (1ul << 28) ? 28 : \\r
+ (u) & (1ul << 29) ? 29 : \\r
+ (u) & (1ul << 30) ? 30 : \\r
+ (u) & (1ul << 31) ? 31 : \\r
+ 32)\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Bit Reversing\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reverses the bits of \a u8.\r
+ *\r
+ * \param u8 U8 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u8 with reversed bits.\r
+ */\r
+#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))\r
+\r
+/*! \brief Reverses the bits of \a u16.\r
+ *\r
+ * \param u16 U16 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u16 with reversed bits.\r
+ */\r
+#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16))\r
+\r
+/*! \brief Reverses the bits of \a u32.\r
+ *\r
+ * \param u32 U32 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u32 with reversed bits.\r
+ */\r
+#define bit_reverse32(u32) __RBIT(u32)\r
+\r
+/*! \brief Reverses the bits of \a u64.\r
+ *\r
+ * \param u64 U64 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u64 with reversed bits.\r
+ */\r
+#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\\r
+ ((U64)bit_reverse32((U64)(u64)) << 32)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Alignment\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tests alignment of the number \a val with the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.\r
+ */\r
+#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) )\r
+\r
+/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Alignment of the number \a val with respect to the \a n boundary.\r
+ */\r
+#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) )\r
+\r
+/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.\r
+ *\r
+ * \param lval Input/output lvalue.\r
+ * \param n Boundary.\r
+ * \param alg Alignment.\r
+ *\r
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.\r
+ */\r
+#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )\r
+\r
+/*! \brief Aligns the number \a val with the upper \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.\r
+ */\r
+#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1))\r
+\r
+/*! \brief Aligns the number \a val with the lower \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.\r
+ */\r
+#define Align_down(val, n ) ( (val) & ~((n) - 1))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Mathematics\r
+ *\r
+ * The same considerations as for clz and ctz apply here but GCC does not\r
+ * provide built-in functions to access the assembly instructions abs, min and\r
+ * max and it does not produce them by itself in most cases, so two sets of\r
+ * macros are defined here:\r
+ * - Abs, Min and Max to apply to constant expressions (values known at\r
+ * compile time);\r
+ * - abs, min and max to apply to non-constant expressions (values unknown at\r
+ * compile time), abs is found in stdlib.h.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Takes the absolute value of \a a.\r
+ *\r
+ * \param a Input value.\r
+ *\r
+ * \return Absolute value of \a a.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Abs(a) (((a) < 0 ) ? -(a) : (a))\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Min(a, b) (((a) < (b)) ? (a) : (b))\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Max(a, b) (((a) > (b)) ? (a) : (b))\r
+\r
+// abs() is already defined by stdlib.h\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define min(a, b) Min(a, b)\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define max(a, b) Max(a, b)\r
+\r
+//! @}\r
+\r
+\r
+/*! \brief Calls the routine at address \a addr.\r
+ *\r
+ * It generates a long call opcode.\r
+ *\r
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if\r
+ * it is invoked from the CPU supervisor mode.\r
+ *\r
+ * \param addr Address of the routine to call.\r
+ *\r
+ * \note It may be used as a long jump opcode in some special cases.\r
+ */\r
+#define Long_call(addr) ((*(void (*)(void))(addr))())\r
+\r
+\r
+/*! \name MCU Endianism Handling\r
+ * ARM is MCU little endianism.\r
+ */\r
+//! @{\r
+#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.\r
+#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.\r
+\r
+#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.\r
+#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.\r
+#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.\r
+#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.\r
+#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+ \r
+#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.\r
+#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.\r
+#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.\r
+#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.\r
+#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.\r
+#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.\r
+#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.\r
+#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.\r
+#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.\r
+#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.\r
+#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.\r
+#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.\r
+#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.\r
+#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.\r
+#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.\r
+#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.\r
+#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.\r
+#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.\r
+#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.\r
+#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.\r
+#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.\r
+#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.\r
+#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.\r
+#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.\r
+#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.\r
+#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.\r
+\r
+#define BE16(x) Swap16(x)\r
+#define LE16(x) (x)\r
+\r
+#define le16_to_cpu(x) (x)\r
+#define cpu_to_le16(x) (x)\r
+#define LE16_TO_CPU(x) (x)\r
+#define CPU_TO_LE16(x) (x)\r
+\r
+#define be16_to_cpu(x) Swap16(x)\r
+#define cpu_to_be16(x) Swap16(x)\r
+#define BE16_TO_CPU(x) Swap16(x)\r
+#define CPU_TO_BE16(x) Swap16(x)\r
+\r
+#define le32_to_cpu(x) (x)\r
+#define cpu_to_le32(x) (x)\r
+#define LE32_TO_CPU(x) (x)\r
+#define CPU_TO_LE32(x) (x)\r
+\r
+#define be32_to_cpu(x) swap32(x)\r
+#define cpu_to_be32(x) swap32(x)\r
+#define BE32_TO_CPU(x) swap32(x)\r
+#define CPU_TO_BE32(x) swap32(x)\r
+//! @}\r
+\r
+\r
+/*! \name Endianism Conversion\r
+ *\r
+ * The same considerations as for clz and ctz apply here but GCC's\r
+ * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when\r
+ * applied to constant expressions, so two sets of macros are defined here:\r
+ * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known\r
+ * at compile time);\r
+ * - swap16, swap32 and swap64 to apply to non-constant expressions (values\r
+ * unknown at compile time).\r
+ */\r
+//! @{\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\\r
+ ((U16)(u16) << 8)))\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\\r
+ ((U32)Swap16((U32)(u32)) << 16)))\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\\r
+ ((U64)Swap32((U64)(u64)) << 32)))\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define swap16(u16) Swap16(u16)\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32)))\r
+#else\r
+# define swap32(u32) Swap32(u32)\r
+#endif\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64)))\r
+#else\r
+# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\\r
+ ((U64)swap32((U64)(u64)) << 32)))\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Target Abstraction\r
+ */\r
+//! @{\r
+\r
+#define _GLOBEXT_ extern //!< extern storage-class specifier.\r
+#define _CONST_TYPE_ const //!< const type qualifier.\r
+#define _MEM_TYPE_SLOW_ //!< Slow memory type.\r
+#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.\r
+#define _MEM_TYPE_FAST_ //!< Fast memory type.\r
+\r
+typedef U8 Byte; //!< 8-bit unsigned integer.\r
+\r
+#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.\r
+#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.\r
+#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.\r
+#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.\r
+\r
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.\r
+\r
+//! @}\r
+\r
+/**\r
+ * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using\r
+ * integer arithmetic.\r
+ *\r
+ * \param a An integer\r
+ * \param b Another integer\r
+ *\r
+ * \return (\a a / \a b) rounded up to the nearest integer.\r
+ */\r
+#define div_ceil(a, b) (((a) + (b) - 1) / (b))\r
+\r
+#endif // #ifndef __ASSEMBLY__\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif /* UTILS_COMPILER_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Arch file for SAM.\r
+ *\r
+ * This file defines common SAM series.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM_IO_\r
+#define _SAM_IO_\r
+\r
+/* SAM3 family */\r
+\r
+/* SAM3S series */\r
+#if (SAM3S)\r
+# if (SAM3S8 || SAM3SD8)\r
+# include "sam3s8.h"\r
+# else\r
+# include "sam3s.h"\r
+# endif\r
+#endif\r
+\r
+/* SAM3U series */\r
+#if (SAM3U)\r
+# include "sam3u.h"\r
+#endif\r
+\r
+/* SAM3N series */\r
+#if (SAM3N)\r
+# include "sam3n.h"\r
+#endif\r
+\r
+/* SAM3XA series */\r
+#if (SAM3XA)\r
+# include "sam3xa.h"\r
+#endif\r
+\r
+/* SAM4S series */\r
+#if (SAM4S)\r
+# include "sam4s.h"\r
+#endif\r
+\r
+#endif /* _SAM_IO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Flash Linker script for SAM.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ * \r
+ * 1. Redistributions of source code must retain the above copyright notice, \r
+ * this list of conditions and the following disclaimer.\r
+ * \r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * \r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ * \r
+ * 4. This software may only be redistributed and used in connection with an \r
+ * Atmel microcontroller product.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+SEARCH_DIR(.)\r
+\r
+/* Memory Spaces Definitions */\r
+MEMORY\r
+{\r
+ rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash has two banks, one bank = 256K */\r
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */\r
+}\r
+\r
+/* The stack size used by the application. NOTE: you need to adjust */\r
+STACK_SIZE = 0x2000;\r
+\r
+/* Section Definitions */ \r
+SECTIONS \r
+{ \r
+ .text : \r
+ { \r
+ . = ALIGN(4);\r
+ _sfixed = .;\r
+ KEEP(*(.vectors .vectors.*))\r
+ *(.text .text.* .gnu.linkonce.t.*) \r
+ *(.glue_7t) *(.glue_7) \r
+ *(.rodata .rodata* .gnu.linkonce.r.*) \r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+\r
+ /* Support C constructors, and C destructors in both user code\r
+ and the C library. This also provides support for C++ code. */\r
+ . = ALIGN(4);\r
+ KEEP(*(.init))\r
+ . = ALIGN(4);\r
+ __preinit_array_start = .;\r
+ KEEP (*(.preinit_array))\r
+ __preinit_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ __init_array_start = .;\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array))\r
+ __init_array_end = .;\r
+\r
+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+ __fini_array_start = .;\r
+ KEEP (*(.fini_array))\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ __fini_array_end = .;\r
+\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
+\r
+ . = ALIGN(4);\r
+ _efixed = .; /* End of text section */\r
+ } > rom\r
+\r
+ /* .ARM.exidx is sorted, so has to go in its own output section. */\r
+ PROVIDE_HIDDEN (__exidx_start = .);\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > rom\r
+ PROVIDE_HIDDEN (__exidx_end = .);\r
+\r
+ . = ALIGN(4); \r
+ _etext = .;\r
+\r
+ .relocate : AT (_etext)\r
+ {\r
+ . = ALIGN(4);\r
+ _srelocate = .;\r
+ *(.ramfunc .ramfunc.*);\r
+ *(.data .data.*);\r
+ . = ALIGN(4);\r
+ _erelocate = .;\r
+ } > ram\r
+\r
+ /* .bss section which is used for uninitialized data */ \r
+ .bss (NOLOAD) :\r
+ { \r
+ . = ALIGN(4);\r
+ _sbss = . ;\r
+ _szero = .;\r
+ *(.bss .bss.*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ _ebss = . ;\r
+ _ezero = .;\r
+ } > ram\r
+\r
+ /* stack section */\r
+ .stack (NOLOAD):\r
+ {\r
+ . = ALIGN(8);\r
+ _sstack = .;\r
+ . = . + STACK_SIZE;\r
+ . = ALIGN(8);\r
+ _estack = .;\r
+ } > ram\r
+\r
+ . = ALIGN(4); \r
+ _end = . ; \r
+}\r
--- /dev/null
+# List of available make goals:\r
+#\r
+# all Default target, builds the project\r
+# clean Clean up the project\r
+# rebuild Rebuild the project\r
+# debug_flash Builds the project and debug in flash\r
+# debug_sram Builds the project and debug in sram\r
+#\r
+# doc Build the documentation\r
+# cleandoc Clean up the documentation\r
+# rebuilddoc Rebuild the documentation\r
+#\r
+# \file\r
+#\r
+# Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+#\r
+# \asf_license_start\r
+#\r
+# \page License\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# 1. Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the following disclaimer.\r
+#\r
+# 2. Redistributions in binary form must reproduce the above copyright notice,\r
+# this list of conditions and the following disclaimer in the documentation\r
+# and/or other materials provided with the distribution.\r
+#\r
+# 3. The name of Atmel may not be used to endorse or promote products derived\r
+# from this software without specific prior written permission.\r
+#\r
+# 4. This software may only be redistributed and used in connection with an\r
+# Atmel microcontroller product.\r
+#\r
+# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+# POSSIBILITY OF SUCH DAMAGE.\r
+#\r
+# \asf_license_stop\r
+#\r
+\r
+# Include the config.mk file from the current working path, e.g., where the\r
+# user called make.\r
+include config.mk\r
+\r
+# Tool to use to generate documentation from the source code\r
+DOCGEN ?= doxygen\r
+\r
+# Look for source files relative to the top-level source directory\r
+VPATH := $(PRJ_PATH)\r
+\r
+# Output target file\r
+project_type := $(PROJECT_TYPE)\r
+\r
+# Output target file\r
+ifeq ($(project_type),flash)\r
+target := $(TARGET_FLASH)\r
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)\r
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)\r
+else\r
+target := $(TARGET_SRAM)\r
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)\r
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)\r
+endif\r
+\r
+# Output project name (target name minus suffix)\r
+project := $(basename $(target))\r
+\r
+# Output target file (typically ELF or static library)\r
+ifeq ($(suffix $(target)),.a)\r
+target_type := lib\r
+else\r
+ifeq ($(suffix $(target)),.elf)\r
+target_type := elf\r
+else\r
+$(error "Target type $(target_type) is not supported")\r
+endif\r
+endif\r
+\r
+# Allow override of operating system detection. The user can add OS=Linux or\r
+# OS=Windows on the command line to explicit set the host OS.\r
+#\r
+# This allows to work around broken uname utility on certain systems.\r
+ifdef OS\r
+ ifeq ($(strip $(OS)), Linux)\r
+ os_type := Linux\r
+ endif\r
+ ifeq (Windows,$(findstring Windows,$(OS)))\r
+ os_type := windows32_64\r
+ endif\r
+endif\r
+\r
+#os_type ?= $(strip $(shell uname))\r
+\r
+#ifeq ($(os_type),windows32)\r
+#os := Windows\r
+#else\r
+#ifeq ($(os_type),windows64)\r
+#os := Windows\r
+#else\r
+#ifeq ($(os_type),)\r
+#os := Windows\r
+#else\r
+## Default to Linux style operating system. Both Cygwin and mingw are fully\r
+## compatible (for this Makefile) with Linux.\r
+#os := Linux\r
+#endif\r
+#endif\r
+#endif\r
+\r
+ifeq ($(os_type),windows32_64)\r
+os := Windows\r
+else\r
+ifeq ($(os_type),Linux)\r
+os := Linux\r
+else\r
+os := Linux\r
+endif\r
+endif\r
+\r
+# Output documentation directory and configuration file.\r
+docdir := ../doxygen/html\r
+doccfg := ../doxygen/doxyfile.doxygen\r
+\r
+CROSS ?= arm-none-eabi-\r
+AR := $(CROSS)ar\r
+AS := $(CROSS)as\r
+CC := $(CROSS)gcc\r
+CPP := $(CROSS)gcc -E\r
+CXX := $(CROSS)g++\r
+LD := $(CROSS)g++\r
+NM := $(CROSS)nm\r
+OBJCOPY := $(CROSS)objcopy\r
+OBJDUMP := $(CROSS)objdump\r
+SIZE := $(CROSS)size\r
+GDB := $(CROSS)gdb\r
+\r
+RM := cs-rm -f\r
+ifeq ($(os),Windows)\r
+#RMDIR := rmdir /S /Q\r
+RMDIR := cs-rm -rf\r
+else\r
+RMDIR := rmdir -p --ignore-fail-on-non-empty\r
+endif\r
+\r
+# Strings for beautifying output\r
+MSG_CLEAN_FILES = "RM *.o *.d"\r
+MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))"\r
+MSG_CLEAN_DOC = "RMDIR $(docdir)"\r
+MSG_MKDIR = "MKDIR $(dir $@)"\r
+\r
+MSG_INFO = "INFO "\r
+\r
+MSG_ARCHIVING = "AR $@"\r
+MSG_ASSEMBLING = "AS $@"\r
+MSG_BINARY_IMAGE = "OBJCOPY $@"\r
+MSG_COMPILING = "CC $@"\r
+MSG_COMPILING_CXX = "CXX $@"\r
+MSG_EXTENDED_LISTING = "OBJDUMP $@"\r
+MSG_IHEX_IMAGE = "OBJCOPY $@"\r
+MSG_LINKING = "LN $@"\r
+MSG_PREPROCESSING = "CPP $@"\r
+MSG_SIZE = "SIZE $@"\r
+MSG_SYMBOL_TABLE = "NM $@"\r
+\r
+MSG_GENERATING_DOC = "DOXYGEN $(docdir)"\r
+\r
+# Don't use make's built-in rules and variables\r
+MAKEFLAGS += -rR\r
+\r
+# Don't print 'Entering directory ...'\r
+MAKEFLAGS += --no-print-directory\r
+\r
+# Function for reversing the order of a list\r
+reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))\r
+\r
+# Hide command output by default, but allow the user to override this\r
+# by adding V=1 on the command line.\r
+#\r
+# This is inspired by the Kbuild system used by the Linux kernel.\r
+ifdef V\r
+ ifeq ("$(origin V)", "command line")\r
+ VERBOSE = $(V)\r
+ endif\r
+endif\r
+ifndef VERBOSE\r
+ VERBOSE = 0\r
+endif\r
+\r
+ifeq ($(VERBOSE), 1)\r
+ Q =\r
+else\r
+# Q = @\r
+ Q =\r
+endif\r
+\r
+arflags-gnu-y := $(ARFLAGS)\r
+asflags-gnu-y := $(ASFLAGS)\r
+cflags-gnu-y := $(CFLAGS)\r
+cxxflags-gnu-y := $(CXXFLAGS)\r
+cppflags-gnu-y := $(CPPFLAGS)\r
+cpuflags-gnu-y :=\r
+dbgflags-gnu-y := $(DBGFLAGS)\r
+libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB))\r
+ldflags-gnu-y := $(LDFLAGS)\r
+flashflags-gnu-y :=\r
+clean-files :=\r
+clean-dirs :=\r
+\r
+clean-files += $(wildcard $(target) $(project).map)\r
+clean-files += $(wildcard $(project).hex $(project).bin)\r
+clean-files += $(wildcard $(project).lss $(project).sym)\r
+clean-files += $(wildcard $(build))\r
+\r
+# Use pipes instead of temporary files for communication between processes\r
+cflags-gnu-y += -pipe\r
+asflags-gnu-y += -pipe\r
+ldflags-gnu-y += -pipe\r
+\r
+# Archiver flags.\r
+arflags-gnu-y += rcs\r
+\r
+# Always enable warnings. And be very careful about implicit\r
+# declarations.\r
+cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes\r
+cflags-gnu-y += -Werror-implicit-function-declaration\r
+cxxflags-gnu-y += -Wall\r
+# IAR doesn't allow arithmetic on void pointers, so warn about that.\r
+cflags-gnu-y += -Wpointer-arith\r
+cxxflags-gnu-y += -Wpointer-arith\r
+\r
+# Preprocessor flags.\r
+cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))\r
+asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')\r
+\r
+# CPU specific flags.\r
+cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__\r
+\r
+# Dependency file flags.\r
+depflags = -MD -MP -MQ $@\r
+\r
+# Debug specific flags.\r
+ifdef BUILD_DEBUG_LEVEL\r
+dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL)\r
+else\r
+dbgflags-gnu-y += -g3\r
+endif\r
+\r
+# Optimization specific flags.\r
+ifdef BUILD_OPTIMIZATION\r
+optflags-gnu-y = -O$(BUILD_OPTIMIZATION)\r
+else\r
+optflags-gnu-y = $(OPTIMIZATION)\r
+endif\r
+\r
+# Always preprocess assembler files.\r
+asflags-gnu-y += -x assembler-with-cpp\r
+# Compile C files using the GNU99 standard.\r
+cflags-gnu-y += -std=gnu99\r
+# Compile C++ files using the GNU++98 standard.\r
+cxxflags-gnu-y += -std=gnu++98\r
+\r
+\r
+# Separate each function and data into its own separate section to allow\r
+# garbage collection of unused sections.\r
+cflags-gnu-y += -ffunction-sections -fdata-sections\r
+cxxflags-gnu-y += -ffunction-sections -fdata-sections\r
+\r
+# Various cflags.\r
+cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int\r
+cflags-gnu-y += -Wmain -Wparentheses\r
+cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused\r
+cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef\r
+cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings\r
+cflags-gnu-y += -Wsign-compare -Waggregate-return \r
+cflags-gnu-y += -Wmissing-declarations\r
+cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations\r
+cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long\r
+cflags-gnu-y += -Wunreachable-code\r
+cflags-gnu-y += -Wcast-align\r
+cflags-gnu-y += --param max-inline-insns-single=500\r
+\r
+# To reduce application size use only integer printf function.\r
+cflags-gnu-y += -Dprintf=iprintf\r
+\r
+# Garbage collect unreferred sections when linking.\r
+ldflags-gnu-y += -Wl,--gc-sections\r
+\r
+# Use the linker script if provided by the project.\r
+ifneq ($(strip $(linker_script)),)\r
+ldflags-gnu-y += -Wl,-T $(linker_script)\r
+endif\r
+\r
+# Output a link map file and a cross reference table\r
+ldflags-gnu-y += -Wl,-Map=$(project).map,--cref\r
+\r
+# Add library search paths relative to the top level directory.\r
+ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))\r
+\r
+a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__\r
+c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)\r
+cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)\r
+l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)\r
+ar_flags = $(arflags-gnu-y)\r
+\r
+# Source files list and part informations must already be included before\r
+# running this makefile\r
+\r
+# If a custom build directory is specified, use it -- force trailing / in directory name.\r
+ifdef BUILD_DIR\r
+ build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)\r
+else\r
+ build-dir =\r
+endif\r
+\r
+# Create object files list from source files list.\r
+obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))\r
+# Create dependency files list from source files list.\r
+dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))\r
+\r
+clean-files += $(wildcard $(obj-y))\r
+clean-files += $(dep-files)\r
+\r
+clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))\r
+\r
+.PHONY: all\r
+\r
+# Default target.\r
+.PHONY: all\r
+ifeq ($(project_type),all)\r
+all:\r
+ $(MAKE) all PROJECT_TYPE=flash\r
+ $(MAKE) all PROJECT_TYPE=sram\r
+else\r
+ifeq ($(target_type),lib)\r
+all: $(target) $(project).lss $(project).sym\r
+else\r
+ifeq ($(target_type),elf)\r
+all: $(target) $(project).lss $(project).sym $(project).hex $(project).bin\r
+endif\r
+endif\r
+endif\r
+\r
+# Default target.\r
+.PHONY: os\r
+os:\r
+ @echo OS '$(OS)'\r
+ @echo os type '$(os_type)'\r
+ @echo os '$(os)'\r
+ @echo '$(findstring Windows,$(OS))'\r
+\r
+# Clean up the project.\r
+.PHONY: clean\r
+clean:\r
+ @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))\r
+ $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)\r
+ @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))\r
+# Remove created directories, and make sure we only remove existing\r
+# directories, since recursive rmdir might help us a bit on the way.\r
+ifeq ($(os),Windows)\r
+ $(Q)$(if $(strip $(clean-dirs)), \\r
+ $(RMDIR) $(strip $(subst /,\,$(clean-dirs))))\r
+else\r
+ $(Q)$(if $(strip $(clean-dirs)), \\r
+ for directory in $(strip $(clean-dirs)); do \\r
+ if [ -d "$$directory" ]; then \\r
+ $(RMDIR) $$directory; \\r
+ fi \\r
+ done \\r
+ )\r
+endif\r
+\r
+# Rebuild the project.\r
+.PHONY: rebuild\r
+rebuild: clean all\r
+\r
+# Debug the project in flash.\r
+.PHONY: debug_flash\r
+debug_flash: all\r
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)\r
+\r
+# Debug the project in sram.\r
+.PHONY: debug_sram\r
+debug_sram: all\r
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)\r
+\r
+.PHONY: objfiles\r
+objfiles: $(obj-y)\r
+\r
+# Create object files from C source files.\r
+$(build-dir)%.o: %.c $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk\r
+ @echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ -mkdir $(subst /,\,$(dir $@))\r
+else\r
+ -mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_COMPILING)\r
+ $(Q)$(CC) $(c_flags) -c $< -o $@\r
+\r
+# Create object files from C++ source files.\r
+$(build-dir)%.o: %.cpp $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk\r
+ @echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ -mkdir $(subst /,\,$(dir $@))\r
+else\r
+ -mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_COMPILING_CXX)\r
+ $(Q)$(CXX) $(cxx_flags) -c $< -o $@\r
+\r
+# Preprocess and assemble: create object files from assembler source files.\r
+$(build-dir)%.o: %.S $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk\r
+ @echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ -mkdir $(subst /,\,$(dir $@))\r
+else\r
+ -mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_ASSEMBLING)\r
+ $(Q)$(CC) $(a_flags) -c $< -o $@\r
+\r
+# Include all dependency files to add depedency to all header files in use.\r
+include $(dep-files)\r
+\r
+ifeq ($(target_type),lib)\r
+# Archive object files into an archive\r
+$(target): $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk $(obj-y)\r
+ @echo $(MSG_ARCHIVING)\r
+ $(Q)$(AR) $(ar_flags) $@ $(obj-y)\r
+ @echo $(MSG_SIZE)\r
+ $(Q)$(SIZE) -Bxt $@\r
+else\r
+ifeq ($(target_type),elf)\r
+# Link the object files into an ELF file. Also make sure the target is rebuilt\r
+# if the common Makefile.in or project config.mk is changed.\r
+$(target): $(linker_script) $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk $(obj-y)\r
+ @echo $(MSG_LINKING)\r
+ @echo $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@\r
+ $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@\r
+ @echo $(MSG_SIZE)\r
+ $(Q)$(SIZE) -Ax $@\r
+ $(Q)$(SIZE) -Bx $@\r
+endif\r
+endif\r
+\r
+# Create extended function listing from target output file.\r
+%.lss: $(target)\r
+ @echo $(MSG_EXTENDED_LISTING)\r
+ $(Q)$(OBJDUMP) -h -S $< > $@\r
+\r
+# Create symbol table from target output file.\r
+%.sym: $(target)\r
+ @echo $(MSG_SYMBOL_TABLE)\r
+ $(Q)$(NM) -n $< > $@\r
+\r
+# Create Intel HEX image from ELF output file.\r
+%.hex: $(target)\r
+ @echo $(MSG_IHEX_IMAGE)\r
+ $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@\r
+\r
+# Create binary image from ELF output file.\r
+%.bin: $(target)\r
+ @echo $(MSG_BINARY_IMAGE)\r
+ $(Q)$(OBJCOPY) -O binary $< $@\r
+\r
+# Provide information about the detected host operating system.\r
+.SECONDARY: info-os\r
+info-os:\r
+ @echo $(MSG_INFO)$(os) build host detected\r
+\r
+# Build Doxygen generated documentation.\r
+.PHONY: doc\r
+doc:\r
+ @echo $(MSG_GENERATING_DOC)\r
+ $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))\r
+\r
+# Clean Doxygen generated documentation.\r
+.PHONY: cleandoc\r
+cleandoc:\r
+ @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))\r
+ $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))\r
+\r
+# Rebuild the Doxygen generated documentation.\r
+.PHONY: rebuilddoc\r
+rebuilddoc: cleandoc doc\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor macro repeating utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _MREPEAT_H_\r
+#define _MREPEAT_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+#include "preprocessor.h"\r
+\r
+\r
+//! Maximal number of repetitions supported by MREPEAT.\r
+#define MREPEAT_LIMIT 256\r
+\r
+/*! \brief Macro repeat.\r
+ *\r
+ * This macro represents a horizontal repetition construct.\r
+ *\r
+ * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.\r
+ * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with\r
+ * the current repetition number and the auxiliary data argument.\r
+ * \param data Auxiliary data passed to macro.\r
+ *\r
+ * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>\r
+ */\r
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)\r
+\r
+#define MREPEAT0( macro, data)\r
+#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)\r
+#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)\r
+#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)\r
+#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)\r
+#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)\r
+#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)\r
+#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)\r
+#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)\r
+#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)\r
+#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)\r
+#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)\r
+#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)\r
+#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)\r
+#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)\r
+#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)\r
+#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)\r
+#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)\r
+#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)\r
+#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)\r
+#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)\r
+#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)\r
+#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)\r
+#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)\r
+#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)\r
+#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)\r
+#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)\r
+#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)\r
+#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)\r
+#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)\r
+#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)\r
+#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)\r
+#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)\r
+#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)\r
+#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)\r
+#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)\r
+#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)\r
+#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)\r
+#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)\r
+#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)\r
+#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)\r
+#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)\r
+#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)\r
+#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)\r
+#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)\r
+#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)\r
+#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)\r
+#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)\r
+#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)\r
+#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)\r
+#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)\r
+#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)\r
+#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)\r
+#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)\r
+#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)\r
+#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)\r
+#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)\r
+#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)\r
+#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)\r
+#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)\r
+#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)\r
+#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)\r
+#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)\r
+#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)\r
+#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)\r
+#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)\r
+#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)\r
+#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)\r
+#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)\r
+#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)\r
+#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)\r
+#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)\r
+#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)\r
+#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)\r
+#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)\r
+#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)\r
+#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)\r
+#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)\r
+#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)\r
+#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)\r
+#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)\r
+#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)\r
+#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)\r
+#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)\r
+#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)\r
+#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)\r
+#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)\r
+#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)\r
+#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)\r
+#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)\r
+#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)\r
+#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)\r
+#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)\r
+#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)\r
+#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)\r
+#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)\r
+#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)\r
+#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)\r
+#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)\r
+#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)\r
+#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)\r
+#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)\r
+#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)\r
+#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)\r
+#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)\r
+#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)\r
+#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)\r
+#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)\r
+#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)\r
+#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)\r
+#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)\r
+#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)\r
+#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)\r
+#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)\r
+#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)\r
+#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)\r
+#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)\r
+#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)\r
+#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)\r
+#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)\r
+#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)\r
+#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)\r
+#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)\r
+#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)\r
+#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)\r
+#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)\r
+#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)\r
+#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)\r
+#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)\r
+#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)\r
+#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)\r
+#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)\r
+#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)\r
+#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)\r
+#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)\r
+#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)\r
+#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)\r
+#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)\r
+#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)\r
+#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)\r
+#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)\r
+#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)\r
+#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)\r
+#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)\r
+#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)\r
+#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)\r
+#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)\r
+#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)\r
+#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)\r
+#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)\r
+#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)\r
+#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)\r
+#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)\r
+#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)\r
+#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)\r
+#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)\r
+#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)\r
+#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)\r
+#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)\r
+#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)\r
+#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)\r
+#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)\r
+#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)\r
+#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)\r
+#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)\r
+#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)\r
+#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)\r
+#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)\r
+#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)\r
+#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)\r
+#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)\r
+#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)\r
+#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)\r
+#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)\r
+#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)\r
+#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)\r
+#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)\r
+#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)\r
+#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)\r
+#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)\r
+#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)\r
+#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)\r
+#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)\r
+#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)\r
+#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)\r
+#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)\r
+#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)\r
+#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)\r
+#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)\r
+#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)\r
+#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)\r
+#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)\r
+#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)\r
+#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)\r
+#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)\r
+#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)\r
+#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)\r
+#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)\r
+#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)\r
+#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)\r
+#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)\r
+#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)\r
+#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)\r
+#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)\r
+#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)\r
+#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)\r
+#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)\r
+#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)\r
+#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)\r
+#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)\r
+#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)\r
+#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)\r
+#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)\r
+#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)\r
+#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)\r
+#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)\r
+#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)\r
+#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)\r
+#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)\r
+#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)\r
+#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)\r
+#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)\r
+#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)\r
+#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)\r
+#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)\r
+#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)\r
+#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)\r
+#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)\r
+#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)\r
+#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)\r
+#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)\r
+#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)\r
+#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)\r
+#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)\r
+#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)\r
+#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)\r
+#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)\r
+#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)\r
+#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)\r
+#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)\r
+#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)\r
+#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)\r
+#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)\r
+#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)\r
+#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)\r
+#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)\r
+#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)\r
+#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)\r
+#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)\r
+#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)\r
+#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)\r
+#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)\r
+#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)\r
+#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)\r
+#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)\r
+#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)\r
+#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _MREPEAT_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _PREPROCESSOR_H_\r
+#define _PREPROCESSOR_H_\r
+\r
+#include "tpaste.h"\r
+#include "stringz.h"\r
+#include "mrepeat.h"\r
+\r
+\r
+#endif // _PREPROCESSOR_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor stringizing utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _STRINGZ_H_\r
+#define _STRINGZ_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_stringz Preprocessor - Stringize\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+/*! \brief Stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the token passed as an argument if the token is \#defined.\r
+ *\r
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)\r
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to\r
+ * writing "A0".\r
+ */\r
+#define STRINGZ(x) #x\r
+\r
+/*! \brief Absolute stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the token is \#defined.\r
+ *\r
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is\r
+ * equivalent to writing "A0".\r
+ */\r
+#define ASTRINGZ(x) STRINGZ(x)\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _STRINGZ_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor token pasting utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _TPASTE_H_\r
+#define _TPASTE_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+/*! \name Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.\r
+ *\r
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by\r
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is\r
+ * equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define TPASTE2( a, b) a##b\r
+#define TPASTE3( a, b, c) a##b##c\r
+#define TPASTE4( a, b, c, d) a##b##c##d\r
+#define TPASTE5( a, b, c, d, e) a##b##c##d##e\r
+#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f\r
+#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g\r
+#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h\r
+#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i\r
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j\r
+//! @}\r
+\r
+/*! \name Absolute Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the tokens are \#defined.\r
+ *\r
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined\r
+ * as 32 is equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define ATPASTE2( a, b) TPASTE2( a, b)\r
+#define ATPASTE3( a, b, c) TPASTE3( a, b, c)\r
+#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)\r
+#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)\r
+#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)\r
+#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)\r
+#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)\r
+#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)\r
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)\r
+//! @}\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _TPASTE_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Status code definitions.\r
+ *\r
+ * This file defines various status codes returned by functions,\r
+ * indicating success or failure as well as what kind of failure.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef STATUS_CODES_H_INCLUDED\r
+#define STATUS_CODES_H_INCLUDED\r
+\r
+/**\r
+ * Status code that may be returned by shell commands and protocol\r
+ * implementations.\r
+ *\r
+ * \note Any change to these status codes and the corresponding\r
+ * message strings is strictly forbidden. New codes can be added,\r
+ * however, but make sure that any message string tables are updated\r
+ * at the same time.\r
+ */\r
+enum status_code {\r
+ STATUS_OK = 0, //!< Success\r
+ ERR_IO_ERROR = -1, //!< I/O error\r
+ ERR_FLUSHED = -2, //!< Request flushed from queue\r
+ ERR_TIMEOUT = -3, //!< Operation timed out\r
+ ERR_BAD_DATA = -4, //!< Data integrity check failed\r
+ ERR_PROTOCOL = -5, //!< Protocol error\r
+ ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device\r
+ ERR_NO_MEMORY = -7, //!< Insufficient memory\r
+ ERR_INVALID_ARG = -8, //!< Invalid argument\r
+ ERR_BAD_ADDRESS = -9, //!< Bad address\r
+ ERR_BUSY = -10, //!< Resource is busy\r
+ ERR_BAD_FORMAT = -11, //!< Data format not recognized\r
+\r
+ /**\r
+ * \brief Operation in progress\r
+ *\r
+ * This status code is for driver-internal use when an operation\r
+ * is currently being performed.\r
+ *\r
+ * \note Drivers should never return this status code to any\r
+ * callers. It is strictly for internal use.\r
+ */\r
+ OPERATION_IN_PROGRESS = -128,\r
+};\r
+\r
+typedef enum status_code status_code_t;\r
+\r
+#endif /* STATUS_CODES_H_INCLUDED */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V2.11\r
+ * @date 08. September 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+\r
+/** \mainpage CMSIS Cortex-M3\r
+\r
+ This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.\r
+ It consists of:\r
+\r
+ - Cortex-M Core Register Definitions\r
+ - Cortex-M functions\r
+ - Cortex-M instructions\r
+\r
+ The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease\r
+ access to the Cortex-M Core\r
+ */\r
+\r
+/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates following MISRA-C2004 Rules:\r
+ \r
+ - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'. \r
+\r
+ - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+ \r
+ - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code. \r
+\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core\r
+ - Cortex-M core Revision Number\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+#define __FPU_USED 0 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ /* add preprocessor checks */\r
+#endif\r
+\r
+#include <stdint.h> /*!< standard types definitions */\r
+#include "core_cmInstr.h" /*!< Core Instruction Access */\r
+#include "core_cmFunc.h" /*!< Core Function Access */\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM3_REV\r
+ #define __CM3_REV 0x0200\r
+ #warning "__CM3_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+/*@} end of group CMSIS_core_definitions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register CMSIS Core Register\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE CMSIS Core\r
+ Type definitions for the Cortex-M Core Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC CMSIS NVIC\r
+ Type definitions for the Cortex-M NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB CMSIS SCB\r
+ Type definitions for the Cortex-M System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#if (__CM3_REV < 0x0201) /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#else\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB\r
+ Type definitions for the Cortex-M System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1[1];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick CMSIS SysTick\r
+ Type definitions for the Cortex-M System Timer Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM CMSIS ITM\r
+ Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */\r
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU CMSIS MPU\r
+ Type definitions for the Cortex-M Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug\r
+ Type definitions for the Cortex-M Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ This function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ This function gets the priority grouping from NVIC Interrupt Controller.\r
+ Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+\r
+ \return Priority grouping field\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ This function enables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to enable\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ This function disables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to disable\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ This function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for get pending\r
+ \return 0 Interrupt status is not pending\r
+ \return 1 Interrupt status is pending\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ This function sets the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for set pending\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ This function clears the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for clear pending\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ This function reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Number of the interrupt for get active\r
+ \return 0 Interrupt status is not active\r
+ \return 1 Interrupt status is active\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ This function sets the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ Note: The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for set priority\r
+ \param [in] priority Priority to set\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ This function reads the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ The returned priority value is automatically aligned to the implemented\r
+ priority bits of the microcontroller.\r
+\r
+ \param [in] IRQn Number of the interrupt for get priority\r
+ \return Interrupt Priority\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ This function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ The returned priority value can be used for NVIC_SetPriority(...) function\r
+\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0)\r
+ \param [in] SubPriority Sub priority value (starting from 0)\r
+ \return Encoded priority for the interrupt\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ This function decodes an interrupt priority value with the given priority group to\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ The priority value can be retrieved with NVIC_GetPriority(...) function\r
+\r
+ \param [in] Priority Priority value\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0)\r
+ \param [out] pSubPriority Sub priority value (starting from 0)\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ This function initiate a system reset request to reset the MCU.\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ This function initialises the system tick timer and its interrupt and start the system tick timer.\r
+ Counter is in free running mode to generate periodical interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ This function transmits a character via the ITM channel 0.\r
+ It just returns when no debugger is connected that has booked the output.\r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+\r
+ \param [in] ch Character to transmit\r
+ \return Character to transmit\r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ This function inputs a character via external variable ITM_RxBuffer.\r
+ It just returns when no debugger is connected that has booked the output.\r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+\r
+ \return Received character\r
+ \return -1 No character received\r
+ */\r
+static __INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ This function checks external variable ITM_RxBuffer whether a character is available or not.\r
+ It returns '1' if a character is available and '0' if no character is available.\r
+\r
+ \return 0 No character available\r
+ \return 1 Character available\r
+ */\r
+static __INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V2.10\r
+ * @date 26. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface \r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+static __INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+static __INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+static __INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+static __INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+static __INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+ \r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+static __INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+static __INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V2.10\r
+ * @date 19. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor, \r
+ so that all instructions following the ISB are fetched from cache or \r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier. \r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before \r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+static __INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+static __INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz \r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor, \r
+ so that all instructions following the ISB are fetched from cache or \r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier. \r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before \r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint8_t result;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint16_t result;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint8_t result;\r
+ \r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+* -------------------------------------------------------------------\r
+* Copyright (C) 2011 ARM Limited. All rights reserved. \r
+* \r
+* Date: 25 July 2011 \r
+* Revision: V2.10 \r
+* \r
+* Project: Cortex Microcontroller Software Interface Standard (CMSIS)\r
+* Title: Release Note for CMSIS\r
+*\r
+* -------------------------------------------------------------------\r
+\r
+\r
+NOTE - Open the index.html file to access CMSIS documentation\r
+\r
+\r
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all \r
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects \r
+and reduces time-to-market for new embedded applications.\r
+\r
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").\r
+Any user of the software package is bound to the terms and conditions of the end user license agreement.\r
+\r
+\r
+You will find the following sub-directories:\r
+\r
+Documentation - Contains CMSIS documentation.\r
+ \r
+DSP_Lib - MDK project files, Examples and source files etc.. to build the \r
+ CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.\r
+\r
+Include - CMSIS Core Support and CMSIS DSP Include Files.\r
+\r
+Lib - CMSIS DSP Binaries \r
+---\r
--- /dev/null
+END USER LICENCE AGREEMENT FOR THE CORTEX MICROCONTROLLER SOFTWARE INTERFACE\r
+STANDARD (CMSIS) SPECIFICATION AND SOFTWARE\r
+\r
+THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A\r
+SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE\r
+CMSIS SPECIFICATION, EXAMPLE CODE, DSP LIBRARY SPECIFICATION AND DSP LIBRARY\r
+IMPLEMENTATION AS SUCH TERMS ARE DEFINED BELOW (COLLECTIVELY, THE "ARM\r
+DELIVERABLES"). ARM IS ONLY WILLING TO LICENSE THE ARM DELIVERABLES TO YOU ON CONDITION\r
+THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING\r
+OR OTHERWISE USING OR COPYING THE ARM DELIVERABLES YOU INDICATE THAT YOU AGREE TO\r
+BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS\r
+LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE THE ARM DELIVERABLES AND YOU MAY NOT\r
+INSTALL, USE OR COPY THE ARM DELIVERABLES.\r
+\r
+"CMSIS Specification" means any documentation and C programming language files defining the application\r
+programming interface, naming and coding conventions of the Cortex Microcontroller Software Interface\r
+Standard (CMSIS) as well as the System View Description (SVD) documentation and associated XML schema\r
+file. Notwithstanding the foregoing, "CMSIS Specification" shall not include (i) the implementation of other\r
+published specifications referenced in the CMSIS Specification; (ii) any enabling technologies that may be\r
+necessary to make or use any product or portion thereof that complies with the CMSIS Specification, but are not\r
+themselves expressly set forth in the CMSIS Specification (e.g. compiler front ends, code generators, back ends,\r
+libraries or other compiler, assembler or linker technologies; validation or debug software or hardware;\r
+applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii)\r
+maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of\r
+integrated circuit designs.\r
+\r
+"DSP Library Implementation" means any C programming language source code implementing the functionality\r
+of the digital signal processor (DSP) algorithms and the application programming interface as defined in the DSP\r
+Library Specification. The DSP Library Implementation makes use of CMSIS application programming interface\r
+and therefore is targeted at Cortex-M class processors.\r
+\r
+"DSP Library Specification" means the DSP library documentation and C programming language file defining the\r
+application programming interface of the DSP Library Implementation. Notwithstanding the foregoing, "DSP\r
+Library Specification" shall not include (i) the implementation of other published specifications referenced in the\r
+DSP Library Specification; (ii) any enabling technologies that may be necessary to make or use any product or\r
+portion thereof that complies with the DSP Library Specification, but are not themselves expressly set forth in the\r
+DSP Library Specification (e.g. compiler front ends, code generators, back ends, libraries or other compiler,\r
+assembler or linker technologies; validation or debug software or hardware; applications, operating system or\r
+driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of\r
+integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs.\r
+\r
+"Example Code" means any files in C, C++ or ARM assembly programming languages, associated project and\r
+configuration files that demonstrate the usage of the CMSIS Specification, the DSP Library Specification and the\r
+DSP Library Implementation, for microprocessors or device specific software applications that are for use with\r
+microprocessors.\r
+\r
+1. LICENCE GRANTS.\r
+\r
+1.1 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, nontransferable\r
+licence, to;\r
+\r
+(i) use and copy the CMSIS Specification for the purpose of developing, having developed, manufacturing,\r
+having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the\r
+CMSIS Specification, provided that you preserve any copyright notices which are included with, or in, the CMSIS\r
+Specification and provided that you do not use ARM's name, logo or trademarks to market such products;\r
+\r
+(ii) use, copy, and modify (solely to the extent necessary to incorporate the whole or any part of the DSP Library\r
+Specification into your documentation), the DSP Library Specification, for the purpose of developing, having\r
+developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing\r
+products that comply with the DSP Library Specification, and distribute and have distributed any documentation\r
+created by or for you that has been derived from the DSP Library Specification with such products, provided that\r
+you preserve any copyright notices which are included with, or in, the DSP Library Specification and provided that\r
+you do not use ARM's name, logo or trademarks to market such products;\r
+\r
+(iii) use, copy, modify and sublicense the Example Code solely for the purpose of developing, having developed,\r
+manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that\r
+comply with either or both the CMSIS Specification and the DSP Library Specification, provided that you preserve\r
+any copyright notices which are included with, or in, the Example Code and that you do not use ARM's name,\r
+logo or trademarks to market such products;\r
+\r
+(iv) use, copy and modify (provided that the logical functionality and the application programming interface of the\r
+DSP Library Implementation are maintained) the DSP Library Implementation, solely for the purposes of\r
+developing; (a) software applications for use with microprocessors manufactured or simulated under licence from\r
+ARM ("Software Applications"); and (b) tools that are designed to develop software programs for use with\r
+microprocessors manufactured or simulated under licence from ARM ("Tools"); and\r
+\r
+(v) subject to clause 1.1(vi) below; (a) distribute and sublicense the use of the DSP Library Implementation\r
+(including any modified forms thereof created under Clause 1.1(iv) above) in binary or source format, solely as\r
+incorporated into Software Library Applications and Tools to third parties; and (b) sublicense to such third parties\r
+the right to use and copy the Tools for the purposes of developing and distribute software programs for use with\r
+microprocessors manufactured or simulated under licence from ARM.\r
+\r
+(vi) CONDITIONS ON REDISTRIBUTION: If you choose to redistribute the whole or any part of the DSP Library\r
+Implementation as incorporated into Software Library Applications or Tools, you agree to; (a) ensure that the\r
+DSP Library Implementation is licensed for use only as part of Software Library Applications and Tools and only\r
+for use with microprocessors manufactured or simulated under licence from ARM; (b) not to use ARM's name,\r
+logo or trademarks to market Software Applications and Tools; and (c) include valid copyright notices on\r
+Software Applications and Tools, and preserve any copyright notices which are included with, or in, the DSP\r
+Library Implementation.\r
+\r
+2. RESTRICTIONS ON USE OF THE ARM DELIVERABLES.\r
+\r
+PERMITTED USERS: The ARM Deliverables shall be used only by you (either a single individual, or single legal\r
+entity) your employees, or by your on-site bona fide sub-contractors for whose acts and omissions you hereby\r
+agree to be responsible to ARM for to the same extent as you are for your employees, and provided always that\r
+such sub-contractors; (i) are contractually obligated to use the ARM Deliverables only for your benefit, and (ii)\r
+agree to assign all their work product and any rights they create therein in the supply of such work to you.\r
+COPYRIGHT AND RESERVATION OF RIGHTS: The ARM Deliverables are owned by ARM or its licensors and\r
+are protected by copyright and other intellectual property laws and international treaties. The ARM Deliverables\r
+are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the ARM\r
+Deliverables or any intellectual property therein. In no event shall the licences granted herein be construed as\r
+granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except\r
+the ARM Deliverables.\r
+\r
+3. SUPPORT.\r
+\r
+ARM is not obligated to support the ARM Deliverables but may do so entirely at ARM's discretion.\r
+\r
+4. NO WARRANTY\r
+\r
+YOU AGREE THAT THE ARM DELIVERABLES ARE LICENSED "AS IS", AND THAT ARM EXPRESSLY\r
+DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS,\r
+IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF NONINFRINGEMENT,\r
+SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE. THE ARM\r
+DELIVERABLES MAY CONTAIN ERRORS. ARM RESERVES THE RIGHT TO INCORPORATE\r
+MODIFICATIONS TO THE ARM DELIVERABLES IN LATER REVISIONS OF THEM, AND TO MAKE\r
+IMPROVEMENTS OR CHANGES IN THE ARM DELIVERABLES AT ANY TIME.\r
+\r
+5. LIMITATION OF LIABILITY.\r
+\r
+THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN\r
+CONTRACT, TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS\r
+LICENCE SHALL NOT EXCEED THE GREATER OF (I) THE TOTAL OF SUMS PAID BY YOU TO ARM (IF\r
+ANY) FOR THIS LICENCE AND (II) US$10.00. THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN\r
+THIS LICENCE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW.\r
+\r
+6. U.S. GOVERNMENT END USERS.\r
+US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this\r
+commercial product and accompanying documentation is restricted in accordance with the terms of this Licence.\r
+\r
+7. TERM AND TERMINATION.\r
+\r
+7.1 This Licence shall remain in force until terminated in accordance with the terms of Clause 7.2 or Clause 7.3\r
+below.\r
+\r
+7.2 Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this\r
+Licence then ARM may terminate this Licence immediately upon giving written notice to you. You may terminate\r
+this Licence at any time.\r
+\r
+7.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you\r
+asserts any patents against ARM, ARM affiliates, third parties who have a valid licence from ARM for the ARM\r
+Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate)\r
+patent is Necessary to implement the CMSIS Specification or DSP Library Specification. In this Licence; (i)\r
+"affiliate" means any entity controlling, controlled by or under common control with a party (in fact or in law, via\r
+voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert"\r
+means to allege infringement in legal or administrative proceedings, or proceedings before any other competent\r
+trade, arbitral or international authority; (iii) "Necessary" means with respect to any claims of any patent, those\r
+claims which, without the appropriate permission of the patent owner, will be infringed when implementing the\r
+CMSIS Specification or DSP Library Specification because no alternative, commercially reasonable, noninfringing\r
+way of implementing the CMSIS Specification or DSP Library Specification is known.\r
+\r
+7.4 Upon termination of this Licence, you shall stop using the ARM Deliverables and destroy all copies of the\r
+ARM Deliverables in your possession. The provisions of clauses 5, 6, 7, and 8 shall survive termination of this\r
+Licence.\r
+\r
+8. GENERAL.\r
+\r
+This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by\r
+you and ARM, this is the only agreement between you and ARM relating to the ARM Deliverables and it may only\r
+be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence\r
+may not be modified by purchase orders, advertising or other representation by any person. If any clause or\r
+sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this\r
+Licence shall not be affected thereby. The failure by ARM to enforce any of the provisions of this Licence, unless\r
+waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of\r
+this Licence in the future. This Licence may not be assigned without the prior written consent of ARM.\r
+\r
+ARM contract reference LEC-PRE-00489\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Board configuration.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CONF_BOARD_H_INCLUDED\r
+#define CONF_BOARD_H_INCLUDED\r
+\r
+/* Configure UART pins */\r
+//#define CONF_BOARD_UART_CONSOLE\r
+\r
+/* Configure ADC example pins */\r
+//#define CONF_BOARD_ADC\r
+\r
+/*\r
+ * LED pins are not configured for PWM function here.\r
+ * Because those LED pins are enabled for PIO function by default.\r
+ * You can enable them according to application.\r
+ */\r
+/* Configure PWM LED0 pin */\r
+//#define CONF_BOARD_PWM_LED0\r
+\r
+/* Configure PWM LED1 pin */\r
+//#define CONF_BOARD_PWM_LED1\r
+\r
+/* Configure PWM LED2 pin */\r
+//#define CONF_BOARD_PWM_LED2\r
+\r
+/* Configure SPI pins */\r
+//#define CONF_BOARD_SPI\r
+//#define CONF_BOARD_SPI_NPCS0\r
+//#define CONF_BOARD_SPI_NPCS1\r
+//#define CONF_BOARD_SPI_NPCS2\r
+//#define CONF_BOARD_SPI_NPCS3\r
+\r
+/*\r
+ * USART pins are configured as basic serial port by default.\r
+ * You can enable other pins according application.\r
+ */\r
+/* Configure USART RXD pin */\r
+#define CONF_BOARD_USART_RXD\r
+\r
+/* Configure USART TXD pin */\r
+#define CONF_BOARD_USART_TXD\r
+\r
+/* Configure USART CTS pin */\r
+//#define CONF_BOARD_USART_CTS\r
+\r
+/* Configure USART RTS pin */\r
+//#define CONF_BOARD_USART_RTS\r
+\r
+/* Configure USART synchronous communication SCK pin */\r
+//#define CONF_BOARD_USART_SCK\r
+\r
+/* Configure ADM33312 enable pin */\r
+#define CONF_BOARD_ADM3312_EN\r
+\r
+/* Configure IrDA transceiver shutdown pin */\r
+//#define CONF_BOARD_TFDU4300_SD\r
+\r
+/* Configure RS485 transceiver RE pin */\r
+//#define CONF_BOARD_ADM3485_RE\r
+\r
+/* Configure LCD EBI pins */\r
+//#define CONF_BOARD_ILI9325\r
+\r
+/* Configure Backlight control pin */\r
+//#define CONF_BOARD_AAT3155\r
+\r
+/* Configure Touchscreen SPI pins */\r
+//#define CONF_BOARD_ADS7843\r
+\r
+#endif /* CONF_BOARD_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM3S clock configuration.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CONF_CLOCK_H_INCLUDED\r
+#define CONF_CLOCK_H_INCLUDED\r
+\r
+// ===== System Clock (MCK) Source Options\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS\r
+#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLBCK\r
+\r
+// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES))\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3\r
+\r
+// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)\r
+// Use mul and div effective values here.\r
+#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+#define CONFIG_PLL0_MUL 32\r
+#define CONFIG_PLL0_DIV 3\r
+\r
+// ===== PLL1 (B) Options (Fpll = (Fclk * PLL_mul) / PLL_div)\r
+// Use mul and div effective values here.\r
+#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL\r
+#define CONFIG_PLL1_MUL 16\r
+#define CONFIG_PLL1_DIV 2\r
+\r
+// ===== USB Clock Source Options (Fusb = FpllX / USB_div)\r
+// Use div effective value here.\r
+//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0\r
+//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1\r
+//#define CONFIG_USBCLK_DIV 2\r
+\r
+// ===== Target frequency (System clock)\r
+// - XTAL frequency: 12MHz\r
+// - System clock source: PLLA\r
+// - System clock prescaler: 2 (divided by 2)\r
+// - PLLA source: XTAL\r
+// - PLLA output: XTAL * 32 / 3\r
+// - System clock is: 12 * 32 / 3 / 2 = 64MHz\r
+// ===== Target frequency (USB Clock)\r
+// - USB clock source: PLLB\r
+// - USB clock divider: 2 (divided by 2)\r
+// - PLLB output: XTAL * 16 / 2\r
+// - USB clock: 12 * 16 / 2 / 2 = 48MHz\r
+\r
+\r
+#endif /* CONF_CLOCK_H_INCLUDED */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, training, latest information,\r
+ license and contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+ the code with commercial support, indemnification, and middleware, under\r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under\r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard demo includes - just needed for the LED (ParTest) initialisation\r
+function. */\r
+#include "partest.h"\r
+\r
+/* Atmel library includes. */\r
+#include <asf.h>\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Set up the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+extern void main_blinky( void );\r
+extern void main_full( void );\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the documentation page for this demo on the FreeRTOS.org web site for\r
+full information - including hardware setup requirements. */\r
+\r
+int main( void )\r
+{\r
+ /* Prepare the hardware to run this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+extern void SystemCoreClockUpdate( void );\r
+\r
+ /* ASF function to setup clocking. */\r
+ sysclk_init();\r
+\r
+ /* Ensure all priority bits are assigned as preemption priority bits. */\r
+ NVIC_SetPriorityGrouping( 0 );\r
+\r
+ /* Atmel library function to setup for the evaluation kit being used. */\r
+ board_init();\r
+\r
+ /* Perform any configuration necessary to use the ParTest LED output\r
+ functions. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if\r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles the LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Atmel library includes. */\r
+#include "asf.h"\r
+\r
+/* Common demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* Values passed to the two tasks just to check the task parameter \r
+functionality. */\r
+#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
+#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Called by main() to create the simply blinky style application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was insufficient FreeRTOS heap memory available for the idle and/or\r
+ timer tasks to be created. See the memory management section on the\r
+ FreeRTOS web site for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again.\r
+ The block time is specified in ticks, the constant used converts ticks\r
+ to ms. While in the Blocked state this task will not consume any CPU\r
+ time. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == 100UL )\r
+ {\r
+ vParTestToggleLED( 0 );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and a software timer, then\r
+ * starts the scheduler. The web documentation provides more details of the \r
+ * standard demo application tasks, which provide no particular functionality, \r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Check" timer - The check software timer period is initially set to three\r
+ * seconds. The callback function associated with the check software timer\r
+ * checks that all the standard demo tasks are not only still executing, but \r
+ * are executing without reporting any errors. If the check software timer \r
+ * discovers that a task has either stalled, or reported an error, then it \r
+ * changes its own execution period from the initial three seconds, to just \r
+ * 200ms. The check software timer callback function also toggles the green \r
+ * LED each time it is called. This provides a visual indication of the system \r
+ * status: If the green LED toggles every three seconds, then no issues have \r
+ * been discovered. If the green LED toggles every 200ms, then an issue has \r
+ * been discovered with at least one task.\r
+ *\r
+ * See the documentation page for this demo on the FreeRTOS.org web site for\r
+ * full information, including hardware setup requirements. \r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "flash_timer.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+\r
+\r
+/* Atmel library includes. */\r
+#include "asf.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/* The standard demo flash timers can be used to flash any number of LEDs. In\r
+this case, because only three LEDs are available, and one is in use by the\r
+check timer, only two are used by the flash timers. */\r
+#define mainNUMBER_OF_FLASH_TIMERS_LEDS ( 2 )\r
+\r
+/* The LED toggled by the check timer. The first two LEDs are toggle by the\r
+standard demo flash timers. */\r
+#define mainCHECK_LED ( 2 )\r
+\r
+/* Baud rate used by the comtest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( 115200 )\r
+\r
+/* The LED used by the comtest tasks. In this case, there are no LEDs available\r
+for the comtest, so the LED number is deliberately out of range. */\r
+#define mainCOM_TEST_LED ( 3 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+xTimerHandle xCheckTimer = NULL;\r
+\r
+ /* Start all the other standard demo/test tasks. The have not particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartLEDFlashTimers( mainNUMBER_OF_FLASH_TIMERS_LEDS );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ \r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ ); \r
+ \r
+ if( xCheckTimer != NULL )\r
+ {\r
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+ }\r
+\r
+ /* The set of tasks created by the following function call have to be \r
+ created last as they keep account of the number of tasks they expect to see \r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* If all is well, the scheduler will now be running, and the following line\r
+ will never be reached. If the following line does execute, then there was\r
+ insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+ to be created. See the memory management section on the FreeRTOS web site\r
+ for more details. */\r
+ for( ;; ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ they are all still running, and that none have detected an error. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ \r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ \r
+ /* Have any errors been latch in ulErrorFound? If so, shorten the\r
+ period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+ This will result in an increase in the rate at which mainCHECK_LED\r
+ toggles. */\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+ \r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, training, latest information,\r
+ license and contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+ the code with commercial support, indemnification, and middleware, under\r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under\r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART1.\r
+\r
+ ***Note*** This example uses queues to send each character into an interrupt\r
+ service routine and out of an interrupt service routine individually. This\r
+ is done to demonstrate queues being used in an interrupt, and to deliberately\r
+ load the system to test the FreeRTOS port. It is *NOT* meant to be an\r
+ example of an efficient implementation. An efficient implementation should\r
+ use FIFO's or DMA if available, and only use FreeRTOS API functions when\r
+ enough has been received to warrant a task being unblocked to process the\r
+ data.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+#include "comtest2.h"\r
+\r
+/* Library includes. */\r
+#include "asf.h"\r
+\r
+/* Demo application includes. */\r
+#include "demo_serial.h"\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Misc defines. */\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+#define serPMC_USART_ID ( BOARD_ID_USART )\r
+\r
+/* The USART supported by this file. */\r
+#define serUSART_PORT ( USART1 )\r
+#define serUSART_IRQ ( USART1_IRQn )\r
+\r
+/* Every bit in the interrupt mask. */\r
+#define serMASK_ALL_INTERRUPTS ( 0xffffffffUL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * See the serial.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+uint32_t ulChar;\r
+xComPortHandle xReturn;\r
+const sam_usart_opt_t xUSARTSettings =\r
+{\r
+ ulWantedBaud,\r
+ US_MR_CHRL_8_BIT,\r
+ US_MR_PAR_NO,\r
+ US_MR_NBSTOP_1_BIT,\r
+ US_MR_CHMODE_NORMAL,\r
+ 0 /* Only used in IrDA mode. */\r
+};\r
+\r
+ /* Create the queues used to hold Rx/Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+\r
+ /* If the queues were created correctly then setup the serial port\r
+ hardware. */\r
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+ {\r
+ /* Enable the peripheral clock in the PMC. */\r
+ pmc_enable_periph_clk( serPMC_USART_ID );\r
+\r
+ /* Configure USART in serial mode. */\r
+ usart_init_rs232( serUSART_PORT, &xUSARTSettings, sysclk_get_cpu_hz() );\r
+\r
+ /* Disable all the interrupts. */\r
+ usart_disable_interrupt( serUSART_PORT, serMASK_ALL_INTERRUPTS );\r
+\r
+ /* Enable the receiver and transmitter. */\r
+ usart_enable_tx( serUSART_PORT );\r
+ usart_enable_rx( serUSART_PORT );\r
+\r
+ /* Clear any characters before enabling interrupt. */\r
+ usart_getchar( serUSART_PORT, &ulChar );\r
+\r
+ /* Enable Rx end interrupt. */\r
+ usart_enable_interrupt( serUSART_PORT, US_IER_RXRDY );\r
+\r
+ /* Configure and enable interrupt of USART. */\r
+ NVIC_SetPriority( serUSART_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+ NVIC_EnableIRQ( serUSART_IRQ );\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ /* This demo file only supports a single port but we have to return\r
+ something to comply with the standard demo header file. */\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )\r
+{\r
+signed char *pxNext;\r
+\r
+ /* A couple of parameters that this port does not use. */\r
+ ( void ) usStringLength;\r
+ ( void ) pxPort;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports USART1. */\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed char * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* This simple example only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )\r
+ {\r
+ xReturn = pdPASS;\r
+ usart_enable_interrupt( serUSART_PORT, US_IER_TXRDY );\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+ ( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * It should be noted that the com test tasks (which use make use of this file)\r
+ * are included to demonstrate queues being used to communicate between tasks\r
+ * and interrupts, and to demonstrate a context switch being performed from\r
+ * inside an interrupt service routine. The serial driver used here is *not*\r
+ * intended to represent an efficient implementation. Real applications should\r
+ * make use of the USARTS peripheral DMA channel (PDC).\r
+ */\r
+void USART1_Handler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+uint8_t ucChar;\r
+uint32_t ulChar;\r
+uint32_t ulUSARTStatus, ulUSARTMask;\r
+\r
+ ulUSARTStatus = usart_get_status( serUSART_PORT );\r
+ ulUSARTMask = usart_get_interrupt_mask( serUSART_PORT );\r
+ ulUSARTStatus &= ulUSARTMask;\r
+\r
+ if( ( ulUSARTStatus & US_CSR_TXRDY ) != 0UL )\r
+ {\r
+ /* The interrupt was caused by the TX register becoming empty. Are\r
+ there any more characters to transmit? */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &ucChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
+ {\r
+ /* A character was retrieved from the queue so can be sent to the\r
+ USART now. */\r
+ usart_putchar( serUSART_PORT, ( uint32_t ) ucChar );\r
+ }\r
+ else\r
+ {\r
+ usart_disable_interrupt( serUSART_PORT, US_IER_TXRDY );\r
+ }\r
+ }\r
+\r
+ if( ( ulUSARTStatus & US_CSR_RXRDY ) != 0UL )\r
+ {\r
+ /* A character has been received on the USART, send it to the Rx\r
+ handler task. */\r
+ usart_getchar( serUSART_PORT, &ulChar );\r
+ ucChar = ( uint8_t ) ( ulChar & 0xffUL );\r
+ xQueueSendFromISR( xRxedChars, &ucChar, &xHigherPriorityTaskWoken );\r
+ }\r
+\r
+ /* If sending or receiving from a queue has caused a task to unblock, and\r
+ the unblocked task has a priority equal to or higher than the currently\r
+ running task (the task this ISR interrupted), then xHigherPriorityTaskWoken\r
+ will have automatically been set to pdTRUE within the queue send or receive\r
+ function. portEND_SWITCHING_ISR() will then ensure that this ISR returns\r
+ directly to the higher priority unblocked task. */\r
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
projects / freertos / commitdiff