4 * Copyright (c) 2012 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 #ifndef _SAM3S8_PDC_COMPONENT_
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43 #define _SAM3S8_PDC_COMPONENT_
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45 /* ============================================================================= */
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46 /** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
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47 /* ============================================================================= */
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48 /** \addtogroup SAM3S8_PDC Peripheral DMA Controller */
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51 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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52 /** \brief Pdc hardware registers */
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54 RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
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55 RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
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56 RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
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57 RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
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58 RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
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59 RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
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60 RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
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61 RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
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62 WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
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63 RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
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65 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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66 /* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
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67 #define PERIPH_RPR_RXPTR_Pos 0
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68 #define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
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69 #define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
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70 /* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
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71 #define PERIPH_RCR_RXCTR_Pos 0
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72 #define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
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73 #define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
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74 /* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
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75 #define PERIPH_TPR_TXPTR_Pos 0
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76 #define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
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77 #define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
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78 /* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
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79 #define PERIPH_TCR_TXCTR_Pos 0
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80 #define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
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81 #define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
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82 /* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
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83 #define PERIPH_RNPR_RXNPTR_Pos 0
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84 #define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
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85 #define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
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86 /* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
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87 #define PERIPH_RNCR_RXNCTR_Pos 0
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88 #define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
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89 #define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
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90 /* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
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91 #define PERIPH_TNPR_TXNPTR_Pos 0
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92 #define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
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93 #define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
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94 /* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
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95 #define PERIPH_TNCR_TXNCTR_Pos 0
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96 #define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
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97 #define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
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98 /* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
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99 #define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
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100 #define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
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101 #define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
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102 #define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
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103 /* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
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104 #define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
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105 #define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
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110 #endif /* _SAM3S8_PDC_COMPONENT_ */
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