4 * Copyright (c) 2012 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 #ifndef _SAM3S8_DACC_INSTANCE_
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43 #define _SAM3S8_DACC_INSTANCE_
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45 /* ========== Register definition for DACC peripheral ========== */
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46 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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47 #define REG_DACC_CR (0x4003C000U) /**< \brief (DACC) Control Register */
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48 #define REG_DACC_MR (0x4003C004U) /**< \brief (DACC) Mode Register */
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49 #define REG_DACC_CHER (0x4003C010U) /**< \brief (DACC) Channel Enable Register */
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50 #define REG_DACC_CHDR (0x4003C014U) /**< \brief (DACC) Channel Disable Register */
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51 #define REG_DACC_CHSR (0x4003C018U) /**< \brief (DACC) Channel Status Register */
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52 #define REG_DACC_CDR (0x4003C020U) /**< \brief (DACC) Conversion Data Register */
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53 #define REG_DACC_IER (0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
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54 #define REG_DACC_IDR (0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
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55 #define REG_DACC_IMR (0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
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56 #define REG_DACC_ISR (0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
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57 #define REG_DACC_ACR (0x4003C094U) /**< \brief (DACC) Analog Current Register */
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58 #define REG_DACC_WPMR (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
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59 #define REG_DACC_WPSR (0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
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60 #define REG_DACC_TPR (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
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61 #define REG_DACC_TCR (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
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62 #define REG_DACC_TNPR (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
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63 #define REG_DACC_TNCR (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
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64 #define REG_DACC_PTCR (0x4003C120U) /**< \brief (DACC) Transfer Control Register */
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65 #define REG_DACC_PTSR (0x4003C124U) /**< \brief (DACC) Transfer Status Register */
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67 #define REG_DACC_CR (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */
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68 #define REG_DACC_MR (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */
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69 #define REG_DACC_CHER (*(WoReg*)0x4003C010U) /**< \brief (DACC) Channel Enable Register */
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70 #define REG_DACC_CHDR (*(WoReg*)0x4003C014U) /**< \brief (DACC) Channel Disable Register */
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71 #define REG_DACC_CHSR (*(RoReg*)0x4003C018U) /**< \brief (DACC) Channel Status Register */
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72 #define REG_DACC_CDR (*(WoReg*)0x4003C020U) /**< \brief (DACC) Conversion Data Register */
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73 #define REG_DACC_IER (*(WoReg*)0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
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74 #define REG_DACC_IDR (*(WoReg*)0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
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75 #define REG_DACC_IMR (*(RoReg*)0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
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76 #define REG_DACC_ISR (*(RoReg*)0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
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77 #define REG_DACC_ACR (*(RwReg*)0x4003C094U) /**< \brief (DACC) Analog Current Register */
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78 #define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
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79 #define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
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80 #define REG_DACC_TPR (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
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81 #define REG_DACC_TCR (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
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82 #define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
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83 #define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
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84 #define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */
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85 #define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */
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86 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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88 #endif /* _SAM3S8_DACC_INSTANCE_ */
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