2 ;******************************************************************************
\r
3 ;* © 2013 Microchip Technology Inc. and its subsidiaries.
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4 ;* You may use this software and any derivatives exclusively with
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5 ;* Microchip products.
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6 ;* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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7 ;* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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8 ;* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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9 ;* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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10 ;* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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11 ;* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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12 ;* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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13 ;* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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14 ;* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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15 ;* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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16 ;* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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17 ;* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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18 ;* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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20 ;******************************************************************************
\r
22 ;/** @file startup_CEC1302.s
\r
23 ; *CEC1302 API Test: startup and vector table
\r
25 ;/** @defgroup startup_CEC1302
\r
30 IMPORT |Image$$RW_IRAM1$$Base|
\r
31 IMPORT |Image$$RW_IRAM1$$Limit|
\r
32 IMPORT |Image$$RW_IRAM1$$Length|
\r
33 IMPORT |Image$$RW_IRAM1$$ZI$$Base|
\r
34 IMPORT |Image$$RW_IRAM1$$ZI$$Limit|
\r
35 IMPORT |Image$$ER_IROM1$$Base|
\r
36 IMPORT |Image$$ER_IROM1$$Limit|
\r
38 IMPORT system_set_ec_clock
\r
40 EXPORT Reset_Handler
\r
42 ; <h> Stack Configuration
\r
43 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
\r
46 Stack_Size EQU 0x00000800
\r
48 AREA STACK, NOINIT, READWRITE, ALIGN=3
\r
49 EXPORT __stack_bottom
\r
51 Stack_Mem SPACE Stack_Size
\r
54 ; <h> Heap Configuration
\r
55 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
\r
58 Heap_Size EQU 0x00000000
\r
60 AREA HEAP, NOINIT, READWRITE, ALIGN=3
\r
62 Heap_Mem SPACE Heap_Size
\r
68 ; Vector Table Mapped to Address 0 at Reset
\r
70 AREA RESET, DATA, READONLY
\r
74 __Vectors DCD __initial_sp ; Top of Stack
\r
75 DCD Reset_Handler ; Reset Handler
\r
76 DCD NMI_Handler ; NMI Handler
\r
77 DCD HardFault_Handler ; Hard Fault Handler
\r
78 DCD MemManage_Handler ; MPU Fault Handler
\r
79 DCD BusFault_Handler ; Bus Fault Handler
\r
80 DCD UsageFault_Handler ; Usage Fault Handler
\r
85 DCD SVC_Handler ; SVCall Handler
\r
86 DCD DebugMon_Handler ; Debug Monitor Handler
\r
88 DCD PendSV_Handler ; PendSV Handler
\r
89 DCD SysTick_Handler ; SysTick Handler
\r
91 ; CEC1302 External Interrupts
\r
92 DCD NVIC_Handler_I2C0 ; 40h: 0, I2C/SMBus 0
\r
93 DCD NVIC_Handler_I2C1 ; 44h: 1, I2C/SMBus 1
\r
94 DCD NVIC_Handler_I2C2 ; 48h: 2, I2C/SMBus 2
\r
95 DCD NVIC_Handler_I2C3 ; 4Ch: 3, I2C/SMBus 3
\r
96 DCD NVIC_Handler_DMA0 ; 50h: 4, DMA Channel 0
\r
97 DCD NVIC_Handler_DMA1 ; 54h: 5, DMA Channel 1
\r
98 DCD NVIC_Handler_DMA2 ; 58h: 6, DMA Channel 2
\r
99 DCD NVIC_Handler_DMA3 ; 5Ch: 7, DMA Channel 3
\r
100 DCD NVIC_Handler_DMA4 ; 60h: 8, DMA Channel 4
\r
101 DCD NVIC_Handler_DMA5 ; 64h: 9, DMA Channel 5
\r
102 DCD NVIC_Handler_DMA6 ; 68h: 10, DMA Channel 6
\r
103 DCD NVIC_Handler_DMA7 ; 6Ch: 11, DMA Channel 7
\r
104 DCD NVIC_Handler_LPCBERR ; 70h: 12, LPC Bus Error
\r
105 DCD NVIC_Handler_UART0 ; 74h: 13, UART0
\r
106 DCD NVIC_Handler_IMAP0 ; 78h: 14, IMAP0
\r
107 DCD NVIC_Handler_EC0_IBF ; 7Ch: 15, ACPI_EC0_IBF
\r
108 DCD NVIC_Handler_EC0_OBF ; 80h: 16, ACPI_EC0_OBF
\r
109 DCD NVIC_Handler_EC1_IBF ; 84h: 17, ACPI_EC1_IBF
\r
110 DCD NVIC_Handler_EC1_OBF ; 88h: 18, ACPI_EC1_OBF
\r
111 DCD NVIC_Handler_PM1_CTL ; 8Ch: 19, ACPI_PM1_CTL
\r
112 DCD NVIC_Handler_PM1_EN ; 90h: 20, ACPI_PM1_EN
\r
113 DCD NVIC_Handler_PM1_STS ; 94h: 21, ACPI_PM1_STS
\r
114 DCD NVIC_Handler_MIF8042_OBF ; 98h: 22, MIF8042_OBF
\r
115 DCD NVIC_Handler_MIF8042_IBF ; 9Ch: 23, MIF8042_IBF
\r
116 DCD NVIC_Handler_MAILBOX ; A0h: 24, Mailbox
\r
117 DCD NVIC_Handler_PECI ; A4h: 25, PECI
\r
118 DCD NVIC_Handler_TACH0 ; A8h: 26, TACH0
\r
119 DCD NVIC_Handler_TACH1 ; ACh: 27, TACH1
\r
120 DCD NVIC_Handler_ADC_SNGL ; B0h: 28, ADC_SNGL
\r
121 DCD NVIC_Handler_ADC_RPT ; B4h: 29, ADC_RPT
\r
122 DCD NVIC_Handler_V2P_INT0 ; B8h: 30, V2P_INT0
\r
123 DCD NVIC_Handler_V2P_INT1 ; BCh: 31, V2P_INT1
\r
124 DCD NVIC_Handler_PS2_CH0 ; C0h: 32, PS2_0
\r
125 DCD NVIC_Handler_PS2_CH1 ; C4h: 33, PS2_1
\r
126 DCD NVIC_Handler_PS2_CH2 ; C8h: 34, PS2_2
\r
127 DCD NVIC_Handler_PS2_CH3 ; CCh: 35, PS2_3
\r
128 DCD NVIC_Handler_SPI0_TX ; D0h: 36, SPI0_TX
\r
129 DCD NVIC_Handler_SPI0_RX ; D4h: 37, SPI0_RX
\r
130 DCD NVIC_Handler_HIB_TMR ; D8h: 38, HIB_TMR
\r
131 DCD NVIC_Handler_KEY_INT ; DCh: 39, KEY_INT
\r
132 DCD NVIC_Handler_KEY_WAKE ; E0h: 40, KEY_WAKE
\r
133 DCD NVIC_Handler_RPM_STALL ; E4h: 41, RPM_STALL
\r
134 DCD NVIC_Handler_RPM_SPIN ; E8h: 42, RPM_SPIN
\r
135 DCD NVIC_Handler_VBAT ; ECh: 43, VBAT
\r
136 DCD NVIC_Handler_LED0 ; F0h: 44, LED0
\r
137 DCD NVIC_Handler_LED1 ; F4h: 45, LED1
\r
138 DCD NVIC_Handler_LED2 ; F8h: 46, LED2
\r
139 DCD NVIC_Handler_MBC_ERR ; FCh: 47, MBC_ERR
\r
140 DCD NVIC_Handler_MBC_BUSY ; 100h: 48, MBC_BUSY
\r
141 DCD NVIC_Handler_TMR0 ; 104h: 49, TMR0
\r
142 DCD NVIC_Handler_TMR1 ; 108h: 50, TMR1
\r
143 DCD NVIC_Handler_TMR2 ; 10Ch: 51, TMR2
\r
144 DCD NVIC_Handler_TMR3 ; 110h: 52, TMR3
\r
145 DCD NVIC_Handler_TMR4 ; 114h: 53, TMR4
\r
146 DCD NVIC_Handler_TMR5 ; 118h: 54, TMR5
\r
147 DCD NVIC_Handler_SPI1_TX ; 11Ch: 55, SPI1_TX
\r
148 DCD NVIC_Handler_SPI1_RX ; 120h: 56, SPI1_RX
\r
149 DCD NVIC_Handler_GIRQ08 ; 124h: 57, GIRQ08
\r
150 DCD NVIC_Handler_GIRQ09 ; 128h: 58, GIRQ09
\r
151 DCD NVIC_Handler_GIRQ10 ; 12Ch: 59, GIRQ10
\r
152 DCD NVIC_Handler_GIRQ11 ; 130h: 60, GIRQ11
\r
153 DCD NVIC_Handler_GIRQ12 ; 134h: 61, GIRQ12
\r
154 DCD NVIC_Handler_GIRQ13 ; 138h: 62, GIRQ13
\r
155 DCD NVIC_Handler_GIRQ14 ; 13Ch: 63, GIRQ14
\r
156 DCD NVIC_Handler_GIRQ15 ; 140h: 64, GIRQ15
\r
157 DCD NVIC_Handler_GIRQ16 ; 144h: 65, GIRQ16
\r
158 DCD NVIC_Handler_GIRQ17 ; 148h: 66, GIRQ17
\r
159 DCD NVIC_Handler_GIRQ18 ; 14Ch: 67, GIRQ18
\r
160 DCD NVIC_Handler_GIRQ19 ; 150h: 68, GIRQ19
\r
161 DCD NVIC_Handler_GIRQ20 ; 154h: 69, GIRQ20
\r
162 DCD NVIC_Handler_GIRQ21 ; 158h: 70, GIRQ21
\r
163 DCD NVIC_Handler_GIRQ22 ; 15Ch: 71, GIRQ22
\r
164 DCD NVIC_Handler_GIRQ23 ; 160h: 72, GIRQ23
\r
165 DCD NVIC_Handler_073 ; 164h: 73, unknown
\r
166 DCD NVIC_Handler_074 ; 168h: 74, unknown
\r
167 DCD NVIC_Handler_075 ; 16Ch: 75, unknown
\r
168 DCD NVIC_Handler_076 ; 170h: 76, unknown
\r
169 DCD NVIC_Handler_077 ; 174h: 77, unknown
\r
170 DCD NVIC_Handler_078 ; 178h: 78, unknown
\r
171 DCD NVIC_Handler_079 ; 17Ch: 79, unknown
\r
172 DCD NVIC_Handler_080 ; 180h: 80, unknown
\r
173 DCD NVIC_Handler_DMA8 ; 184h: 81, DMA CH8
\r
174 DCD NVIC_Handler_DMA9 ; 188h: 82, DMA CH9
\r
175 DCD NVIC_Handler_DMA10 ; 18Ch: 83, DMA CH10
\r
176 DCD NVIC_Handler_DMA11 ; 190h: 84, DMA CH11
\r
177 DCD NVIC_Handler_LED3 ; 194h: 85, LED3
\r
178 DCD NVIC_Handler_PKE_ERR ; 198h: 86, PKE Error
\r
179 DCD NVIC_Handler_PKE_END ; 19Ch: 87, PKE End
\r
180 DCD NVIC_Handler_TRNG ; 1A0h: 88, TRandom Num Gen
\r
181 DCD NVIC_Handler_AES ; 1A4h: 89, AES
\r
182 DCD NVIC_Handler_HASH ; 1A8h: 90, HASH
\r
185 AREA ROMTABLE, CODE, READONLY
\r
187 ; ---------- ROM API ----------
\r
188 ; Jump table to ROM API C functions
\r
191 ; ---------- ROM API End ------
\r
194 AREA |.text|, CODE, READONLY
\r
198 EXPORT Reset_Handler [WEAK]
\r
202 ; support code is loaded from ROM loader
\r
203 LDR SP, =__initial_sp
\r
204 ; configure CPU speed
\r
205 LDR R0, =system_set_ec_clock
\r
208 LDR SP, =__initial_sp
\r
211 IF {CPU} = "Cortex-M4.fp"
\r
212 LDR R0, =0xE000ED88 ; Enable CP10,CP11
\r
214 ORR R1,R1,#(0xF << 20)
\r
218 ; Enter Keil startup code which calls our main
\r
223 ; Dummy Exception Handlers (infinite loops which can be modified)
\r
226 EXPORT NMI_Handler [WEAK]
\r
232 EXPORT HardFault_Handler [WEAK]
\r
238 EXPORT MemManage_Handler [WEAK]
\r
244 EXPORT BusFault_Handler [WEAK]
\r
248 UsageFault_Handler\
\r
250 EXPORT UsageFault_Handler [WEAK]
\r
255 EXPORT SVC_Handler [WEAK]
\r
261 EXPORT DebugMon_Handler [WEAK]
\r
265 PendSV_Handler PROC
\r
266 EXPORT PendSV_Handler [WEAK]
\r
270 SysTick_Handler PROC
\r
271 EXPORT SysTick_Handler [WEAK]
\r
276 Default_Handler PROC
\r
278 ; External CEC1302 NVIC Interrupt Inputs
\r
279 EXPORT NVIC_Handler_I2C0 [WEAK]
\r
280 EXPORT NVIC_Handler_I2C1 [WEAK]
\r
281 EXPORT NVIC_Handler_I2C2 [WEAK]
\r
282 EXPORT NVIC_Handler_I2C3 [WEAK]
\r
283 EXPORT NVIC_Handler_DMA0 [WEAK]
\r
284 EXPORT NVIC_Handler_DMA1 [WEAK]
\r
285 EXPORT NVIC_Handler_DMA2 [WEAK]
\r
286 EXPORT NVIC_Handler_DMA3 [WEAK]
\r
287 EXPORT NVIC_Handler_DMA4 [WEAK]
\r
288 EXPORT NVIC_Handler_DMA5 [WEAK]
\r
289 EXPORT NVIC_Handler_DMA6 [WEAK]
\r
290 EXPORT NVIC_Handler_DMA7 [WEAK]
\r
291 EXPORT NVIC_Handler_LPCBERR [WEAK]
\r
292 EXPORT NVIC_Handler_UART0 [WEAK]
\r
293 EXPORT NVIC_Handler_IMAP0 [WEAK]
\r
294 EXPORT NVIC_Handler_EC0_IBF [WEAK]
\r
295 EXPORT NVIC_Handler_EC0_OBF [WEAK]
\r
296 EXPORT NVIC_Handler_EC1_IBF [WEAK]
\r
297 EXPORT NVIC_Handler_EC1_OBF [WEAK]
\r
298 EXPORT NVIC_Handler_PM1_CTL [WEAK]
\r
299 EXPORT NVIC_Handler_PM1_EN [WEAK]
\r
300 EXPORT NVIC_Handler_PM1_STS [WEAK]
\r
301 EXPORT NVIC_Handler_MIF8042_OBF [WEAK]
\r
302 EXPORT NVIC_Handler_MIF8042_IBF [WEAK]
\r
303 EXPORT NVIC_Handler_MAILBOX [WEAK]
\r
304 EXPORT NVIC_Handler_PECI [WEAK]
\r
305 EXPORT NVIC_Handler_TACH0 [WEAK]
\r
306 EXPORT NVIC_Handler_TACH1 [WEAK]
\r
307 EXPORT NVIC_Handler_ADC_SNGL [WEAK]
\r
308 EXPORT NVIC_Handler_ADC_RPT [WEAK]
\r
309 EXPORT NVIC_Handler_V2P_INT0 [WEAK]
\r
310 EXPORT NVIC_Handler_V2P_INT1 [WEAK]
\r
311 EXPORT NVIC_Handler_PS2_CH0 [WEAK]
\r
312 EXPORT NVIC_Handler_PS2_CH1 [WEAK]
\r
313 EXPORT NVIC_Handler_PS2_CH2 [WEAK]
\r
314 EXPORT NVIC_Handler_PS2_CH3 [WEAK]
\r
315 EXPORT NVIC_Handler_SPI0_TX [WEAK]
\r
316 EXPORT NVIC_Handler_SPI0_RX [WEAK]
\r
317 EXPORT NVIC_Handler_HIB_TMR [WEAK]
\r
318 EXPORT NVIC_Handler_KEY_INT [WEAK]
\r
319 EXPORT NVIC_Handler_KEY_WAKE [WEAK]
\r
320 EXPORT NVIC_Handler_RPM_STALL [WEAK]
\r
321 EXPORT NVIC_Handler_RPM_SPIN [WEAK]
\r
322 EXPORT NVIC_Handler_VBAT [WEAK]
\r
323 EXPORT NVIC_Handler_LED0 [WEAK]
\r
324 EXPORT NVIC_Handler_LED1 [WEAK]
\r
325 EXPORT NVIC_Handler_LED2 [WEAK]
\r
326 EXPORT NVIC_Handler_MBC_ERR [WEAK]
\r
327 EXPORT NVIC_Handler_MBC_BUSY [WEAK]
\r
328 EXPORT NVIC_Handler_TMR0 [WEAK]
\r
329 EXPORT NVIC_Handler_TMR1 [WEAK]
\r
330 EXPORT NVIC_Handler_TMR2 [WEAK]
\r
331 EXPORT NVIC_Handler_TMR3 [WEAK]
\r
332 EXPORT NVIC_Handler_TMR4 [WEAK]
\r
333 EXPORT NVIC_Handler_TMR5 [WEAK]
\r
334 EXPORT NVIC_Handler_SPI1_TX [WEAK]
\r
335 EXPORT NVIC_Handler_SPI1_RX [WEAK]
\r
336 EXPORT NVIC_Handler_GIRQ08 [WEAK]
\r
337 EXPORT NVIC_Handler_GIRQ09 [WEAK]
\r
338 EXPORT NVIC_Handler_GIRQ10 [WEAK]
\r
339 EXPORT NVIC_Handler_GIRQ11 [WEAK]
\r
340 EXPORT NVIC_Handler_GIRQ12 [WEAK]
\r
341 EXPORT NVIC_Handler_GIRQ13 [WEAK]
\r
342 EXPORT NVIC_Handler_GIRQ14 [WEAK]
\r
343 EXPORT NVIC_Handler_GIRQ15 [WEAK]
\r
344 EXPORT NVIC_Handler_GIRQ16 [WEAK]
\r
345 EXPORT NVIC_Handler_GIRQ17 [WEAK]
\r
346 EXPORT NVIC_Handler_GIRQ18 [WEAK]
\r
347 EXPORT NVIC_Handler_GIRQ19 [WEAK]
\r
348 EXPORT NVIC_Handler_GIRQ20 [WEAK]
\r
349 EXPORT NVIC_Handler_GIRQ21 [WEAK]
\r
350 EXPORT NVIC_Handler_GIRQ22 [WEAK]
\r
351 EXPORT NVIC_Handler_GIRQ23 [WEAK]
\r
352 EXPORT NVIC_Handler_073 [WEAK]
\r
353 EXPORT NVIC_Handler_074 [WEAK]
\r
354 EXPORT NVIC_Handler_075 [WEAK]
\r
355 EXPORT NVIC_Handler_076 [WEAK]
\r
356 EXPORT NVIC_Handler_077 [WEAK]
\r
357 EXPORT NVIC_Handler_078 [WEAK]
\r
358 EXPORT NVIC_Handler_079 [WEAK]
\r
359 EXPORT NVIC_Handler_080 [WEAK]
\r
360 EXPORT NVIC_Handler_DMA8 [WEAK]
\r
361 EXPORT NVIC_Handler_DMA9 [WEAK]
\r
362 EXPORT NVIC_Handler_DMA10 [WEAK]
\r
363 EXPORT NVIC_Handler_DMA11 [WEAK]
\r
364 EXPORT NVIC_Handler_LED3 [WEAK]
\r
365 EXPORT NVIC_Handler_PKE_ERR [WEAK]
\r
366 EXPORT NVIC_Handler_PKE_END [WEAK]
\r
367 EXPORT NVIC_Handler_TRNG [WEAK]
\r
368 EXPORT NVIC_Handler_AES [WEAK]
\r
369 EXPORT NVIC_Handler_HASH [WEAK]
\r
383 NVIC_Handler_LPCBERR
\r
386 NVIC_Handler_EC0_IBF
\r
387 NVIC_Handler_EC0_OBF
\r
388 NVIC_Handler_EC1_IBF
\r
389 NVIC_Handler_EC1_OBF
\r
390 NVIC_Handler_PM1_CTL
\r
391 NVIC_Handler_PM1_EN
\r
392 NVIC_Handler_PM1_STS
\r
393 NVIC_Handler_MIF8042_OBF
\r
394 NVIC_Handler_MIF8042_IBF
\r
395 NVIC_Handler_MAILBOX
\r
399 NVIC_Handler_ADC_SNGL
\r
400 NVIC_Handler_ADC_RPT
\r
401 NVIC_Handler_V2P_INT0
\r
402 NVIC_Handler_V2P_INT1
\r
403 NVIC_Handler_PS2_CH0
\r
404 NVIC_Handler_PS2_CH1
\r
405 NVIC_Handler_PS2_CH2
\r
406 NVIC_Handler_PS2_CH3
\r
407 NVIC_Handler_SPI0_TX
\r
408 NVIC_Handler_SPI0_RX
\r
409 NVIC_Handler_HIB_TMR
\r
410 NVIC_Handler_KEY_INT
\r
411 NVIC_Handler_KEY_WAKE
\r
412 NVIC_Handler_RPM_STALL
\r
413 NVIC_Handler_RPM_SPIN
\r
418 NVIC_Handler_MBC_ERR
\r
419 NVIC_Handler_MBC_BUSY
\r
426 NVIC_Handler_SPI1_TX
\r
427 NVIC_Handler_SPI1_RX
\r
428 NVIC_Handler_GIRQ08
\r
429 NVIC_Handler_GIRQ09
\r
430 NVIC_Handler_GIRQ10
\r
431 NVIC_Handler_GIRQ11
\r
432 NVIC_Handler_GIRQ12
\r
433 NVIC_Handler_GIRQ13
\r
434 NVIC_Handler_GIRQ14
\r
435 NVIC_Handler_GIRQ15
\r
436 NVIC_Handler_GIRQ16
\r
437 NVIC_Handler_GIRQ17
\r
438 NVIC_Handler_GIRQ18
\r
439 NVIC_Handler_GIRQ19
\r
440 NVIC_Handler_GIRQ20
\r
441 NVIC_Handler_GIRQ21
\r
442 NVIC_Handler_GIRQ22
\r
443 NVIC_Handler_GIRQ23
\r
457 NVIC_Handler_PKE_ERR
\r
458 NVIC_Handler_PKE_END
\r
468 ; User Initial Stack & Heap
\r
472 EXPORT __initial_sp
\r
474 EXPORT __heap_limit
\r
475 EXPORT __stack_bottom
\r
479 IMPORT __use_two_region_memory
\r
480 EXPORT __user_initial_stackheap
\r
481 __user_initial_stackheap
\r
484 LDR R1, =(Stack_Mem + Stack_Size)
\r
485 LDR R2, = (Heap_Mem + Heap_Size)
\r
486 LDR R3, = Stack_Mem
\r