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<Name>Debug</Name>
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<Doc>
<Name>..\main.c</Name>
- <ColumnNumber>0</ColumnNumber>
- <TopLine>67</TopLine>
- <CurrentLine>142</CurrentLine>
+ <ColumnNumber>47</ColumnNumber>
+ <TopLine>65</TopLine>
+ <CurrentLine>180</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
- <tGomain>1</tGomain>
+ <tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
- <aLwin>0</aLwin>
+ <aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<Group>
<GroupName>main_and_config</GroupName>
- <tvExp>1</tvExp>
+ <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<Group>
<GroupName>main_low_power</GroupName>
- <tvExp>1</tvExp>
+ <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<Group>
<GroupName>main_full</GroupName>
- <tvExp>1</tvExp>
+ <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
/*\r
- * Default linker script for GCC MEC1322\r
+ * Default linker script for GCC CEC1302\r
* Based upon linker scripts from GNU ARM Eclipse plug-in\r
*/\r
\r
INCLUDE mem.ld\r
+__SRAM_segment_end__ = ORIGIN( RAM ) + LENGTH( RAM );\r
\r
/*\r
* The '__stack' definition is required by crt0, do not remove it.\r
* For Cortex-M devices, the beginning of the startup code is stored in\r
* the .isr_vector section, which goes to ROM\r
*/\r
- \r
+\r
.isr_vector :\r
{\r
. = ALIGN(4);\r
KEEP(*(.isr_vector))\r
. = ALIGN(4);\r
} >ROM\r
- \r
- \r
+\r
+\r
.text :\r
{\r
. = ALIGN(4);\r
.syntax unified
.arch armv7e-m
- .section .stack
- .align 3
-
- .equ ulMainStackSize, 200 * 4
- .equ Stack_Size, 0x004
- .globl __StackTop
- .globl __StackLimit
- .extern ulMainStack
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
+ .extern __SRAM_segment_end__
.section .isr_vector,"a",%progbits
+ .align 4
+ .globl __isr_vector
.global __Vectors
- .type __Vectors, %object
- .size __Vectors, .-__Vectors
+
__Vectors:
- .long ulMainStack + ulMainStackSize /* Top of Stack */
+__isr_vector:
+ .long __SRAM_segment_end__ - 4 /* Top of Stack at top of RAM*/
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
*
* All addresses must be aligned to 4 bytes boundary.
*/
- ldr sp, =ulMainStack + ulMainStackSize
- sub sp, sp, #4
-
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
-/* def_irq_handler SVC_Handler */
+ def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
-/* def_irq_handler PendSV_Handler */
-/* def_irq_handler SysTick_Handler */
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
def_irq_handler DEF_IRQHandler
def_irq_handler NVIC_Handler_I2C0
* @{\r
*/\r
/** @file pwm_c_wrapper.cpp\r
- \brief the pwm component C wrapper \r
+ \brief the pwm component C wrapper\r
This program is designed to allow the other C programs to be able to use this component\r
\r
There are entry points for all C wrapper API implementation\r
\r
-<b>Platform:</b> This is ARC-based component \r
+<b>Platform:</b> This is ARC-based component\r
\r
<b>Toolset:</b> Metaware IDE(8.5.1)\r
<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
* AUTHOR: $Author: akrishnan $\r
*\r
* Revision history (latest first):\r
- * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) \r
+ * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1)\r
* #2 2011/03/25 martin_y support FPGA build 058 apps\r
* #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200\r
***********************************************************************************\r
#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))\r
#define CPU_CLOCK_DIVIDER 1\r
\r
-/* The start up code is configured to use the following array as the stack used\r
-by main(), which will then also get used by FreeRTOS interrupt handlers after \r
-the scheduler has been started. */\r
-#warning If the array size is modified here then ulMainStackSize must also be modified in startup_ARMCM4.S.\r
-volatile uint32_t ulMainStack[ 200 ];\r
-\r
/******************************************************************************/\r
/** system_set_ec_clock\r
* Set CPU speed\r
<GroupNumber>5</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
- <tvExp>1</tvExp>
+ <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\main_full\main_full.c</PathWithFileName>
<GroupNumber>6</GroupNumber>
<FileNumber>28</FileNumber>
<FileType>1</FileType>
- <tvExp>0</tvExp>
+ <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\peripheral_library\basic_timer\btimer_api.c</PathWithFileName>
;* OF THESE TERMS.\r
;******************************************************************************\r
; */\r
-;/** @file startup_MEC1322.s\r
-; *MEC1322 API Test: startup and vector table\r
+;/** @file startup_CEC1302.s\r
+; *CEC1302 API Test: startup and vector table\r
; */\r
-;/** @defgroup startup_MEC1322\r
+;/** @defgroup startup_CEC1302\r
; * @{\r
; */\r
\r
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
; </h>\r
\r
-Heap_Size EQU 0x00000000 \r
+Heap_Size EQU 0x00000000\r
\r
AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
__heap_base\r
DCD PendSV_Handler ; PendSV Handler\r
DCD SysTick_Handler ; SysTick Handler\r
\r
- ; MEC1322 External Interrupts\r
+ ; CEC1302 External Interrupts\r
DCD NVIC_Handler_I2C0 ; 40h: 0, I2C/SMBus 0\r
DCD NVIC_Handler_I2C1 ; 44h: 1, I2C/SMBus 1\r
DCD NVIC_Handler_I2C2 ; 48h: 2, I2C/SMBus 2\r
DCD NVIC_Handler_GIRQ11 ; 130h: 60, GIRQ11\r
DCD NVIC_Handler_GIRQ12 ; 134h: 61, GIRQ12\r
DCD NVIC_Handler_GIRQ13 ; 138h: 62, GIRQ13\r
- DCD NVIC_Handler_GIRQ14 ; 13Ch: 63, GIRQ14\r
+ DCD NVIC_Handler_GIRQ14 ; 13Ch: 63, GIRQ14\r
DCD NVIC_Handler_GIRQ15 ; 140h: 64, GIRQ15\r
DCD NVIC_Handler_GIRQ16 ; 144h: 65, GIRQ16\r
DCD NVIC_Handler_GIRQ17 ; 148h: 66, GIRQ17\r
DCD NVIC_Handler_PKE_ERR ; 198h: 86, PKE Error\r
DCD NVIC_Handler_PKE_END ; 19Ch: 87, PKE End\r
DCD NVIC_Handler_TRNG ; 1A0h: 88, TRandom Num Gen\r
- DCD NVIC_Handler_AES ; 1A4h: 89, AES \r
+ DCD NVIC_Handler_AES ; 1A4h: 89, AES\r
DCD NVIC_Handler_HASH ; 1A8h: 90, HASH\r
- \r
+\r
\r
AREA ROMTABLE, CODE, READONLY\r
THUMB\r
EXPORT Reset_Handler [WEAK]\r
\r
CPSID i\r
- \r
- ; support code is loaded from ROM loader\r
- LDR SP, =__initial_sp\r
- ; configure CPU speed \r
+\r
+ ; support code is loaded from ROM loader\r
+ LDR SP, =__initial_sp\r
+ ; configure CPU speed\r
LDR R0, =system_set_ec_clock\r
BLX R0\r
\r
LDR SP, =__initial_sp\r
\r
- ; support FPU\r
+ ; support FPU\r
IF {CPU} = "Cortex-M4.fp"\r
LDR R0, =0xE000ED88 ; Enable CP10,CP11\r
LDR R1,[R0]\r
\r
Default_Handler PROC\r
\r
- ; External MEC1322 NVIC Interrupt Inputs\r
+ ; External CEC1302 NVIC Interrupt Inputs\r
EXPORT NVIC_Handler_I2C0 [WEAK]\r
EXPORT NVIC_Handler_I2C1 [WEAK]\r
EXPORT NVIC_Handler_I2C2 [WEAK]\r
; User Initial Stack & Heap\r
\r
IF :DEF:__MICROLIB\r
- \r
+\r
EXPORT __initial_sp\r
EXPORT __heap_base\r
EXPORT __heap_limit\r
EXPORT __stack_bottom\r
\r
ELSE\r
- \r
+\r
IMPORT __use_two_region_memory\r
EXPORT __user_initial_stackheap\r
__user_initial_stackheap\r
extern void system_set_ec_clock( void );\r
extern unsigned long __Vectors[];\r
\r
- /* Disable M4 write buffer: fix MEC1322 hardware bug. */\r
+ /* Disable M4 write buffer: fix CEC1302 hardware bug. */\r
mainNVIC_AUX_ACTLR |= 0x07;\r
\r
/* Enable alternative NVIC vectors. */\r
#define tmrMEDIUM_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 )\r
#define tmrHIGHER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )\r
\r
-/* Hardware register locations. */\r
-#define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )\r
+/* Hardware register locations and bit definitions to enable the btimer \r
+interrupts. */\r
+#define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )\r
+#define tmrGIRQ23_BIT_TIMER0 ( 1UL << 0UL )\r
+#define tmrGIRQ23_BIT_TIMER1 ( 1UL << 1UL )\r
+#define tmrGIRQ23_BIT_TIMER2 ( 1UL << 2UL )\r
+#define tmrGIRQ23_TIMER_BITS ( tmrGIRQ23_BIT_TIMER0 | tmrGIRQ23_BIT_TIMER1 | tmrGIRQ23_BIT_TIMER2 )\r
\r
#define tmrRECORD_NESTING_DEPTH() \\r
ulNestingDepth++; \\r
const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY;\r
const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;\r
\r
- tmrGIRQ23_ENABLE_SET = 0x03;\r
+ tmrGIRQ23_ENABLE_SET = tmrGIRQ23_TIMER_BITS;\r
\r
/* Initialise the three timers as described at the top of this file, and\r
enable their interrupts in the NVIC. */\r
btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 );\r
- enable_timer0_irq();\r
NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY ); //0xc0 into 0xe000e431\r
NVIC_ClearPendingIRQ( TIMER0_IRQn );\r
NVIC_EnableIRQ( TIMER0_IRQn );\r
\r
btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count );\r
btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 );\r
- enable_timer1_irq();\r
NVIC_SetPriority( TIMER1_IRQn, tmrMEDIUM_PRIORITY ); //0xa0 into 0xe000e432\r
NVIC_ClearPendingIRQ( TIMER1_IRQn );\r
NVIC_EnableIRQ( TIMER1_IRQn );\r
\r
btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count );\r
btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 );\r
- enable_timer2_irq();\r
NVIC_SetPriority( TIMER2_IRQn, tmrHIGHER_PRIORITY );\r
NVIC_ClearPendingIRQ( TIMER2_IRQn );\r
NVIC_EnableIRQ( TIMER2_IRQn );\r
\r
/* Library includes. */\r
#include "common_lib.h"\r
+#include "peripheral_library/interrupt/interrupt.h"\r
+#include "peripheral_library/basic_timer/btimer.h"\r
\r
/* This file contains functions that will override the default implementations\r
in the RTOS port layer. Therefore only build this file if the low power demo\r
#if( lpINCLUDE_TEST_TIMER == 1 )\r
\r
#define lpGIRQ23_ENABLE_SET ( * ( uint32_t * ) 0x4000C130 )\r
+ #define tmrGIRQ23_BIT_TIMER0 ( 1UL << 0UL )\r
\r
static void prvSetupBasicTimer( void )\r
{\r
const uint8_t ucTimerChannel = 0;\r
const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / 10;\r
\r
- lpGIRQ23_ENABLE_SET = 0x03;\r
+ lpGIRQ23_ENABLE_SET = tmrGIRQ23_BIT_TIMER0;\r
\r
/* To fully test the low power tick processing it is necessary to sometimes\r
bring the MCU out of its sleep state by a method other than the tick\r
purpose. */\r
btimer_init( ucTimerChannel, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
btimer_interrupt_status_get_clr( ucTimerChannel );\r
- enable_timer0_irq();\r
NVIC_SetPriority( TIMER0_IRQn, ucTimerChannel );\r
NVIC_ClearPendingIRQ( TIMER0_IRQn );\r
NVIC_EnableIRQ( TIMER0_IRQn );\r
-/*\r
- **********************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
- **********************************************************************************\r
- * ARM_REG.h\r
- * This is the header to define Cortex-M3 system control & status registers\r
- **********************************************************************************\r
- * SMSC version control information (Perforce):\r
- *\r
- * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/ARM_REG.h $\r
- * REVISION: $Revision: #1 $\r
- * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
- * AUTHOR: $Author: akrishnan $\r
- *\r
- * Revision history (latest first):\r
- * #xx\r
- ***********************************************************************************\r
- */\r
-\r
-/******************************************************************************/\r
-/** @defgroup ARM_REG ARM_REG\r
- * @{\r
- */\r
-\r
-/** @file ARM_REG.h\r
-* \brief ARM Cortex-M3 registers header file\r
-* \author KBCEC Team\r
-* \r
-* This file contains ARM Cortex-M3 system control & status registers.\r
-******************************************************************************/ \r
-#ifndef ARM_REG_H_\r
-#define ARM_REG_H_\r
-\r
-#define REG8(x) (*((volatile unsigned char *)(x)))\r
-#define REG16(x) (*((volatile unsigned short *)(x)))\r
-#define REG32(x) (*((volatile unsigned long *)(x)))\r
-\r
-/* NVIC Registers */\r
-#define NVIC_INT_TYPE REG32(0xE000E004)\r
-#define NVIC_AUX_ACTLR REG32(0xE000E008)\r
- #define WR_BUF_DISABLE (1 << 1)\r
-#define NVIC_ST_CTRL REG32(0xE000E010)\r
- #define ST_ENABLE (1 << 0)\r
- #define ST_TICKINT (1 << 1)\r
- #define ST_CLKSOURCE (1 << 2)\r
- #define ST_COUNTFLAG (1 << 3)\r
-#define NVIC_ST_RELOAD REG32(0xE000E014)\r
-#define NVIC_ST_CURRENT REG32(0xE000E018)\r
-#define NVIC_ST_CALIB REG32(0xE000E01C)\r
-#define NVIC_ENABLE0 REG32(0xE000E100)\r
-#define NVIC_ENABLE1 REG32(0xE000E104)\r
-#define NVIC_ENABLE2 REG32(0xE000E108)\r
-#define NVIC_ENABLE3 REG32(0xE000E10C)\r
-#define NVIC_ENABLE4 REG32(0xE000E110)\r
-#define NVIC_ENABLE5 REG32(0xE000E114)\r
-#define NVIC_ENABLE6 REG32(0xE000E118)\r
-#define NVIC_ENABLE7 REG32(0xE000E11C)\r
-#define NVIC_DISABLE0 REG32(0xE000E180)\r
-#define NVIC_DISABLE1 REG32(0xE000E184)\r
-#define NVIC_DISABLE2 REG32(0xE000E188)\r
-#define NVIC_DISABLE3 REG32(0xE000E18C)\r
-#define NVIC_DISABLE4 REG32(0xE000E190)\r
-#define NVIC_DISABLE5 REG32(0xE000E194)\r
-#define NVIC_DISABLE6 REG32(0xE000E198)\r
-#define NVIC_DISABLE7 REG32(0xE000E19C)\r
-#define NVIC_PEND0 REG32(0xE000E200)\r
-#define NVIC_PEND1 REG32(0xE000E204)\r
-#define NVIC_PEND2 REG32(0xE000E208)\r
-#define NVIC_PEND3 REG32(0xE000E20C)\r
-#define NVIC_PEND4 REG32(0xE000E210)\r
-#define NVIC_PEND5 REG32(0xE000E214)\r
-#define NVIC_PEND6 REG32(0xE000E218)\r
-#define NVIC_PEND7 REG32(0xE000E21C)\r
-#define NVIC_UNPEND0 REG32(0xE000E280)\r
-#define NVIC_UNPEND1 REG32(0xE000E284)\r
-#define NVIC_UNPEND2 REG32(0xE000E288)\r
-#define NVIC_UNPEND3 REG32(0xE000E28C)\r
-#define NVIC_UNPEND4 REG32(0xE000E290)\r
-#define NVIC_UNPEND5 REG32(0xE000E294)\r
-#define NVIC_UNPEND6 REG32(0xE000E298)\r
-#define NVIC_UNPEND7 REG32(0xE000E29C)\r
-#define NVIC_ACTIVE0 REG32(0xE000E300)\r
-#define NVIC_ACTIVE1 REG32(0xE000E304)\r
-#define NVIC_ACTIVE2 REG32(0xE000E308)\r
-#define NVIC_ACTIVE3 REG32(0xE000E30C)\r
-#define NVIC_ACTIVE4 REG32(0xE000E310)\r
-#define NVIC_ACTIVE5 REG32(0xE000E314)\r
-#define NVIC_ACTIVE6 REG32(0xE000E318)\r
-#define NVIC_ACTIVE7 REG32(0xE000E31C)\r
-#define NVIC_PRI0 REG32(0xE000E400)\r
-#define NVIC_PRI1 REG32(0xE000E404)\r
-#define NVIC_PRI2 REG32(0xE000E408)\r
-#define NVIC_PRI3 REG32(0xE000E40C)\r
-#define NVIC_PRI4 REG32(0xE000E410)\r
-#define NVIC_PRI5 REG32(0xE000E414)\r
-#define NVIC_PRI6 REG32(0xE000E418)\r
-#define NVIC_PRI7 REG32(0xE000E41C)\r
-#define NVIC_PRI8 REG32(0xE000E420)\r
-#define NVIC_PRI9 REG32(0xE000E424)\r
-#define NVIC_PRI10 REG32(0xE000E428)\r
-#define NVIC_PRI11 REG32(0xE000E42C)\r
-#define NVIC_PRI12 REG32(0xE000E430)\r
-#define NVIC_PRI13 REG32(0xE000E434)\r
-#define NVIC_PRI14 REG32(0xE000E438)\r
-#define NVIC_PRI15 REG32(0xE000E43C)\r
-#define NVIC_PRI16 REG32(0xE000E440)\r
-#define NVIC_PRI17 REG32(0xE000E444)\r
-#define NVIC_PRI18 REG32(0xE000E448)\r
-#define NVIC_PRI19 REG32(0xE000E44C)\r
-#define NVIC_PRI20 REG32(0xE000E450)\r
-#define NVIC_PRI21 REG32(0xE000E454)\r
-#define NVIC_PRI22 REG32(0xE000E458)\r
-#define NVIC_PRI23 REG32(0xE000E45C)\r
-#define NVIC_PRI24 REG32(0xE000E460)\r
-#define NVIC_PRI25 REG32(0xE000E464)\r
-#define NVIC_PRI26 REG32(0xE000E468)\r
-#define NVIC_PRI27 REG32(0xE000E46C)\r
-#define NVIC_PRI28 REG32(0xE000E470)\r
-#define NVIC_PRI29 REG32(0xE000E474)\r
-#define NVIC_PRI30 REG32(0xE000E478)\r
-#define NVIC_PRI31 REG32(0xE000E47C)\r
-#define NVIC_PRI32 REG32(0xE000E480)\r
-#define NVIC_PRI33 REG32(0xE000E484)\r
-#define NVIC_PRI34 REG32(0xE000E488)\r
-#define NVIC_PRI35 REG32(0xE000E48C)\r
-#define NVIC_PRI36 REG32(0xE000E490)\r
-#define NVIC_PRI37 REG32(0xE000E494)\r
-#define NVIC_PRI38 REG32(0xE000E498)\r
-#define NVIC_PRI39 REG32(0xE000E49C)\r
-#define NVIC_PRI40 REG32(0xE000E4A0)\r
-#define NVIC_PRI41 REG32(0xE000E4A4)\r
-#define NVIC_PRI42 REG32(0xE000E4A8)\r
-#define NVIC_PRI43 REG32(0xE000E4AC)\r
-#define NVIC_PRI44 REG32(0xE000E4B0)\r
-#define NVIC_PRI45 REG32(0xE000E4B4)\r
-#define NVIC_PRI46 REG32(0xE000E4B8)\r
-#define NVIC_PRI47 REG32(0xE000E4BC)\r
-#define NVIC_PRI48 REG32(0xE000E4C0)\r
-#define NVIC_PRI49 REG32(0xE000E4C4)\r
-#define NVIC_PRI50 REG32(0xE000E4C8)\r
-#define NVIC_PRI51 REG32(0xE000E4CC)\r
-#define NVIC_PRI52 REG32(0xE000E4D0)\r
-#define NVIC_PRI53 REG32(0xE000E4D4)\r
-#define NVIC_PRI54 REG32(0xE000E4D8)\r
-#define NVIC_PRI55 REG32(0xE000E4DC)\r
-#define NVIC_PRI56 REG32(0xE000E4E0)\r
-#define NVIC_PRI57 REG32(0xE000E4E4)\r
-#define NVIC_PRI58 REG32(0xE000E4E8)\r
-#define NVIC_PRI59 REG32(0xE000E4EC)\r
-#define NVIC_CPUID REG32(0xE000ED00)\r
-#define NVIC_INT_CTRL REG32(0xE000ED04)\r
-#define NVIC_VECT_TABLE REG32(0xE000ED08)\r
-#define NVIC_AP_INT_RST REG32(0xE000ED0C)\r
-#define NVIC_SYS_CTRL REG32(0xE000ED10)\r
-#define NVIC_CFG_CTRL REG32(0xE000ED14)\r
-#define NVIC_SYS_H_PRI1 REG32(0xE000ED18)\r
-#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C)\r
-#define NVIC_SYS_H_PRI3 REG32(0xE000ED20)\r
-#define NVIC_SYS_H_CTRL REG32(0xE000ED24)\r
-#define NVIC_FAULT_STA REG32(0xE000ED28)\r
-#define NVIC_HARD_F_STA REG32(0xE000ED2C)\r
-#define NVIC_DBG_F_STA REG32(0xE000ED30)\r
-#define NVIC_MM_F_ADR REG32(0xE000ED34)\r
-#define NVIC_BUS_F_ADR REG32(0xE000ED38)\r
-#define NVIC_SW_TRIG REG32(0xE000EF00)\r
-\r
-/* MPU Registers */\r
-#define MPU_TYPE REG32(0xE000ED90)\r
-#define MPU_CTRL REG32(0xE000ED94)\r
-#define MPU_RG_NUM REG32(0xE000ED98)\r
-#define MPU_RG_ADDR REG32(0xE000ED9C)\r
-#define MPU_RG_AT_SZ REG32(0xE000EDA0)\r
-\r
-\r
-#endif /* #ifndef ARM_REG_H_ */\r
-\r
-/** @}\r
- */\r
+/*
+ **********************************************************************************
+* © 2013 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+ **********************************************************************************
+ * ARM_REG.h
+ * This is the header to define Cortex-M3 system control & status registers
+ **********************************************************************************
+ * SMSC version control information (Perforce):
+ *
+ * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/ARM_REG.h $
+ * REVISION: $Revision: #1 $
+ * DATETIME: $DateTime: 2016/04/08 10:18:28 $
+ * AUTHOR: $Author: pramans $
+ *
+ * Revision history (latest first):
+ * #xx
+ ***********************************************************************************
+ */
+
+/******************************************************************************/
+/** @defgroup ARM_REG ARM_REG
+ * @{
+ */
+
+/** @file ARM_REG.h
+* \brief ARM Cortex-M3 registers header file
+* \author KBCEC Team
+*
+* This file contains ARM Cortex-M3 system control & status registers.
+******************************************************************************/
+#ifndef ARM_REG_H_
+#define ARM_REG_H_
+
+#define REG8(x) (*((volatile unsigned char *)(x)))
+#define REG16(x) (*((volatile unsigned short *)(x)))
+#define REG32(x) (*((volatile unsigned long *)(x)))
+
+/* NVIC Registers */
+#define NVIC_INT_TYPE REG32(0xE000E004)
+#define NVIC_AUX_ACTLR REG32(0xE000E008)
+ #define WR_BUF_DISABLE (1 << 1)
+#define NVIC_ST_CTRL REG32(0xE000E010)
+ #define ST_ENABLE (1 << 0)
+ #define ST_TICKINT (1 << 1)
+ #define ST_CLKSOURCE (1 << 2)
+ #define ST_COUNTFLAG (1 << 3)
+#define NVIC_ST_RELOAD REG32(0xE000E014)
+#define NVIC_ST_CURRENT REG32(0xE000E018)
+#define NVIC_ST_CALIB REG32(0xE000E01C)
+#define NVIC_ENABLE0 REG32(0xE000E100)
+#define NVIC_ENABLE1 REG32(0xE000E104)
+#define NVIC_ENABLE2 REG32(0xE000E108)
+#define NVIC_ENABLE3 REG32(0xE000E10C)
+#define NVIC_ENABLE4 REG32(0xE000E110)
+#define NVIC_ENABLE5 REG32(0xE000E114)
+#define NVIC_ENABLE6 REG32(0xE000E118)
+#define NVIC_ENABLE7 REG32(0xE000E11C)
+#define NVIC_DISABLE0 REG32(0xE000E180)
+#define NVIC_DISABLE1 REG32(0xE000E184)
+#define NVIC_DISABLE2 REG32(0xE000E188)
+#define NVIC_DISABLE3 REG32(0xE000E18C)
+#define NVIC_DISABLE4 REG32(0xE000E190)
+#define NVIC_DISABLE5 REG32(0xE000E194)
+#define NVIC_DISABLE6 REG32(0xE000E198)
+#define NVIC_DISABLE7 REG32(0xE000E19C)
+#define NVIC_PEND0 REG32(0xE000E200)
+#define NVIC_PEND1 REG32(0xE000E204)
+#define NVIC_PEND2 REG32(0xE000E208)
+#define NVIC_PEND3 REG32(0xE000E20C)
+#define NVIC_PEND4 REG32(0xE000E210)
+#define NVIC_PEND5 REG32(0xE000E214)
+#define NVIC_PEND6 REG32(0xE000E218)
+#define NVIC_PEND7 REG32(0xE000E21C)
+#define NVIC_UNPEND0 REG32(0xE000E280)
+#define NVIC_UNPEND1 REG32(0xE000E284)
+#define NVIC_UNPEND2 REG32(0xE000E288)
+#define NVIC_UNPEND3 REG32(0xE000E28C)
+#define NVIC_UNPEND4 REG32(0xE000E290)
+#define NVIC_UNPEND5 REG32(0xE000E294)
+#define NVIC_UNPEND6 REG32(0xE000E298)
+#define NVIC_UNPEND7 REG32(0xE000E29C)
+#define NVIC_ACTIVE0 REG32(0xE000E300)
+#define NVIC_ACTIVE1 REG32(0xE000E304)
+#define NVIC_ACTIVE2 REG32(0xE000E308)
+#define NVIC_ACTIVE3 REG32(0xE000E30C)
+#define NVIC_ACTIVE4 REG32(0xE000E310)
+#define NVIC_ACTIVE5 REG32(0xE000E314)
+#define NVIC_ACTIVE6 REG32(0xE000E318)
+#define NVIC_ACTIVE7 REG32(0xE000E31C)
+#define NVIC_PRI0 REG32(0xE000E400)
+#define NVIC_PRI1 REG32(0xE000E404)
+#define NVIC_PRI2 REG32(0xE000E408)
+#define NVIC_PRI3 REG32(0xE000E40C)
+#define NVIC_PRI4 REG32(0xE000E410)
+#define NVIC_PRI5 REG32(0xE000E414)
+#define NVIC_PRI6 REG32(0xE000E418)
+#define NVIC_PRI7 REG32(0xE000E41C)
+#define NVIC_PRI8 REG32(0xE000E420)
+#define NVIC_PRI9 REG32(0xE000E424)
+#define NVIC_PRI10 REG32(0xE000E428)
+#define NVIC_PRI11 REG32(0xE000E42C)
+#define NVIC_PRI12 REG32(0xE000E430)
+#define NVIC_PRI13 REG32(0xE000E434)
+#define NVIC_PRI14 REG32(0xE000E438)
+#define NVIC_PRI15 REG32(0xE000E43C)
+#define NVIC_PRI16 REG32(0xE000E440)
+#define NVIC_PRI17 REG32(0xE000E444)
+#define NVIC_PRI18 REG32(0xE000E448)
+#define NVIC_PRI19 REG32(0xE000E44C)
+#define NVIC_PRI20 REG32(0xE000E450)
+#define NVIC_PRI21 REG32(0xE000E454)
+#define NVIC_PRI22 REG32(0xE000E458)
+#define NVIC_PRI23 REG32(0xE000E45C)
+#define NVIC_PRI24 REG32(0xE000E460)
+#define NVIC_PRI25 REG32(0xE000E464)
+#define NVIC_PRI26 REG32(0xE000E468)
+#define NVIC_PRI27 REG32(0xE000E46C)
+#define NVIC_PRI28 REG32(0xE000E470)
+#define NVIC_PRI29 REG32(0xE000E474)
+#define NVIC_PRI30 REG32(0xE000E478)
+#define NVIC_PRI31 REG32(0xE000E47C)
+#define NVIC_PRI32 REG32(0xE000E480)
+#define NVIC_PRI33 REG32(0xE000E484)
+#define NVIC_PRI34 REG32(0xE000E488)
+#define NVIC_PRI35 REG32(0xE000E48C)
+#define NVIC_PRI36 REG32(0xE000E490)
+#define NVIC_PRI37 REG32(0xE000E494)
+#define NVIC_PRI38 REG32(0xE000E498)
+#define NVIC_PRI39 REG32(0xE000E49C)
+#define NVIC_PRI40 REG32(0xE000E4A0)
+#define NVIC_PRI41 REG32(0xE000E4A4)
+#define NVIC_PRI42 REG32(0xE000E4A8)
+#define NVIC_PRI43 REG32(0xE000E4AC)
+#define NVIC_PRI44 REG32(0xE000E4B0)
+#define NVIC_PRI45 REG32(0xE000E4B4)
+#define NVIC_PRI46 REG32(0xE000E4B8)
+#define NVIC_PRI47 REG32(0xE000E4BC)
+#define NVIC_PRI48 REG32(0xE000E4C0)
+#define NVIC_PRI49 REG32(0xE000E4C4)
+#define NVIC_PRI50 REG32(0xE000E4C8)
+#define NVIC_PRI51 REG32(0xE000E4CC)
+#define NVIC_PRI52 REG32(0xE000E4D0)
+#define NVIC_PRI53 REG32(0xE000E4D4)
+#define NVIC_PRI54 REG32(0xE000E4D8)
+#define NVIC_PRI55 REG32(0xE000E4DC)
+#define NVIC_PRI56 REG32(0xE000E4E0)
+#define NVIC_PRI57 REG32(0xE000E4E4)
+#define NVIC_PRI58 REG32(0xE000E4E8)
+#define NVIC_PRI59 REG32(0xE000E4EC)
+#define NVIC_CPUID REG32(0xE000ED00)
+#define NVIC_INT_CTRL REG32(0xE000ED04)
+#define NVIC_VECT_TABLE REG32(0xE000ED08)
+#define NVIC_AP_INT_RST REG32(0xE000ED0C)
+#define NVIC_SYS_CTRL REG32(0xE000ED10)
+#define NVIC_CFG_CTRL REG32(0xE000ED14)
+#define NVIC_SYS_H_PRI1 REG32(0xE000ED18)
+#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C)
+#define NVIC_SYS_H_PRI3 REG32(0xE000ED20)
+#define NVIC_SYS_H_CTRL REG32(0xE000ED24)
+#define NVIC_FAULT_STA REG32(0xE000ED28)
+#define NVIC_HARD_F_STA REG32(0xE000ED2C)
+#define NVIC_DBG_F_STA REG32(0xE000ED30)
+#define NVIC_MM_F_ADR REG32(0xE000ED34)
+#define NVIC_BUS_F_ADR REG32(0xE000ED38)
+#define NVIC_SW_TRIG REG32(0xE000EF00)
+
+/* MPU Registers */
+#define MPU_TYPE REG32(0xE000ED90)
+#define MPU_CTRL REG32(0xE000ED94)
+#define MPU_RG_NUM REG32(0xE000ED98)
+#define MPU_RG_ADDR REG32(0xE000ED9C)
+#define MPU_RG_AT_SZ REG32(0xE000EDA0)
+
+
+#endif /* #ifndef ARM_REG_H_ */
+
+/** @}
+ */
struct {\r
__I uint8_t OBF : 1; /*!< Output Buffer Full bit */\r
__I uint8_t IBF : 1; /*!< Input Buffer Full bit */\r
- __I uint8_t UD1A : 1; /*!< User Defined */\r
+ __IO uint8_t UD1A : 1; /*!< User Defined */\r
__I uint8_t CMD : 1; /*!< OS2EC Data contains a command byte */\r
__IO uint8_t BURST : 1; /*!< set when the ACPI_EC is in Burst Mode */\r
__IO uint8_t SCI_EVT : 1; /*!< set when an SCI event is pending */\r
__I uint16_t RESERVED1;\r
\r
union {\r
- __IO uint32_t OS2EC_DATA; /*!< OS2EC Data EC-Register */\r
- __IO uint8_t OS2EC_DATA_BYTE[4]; /*!< OS2EC Data Bytes */\r
+ __I uint32_t OS2EC_DATA; /*!< OS2EC Data EC-Register */\r
+ __I uint8_t OS2EC_DATA_BYTE[4]; /*!< OS2EC Data Bytes */\r
};\r
} ACPI_EC0_Type;\r
\r
__IO uint8_t UD0 : 1; /*!< User-defined data. */\r
__I uint8_t CMDnDATA : 1; /*!< data register contains data(0) or command(1) */\r
__IO uint8_t UD1 : 1; /*!< User-defined data. */\r
- __IO uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */\r
+ __I uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */\r
__IO uint8_t UD2 : 2; /*!< User-defined data. */\r
} STATUS_b; /*!< BitSize */\r
};\r
__I uint8_t RESERVED1[7];\r
__O uint8_t SETGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */\r
__I uint8_t RESERVED2[3];\r
- __IO uint8_t RSTGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */\r
+ __O uint8_t RSTGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */\r
__I uint8_t RESERVED3[547];\r
__IO uint8_t PORT92_ENABLE; /*!< [0:0] 1= Port92h Register is enabled. */\r
} PORT92_Type;\r
__IO uint8_t VALID_TACH_COUNT; /*!< max value to indicate fan spin properly */\r
__IO uint16_t DRIVE_FAIL_BAND; /*!< [15:3]counts for Drive Fail circuitry */\r
__IO uint16_t TACH_TARGET; /*!< [12:0] The target tachometer value. */\r
- __IO uint8_t TACH_READING; /*!< [15:3]current tachometer reading value. */\r
- __I uint8_t RESERVED1;\r
+ __IO uint16_t TACH_READING; /*!< [15:3]current tachometer reading value. */\r
__IO uint8_t DRIVER_BASE_FREQUENCY; /*!< [1:0]frequency range of the PWM fan driver */\r
\r
union {\r
\r
\r
/*------------- Public Key Encryption Subsystem (PKE) -----------------------------*/\r
-/** @addtogroup MEC1322_PKE Public Key Encryption (PKE)\r
+/** @addtogroup CEC1302_PKE Public Key Encryption (PKE)\r
@{\r
*/\r
typedef struct\r
__I uint32_t VERSION; /*!< Offset: 0x0010 Version */\r
__IO uint32_t LOAD_MICRO_CODE; /*!< Offset: 0x0014 Load Micro Code */\r
} PKE_TypeDef;\r
-/*@}*/ /* end of group MEC1322_PKE */\r
+/*@}*/ /* end of group CEC1302_PKE */\r
\r
/*------------- Random Number Generator Subsystem (TRNG) -----------------------------*/\r
-/** @addtogroup MEC1322_TRNG Random Number Generator (TRNG)\r
+/** @addtogroup CEC1302_TRNG Random Number Generator (TRNG)\r
@{\r
*/\r
typedef struct\r
__I uint32_t FIFO_LEVEL; /*!< Offset: 0x0004 FIFO Level */\r
__I uint32_t VERSION; /*!< Offset: 0x0008 Version */\r
} TRNG_TypeDef;\r
-/*@}*/ /* end of group MEC1322_TRNG */\r
+/*@}*/ /* end of group CEC1302_TRNG */\r
\r
/*------------- Hash Subsystem (HASH) -----------------------------*/\r
-/** @addtogroup MEC1322_HASH Hash Security (HASH)\r
+/** @addtogroup CEC1302_HASH Hash Security (HASH)\r
@{\r
*/\r
typedef struct\r
__IO uint32_t DATA_SOURCE_ADDR; /*!< Offset: 0x001C Data to hash Address */\r
__IO uint32_t HASH_RESULT_ADDR; /*!< Offset: 0x0020 Hash result address */\r
} HASH_TypeDef;\r
-/*@}*/ /* end of group MEC1322_HASH */\r
+/*@}*/ /* end of group CEC1302_HASH */\r
\r
\r
\r
/*------------- Advanced Encryption Subsystem (AES) -----------------------------*/\r
-/** @addtogroup MEC1322_AES Advanced Encryption Subsys (AES)\r
+/** @addtogroup CEC1302_AES Advanced Encryption Subsys (AES)\r
@{\r
*/\r
\r
!< Offset: 0x0158 KeyIn1[95:64] \r
!< Offset: 0x015C KeyIn1[127:96] */\r
} AES_TypeDef;\r
-/*@}*/ /* end of group MEC1322_AES */\r
+/*@}*/ /* end of group CEC1302_AES */\r
\r
/* -------------------- End of section using anonymous unions ------------------- */\r
#if defined(__CC_ARM)\r
#define ACPI_EC0_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC0 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */\r
\r
\r
-/* ================================================================================ */\r
-/* ================ struct 'ACPI_EC1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- ACPI_EC1_OS_STATUS ----------------------------- */\r
-#define ACPI_EC1_OS_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bit 0) */\r
-#define ACPI_EC1_OS_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bit 1) */\r
-#define ACPI_EC1_OS_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_UD1B_Pos (2UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bit 2) */\r
-#define ACPI_EC1_OS_STATUS_UD1B_Msk (0x4UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bit 3) */\r
-#define ACPI_EC1_OS_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bit 4) */\r
-#define ACPI_EC1_OS_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bit 5) */\r
-#define ACPI_EC1_OS_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bit 6) */\r
-#define ACPI_EC1_OS_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_UD0B_Pos (7UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bit 7) */\r
-#define ACPI_EC1_OS_STATUS_UD0B_Msk (0x80UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bitfield-Mask: 0x01) */\r
-\r
-/* ----------------------------- ACPI_EC1_EC_STATUS ----------------------------- */\r
-#define ACPI_EC1_EC_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bit 0) */\r
-#define ACPI_EC1_EC_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bit 1) */\r
-#define ACPI_EC1_EC_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_UD1A_Pos (2UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bit 2) */\r
-#define ACPI_EC1_EC_STATUS_UD1A_Msk (0x4UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bit 3) */\r
-#define ACPI_EC1_EC_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bit 4) */\r
-#define ACPI_EC1_EC_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bit 5) */\r
-#define ACPI_EC1_EC_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bit 6) */\r
-#define ACPI_EC1_EC_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_UD0A_Pos (7UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bit 7) */\r
-#define ACPI_EC1_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'KBC' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------- KBC_RD_PORT64_STATUS ---------------------------- */\r
-#define KBC_RD_PORT64_STATUS_OBF_Pos (0UL) /*!< KBC RD_PORT64_STATUS: OBF (Bit 0) */\r
-#define KBC_RD_PORT64_STATUS_OBF_Msk (0x1UL) /*!< KBC RD_PORT64_STATUS: OBF (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_IBF_Pos (1UL) /*!< KBC RD_PORT64_STATUS: IBF (Bit 1) */\r
-#define KBC_RD_PORT64_STATUS_IBF_Msk (0x2UL) /*!< KBC RD_PORT64_STATUS: IBF (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_UD0_Pos (2UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bit 2) */\r
-#define KBC_RD_PORT64_STATUS_UD0_Msk (0x4UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_CMDnDATA_Pos (3UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bit 3) */\r
-#define KBC_RD_PORT64_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_UD1_Pos (4UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bit 4) */\r
-#define KBC_RD_PORT64_STATUS_UD1_Msk (0x10UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_AUXOBF_Pos (5UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bit 5) */\r
-#define KBC_RD_PORT64_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_UD2_Pos (6UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bit 6) */\r
-#define KBC_RD_PORT64_STATUS_UD2_Msk (0xc0UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bitfield-Mask: 0x03) */\r
-\r
-/* --------------------------------- KBC_STATUS --------------------------------- */\r
-#define KBC_STATUS_OBF_Pos (0UL) /*!< KBC STATUS: OBF (Bit 0) */\r
-#define KBC_STATUS_OBF_Msk (0x1UL) /*!< KBC STATUS: OBF (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_IBF_Pos (1UL) /*!< KBC STATUS: IBF (Bit 1) */\r
-#define KBC_STATUS_IBF_Msk (0x2UL) /*!< KBC STATUS: IBF (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_UD0_Pos (2UL) /*!< KBC STATUS: UD0 (Bit 2) */\r
-#define KBC_STATUS_UD0_Msk (0x4UL) /*!< KBC STATUS: UD0 (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_CMDnDATA_Pos (3UL) /*!< KBC STATUS: CMDnDATA (Bit 3) */\r
-#define KBC_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC STATUS: CMDnDATA (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_UD1_Pos (4UL) /*!< KBC STATUS: UD1 (Bit 4) */\r
-#define KBC_STATUS_UD1_Msk (0x10UL) /*!< KBC STATUS: UD1 (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_AUXOBF_Pos (5UL) /*!< KBC STATUS: AUXOBF (Bit 5) */\r
-#define KBC_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC STATUS: AUXOBF (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_UD2_Pos (6UL) /*!< KBC STATUS: UD2 (Bit 6) */\r
-#define KBC_STATUS_UD2_Msk (0xc0UL) /*!< KBC STATUS: UD2 (Bitfield-Mask: 0x03) */\r
-\r
-/* --------------------------------- KBC_CONTROL -------------------------------- */\r
-#define KBC_CONTROL_UD3_Pos (0UL) /*!< KBC CONTROL: UD3 (Bit 0) */\r
-#define KBC_CONTROL_UD3_Msk (0x1UL) /*!< KBC CONTROL: UD3 (Bitfield-Mask: 0x01) */\r
-#define KBC_CONTROL_SAEN_Pos (1UL) /*!< KBC CONTROL: SAEN (Bit 1) */\r
-#define KBC_CONTROL_SAEN_Msk (0x2UL) /*!< KBC CONTROL: SAEN (Bitfield-Mask: 0x01) */\r
-#define KBC_CONTROL_PCOBFEN_Pos (2UL) /*!< KBC CONTROL: PCOBFEN (Bit 2) */\r
-#define KBC_CONTROL_PCOBFEN_Msk (0x4UL) /*!< KBC CONTROL: PCOBFEN (Bitfield-Mask: 0x01) */\r
-#define KBC_CONTROL_UD4_Pos (3UL) /*!< KBC CONTROL: UD4 (Bit 3) */\r
-#define KBC_CONTROL_UD4_Msk (0x18UL) /*!< KBC CONTROL: UD4 (Bitfield-Mask: 0x03) */\r
-#define KBC_CONTROL_OBFEN_Pos (5UL) /*!< KBC CONTROL: OBFEN (Bit 5) */\r
-#define KBC_CONTROL_OBFEN_Msk (0x20UL) /*!< KBC CONTROL: OBFEN (Bitfield-Mask: 0x01) */\r
-#define KBC_CONTROL_UD5_Pos (6UL) /*!< KBC CONTROL: UD5 (Bit 6) */\r
-#define KBC_CONTROL_UD5_Msk (0x40UL) /*!< KBC CONTROL: UD5 (Bitfield-Mask: 0x01) */\r
-#define KBC_CONTROL_AUXH_Pos (7UL) /*!< KBC CONTROL: AUXH (Bit 7) */\r
-#define KBC_CONTROL_AUXH_Msk (0x80UL) /*!< KBC CONTROL: AUXH (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PORT92' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PORT92_PORT92 ------------------------------- */\r
-#define PORT92_PORT92_ALT_CPU_RESET_Pos (0UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bit 0) */\r
-#define PORT92_PORT92_ALT_CPU_RESET_Msk (0x1UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bitfield-Mask: 0x01) */\r
-#define PORT92_PORT92_ALT_GATE_A20_Pos (1UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bit 1) */\r
-#define PORT92_PORT92_ALT_GATE_A20_Msk (0x2UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bitfield-Mask: 0x01) */\r
-\r
-\r
/* ================================================================================ */\r
/* ================ struct 'MBX' Position & Mask ================ */\r
/* ================================================================================ */\r
+++ /dev/null
-/*******************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-********************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-$File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/MEC1322.h $\r
-********************************************************************************\r
-$Revision: #1 $\r
-$DateTime: 2015/12/23 15:37:58 $\r
-$Author: akrishnan $\r
- Change Description: Initial revision for MEC1322\r
-******************************************************************************/\r
-/** @file smscmmcr.h\r
-* brief the mmcr definitions\r
-* \r
-******************************************************************************/\r
-#ifndef SMSCMMCR_H_\r
-#define SMSCMMCR_H_\r
-\r
-//NOTE: Please Don't edit this File, this is extrated from the Spread sheet \r
-// : //depotAE/projects/MEC1322/docs/MMCRs/MEC1322_FPGA1_Query_All_Addressing_ResultSet.csv\r
-typedef volatile unsigned char VUINT8;\r
-typedef volatile unsigned short int VUINT16;\r
-typedef volatile unsigned long int VUINT32;\r
-\r
-/***************************************************************\r
-* PWM\r
-***************************************************************/\r
-#define ADDR_PWM_0_COUNTER_ON_TIME 0x40005800\r
-#define MMCR_PWM_0_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_0_COUNTER_OFF_TIME 0x40005804\r
-#define MMCR_PWM_0_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_0_CONFIGURATION 0x40005808\r
-#define MMCR_PWM_0_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_0_CONFIGURATION))\r
-\r
-#define ADDR_PWM_1_COUNTER_ON_TIME 0x40005810\r
-#define MMCR_PWM_1_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_1_COUNTER_OFF_TIME 0x40005814\r
-#define MMCR_PWM_1_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_1_CONFIGURATION 0x40005818\r
-#define MMCR_PWM_1_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_1_CONFIGURATION))\r
-\r
-#define ADDR_PWM_2_COUNTER_ON_TIME 0x40005820\r
-#define MMCR_PWM_2_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_2_COUNTER_OFF_TIME 0x40005824\r
-#define MMCR_PWM_2_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_2_CONFIGURATION 0x40005828\r
-#define MMCR_PWM_2_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_2_CONFIGURATION))\r
-\r
-#define ADDR_PWM_3_COUNTER_ON_TIME 0x40005830\r
-#define MMCR_PWM_3_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_3_COUNTER_OFF_TIME 0x40005834\r
-#define MMCR_PWM_3_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_3_CONFIGURATION 0x40005838\r
-#define MMCR_PWM_3_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_3_CONFIGURATION))\r
-\r
-/***************************************************************\r
-* PECI\r
-***************************************************************/\r
-#define ADDR_PECI_WRITE_DATA 0x40006400\r
-#define MMCR_PECI_WRITE_DATA (*(VUINT32 *)(ADDR_PECI_WRITE_DATA))\r
-\r
-#define ADDR_PECI_READ_DATA 0x40006404\r
-#define MMCR_PECI_READ_DATA (*(VUINT32 *)(ADDR_PECI_READ_DATA))\r
-\r
-#define ADDR_PECI_CONTROL 0x40006408\r
-#define MMCR_PECI_CONTROL (*(VUINT32 *)(ADDR_PECI_CONTROL))\r
-\r
-#define ADDR_PECI_STATUS_1 0x4000640C\r
-#define MMCR_PECI_STATUS_1 (*(VUINT32 *)(ADDR_PECI_STATUS_1))\r
-\r
-#define ADDR_PECI_STATUS_2 0x40006410\r
-#define MMCR_PECI_STATUS_2 (*(VUINT32 *)(ADDR_PECI_STATUS_2))\r
-\r
-#define ADDR_PECI_ERROR 0x40006414\r
-#define MMCR_PECI_ERROR (*(VUINT32 *)(ADDR_PECI_ERROR))\r
-\r
-#define ADDR_PECI_INTERRUPT_ENABLE_1 0x40006418\r
-#define MMCR_PECI_INTERRUPT_ENABLE_1 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_1))\r
-\r
-#define ADDR_PECI_INTERRUPT_ENABLE_2 0x4000641C\r
-#define MMCR_PECI_INTERRUPT_ENABLE_2 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_2))\r
-\r
-#define ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE 0x40006420\r
-#define MMCR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE))\r
-\r
-#define ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE 0x40006424\r
-#define MMCR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE))\r
-\r
-#define ADDR_PECI_REQUEST_TIMER_LOW_BYTE 0x40006428\r
-#define MMCR_PECI_REQUEST_TIMER_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_LOW_BYTE))\r
-\r
-#define ADDR_PECI_REQUEST_TIMER_HIGH_BYTE 0x4000642C\r
-#define MMCR_PECI_REQUEST_TIMER_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_HIGH_BYTE))\r
-\r
-#define ADDR_PECI_BLOCK_ID 0x40006440\r
-#define MMCR_PECI_BLOCK_ID (*(VUINT32 *)(ADDR_PECI_BLOCK_ID))\r
-\r
-#define ADDR_PECI_BLOCK_REVISION 0x40006444\r
-#define MMCR_PECI_BLOCK_REVISION (*(VUINT32 *)(ADDR_PECI_BLOCK_REVISION))\r
-\r
-/***************************************************************\r
-* ACPI EC Interface \r
-***************************************************************/\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0 0x400F0D00\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1 0x400F0D01\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2 0x400F0D02\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3 0x400F0D03\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3))\r
-\r
-#define ADDR_ACPI_0_STATUS_EC 0x400F0D04\r
-#define MMCR_ACPI_0_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_0_STATUS_EC))\r
-\r
-#define ADDR_ACPI_0_BYTE_CONTROL_EC 0x400F0D05\r
-#define MMCR_ACPI_0_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_0_BYTE_CONTROL_EC))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1 0x400F0D09\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2 0x400F0D0A\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3 0x400F0D0B\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0 0x400F1100\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1 0x400F1101\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2 0x400F1102\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3 0x400F1103\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3))\r
-\r
-#define ADDR_ACPI_1_STATUS_EC 0x400F1104\r
-#define MMCR_ACPI_1_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_1_STATUS_EC))\r
-\r
-#define ADDR_ACPI_1_BYTE_CONTROL_EC 0x400F1105\r
-#define MMCR_ACPI_1_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_1_BYTE_CONTROL_EC))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1 0x400F1109\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2 0x400F110A\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3 0x400F110B\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3))\r
-\r
-/***************************************************************\r
-* Keyboard Matrix Scan Support\r
-***************************************************************/\r
-#define ADDR_KEYBOARD_KSO_SELECT 0x40009C04\r
-#define MMCR_KEYBOARD_KSO_SELECT (*(VUINT32 *)(ADDR_KEYBOARD_KSO_SELECT))\r
-\r
-#define ADDR_KEYBOARD_KSI_INPUT 0x40009C08\r
-#define MMCR_KEYBOARD_KSI_INPUT (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INPUT))\r
-\r
-#define ADDR_KEYBOARD_KSI_STATUS 0x40009C0C\r
-#define MMCR_KEYBOARD_KSI_STATUS (*(VUINT32 *)(ADDR_KEYBOARD_KSI_STATUS))\r
-\r
-#define ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE 0x40009C10\r
-#define MMCR_KEYBOARD_KSI_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL 0x40009C14\r
-#define MMCR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL (*(VUINT32 *)(ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL))\r
-\r
-/***************************************************************\r
-* PS/2 Device Interface\r
-***************************************************************/\r
-#define ADDR_PS2_3_STATUS 0x400090C8\r
-#define MMCR_PS2_3_STATUS (*(VUINT8 *)(ADDR_PS2_3_STATUS))\r
-\r
-#define ADDR_PS2_3_CONTROL 0x400090C4\r
-#define MMCR_PS2_3_CONTROL (*(VUINT8 *)(ADDR_PS2_3_CONTROL))\r
-\r
-#define ADDR_PS2_3_RECEIVE_BUFFER 0x400090C0\r
-#define MMCR_PS2_3_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_3_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_3_TRANSMIT_BUFFER 0x400090C0\r
-#define MMCR_PS2_3_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_3_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_0_TRANSMIT_BUFFER 0x40009000\r
-#define MMCR_PS2_0_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_0_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_0_RECEIVE_BUFFER 0x40009000\r
-#define MMCR_PS2_0_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_0_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_0_CONTROL 0x40009004\r
-#define MMCR_PS2_0_CONTROL (*(VUINT8 *)(ADDR_PS2_0_CONTROL))\r
-\r
-#define ADDR_PS2_0_STATUS 0x40009008\r
-#define MMCR_PS2_0_STATUS (*(VUINT8 *)(ADDR_PS2_0_STATUS))\r
-\r
-#define ADDR_PS2_1_TRANSMIT_BUFFER 0x40009040\r
-#define MMCR_PS2_1_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_1_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_1_RECEIVE_BUFFER 0x40009040\r
-#define MMCR_PS2_1_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_1_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_1_CONTROL 0x40009044\r
-#define MMCR_PS2_1_CONTROL (*(VUINT8 *)(ADDR_PS2_1_CONTROL))\r
-\r
-#define ADDR_PS2_1_STATUS 0x40009048\r
-#define MMCR_PS2_1_STATUS (*(VUINT8 *)(ADDR_PS2_1_STATUS))\r
-\r
-#define ADDR_PS2_2_RECEIVE_BUFFER 0x40009080\r
-#define MMCR_PS2_2_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_2_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_2_TRANSMIT_BUFFER 0x40009080\r
-#define MMCR_PS2_2_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_2_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_2_CONTROL 0x40009084\r
-#define MMCR_PS2_2_CONTROL (*(VUINT8 *)(ADDR_PS2_2_CONTROL))\r
-\r
-#define ADDR_PS2_2_STATUS 0x40009088\r
-#define MMCR_PS2_2_STATUS (*(VUINT8 *)(ADDR_PS2_2_STATUS))\r
-\r
-/***************************************************************\r
-* 8042 Host Interface\r
-***************************************************************/\r
-#define ADDR_8042_ACTIVATE 0x400F0730\r
-#define MMCR_8042_ACTIVATE (*(VUINT8 *)(ADDR_8042_ACTIVATE))\r
-\r
-#define ADDR_8042_HOST_EC_DATACMD 0x400F0500\r
-#define MMCR_8042_HOST_EC_DATACMD (*(VUINT8 *)(ADDR_8042_HOST_EC_DATACMD))\r
-\r
-#define ADDR_8042_EC_HOST_DATA 0x400F0500\r
-#define MMCR_8042_EC_HOST_DATA (*(VUINT8 *)(ADDR_8042_EC_HOST_DATA))\r
-\r
-#define ADDR_8042_KEYBOARD_STATUS_READ 0x400F0504\r
-#define MMCR_8042_KEYBOARD_STATUS_READ (*(VUINT8 *)(ADDR_8042_KEYBOARD_STATUS_READ))\r
-\r
-#define ADDR_8042_KEYBOARD_CONTROL 0x400F0508\r
-#define MMCR_8042_KEYBOARD_CONTROL (*(VUINT8 *)(ADDR_8042_KEYBOARD_CONTROL))\r
-\r
-#define ADDR_8042_EC_HOST_AUX 0x400F050C\r
-#define MMCR_8042_EC_HOST_AUX (*(VUINT8 *)(ADDR_8042_EC_HOST_AUX))\r
-\r
-#define ADDR_8042_PCOBF 0x400F0514\r
-#define MMCR_8042_PCOBF (*(VUINT8 *)(ADDR_8042_PCOBF))\r
-\r
-#define ADDR_8042_PORT92_ENABLE 0x400F1B30\r
-#define MMCR_8042_PORT92_ENABLE (*(VUINT8 *)(ADDR_8042_PORT92_ENABLE))\r
-\r
-#define ADDR_8042_GATEA20_CONTROL 0x400F1900\r
-#define MMCR_8042_GATEA20_CONTROL (*(VUINT8 *)(ADDR_8042_GATEA20_CONTROL))\r
-\r
-#define ADDR_8042_SETGA20L 0x400F1908\r
-#define MMCR_8042_SETGA20L (*(VUINT8 *)(ADDR_8042_SETGA20L))\r
-\r
-#define ADDR_8042_RSTGA20L 0x400F190C\r
-#define MMCR_8042_RSTGA20L (*(VUINT8 *)(ADDR_8042_RSTGA20L))\r
-\r
-/***************************************************************\r
-* SMBus\r
-***************************************************************/\r
-#define ADDR_SMB_3_DEBUG_FSM_SMB 0x4000B45C\r
-#define MMCR_SMB_3_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_SMB))\r
-\r
-#define ADDR_SMB_3_DEBUG_FSM_I2C 0x4000B458\r
-#define MMCR_SMB_3_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER 0x4000B454\r
-#define MMCR_SMBUS_3_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER 0x4000B450\r
-#define MMCR_SMBUS_3_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER 0x4000B44C\r
-#define MMCR_SMBUS_3_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER 0x4000B448\r
-#define MMCR_SMBUS_3_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMB_3_TIME_OUT_SCALING 0x4000B444\r
-#define MMCR_SMB_3_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_3_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMB_3_DATA_TIMING 0x4000B440\r
-#define MMCR_SMB_3_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_3_DATA_TIMING))\r
-\r
-#define ADDR_SMB_3_CLOCK_SYNC 0x4000B43C\r
-#define MMCR_SMB_3_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_3_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_3_BIT_BANG_CONTROL 0x4000B438\r
-#define MMCR_SMB_3_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_3_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_3_REVISION 0x4000B434\r
-#define MMCR_SMB_3_REVISION (*(VUINT8 *)(ADDR_SMB_3_REVISION))\r
-\r
-#define ADDR_SMB_3_BLOCK_ID 0x4000B430\r
-#define MMCR_SMB_3_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_3_BLOCK_ID))\r
-\r
-#define ADDR_SMB_3_BUS_CLOCK 0x4000B42C\r
-#define MMCR_SMB_3_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_3_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_3_CONFIGURATION 0x4000B428\r
-#define MMCR_SMB_3_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_3_CONFIGURATION))\r
-\r
-#define ADDR_SMB_3_IDLE_SCALING 0x4000B424\r
-#define MMCR_SMB_3_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_3_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_3_COMPLETION 0x4000B420\r
-#define MMCR_SMB_3_COMPLETION (*(VUINT32 *)(ADDR_SMB_3_COMPLETION))\r
-\r
-#define ADDR_SMB_3_DATA_TIMING2 0x4000B418\r
-#define MMCR_SMB_3_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_3_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_3_PEC 0x4000B414\r
-#define MMCR_SMB_3_PEC (*(VUINT8 *)(ADDR_SMB_3_PEC))\r
-\r
-#define ADDR_SMBUS_3_SLAVE_COMMAND 0x4000B410\r
-#define MMCR_SMBUS_3_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMBUS_3_MASTER_COMMAND 0x4000B40C\r
-#define MMCR_SMBUS_3_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_MASTER_COMMAND))\r
-\r
-#define ADDR_SMB_3_DATA 0x4000B408\r
-#define MMCR_SMB_3_DATA (*(VUINT8 *)(ADDR_SMB_3_DATA))\r
-\r
-#define ADDR_SMB_3_OWN_ADDRESS 0x4000B404\r
-#define MMCR_SMB_3_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_3_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_3_STATUS 0x4000B400\r
-#define MMCR_SMB_3_STATUS (*(VUINT8 *)(ADDR_SMB_3_STATUS))\r
-\r
-#define ADDR_SMB_3_CONTROL 0x4000B400\r
-#define MMCR_SMB_3_CONTROL (*(VUINT8 *)(ADDR_SMB_3_CONTROL))\r
-\r
-#define ADDR_SMB_2_CONTROL 0x4000B000\r
-#define MMCR_SMB_2_CONTROL (*(VUINT8 *)(ADDR_SMB_2_CONTROL))\r
-\r
-#define ADDR_SMB_2_STATUS 0x4000B000\r
-#define MMCR_SMB_2_STATUS (*(VUINT8 *)(ADDR_SMB_2_STATUS))\r
-\r
-#define ADDR_SMB_2_OWN_ADDRESS 0x4000B004\r
-#define MMCR_SMB_2_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_2_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_2_DATA 0x4000B008\r
-#define MMCR_SMB_2_DATA (*(VUINT8 *)(ADDR_SMB_2_DATA))\r
-\r
-#define ADDR_SMBUS_2_MASTER_COMMAND 0x4000B00C\r
-#define MMCR_SMBUS_2_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_MASTER_COMMAND))\r
-\r
-#define ADDR_SMBUS_2_SLAVE_COMMAND 0x4000B010\r
-#define MMCR_SMBUS_2_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMB_2_PEC 0x4000B014\r
-#define MMCR_SMB_2_PEC (*(VUINT8 *)(ADDR_SMB_2_PEC))\r
-\r
-#define ADDR_SMB_2_DATA_TIMING2 0x4000B018\r
-#define MMCR_SMB_2_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_2_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_2_COMPLETION 0x4000B020\r
-#define MMCR_SMB_2_COMPLETION (*(VUINT32 *)(ADDR_SMB_2_COMPLETION))\r
-\r
-#define ADDR_SMB_2_IDLE_SCALING 0x4000B024\r
-#define MMCR_SMB_2_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_2_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_2_CONFIGURATION 0x4000B028\r
-#define MMCR_SMB_2_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_2_CONFIGURATION))\r
-\r
-#define ADDR_SMB_2_BUS_CLOCK 0x4000B02C\r
-#define MMCR_SMB_2_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_2_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_2_BLOCK_ID 0x4000B030\r
-#define MMCR_SMB_2_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_2_BLOCK_ID))\r
-\r
-#define ADDR_SMB_2_REVISION 0x4000B034\r
-#define MMCR_SMB_2_REVISION (*(VUINT8 *)(ADDR_SMB_2_REVISION))\r
-\r
-#define ADDR_SMB_2_BIT_BANG_CONTROL 0x4000B038\r
-#define MMCR_SMB_2_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_2_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_2_CLOCK_SYNC 0x4000B03C\r
-#define MMCR_SMB_2_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_2_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_2_DATA_TIMING 0x4000B040\r
-#define MMCR_SMB_2_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_2_DATA_TIMING))\r
-\r
-#define ADDR_SMB_2_TIME_OUT_SCALING 0x4000B044\r
-#define MMCR_SMB_2_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_2_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER 0x4000B048\r
-#define MMCR_SMBUS_2_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER 0x4000B04C\r
-#define MMCR_SMBUS_2_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER 0x4000B050\r
-#define MMCR_SMBUS_2_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER 0x4000B054\r
-#define MMCR_SMBUS_2_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMB_2_DEBUG_FSM_I2C 0x4000B058\r
-#define MMCR_SMB_2_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMB_2_DEBUG_FSM_SMB 0x4000B05C\r
-#define MMCR_SMB_2_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_SMB))\r
-\r
-#define ADDR_SMB_1_CONTROL 0x4000AC00\r
-#define MMCR_SMB_1_CONTROL (*(VUINT8 *)(ADDR_SMB_1_CONTROL))\r
-\r
-#define ADDR_SMB_1_STATUS 0x4000AC00\r
-#define MMCR_SMB_1_STATUS (*(VUINT8 *)(ADDR_SMB_1_STATUS))\r
-\r
-#define ADDR_SMB_1_OWN_ADDRESS 0x4000AC04\r
-#define MMCR_SMB_1_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_1_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_1_DATA 0x4000AC08\r
-#define MMCR_SMB_1_DATA (*(VUINT8 *)(ADDR_SMB_1_DATA))\r
-\r
-#define ADDR_SMBUS_1_MASTER_COMMAND 0x4000AC0C\r
-#define MMCR_SMBUS_1_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_MASTER_COMMAND))\r
-\r
-#define ADDR_SMBUS_1_SLAVE_COMMAND 0x4000AC10\r
-#define MMCR_SMBUS_1_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMB_1_PEC 0x4000AC14\r
-#define MMCR_SMB_1_PEC (*(VUINT8 *)(ADDR_SMB_1_PEC))\r
-\r
-#define ADDR_SMB_1_DATA_TIMING2 0x4000AC18\r
-#define MMCR_SMB_1_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_1_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_1_COMPLETION 0x4000AC20\r
-#define MMCR_SMB_1_COMPLETION (*(VUINT32 *)(ADDR_SMB_1_COMPLETION))\r
-\r
-#define ADDR_SMB_1_IDLE_SCALING 0x4000AC24\r
-#define MMCR_SMB_1_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_1_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_1_CONFIGURATION 0x4000AC28\r
-#define MMCR_SMB_1_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_1_CONFIGURATION))\r
-\r
-#define ADDR_SMB_1_BUS_CLOCK 0x4000AC2C\r
-#define MMCR_SMB_1_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_1_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_1_BLOCK_ID 0x4000AC30\r
-#define MMCR_SMB_1_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_1_BLOCK_ID))\r
-\r
-#define ADDR_SMB_1_REVISION 0x4000AC34\r
-#define MMCR_SMB_1_REVISION (*(VUINT8 *)(ADDR_SMB_1_REVISION))\r
-\r
-#define ADDR_SMB_1_BIT_BANG_CONTROL 0x4000AC38\r
-#define MMCR_SMB_1_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_1_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_1_CLOCK_SYNC 0x4000AC3C\r
-#define MMCR_SMB_1_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_1_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_1_DATA_TIMING 0x4000AC40\r
-#define MMCR_SMB_1_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_1_DATA_TIMING))\r
-\r
-#define ADDR_SMB_1_TIME_OUT_SCALING 0x4000AC44\r
-#define MMCR_SMB_1_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_1_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER 0x4000AC48\r
-#define MMCR_SMBUS_1_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER 0x4000AC4C\r
-#define MMCR_SMBUS_1_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER 0x4000AC50\r
-#define MMCR_SMBUS_1_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER 0x4000AC54\r
-#define MMCR_SMBUS_1_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMB_1_DEBUG_FSM_I2C 0x4000AC58\r
-#define MMCR_SMB_1_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMB_1_DEBUG_FSM_SMB 0x4000AC5C\r
-#define MMCR_SMB_1_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_SMB))\r
-\r
-#define ADDR_SMB_0_STATUS 0x40001800\r
-#define MMCR_SMB_0_STATUS (*(VUINT8 *)(ADDR_SMB_0_STATUS))\r
-\r
-#define ADDR_SMB_0_CONTROL 0x40001800\r
-#define MMCR_SMB_0_CONTROL (*(VUINT8 *)(ADDR_SMB_0_CONTROL))\r
-\r
-#define ADDR_SMB_0_OWN_ADDRESS 0x40001804\r
-#define MMCR_SMB_0_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_0_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_0_DATA 0x40001808\r
-#define MMCR_SMB_0_DATA (*(VUINT8 *)(ADDR_SMB_0_DATA))\r
-\r
-#define ADDR_SMBUS_0_MASTER_COMMAND 0x4000180C\r
-#define MMCR_SMBUS_0_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_MASTER_COMMAND))\r
-\r
-#define ADDR_SMBUS_0_SLAVE_COMMAND 0x40001810\r
-#define MMCR_SMBUS_0_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMB_0_PEC 0x40001814\r
-#define MMCR_SMB_0_PEC (*(VUINT8 *)(ADDR_SMB_0_PEC))\r
-\r
-#define ADDR_SMB_0_DATA_TIMING2 0x40001818\r
-#define MMCR_SMB_0_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_0_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_0_COMPLETION 0x40001820\r
-#define MMCR_SMB_0_COMPLETION (*(VUINT32 *)(ADDR_SMB_0_COMPLETION))\r
-\r
-#define ADDR_SMB_0_IDLE_SCALING 0x40001824\r
-#define MMCR_SMB_0_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_0_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_0_CONFIGURATION 0x40001828\r
-#define MMCR_SMB_0_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_0_CONFIGURATION))\r
-\r
-#define ADDR_SMB_0_BUS_CLOCK 0x4000182C\r
-#define MMCR_SMB_0_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_0_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_0_BLOCK_ID 0x40001830\r
-#define MMCR_SMB_0_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_0_BLOCK_ID))\r
-\r
-#define ADDR_SMB_0_REVISION 0x40001834\r
-#define MMCR_SMB_0_REVISION (*(VUINT8 *)(ADDR_SMB_0_REVISION))\r
-\r
-#define ADDR_SMB_0_BIT_BANG_CONTROL 0x40001838\r
-#define MMCR_SMB_0_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_0_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_0_CLOCK_SYNC 0x4000183C\r
-#define MMCR_SMB_0_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_0_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_0_DATA_TIMING 0x40001840\r
-#define MMCR_SMB_0_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_0_DATA_TIMING))\r
-\r
-#define ADDR_SMB_0_TIME_OUT_SCALING 0x40001844\r
-#define MMCR_SMB_0_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_0_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER 0x40001848\r
-#define MMCR_SMBUS_0_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER 0x4000184C\r
-#define MMCR_SMBUS_0_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER 0x40001850\r
-#define MMCR_SMBUS_0_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER 0x40001854\r
-#define MMCR_SMBUS_0_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMB_0_DEBUG_FSM_I2C 0x40001858\r
-#define MMCR_SMB_0_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMB_0_DEBUG_FSM_SMB 0x4000185C\r
-#define MMCR_SMB_0_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_SMB))\r
-\r
-/***************************************************************\r
-* Watchdog Timer Interface\r
-***************************************************************/\r
-#define ADDR_WATCHDOG_WDT_LOAD 0x40000400\r
-#define MMCR_WATCHDOG_WDT_LOAD (*(VUINT16 *)(ADDR_WATCHDOG_WDT_LOAD))\r
-\r
-#define ADDR_WATCHDOG_WDT_CONTROL 0x40000404\r
-#define MMCR_WATCHDOG_WDT_CONTROL (*(VUINT8 *)(ADDR_WATCHDOG_WDT_CONTROL))\r
-\r
-#define ADDR_WATCHDOG_WDT_KICK 0x40000408\r
-#define MMCR_WATCHDOG_WDT_KICK (*(VUINT8 *)(ADDR_WATCHDOG_WDT_KICK))\r
-\r
-#define ADDR_WATCHDOG_WDT_COUNT 0x4000040C\r
-#define MMCR_WATCHDOG_WDT_COUNT (*(VUINT16 *)(ADDR_WATCHDOG_WDT_COUNT))\r
-\r
-/***************************************************************\r
-* ACPI PM1\r
-***************************************************************/\r
-#define ADDR_ACPI_0_PM1_STATUS_1 0x400F1500\r
-#define MMCR_ACPI_0_PM1_STATUS_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_1))\r
-\r
-#define ADDR_ACPI_0_PM1_STATUS_2 0x400F1501\r
-#define MMCR_ACPI_0_PM1_STATUS_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_2))\r
-\r
-#define ADDR_ACPI_0_PM1_ENABLE_1 0x400F1502\r
-#define MMCR_ACPI_0_PM1_ENABLE_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_1))\r
-\r
-#define ADDR_ACPI_0_PM1_ENABLE_2 0x400F1503\r
-#define MMCR_ACPI_0_PM1_ENABLE_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_2))\r
-\r
-#define ADDR_ACPI_0_PM1_CONTROL_1 0x400F1504\r
-#define MMCR_ACPI_0_PM1_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_1))\r
-\r
-#define ADDR_ACPI_0_PM1_CONTROL_2 0x400F1505\r
-#define MMCR_ACPI_0_PM1_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_2))\r
-\r
-#define ADDR_ACPI_0_PM2_CONTROL_1 0x400F1506\r
-#define MMCR_ACPI_0_PM2_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_1))\r
-\r
-#define ADDR_ACPI_0_PM2_CONTROL_2 0x400F1507\r
-#define MMCR_ACPI_0_PM2_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_2))\r
-\r
-#define ADDR_ACPI_0_PM1_EC_PM_STATUS 0x400F1510\r
-#define MMCR_ACPI_0_PM1_EC_PM_STATUS (*(VUINT8 *)(ADDR_ACPI_0_PM1_EC_PM_STATUS))\r
-\r
-/***************************************************************\r
-* EC GP-SPI\r
-***************************************************************/\r
-#define ADDR_EC_1_SPI_CLOCK_GENERATOR 0x40009498\r
-#define MMCR_EC_1_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_GENERATOR))\r
-\r
-#define ADDR_EC_1_SPI_CLOCK_CONTROL 0x40009494\r
-#define MMCR_EC_1_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_CONTROL))\r
-\r
-#define ADDR_EC_1_SPI_RX_DATA 0x40009490\r
-#define MMCR_EC_1_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_RX_DATA))\r
-\r
-#define ADDR_EC_1_SPI_TX_DATA 0x4000948C\r
-#define MMCR_EC_1_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_TX_DATA))\r
-\r
-#define ADDR_EC_1_SPI_STATUS 0x40009488\r
-#define MMCR_EC_1_SPI_STATUS (*(VUINT32 *)(ADDR_EC_1_SPI_STATUS))\r
-\r
-#define ADDR_EC_1_SPI_CONTROL 0x40009484\r
-#define MMCR_EC_1_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CONTROL))\r
-\r
-#define ADDR_EC_1_SPI_ENABLE 0x40009480\r
-#define MMCR_EC_1_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_1_SPI_ENABLE))\r
-\r
-#define ADDR_EC_0_SPI_ENABLE 0x40009400\r
-#define MMCR_EC_0_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_0_SPI_ENABLE))\r
-\r
-#define ADDR_EC_0_SPI_CONTROL 0x40009404\r
-#define MMCR_EC_0_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CONTROL))\r
-\r
-#define ADDR_EC_0_SPI_STATUS 0x40009408\r
-#define MMCR_EC_0_SPI_STATUS (*(VUINT32 *)(ADDR_EC_0_SPI_STATUS))\r
-\r
-#define ADDR_EC_0_SPI_TX_DATA 0x4000940C\r
-#define MMCR_EC_0_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_TX_DATA))\r
-\r
-#define ADDR_EC_0_SPI_RX_DATA 0x40009410\r
-#define MMCR_EC_0_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_RX_DATA))\r
-\r
-#define ADDR_EC_0_SPI_CLOCK_CONTROL 0x40009414\r
-#define MMCR_EC_0_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_CONTROL))\r
-\r
-#define ADDR_EC_0_SPI_CLOCK_GENERATOR 0x40009418\r
-#define MMCR_EC_0_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_GENERATOR))\r
-\r
-/***************************************************************\r
-* Mailbox Registers Interface\r
-***************************************************************/\r
-#define ADDR_MAILBOX_HOST_TO_EC_MAILBOX 0x400F2500\r
-#define MMCR_MAILBOX_HOST_TO_EC_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_HOST_TO_EC_MAILBOX))\r
-\r
-#define ADDR_MAILBOX_EC_TO_HOST_MAILBOX 0x400F2504\r
-#define MMCR_MAILBOX_EC_TO_HOST_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_EC_TO_HOST_MAILBOX))\r
-\r
-#define ADDR_MAILBOX_SMI_INTERRUPT_SOURCE 0x400F2508\r
-#define MMCR_MAILBOX_SMI_INTERRUPT_SOURCE (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_SOURCE))\r
-\r
-#define ADDR_MAILBOX_SMI_INTERRUPT_MASK 0x400F250C\r
-#define MMCR_MAILBOX_SMI_INTERRUPT_MASK (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_MASK))\r
-\r
-#define ADDR_MAILBOX_3_0 0x400F2510\r
-#define MMCR_MAILBOX_3_0 (*(VUINT32 *)(ADDR_MAILBOX_3_0))\r
-\r
-#define ADDR_MAILBOX_7_4 0x400F2514\r
-#define MMCR_MAILBOX_7_4 (*(VUINT32 *)(ADDR_MAILBOX_7_4))\r
-\r
-#define ADDR_MAILBOX_BH_8 0x400F2518\r
-#define MMCR_MAILBOX_BH_8 (*(VUINT32 *)(ADDR_MAILBOX_BH_8))\r
-\r
-#define ADDR_MAILBOX_FH_CH 0x400F251C\r
-#define MMCR_MAILBOX_FH_CH (*(VUINT32 *)(ADDR_MAILBOX_FH_CH))\r
-\r
-#define ADDR_MAILBOX_13H_10H 0x400F2520\r
-#define MMCR_MAILBOX_13H_10H (*(VUINT32 *)(ADDR_MAILBOX_13H_10H))\r
-\r
-#define ADDR_MAILBOX_17H_14H 0x400F2524\r
-#define MMCR_MAILBOX_17H_14H (*(VUINT32 *)(ADDR_MAILBOX_17H_14H))\r
-\r
-#define ADDR_MAILBOX_1BH_18H 0x400F2528\r
-#define MMCR_MAILBOX_1BH_18H (*(VUINT32 *)(ADDR_MAILBOX_1BH_18H))\r
-\r
-#define ADDR_MAILBOX_1FH_1CH 0x400F252C\r
-#define MMCR_MAILBOX_1FH_1CH (*(VUINT32 *)(ADDR_MAILBOX_1FH_1CH))\r
-\r
-/***************************************************************\r
-* Hibernation Timer\r
-***************************************************************/\r
-#define ADDR_HIBERNATION_0_HTIMER_X_PRELOAD 0x40009800\r
-#define MMCR_HIBERNATION_0_HTIMER_X_PRELOAD (*(VUINT16 *)(ADDR_HIBERNATION_0_HTIMER_X_PRELOAD))\r
-\r
-#define ADDR_HIBERNATION_0_TIMER_X_CONTROL 0x40009804\r
-#define MMCR_HIBERNATION_0_TIMER_X_CONTROL (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_CONTROL))\r
-\r
-#define ADDR_HIBERNATION_0_TIMER_X_COUNT 0x40009808\r
-#define MMCR_HIBERNATION_0_TIMER_X_COUNT (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_COUNT))\r
-\r
-/***************************************************************\r
-* UART\r
-***************************************************************/\r
-#define ADDR_M16C550A_UART_ACTIVATE 0x400F1F30\r
-#define MMCR_M16C550A_UART_ACTIVATE (*(VUINT8 *)(ADDR_M16C550A_UART_ACTIVATE))\r
-\r
-#define ADDR_M16C550A_UART_CONFIG_SELECT 0x400F1FF0\r
-#define MMCR_M16C550A_UART_CONFIG_SELECT (*(VUINT8 *)(ADDR_M16C550A_UART_CONFIG_SELECT))\r
-\r
-#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB 0x400F1D00\r
-#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB))\r
-\r
-#define ADDR_M16C550A_UART_RECEIVE_BUFFER 0x400F1D00\r
-#define MMCR_M16C550A_UART_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_RECEIVE_BUFFER))\r
-\r
-#define ADDR_M16C550A_UART_TRANSMIT_BUFFER 0x400F1D00\r
-#define MMCR_M16C550A_UART_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB 0x400F1D01\r
-#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB))\r
-\r
-#define ADDR_M16C550A_UART_INTERRUPT_ENABLE 0x400F1D01\r
-#define MMCR_M16C550A_UART_INTERRUPT_ENABLE (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_M16C550A_UART_FIFO_CONTROL 0x400F1D02\r
-#define MMCR_M16C550A_UART_FIFO_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_FIFO_CONTROL))\r
-\r
-#define ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION 0x400F1D02\r
-#define MMCR_M16C550A_UART_INTERRUPT_IDENTIFICATION (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION))\r
-\r
-#define ADDR_M16C550A_UART_LINE_CONTROL 0x400F1D03\r
-#define MMCR_M16C550A_UART_LINE_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_CONTROL))\r
-\r
-#define ADDR_M16C550A_UART_MODEM_CONTROL 0x400F1D04\r
-#define MMCR_M16C550A_UART_MODEM_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_CONTROL))\r
-\r
-#define ADDR_M16C550A_UART_LINE_STATUS 0x400F1D05\r
-#define MMCR_M16C550A_UART_LINE_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_STATUS))\r
-\r
-#define ADDR_M16C550A_UART_MODEM_STATUS 0x400F1D06\r
-#define MMCR_M16C550A_UART_MODEM_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_STATUS))\r
-\r
-#define ADDR_M16C550A_UART_SCRATCHPAD 0x400F1D07\r
-#define MMCR_M16C550A_UART_SCRATCHPAD (*(VUINT8 *)(ADDR_M16C550A_UART_SCRATCHPAD))\r
-\r
-/***************************************************************\r
-* TACH\r
-***************************************************************/\r
-#define ADDR_TACH_0_CONTROL 0x40006000\r
-#define MMCR_TACH_0_CONTROL (*(VUINT32 *)(ADDR_TACH_0_CONTROL))\r
-\r
-#define ADDR_TACH_0_STATUS 0x40006004\r
-#define MMCR_TACH_0_STATUS (*(VUINT32 *)(ADDR_TACH_0_STATUS))\r
-\r
-#define ADDR_TACH_0_HIGH_LIMIT 0x40006008\r
-#define MMCR_TACH_0_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_0_HIGH_LIMIT))\r
-\r
-#define ADDR_TACH_0_LOW_LIMIT 0x4000600C\r
-#define MMCR_TACH_0_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_0_LOW_LIMIT))\r
-\r
-#define ADDR_TACH_1_CONTROL 0x40006010\r
-#define MMCR_TACH_1_CONTROL (*(VUINT32 *)(ADDR_TACH_1_CONTROL))\r
-\r
-#define ADDR_TACH_1_STATUS 0x40006014\r
-#define MMCR_TACH_1_STATUS (*(VUINT32 *)(ADDR_TACH_1_STATUS))\r
-\r
-#define ADDR_TACH_1_HIGH_LIMIT 0x40006018\r
-#define MMCR_TACH_1_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_1_HIGH_LIMIT))\r
-\r
-#define ADDR_TACH_1_LOW_LIMIT 0x4000601C\r
-#define MMCR_TACH_1_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_1_LOW_LIMIT))\r
-\r
-/***************************************************************\r
-* Global Config Regs Basic\r
-***************************************************************/\r
-#define ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER 0x400FFF07\r
-#define MMCR_GLOBAL_LOGICAL_DEVICE_NUMBER (*(VUINT8 *)(ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER))\r
-\r
-#define ADDR_GLOBAL_DEVICE_ID 0x400FFF20\r
-#define MMCR_GLOBAL_DEVICE_ID (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_ID))\r
-\r
-#define ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED 0x400FFF21\r
-#define MMCR_GLOBAL_DEVICE_REVISION_HARD_WIRED (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED))\r
-\r
-#define ADDR_GLOBAL_GCR_BUILD 0x400FFF28\r
-#define MMCR_GLOBAL_GCR_BUILD (*(VUINT16 *)(ADDR_GLOBAL_GCR_BUILD))\r
-\r
-#define ADDR_GLOBAL_GCR_SCRATCH 0x400FFF2C\r
-#define MMCR_GLOBAL_GCR_SCRATCH (*(VUINT32 *)(ADDR_GLOBAL_GCR_SCRATCH))\r
-\r
-/***************************************************************\r
-* Trace FIFO Debug Port\r
-***************************************************************/\r
-#define ADDR_TRACE_DATA 0x40008C00\r
-#define MMCR_TRACE_DATA (*(VUINT32 *)(ADDR_TRACE_DATA))\r
-\r
-#define ADDR_TRACE_CONTROL 0x40008C04\r
-#define MMCR_TRACE_CONTROL (*(VUINT32 *)(ADDR_TRACE_CONTROL))\r
-\r
-/***************************************************************\r
-* STAP\r
-***************************************************************/\r
-#define ADDR_STAP_MESSAGE_OBF 0x40080000\r
-#define MMCR_STAP_MESSAGE_OBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_OBF))\r
-\r
-#define ADDR_STAP_MESSAGE_IBF 0x40080004\r
-#define MMCR_STAP_MESSAGE_IBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_IBF))\r
-\r
-#define ADDR_STAP_OBF_STATUS 0x40080008\r
-#define MMCR_STAP_OBF_STATUS (*(VUINT8 *)(ADDR_STAP_OBF_STATUS))\r
-\r
-#define ADDR_STAP_IBF_STATUS 0x40080009\r
-#define MMCR_STAP_IBF_STATUS (*(VUINT8 *)(ADDR_STAP_IBF_STATUS))\r
-\r
-#define ADDR_STAP_DBG_CTRL 0x4008000C\r
-#define MMCR_STAP_DBG_CTRL (*(VUINT8 *)(ADDR_STAP_DBG_CTRL))\r
-\r
-/***************************************************************\r
-* EMI\r
-***************************************************************/\r
-#define ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX 0x400F0100\r
-#define MMCR_IMAP_EMI_HOST_TO_EC_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX))\r
-\r
-#define ADDR_IMAP_EC_TO_HOST_MAILBOX 0x400F0101\r
-#define MMCR_IMAP_EC_TO_HOST_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EC_TO_HOST_MAILBOX))\r
-\r
-#define ADDR_IMAP_MEMORY_BASE_ADDRESS_0 0x400F0104\r
-#define MMCR_IMAP_MEMORY_BASE_ADDRESS_0 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_0))\r
-\r
-#define ADDR_IMAP_MEMORY_READ_LIMIT_0 0x400F0108\r
-#define MMCR_IMAP_MEMORY_READ_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_0))\r
-\r
-#define ADDR_IMAP_MEMORY_WRITE_LIMIT_0 0x400F010A\r
-#define MMCR_IMAP_MEMORY_WRITE_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_0))\r
-\r
-#define ADDR_IMAP_MEMORY_BASE_ADDRESS_1 0x400F010C\r
-#define MMCR_IMAP_MEMORY_BASE_ADDRESS_1 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_1))\r
-\r
-#define ADDR_IMAP_MEMORY_READ_LIMIT_1 0x400F0110\r
-#define MMCR_IMAP_MEMORY_READ_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_1))\r
-\r
-#define ADDR_IMAP_MEMORY_WRITE_LIMIT_1 0x400F0112\r
-#define MMCR_IMAP_MEMORY_WRITE_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_1))\r
-\r
-#define ADDR_IMAP_INTERRUPT_SET 0x400F0114\r
-#define MMCR_IMAP_INTERRUPT_SET (*(VUINT16 *)(ADDR_IMAP_INTERRUPT_SET))\r
-\r
-#define ADDR_IMAP_HOST_CLEAR_ENABLE 0x400F0116\r
-#define MMCR_IMAP_HOST_CLEAR_ENABLE (*(VUINT16 *)(ADDR_IMAP_HOST_CLEAR_ENABLE))\r
-\r
-/***************************************************************\r
-* Blinking/Breathing PWM\r
-***************************************************************/\r
-#define ADDR_LED_3_UPDATE_INTERVAL 0x4000BB10\r
-#define MMCR_LED_3_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_3_UPDATE_INTERVAL))\r
-\r
-#define ADDR_LED_3_UPDATE_STEPSIZE 0x4000BB0C\r
-#define MMCR_LED_3_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_3_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_3_DELAY 0x4000BB08\r
-#define MMCR_LED_3_DELAY (*(VUINT32 *)(ADDR_LED_3_DELAY))\r
-\r
-#define ADDR_LED_3_LIMITS 0x4000BB04\r
-#define MMCR_LED_3_LIMITS (*(VUINT32 *)(ADDR_LED_3_LIMITS))\r
-\r
-#define ADDR_LED_3_CONFIGURATION 0x4000BB00\r
-#define MMCR_LED_3_CONFIGURATION (*(VUINT32 *)(ADDR_LED_3_CONFIGURATION))\r
-\r
-#define ADDR_LED_2_UPDATE_INTERVAL 0x4000BA10\r
-#define MMCR_LED_2_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_2_UPDATE_INTERVAL))\r
-\r
-#define ADDR_LED_2_UPDATE_STEPSIZE 0x4000BA0C\r
-#define MMCR_LED_2_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_2_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_2_DELAY 0x4000BA08\r
-#define MMCR_LED_2_DELAY (*(VUINT32 *)(ADDR_LED_2_DELAY))\r
-\r
-#define ADDR_LED_2_LIMITS 0x4000BA04\r
-#define MMCR_LED_2_LIMITS (*(VUINT32 *)(ADDR_LED_2_LIMITS))\r
-\r
-#define ADDR_LED_2_CONFIGURATION 0x4000BA00\r
-#define MMCR_LED_2_CONFIGURATION (*(VUINT32 *)(ADDR_LED_2_CONFIGURATION))\r
-\r
-#define ADDR_LED_1_CONFIGURATION 0x4000B900\r
-#define MMCR_LED_1_CONFIGURATION (*(VUINT32 *)(ADDR_LED_1_CONFIGURATION))\r
-\r
-#define ADDR_LED_1_LIMITS 0x4000B904\r
-#define MMCR_LED_1_LIMITS (*(VUINT32 *)(ADDR_LED_1_LIMITS))\r
-\r
-#define ADDR_LED_1_DELAY 0x4000B908\r
-#define MMCR_LED_1_DELAY (*(VUINT32 *)(ADDR_LED_1_DELAY))\r
-\r
-#define ADDR_LED_1_UPDATE_STEPSIZE 0x4000B90C\r
-#define MMCR_LED_1_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_1_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_1_UPDATE_INTERVAL 0x4000B910\r
-#define MMCR_LED_1_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_1_UPDATE_INTERVAL))\r
-\r
-#define ADDR_LED_0_CONFIGURATION 0x4000B800\r
-#define MMCR_LED_0_CONFIGURATION (*(VUINT32 *)(ADDR_LED_0_CONFIGURATION))\r
-\r
-#define ADDR_LED_0_LIMITS 0x4000B804\r
-#define MMCR_LED_0_LIMITS (*(VUINT32 *)(ADDR_LED_0_LIMITS))\r
-\r
-#define ADDR_LED_0_DELAY 0x4000B808\r
-#define MMCR_LED_0_DELAY (*(VUINT32 *)(ADDR_LED_0_DELAY))\r
-\r
-#define ADDR_LED_0_UPDATE_STEPSIZE 0x4000B80C\r
-#define MMCR_LED_0_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_0_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_0_UPDATE_INTERVAL 0x4000B810\r
-#define MMCR_LED_0_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_0_UPDATE_INTERVAL))\r
-\r
-/***************************************************************\r
-* SMSC BC-Link Master\r
-***************************************************************/\r
-#define ADDR_BC_LINK_STATUS 0x4000BC00\r
-#define MMCR_BC_LINK_STATUS (*(VUINT8 *)(ADDR_BC_LINK_STATUS))\r
-\r
-#define ADDR_BC_LINK_ADDRESS 0x4000BC04\r
-#define MMCR_BC_LINK_ADDRESS (*(VUINT8 *)(ADDR_BC_LINK_ADDRESS))\r
-\r
-#define ADDR_BC_LINK_DATA 0x4000BC08\r
-#define MMCR_BC_LINK_DATA (*(VUINT8 *)(ADDR_BC_LINK_DATA))\r
-\r
-#define ADDR_BC_LINK_CLOCK_SELECT 0x4000BC0C\r
-#define MMCR_BC_LINK_CLOCK_SELECT (*(VUINT8 *)(ADDR_BC_LINK_CLOCK_SELECT))\r
-\r
-/***************************************************************\r
-* Basic Timer\r
-***************************************************************/\r
-#define ADDR_BASIC_0_TIMER_COUNT 0x40000C00\r
-#define MMCR_BASIC_0_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_0_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_0_TIMER_PRELOAD 0x40000C04\r
-#define MMCR_BASIC_0_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_0_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_0_TIMER_STATUS 0x40000C08\r
-#define MMCR_BASIC_0_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_0_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE 0x40000C0C\r
-#define MMCR_BASIC_0_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_0_TIMER_CONTROL 0x40000C10\r
-#define MMCR_BASIC_0_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_0_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_1_TIMER_COUNT 0x40000C20\r
-#define MMCR_BASIC_1_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_1_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_1_TIMER_PRELOAD 0x40000C24\r
-#define MMCR_BASIC_1_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_1_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_1_TIMER_STATUS 0x40000C28\r
-#define MMCR_BASIC_1_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_1_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE 0x40000C2C\r
-#define MMCR_BASIC_1_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_1_TIMER_CONTROL 0x40000C30\r
-#define MMCR_BASIC_1_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_1_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_2_TIMER_COUNT 0x40000C40\r
-#define MMCR_BASIC_2_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_2_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_2_TIMER_PRELOAD 0x40000C44\r
-#define MMCR_BASIC_2_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_2_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_2_TIMER_STATUS 0x40000C48\r
-#define MMCR_BASIC_2_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_2_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE 0x40000C4C\r
-#define MMCR_BASIC_2_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_2_TIMER_CONTROL 0x40000C50\r
-#define MMCR_BASIC_2_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_2_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_3_TIMER_COUNT 0x40000C60\r
-#define MMCR_BASIC_3_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_3_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_3_TIMER_PRELOAD 0x40000C64\r
-#define MMCR_BASIC_3_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_3_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_3_TIMER_STATUS 0x40000C68\r
-#define MMCR_BASIC_3_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_3_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE 0x40000C6C\r
-#define MMCR_BASIC_3_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_3_TIMER_CONTROL 0x40000C70\r
-#define MMCR_BASIC_3_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_3_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_4_TIMER_COUNT 0x40000C80\r
-#define MMCR_BASIC_4_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_4_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_4_TIMER_PRELOAD 0x40000C84\r
-#define MMCR_BASIC_4_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_4_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_4_TIMER_STATUS 0x40000C88\r
-#define MMCR_BASIC_4_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_4_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE 0x40000C8C\r
-#define MMCR_BASIC_4_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_4_TIMER_CONTROL 0x40000C90\r
-#define MMCR_BASIC_4_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_4_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_5_TIMER_COUNT 0x40000CA0\r
-#define MMCR_BASIC_5_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_5_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_5_TIMER_PRELOAD 0x40000CA4\r
-#define MMCR_BASIC_5_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_5_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_5_TIMER_STATUS 0x40000CA8\r
-#define MMCR_BASIC_5_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_5_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE 0x40000CAC\r
-#define MMCR_BASIC_5_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_5_TIMER_CONTROL 0x40000CB0\r
-#define MMCR_BASIC_5_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_5_TIMER_CONTROL))\r
-\r
-/***************************************************************\r
-* INTS\r
-***************************************************************/\r
-#define ADDR_EC_GIRQ8_SOURCE 0x4000C000\r
-#define MMCR_EC_GIRQ8_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ8_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ8_ENABLE_SET 0x4000C004\r
-#define MMCR_EC_GIRQ8_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ8_RESULT 0x4000C008\r
-#define MMCR_EC_GIRQ8_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ8_RESULT))\r
-\r
-#define ADDR_EC_GIRQ8_ENABLE_CLEAR 0x4000C00C\r
-#define MMCR_EC_GIRQ8_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ9_SOURCE 0x4000C014\r
-#define MMCR_EC_GIRQ9_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ9_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ9_ENABLE_SET 0x4000C018\r
-#define MMCR_EC_GIRQ9_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ9_RESULT 0x4000C01C\r
-#define MMCR_EC_GIRQ9_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ9_RESULT))\r
-\r
-#define ADDR_EC_GIRQ9_ENABLE_CLEAR 0x4000C020\r
-#define MMCR_EC_GIRQ9_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ10_SOURCE 0x4000C028\r
-#define MMCR_EC_GIRQ10_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ10_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ10_ENABLE_SET 0x4000C02C\r
-#define MMCR_EC_GIRQ10_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ10_RESULT 0x4000C030\r
-#define MMCR_EC_GIRQ10_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ10_RESULT))\r
-\r
-#define ADDR_EC_GIRQ10_ENABLE_CLEAR 0x4000C034\r
-#define MMCR_EC_GIRQ10_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ11_SOURCE 0x4000C03C\r
-#define MMCR_EC_GIRQ11_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ11_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ11_ENABLE_SET 0x4000C040\r
-#define MMCR_EC_GIRQ11_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ11_RESULT 0x4000C044\r
-#define MMCR_EC_GIRQ11_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ11_RESULT))\r
-\r
-#define ADDR_EC_GIRQ11_ENABLE_CLEAR 0x4000C048\r
-#define MMCR_EC_GIRQ11_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ12_SOURCE 0x4000C050\r
-#define MMCR_EC_GIRQ12_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ12_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ12_ENABLE_SET 0x4000C054\r
-#define MMCR_EC_GIRQ12_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ12_RESULT 0x4000C058\r
-#define MMCR_EC_GIRQ12_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ12_RESULT))\r
-\r
-#define ADDR_EC_GIRQ12_ENABLE_CLEAR 0x4000C05C\r
-#define MMCR_EC_GIRQ12_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ13_SOURCE 0x4000C064\r
-#define MMCR_EC_GIRQ13_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ13_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ13_ENABLE_SET 0x4000C068\r
-#define MMCR_EC_GIRQ13_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ13_RESULT 0x4000C06C\r
-#define MMCR_EC_GIRQ13_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ13_RESULT))\r
-\r
-#define ADDR_EC_GIRQ13_ENABLE_CLEAR 0x4000C070\r
-#define MMCR_EC_GIRQ13_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ14_SOURCE 0x4000C078\r
-#define MMCR_EC_GIRQ14_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ14_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ14_ENABLE_SET 0x4000C07C\r
-#define MMCR_EC_GIRQ14_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ14_RESULT 0x4000C080\r
-#define MMCR_EC_GIRQ14_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ14_RESULT))\r
-\r
-#define ADDR_EC_GIRQ14_ENABLE_CLEAR 0x4000C084\r
-#define MMCR_EC_GIRQ14_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ15_SOURCE 0x4000C08C\r
-#define MMCR_EC_GIRQ15_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ15_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ15_ENABLE_SET 0x4000C090\r
-#define MMCR_EC_GIRQ15_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ15_RESULT 0x4000C094\r
-#define MMCR_EC_GIRQ15_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ15_RESULT))\r
-\r
-#define ADDR_EC_GIRQ15_ENABLE_CLEAR 0x4000C098\r
-#define MMCR_EC_GIRQ15_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ16_SOURCE 0x4000C0A0\r
-#define MMCR_EC_GIRQ16_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ16_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ16_ENABLE_SET 0x4000C0A4\r
-#define MMCR_EC_GIRQ16_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ16_RESULT 0x4000C0A8\r
-#define MMCR_EC_GIRQ16_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ16_RESULT))\r
-\r
-#define ADDR_EC_GIRQ16_ENABLE_CLEAR 0x4000C0AC\r
-#define MMCR_EC_GIRQ16_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ17_SOURCE 0x4000C0B4\r
-#define MMCR_EC_GIRQ17_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ17_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ17_ENABLE_SET 0x4000C0B8\r
-#define MMCR_EC_GIRQ17_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ17_RESULT 0x4000C0BC\r
-#define MMCR_EC_GIRQ17_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ17_RESULT))\r
-\r
-#define ADDR_EC_GIRQ17_ENABLE_CLEAR 0x4000C0C0\r
-#define MMCR_EC_GIRQ17_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ18_SOURCE 0x4000C0C8\r
-#define MMCR_EC_GIRQ18_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ18_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ18_ENABLE_SET 0x4000C0CC\r
-#define MMCR_EC_GIRQ18_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ18_RESULT 0x4000C0D0\r
-#define MMCR_EC_GIRQ18_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ18_RESULT))\r
-\r
-#define ADDR_EC_GIRQ18_ENABLE_CLEAR 0x4000C0D4\r
-#define MMCR_EC_GIRQ18_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ19_SOURCE 0x4000C0DC\r
-#define MMCR_EC_GIRQ19_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ19_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ19_ENABLE_SET 0x4000C0E0\r
-#define MMCR_EC_GIRQ19_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ19_RESULT 0x4000C0E4\r
-#define MMCR_EC_GIRQ19_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ19_RESULT))\r
-\r
-#define ADDR_EC_GIRQ19_ENABLE_CLEAR 0x4000C0E8\r
-#define MMCR_EC_GIRQ19_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ20_SOURCE 0x4000C0F0\r
-#define MMCR_EC_GIRQ20_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ20_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ20_ENABLE_SET 0x4000C0F4\r
-#define MMCR_EC_GIRQ20_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ20_RESULT 0x4000C0F8\r
-#define MMCR_EC_GIRQ20_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ20_RESULT))\r
-\r
-#define ADDR_EC_GIRQ20_ENABLE_CLEAR 0x4000C0FC\r
-#define MMCR_EC_GIRQ20_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ21_SOURCE 0x4000C104\r
-#define MMCR_EC_GIRQ21_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ21_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ21_ENABLE_SET 0x4000C108\r
-#define MMCR_EC_GIRQ21_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ21_RESULT 0x4000C10C\r
-#define MMCR_EC_GIRQ21_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ21_RESULT))\r
-\r
-#define ADDR_EC_GIRQ21_ENABLE_CLEAR 0x4000C110\r
-#define MMCR_EC_GIRQ21_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ22_SOURCE 0x4000C118\r
-#define MMCR_EC_GIRQ22_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ22_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ22_ENABLE_SET 0x4000C11C\r
-#define MMCR_EC_GIRQ22_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ22_RESULT 0x4000C120\r
-#define MMCR_EC_GIRQ22_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ22_RESULT))\r
-\r
-#define ADDR_EC_GIRQ22_ENABLE_CLEAR 0x4000C124\r
-#define MMCR_EC_GIRQ22_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ23_SOURCE 0x4000C12C\r
-#define MMCR_EC_GIRQ23_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ23_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ23_ENABLE_SET 0x4000C130\r
-#define MMCR_EC_GIRQ23_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ23_RESULT 0x4000C134\r
-#define MMCR_EC_GIRQ23_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ23_RESULT))\r
-\r
-#define ADDR_EC_GIRQ23_ENABLE_CLEAR 0x4000C138\r
-#define MMCR_EC_GIRQ23_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_BLOCK_ENABLE_SET 0x4000C200\r
-#define MMCR_EC_BLOCK_ENABLE_SET (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_SET))\r
-\r
-#define ADDR_EC_BLOCK_ENABLE_CLEAR 0x4000C204\r
-#define MMCR_EC_BLOCK_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_BLOCK_IRQ_VECTOR 0x4000C208\r
-#define MMCR_EC_BLOCK_IRQ_VECTOR (*(VUINT32 *)(ADDR_EC_BLOCK_IRQ_VECTOR))\r
-\r
-/***************************************************************\r
-* RPM Fan Control\r
-***************************************************************/\r
-#define ADDR_RPM_FAN_SETTING 0x4000A000\r
-#define MMCR_RPM_FAN_SETTING (*(VUINT8 *)(ADDR_RPM_FAN_SETTING))\r
-\r
-#define ADDR_RPM_PWM_DIVIDE 0x4000A001\r
-#define MMCR_RPM_PWM_DIVIDE (*(VUINT8 *)(ADDR_RPM_PWM_DIVIDE))\r
-\r
-#define ADDR_RPM_FAN_CONFIGURATION_1 0x4000A002\r
-#define MMCR_RPM_FAN_CONFIGURATION_1 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_1))\r
-\r
-#define ADDR_RPM_FAN_CONFIGURATION_2 0x4000A003\r
-#define MMCR_RPM_FAN_CONFIGURATION_2 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_2))\r
-\r
-#define ADDR_RPM_GAIN 0x4000A005\r
-#define MMCR_RPM_GAIN (*(VUINT8 *)(ADDR_RPM_GAIN))\r
-\r
-#define ADDR_RPM_FAN_SPIN_UP_CONFIGURATION 0x4000A006\r
-#define MMCR_RPM_FAN_SPIN_UP_CONFIGURATION (*(VUINT8 *)(ADDR_RPM_FAN_SPIN_UP_CONFIGURATION))\r
-\r
-#define ADDR_RPM_FAN_STEP 0x4000A007\r
-#define MMCR_RPM_FAN_STEP (*(VUINT8 *)(ADDR_RPM_FAN_STEP))\r
-\r
-#define ADDR_RPM_FAN_MINIMUM_DRIVE 0x4000A008\r
-#define MMCR_RPM_FAN_MINIMUM_DRIVE (*(VUINT8 *)(ADDR_RPM_FAN_MINIMUM_DRIVE))\r
-\r
-#define ADDR_RPM_VALID_TACH_COUNT 0x4000A009\r
-#define MMCR_RPM_VALID_TACH_COUNT (*(VUINT8 *)(ADDR_RPM_VALID_TACH_COUNT))\r
-\r
-#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE 0x4000A00A\r
-#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE))\r
-\r
-#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE 0x4000A00B\r
-#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE))\r
-\r
-#define ADDR_RPM_TACH_TARGET_LOW_BYTE 0x4000A00C\r
-#define MMCR_RPM_TACH_TARGET_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_LOW_BYTE))\r
-\r
-#define ADDR_RPM_TACH_TARGET_HIGH_BYTE 0x4000A00D\r
-#define MMCR_RPM_TACH_TARGET_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_HIGH_BYTE))\r
-\r
-#define ADDR_RPM_TACH_READING_LOW_BYTE 0x4000A00E\r
-#define MMCR_RPM_TACH_READING_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_LOW_BYTE))\r
-\r
-#define ADDR_RPM_TACH_READING_HIGH_BYTE 0x4000A00F\r
-#define MMCR_RPM_TACH_READING_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_HIGH_BYTE))\r
-\r
-#define ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY 0x4000A010\r
-#define MMCR_RPM_PWM_DRIVER_BASE_FREQUENCY (*(VUINT8 *)(ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY))\r
-\r
-#define ADDR_RPM_FAN_STATUS 0x4000A011\r
-#define MMCR_RPM_FAN_STATUS (*(VUINT8 *)(ADDR_RPM_FAN_STATUS))\r
-\r
-#define ADDR_RPM_FAN_TEST 0x4000A014\r
-#define MMCR_RPM_FAN_TEST (*(VUINT8 *)(ADDR_RPM_FAN_TEST))\r
-\r
-#define ADDR_RPM_FAN_TEST1 0x4000A015\r
-#define MMCR_RPM_FAN_TEST1 (*(VUINT8 *)(ADDR_RPM_FAN_TEST1))\r
-\r
-#define ADDR_RPM_FAN_TEST2 0x4000A016\r
-#define MMCR_RPM_FAN_TEST2 (*(VUINT8 *)(ADDR_RPM_FAN_TEST2))\r
-\r
-#define ADDR_RPM_FAN_TEST3 0x4000A017\r
-#define MMCR_RPM_FAN_TEST3 (*(VUINT8 *)(ADDR_RPM_FAN_TEST3))\r
-\r
-/***************************************************************\r
-* V2P (HP ckt#1) 32bit_aligned\r
-***************************************************************/\r
-#define ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY 0x40007C80\r
-#define MMCR_V2P_ADC2PWM_OUTPUT_FREQUENCY (*(VUINT32 *)(ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY))\r
-\r
-#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW 0x40007C84\r
-#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW))\r
-\r
-#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH 0x40007C88\r
-#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH))\r
-\r
-#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA 0x40007C8C\r
-#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA))\r
-\r
-#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS 0x40007C90\r
-#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_STATUS (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS))\r
-\r
-#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 0x40007C94\r
-#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1))\r
-\r
-#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 0x40007C98\r
-#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2))\r
-\r
-#define ADDR_V2P_ADC2PWM_CONTROL 0x40007C9C\r
-#define MMCR_V2P_ADC2PWM_CONTROL (*(VUINT32 *)(ADDR_V2P_ADC2PWM_CONTROL))\r
-\r
-#define ADDR_V2P_LPF_CUT_OFF_FREQUENCY 0x40007CA0\r
-#define MMCR_V2P_LPF_CUT_OFF_FREQUENCY (*(VUINT32 *)(ADDR_V2P_LPF_CUT_OFF_FREQUENCY))\r
-\r
-#define ADDR_V2P_TEST 0x40007CA4\r
-#define MMCR_V2P_TEST (*(VUINT32 *)(ADDR_V2P_TEST))\r
-\r
-#define ADDR_V2P_NOTICE_DATA 0x40007CA8\r
-#define MMCR_V2P_NOTICE_DATA (*(VUINT32 *)(ADDR_V2P_NOTICE_DATA))\r
-\r
-#define ADDR_V2P_TEST_DATA 0x40007CAC\r
-#define MMCR_V2P_TEST_DATA (*(VUINT32 *)(ADDR_V2P_TEST_DATA))\r
-\r
-#define ADDR_V2P_COUNTER_START 0x40007CB0\r
-#define MMCR_V2P_COUNTER_START (*(VUINT32 *)(ADDR_V2P_COUNTER_START))\r
-\r
-#define ADDR_V2P_HYSTERESIS 0x40007CB4\r
-#define MMCR_V2P_HYSTERESIS (*(VUINT32 *)(ADDR_V2P_HYSTERESIS))\r
-\r
-#define ADDR_V2P_BIAS 0x40007CB8\r
-#define MMCR_V2P_BIAS (*(VUINT32 *)(ADDR_V2P_BIAS))\r
-\r
-#define ADDR_V2P_INTERRUPT_CONTROL 0x40007CBC\r
-#define MMCR_V2P_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_V2P_INTERRUPT_CONTROL))\r
-\r
-/***************************************************************\r
-* VBAT_REGS (1322)\r
-***************************************************************/\r
-#define ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS 0x4000A400\r
-#define MMCR_VBAT_POWER_FAIL_AND_RESET_STATUS (*(VUINT8 *)(ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS))\r
-\r
-#define ADDR_VBAT_CONTROL 0x4000A404\r
-#define MMCR_VBAT_CONTROL (*(VUINT8 *)(ADDR_VBAT_CONTROL))\r
-\r
-#define ADDR_VBAT_CLOCK_ENABLE 0x4000A408\r
-#define MMCR_VBAT_CLOCK_ENABLE (*(VUINT8 *)(ADDR_VBAT_CLOCK_ENABLE))\r
-\r
-/***************************************************************\r
-* EC_REG_BANK (1322)\r
-***************************************************************/\r
-#define ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS 0x4000FC04\r
-#define MMCR_EC_REG_BANK_AHB_ERROR_ADDRESS (*(VUINT32 *)(ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS))\r
-\r
-#define ADDR_EC_REG_BANK_INPUT_MUX0 0x4000FC08\r
-#define MMCR_EC_REG_BANK_INPUT_MUX0 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX0))\r
-\r
-#define ADDR_EC_REG_BANK_INPUT_MUX1 0x4000FC0C\r
-#define MMCR_EC_REG_BANK_INPUT_MUX1 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX1))\r
-\r
-#define ADDR_EC_REG_BANK_ID 0x4000FC10\r
-#define MMCR_EC_REG_BANK_ID (*(VUINT8 *)(ADDR_EC_REG_BANK_ID))\r
-\r
-#define ADDR_EC_REG_BANK_AHB_ERROR_CONTROL 0x4000FC14\r
-#define MMCR_EC_REG_BANK_AHB_ERROR_CONTROL (*(VUINT8 *)(ADDR_EC_REG_BANK_AHB_ERROR_CONTROL))\r
-\r
-#define ADDR_EC_REG_BANK_INTERRUPT_CONTROL 0x4000FC18\r
-#define MMCR_EC_REG_BANK_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_INTERRUPT_CONTROL))\r
-\r
-#define ADDR_EC_REG_BANK_ETM_TRACE 0x4000FC1C\r
-#define MMCR_EC_REG_BANK_ETM_TRACE (*(VUINT32 *)(ADDR_EC_REG_BANK_ETM_TRACE))\r
-\r
-#define ADDR_EC_REG_BANK_JTAG_ENABLE 0x4000FC20\r
-#define MMCR_EC_REG_BANK_JTAG_ENABLE (*(VUINT32 *)(ADDR_EC_REG_BANK_JTAG_ENABLE))\r
-\r
-#define ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK 0x4000FC24\r
-#define MMCR_EC_REG_BANK_PRIVATE_KEY_LOCK (*(VUINT32 *)(ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK))\r
-\r
-#define ADDR_EC_REG_BANK_WDT_COUNT 0x4000FC28\r
-#define MMCR_EC_REG_BANK_WDT_COUNT (*(VUINT32 *)(ADDR_EC_REG_BANK_WDT_COUNT))\r
-\r
-#define ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL 0x4000FC2C\r
-#define MMCR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL))\r
-\r
-#define ADDR_EC_REG_BANK_ADC_VREF_TRIM 0x4000FC30\r
-#define MMCR_EC_REG_BANK_ADC_VREF_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_TRIM))\r
-\r
-#define ADDR_EC_REG_BANK_REGULATOR_TRIM 0x4000FC34\r
-#define MMCR_EC_REG_BANK_REGULATOR_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_REGULATOR_TRIM))\r
-\r
-#define ADDR_EC_REG_BANK_ADC_VREF_PD 0x4000FC38\r
-#define MMCR_EC_REG_BANK_ADC_VREF_PD (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_PD))\r
-\r
-#define ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST 0x4000FC3C\r
-#define MMCR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST))\r
-\r
-#define ADDR_EC_REG_BANK_MISC_TRIM 0x4000FC40\r
-#define MMCR_EC_REG_BANK_MISC_TRIM (*(VUINT8 *)(ADDR_EC_REG_BANK_MISC_TRIM))\r
-\r
-/***************************************************************\r
-* PCR\r
-***************************************************************/\r
-#define ADDR_PCR_CHIP_SLEEP_ENABLE 0x40080100\r
-#define MMCR_PCR_CHIP_SLEEP_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_SLEEP_ENABLE))\r
-\r
-#define ADDR_PCR_CHIP_CLOCK_REQUIRED 0x40080104\r
-#define MMCR_PCR_CHIP_CLOCK_REQUIRED (*(VUINT32 *)(ADDR_PCR_CHIP_CLOCK_REQUIRED))\r
-\r
-#define ADDR_PCR_EC_SLEEP_ENABLES 0x40080108\r
-#define MMCR_PCR_EC_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLES))\r
-\r
-#define ADDR_PCR_EC_CLOCK_REQUIRED_STATUS 0x4008010C\r
-#define MMCR_PCR_EC_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_STATUS))\r
-\r
-#define ADDR_PCR_HOST_SLEEP_ENABLES 0x40080110\r
-#define MMCR_PCR_HOST_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_HOST_SLEEP_ENABLES))\r
-\r
-#define ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS 0x40080114\r
-#define MMCR_PCR_HOST_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS))\r
-\r
-#define ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 0x40080118\r
-#define MMCR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 (*(VUINT32 *)(ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0))\r
-\r
-#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120\r
-#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))\r
-\r
-#define ADDR_PCR_EC_SLEEP_ENABLE_2 0x40080124\r
-#define MMCR_PCR_EC_SLEEP_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLE_2))\r
-\r
-#define ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS 0x40080128\r
-#define MMCR_PCR_EC_CLOCK_REQUIRED_2_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS))\r
-\r
-#define ADDR_PCR_SLOW_CLOCK_CONTROL 0x4008012C\r
-#define MMCR_PCR_SLOW_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_SLOW_CLOCK_CONTROL))\r
-\r
-#define ADDR_PCR_OSCILLATOR_ID 0x40080130\r
-#define MMCR_PCR_OSCILLATOR_ID (*(VUINT32 *)(ADDR_PCR_OSCILLATOR_ID))\r
-\r
-#define ADDR_PCR_CHIP_RESET_ENABLE 0x40080138\r
-#define MMCR_PCR_CHIP_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_RESET_ENABLE))\r
-\r
-#define ADDR_PCR_HOST_RESET_ENABLE 0x4008013C\r
-#define MMCR_PCR_HOST_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_HOST_RESET_ENABLE))\r
-\r
-#define ADDR_PCR_EC_RESET_ENABLE 0x40080140\r
-#define MMCR_PCR_EC_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE))\r
-\r
-#define ADDR_PCR_EC_RESET_ENABLE_2 0x40080144\r
-#define MMCR_PCR_EC_RESET_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE_2))\r
-\r
-#define ADDR_PCR_CLOCK_RESET_CONTROL 0x40080148\r
-#define MMCR_PCR_CLOCK_RESET_CONTROL (*(VUINT32 *)(ADDR_PCR_CLOCK_RESET_CONTROL))\r
-\r
-/***************************************************************\r
-* Public Key Crypto Engine\r
-***************************************************************/\r
-#define ADDR_PUBLIC_PK_CONFIGREG 0x4000BD00\r
-#define MMCR_PUBLIC_PK_CONFIGREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONFIGREG))\r
-\r
-#define ADDR_PUBLIC_PK_COMMANDREG 0x4000BD04\r
-#define MMCR_PUBLIC_PK_COMMANDREG (*(VUINT32 *)(ADDR_PUBLIC_PK_COMMANDREG))\r
-\r
-#define ADDR_PUBLIC_PK_CONTROLREG 0x4000BD08\r
-#define MMCR_PUBLIC_PK_CONTROLREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONTROLREG))\r
-\r
-#define ADDR_PUBLIC_PK_STATUSREG 0x4000BD0C\r
-#define MMCR_PUBLIC_PK_STATUSREG (*(VUINT32 *)(ADDR_PUBLIC_PK_STATUSREG))\r
-\r
-#define ADDR_PUBLIC_PK_VERSIONREG 0x4000BD10\r
-#define MMCR_PUBLIC_PK_VERSIONREG (*(VUINT32 *)(ADDR_PUBLIC_PK_VERSIONREG))\r
-\r
-#define ADDR_PUBLIC_PK_LOADMICROCODEREG 0x4000BD14\r
-#define MMCR_PUBLIC_PK_LOADMICROCODEREG (*(VUINT32 *)(ADDR_PUBLIC_PK_LOADMICROCODEREG))\r
-\r
-/***************************************************************\r
-* Non Deterministic Random Number Generator\r
-***************************************************************/\r
-#define ADDR_NON_CONTROLREG 0x4000BE00\r
-#define MMCR_NON_CONTROLREG (*(VUINT32 *)(ADDR_NON_CONTROLREG))\r
-\r
-#define ADDR_NON_FIFOLEVELREG 0x4000BE04\r
-#define MMCR_NON_FIFOLEVELREG (*(VUINT32 *)(ADDR_NON_FIFOLEVELREG))\r
-\r
-#define ADDR_NON_VERSIONREG 0x4000BE08\r
-#define MMCR_NON_VERSIONREG (*(VUINT32 *)(ADDR_NON_VERSIONREG))\r
-\r
-/***************************************************************\r
-* RTC\r
-***************************************************************/\r
-#define ADDR_RTC_SECONDS 0x400F2800\r
-#define MMCR_RTC_SECONDS (*(VUINT8 *)(ADDR_RTC_SECONDS))\r
-\r
-#define ADDR_RTC_SECONDS_ALARM 0x400F2801\r
-#define MMCR_RTC_SECONDS_ALARM (*(VUINT8 *)(ADDR_RTC_SECONDS_ALARM))\r
-\r
-#define ADDR_RTC_MINUTES 0x400F2802\r
-#define MMCR_RTC_MINUTES (*(VUINT8 *)(ADDR_RTC_MINUTES))\r
-\r
-#define ADDR_RTC_MINUTES_ALARM 0x400F2803\r
-#define MMCR_RTC_MINUTES_ALARM (*(VUINT8 *)(ADDR_RTC_MINUTES_ALARM))\r
-\r
-#define ADDR_RTC_HOURS 0x400F2804\r
-#define MMCR_RTC_HOURS (*(VUINT8 *)(ADDR_RTC_HOURS))\r
-\r
-#define ADDR_RTC_HOURS_ALARM 0x400F2805\r
-#define MMCR_RTC_HOURS_ALARM (*(VUINT8 *)(ADDR_RTC_HOURS_ALARM))\r
-\r
-#define ADDR_RTC_DAY_OF_WEEK 0x400F2806\r
-#define MMCR_RTC_DAY_OF_WEEK (*(VUINT8 *)(ADDR_RTC_DAY_OF_WEEK))\r
-\r
-#define ADDR_RTC_DAY_OF_MONTH 0x400F2807\r
-#define MMCR_RTC_DAY_OF_MONTH (*(VUINT8 *)(ADDR_RTC_DAY_OF_MONTH))\r
-\r
-#define ADDR_RTC_MONTH 0x400F2808\r
-#define MMCR_RTC_MONTH (*(VUINT8 *)(ADDR_RTC_MONTH))\r
-\r
-#define ADDR_RTC_YEAR 0x400F2809\r
-#define MMCR_RTC_YEAR (*(VUINT8 *)(ADDR_RTC_YEAR))\r
-\r
-#define ADDR_RTC_A 0x400F280A\r
-#define MMCR_RTC_A (*(VUINT8 *)(ADDR_RTC_A))\r
-\r
-#define ADDR_RTC_B 0x400F280B\r
-#define MMCR_RTC_B (*(VUINT8 *)(ADDR_RTC_B))\r
-\r
-#define ADDR_RTC_C 0x400F280C\r
-#define MMCR_RTC_C (*(VUINT8 *)(ADDR_RTC_C))\r
-\r
-#define ADDR_RTC_D 0x400F280D\r
-#define MMCR_RTC_D (*(VUINT8 *)(ADDR_RTC_D))\r
-\r
-#define ADDR_RTC_CONTROL 0x400F2810\r
-#define MMCR_RTC_CONTROL (*(VUINT8 *)(ADDR_RTC_CONTROL))\r
-\r
-#define ADDR_RTC_WEEK_ALARM 0x400F2814\r
-#define MMCR_RTC_WEEK_ALARM (*(VUINT8 *)(ADDR_RTC_WEEK_ALARM))\r
-\r
-#define ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD 0x400F2818\r
-#define MMCR_RTC_DAYLIGHT_SAVINGS_FORWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD))\r
-\r
-#define ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD 0x400F281C\r
-#define MMCR_RTC_DAYLIGHT_SAVINGS_BACKWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD))\r
-\r
-#define ADDR_RTC_TEST_MODE 0x400F2820\r
-#define MMCR_RTC_TEST_MODE (*(VUINT8 *)(ADDR_RTC_TEST_MODE))\r
-\r
-/***************************************************************\r
-* Analog to Digital Converter (ADC)\r
-***************************************************************/\r
-#define ADDR_ADC_CONTROL 0x40007C00\r
-#define MMCR_ADC_CONTROL (*(VUINT32 *)(ADDR_ADC_CONTROL))\r
-\r
-#define ADDR_ADC_DELAY 0x40007C04\r
-#define MMCR_ADC_DELAY (*(VUINT32 *)(ADDR_ADC_DELAY))\r
-\r
-#define ADDR_ADC_STATUS 0x40007C08\r
-#define MMCR_ADC_STATUS (*(VUINT32 *)(ADDR_ADC_STATUS))\r
-\r
-#define ADDR_ADC_SINGLE 0x40007C0C\r
-#define MMCR_ADC_SINGLE (*(VUINT32 *)(ADDR_ADC_SINGLE))\r
-\r
-#define ADDR_ADC_REPEAT 0x40007C10\r
-#define MMCR_ADC_REPEAT (*(VUINT32 *)(ADDR_ADC_REPEAT))\r
-\r
-#define ADDR_ADC_CHANNEL_0_READINGS 0x40007C14\r
-#define MMCR_ADC_CHANNEL_0_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_0_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_1_READINGS 0x40007C18\r
-#define MMCR_ADC_CHANNEL_1_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_1_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_2_READINGS 0x40007C1C\r
-#define MMCR_ADC_CHANNEL_2_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_2_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_3_READINGS 0x40007C20\r
-#define MMCR_ADC_CHANNEL_3_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_3_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_4_READINGS 0x40007C24\r
-#define MMCR_ADC_CHANNEL_4_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_4_READINGS))\r
-\r
-#define ADDR_ADC_DEBUG_FPGA_TEST_MODE 0x40007C54\r
-#define MMCR_ADC_DEBUG_FPGA_TEST_MODE (*(VUINT32 *)(ADDR_ADC_DEBUG_FPGA_TEST_MODE))\r
-\r
-#define ADDR_ADC_TEST 0x40007C78\r
-#define MMCR_ADC_TEST (*(VUINT32 *)(ADDR_ADC_TEST))\r
-\r
-#define ADDR_ADC_CONFIGURATION 0x40007C7C\r
-#define MMCR_ADC_CONFIGURATION (*(VUINT32 *)(ADDR_ADC_CONFIGURATION))\r
-\r
-/***************************************************************\r
-* eFUSE\r
-***************************************************************/\r
-#define ADDR_EFUSE_CONTROL 0x40082000\r
-#define MMCR_EFUSE_CONTROL (*(VUINT8 *)(ADDR_EFUSE_CONTROL))\r
-\r
-#define ADDR_EFUSE_MANUAL_CONTROL 0x40082004\r
-#define MMCR_EFUSE_MANUAL_CONTROL (*(VUINT8 *)(ADDR_EFUSE_MANUAL_CONTROL))\r
-\r
-#define ADDR_EFUSE_MANUAL_MODE_ADDRESS 0x40082006\r
-#define MMCR_EFUSE_MANUAL_MODE_ADDRESS (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_ADDRESS))\r
-\r
-#define ADDR_EFUSE_MANUAL_MODE_DATA 0x4008200C\r
-#define MMCR_EFUSE_MANUAL_MODE_DATA (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_DATA))\r
-\r
-/***************************************************************\r
-* AES Crypto Engine & Hash Function\r
-***************************************************************/\r
-#define ADDR_AES_CONFIGREG 0x4000D200\r
-#define MMCR_AES_CONFIGREG (*(VUINT32 *)(ADDR_AES_CONFIGREG))\r
-\r
-#define ADDR_AES_COMMANDREG 0x4000D204\r
-#define MMCR_AES_COMMANDREG (*(VUINT32 *)(ADDR_AES_COMMANDREG))\r
-\r
-#define ADDR_AES_CONTROLREG 0x4000D208\r
-#define MMCR_AES_CONTROLREG (*(VUINT32 *)(ADDR_AES_CONTROLREG))\r
-\r
-#define ADDR_AES_STATUSREG 0x4000D20C\r
-#define MMCR_AES_STATUSREG (*(VUINT32 *)(ADDR_AES_STATUSREG))\r
-\r
-#define ADDR_AES_VERSIONREG 0x4000D210\r
-#define MMCR_AES_VERSIONREG (*(VUINT32 *)(ADDR_AES_VERSIONREG))\r
-\r
-#define ADDR_AES_NBHEADERREG 0x4000D214\r
-#define MMCR_AES_NBHEADERREG (*(VUINT32 *)(ADDR_AES_NBHEADERREG))\r
-\r
-#define ADDR_AES_LASTHEADERREG 0x4000D218\r
-#define MMCR_AES_LASTHEADERREG (*(VUINT32 *)(ADDR_AES_LASTHEADERREG))\r
-\r
-#define ADDR_AES_NBBLOCKREG 0x4000D21C\r
-#define MMCR_AES_NBBLOCKREG (*(VUINT32 *)(ADDR_AES_NBBLOCKREG))\r
-\r
-#define ADDR_AES_LASTBLOCKREG 0x4000D220\r
-#define MMCR_AES_LASTBLOCKREG (*(VUINT32 *)(ADDR_AES_LASTBLOCKREG))\r
-\r
-#define ADDR_AES_DMAINREG 0x4000D224\r
-#define MMCR_AES_DMAINREG (*(VUINT32 *)(ADDR_AES_DMAINREG))\r
-\r
-#define ADDR_AES_DMAOUTREG 0x4000D228\r
-#define MMCR_AES_DMAOUTREG (*(VUINT32 *)(ADDR_AES_DMAOUTREG))\r
-\r
-#define ADDR_AES_SHAMODE_REGISTER 0x4000D000\r
-#define MMCR_AES_SHAMODE_REGISTER (*(VUINT32 *)(ADDR_AES_SHAMODE_REGISTER))\r
-\r
-#define ADDR_AES_NBBLOCK_REGISTER 0x4000D004\r
-#define MMCR_AES_NBBLOCK_REGISTER (*(VUINT32 *)(ADDR_AES_NBBLOCK_REGISTER))\r
-\r
-#define ADDR_AES_CONTROL 0x4000D008\r
-#define MMCR_AES_CONTROL (*(VUINT32 *)(ADDR_AES_CONTROL))\r
-\r
-#define ADDR_AES_STATUS 0x4000D00C\r
-#define MMCR_AES_STATUS (*(VUINT32 *)(ADDR_AES_STATUS))\r
-\r
-#define ADDR_AES_VERSION 0x4000D010\r
-#define MMCR_AES_VERSION (*(VUINT32 *)(ADDR_AES_VERSION))\r
-\r
-#define ADDR_AES_GENERICVALUE_REGISTER 0x4000D014\r
-#define MMCR_AES_GENERICVALUE_REGISTER (*(VUINT32 *)(ADDR_AES_GENERICVALUE_REGISTER))\r
-\r
-#define ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS 0x4000D018\r
-#define MMCR_AES_INITIAL_HASH_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS))\r
-\r
-#define ADDR_AES_DATA_SOURCE_ADDRESS 0x4000D01C\r
-#define MMCR_AES_DATA_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_DATA_SOURCE_ADDRESS))\r
-\r
-#define ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS 0x4000D020\r
-#define MMCR_AES_HASH_RESULT_DESTINATION_ADDRESS (*(VUINT32 *)(ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS))\r
-\r
-/***************************************************************\r
-* LPC\r
-***************************************************************/\r
-#define ADDR_LPC_ACTIVATE 0x400F3330\r
-#define MMCR_LPC_ACTIVATE (*(VUINT8 *)(ADDR_LPC_ACTIVATE))\r
-\r
-#define ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION 0x400F3340\r
-#define MMCR_LPC_SIRQ0_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION 0x400F3341\r
-#define MMCR_LPC_SIRQ1_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION 0x400F3342\r
-#define MMCR_LPC_SIRQ2_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION 0x400F3343\r
-#define MMCR_LPC_SIRQ3_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION 0x400F3344\r
-#define MMCR_LPC_SIRQ4_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION 0x400F3345\r
-#define MMCR_LPC_SIRQ5_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION 0x400F3346\r
-#define MMCR_LPC_SIRQ6_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION 0x400F3347\r
-#define MMCR_LPC_SIRQ7_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION 0x400F3348\r
-#define MMCR_LPC_SIRQ8_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION 0x400F3349\r
-#define MMCR_LPC_SIRQ9_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION 0x400F334A\r
-#define MMCR_LPC_SIRQ10_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION 0x400F334B\r
-#define MMCR_LPC_SIRQ11_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION 0x400F334C\r
-#define MMCR_LPC_SIRQ12_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION 0x400F334D\r
-#define MMCR_LPC_SIRQ13_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION 0x400F334E\r
-#define MMCR_LPC_SIRQ14_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION 0x400F334F\r
-#define MMCR_LPC_SIRQ15_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_INTERFACE_BAR 0x400F3360\r
-#define MMCR_LPC_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_EM_INTERFACE_0_BAR 0x400F3364\r
-#define MMCR_LPC_EM_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_EM_INTERFACE_0_BAR))\r
-\r
-#define ADDR_LPC_UART_0_BAR 0x400F3368\r
-#define MMCR_LPC_UART_0_BAR (*(VUINT32 *)(ADDR_LPC_UART_0_BAR))\r
-\r
-#define ADDR_LPC_KEYBOARD_CONTROLLER_BAR 0x400F3378\r
-#define MMCR_LPC_KEYBOARD_CONTROLLER_BAR (*(VUINT32 *)(ADDR_LPC_KEYBOARD_CONTROLLER_BAR))\r
-\r
-#define ADDR_LPC_ACPI_EC_INTERFACE_0_BAR 0x400F3388\r
-#define MMCR_LPC_ACPI_EC_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_0_BAR))\r
-\r
-#define ADDR_LPC_ACPI_EC_INTERFACE_1_BAR 0x400F338C\r
-#define MMCR_LPC_ACPI_EC_INTERFACE_1_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_1_BAR))\r
-\r
-#define ADDR_LPC_ACPI_PM1_INTERFACE_BAR 0x400F3390\r
-#define MMCR_LPC_ACPI_PM1_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_PM1_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR 0x400F3394\r
-#define MMCR_LPC_LEGACY_GATEA20_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_MAILBOXS_INTERFACE_BAR 0x400F3398\r
-#define MMCR_LPC_MAILBOXS_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_MAILBOXS_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_BUS_MONITOR 0x400F3104\r
-#define MMCR_LPC_BUS_MONITOR (*(VUINT32 *)(ADDR_LPC_BUS_MONITOR))\r
-\r
-#define ADDR_LPC_HOST_BUS_ERROR 0x400F3108\r
-#define MMCR_LPC_HOST_BUS_ERROR (*(VUINT32 *)(ADDR_LPC_HOST_BUS_ERROR))\r
-\r
-#define ADDR_LPC_EC_SERIRQ 0x400F310C\r
-#define MMCR_LPC_EC_SERIRQ (*(VUINT32 *)(ADDR_LPC_EC_SERIRQ))\r
-\r
-#define ADDR_LPC_EC_CLOCK_CONTROL 0x400F3110\r
-#define MMCR_LPC_EC_CLOCK_CONTROL (*(VUINT32 *)(ADDR_LPC_EC_CLOCK_CONTROL))\r
-\r
-#define ADDR_LPC_BAR_INHIBIT 0x400F3120\r
-#define MMCR_LPC_BAR_INHIBIT (*(VUINT32 *)(ADDR_LPC_BAR_INHIBIT))\r
-\r
-#define ADDR_LPC_BAR_INIT 0x400F3130\r
-#define MMCR_LPC_BAR_INIT (*(VUINT16 *)(ADDR_LPC_BAR_INIT))\r
-\r
-#define ADDR_LPC_MEMORY_HOST_CONFIGURATION 0x400F31FC\r
-#define MMCR_LPC_MEMORY_HOST_CONFIGURATION (*(VUINT32 *)(ADDR_LPC_MEMORY_HOST_CONFIGURATION))\r
-\r
-/***************************************************************\r
-* GPIO\r
-***************************************************************/\r
-#define ADDR_GPIO000_PIN_CONTROL 0x40081000\r
-#define MMCR_GPIO000_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO001_PIN_CONTROL 0x40081004\r
-#define MMCR_GPIO001_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO002_PIN_CONTROL 0x40081008\r
-#define MMCR_GPIO002_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO003_PIN_CONTROL 0x4008100C\r
-#define MMCR_GPIO003_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO004_PIN_CONTROL 0x40081010\r
-#define MMCR_GPIO004_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO005_PIN_CONTROL 0x40081014\r
-#define MMCR_GPIO005_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO006_PIN_CONTROL 0x40081018\r
-#define MMCR_GPIO006_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO007_PIN_CONTROL 0x4008101C\r
-#define MMCR_GPIO007_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO010_PIN_CONTROL 0x40081020\r
-#define MMCR_GPIO010_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO011_PIN_CONTROL 0x40081024\r
-#define MMCR_GPIO011_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO012_PIN_CONTROL 0x40081028\r
-#define MMCR_GPIO012_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO013_PIN_CONTROL 0x4008102C\r
-#define MMCR_GPIO013_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO014_PIN_CONTROL 0x40081030\r
-#define MMCR_GPIO014_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO015_PIN_CONTROL 0x40081034\r
-#define MMCR_GPIO015_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO016_PIN_CONTROL 0x40081038\r
-#define MMCR_GPIO016_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO017_PIN_CONTROL 0x4008103C\r
-#define MMCR_GPIO017_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO020_PIN_CONTROL 0x40081040\r
-#define MMCR_GPIO020_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO021_PIN_CONTROL 0x40081044\r
-#define MMCR_GPIO021_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO022_PIN_CONTROL 0x40081048\r
-#define MMCR_GPIO022_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO023_PIN_CONTROL 0x4008104C\r
-#define MMCR_GPIO023_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO024_PIN_CONTROL 0x40081050\r
-#define MMCR_GPIO024_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO025_PIN_CONTROL 0x40081054\r
-#define MMCR_GPIO025_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO026_PIN_CONTROL 0x40081058\r
-#define MMCR_GPIO026_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO027_PIN_CONTROL 0x4008105C\r
-#define MMCR_GPIO027_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO030_PIN_CONTROL 0x40081060\r
-#define MMCR_GPIO030_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO031_PIN_CONTROL 0x40081064\r
-#define MMCR_GPIO031_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO032_PIN_CONTROL 0x40081068\r
-#define MMCR_GPIO032_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO033_PIN_CONTROL 0x4008106C\r
-#define MMCR_GPIO033_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO034_PIN_CONTROL 0x40081070\r
-#define MMCR_GPIO034_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO035_PIN_CONTROL 0x40081074\r
-#define MMCR_GPIO035_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO036_PIN_CONTROL 0x40081078\r
-#define MMCR_GPIO036_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO040_PIN_CONTROL 0x40081080\r
-#define MMCR_GPIO040_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO041_PIN_CONTROL 0x40081084\r
-#define MMCR_GPIO041_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO042_PIN_CONTROL 0x40081088\r
-#define MMCR_GPIO042_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO043_PIN_CONTROL 0x4008108C\r
-#define MMCR_GPIO043_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO044_PIN_CONTROL 0x40081090\r
-#define MMCR_GPIO044_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO045_PIN_CONTROL 0x40081094\r
-#define MMCR_GPIO045_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO046_PIN_CONTROL 0x40081098\r
-#define MMCR_GPIO046_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO047_PIN_CONTROL 0x4008109C\r
-#define MMCR_GPIO047_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO050_PIN_CONTROL 0x400810A0\r
-#define MMCR_GPIO050_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO051_PIN_CONTROL 0x400810A4\r
-#define MMCR_GPIO051_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO052_PIN_CONTROL 0x400810A8\r
-#define MMCR_GPIO052_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO053_PIN_CONTROL 0x400810AC\r
-#define MMCR_GPIO053_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO054_PIN_CONTROL 0x400810B0\r
-#define MMCR_GPIO054_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO055_PIN_CONTROL 0x400810B4\r
-#define MMCR_GPIO055_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO056_PIN_CONTROL 0x400810B8\r
-#define MMCR_GPIO056_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO057_PIN_CONTROL 0x400810BC\r
-#define MMCR_GPIO057_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO060_PIN_CONTROL 0x400810C0\r
-#define MMCR_GPIO060_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO061_PIN_CONTROL 0x400810C4\r
-#define MMCR_GPIO061_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO062_PIN_CONTROL 0x400810C8\r
-#define MMCR_GPIO062_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO063_PIN_CONTROL 0x400810CC\r
-#define MMCR_GPIO063_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO064_PIN_CONTROL 0x400810D0\r
-#define MMCR_GPIO064_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO065_PIN_CONTROL 0x400810D4\r
-#define MMCR_GPIO065_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO066_PIN_CONTROL 0x400810D8\r
-#define MMCR_GPIO066_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO067_PIN_CONTROL 0x400810DC\r
-#define MMCR_GPIO067_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO100_PIN_CONTROL 0x40081100\r
-#define MMCR_GPIO100_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO101_PIN_CONTROL 0x40081104\r
-#define MMCR_GPIO101_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO102_PIN_CONTROL 0x40081108\r
-#define MMCR_GPIO102_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO103_PIN_CONTROL 0x4008110C\r
-#define MMCR_GPIO103_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO104_PIN_CONTROL 0x40081110\r
-#define MMCR_GPIO104_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO105_PIN_CONTROL 0x40081114\r
-#define MMCR_GPIO105_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO106_PIN_CONTROL 0x40081118\r
-#define MMCR_GPIO106_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO107_PIN_CONTROL 0x4008111C\r
-#define MMCR_GPIO107_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO110_PIN_CONTROL 0x40081120\r
-#define MMCR_GPIO110_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO111_PIN_CONTROL 0x40081124\r
-#define MMCR_GPIO111_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO112_PIN_CONTROL 0x40081128\r
-#define MMCR_GPIO112_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO113_PIN_CONTROL 0x4008112C\r
-#define MMCR_GPIO113_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO114_PIN_CONTROL 0x40081130\r
-#define MMCR_GPIO114_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO115_PIN_CONTROL 0x40081134\r
-#define MMCR_GPIO115_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO116_PIN_CONTROL 0x40081138\r
-#define MMCR_GPIO116_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO117_PIN_CONTROL 0x4008113C\r
-#define MMCR_GPIO117_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO120_PIN_CONTROL 0x40081140\r
-#define MMCR_GPIO120_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO121_PIN_CONTROL 0x40081144\r
-#define MMCR_GPIO121_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO122_PIN_CONTROL 0x40081148\r
-#define MMCR_GPIO122_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO123_PIN_CONTROL 0x4008114C\r
-#define MMCR_GPIO123_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO124_PIN_CONTROL 0x40081150\r
-#define MMCR_GPIO124_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO125_PIN_CONTROL 0x40081154\r
-#define MMCR_GPIO125_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO126_PIN_CONTROL 0x40081158\r
-#define MMCR_GPIO126_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO127_PIN_CONTROL 0x4008115C\r
-#define MMCR_GPIO127_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO130_PIN_CONTROL 0x40081160\r
-#define MMCR_GPIO130_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO131_PIN_CONTROL 0x40081164\r
-#define MMCR_GPIO131_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO132_PIN_CONTROL 0x40081168\r
-#define MMCR_GPIO132_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO133_PIN_CONTROL 0x4008116C\r
-#define MMCR_GPIO133_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO134_PIN_CONTROL 0x40081170\r
-#define MMCR_GPIO134_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO135_PIN_CONTROL 0x40081174\r
-#define MMCR_GPIO135_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO136_PIN_CONTROL 0x40081178\r
-#define MMCR_GPIO136_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO140_PIN_CONTROL 0x40081180\r
-#define MMCR_GPIO140_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO141_PIN_CONTROL 0x40081184\r
-#define MMCR_GPIO141_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO142_PIN_CONTROL 0x40081188\r
-#define MMCR_GPIO142_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO143_PIN_CONTROL 0x4008118C\r
-#define MMCR_GPIO143_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO144_PIN_CONTROL 0x40081190\r
-#define MMCR_GPIO144_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO145_PIN_CONTROL 0x40081194\r
-#define MMCR_GPIO145_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO146_PIN_CONTROL 0x40081198\r
-#define MMCR_GPIO146_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO147_PIN_CONTROL 0x4008119C\r
-#define MMCR_GPIO147_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO150_PIN_CONTROL 0x400811A0\r
-#define MMCR_GPIO150_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO151_PIN_CONTROL 0x400811A4\r
-#define MMCR_GPIO151_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO152_PIN_CONTROL 0x400811A8\r
-#define MMCR_GPIO152_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO153_PIN_CONTROL 0x400811AC\r
-#define MMCR_GPIO153_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO154_PIN_CONTROL 0x400811B0\r
-#define MMCR_GPIO154_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO155_PIN_CONTROL 0x400811B4\r
-#define MMCR_GPIO155_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO156_PIN_CONTROL 0x400811B8\r
-#define MMCR_GPIO156_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO157_PIN_CONTROL 0x400811BC\r
-#define MMCR_GPIO157_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO160_PIN_CONTROL 0x400811C0\r
-#define MMCR_GPIO160_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO161_PIN_CONTROL 0x400811C4\r
-#define MMCR_GPIO161_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO162_PIN_CONTROL 0x400811C8\r
-#define MMCR_GPIO162_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO163_PIN_CONTROL 0x400811CC\r
-#define MMCR_GPIO163_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO164_PIN_CONTROL 0x400811D0\r
-#define MMCR_GPIO164_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO165_PIN_CONTROL 0x400811D4\r
-#define MMCR_GPIO165_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO200_PIN_CONTROL 0x40081200\r
-#define MMCR_GPIO200_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO201_PIN_CONTROL 0x40081204\r
-#define MMCR_GPIO201_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO202_PIN_CONTROL 0x40081208\r
-#define MMCR_GPIO202_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO203_PIN_CONTROL 0x4008120C\r
-#define MMCR_GPIO203_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO204_PIN_CONTROL 0x40081210\r
-#define MMCR_GPIO204_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO206_PIN_CONTROL 0x40081218\r
-#define MMCR_GPIO206_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO210_PIN_CONTROL 0x40081220\r
-#define MMCR_GPIO210_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO211_PIN_CONTROL 0x40081224\r
-#define MMCR_GPIO211_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO212_PIN_CONTROL 0x40081228\r
-#define MMCR_GPIO212_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO213_PIN_CONTROL 0x4008122C\r
-#define MMCR_GPIO213_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_000_036 0x40081280\r
-#define MMCR_GPIO_OUTPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_000_036))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_040_076 0x40081284\r
-#define MMCR_GPIO_OUTPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_040_076))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_100_136 0x40081288\r
-#define MMCR_GPIO_OUTPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_100_136))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_140_176 0x4008128C\r
-#define MMCR_GPIO_OUTPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_140_176))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_200_236 0x40081290\r
-#define MMCR_GPIO_OUTPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_200_236))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_000_036 0x40081300\r
-#define MMCR_GPIO_INPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_000_036))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_040_076 0x40081304\r
-#define MMCR_GPIO_INPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_040_076))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_100_136 0x40081308\r
-#define MMCR_GPIO_INPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_100_136))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_140_176 0x4008130C\r
-#define MMCR_GPIO_INPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_140_176))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_200_236 0x40081310\r
-#define MMCR_GPIO_INPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_200_236))\r
-\r
-#define ADDR_GPIO_LOCK_4 0x400813EC\r
-#define MMCR_GPIO_LOCK_4 (*(VUINT32 *)(ADDR_GPIO_LOCK_4))\r
-\r
-#define ADDR_GPIO_LOCK_3 0x400813F0\r
-#define MMCR_GPIO_LOCK_3 (*(VUINT32 *)(ADDR_GPIO_LOCK_3))\r
-\r
-#define ADDR_GPIO_LOCK_2 0x400813F4\r
-#define MMCR_GPIO_LOCK_2 (*(VUINT32 *)(ADDR_GPIO_LOCK_2))\r
-\r
-#define ADDR_GPIO_LOCK_1 0x400813F8\r
-#define MMCR_GPIO_LOCK_1 (*(VUINT32 *)(ADDR_GPIO_LOCK_1))\r
-\r
-#define ADDR_GPIO_LOCK_0 0x400813FC\r
-#define MMCR_GPIO_LOCK_0 (*(VUINT32 *)(ADDR_GPIO_LOCK_0))\r
-\r
-#define ADDR_GPIO000_PIN_CONTROL_2 0x40081500\r
-#define MMCR_GPIO000_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO001_PIN_CONTROL_2 0x40081504\r
-#define MMCR_GPIO001_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO002_PIN_CONTROL_2 0x40081508\r
-#define MMCR_GPIO002_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO003_PIN_CONTROL_2 0x4008150C\r
-#define MMCR_GPIO003_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO004_PIN_CONTROL_2 0x40081510\r
-#define MMCR_GPIO004_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO005_PIN_CONTROL_2 0x40081514\r
-#define MMCR_GPIO005_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO006_PIN_CONTROL_2 0x40081518\r
-#define MMCR_GPIO006_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO007_PIN_CONTROL_2 0x4008151C\r
-#define MMCR_GPIO007_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO010_PIN_CONTROL_2 0x40081520\r
-#define MMCR_GPIO010_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO011_PIN_CONTROL_2 0x40081524\r
-#define MMCR_GPIO011_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO012_PIN_CONTROL_2 0x40081528\r
-#define MMCR_GPIO012_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO013_PIN_CONTROL_2 0x4008152C\r
-#define MMCR_GPIO013_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO014_PIN_CONTROL_2 0x40081530\r
-#define MMCR_GPIO014_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO015_PIN_CONTROL_2 0x40081534\r
-#define MMCR_GPIO015_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO016_PIN_CONTROL_2 0x40081538\r
-#define MMCR_GPIO016_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO017_PIN_CONTROL_2 0x4008153C\r
-#define MMCR_GPIO017_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO020_PIN_CONTROL_2 0x40081540\r
-#define MMCR_GPIO020_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO021_PIN_CONTROL_2 0x40081544\r
-#define MMCR_GPIO021_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO022_PIN_CONTROL_2 0x40081548\r
-#define MMCR_GPIO022_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO023_PIN_CONTROL_2 0x4008154C\r
-#define MMCR_GPIO023_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO024_PIN_CONTROL_2 0x40081550\r
-#define MMCR_GPIO024_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO025_PIN_CONTROL_2 0x40081554\r
-#define MMCR_GPIO025_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO026_PIN_CONTROL_2 0x40081558\r
-#define MMCR_GPIO026_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO027_PIN_CONTROL_2 0x4008155C\r
-#define MMCR_GPIO027_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO030_PIN_CONTROL_2 0x40081560\r
-#define MMCR_GPIO030_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO031_PIN_CONTROL_2 0x40081564\r
-#define MMCR_GPIO031_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO032_PIN_CONTROL_2 0x40081568\r
-#define MMCR_GPIO032_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO033_PIN_CONTROL_2 0x4008156C\r
-#define MMCR_GPIO033_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO034_PIN_CONTROL_2 0x40081570\r
-#define MMCR_GPIO034_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO035_PIN_CONTROL_2 0x40081574\r
-#define MMCR_GPIO035_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO036_PIN_CONTROL_2 0x40081578\r
-#define MMCR_GPIO036_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO040_PIN_CONTROL_2 0x40081580\r
-#define MMCR_GPIO040_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO041_PIN_CONTROL_2 0x40081584\r
-#define MMCR_GPIO041_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO042_PIN_CONTROL_2 0x40081588\r
-#define MMCR_GPIO042_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO043_PIN_CONTROL_2 0x4008158C\r
-#define MMCR_GPIO043_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO044_PIN_CONTROL_2 0x40081590\r
-#define MMCR_GPIO044_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO045_PIN_CONTROL_2 0x40081594\r
-#define MMCR_GPIO045_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO046_PIN_CONTROL_2 0x40081598\r
-#define MMCR_GPIO046_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO047_PIN_CONTROL_2 0x4008159C\r
-#define MMCR_GPIO047_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO050_PIN_CONTROL_2 0x400815A0\r
-#define MMCR_GPIO050_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO051_PIN_CONTROL_2 0x400815A4\r
-#define MMCR_GPIO051_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO052_PIN_CONTROL_2 0x400815A8\r
-#define MMCR_GPIO052_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO053_PIN_CONTROL_2 0x400815AC\r
-#define MMCR_GPIO053_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO054_PIN_CONTROL_2 0x400815B0\r
-#define MMCR_GPIO054_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO055_PIN_CONTROL_2 0x400815B4\r
-#define MMCR_GPIO055_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO056_PIN_CONTROL_2 0x400815B8\r
-#define MMCR_GPIO056_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO057_PIN_CONTROL_2 0x400815BC\r
-#define MMCR_GPIO057_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO060_PIN_CONTROL_2 0x400815C0\r
-#define MMCR_GPIO060_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO061_PIN_CONTROL_2 0x400815C4\r
-#define MMCR_GPIO061_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO062_PIN_CONTROL_2 0x400815C8\r
-#define MMCR_GPIO062_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO063_PIN_CONTROL_2 0x400815CC\r
-#define MMCR_GPIO063_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO064_PIN_CONTROL_2 0x400815D0\r
-#define MMCR_GPIO064_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO065_PIN_CONTROL_2 0x400815D4\r
-#define MMCR_GPIO065_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO066_PIN_CONTROL_2 0x400815D8\r
-#define MMCR_GPIO066_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO067_PIN_CONTROL_2 0x400815DC\r
-#define MMCR_GPIO067_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO100_PIN_CONTROL_2 0x400815E0\r
-#define MMCR_GPIO100_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO101_PIN_CONTROL_2 0x400815E4\r
-#define MMCR_GPIO101_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO102_PIN_CONTROL_2 0x400815E8\r
-#define MMCR_GPIO102_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO103_PIN_CONTROL_2 0x400815EC\r
-#define MMCR_GPIO103_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO104_PIN_CONTROL_2 0x400815F0\r
-#define MMCR_GPIO104_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO105_PIN_CONTROL_2 0x400815F4\r
-#define MMCR_GPIO105_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO106_PIN_CONTROL_2 0x400815F8\r
-#define MMCR_GPIO106_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO107_PIN_CONTROL_2 0x400815FC\r
-#define MMCR_GPIO107_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO110_PIN_CONTROL_2 0x40081600\r
-#define MMCR_GPIO110_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO111_PIN_CONTROL_2 0x40081604\r
-#define MMCR_GPIO111_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO112_PIN_CONTROL_2 0x40081608\r
-#define MMCR_GPIO112_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO113_PIN_CONTROL_2 0x4008160C\r
-#define MMCR_GPIO113_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO114_PIN_CONTROL_2 0x40081610\r
-#define MMCR_GPIO114_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO115_PIN_CONTROL_2 0x40081614\r
-#define MMCR_GPIO115_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO116_PIN_CONTROL_2 0x40081618\r
-#define MMCR_GPIO116_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO117_PIN_CONTROL_2 0x4008161C\r
-#define MMCR_GPIO117_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO120_PIN_CONTROL_2 0x40081620\r
-#define MMCR_GPIO120_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO121_PIN_CONTROL_2 0x40081624\r
-#define MMCR_GPIO121_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO122_PIN_CONTROL_2 0x40081628\r
-#define MMCR_GPIO122_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO123_PIN_CONTROL_2 0x4008162C\r
-#define MMCR_GPIO123_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO124_PIN_CONTROL_2 0x40081630\r
-#define MMCR_GPIO124_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO125_PIN_CONTROL_2 0x40081634\r
-#define MMCR_GPIO125_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO126_PIN_CONTROL_2 0x40081638\r
-#define MMCR_GPIO126_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO127_PIN_CONTROL_2 0x4008163C\r
-#define MMCR_GPIO127_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO130_PIN_CONTROL_2 0x40081640\r
-#define MMCR_GPIO130_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO131_PIN_CONTROL_2 0x40081644\r
-#define MMCR_GPIO131_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO132_PIN_CONTROL_2 0x40081648\r
-#define MMCR_GPIO132_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO133_PIN_CONTROL_2 0x4008164C\r
-#define MMCR_GPIO133_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO134_PIN_CONTROL_2 0x40081650\r
-#define MMCR_GPIO134_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO135_PIN_CONTROL_2 0x40081654\r
-#define MMCR_GPIO135_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO136_PIN_CONTROL_2 0x40081658\r
-#define MMCR_GPIO136_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO140_PIN_CONTROL_2 0x40081660\r
-#define MMCR_GPIO140_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO141_PIN_CONTROL_2 0x40081664\r
-#define MMCR_GPIO141_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO142_PIN_CONTROL_2 0x40081668\r
-#define MMCR_GPIO142_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO143_PIN_CONTROL_2 0x4008166C\r
-#define MMCR_GPIO143_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO144_PIN_CONTROL_2 0x40081670\r
-#define MMCR_GPIO144_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO145_PIN_CONTROL_2 0x40081674\r
-#define MMCR_GPIO145_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO146_PIN_CONTROL_2 0x40081678\r
-#define MMCR_GPIO146_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO147_PIN_CONTROL_2 0x4008167C\r
-#define MMCR_GPIO147_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO150_PIN_CONTROL_2 0x40081680\r
-#define MMCR_GPIO150_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO151_PIN_CONTROL_2 0x40081684\r
-#define MMCR_GPIO151_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO152_PIN_CONTROL_2 0x40081688\r
-#define MMCR_GPIO152_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO153_PIN_CONTROL_2 0x4008168C\r
-#define MMCR_GPIO153_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO154_PIN_CONTROL_2 0x40081690\r
-#define MMCR_GPIO154_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO155_PIN_CONTROL_2 0x40081694\r
-#define MMCR_GPIO155_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO156_PIN_CONTROL_2 0x40081698\r
-#define MMCR_GPIO156_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO157_PIN_CONTROL_2 0x4008169C\r
-#define MMCR_GPIO157_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO160_PIN_CONTROL_2 0x400816A0\r
-#define MMCR_GPIO160_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO161_PIN_CONTROL_2 0x400816A4\r
-#define MMCR_GPIO161_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO162_PIN_CONTROL_2 0x400816A8\r
-#define MMCR_GPIO162_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO163_PIN_CONTROL_2 0x400816AC\r
-#define MMCR_GPIO163_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO164_PIN_CONTROL_2 0x400816B0\r
-#define MMCR_GPIO164_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO165_PIN_CONTROL_2 0x400816B4\r
-#define MMCR_GPIO165_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO200_PIN_CONTROL_2 0x40081720\r
-#define MMCR_GPIO200_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO201_PIN_CONTROL_2 0x40081724\r
-#define MMCR_GPIO201_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO202_PIN_CONTROL_2 0x40081728\r
-#define MMCR_GPIO202_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO203_PIN_CONTROL_2 0x4008172C\r
-#define MMCR_GPIO203_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO204_PIN_CONTROL_2 0x40081730\r
-#define MMCR_GPIO204_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO206_PIN_CONTROL_2 0x40081738\r
-#define MMCR_GPIO206_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO210_PIN_CONTROL_2 0x40081740\r
-#define MMCR_GPIO210_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO211_PIN_CONTROL_2 0x40081744\r
-#define MMCR_GPIO211_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO212_PIN_CONTROL_2 0x40081748\r
-#define MMCR_GPIO212_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO213_PIN_CONTROL_2 0x4008174C\r
-#define MMCR_GPIO213_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL_2))\r
-\r
-/***************************************************************\r
-* DMA\r
-***************************************************************/\r
-#define ADDR_DMA_MAIN_CONTROL 0x40002400\r
-#define MMCR_DMA_MAIN_CONTROL (*(VUINT8 *)(ADDR_DMA_MAIN_CONTROL))\r
-\r
-#define ADDR_DMA_AFIFO_DATA 0x40002404\r
-#define MMCR_DMA_AFIFO_DATA (*(VUINT32 *)(ADDR_DMA_AFIFO_DATA))\r
-\r
-#define ADDR_DMA_MAIN_DEBUG 0x40002408\r
-#define MMCR_DMA_MAIN_DEBUG (*(VUINT8 *)(ADDR_DMA_MAIN_DEBUG))\r
-\r
-#define ADDR_DMA_CH0_ACTIVATE 0x40002410\r
-#define MMCR_DMA_CH0_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH0_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH0_MEMORY_START_ADDRESS 0x40002414\r
-#define MMCR_DMA_CH0_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH0_MEMORY_END_ADDRESS 0x40002418\r
-#define MMCR_DMA_CH0_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH0_AHB_ADDRESS 0x4000241C\r
-#define MMCR_DMA_CH0_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH0_CONTROL 0x40002420\r
-#define MMCR_DMA_CH0_CONTROL (*(VUINT32 *)(ADDR_DMA_CH0_CONTROL))\r
-\r
-#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS 0x40002424\r
-#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE 0x40002428\r
-#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH0_TEST 0x4000242C\r
-#define MMCR_DMA_CH0_TEST (*(VUINT32 *)(ADDR_DMA_CH0_TEST))\r
-\r
-#define ADDR_DMA_CH1_ACTIVATE 0x40002430\r
-#define MMCR_DMA_CH1_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH1_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH1_MEMORY_START_ADDRESS 0x40002434\r
-#define MMCR_DMA_CH1_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH1_MEMORY_END_ADDRESS 0x40002438\r
-#define MMCR_DMA_CH1_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH1_AHB_ADDRESS 0x4000243C\r
-#define MMCR_DMA_CH1_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH1_CONTROL 0x40002440\r
-#define MMCR_DMA_CH1_CONTROL (*(VUINT32 *)(ADDR_DMA_CH1_CONTROL))\r
-\r
-#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS 0x40002444\r
-#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE 0x40002448\r
-#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH1_TEST 0x4000244C\r
-#define MMCR_DMA_CH1_TEST (*(VUINT32 *)(ADDR_DMA_CH1_TEST))\r
-\r
-#define ADDR_DMA_CH10_ACTIVATE 0x40002550\r
-#define MMCR_DMA_CH10_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH10_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH10_MEMORY_START_ADDRESS 0x40002554\r
-#define MMCR_DMA_CH10_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH10_MEMORY_END_ADDRESS 0x40002558\r
-#define MMCR_DMA_CH10_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH10_AHB_ADDRESS 0x4000255C\r
-#define MMCR_DMA_CH10_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH10_CONTROL 0x40002560\r
-#define MMCR_DMA_CH10_CONTROL (*(VUINT32 *)(ADDR_DMA_CH10_CONTROL))\r
-\r
-#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS 0x40002564\r
-#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE 0x40002568\r
-#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH10_TEST 0x4000256C\r
-#define MMCR_DMA_CH10_TEST (*(VUINT32 *)(ADDR_DMA_CH10_TEST))\r
-\r
-#define ADDR_DMA_CH11_ACTIVATE 0x40002570\r
-#define MMCR_DMA_CH11_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH11_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH11_MEMORY_START_ADDRESS 0x40002574\r
-#define MMCR_DMA_CH11_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH11_MEMORY_END_ADDRESS 0x40002578\r
-#define MMCR_DMA_CH11_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH11_AHB_ADDRESS 0x4000257C\r
-#define MMCR_DMA_CH11_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH11_CONTROL 0x40002580\r
-#define MMCR_DMA_CH11_CONTROL (*(VUINT32 *)(ADDR_DMA_CH11_CONTROL))\r
-\r
-#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS 0x40002584\r
-#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE 0x40002588\r
-#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH11_TEST 0x4000258C\r
-#define MMCR_DMA_CH11_TEST (*(VUINT32 *)(ADDR_DMA_CH11_TEST))\r
-\r
-#define ADDR_DMA_CH2_ACTIVATE 0x40002450\r
-#define MMCR_DMA_CH2_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH2_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH2_MEMORY_START_ADDRESS 0x40002454\r
-#define MMCR_DMA_CH2_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH2_MEMORY_END_ADDRESS 0x40002458\r
-#define MMCR_DMA_CH2_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH2_AHB_ADDRESS 0x4000245C\r
-#define MMCR_DMA_CH2_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH2_CONTROL 0x40002460\r
-#define MMCR_DMA_CH2_CONTROL (*(VUINT32 *)(ADDR_DMA_CH2_CONTROL))\r
-\r
-#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS 0x40002464\r
-#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE 0x40002468\r
-#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH2_TEST 0x4000246C\r
-#define MMCR_DMA_CH2_TEST (*(VUINT32 *)(ADDR_DMA_CH2_TEST))\r
-\r
-#define ADDR_DMA_CH3_ACTIVATE 0x40002470\r
-#define MMCR_DMA_CH3_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH3_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH3_MEMORY_START_ADDRESS 0x40002474\r
-#define MMCR_DMA_CH3_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH3_MEMORY_END_ADDRESS 0x40002478\r
-#define MMCR_DMA_CH3_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH3_AHB_ADDRESS 0x4000247C\r
-#define MMCR_DMA_CH3_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH3_CONTROL 0x40002480\r
-#define MMCR_DMA_CH3_CONTROL (*(VUINT32 *)(ADDR_DMA_CH3_CONTROL))\r
-\r
-#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS 0x40002484\r
-#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE 0x40002488\r
-#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH3_TEST 0x4000248C\r
-#define MMCR_DMA_CH3_TEST (*(VUINT32 *)(ADDR_DMA_CH3_TEST))\r
-\r
-#define ADDR_DMA_CH4_ACTIVATE 0x40002490\r
-#define MMCR_DMA_CH4_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH4_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH4_MEMORY_START_ADDRESS 0x40002494\r
-#define MMCR_DMA_CH4_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH4_MEMORY_END_ADDRESS 0x40002498\r
-#define MMCR_DMA_CH4_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH4_AHB_ADDRESS 0x4000249C\r
-#define MMCR_DMA_CH4_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH4_CONTROL 0x400024A0\r
-#define MMCR_DMA_CH4_CONTROL (*(VUINT32 *)(ADDR_DMA_CH4_CONTROL))\r
-\r
-#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS 0x400024A4\r
-#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE 0x400024A8\r
-#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH4_TEST 0x400024AC\r
-#define MMCR_DMA_CH4_TEST (*(VUINT32 *)(ADDR_DMA_CH4_TEST))\r
-\r
-#define ADDR_DMA_CH5_ACTIVATE 0x400024B0\r
-#define MMCR_DMA_CH5_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH5_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH5_MEMORY_START_ADDRESS 0x400024B4\r
-#define MMCR_DMA_CH5_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH5_MEMORY_END_ADDRESS 0x400024B8\r
-#define MMCR_DMA_CH5_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH5_AHB_ADDRESS 0x400024BC\r
-#define MMCR_DMA_CH5_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH5_CONTROL 0x400024C0\r
-#define MMCR_DMA_CH5_CONTROL (*(VUINT32 *)(ADDR_DMA_CH5_CONTROL))\r
-\r
-#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS 0x400024C4\r
-#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE 0x400024C8\r
-#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH5_TEST 0x400024CC\r
-#define MMCR_DMA_CH5_TEST (*(VUINT32 *)(ADDR_DMA_CH5_TEST))\r
-\r
-#define ADDR_DMA_CH6_ACTIVATE 0x400024D0\r
-#define MMCR_DMA_CH6_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH6_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH6_MEMORY_START_ADDRESS 0x400024D4\r
-#define MMCR_DMA_CH6_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH6_MEMORY_END_ADDRESS 0x400024D8\r
-#define MMCR_DMA_CH6_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH6_AHB_ADDRESS 0x400024DC\r
-#define MMCR_DMA_CH6_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH6_CONTROL 0x4.00E+05\r
-#define MMCR_DMA_CH6_CONTROL (*(VUINT32 *)(ADDR_DMA_CH6_CONTROL))\r
-\r
-#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS 0x4.00E+09\r
-#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE 0x4.00E+13\r
-#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH6_TEST 0x400024EC\r
-#define MMCR_DMA_CH6_TEST (*(VUINT32 *)(ADDR_DMA_CH6_TEST))\r
-\r
-#define ADDR_DMA_CH7_ACTIVATE 0x400024F0\r
-#define MMCR_DMA_CH7_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH7_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH7_MEMORY_START_ADDRESS 0x400024F4\r
-#define MMCR_DMA_CH7_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH7_MEMORY_END_ADDRESS 0x400024F8\r
-#define MMCR_DMA_CH7_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH7_AHB_ADDRESS 0x400024FC\r
-#define MMCR_DMA_CH7_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH7_CONTROL 0x40002500\r
-#define MMCR_DMA_CH7_CONTROL (*(VUINT32 *)(ADDR_DMA_CH7_CONTROL))\r
-\r
-#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS 0x40002504\r
-#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE 0x40002508\r
-#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH7_TEST 0x4000250C\r
-#define MMCR_DMA_CH7_TEST (*(VUINT32 *)(ADDR_DMA_CH7_TEST))\r
-\r
-#define ADDR_DMA_CH8_ACTIVATE 0x40002510\r
-#define MMCR_DMA_CH8_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH8_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH8_MEMORY_START_ADDRESS 0x40002514\r
-#define MMCR_DMA_CH8_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH8_MEMORY_END_ADDRESS 0x40002518\r
-#define MMCR_DMA_CH8_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH8_AHB_ADDRESS 0x4000251C\r
-#define MMCR_DMA_CH8_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH8_CONTROL 0x40002520\r
-#define MMCR_DMA_CH8_CONTROL (*(VUINT32 *)(ADDR_DMA_CH8_CONTROL))\r
-\r
-#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS 0x40002524\r
-#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE 0x40002528\r
-#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH8_TEST 0x4000252C\r
-#define MMCR_DMA_CH8_TEST (*(VUINT32 *)(ADDR_DMA_CH8_TEST))\r
-\r
-#define ADDR_DMA_CH9_ACTIVATE 0x40002530\r
-#define MMCR_DMA_CH9_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH9_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH9_MEMORY_START_ADDRESS 0x40002534\r
-#define MMCR_DMA_CH9_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH9_MEMORY_END_ADDRESS 0x40002538\r
-#define MMCR_DMA_CH9_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH9_AHB_ADDRESS 0x4000253C\r
-#define MMCR_DMA_CH9_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH9_CONTROL 0x40002540\r
-#define MMCR_DMA_CH9_CONTROL (*(VUINT32 *)(ADDR_DMA_CH9_CONTROL))\r
-\r
-#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS 0x40002544\r
-#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE 0x40002548\r
-#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH9_TEST 0x4000254C\r
-#define MMCR_DMA_CH9_TEST (*(VUINT32 *)(ADDR_DMA_CH9_TEST))\r
-\r
-#endif /*SMSCMMCR_H_*/\r
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/11/22 06:01:28 $ \r
-$Author: amohandas $\r
-Last Change: Updated with unit testing feedbacks\r
-******************************************************************************/\r
-/** @file btimer.h\r
-* \brief Basic Timer Peripheral Header file\r
-* \author jvasanth\r
-* \r
-* This file is the header file for Basic Timer Peripheral \r
-******************************************************************************/\r
-\r
-/** @defgroup Basic_Timer\r
- * @{\r
- */\r
-\r
-#ifndef _BTIMER_H\r
-#define _BTIMER_H\r
-\r
-/******************************************************************************/\r
-/** Logical Timer ID for APIs.\r
- * This is the timer IDs passed to Basic Timer API function calls \r
- *******************************************************************************/\r
-enum _PID_BTIMER_\r
-{\r
- PID_BTIMER_0,\r
- PID_BTIMER_1,\r
- PID_BTIMER_2,\r
- PID_BTIMER_3,\r
- PID_BTIMER_4,\r
- PID_BTIMER_5,\r
- PID_BTIMER_MAX \r
-};\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Logical flags for Timer Control */\r
-/* ---------------------------------------------------------------------- */\r
-//This is for tmr_cntl parameter in btimer_init function\r
-#define BTIMER_AUTO_RESTART (0x08u)\r
-#define BTIMER_ONE_SHOT (0u)\r
-#define BTIMER_COUNT_UP (0x04u)\r
-#define BTIMER_COUNT_DOWN (0u)\r
-#define BTIMER_INT_EN (0x01u)\r
-#define BTIMER_NO_INT (0u)\r
-/* ---------------------------------------------------------------------- */\r
-\r
-\r
-//Timer Block Hardware Bits and Masks\r
-#define BTIMER_CNTL_HALT (0x80UL)\r
-#define BTIMER_CNTL_RELOAD (0x40UL)\r
-#define BTIMER_CNTL_START (0x20UL)\r
-#define BTIMER_CNTL_SOFT_RESET (0x10UL)\r
-#define BTIMER_CNTL_AUTO_RESTART (0x08UL)\r
-#define BTIMER_CNTL_COUNT_UP (0x04UL)\r
-#define BTIMER_CNTL_ENABLE (0x01UL)\r
-\r
-#define BTIMER_CNTL_HALT_BIT (7U)\r
-#define BTIMER_CNTL_RELOAD_BIT (6U)\r
-#define BTIMER_CNTL_START_BIT (5U)\r
-#define BTIMER_CNTRL_SOFT_RESET_BIT (4U)\r
-#define BTIMER_CNTL_AUTO_RESTART_BIT (3U)\r
-#define BTIMER_CNTL_COUNT_DIR_BIT (2U)\r
-#define BTIMER_CNTL_ENABLE_BIT (0U)\r
-\r
-#define BTIMER_GIRQ MEC_GIRQ23_ID\r
-#define BTIMER_MAX_INSTANCE PID_BTIMER_MAX\r
-\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Basic Timer Intitialization function */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Initialize specified timer\r
- * @param btimer_id Basic Timer ID\r
- * @param tmr_cntl Logical flags for Timer Control\r
- * @param initial_count Initial Count\r
- * @param preload_count Preload Count\r
- * @note Performs a soft reset of the timer before configuration \r
- */\r
-void btimer_init(uint8_t btimer_id, \r
- uint16_t tmr_cntl,\r
- uint16_t prescaler,\r
- uint32_t initial_count,\r
- uint32_t preload_count);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions to program and read the Basic Timer Counter */\r
-/* ---------------------------------------------------------------------- */\r
-/** Program timer's counter register.\r
- * @param btimer_id Basic Timer ID\r
- * @param count new counter value \r
- * @note Timer hardware may implement a 16-bit or 32-bit \r
- * hardware counter. If the timer is 16-bit only the lower\r
- * 16-bits of the count paramter are used.\r
- */\r
-void btimer_count_set(uint8_t btimer_id, uint32_t count);\r
-\r
-/** Return current value of timer's count register.\r
- * @param btimer_id Basic Timer ID. \r
- * @return uint32_t timer count may be 32 or 16 bits depending \r
- * upon the hardware. Timers 0-3 are 16-bit\r
- * and Timers 4-5 are 32-bit.\r
- */\r
-uint32_t btimer_count_get(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Function to reload counter from Preload Register */\r
-/* ---------------------------------------------------------------------- */\r
-/** Force timer to reload counter from preload \r
- * register. \r
- * @param btimer_id Basic Timer ID. \r
- * @note Hardware will only reload counter if timer is running. \r
- */\r
-void btimer_reload(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for stopping and starting the basic Timer */\r
-/* ---------------------------------------------------------------------- */\r
-/** Start timer counting.\r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_start(uint8_t btimer_id);\r
-\r
-/** Stop timer. \r
- * @param btimer_id Basic Timer ID. \r
- * @note When a stopped timer is started again it will reload \r
- * the count register from preload value.\r
- */\r
-void btimer_stop(uint8_t btimer_id);\r
-\r
-/** Return state of timer's START bit. \r
- * @param btimer_id Basic Timer ID. \r
- * @return uint8_t 0(timer not started), 1 (timer started)\r
- */\r
-uint8_t btimer_is_started(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Function to perform basic timer soft reset */\r
-/* ---------------------------------------------------------------------- */\r
-/** Peform soft reset of specified timer. \r
- * @param btimer_id Basic Timer ID \r
- * @note Soft reset set all registers to POR values.\r
- * Spins 256 times waiting on hardware to clear reset bit. \r
- */\r
-void btimer_reset(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions to halt/unhalt the timer counting */\r
-/* ---------------------------------------------------------------------- */\r
-/** Halt timer counting with no reload on unhalt. \r
- * @param btimer_id Basic Timer ID. \r
- * @note A halted timer will not reload the count register when \r
- * unhalted, it will continue counting from the current\r
- * count value.\r
- */\r
-void btimer_halt(uint8_t btimer_id);\r
-\r
-/** Unhalt timer counting. \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_unhalt(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for Basic Timer interrupt */\r
-/* ---------------------------------------------------------------------- */\r
-/** Enable specified timer's interrupt from the block. \r
- * @param btimer_id Basic Timer ID.\r
- * @param ien Non-zero enable interrupt in timer block, 0 \r
- * disable.\r
- */\r
-void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien);\r
-\r
-/** Read Timer interrupt status and clear if set \r
- * @param btimer_id Basic Timer ID. \r
- * @return uint8_t 1 (Timer interrupt status set) else 0. \r
- * @note If timer interrupt status is set then clear it before \r
- * returning.\r
- */\r
-uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for Basic Timer GIRQ */\r
-/* ---------------------------------------------------------------------- */\r
-/** Enables GIRQ enable bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_enable_set(uint8_t btimer_id);\r
-\r
-/** Clears GIRQ enable bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_enable_clr(uint8_t btimer_id);\r
-\r
-/** Returns GIRQ source bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- * @return uint8_t 0(src bit not set), Non-zero (src bit set)\r
- */\r
-uint8_t btimer_girq_src_get(uint8_t btimer_id);\r
-\r
-/** Clears GIRQ source bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_src_clr(uint8_t btimer_id);\r
-\r
-/** Returns GIRQ result bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- * @return uint8_t 0(result bit not set), Non-zero (result bit set)\r
- */\r
-uint8_t btimer_girq_result_get(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for Basic Timer Sleep */\r
-/* ---------------------------------------------------------------------- */\r
-/** Enable/Disable clock gating on idle of a timer \r
- * @param btimer_id Basic Timer ID.\r
- * @param sleep_en 1 = Sleep enable, 0 = Sleep disable\r
- */\r
-void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en);\r
-\r
-/** Returns clk required status for the timer block\r
- * @param btimer_id Basic Timer ID.\r
- * @return Non-zero if clk required, else 0\r
- */\r
-uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id);\r
-\r
-/** Enable/Disable reset on sleep for the timer block \r
- * @param btimer_id Basic Timer ID.\r
- * @param reset_en 1 to enable, 0 to disable\r
- */\r
-void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to set and read Timer Counter Register */\r
-/* ---------------------------------------------------------------------- */\r
-/** Sets timer counter\r
- * @param btimer_id Basic Timer ID\r
- * @param count - 32-bit counter \r
- */\r
-void p_btimer_count_set(uint8_t btimer_id, uint32_t count);\r
-\r
-/** Read the timer counter\r
- * @param btimer_id Basic Timer ID\r
- * @return count - 32-bit counter \r
- */\r
-uint32_t p_btimer_count_get(uint8_t btimer_id);\r
-\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to program the Preload */\r
-/* ---------------------------------------------------------------------- */\r
-/** Sets preload for the counter\r
- * @param btimer_id Basic Timer ID\r
- * @param preload_count - 32-bit pre-load value \r
- */\r
-void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Functions - Functions for basic timer interrupts */\r
-/* ---------------------------------------------------------------------- */\r
-/** Reads the interrupt status bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- * @return status - 1 if interrupt status set, else 0\r
- */\r
-uint8_t p_btimer_int_status_get(uint8_t btimer_id);\r
-\r
-/** Clears interrupt status bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_status_clr(uint8_t btimer_id);\r
-\r
-/** Sets interrupt enable bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_enable_set(uint8_t btimer_id);\r
-\r
-/** Clears interrupt enable bit for the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_enable_clr(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Functions - Functions for Control Register */\r
-/* ---------------------------------------------------------------------- */\r
-/** Writes the control register 32-bits\r
- * @param btimer_id Basic Timer ID\r
- * @param value - 32-bit value to program\r
- */\r
-void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value);\r
-\r
-/** Reads the control register \r
- * @param btimer_id Basic Timer ID\r
- * @return uint32_t - 32-bit value\r
- */\r
-uint32_t p_btimer_ctrl_read(uint8_t btimer_id);\r
-\r
-/** Clears enable bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_enable_set(uint8_t btimer_id);\r
-\r
-/** Clears enable bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_enable_clr(uint8_t btimer_id);\r
-\r
-/** Sets counter direction bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id);\r
-\r
-/** Clears counter direction bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id);\r
-\r
-/** Sets auto restart bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id);\r
-\r
-/** Clears auto resetart bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id);\r
-\r
-/** Sets soft reset bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id);\r
-\r
-/** Read Soft Reset bit \r
- * @param btimer_id Basic Timer ID\r
- * @return 0 if soft reset status bit cleared; else non-zero value\r
- */\r
-uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id);\r
-\r
-/** Sets start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_start_set(uint8_t btimer_id);\r
-\r
-/** Read start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- * @return 0 if start bit not set; else non-zero value\r
- */\r
-uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id);\r
-\r
-/** Clears start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_start_clr(uint8_t btimer_id);\r
-\r
-/** Sets reload bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_reload_set(uint8_t btimer_id);\r
-\r
-/** Clears reload bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_reload_clr(uint8_t btimer_id);\r
-\r
-/** Sets halt bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_halt_set(uint8_t btimer_id);\r
-\r
-/** Clears halt bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-\r
-void p_btimer_ctrl_halt_clr(uint8_t btimer_id);\r
-\r
-/** Sets prescale value\r
- * @param btimer_id Basic Timer ID\r
- * @param prescaler - 16-bit pre-scale value \r
- */\r
-void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler);\r
-\r
-\r
-#endif // #ifndef _BTIMER_H\r
-\r
-/* end btimer_perphl.c */\r
-\r
-/** @} //Peripherals Basic_Timer\r
- */\r
-\r
+/*****************************************************************************
+* © 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $
+$DateTime: 2016/04/08 10:18:28 $
+$Author: pramans $
+Last Change: Updated with unit testing feedbacks
+******************************************************************************/
+/** @file btimer.h
+* \brief Basic Timer Peripheral Header file
+* \author jvasanth
+*
+* This file is the header file for Basic Timer Peripheral
+******************************************************************************/
+
+/** @defgroup Basic_Timer
+ * @{
+ */
+
+#ifndef _BTIMER_H
+#define _BTIMER_H
+
+/******************************************************************************/
+/** Logical Timer ID for APIs.
+ * This is the timer IDs passed to Basic Timer API function calls
+ *******************************************************************************/
+enum _PID_BTIMER_
+{
+ PID_BTIMER_0,
+ PID_BTIMER_1,
+ PID_BTIMER_2,
+ PID_BTIMER_3,
+ PID_BTIMER_4,
+ PID_BTIMER_5,
+ PID_BTIMER_MAX
+};
+
+/* ---------------------------------------------------------------------- */
+/* Logical flags for Timer Control */
+/* ---------------------------------------------------------------------- */
+//This is for tmr_cntl parameter in btimer_init function
+#define BTIMER_AUTO_RESTART (0x08u)
+#define BTIMER_ONE_SHOT (0u)
+#define BTIMER_COUNT_UP (0x04u)
+#define BTIMER_COUNT_DOWN (0u)
+#define BTIMER_INT_EN (0x01u)
+#define BTIMER_NO_INT (0u)
+/* ---------------------------------------------------------------------- */
+
+
+//Timer Block Hardware Bits and Masks
+#define BTIMER_CNTL_HALT (0x80UL)
+#define BTIMER_CNTL_RELOAD (0x40UL)
+#define BTIMER_CNTL_START (0x20UL)
+#define BTIMER_CNTL_SOFT_RESET (0x10UL)
+#define BTIMER_CNTL_AUTO_RESTART (0x08UL)
+#define BTIMER_CNTL_COUNT_UP (0x04UL)
+#define BTIMER_CNTL_ENABLE (0x01UL)
+
+#define BTIMER_CNTL_HALT_BIT (7U)
+#define BTIMER_CNTL_RELOAD_BIT (6U)
+#define BTIMER_CNTL_START_BIT (5U)
+#define BTIMER_CNTRL_SOFT_RESET_BIT (4U)
+#define BTIMER_CNTL_AUTO_RESTART_BIT (3U)
+#define BTIMER_CNTL_COUNT_DIR_BIT (2U)
+#define BTIMER_CNTL_ENABLE_BIT (0U)
+
+#define BTIMER_GIRQ MEC_GIRQ23_ID
+#define BTIMER_MAX_INSTANCE PID_BTIMER_MAX
+
+
+/* ---------------------------------------------------------------------- */
+/* API - Basic Timer Intitialization function */
+/* ---------------------------------------------------------------------- */
+
+/** Initialize specified timer
+ * @param btimer_id Basic Timer ID
+ * @param tmr_cntl Logical flags for Timer Control
+ * @param initial_count Initial Count
+ * @param preload_count Preload Count
+ * @note Performs a soft reset of the timer before configuration
+ */
+void btimer_init(uint8_t btimer_id,
+ uint16_t tmr_cntl,
+ uint16_t prescaler,
+ uint32_t initial_count,
+ uint32_t preload_count);
+
+/* ---------------------------------------------------------------------- */
+/* API - Functions to program and read the Basic Timer Counter */
+/* ---------------------------------------------------------------------- */
+/** Program timer's counter register.
+ * @param btimer_id Basic Timer ID
+ * @param count new counter value
+ * @note Timer hardware may implement a 16-bit or 32-bit
+ * hardware counter. If the timer is 16-bit only the lower
+ * 16-bits of the count paramter are used.
+ */
+void btimer_count_set(uint8_t btimer_id, uint32_t count);
+
+/** Return current value of timer's count register.
+ * @param btimer_id Basic Timer ID.
+ * @return uint32_t timer count may be 32 or 16 bits depending
+ * upon the hardware. Timers 0-3 are 16-bit
+ * and Timers 4-5 are 32-bit.
+ */
+uint32_t btimer_count_get(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/* API - Function to reload counter from Preload Register */
+/* ---------------------------------------------------------------------- */
+/** Force timer to reload counter from preload
+ * register.
+ * @param btimer_id Basic Timer ID.
+ * @note Hardware will only reload counter if timer is running.
+ */
+void btimer_reload(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/* API - Functions for stopping and starting the basic Timer */
+/* ---------------------------------------------------------------------- */
+/** Start timer counting.
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_start(uint8_t btimer_id);
+
+/** Stop timer.
+ * @param btimer_id Basic Timer ID.
+ * @note When a stopped timer is started again it will reload
+ * the count register from preload value.
+ */
+void btimer_stop(uint8_t btimer_id);
+
+/** Return state of timer's START bit.
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 0(timer not started), 1 (timer started)
+ */
+uint8_t btimer_is_started(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/* API - Function to perform basic timer soft reset */
+/* ---------------------------------------------------------------------- */
+/** Peform soft reset of specified timer.
+ * @param btimer_id Basic Timer ID
+ * @note Soft reset set all registers to POR values.
+ * Spins 256 times waiting on hardware to clear reset bit.
+ */
+void btimer_reset(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/* API - Functions to halt/unhalt the timer counting */
+/* ---------------------------------------------------------------------- */
+/** Halt timer counting with no reload on unhalt.
+ * @param btimer_id Basic Timer ID.
+ * @note A halted timer will not reload the count register when
+ * unhalted, it will continue counting from the current
+ * count value.
+ */
+void btimer_halt(uint8_t btimer_id);
+
+/** Unhalt timer counting.
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_unhalt(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/* API - Functions for Basic Timer interrupt */
+/* ---------------------------------------------------------------------- */
+/** Enable specified timer's interrupt from the block.
+ * @param btimer_id Basic Timer ID.
+ * @param ien Non-zero enable interrupt in timer block, 0
+ * disable.
+ */
+void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien);
+
+/** Read Timer interrupt status and clear if set
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 1 (Timer interrupt status set) else 0.
+ * @note If timer interrupt status is set then clear it before
+ * returning.
+ */
+uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/* API - Functions for Basic Timer GIRQ */
+/* ---------------------------------------------------------------------- */
+/** Enables GIRQ enable bit for the timer
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_enable_set(uint8_t btimer_id);
+
+/** Clears GIRQ enable bit for the timer
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_enable_clr(uint8_t btimer_id);
+
+/** Returns GIRQ source bit for the timer
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 0(src bit not set), Non-zero (src bit set)
+ */
+uint8_t btimer_girq_src_get(uint8_t btimer_id);
+
+/** Clears GIRQ source bit for the timer
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_src_clr(uint8_t btimer_id);
+
+/** Returns GIRQ result bit for the timer
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 0(result bit not set), Non-zero (result bit set)
+ */
+uint8_t btimer_girq_result_get(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/* API - Functions for Basic Timer Sleep */
+/* ---------------------------------------------------------------------- */
+/** Enable/Disable clock gating on idle of a timer
+ * @param btimer_id Basic Timer ID.
+ * @param sleep_en 1 = Sleep enable, 0 = Sleep disable
+ */
+void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en);
+
+/** Returns clk required status for the timer block
+ * @param btimer_id Basic Timer ID.
+ * @return Non-zero if clk required, else 0
+ */
+uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id);
+
+/** Enable/Disable reset on sleep for the timer block
+ * @param btimer_id Basic Timer ID.
+ * @param reset_en 1 to enable, 0 to disable
+ */
+void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions to set and read Timer Counter Register */
+/* ---------------------------------------------------------------------- */
+/** Sets timer counter
+ * @param btimer_id Basic Timer ID
+ * @param count - 32-bit counter
+ */
+void p_btimer_count_set(uint8_t btimer_id, uint32_t count);
+
+/** Read the timer counter
+ * @param btimer_id Basic Timer ID
+ * @return count - 32-bit counter
+ */
+uint32_t p_btimer_count_get(uint8_t btimer_id);
+
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Function to program the Preload */
+/* ---------------------------------------------------------------------- */
+/** Sets preload for the counter
+ * @param btimer_id Basic Timer ID
+ * @param preload_count - 32-bit pre-load value
+ */
+void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Functions - Functions for basic timer interrupts */
+/* ---------------------------------------------------------------------- */
+/** Reads the interrupt status bit in the timer block
+ * @param btimer_id Basic Timer ID
+ * @return status - 1 if interrupt status set, else 0
+ */
+uint8_t p_btimer_int_status_get(uint8_t btimer_id);
+
+/** Clears interrupt status bit in the timer block
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_int_status_clr(uint8_t btimer_id);
+
+/** Sets interrupt enable bit in the timer block
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_int_enable_set(uint8_t btimer_id);
+
+/** Clears interrupt enable bit for the timer block
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_int_enable_clr(uint8_t btimer_id);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Functions - Functions for Control Register */
+/* ---------------------------------------------------------------------- */
+/** Writes the control register 32-bits
+ * @param btimer_id Basic Timer ID
+ * @param value - 32-bit value to program
+ */
+void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value);
+
+/** Reads the control register
+ * @param btimer_id Basic Timer ID
+ * @return uint32_t - 32-bit value
+ */
+uint32_t p_btimer_ctrl_read(uint8_t btimer_id);
+
+/** Clears enable bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_enable_set(uint8_t btimer_id);
+
+/** Clears enable bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_enable_clr(uint8_t btimer_id);
+
+/** Sets counter direction bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id);
+
+/** Clears counter direction bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id);
+
+/** Sets auto restart bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id);
+
+/** Clears auto resetart bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id);
+
+/** Sets soft reset bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id);
+
+/** Read Soft Reset bit
+ * @param btimer_id Basic Timer ID
+ * @return 0 if soft reset status bit cleared; else non-zero value
+ */
+uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id);
+
+/** Sets start bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_start_set(uint8_t btimer_id);
+
+/** Read start bit in the control register
+ * @param btimer_id Basic Timer ID
+ * @return 0 if start bit not set; else non-zero value
+ */
+uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id);
+
+/** Clears start bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_start_clr(uint8_t btimer_id);
+
+/** Sets reload bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_reload_set(uint8_t btimer_id);
+
+/** Clears reload bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_reload_clr(uint8_t btimer_id);
+
+/** Sets halt bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_halt_set(uint8_t btimer_id);
+
+/** Clears halt bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+
+void p_btimer_ctrl_halt_clr(uint8_t btimer_id);
+
+/** Sets prescale value
+ * @param btimer_id Basic Timer ID
+ * @param prescaler - 16-bit pre-scale value
+ */
+void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler);
+
+
+#endif // #ifndef _BTIMER_H
+
+/* end btimer_perphl.c */
+
+/** @} //Peripherals Basic_Timer
+ */
+
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #2 $ \r
-$DateTime: 2015/11/24 06:27:00 $ \r
-$Author: amohandas $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file btimer_api.c\r
-* \brief Basic Timer APIs Source file\r
-* \author jvasanth\r
-* \r
-* This file implements the Basic Timer API functions \r
-******************************************************************************/\r
-\r
-/** @defgroup Basic_Timer\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "btimer.h"\r
-#include "..\pcr\pcr.h"\r
-\r
-/** Basic Timer Sleep Registers & Bit Positions */\r
-static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = {\r
- PCR_BTIMER0,\r
- PCR_BTIMER1,\r
- PCR_BTIMER2,\r
- PCR_BTIMER3,\r
- PCR_BTIMER4,\r
- PCR_BTIMER5\r
-};\r
-\r
-#ifdef PLIB_BTIMER_CHECK_ID\r
-\r
-/** Local helper that checks if logical Timer ID is valid. \r
- * @param btimer_id Basic Timer ID \r
- * @return uint8_t Non-zero(VALID), 0(Invalid)\r
- */\r
-static uint8_t btmr_valid(uint8_t btimer_id)\r
-{\r
- if ( btimer_id < (PID_BTIMER_MAX ) ) {\r
- return true;\r
- }\r
- return false;\r
-}\r
-\r
-#else\r
-\r
-\r
-/** This version of tmr_valid skips checking always returning 1. \r
- * Compiler may optimize it out.\r
- * @param btimer_id Basic Timer ID \r
- * @return uint8_t 1(VALID) \r
- */\r
-static uint8_t btmr_valid(uint8_t btimer_id) { return 1; }\r
-\r
-#endif\r
-\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Basic Timer Intitialization function */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Initialize specified timer\r
- * @param btimer_id Basic Timer ID\r
- * @param tmr_cntl Logical flags for Timer Control\r
- * @param initial_count Initial Count\r
- * @param preload_count Preload Count\r
- * @note Performs a soft reset of the timer before configuration \r
- */\r
-void btimer_init(uint8_t btimer_id, \r
- uint16_t tmr_cntl,\r
- uint16_t prescaler,\r
- uint32_t initial_count,\r
- uint32_t preload_count)\r
-{ \r
- uint32_t value; \r
-\r
- if (btmr_valid(btimer_id)) {\r
- \r
- btimer_reset(btimer_id); \r
- \r
- // Ungate timer clocks and program prescale\r
- value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE); \r
- p_btimer_ctrl_write(btimer_id, value);\r
- \r
- // Program Preload & initial counter value\r
- p_btimer_preload_set(btimer_id, preload_count);\r
- p_btimer_count_set(btimer_id, initial_count); \r
- \r
- // Program control register, interrupt enable, and clear status\r
- if (tmr_cntl & BTIMER_COUNT_UP) { \r
- p_btimer_ctrl_counter_dir_set(btimer_id); \r
- }\r
- if (tmr_cntl & BTIMER_AUTO_RESTART) {\r
- p_btimer_ctrl_auto_restart_set(btimer_id); \r
- } \r
- if (tmr_cntl & BTIMER_INT_EN) { \r
- p_btimer_int_enable_set(btimer_id); // enable first\r
- p_btimer_int_status_clr(btimer_id); // clear status \r
- }\r
- }\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to program and read the Basic Timer Counter */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Program timer's counter register.\r
- * @param btimer_id Basic Timer ID\r
- * @param count new counter value \r
- * @note Timer hardware may implement a 16-bit or 32-bit \r
- * hardware counter. If the timer is 16-bit only the lower\r
- * 16-bits of the count paramter are used.\r
- */\r
-void btimer_count_set(uint8_t btimer_id, uint32_t count)\r
-{\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- p_btimer_count_set(btimer_id, count); \r
- }\r
-}\r
-\r
-/** Return current value of timer's count register.\r
- * @param btimer_id Basic Timer ID. \r
- * @return uint32_t timer count may be 32 or 16 bits depending \r
- * upon the hardware. Timers 0-3 are 16-bit\r
- * and Timers 4-5 are 32-bit.\r
- */\r
-uint32_t btimer_count_get(uint8_t btimer_id)\r
-{ \r
- uint32_t cnt;\r
- \r
- cnt = 0ul;\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- cnt = p_btimer_count_get(btimer_id); \r
- }\r
- \r
- return cnt;\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to reload counter from Preload Register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Force timer to reload counter from preload \r
- * register. \r
- * @param btimer_id Basic Timer ID. \r
- * @note Hardware will only reload counter if timer is running. \r
- */\r
-void btimer_reload(uint8_t btimer_id)\r
-{\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running\r
- {\r
- p_btimer_ctrl_reload_set(btimer_id);\r
- }\r
- }\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for stopping and starting the basic Timer */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Start timer counting.\r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_start(uint8_t btimer_id)\r
-{\r
- if ( btmr_valid(btimer_id) ) {\r
- \r
- p_btimer_ctrl_start_set(btimer_id);\r
- }\r
-}\r
-\r
-/** Stop timer. \r
- * @param btimer_id Basic Timer ID. \r
- * @note When a stopped timer is started again it will reload \r
- * the count register from preload value.\r
- */\r
-void btimer_stop(uint8_t btimer_id)\r
-{\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- p_btimer_ctrl_start_clr(btimer_id); \r
- \r
- }\r
-}\r
-\r
-/** Return state of timer's START bit. \r
- * @param btimer_id Basic Timer ID. \r
- * @return uint8_t 0(timer not started), 1 (timer started)\r
- */\r
-uint8_t btimer_is_started(uint8_t btimer_id)\r
-{ \r
- uint8_t sts;\r
- \r
- sts = 0;\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- if (p_btimer_ctrl_start_get(btimer_id)) \r
- {\r
- sts = 1;\r
- } \r
- }\r
- return sts;\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to perform basic timer soft reset */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Peform soft reset of specified timer. \r
- * @param btimer_id Basic Timer ID \r
- * @note Soft reset set all registers to POR values.\r
- * Spins 256 times waiting on hardware to clear reset bit. \r
- */\r
-void btimer_reset(uint8_t btimer_id)\r
-{ \r
- uint32_t wait_cnt;\r
- uint8_t soft_reset_sts;\r
-\r
- if (btmr_valid(btimer_id)) { \r
- \r
- p_btimer_ctrl_soft_reset_set(btimer_id); \r
-\r
- wait_cnt = 256ul;\r
- do {\r
- soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id);\r
- \r
- if (0 == soft_reset_sts){ \r
- break;\r
- }\r
- } \r
- while ( wait_cnt-- ); \r
- } \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to halt/unhalt the timer counting */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Halt timer counting with no reload on unhalt. \r
- * @param btimer_id Basic Timer ID. \r
- * @note A halted timer will not reload the count register when \r
- * unhalted, it will continue counting from the current\r
- * count value.\r
- */\r
-void btimer_halt(uint8_t btimer_id)\r
-{\r
- if ( btmr_valid(btimer_id) ) {\r
- \r
- p_btimer_ctrl_halt_set(btimer_id); \r
- }\r
-}\r
-\r
-/** Unhalt timer counting. \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_unhalt(uint8_t btimer_id)\r
-{\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- p_btimer_ctrl_halt_clr(btimer_id);\r
- }\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for Basic Timer interrupt */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Enable specified timer's interrupt from the block. \r
- * @param btimer_id Basic Timer ID.\r
- * @param ien Non-zero enable interrupt in timer block, 0 \r
- * disable.\r
- */\r
-void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien)\r
-{ \r
- if (btmr_valid(btimer_id)) { \r
- \r
- p_btimer_int_enable_set(btimer_id);\r
-\r
- if (ien) {\r
- p_btimer_int_enable_set(btimer_id);\r
- } else {\r
- p_btimer_int_enable_clr(btimer_id);\r
- }\r
- }\r
-}\r
-\r
-/** Read Timer interrupt status and clear if set \r
- * @param btimer_id Basic Timer ID. \r
- * @return uint8_t 1 (Timer interrupt status set) else 0. \r
- * @note If timer interrupt status is set then clear it before \r
- * returning.\r
- */\r
-uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id)\r
-{ \r
- uint8_t sts;\r
-\r
- sts = 0;\r
- if (btmr_valid(btimer_id)) { \r
- \r
- sts = p_btimer_int_status_get(btimer_id);\r
- if (sts) {\r
- p_btimer_int_status_clr(btimer_id); \r
- }\r
- }\r
- return sts;\r
-}\r
-\r
-#if 0 //Temporary disable until interrupt module\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for Basic Timer GIRQ */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Enables GIRQ enable bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_enable_set(uint8_t btimer_id)\r
-{\r
- if (btmr_valid(btimer_id))\r
- {\r
- //Note: Bit Position is same as Timer ID \r
- p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id);\r
- } \r
-}\r
-\r
-/** Clears GIRQ enable bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_enable_clr(uint8_t btimer_id)\r
-{ \r
- if (btmr_valid(btimer_id))\r
- { \r
- //Note: Bit Position is same as Timer ID \r
- p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id);\r
- } \r
- \r
-}\r
-\r
-/** Returns GIRQ source bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- * @return uint8_t 0(src bit not set), Non-zero (src bit set)\r
- */\r
-uint8_t btimer_girq_src_get(uint8_t btimer_id)\r
-{\r
- uint8_t retVal;\r
-\r
- retVal = 0;\r
- if (btmr_valid(btimer_id))\r
- {\r
- //Note: Bit Position is same as Timer ID \r
- retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id); \r
- }\r
-\r
- return retVal;\r
-}\r
-\r
-/** Clears GIRQ source bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_src_clr(uint8_t btimer_id)\r
-{\r
- if (btmr_valid(btimer_id))\r
- {\r
- //Note: Bit Position is same as Timer ID \r
- p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id); \r
- } \r
-}\r
-\r
-/** Returns GIRQ result bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- * @return uint8_t 0(result bit not set), Non-zero (result bit set)\r
- */\r
-uint8_t btimer_girq_result_get(uint8_t btimer_id)\r
-{\r
- uint8_t retVal;\r
-\r
- retVal = 0;\r
- if (btmr_valid(btimer_id))\r
- {\r
- //Note: Bit Position is same as Timer ID \r
- retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id); \r
- }\r
-\r
- return retVal; \r
-}\r
-#endif\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for Basic Timer Sleep */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Enable/Disable clock gating on idle of a timer \r
- * @param btimer_id Basic Timer ID.\r
- * @param sleep_en 1 = Sleep enable, 0 = Sleep disable\r
- */\r
-void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en)\r
-{\r
- uint32_t pcr_blk_id;\r
- \r
- if ( btmr_valid(btimer_id) ) \r
- { \r
- pcr_blk_id = btmr_pcr_id[btimer_id]; \r
- \r
- pcr_sleep_enable(pcr_blk_id, sleep_en); \r
- }\r
-}\r
-\r
-/** Returns clk required status for the timer block\r
- * @param btimer_id Basic Timer ID.\r
- * @return Non-zero if clk required, else 0\r
- */\r
-uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id)\r
-{\r
- uint32_t retVal;\r
- uint32_t pcr_blk_id;\r
- \r
- retVal = 0ul; \r
- if ( btmr_valid(btimer_id) ) \r
- { \r
- pcr_blk_id = btmr_pcr_id[btimer_id];\r
- \r
- retVal = pcr_clock_reqd_status_get(pcr_blk_id); \r
- }\r
- \r
- return retVal;\r
-}\r
-\r
-/** Enable/Disable reset on sleep for the timer block \r
- * @param btimer_id Basic Timer ID.\r
- * @param reset_en 1 to enable, 0 to disable\r
- */\r
-void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en)\r
-{\r
- uint32_t pcr_blk_id; \r
- \r
- if ( btmr_valid(btimer_id) ) \r
- { \r
- pcr_blk_id = btmr_pcr_id[btimer_id];\r
- \r
- pcr_reset_enable(pcr_blk_id, reset_en); \r
- }\r
-}\r
-\r
-/* end btimer_api.c */\r
-\r
-/** @} //Peripheral Basic_Timer\r
- */\r
+/*****************************************************************************
+* © 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $
+$DateTime: 2016/04/08 10:18:28 $
+$Author: pramans $
+Last Change: Updated for tabs
+******************************************************************************/
+/** @file btimer_api.c
+* \brief Basic Timer APIs Source file
+* \author jvasanth
+*
+* This file implements the Basic Timer API functions
+******************************************************************************/
+
+/** @defgroup Basic_Timer
+ * @{
+ */
+
+#include "common_lib.h"
+#include "btimer.h"
+#include "..\pcr\pcr.h"
+//#include "..\interrupt\ecia.h"
+
+/** Basic Timer Sleep Registers & Bit Positions */
+static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = {
+ PCR_BTIMER0,
+ PCR_BTIMER1,
+ PCR_BTIMER2,
+ PCR_BTIMER3,
+ PCR_BTIMER4,
+ PCR_BTIMER5
+};
+
+#ifdef PLIB_BTIMER_CHECK_ID
+
+/** Local helper that checks if logical Timer ID is valid.
+ * @param btimer_id Basic Timer ID
+ * @return uint8_t Non-zero(VALID), 0(Invalid)
+ */
+static uint8_t btmr_valid(uint8_t btimer_id)
+{
+ if ( btimer_id < (PID_BTIMER_MAX ) ) {
+ return true;
+ }
+ return false;
+}
+
+#else
+
+
+/** This version of tmr_valid skips checking always returning 1.
+ * Compiler may optimize it out.
+ * @param btimer_id Basic Timer ID
+ * @return uint8_t 1(VALID)
+ */
+static uint8_t btmr_valid(uint8_t btimer_id) { return 1; }
+
+#endif
+
+
+/* ---------------------------------------------------------------------- */
+/* Basic Timer Intitialization function */
+/* ---------------------------------------------------------------------- */
+
+/** Initialize specified timer
+ * @param btimer_id Basic Timer ID
+ * @param tmr_cntl Logical flags for Timer Control
+ * @param initial_count Initial Count
+ * @param preload_count Preload Count
+ * @note Performs a soft reset of the timer before configuration
+ */
+void btimer_init(uint8_t btimer_id,
+ uint16_t tmr_cntl,
+ uint16_t prescaler,
+ uint32_t initial_count,
+ uint32_t preload_count)
+{
+ uint32_t value;
+
+ if (btmr_valid(btimer_id)) {
+
+ btimer_reset(btimer_id);
+
+ // Ungate timer clocks and program prescale
+ value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE);
+ p_btimer_ctrl_write(btimer_id, value);
+
+ // Program Preload & initial counter value
+ p_btimer_preload_set(btimer_id, preload_count);
+ p_btimer_count_set(btimer_id, initial_count);
+
+ // Program control register, interrupt enable, and clear status
+ if (tmr_cntl & BTIMER_COUNT_UP) {
+ p_btimer_ctrl_counter_dir_set(btimer_id);
+ }
+ if (tmr_cntl & BTIMER_AUTO_RESTART) {
+ p_btimer_ctrl_auto_restart_set(btimer_id);
+ }
+ if (tmr_cntl & BTIMER_INT_EN) {
+ p_btimer_int_enable_set(btimer_id); // enable first
+ p_btimer_int_status_clr(btimer_id); // clear status
+ }
+ }
+}
+
+/* ---------------------------------------------------------------------- */
+/* Functions to program and read the Basic Timer Counter */
+/* ---------------------------------------------------------------------- */
+
+/** Program timer's counter register.
+ * @param btimer_id Basic Timer ID
+ * @param count new counter value
+ * @note Timer hardware may implement a 16-bit or 32-bit
+ * hardware counter. If the timer is 16-bit only the lower
+ * 16-bits of the count paramter are used.
+ */
+void btimer_count_set(uint8_t btimer_id, uint32_t count)
+{
+ if ( btmr_valid(btimer_id) ) {
+
+ p_btimer_count_set(btimer_id, count);
+ }
+}
+
+/** Return current value of timer's count register.
+ * @param btimer_id Basic Timer ID.
+ * @return uint32_t timer count may be 32 or 16 bits depending
+ * upon the hardware. Timers 0-3 are 16-bit
+ * and Timers 4-5 are 32-bit.
+ */
+uint32_t btimer_count_get(uint8_t btimer_id)
+{
+ uint32_t cnt;
+
+ cnt = 0ul;
+ if ( btmr_valid(btimer_id) ) {
+
+ cnt = p_btimer_count_get(btimer_id);
+ }
+
+ return cnt;
+}
+
+/* ---------------------------------------------------------------------- */
+/* Function to reload counter from Preload Register */
+/* ---------------------------------------------------------------------- */
+
+/** Force timer to reload counter from preload
+ * register.
+ * @param btimer_id Basic Timer ID.
+ * @note Hardware will only reload counter if timer is running.
+ */
+void btimer_reload(uint8_t btimer_id)
+{
+ if ( btmr_valid(btimer_id) ) {
+
+ if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running
+ {
+ p_btimer_ctrl_reload_set(btimer_id);
+ }
+ }
+}
+
+/* ---------------------------------------------------------------------- */
+/* Functions for stopping and starting the basic Timer */
+/* ---------------------------------------------------------------------- */
+
+/** Start timer counting.
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_start(uint8_t btimer_id)
+{
+ if ( btmr_valid(btimer_id) ) {
+
+ p_btimer_ctrl_start_set(btimer_id);
+ }
+}
+
+/** Stop timer.
+ * @param btimer_id Basic Timer ID.
+ * @note When a stopped timer is started again it will reload
+ * the count register from preload value.
+ */
+void btimer_stop(uint8_t btimer_id)
+{
+ if ( btmr_valid(btimer_id) ) {
+
+ p_btimer_ctrl_start_clr(btimer_id);
+
+ }
+}
+
+/** Return state of timer's START bit.
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 0(timer not started), 1 (timer started)
+ */
+uint8_t btimer_is_started(uint8_t btimer_id)
+{
+ uint8_t sts;
+
+ sts = 0;
+ if ( btmr_valid(btimer_id) ) {
+
+ if (p_btimer_ctrl_start_get(btimer_id))
+ {
+ sts = 1;
+ }
+ }
+ return sts;
+}
+
+/* ---------------------------------------------------------------------- */
+/* Function to perform basic timer soft reset */
+/* ---------------------------------------------------------------------- */
+
+/** Peform soft reset of specified timer.
+ * @param btimer_id Basic Timer ID
+ * @note Soft reset set all registers to POR values.
+ * Spins 256 times waiting on hardware to clear reset bit.
+ */
+void btimer_reset(uint8_t btimer_id)
+{
+ uint32_t wait_cnt;
+ uint8_t soft_reset_sts;
+
+ if (btmr_valid(btimer_id)) {
+
+ p_btimer_ctrl_soft_reset_set(btimer_id);
+
+ wait_cnt = 256ul;
+ do {
+ soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id);
+
+ if (0 == soft_reset_sts){
+ break;
+ }
+ }
+ while ( wait_cnt-- );
+ }
+}
+
+/* ---------------------------------------------------------------------- */
+/* Functions to halt/unhalt the timer counting */
+/* ---------------------------------------------------------------------- */
+
+/** Halt timer counting with no reload on unhalt.
+ * @param btimer_id Basic Timer ID.
+ * @note A halted timer will not reload the count register when
+ * unhalted, it will continue counting from the current
+ * count value.
+ */
+void btimer_halt(uint8_t btimer_id)
+{
+ if ( btmr_valid(btimer_id) ) {
+
+ p_btimer_ctrl_halt_set(btimer_id);
+ }
+}
+
+/** Unhalt timer counting.
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_unhalt(uint8_t btimer_id)
+{
+ if ( btmr_valid(btimer_id) ) {
+
+ p_btimer_ctrl_halt_clr(btimer_id);
+ }
+}
+
+/* ---------------------------------------------------------------------- */
+/* Functions for Basic Timer interrupt */
+/* ---------------------------------------------------------------------- */
+
+/** Enable specified timer's interrupt from the block.
+ * @param btimer_id Basic Timer ID.
+ * @param ien Non-zero enable interrupt in timer block, 0
+ * disable.
+ */
+void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien)
+{
+ if (btmr_valid(btimer_id)) {
+
+ p_btimer_int_enable_set(btimer_id);
+
+ if (ien) {
+ p_btimer_int_enable_set(btimer_id);
+ } else {
+ p_btimer_int_enable_clr(btimer_id);
+ }
+ }
+}
+
+/** Read Timer interrupt status and clear if set
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 1 (Timer interrupt status set) else 0.
+ * @note If timer interrupt status is set then clear it before
+ * returning.
+ */
+uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id)
+{
+ uint8_t sts;
+
+ sts = 0;
+ if (btmr_valid(btimer_id)) {
+
+ sts = p_btimer_int_status_get(btimer_id);
+ if (sts) {
+ p_btimer_int_status_clr(btimer_id);
+ }
+ }
+ return sts;
+}
+
+#if 0 //Temporary disable until interrupt module
+
+/* ---------------------------------------------------------------------- */
+/* Functions for Basic Timer GIRQ */
+/* ---------------------------------------------------------------------- */
+
+/** Enables GIRQ enable bit for the timer
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_enable_set(uint8_t btimer_id)
+{
+ if (btmr_valid(btimer_id))
+ {
+ //Note: Bit Position is same as Timer ID
+ p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id);
+ }
+}
+
+/** Clears GIRQ enable bit for the timer
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_enable_clr(uint8_t btimer_id)
+{
+ if (btmr_valid(btimer_id))
+ {
+ //Note: Bit Position is same as Timer ID
+ p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id);
+ }
+
+}
+
+/** Returns GIRQ source bit for the timer
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 0(src bit not set), Non-zero (src bit set)
+ */
+uint8_t btimer_girq_src_get(uint8_t btimer_id)
+{
+ uint8_t retVal;
+
+ retVal = 0;
+ if (btmr_valid(btimer_id))
+ {
+ //Note: Bit Position is same as Timer ID
+ retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id);
+ }
+
+ return retVal;
+}
+
+/** Clears GIRQ source bit for the timer
+ * @param btimer_id Basic Timer ID.
+ */
+void btimer_girq_src_clr(uint8_t btimer_id)
+{
+ if (btmr_valid(btimer_id))
+ {
+ //Note: Bit Position is same as Timer ID
+ p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id);
+ }
+}
+
+/** Returns GIRQ result bit for the timer
+ * @param btimer_id Basic Timer ID.
+ * @return uint8_t 0(result bit not set), Non-zero (result bit set)
+ */
+uint8_t btimer_girq_result_get(uint8_t btimer_id)
+{
+ uint8_t retVal;
+
+ retVal = 0;
+ if (btmr_valid(btimer_id))
+ {
+ //Note: Bit Position is same as Timer ID
+ retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id);
+ }
+
+ return retVal;
+}
+#endif
+
+/* ---------------------------------------------------------------------- */
+/* Functions for Basic Timer Sleep */
+/* ---------------------------------------------------------------------- */
+
+/** Enable/Disable clock gating on idle of a timer
+ * @param btimer_id Basic Timer ID.
+ * @param sleep_en 1 = Sleep enable, 0 = Sleep disable
+ */
+void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en)
+{
+ uint32_t pcr_blk_id;
+
+ if ( btmr_valid(btimer_id) )
+ {
+ pcr_blk_id = btmr_pcr_id[btimer_id];
+
+ pcr_sleep_enable(pcr_blk_id, sleep_en);
+ }
+}
+
+/** Returns clk required status for the timer block
+ * @param btimer_id Basic Timer ID.
+ * @return Non-zero if clk required, else 0
+ */
+uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id)
+{
+ uint32_t retVal;
+ uint32_t pcr_blk_id;
+
+ retVal = 0ul;
+ if ( btmr_valid(btimer_id) )
+ {
+ pcr_blk_id = btmr_pcr_id[btimer_id];
+
+ retVal = pcr_clock_reqd_status_get(pcr_blk_id);
+ }
+
+ return retVal;
+}
+
+/** Enable/Disable reset on sleep for the timer block
+ * @param btimer_id Basic Timer ID.
+ * @param reset_en 1 to enable, 0 to disable
+ */
+void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en)
+{
+ uint32_t pcr_blk_id;
+
+ if ( btmr_valid(btimer_id) )
+ {
+ pcr_blk_id = btmr_pcr_id[btimer_id];
+
+ pcr_reset_enable(pcr_blk_id, reset_en);
+ }
+}
+
+/* end btimer_api.c */
+
+/** @} //Peripheral Basic_Timer
+ */
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #2 $ \r
-$DateTime: 2015/11/24 06:27:00 $ \r
-$Author: amohandas $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file btimer_perphl.c\r
-* \brief Basic Timer Peripheral Source file\r
-* \author jvasanth\r
-* \r
-* This file implements the Basic Timer Peripheral functions \r
-******************************************************************************/\r
-\r
-/** @defgroup Basic_Timer\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "btimer.h"\r
-\r
-/** Basic Timer Instance base addresses */\r
-static TIMER_16_0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = {\r
- CEC1302_TIMER_16_0,\r
- CEC1302_TIMER_16_1,\r
- CEC1302_TIMER_16_2,\r
- CEC1302_TIMER_16_3,\r
- CEC1302_TIMER_32_0,\r
- CEC1302_TIMER_32_1\r
-};\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to set and read Timer Counter Register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Sets timer counter\r
- * @param btimer_id Basic Timer ID\r
- * @param count - 32-bit counter \r
- */\r
-void p_btimer_count_set(uint8_t btimer_id, uint32_t count)\r
-{\r
- btmr_inst[btimer_id]->COUNT = count; \r
-}\r
-\r
-/** Read the timer counter\r
- * @param btimer_id Basic Timer ID\r
- * @return count - 32-bit counter \r
- */\r
-uint32_t p_btimer_count_get(uint8_t btimer_id)\r
-{ \r
- return btmr_inst[btimer_id]->COUNT; \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to program the Preload */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Sets preload for the counter\r
- * @param btimer_id Basic Timer ID\r
- * @param preload_count - 32-bit pre-load value \r
- */\r
-void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count)\r
-{\r
- btmr_inst[btimer_id]->PRE_LOAD = preload_count; \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for basic timer interrupts */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Reads the interrupt status bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- * @return status - 1 if interrupt status set, else 0\r
- */\r
-uint8_t p_btimer_int_status_get(uint8_t btimer_id)\r
-{\r
- return (uint8_t)(btmr_inst[btimer_id]->INTERRUPT_STATUS);\r
-}\r
-\r
-/** Clears interrupt status bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_status_clr(uint8_t btimer_id)\r
-{\r
- // Write 1 to clear\r
- btmr_inst[btimer_id]->INTERRUPT_STATUS = 1;\r
-}\r
-\r
-/** Sets interrupt enable bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_enable_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->INTERRUPT_ENABLE = 1;\r
-}\r
-\r
-/** Clears interrupt enable bit for the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_enable_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->INTERRUPT_ENABLE = 0;\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for Control Register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Writes the control register 32-bits\r
- * @param btimer_id Basic Timer ID\r
- * @param value - 32-bit value to program\r
- */\r
-void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.w = value;\r
-}\r
-\r
-/** Reads the control register \r
- * @param btimer_id Basic Timer ID\r
- * @return uint32_t - 32-bit value\r
- */\r
-uint32_t p_btimer_ctrl_read(uint8_t btimer_id)\r
-{ \r
- uint32_t retVal;\r
-\r
- retVal = btmr_inst[btimer_id]->CONTROL.w;\r
-\r
- return retVal;\r
-}\r
-\r
-/** Sets enable bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_enable_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE;\r
-}\r
-\r
-/** Clears enable bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_enable_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE;\r
-}\r
-\r
-/** Sets counter direction bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP;\r
-}\r
-\r
-/** Clears counter direction bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP;\r
-}\r
-\r
-/** Sets auto restart bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART;\r
-}\r
-\r
-/** Clears auto resetart bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART;\r
-}\r
-\r
-/** Sets soft reset bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET;\r
-}\r
-\r
-/** Read Soft Reset bit \r
- * @param btimer_id Basic Timer ID\r
- * @return 0 if soft reset status bit cleared; else non-zero value\r
- */\r
-uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id)\r
-{ \r
- return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET);\r
-}\r
-\r
-/** Sets start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_start_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START;\r
-}\r
-\r
-/** Read start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- * @return 0 if start bit not set; else non-zero value\r
- */\r
-uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id)\r
-{ \r
- return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START);\r
-}\r
-\r
-/** Clears start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_start_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START;\r
-}\r
-\r
-/** Sets reload bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_reload_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD;\r
-}\r
-\r
-/** Clears reload bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_reload_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD;\r
-}\r
-\r
-/** Sets halt bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_halt_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT;\r
-}\r
-\r
-/** Clears halt bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_halt_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT;\r
-}\r
-\r
-/** Sets prescale value\r
- * @param btimer_id Basic Timer ID\r
- * @param prescaler - 16-bit pre-scale value \r
- */\r
-void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.h[1] = prescaler;\r
-}\r
-\r
-\r
-/* end btimer_perphl.c */\r
-\r
-/** @} //Peripheral Basic_Timer\r
- */\r
-\r
+/*****************************************************************************
+* © 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $
+$DateTime: 2016/04/08 10:18:28 $
+$Author: pramans $
+Last Change: Updated for tabs
+******************************************************************************/
+/** @file btimer_perphl.c
+* \brief Basic Timer Peripheral Source file
+* \author jvasanth
+*
+* This file implements the Basic Timer Peripheral functions
+******************************************************************************/
+
+/** @defgroup Basic_Timer
+ * @{
+ */
+
+#include "common_lib.h"
+#include "btimer.h"
+
+/** Basic Timer Instance base addresses */
+static TIMER_16_0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = {
+ CEC1302_TIMER_16_0,
+ CEC1302_TIMER_16_1,
+ CEC1302_TIMER_16_2,
+ CEC1302_TIMER_16_3,
+ CEC1302_TIMER_32_0,
+ CEC1302_TIMER_32_1
+};
+
+/* ---------------------------------------------------------------------- */
+/* Functions to set and read Timer Counter Register */
+/* ---------------------------------------------------------------------- */
+
+/** Sets timer counter
+ * @param btimer_id Basic Timer ID
+ * @param count - 32-bit counter
+ */
+void p_btimer_count_set(uint8_t btimer_id, uint32_t count)
+{
+ btmr_inst[btimer_id]->COUNT = count;
+}
+
+/** Read the timer counter
+ * @param btimer_id Basic Timer ID
+ * @return count - 32-bit counter
+ */
+uint32_t p_btimer_count_get(uint8_t btimer_id)
+{
+ return btmr_inst[btimer_id]->COUNT;
+}
+
+/* ---------------------------------------------------------------------- */
+/* Function to program the Preload */
+/* ---------------------------------------------------------------------- */
+
+/** Sets preload for the counter
+ * @param btimer_id Basic Timer ID
+ * @param preload_count - 32-bit pre-load value
+ */
+void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count)
+{
+ btmr_inst[btimer_id]->PRE_LOAD = preload_count;
+}
+
+/* ---------------------------------------------------------------------- */
+/* Functions for basic timer interrupts */
+/* ---------------------------------------------------------------------- */
+
+/** Reads the interrupt status bit in the timer block
+ * @param btimer_id Basic Timer ID
+ * @return status - 1 if interrupt status set, else 0
+ */
+uint8_t p_btimer_int_status_get(uint8_t btimer_id)
+{
+ return (uint8_t)(btmr_inst[btimer_id]->INTERRUPT_STATUS);
+}
+
+/** Clears interrupt status bit in the timer block
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_int_status_clr(uint8_t btimer_id)
+{
+ // Write 1 to clear
+ btmr_inst[btimer_id]->INTERRUPT_STATUS = 1;
+}
+
+/** Sets interrupt enable bit in the timer block
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_int_enable_set(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->INTERRUPT_ENABLE = 1;
+}
+
+/** Clears interrupt enable bit for the timer block
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_int_enable_clr(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->INTERRUPT_ENABLE = 0;
+}
+
+/* ---------------------------------------------------------------------- */
+/* Functions for Control Register */
+/* ---------------------------------------------------------------------- */
+
+/** Writes the control register 32-bits
+ * @param btimer_id Basic Timer ID
+ * @param value - 32-bit value to program
+ */
+void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value)
+{
+ btmr_inst[btimer_id]->CONTROL.w = value;
+}
+
+/** Reads the control register
+ * @param btimer_id Basic Timer ID
+ * @return uint32_t - 32-bit value
+ */
+uint32_t p_btimer_ctrl_read(uint8_t btimer_id)
+{
+ uint32_t retVal;
+
+ retVal = btmr_inst[btimer_id]->CONTROL.w;
+
+ return retVal;
+}
+
+/** Sets enable bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_enable_set(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE;
+}
+
+/** Clears enable bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_enable_clr(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE;
+}
+
+/** Sets counter direction bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP;
+}
+
+/** Clears counter direction bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP;
+}
+
+/** Sets auto restart bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART;
+}
+
+/** Clears auto resetart bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART;
+}
+
+/** Sets soft reset bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET;
+}
+
+/** Read Soft Reset bit
+ * @param btimer_id Basic Timer ID
+ * @return 0 if soft reset status bit cleared; else non-zero value
+ */
+uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id)
+{
+ return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET);
+}
+
+/** Sets start bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_start_set(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START;
+}
+
+/** Read start bit in the control register
+ * @param btimer_id Basic Timer ID
+ * @return 0 if start bit not set; else non-zero value
+ */
+uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id)
+{
+ return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START);
+}
+
+/** Clears start bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_start_clr(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START;
+}
+
+/** Sets reload bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_reload_set(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD;
+}
+
+/** Clears reload bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_reload_clr(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD;
+}
+
+/** Sets halt bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_halt_set(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT;
+}
+
+/** Clears halt bit in the control register
+ * @param btimer_id Basic Timer ID
+ */
+void p_btimer_ctrl_halt_clr(uint8_t btimer_id)
+{
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT;
+}
+
+/** Sets prescale value
+ * @param btimer_id Basic Timer ID
+ * @param prescaler - 16-bit pre-scale value
+ */
+void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler)
+{
+ btmr_inst[btimer_id]->CONTROL.h[1] = prescaler;
+}
+
+
+/* end btimer_perphl.c */
+
+/** @} //Peripheral Basic_Timer
+ */
+
-/*\r
- **********************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
- **********************************************************************************\r
- * common.h\r
- * This is the header file including common headers from various modules\r
- **********************************************************************************\r
- * $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $\r
- * Description: added ict module\r
- **********************************************************************************\r
- * #xx\r
- **********************************************************************************\r
- * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common.h $\r
- */\r
-\r
-/*********************************************************************************/\r
-/** @defgroup common common\r
- * @{\r
- */\r
-\r
-/** @file common.h\r
-* \brief header file including common headers from various modules\r
-* \author App Firmware Team\r
-* \r
-**********************************************************************************/\r
-#ifndef _COMMON_H_\r
-#define _COMMON_H_\r
-\r
-// Include common headers from various modules\r
-// !!! The include order is important !!!\r
-#include "cfg.h"\r
-#include "platform.h"\r
-#include "MCHP_CEC1302.h"\r
-#include "ARM_REG.h"\r
-/* Cortex-M4 processor and core peripherals */\r
-#include "core_cm4.h" \r
-#include "MEC1322.h"\r
-\r
-#include "defs.h"\r
-#include "string.h"\r
-\r
-#include "kernel.h"\r
-#include "..\system\system.h"\r
-#include "..\debug\trace.h"\r
-#include "..\interrupt\interrupt.h"\r
-#include "..\timer\timer_app.h"\r
-\r
-#include "cec1302_crypto_api.h"\r
-\r
-#endif /*_COMMON_H_*/\r
-\r
-/** @}\r
- */\r
-\r
-\r
+/*
+ **********************************************************************************
+* © 2013 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+ **********************************************************************************
+ * common.h
+ * This is the header file including common headers from various modules
+ **********************************************************************************
+ * $Revision: #1 $ $DateTime: 2016/04/08 10:18:28 $ $ $
+ * Description: added ict module
+ **********************************************************************************
+ * #xx
+ **********************************************************************************
+ * $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/common.h $
+ */
+
+/*********************************************************************************/
+/** @defgroup common common
+ * @{
+ */
+
+/** @file common.h
+* \brief header file including common headers from various modules
+* \author App Firmware Team
+*
+**********************************************************************************/
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+// Include common headers from various modules
+// !!! The include order is important !!!
+#include "cfg.h"
+#include "platform.h"
+#include "MCHP_CEC1302.h"
+#include "ARM_REG.h"
+/* Cortex-M4 processor and core peripherals */
+#include "core_cm4.h"
+
+#include "defs.h"
+#include "string.h"
+
+#include "kernel.h"
+#include "..\system\system.h"
+#include "..\debug\trace.h"
+#include "..\interrupt\irqhandler.h"
+#include "..\timer\timer_app.h"
+
+#include "cec1302_crypto_api.h"
+
+#endif /*_COMMON_H_*/
+
+/** @}
+ */
+
+
-/*\r
- **********************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
- **********************************************************************************\r
- * common.h\r
- * This is the header file including common headers from various modules\r
- **********************************************************************************\r
- * $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $\r
- * Description: added ict module\r
- **********************************************************************************\r
- * #xx\r
- **********************************************************************************\r
- * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common_lib.h $\r
- */\r
-\r
-/*********************************************************************************/\r
-/** @defgroup common common\r
- * @{\r
- */\r
-\r
-/** @file common.h\r
-* \brief header file including common headers from various modules\r
-* \author App Firmware Team\r
-* \r
-**********************************************************************************/\r
-#ifndef _COMMON_LIB_H_\r
-#define _COMMON_LIB_H_\r
-\r
-// Include common headers from various modules\r
-// !!! The include order is important !!!\r
-#include "platform.h"\r
-#include "ARM_REG.h"\r
-#include "MCHP_CEC1302.h"\r
-/* Cortex-M4 processor and core peripherals */\r
-#include "core_cm4.h" \r
-#include "MEC1322.h"\r
-#include "defs.h"\r
-#include "string.h"\r
-//_RB_#include "build.h"\r
-//_RB_#include "..\system\system.h"\r
-//_RB_#include "..\debug\trace.h"\r
-#include <stdbool.h>\r
-#endif /*_COMMON_LIB_H_*/\r
-\r
-/** @}\r
- */\r
-\r
-\r
+/*
+ **********************************************************************************
+* © 2013 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+ **********************************************************************************
+ * common.h
+ * This is the header file including common headers from various modules
+ **********************************************************************************
+ * $Revision: #1 $ $DateTime: 2016/04/08 10:18:28 $ $ $
+ * Description: added ict module
+ **********************************************************************************
+ * #xx
+ **********************************************************************************
+ * $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/common_lib.h $
+ */
+
+/*********************************************************************************/
+/** @defgroup common common
+ * @{
+ */
+
+/** @file common.h
+* \brief header file including common headers from various modules
+* \author App Firmware Team
+*
+**********************************************************************************/
+#ifndef _COMMON_LIB_H_
+#define _COMMON_LIB_H_
+
+// Include common headers from various modules
+// !!! The include order is important !!!
+#include "platform.h"
+#include "ARM_REG.h"
+#include "MCHP_CEC1302.h"
+/* Cortex-M4 processor and core peripherals */
+#include "core_cm4.h"
+#include "defs.h"
+#include "string.h"
+//#include "build.h"
+//#include "..\system\system.h"
+//#include "..\debug\trace.h"
+#include <stdbool.h>
+#endif /*_COMMON_LIB_H_*/
+
+/** @}
+ */
+
+
-/*\r
- **********************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
- **********************************************************************************\r
- * defs.h\r
- * This is the definition header file for generic usages\r
- **********************************************************************************\r
- * #xx\r
- **********************************************************************************\r
- * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/defs.h $\r
- */\r
-\r
-\r
-/*********************************************************************************/\r
-/** @defgroup defs defs\r
- * @{\r
- */\r
-\r
-/** @file defs.h\r
-* \brief definition header file for generic usages\r
-* \author App Firmware Team\r
-* \r
-**********************************************************************************/\r
-#ifndef _DEFS_H_\r
-#define _DEFS_H_\r
-\r
-/* bit operation MACRO, xvar could be byte, word or dword */\r
-#define mSET_BIT(x, xvar) ( xvar |= x )\r
-#define mCLR_BIT(x, xvar) ( xvar &= ~x )\r
-#define mGET_BIT(x, xvar) ( xvar & x )\r
-#define mCLR_SRC_BIT(x, xvar) ( xvar = x )\r
-#define mTOGGLE_BIT(x, xvar) {if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}}\r
-\r
-#endif /*_DEFS_H_*/\r
-\r
-/** @}\r
- */\r
-\r
+/*
+ **********************************************************************************
+* © 2013 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+ **********************************************************************************
+ * defs.h
+ * This is the definition header file for generic usages
+ **********************************************************************************
+ * #xx
+ **********************************************************************************
+ * $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/defs.h $
+ */
+
+
+/*********************************************************************************/
+/** @defgroup defs defs
+ * @{
+ */
+
+/** @file defs.h
+* \brief definition header file for generic usages
+* \author App Firmware Team
+*
+**********************************************************************************/
+#ifndef _DEFS_H_
+#define _DEFS_H_
+
+/* bit operation MACRO, xvar could be byte, word or dword */
+#define mSET_BIT(x, xvar) ( xvar |= x )
+#define mCLR_BIT(x, xvar) ( xvar &= ~x )
+#define mGET_BIT(x, xvar) ( xvar & x )
+#define mCLR_SRC_BIT(x, xvar) ( xvar = x )
+#define mTOGGLE_BIT(x, xvar) {if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}}
+
+#endif /*_DEFS_H_*/
+
+/** @}
+ */
+
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/12/17 01:09:00 $ \r
-$Author: snakka $\r
-Last Change: Updated for peripheral functions prefix p_\r
-******************************************************************************/\r
-/** @file btimer.h\r
-* \brief Hibernation Timer Peripheral Header file\r
-* \author jvasanth\r
-* \r
-* This file is the header file for Hibernation Timer Peripheral \r
-******************************************************************************/\r
-\r
-/** @defgroup Hibernation_Timer\r
- * @{\r
- */\r
-\r
-#ifndef _HTIMER_H\r
-#define _HTIMER_H\r
-\r
-/******************************************************************************/\r
-/** Logical Timer ID for APIs.\r
- * This is the timer IDs passed to Hibernation Timer function calls \r
- *******************************************************************************/\r
-enum _PID_HTIMER_\r
-{\r
- PID_HTIMER_0, \r
- PID_HTIMER_MAX \r
-};\r
-\r
-#define HTIMER_MAX_INSTANCE PID_HTIMER_MAX\r
-\r
-/* -------------------------------------------------------------------- */\r
-/* Hibernation Timer APIs */\r
-/* -------------------------------------------------------------------- */\r
-/** Enables hibernation timer\r
- * @param htimer_id Hibernation Timer ID\r
- * @param preload_value - 16-bit preload value \r
- * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
- * 1 - resolution of 0.125s per LSB\r
- */\r
-void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode);\r
-\r
-/** Disables the hibernation timer by programming the prelaod value as 0\r
- * @param htimer_id Hibernation Timer ID \r
- */\r
-void htimer_disable(uint8_t htimer_id);\r
-\r
-\r
-/** Reloads new preload value for the hibernation timer\r
- * @param htimer_id Hibernation Timer ID\r
- * @param reload_value - 16-bit preload value \r
- */\r
-void htimer_reload(uint8_t htimer_id, uint16_t reload_value);\r
-\r
-\r
-/* -------------------------------------------------------------------- */\r
-/* Hibernation Timer Peripheral Functions */\r
-/* -------------------------------------------------------------------- */\r
-/** Sets hibernation timer preload value\r
- * @param htimer_id Hibernation Timer ID\r
- * @param preload_value - 16-bit preload value \r
- */\r
-void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value);\r
-\r
-/*_RB_ Added by RB. */\r
-uint16_t p_htimer_preload_get(uint8_t htimer_id);\r
-\r
-/** Sets hibernation timer resolution\r
- * @param htimer_id Hibernation Timer ID\r
- * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
- * 1 - resolution of 0.125s per LSB\r
- */\r
-void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode);\r
-\r
-\r
-/** Returns the Hibernation Timer current count value\r
- * @param htimer_id Hibernation Timer ID\r
- * @return 16-bit count value \r
- */\r
-uint16_t p_htimer_count_get(uint8_t htimer_id);\r
-\r
-\r
-#endif // #ifndef _HTIMER_H\r
-\r
-/* end htimer.h */\r
-\r
-/** @} //Peripherals Hibernation_Timer\r
- */\r
-\r
+/*****************************************************************************
+* © 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $
+$DateTime: 2016/04/08 10:18:28 $
+$Author: pramans $
+Last Change: Updated for peripheral functions prefix p_
+******************************************************************************/
+/** @file btimer.h
+* \brief Hibernation Timer Peripheral Header file
+* \author jvasanth
+*
+* This file is the header file for Hibernation Timer Peripheral
+******************************************************************************/
+
+/** @defgroup Hibernation_Timer
+ * @{
+ */
+
+#ifndef _HTIMER_H
+#define _HTIMER_H
+
+/******************************************************************************/
+/** Logical Timer ID for APIs.
+ * This is the timer IDs passed to Hibernation Timer function calls
+ *******************************************************************************/
+enum _PID_HTIMER_
+{
+ PID_HTIMER_0,
+ PID_HTIMER_MAX
+};
+
+#define HTIMER_MAX_INSTANCE PID_HTIMER_MAX
+
+/* -------------------------------------------------------------------- */
+/* Hibernation Timer APIs */
+/* -------------------------------------------------------------------- */
+/** Enables hibernation timer
+ * @param htimer_id Hibernation Timer ID
+ * @param preload_value - 16-bit preload value
+ * @param resolution_mode 0 - resolution of 30.5us per LSB,
+ * 1 - resolution of 0.125s per LSB
+ */
+void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode);
+
+/** Disables the hibernation timer by programming the prelaod value as 0
+ * @param htimer_id Hibernation Timer ID
+ */
+void htimer_disable(uint8_t htimer_id);
+
+
+/** Reloads new preload value for the hibernation timer
+ * @param htimer_id Hibernation Timer ID
+ * @param reload_value - 16-bit preload value
+ */
+void htimer_reload(uint8_t htimer_id, uint16_t reload_value);
+
+
+/* -------------------------------------------------------------------- */
+/* Hibernation Timer Peripheral Functions */
+/* -------------------------------------------------------------------- */
+/** Sets hibernation timer preload value
+ * @param htimer_id Hibernation Timer ID
+ * @param preload_value - 16-bit preload value
+ */
+void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value);
+
+/** Sets hibernation timer resolution
+ * @param htimer_id Hibernation Timer ID
+ * @param resolution_mode 0 - resolution of 30.5us per LSB,
+ * 1 - resolution of 0.125s per LSB
+ */
+void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode);
+
+
+/** Returns the Hibernation Timer current count value
+ * @param htimer_id Hibernation Timer ID
+ * @return 16-bit count value
+ */
+uint16_t p_htimer_count_get(uint8_t htimer_id);
+
+
+#endif // #ifndef _HTIMER_H
+
+/* end htimer.h */
+
+/** @} //Peripherals Hibernation_Timer
+ */
+
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/12/17 01:09:00 $ \r
-$Author: snakka $\r
-Last Change: Updated for peripheral functions prefix p_\r
-******************************************************************************/\r
-/** @file btimer_perphl.c\r
-* \brief Hibernation Timer API Source file\r
-* \author jvasanth\r
-* \r
-* This file implements Hibernation Timer APIs \r
-******************************************************************************/\r
-\r
-/** @defgroup Hibernation_Timer\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "htimer.h"\r
-\r
-#ifdef PLIB_HTIMER_CHECK_ID\r
-\r
-/** Local helper that checks if logical Timer ID is valid. \r
- * @param htimer_id Hibernation Timer ID \r
- * @return uint8_t Non-zero(VALID), 0(Invalid)\r
- */\r
-static uint8_t htmr_valid(uint8_t htimer_id)\r
-{\r
- if ( htimer_id < (PID_HTIMER_MAX ) ) {\r
- return 1;\r
- }\r
- return 0;\r
-}\r
-\r
-#else\r
-\r
-\r
-/** This version of tmr_valid skips checking always returning 1. \r
- * Compiler may optimize it out.\r
- * @param htimer_id Hibernation Timer ID\r
- * @return uint8_t 1(VALID) \r
- */\r
-static uint8_t htmr_valid(uint8_t htimer_id) { return 1; }\r
-\r
-#endif\r
-\r
-\r
-/** Enables hibernation timer\r
- * @param htimer_id Hibernation Timer ID\r
- * @param preload_value - 16-bit preload value \r
- * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
- * 1 - resolution of 0.125s per LSB\r
- */\r
-void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode)\r
-{\r
- if (htmr_valid(htimer_id)) \r
- {\r
- p_htimer_preload_set(htimer_id, preload_value);\r
- \r
- p_htimer_resolution_set(htimer_id, resolution_mode);\r
- } \r
-}\r
-\r
-/** Disables the hibernation timer by programming the prelaod value as 0\r
- * @param htimer_id Hibernation Timer ID \r
- */\r
-void htimer_disable(uint8_t htimer_id)\r
-{ \r
- if (htmr_valid(htimer_id)) \r
- {\r
- p_htimer_preload_set(htimer_id, 0);\r
- } \r
-}\r
-\r
-/** Reloads new preload value for the hibernation timer\r
- * @param htimer_id Hibernation Timer ID\r
- * @param reload_value - 16-bit preload value \r
- */\r
-void htimer_reload(uint8_t htimer_id, uint16_t reload_value)\r
-{ \r
- if ( htmr_valid(htimer_id)) \r
- {\r
- p_htimer_preload_set(htimer_id, reload_value);\r
- } \r
-}\r
-\r
-/* end htimer_api.c */\r
-\r
-/** @} //APIs Hibernation_Timer\r
- */\r
-\r
+/*****************************************************************************
+* © 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $
+$DateTime: 2016/04/08 10:18:28 $
+$Author: pramans $
+Last Change: Updated for peripheral functions prefix p_
+******************************************************************************/
+/** @file btimer_perphl.c
+* \brief Hibernation Timer API Source file
+* \author jvasanth
+*
+* This file implements Hibernation Timer APIs
+******************************************************************************/
+
+/** @defgroup Hibernation_Timer
+ * @{
+ */
+
+#include "common_lib.h"
+#include "htimer.h"
+
+#ifdef PLIB_HTIMER_CHECK_ID
+
+/** Local helper that checks if logical Timer ID is valid.
+ * @param htimer_id Hibernation Timer ID
+ * @return uint8_t Non-zero(VALID), 0(Invalid)
+ */
+static uint8_t htmr_valid(uint8_t htimer_id)
+{
+ if ( htimer_id < (PID_HTIMER_MAX ) ) {
+ return 1;
+ }
+ return 0;
+}
+
+#else
+
+
+/** This version of tmr_valid skips checking always returning 1.
+ * Compiler may optimize it out.
+ * @param htimer_id Hibernation Timer ID
+ * @return uint8_t 1(VALID)
+ */
+static uint8_t htmr_valid(uint8_t htimer_id) { return 1; }
+
+#endif
+
+
+/** Enables hibernation timer
+ * @param htimer_id Hibernation Timer ID
+ * @param preload_value - 16-bit preload value
+ * @param resolution_mode 0 - resolution of 30.5us per LSB,
+ * 1 - resolution of 0.125s per LSB
+ */
+void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode)
+{
+ if (htmr_valid(htimer_id))
+ {
+ p_htimer_preload_set(htimer_id, preload_value);
+
+ p_htimer_resolution_set(htimer_id, resolution_mode);
+ }
+}
+
+/** Disables the hibernation timer by programming the prelaod value as 0
+ * @param htimer_id Hibernation Timer ID
+ */
+void htimer_disable(uint8_t htimer_id)
+{
+ if (htmr_valid(htimer_id))
+ {
+ p_htimer_preload_set(htimer_id, 0);
+ }
+}
+
+/** Reloads new preload value for the hibernation timer
+ * @param htimer_id Hibernation Timer ID
+ * @param reload_value - 16-bit preload value
+ */
+void htimer_reload(uint8_t htimer_id, uint16_t reload_value)
+{
+ if ( htmr_valid(htimer_id))
+ {
+ p_htimer_preload_set(htimer_id, reload_value);
+ }
+}
+
+/* end htimer_api.c */
+
+/** @} //APIs Hibernation_Timer
+ */
+
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/12/17 01:09:00 $ \r
-$Author: snakka $\r
-Last Change: Updated for peripheral functions prefix p_\r
-******************************************************************************/\r
-/** @file btimer_perphl.c\r
-* \brief Hibernation Timer Peripheral Source file\r
-* \author jvasanth\r
-* \r
-* This file implements Hibernation Timer Peripheral functions \r
-******************************************************************************/\r
-\r
-/** @defgroup Hibernation_Timer\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "htimer.h"\r
-\r
-/** Hibernation Timer Instance base addresses */\r
-static HTM_Type * const htmr_inst[HTIMER_MAX_INSTANCE] = {\r
- CEC1302_HTM \r
-};\r
-\r
-/** Sets hibernation timer preload value\r
- * @param htimer_id Hibernation Timer ID\r
- * @param preload_value - 16-bit preload value \r
- * @note Setting the preload with a non-zero value starts \r
- * the hibernation timer to down count. Setting the preload \r
- * to 0 disables the hibernation counter\r
- */\r
-void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value)\r
-{\r
- htmr_inst[htimer_id]->PRELOAD = preload_value; \r
-}\r
-\r
-/** Sets hibernation timer resolution\r
- * @param htimer_id Hibernation Timer ID\r
- * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
- * 1 - resolution of 0.125s per LSB\r
- */\r
-void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode)\r
-{\r
- htmr_inst[htimer_id]->CONTROL = resolution_mode; \r
-}\r
-\r
-/** Returns the Hibernation Timer current count value\r
- * @param htimer_id Hibernation Timer ID\r
- * @return 16-bit count value \r
- */\r
-uint16_t p_htimer_count_get(uint8_t htimer_id)\r
-{\r
- uint16_t htimer_count;\r
- \r
- htimer_count = htmr_inst[htimer_id]->COUNT;\r
- \r
- return htimer_count;\r
-}\r
-\r
-/*_RB_ Added by RB. */\r
-uint16_t p_htimer_preload_get(uint8_t htimer_id)\r
-{\r
- return htmr_inst[htimer_id]->PRELOAD;\r
-}\r
-\r
-\r
-/* end htimer_perphl.c */\r
-\r
-/** @} //Peripheral Hibernation_Timer\r
- */\r
-\r
+/*****************************************************************************
+* © 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $
+$DateTime: 2016/04/08 10:18:28 $
+$Author: pramans $
+Last Change: Updated for peripheral functions prefix p_
+******************************************************************************/
+/** @file btimer_perphl.c
+* \brief Hibernation Timer Peripheral Source file
+* \author jvasanth
+*
+* This file implements Hibernation Timer Peripheral functions
+******************************************************************************/
+
+/** @defgroup Hibernation_Timer
+ * @{
+ */
+
+#include "common_lib.h"
+#include "htimer.h"
+
+/** Hibernation Timer Instance base addresses */
+static HTM_Type * const htmr_inst[HTIMER_MAX_INSTANCE] = {
+ CEC1302_HTM
+};
+
+/** Sets hibernation timer preload value
+ * @param htimer_id Hibernation Timer ID
+ * @param preload_value - 16-bit preload value
+ * @note Setting the preload with a non-zero value starts
+ * the hibernation timer to down count. Setting the preload
+ * to 0 disables the hibernation counter
+ */
+void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value)
+{
+ htmr_inst[htimer_id]->PRELOAD = preload_value;
+}
+
+/** Sets hibernation timer resolution
+ * @param htimer_id Hibernation Timer ID
+ * @param resolution_mode 0 - resolution of 30.5us per LSB,
+ * 1 - resolution of 0.125s per LSB
+ */
+void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode)
+{
+ htmr_inst[htimer_id]->CONTROL = resolution_mode;
+}
+
+/** Returns the Hibernation Timer current count value
+ * @param htimer_id Hibernation Timer ID
+ * @return 16-bit count value
+ */
+uint16_t p_htimer_count_get(uint8_t htimer_id)
+{
+ uint16_t htimer_count;
+
+ htimer_count = htmr_inst[htimer_id]->COUNT;
+
+ return htimer_count;
+}
+
+
+/* end htimer_perphl.c */
+
+/** @} //Peripheral Hibernation_Timer
+ */
+
-/****************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-*/\r
-\r
-/** @defgroup interrupt interrupt\r
- * @{\r
- */\r
-/** @file interrupt.h\r
- \brief This is the header file for interrupt.c\r
- This program is designed to allow the other C programs to be able to use this component\r
-\r
- There are entry points for all C wrapper API implementation\r
-\r
-<b>Platform:</b> This is ARC-based component \r
-\r
-<b>Toolset:</b> Metaware IDE(8.5.1)\r
-<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
-\r
-/*******************************************************************************\r
- * SMSC version control information (Perforce):\r
- *\r
- * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/kernel/skern/source/interrupt/interrupt.h $\r
- * REVISION: $Revision: #1 $\r
- * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
- * AUTHOR: $Author: akrishnan $\r
- *\r
- * Revision history (latest first):\r
- * #xx\r
- ***********************************************************************************\r
- */\r
-\r
-#ifndef _INTERRUPT_H_\r
-#define _INTERRUPT_H_\r
-\r
-\r
-/* public function prototypes */\r
-void interrupt_block_init(void);\r
-void null_handler(void);\r
-\r
-/* macro for interrupt control */\r
-/* 16-bit timers interrupt control */\r
-#define sbit_TIMER0 ( 1UL << 0UL )\r
-#define sbit_TIMER1 ( 1UL << 1UL )\r
-#define sbit_TIMER2 ( 1UL << 2UL )\r
-#define sbit_TIMER3 ( 1UL << 3Ul )\r
-\r
-#define disable_timer0_irq() mCLR_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_timer0_irq() mSET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_timer0_source() mCLR_SRC_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_timer0_source() mGET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-#define disable_timer1_irq() mCLR_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_timer1_irq() mSET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_timer1_source() mCLR_SRC_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_timer1_source() mGET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-#define disable_timer2_irq() mCLR_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_timer2_irq() mSET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_timer2_source() mCLR_SRC_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_timer2_source() mGET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-#define disable_timer3_irq() mCLR_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_timer3_irq() mSET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_timer3_source() mCLR_SRC_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_timer3_source() mGET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-\r
-/* hibernation timers interrupt control */\r
-#define sbit_HTIMER0 ( 1UL << 20 )\r
-#define sbit_HTIMER1 b_bit14\r
-\r
-#define disable_htimer0_irq() mCLR_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define enable_htimer0_irq() mSET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define clear_htimer0_source() mCLR_SRC_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE)\r
-#define get_htimer0_source() mGET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE)\r
-\r
-#define disable_htimer1_irq() mCLR_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_htimer1_irq() mSET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_htimer1_source() mCLR_SRC_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_htimer1_source() mGET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-/* RTC interrupt control */\r
-#define b_bit18 (1 << 18)\r
-#define b_bit19 (1 << 19)\r
-#define sbit_RTC_INT b_bit18\r
-#define disable_rtc_irq() mCLR_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define enable_rtc_irq() mSET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define clear_rtc_irq_source() mCLR_SRC_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define get_rtc_irq_source() mGET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-/* RTC alarm interrupt control */\r
-#define sbit_RTC_ALM_INT b_bit19\r
-#define disable_rtc_alm_irq() mCLR_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define enable_rtc_alm_irq() mSET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define clear_rtc_irq_alm_source() mCLR_SRC_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define get_rtc_irq_alm_source() mGET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-\r
-/* week timer interrupt control */\r
-#define sbit_WKTIMER b_bit7\r
-\r
-#define disable_wktimer_irq() mCLR_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_wktimer_irq() mSET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_wktimer_source() mCLR_SRC_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_wktimer_source() mGET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-\r
-/* scan matrix interrupt control */\r
-#define sbit_SCANNER b_bit16\r
-#define disable_scanner_irq() mCLR_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define enable_scanner_irq() mSET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define clear_scanner_source() mCLR_SRC_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE)\r
-#define get_scanner_source() mGET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE)\r
-\r
-\r
-/* PS2 interrupt control */\r
-/* PS2 activity interrupt */\r
-#define sbit_PS2_ACT_0 b_bit13\r
-#define sbit_PS2_ACT_1 b_bit14\r
-#define sbit_PS2_ACT_2 b_bit15\r
-/* PS2 wakeup interrupt: detect start bit */\r
-#define sbit_PS2_WK_0A b_bit17\r
-#define sbit_PS2_WK_1B b_bit20\r
-#define sbit_PS2_WK_2 b_bit21\r
-\r
-/* PS2 activity interrupt control */\r
-#define disable_ps2_act_0_irq() mCLR_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_act_0_irq() mSET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_act_0_source() mCLR_SRC_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_act_0_source() mGET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-#define disable_ps2_act_1_irq() mCLR_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_act_1_irq() mSET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_act_1_source() mCLR_SRC_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_act_1_source() mGET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-#define disable_ps2_act_2_irq() mCLR_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_act_2_irq() mSET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_act_2_source() mCLR_SRC_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_act_2_source() mGET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-/* PS2 wakeup interrupt control */\r
-#define disable_ps2_wk_0_irq() mCLR_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_wk_0_irq() mSET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_wk_0_source() mCLR_SRC_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_wk_0_source() mGET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-#define disable_ps2_wk_1_irq() mCLR_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_wk_1_irq() mSET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_wk_1_source() mCLR_SRC_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_wk_1_source() mGET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-#define disable_ps2_wk_2_irq() mCLR_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_wk_2_irq() mSET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_wk_2_source() mCLR_SRC_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_wk_2_source() mGET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-\r
-/* ICT interrupt control */\r
-/* capture 0~5 interrupt */\r
-#define sbit_ICT_CAPTURE0 b_bit17\r
-#define sbit_ICT_CAPTURE1 b_bit18\r
-#define sbit_ICT_CAPTURE2 b_bit19\r
-#define sbit_ICT_CAPTURE3 b_bit20\r
-#define sbit_ICT_CAPTURE4 b_bit21\r
-#define sbit_ICT_CAPTURE5 b_bit22\r
-\r
-/* capture 0 interrupt control */\r
-#define disable_capture0_irq() mCLR_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_capture0_irq() mSET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_capture0_source() mCLR_SRC_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_capture0_source() mGET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-\r
-/* SMBus interrupt control */\r
-\r
-\r
-/* GPIO interrupt control */\r
-\r
-\r
-/* BC link interrupt control */\r
-/* bclink A~D interrupt */\r
-#define sbit_BCLINK_A_BUSY b_bit0\r
-#define sbit_BCLINK_A_ERR b_bit1\r
-#define sbit_BCLINK_A_INT b_bit2\r
-#define sbit_BCLINK_B_BUSY b_bit3\r
-#define sbit_BCLINK_B_ERR b_bit4\r
-#define sbit_BCLINK_B_INT b_bit5\r
-#define sbit_BCLINK_C_BUSY b_bit6\r
-#define sbit_BCLINK_C_ERR b_bit7\r
-#define sbit_BCLINK_C_INT b_bit8\r
-#define sbit_BCLINK_D_BUSY b_bit9\r
-#define sbit_BCLINK_D_ERR b_bit10\r
-#define sbit_BCLINK_D_INT b_bit11\r
-\r
-/* bclink B interrupt control */\r
-#define disable_bclink_b_busy_irq() mCLR_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define enable_bclink_b_busy_irq() mSET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define clear_bclink_b_busy_source() mCLR_SRC_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE)\r
-#define get_bclink_b_busy_source() mGET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE)\r
-\r
-#define disable_bclink_b_err_irq() mCLR_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define enable_bclink_b_err_irq() mSET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define clear_bclink_b_err_source() mCLR_SRC_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE)\r
-#define get_bclink_b_err_source() mGET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE)\r
-\r
-#define disable_bclink_b_int_irq() mCLR_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define enable_bclink_b_int_irq() mSET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define clear_bclink_b_int_source() mCLR_SRC_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE)\r
-#define get_bclink_b_int_source() mGET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE)\r
-\r
-/* UART interrupt control */\r
-#define sbit_UART_INT b_bit0\r
-\r
-#define disable_uart_irq() mCLR_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET)\r
-#define enable_uart_irq() mSET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET)\r
-#define clear_uart_irq_source() mCLR_SRC_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE)\r
-#define get_uart_irq_source() mGET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE)\r
-\r
-// GIRQ IDs for EC Interrupt Aggregator\r
-enum MEC_GIRQ_IDS\r
-{\r
- MEC_GIRQ08_ID = 0,\r
- MEC_GIRQ09_ID, \r
- MEC_GIRQ10_ID, \r
- MEC_GIRQ11_ID, \r
- MEC_GIRQ12_ID, \r
- MEC_GIRQ13_ID, \r
- MEC_GIRQ14_ID, \r
- MEC_GIRQ15_ID, \r
- MEC_GIRQ16_ID, \r
- MEC_GIRQ17_ID, \r
- MEC_GIRQ18_ID, \r
- MEC_GIRQ19_ID, \r
- MEC_GIRQ20_ID, \r
- MEC_GIRQ21_ID, \r
- MEC_GIRQ22_ID, \r
- MEC_GIRQ23_ID, \r
- MEC_GIRQ_ID_MAX\r
-};\r
-\r
-//Bitmask of GIRQ in ECIA Block Registers\r
-#define MEC_GIRQ08_BITMASK (1UL << (MEC_GIRQ08_ID + 8))\r
-#define MEC_GIRQ09_BITMASK (1UL << (MEC_GIRQ09_ID + 8)) \r
-#define MEC_GIRQ10_BITMASK (1UL << (MEC_GIRQ10_ID + 8)) \r
-#define MEC_GIRQ11_BITMASK (1UL << (MEC_GIRQ11_ID + 8)) \r
-#define MEC_GIRQ12_BITMASK (1UL << (MEC_GIRQ12_ID + 8)) \r
-#define MEC_GIRQ13_BITMASK (1UL << (MEC_GIRQ13_ID + 8)) \r
-#define MEC_GIRQ14_BITMASK (1UL << (MEC_GIRQ14_ID + 8)) \r
-#define MEC_GIRQ15_BITMASK (1UL << (MEC_GIRQ15_ID + 8)) \r
-#define MEC_GIRQ16_BITMASK (1UL << (MEC_GIRQ16_ID + 8)) \r
-#define MEC_GIRQ17_BITMASK (1UL << (MEC_GIRQ17_ID + 8)) \r
-#define MEC_GIRQ18_BITMASK (1UL << (MEC_GIRQ18_ID + 8)) \r
-#define MEC_GIRQ19_BITMASK (1UL << (MEC_GIRQ19_ID + 8)) \r
-#define MEC_GIRQ20_BITMASK (1UL << (MEC_GIRQ20_ID + 8)) \r
-#define MEC_GIRQ21_BITMASK (1UL << (MEC_GIRQ21_ID + 8)) \r
-#define MEC_GIRQ22_BITMASK (1UL << (MEC_GIRQ22_ID + 8)) \r
-#define MEC_GIRQ23_BITMASK (1UL << (MEC_GIRQ23_ID + 8)) \r
-\r
-#define INTERRUPT_MODE_ALL_AGGREGATED (0u)\r
-#define INTERRUPT_MODE_DIRECT (1u)\r
-\r
-// Bit map of GIRQs whose sources can be directly connected to the NVIC\r
-// GIRQs 12 - 18, 23\r
-#define ECIA_GIRQ_DIRECT_BITMAP (0x0087F000ul)\r
-\r
-/*\r
- * n = b[7:0] = zero-based direct mapped NVIC ID\r
- * m = b[15:8] = zero-based aggregated NVIC ID\r
- * a = b[23:16] = block Aggregator register block ID\r
- * b = b[31:24] = block bit position in Aggregator registers\r
-*/\r
-#define IROUTE(b,a,m,n) (((uint32_t)(n)&0xFFul) + \\r
- (((uint32_t)(m)&0xFFul)<<8u) + \\r
- ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \\r
- (((uint32_t)(b)&0x1Ful)<<24))\r
-\r
-#define ECIA_NVIC_ID_BITPOS (0u)\r
-#define ECIA_IA_NVIC_ID_BITPOS (8u)\r
-#define ECIA_GIRQ_ID_BITPOS (16u)\r
-#define ECIA_GIRQ_BIT_BITPOS (24u)\r
-\r
-//\r
-// GIRQ08\r
-//\r
-#define GPIO_0140_IROUTE IROUTE(0,8,57,57)\r
-#define GPIO_0141_IROUTE IROUTE(1,8,57,57)\r
-#define GPIO_0142_IROUTE IROUTE(2,8,57,57)\r
-#define GPIO_0143_IROUTE IROUTE(3,8,57,57)\r
-#define GPIO_0144_IROUTE IROUTE(4,8,57,57)\r
-#define GPIO_0145_IROUTE IROUTE(5,8,57,57)\r
-#define GPIO_0147_IROUTE IROUTE(7,8,57,57)\r
-//\r
-#define GPIO_0150_IROUTE IROUTE(8,8,57,57)\r
-#define GPIO_0151_IROUTE IROUTE(9,8,57,57)\r
-#define GPIO_0152_IROUTE IROUTE(10,8,57,57)\r
-#define GPIO_0153_IROUTE IROUTE(11,8,57,57)\r
-#define GPIO_0154_IROUTE IROUTE(12,8,57,57)\r
-#define GPIO_0155_IROUTE IROUTE(13,8,57,57)\r
-#define GPIO_0156_IROUTE IROUTE(14,8,57,57)\r
-#define GPIO_0157_IROUTE IROUTE(15,8,57,57)\r
-//\r
-#define GPIO_0160_IROUTE IROUTE(16,8,57,57)\r
-#define GPIO_0161_IROUTE IROUTE(17,8,57,57)\r
-#define GPIO_0162_IROUTE IROUTE(18,8,57,57)\r
-#define GPIO_0163_IROUTE IROUTE(19,8,57,57)\r
-#define GPIO_0164_IROUTE IROUTE(20,8,57,57)\r
-#define GPIO_0165_IROUTE IROUTE(21,8,57,57)\r
-#define GPIO_0166_IROUTE IROUTE(22,8,57,57)\r
-#define GPIO_0167_IROUTE IROUTE(23,8,57,57)\r
-\r
-//\r
-// GIRQ09\r
-//\r
-#define GPIO_0100_IROUTE IROUTE(0,9,58,58)\r
-#define GPIO_0101_IROUTE IROUTE(1,9,58,58)\r
-#define GPIO_0102_IROUTE IROUTE(2,9,58,58)\r
-#define GPIO_0103_IROUTE IROUTE(3,9,58,58)\r
-#define GPIO_0104_IROUTE IROUTE(4,9,58,58)\r
-#define GPIO_0105_IROUTE IROUTE(5,9,58,58)\r
-#define GPIO_0105_IROUTE IROUTE(5,9,58,58)\r
-#define GPIO_0107_IROUTE IROUTE(7,9,58,58)\r
-//\r
-#define GPIO_0110_IROUTE IROUTE(8,9,58,58)\r
-#define GPIO_0111_IROUTE IROUTE(9,9,58,58)\r
-#define GPIO_0112_IROUTE IROUTE(10,9,58,58)\r
-#define GPIO_0113_IROUTE IROUTE(11,9,58,58)\r
-#define GPIO_0114_IROUTE IROUTE(12,9,58,58)\r
-#define GPIO_0115_IROUTE IROUTE(13,9,58,58)\r
-#define GPIO_0116_IROUTE IROUTE(14,9,58,58)\r
-#define GPIO_0117_IROUTE IROUTE(15,9,58,58)\r
-//\r
-#define GPIO_0120_IROUTE IROUTE(16,9,58,58)\r
-#define GPIO_0121_IROUTE IROUTE(17,9,58,58)\r
-#define GPIO_0122_IROUTE IROUTE(18,9,58,58)\r
-#define GPIO_0124_IROUTE IROUTE(20,9,58,58)\r
-#define GPIO_0125_IROUTE IROUTE(21,9,58,58)\r
-#define GPIO_0126_IROUTE IROUTE(22,9,58,58)\r
-#define GPIO_0127_IROUTE IROUTE(23,9,58,58)\r
-//\r
-#define GPIO_0130_IROUTE IROUTE(24,9,58,58)\r
-#define GPIO_0131_IROUTE IROUTE(25,9,58,58)\r
-#define GPIO_0132_IROUTE IROUTE(26,9,58,58)\r
-#define GPIO_0133_IROUTE IROUTE(27,9,58,58)\r
-#define GPIO_0134_IROUTE IROUTE(28,9,58,58)\r
-#define GPIO_0135_IROUTE IROUTE(29,9,58,58)\r
-#define GPIO_0136_IROUTE IROUTE(30,9,58,58)\r
-\r
-//\r
-// GIRQ10\r
-//\r
-#define GPIO_0040_IROUTE IROUTE(0,10,59,59)\r
-#define GPIO_0041_IROUTE IROUTE(1,10,59,59)\r
-#define GPIO_0042_IROUTE IROUTE(2,10,59,59)\r
-#define GPIO_0043_IROUTE IROUTE(3,10,59,59)\r
-#define GPIO_0044_IROUTE IROUTE(4,10,59,59)\r
-#define GPIO_0045_IROUTE IROUTE(5,10,59,59)\r
-#define GPIO_0045_IROUTE IROUTE(5,10,59,59)\r
-#define GPIO_0047_IROUTE IROUTE(7,10,59,59)\r
-//\r
-#define GPIO_0050_IROUTE IROUTE(8,10,59,59)\r
-#define GPIO_0051_IROUTE IROUTE(9,10,59,59)\r
-#define GPIO_0052_IROUTE IROUTE(10,10,59,59)\r
-#define GPIO_0053_IROUTE IROUTE(11,10,59,59)\r
-#define GPIO_0054_IROUTE IROUTE(12,10,59,59)\r
-#define GPIO_0055_IROUTE IROUTE(13,10,59,59)\r
-#define GPIO_0056_IROUTE IROUTE(14,10,59,59)\r
-#define GPIO_0057_IROUTE IROUTE(15,10,59,59)\r
-//\r
-#define GPIO_0060_IROUTE IROUTE(16,10,59,59)\r
-#define GPIO_0061_IROUTE IROUTE(17,10,59,59)\r
-#define GPIO_0062_IROUTE IROUTE(18,10,59,59)\r
-#define GPIO_0063_IROUTE IROUTE(19,10,59,59)\r
-#define GPIO_0064_IROUTE IROUTE(20,10,59,59)\r
-#define GPIO_0065_IROUTE IROUTE(21,10,59,59)\r
-#define GPIO_0066_IROUTE IROUTE(22,10,59,59)\r
-#define GPIO_0067_IROUTE IROUTE(23,10,59,59)\r
-//\r
-#define GPIO_0070_IROUTE IROUTE(24,10,59,59)\r
-#define GPIO_0071_IROUTE IROUTE(25,10,59,59)\r
-#define GPIO_0072_IROUTE IROUTE(26,10,59,59)\r
-#define GPIO_0073_IROUTE IROUTE(27,10,59,59)\r
-#define GPIO_0074_IROUTE IROUTE(28,10,59,59)\r
-#define GPIO_0075_IROUTE IROUTE(29,10,59,59)\r
-#define GPIO_0076_IROUTE IROUTE(30,10,59,59)\r
-\r
-//\r
-// GIRQ11\r
-//\r
-#define GPIO_0000_IROUTE IROUTE(0,11,60,60)\r
-#define GPIO_0001_IROUTE IROUTE(1,11,60,60)\r
-#define GPIO_0002_IROUTE IROUTE(2,11,60,60)\r
-#define GPIO_0003_IROUTE IROUTE(3,11,60,60)\r
-#define GPIO_0004_IROUTE IROUTE(4,11,60,60)\r
-#define GPIO_0005_IROUTE IROUTE(5,11,60,60)\r
-#define GPIO_0006_IROUTE IROUTE(6,11,60,60)\r
-#define GPIO_0007_IROUTE IROUTE(7,11,60,60)\r
-//\r
-#define GPIO_0010_IROUTE IROUTE(8,11,60,60)\r
-#define GPIO_0011_IROUTE IROUTE(9,11,60,60)\r
-#define GPIO_0012_IROUTE IROUTE(10,11,60,60)\r
-#define GPIO_0013_IROUTE IROUTE(11,11,60,60)\r
-#define GPIO_0014_IROUTE IROUTE(12,11,60,60)\r
-#define GPIO_0015_IROUTE IROUTE(13,11,60,60)\r
-#define GPIO_0016_IROUTE IROUTE(14,11,60,60)\r
-#define GPIO_0017_IROUTE IROUTE(15,11,60,60)\r
-//\r
-#define GPIO_0020_IROUTE IROUTE(16,11,60,60)\r
-#define GPIO_0021_IROUTE IROUTE(17,11,60,60)\r
-#define GPIO_0022_IROUTE IROUTE(18,11,60,60)\r
-#define GPIO_0023_IROUTE IROUTE(19,11,60,60)\r
-#define GPIO_0024_IROUTE IROUTE(20,11,60,60)\r
-#define GPIO_0025_IROUTE IROUTE(21,11,60,60)\r
-#define GPIO_0026_IROUTE IROUTE(22,11,60,60)\r
-#define GPIO_0027_IROUTE IROUTE(23,11,60,60)\r
-//\r
-#define GPIO_0030_IROUTE IROUTE(24,11,60,60)\r
-#define GPIO_0031_IROUTE IROUTE(25,11,60,60)\r
-#define GPIO_0032_IROUTE IROUTE(26,11,60,60)\r
-#define GPIO_0033_IROUTE IROUTE(27,11,60,60)\r
-#define GPIO_0034_IROUTE IROUTE(28,11,60,60)\r
-#define GPIO_0035_IROUTE IROUTE(29,11,60,60)\r
-#define GPIO_0036_IROUTE IROUTE(30,11,60,60)\r
-\r
-//\r
-// GIRQ12\r
-//\r
-#define SMB0_IROUTE IROUTE(0,12,61,0)\r
-#define SMB1_IROUTE IROUTE(1,12,61,1)\r
-#define SMB2_IROUTE IROUTE(2,12,61,2)\r
-#define SMB3_IROUTE IROUTE(3,12,61,3)\r
-// SMB wakes have no direct connection to NVIC, always aggregated\r
-#define SMB0_WAKE_IROUTE IROUTE(4,12,61,61)\r
-#define SMB1_WAKE_IROUTE IROUTE(5,12,61,61)\r
-#define SMB2_WAKE_IROUTE IROUTE(6,12,61,61)\r
-#define SMB3_WAKE_IROUTE IROUTE(7,12,61,61)\r
-#define SMB4_WAKE_IROUTE IROUTE(8,12,61,61)\r
-\r
-//\r
-// GIRQ13\r
-//\r
-#define DMA0_IROUTE IROUTE(16,13,62,4)\r
-#define DMA1_IROUTE IROUTE(17,13,62,5)\r
-#define DMA2_IROUTE IROUTE(18,13,62,6)\r
-#define DMA3_IROUTE IROUTE(19,13,62,7)\r
-#define DMA4_IROUTE IROUTE(20,13,62,8)\r
-#define DMA5_IROUTE IROUTE(21,13,62,9)\r
-#define DMA6_IROUTE IROUTE(22,13,62,10)\r
-#define DMA7_IROUTE IROUTE(23,13,62,11)\r
-#define DMA8_IROUTE IROUTE(24,13,62,81)\r
-#define DMA9_IROUTE IROUTE(25,13,62,82)\r
-#define DMA10_IROUTE IROUTE(26,13,62,83)\r
-#define DMA11_IROUTE IROUTE(27,13,62,84)\r
-\r
-//\r
-// GIRQ14\r
-//\r
-#define LPC_BERR_IROUTE IROUTE(2,14,63,12)\r
-\r
-//\r
-// GIRQ15\r
-//\r
-#define UART0_IROUTE IROUTE(0,15,64,13)\r
-#define EMI0_IROUTE IROUTE(2,15,64,14)\r
-#define ACPI_EC0_IBF_IROUTE IROUTE(6,15,64,15)\r
-#define ACPI_EC0_OBF_IROUTE IROUTE(7,15,64,16)\r
-#define ACPI_EC1_IBF_IROUTE IROUTE(8,15,64,17)\r
-#define ACPI_EC1_OBF_IROUTE IROUTE(9,15,64,18)\r
-#define ACPI_PM1_CTL_IROUTE IROUTE(10,15,64,19)\r
-#define ACPI_PM1_EN_IROUTE IROUTE(11,15,64,20)\r
-#define ACPI_PM1_STS_IROUTE IROUTE(12,15,64,21)\r
-#define EM8042_OBF_IROUTE IROUTE(13,15,64,22)\r
-#define EM8042_IBF_IROUTE IROUTE(14,15,64,23)\r
-#define MBOX_IROUTE IROUTE(15,15,64,24)\r
-#define MBOX_DATA_IROUTE IROUTE(16,15,64,40) \r
-\r
-//\r
-// GIRQ16\r
-//\r
-#define PECI_IROUTE IROUTE(3,16,65,25)\r
-\r
-//\r
-// GIRQ17\r
-//\r
-#define TACH0_IROUTE IROUTE(0,17,66,26)\r
-#define TACH1_IROUTE IROUTE(1,17,66,27)\r
-#define PS2_0_WAKE_IROUTE IROUTE(2,17,66,66)\r
-#define PS2_1_WAKE_IROUTE IROUTE(3,17,66,66)\r
-#define PS2_2_WAKE_IROUTE IROUTE(4,17,66,66)\r
-#define PS2_3_WAKE_IROUTE IROUTE(5,17,66,66)\r
-#define BC_WAKE_IROUTE IROUTE(6,17,66,66)\r
-#define ADC_SNGL_IROUTE IROUTE(10,17,66,28)\r
-#define ADC_RPT_IROUTE IROUTE(11,17,66,29)\r
-#define ADC2PWM1_IROUTE IROUTE(12,17,66,30)\r
-#define ADC2PWM2_IROUTE IROUTE(13,17,66,31)\r
-#define PS2_0_IROUTE IROUTE(14,17,66,32)\r
-#define PS2_1_IROUTE IROUTE(15,17,66,33)\r
-#define PS2_2_IROUTE IROUTE(16,17,66,34)\r
-#define PS2_3_IROUTE IROUTE(17,17,66,35)\r
-#define RTC_IROUTE IROUTE(18,17,66,91)\r
-#define RTC_ALARM_IROUTE IROUTE(19,17,66,92)\r
-#define HTIMER_IROUTE IROUTE(20,17,66,38)\r
-#define KSC_IROUTE IROUTE(21,17,66,39)\r
-#define KSC_WAKE_IROUTE IROUTE(22,17,66,66)\r
-#define RPM_STALL_IROUTE IROUTE(23,17,66,41)\r
-#define RPM_SPIN_IROUTE IROUTE(24,17,66,42)\r
-#define PFR_IROUTE IROUTE(25,17,66,43)\r
-#define LED0_IROUTE IROUTE(26,17,66,44)\r
-#define LED1_IROUTE IROUTE(27,17,66,45)\r
-#define LED2_IROUTE IROUTE(28,17,66,46)\r
-#define BCM_ERR_IROUTE IROUTE(29,17,66,47)\r
-#define BCM_BUSY_IROUTE IROUTE(30,17,66,48)\r
-\r
-//\r
-// GIRQ18\r
-//\r
-#define SPI0_TX_IROUTE IROUTE(0,18,67,36)\r
-#define SPI0_RX_IROUTE IROUTE(1,18,67,37)\r
-#define SPI1_TX_IROUTE IROUTE(2,18,67,55)\r
-#define SPI1_RX_IROUTE IROUTE(3,18,67,56)\r
-#define LED3_IROUTE IROUTE(4,18,67,85)\r
-#define PKE_ERR_IROUTE IROUTE(5,18,67,86)\r
-#define PKE_END_IROUTE IROUTE(6,18,67,87)\r
-#define NDRNG_IROUTE IROUTE(7,18,67,88)\r
-#define AES_IROUTE IROUTE(8,18,67,89)\r
-#define HASH_IROUTE IROUTE(9,18,67,90)\r
-\r
-//\r
-// GIRQ19, Aggregated only\r
-//\r
-#define LRESET_IROUTE IROUTE(0,19,68,68)\r
-#define VCC_PWRGD_IROUTE IROUTE(1,19,68,68)\r
-\r
-//\r
-// GIRQ20, Aggregated only\r
-//\r
-#define GPIO_0200_IROUTE IROUTE(0,20,69,69)\r
-#define GPIO_0201_IROUTE IROUTE(1,20,69,69)\r
-#define GPIO_0202_IROUTE IROUTE(2,20,69,69)\r
-#define GPIO_0203_IROUTE IROUTE(3,20,69,69)\r
-#define GPIO_0204_IROUTE IROUTE(4,20,69,69)\r
-#define GPIO_0206_IROUTE IROUTE(6,20,69,69)\r
-//\r
-#define GPIO_0210_IROUTE IROUTE(8,20,69,69)\r
-#define GPIO_0211_IROUTE IROUTE(9,20,69,69)\r
-#define GPIO_0212_IROUTE IROUTE(10,20,69,69)\r
-#define GPIO_0213_IROUTE IROUTE(11,20,69,69)\r
-\r
-//\r
-// GIRQ21\r
-//\r
-// No sources\r
-\r
-//\r
-// GIRQ22\r
-//\r
-// No sources\r
-\r
-//\r
-// GIRQ23\r
-//\r
-#define BTMR0_IROUTE IROUTE(0,23,72,49)\r
-#define BTMR1_IROUTE IROUTE(1,23,72,50)\r
-#define BTMR2_IROUTE IROUTE(2,23,72,51)\r
-#define BTMR3_IROUTE IROUTE(3,23,72,52)\r
-#define BTMR4_IROUTE IROUTE(4,23,72,53)\r
-#define BTMR5_IROUTE IROUTE(5,23,72,54)\r
-\r
-// GIRQ08 Bit Positions \r
-#define GIRQ08_GPIO_0140_BITPOS (0)\r
-#define GIRQ08_GPIO_0141_BITPOS (1)\r
-#define GIRQ08_GPIO_0142_BITPOS (2)\r
-#define GIRQ08_GPIO_0143_BITPOS (3)\r
-#define GIRQ08_GPIO_0144_BITPOS (4)\r
-#define GIRQ08_GPIO_0145_BITPOS (5)\r
-//#define GIRQ08_GPIO_0146_BITPOS (6) RESERVED\r
-#define GIRQ08_GPIO_0147_BITPOS (7)\r
-//\r
-#define GIRQ08_GPIO_0150_BITPOS (8)\r
-#define GIRQ08_GPIO_0151_BITPOS (9)\r
-#define GIRQ08_GPIO_0152_BITPOS (10)\r
-#define GIRQ08_GPIO_0153_BITPOS (11)\r
-#define GIRQ08_GPIO_0154_BITPOS (12)\r
-#define GIRQ08_GPIO_0155_BITPOS (13)\r
-#define GIRQ08_GPIO_0156_BITPOS (14) \r
-#define GIRQ08_GPIO_0157_BITPOS (15)\r
-//\r
-#define GIRQ08_GPIO_0160_BITPOS (16)\r
-#define GIRQ08_GPIO_0161_BITPOS (17)\r
-#define GIRQ08_GPIO_0162_BITPOS (18)\r
-#define GIRQ08_GPIO_0163_BITPOS (19)\r
-#define GIRQ08_GPIO_0164_BITPOS (20)\r
-#define GIRQ08_GPIO_0165_BITPOS (21)\r
-#define GIRQ08_GPIO_0166_BITPOS (22) \r
-#define GIRQ08_GPIO_0167_BITPOS (23)\r
-//\r
-#define GIRQ08_MASK (0x00FFFFBFul)\r
-#define GIRQ08_WAKE_CAPABLE_MASK (0x00FFFFBFul)\r
-//\r
-\r
-// GIRQ09 Bit Positions \r
-#define GIRQ09_GPIO_0100_BITPOS (0)\r
-#define GIRQ09_GPIO_0101_BITPOS (1)\r
-#define GIRQ09_GPIO_0102_BITPOS (2)\r
-#define GIRQ09_GPIO_0103_BITPOS (3)\r
-#define GIRQ09_GPIO_0104_BITPOS (4)\r
-#define GIRQ09_GPIO_0105_BITPOS (5)\r
-#define GIRQ09_GPIO_0106_BITPOS (6) \r
-#define GIRQ09_GPIO_0107_BITPOS (7)\r
-//\r
-#define GIRQ09_GPIO_0110_BITPOS (8)\r
-#define GIRQ09_GPIO_0111_BITPOS (9)\r
-#define GIRQ09_GPIO_0112_BITPOS (10)\r
-#define GIRQ09_GPIO_0113_BITPOS (11)\r
-#define GIRQ09_GPIO_0114_BITPOS (12)\r
-#define GIRQ09_GPIO_0115_BITPOS (13)\r
-#define GIRQ09_GPIO_0116_BITPOS (14) \r
-#define GIRQ09_GPIO_0117_BITPOS (15)\r
-//\r
-#define GIRQ09_GPIO_0120_BITPOS (16)\r
-#define GIRQ09_GPIO_0121_BITPOS (17)\r
-#define GIRQ09_GPIO_0122_BITPOS (18)\r
-//#define GIRQ09_GPIO_0123_BITPOS (19) RESERVED\r
-#define GIRQ09_GPIO_0124_BITPOS (20)\r
-#define GIRQ09_GPIO_0125_BITPOS (21)\r
-#define GIRQ09_GPIO_0126_BITPOS (22) \r
-#define GIRQ09_GPIO_0127_BITPOS (23)\r
-//\r
-#define GIRQ09_GPIO_0130_BITPOS (24)\r
-#define GIRQ09_GPIO_0131_BITPOS (25)\r
-#define GIRQ09_GPIO_0132_BITPOS (26)\r
-#define GIRQ09_GPIO_0133_BITPOS (27)\r
-#define GIRQ09_GPIO_0134_BITPOS (28)\r
-#define GIRQ09_GPIO_0135_BITPOS (29)\r
-#define GIRQ09_GPIO_0136_BITPOS (30) \r
-//#define GIRQ09_GPIO_0137_BITPOS (31) RESERVED\r
-//\r
-#define GIRQ09_MASK (0x7FF7FFFFul)\r
-#define GIRQ09_WAKE_CAPABLE_MASK (0x7FF7FFFFul)\r
-//\r
-\r
-// GIRQ10 Bit Positions \r
-#define GIRQ10_GPIO_0040_BITPOS (0)\r
-#define GIRQ10_GPIO_0041_BITPOS (1)\r
-#define GIRQ10_GPIO_0042_BITPOS (2)\r
-#define GIRQ10_GPIO_0043_BITPOS (3)\r
-#define GIRQ10_GPIO_0044_BITPOS (4)\r
-#define GIRQ10_GPIO_0045_BITPOS (5)\r
-#define GIRQ10_GPIO_0046_BITPOS (6) \r
-#define GIRQ10_GPIO_0047_BITPOS (7)\r
-//\r
-#define GIRQ10_GPIO_0050_BITPOS (8)\r
-#define GIRQ10_GPIO_0051_BITPOS (9)\r
-#define GIRQ10_GPIO_0052_BITPOS (10)\r
-#define GIRQ10_GPIO_0053_BITPOS (11)\r
-#define GIRQ10_GPIO_0054_BITPOS (12)\r
-#define GIRQ10_GPIO_0055_BITPOS (13)\r
-#define GIRQ10_GPIO_0056_BITPOS (14) \r
-#define GIRQ10_GPIO_0057_BITPOS (15)\r
-//\r
-#define GIRQ10_GPIO_0060_BITPOS (16)\r
-#define GIRQ10_GPIO_0061_BITPOS (17)\r
-#define GIRQ10_GPIO_0062_BITPOS (18)\r
-#define GIRQ10_GPIO_0063_BITPOS (19)\r
-#define GIRQ10_GPIO_0064_BITPOS (20)\r
-#define GIRQ10_GPIO_0065_BITPOS (21)\r
-#define GIRQ10_GPIO_0066_BITPOS (22) \r
-#define GIRQ10_GPIO_0067_BITPOS (23)\r
-//\r
-#define GIRQ10_GPIO_0070_BITPOS (24)\r
-#define GIRQ10_GPIO_0071_BITPOS (25)\r
-#define GIRQ10_GPIO_0072_BITPOS (26)\r
-#define GIRQ10_GPIO_0073_BITPOS (27)\r
-#define GIRQ10_GPIO_0074_BITPOS (28)\r
-#define GIRQ10_GPIO_0075_BITPOS (29)\r
-#define GIRQ10_GPIO_0076_BITPOS (30) \r
-//#define GIRQ10_GPIO_0077_BITPOS (31) RESERVED\r
-//\r
-#define GIRQ10_MASK (0x7FFFFFFFul)\r
-#define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
-//\r
-\r
-// GIRQ11 Bit Positions \r
-#define GIRQ11_GPIO_0000_BITPOS (0)\r
-#define GIRQ11_GPIO_0001_BITPOS (1)\r
-#define GIRQ11_GPIO_0002_BITPOS (2)\r
-#define GIRQ11_GPIO_0003_BITPOS (3)\r
-#define GIRQ11_GPIO_0004_BITPOS (4)\r
-#define GIRQ11_GPIO_0005_BITPOS (5)\r
-#define GIRQ11_GPIO_0006_BITPOS (6) \r
-#define GIRQ11_GPIO_0007_BITPOS (7)\r
-//\r
-#define GIRQ11_GPIO_0010_BITPOS (8)\r
-#define GIRQ11_GPIO_0011_BITPOS (9)\r
-#define GIRQ11_GPIO_0012_BITPOS (10)\r
-#define GIRQ11_GPIO_0013_BITPOS (11)\r
-#define GIRQ11_GPIO_0014_BITPOS (12)\r
-#define GIRQ11_GPIO_0015_BITPOS (13)\r
-#define GIRQ11_GPIO_0016_BITPOS (14) \r
-#define GIRQ11_GPIO_0017_BITPOS (15)\r
-//\r
-#define GIRQ11_GPIO_0020_BITPOS (16)\r
-#define GIRQ11_GPIO_0021_BITPOS (17)\r
-#define GIRQ11_GPIO_0022_BITPOS (18)\r
-#define GIRQ11_GPIO_0023_BITPOS (19)\r
-#define GIRQ11_GPIO_0024_BITPOS (20)\r
-#define GIRQ11_GPIO_0025_BITPOS (21)\r
-#define GIRQ11_GPIO_0026_BITPOS (22) \r
-#define GIRQ11_GPIO_0027_BITPOS (23)\r
-//\r
-#define GIRQ11_GPIO_0030_BITPOS (24)\r
-#define GIRQ11_GPIO_0031_BITPOS (25)\r
-#define GIRQ11_GPIO_0032_BITPOS (26)\r
-#define GIRQ11_GPIO_0033_BITPOS (27)\r
-#define GIRQ11_GPIO_0034_BITPOS (28)\r
-#define GIRQ11_GPIO_0035_BITPOS (29)\r
-#define GIRQ11_GPIO_0036_BITPOS (30) \r
-//#define GIRQ11_GPIO_0037_BITPOS (31) RESERVED\r
-//\r
-#define GIRQ11_MASK (0x7FFFFFFFul)\r
-#define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
-//\r
-\r
-// GIRQ12 Bit Positions \r
-#define GIRQ12_SMBUS0_BITPOS (0)\r
-#define GIRQ12_SMBUS1_BITPOS (1)\r
-#define GIRQ12_SMBUS2_BITPOS (2)\r
-#define GIRQ12_SMBUS3_BITPOS (3)\r
-#define GIRQ12_SMBUS0_WAKE_BITPOS (4)\r
-#define GIRQ12_SMBUS1_WAKE_BITPOS (5)\r
-#define GIRQ12_SMBUS2_WAKE_BITPOS (6)\r
-#define GIRQ12_SMBUS3_WAKE_BITPOS (7)\r
-#define GIRQ12_SMBUS4_WAKE_BITPOS (8)\r
-// RESERVED bits[31:9]\r
-#define GIRQ12_MASK (0x01FFul)\r
-#define GIRQ12_WAKE_CAPABLE_MASK (0x01F0ul)\r
-//\r
-\r
-// GIRQ13 Bit Positions \r
-#define GIRQ13_DMA0_BITPOS (16)\r
-#define GIRQ13_DMA1_BITPOS (17)\r
-#define GIRQ13_DMA2_BITPOS (18)\r
-#define GIRQ13_DMA3_BITPOS (19)\r
-#define GIRQ13_DMA4_BITPOS (20)\r
-#define GIRQ13_DMA5_BITPOS (21)\r
-#define GIRQ13_DMA6_BITPOS (22)\r
-#define GIRQ13_DMA7_BITPOS (23)\r
-#define GIRQ13_DMA8_BITPOS (24)\r
-#define GIRQ13_DMA9_BITPOS (25)\r
-#define GIRQ13_DMA10_BITPOS (26)\r
-#define GIRQ13_DMA11_BITPOS (27)\r
-//\r
-#define GIRQ13_MASK (0x0FFF0000ul)\r
-#define GIRQ13_WAKE_CAPABLE_MASK (0x00000000ul)\r
-//\r
-\r
-// GIRQ14 Bit Positions \r
-#define GIRQ14_LPC_BITPOS (2)\r
-//\r
-#define GIRQ14_MASK (0x04ul)\r
-#define GIRQ14_WAKE_CAPABLE_MASK (0x00ul)\r
-//\r
-\r
-// GIRQ15 Bit Positions \r
-#define GIRQ15_UART0_BITPOS (0)\r
-#define GIRQ15_IMAP_BITPOS (2)\r
-#define GIRQ15_KBD_K_BITPOS (3)\r
-#define GIRQ15_KBD_M_BITPOS (4)\r
-#define GIRQ15_ACPI0_IBF_BITPOS (6)\r
-#define GIRQ15_ACPI0_OBF_BITPOS (7)\r
-#define GIRQ15_ACPI1_IBF_BITPOS (8)\r
-#define GIRQ15_ACPI1_OBF_BITPOS (9)\r
-#define GIRQ15_ACPI_PM1CTL_BITPOS (10)\r
-#define GIRQ15_ACPI_PM1EN_BITPOS (11)\r
-#define GIRQ15_ACPI_PM1STS_BITPOS (12)\r
-#define GIRQ15_MF8042_OBF_BITPOS (13)\r
-#define GIRQ15_MF8042_IBF_BITPOS (14)\r
-#define GIRQ15_MAILBOX_BITPOS (15)\r
-#define GIRQ15_MAILBOX_DATA_BITPOS (16)\r
-//\r
-#define GIRQ15_MASK (0x01FFDDul)\r
-#define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul)\r
-//\r
-\r
-// GIRQ16 Bit Positions \r
-#define GIRQ16_PECI_BITPOS (3)\r
-//\r
-#define GIRQ16_MASK (0x08ul)\r
-#define GIRQ16_WAKE_CAPABLE_MASK (0x00ul)\r
-//\r
-\r
-// GIRQ17 Bit Positions \r
-#define GIRQ17_TACH0_BITPOS (0)\r
-#define GIRQ17_TACH1_BITPOS (1)\r
-#define GIRQ17_PS2_0_WAKE_BITPOS (2)\r
-#define GIRQ17_PS2_1_WAKE_BITPOS (3)\r
-#define GIRQ17_PS2_2_WAKE_BITPOS (4)\r
-#define GIRQ17_PS2_3_WAKE_BITPOS (5)\r
-#define GIRQ17_BC_WAKE_BITPOS (6)\r
-// RESERVED b[9:7]\r
-#define GIRQ17_ADC_INT0_BITPOS (10)\r
-#define GIRQ17_ADC_INT1_BITPOS (11)\r
-#define GIRQ17_V2P_INT0_BITPOS (12)\r
-#define GIRQ17_V2P_INT1_BITPOS (13)\r
-#define GIRQ17_PS2_0_BITPOS (14)\r
-#define GIRQ17_PS2_1_BITPOS (15)\r
-#define GIRQ17_PS2_2_BITPOS (16)\r
-#define GIRQ17_PS2_3_BITPOS (17)\r
-// RESERVED b[19:18]\r
-#define GIRQ17_HIBTMR_BITPOS (20)\r
-#define GIRQ17_KEY_INT_BITPOS (21)\r
-#define GIRQ17_KEY_INT_WAKE_BITPOS (22)\r
-#define GIRQ17_RPM_STALL_BITPOS (23)\r
-#define GIRQ17_RPM_SPIN_BITPOS (24)\r
-#define GIRQ17_VBAT_BITPOS (25)\r
-#define GIRQ17_LED0_BITPOS (26)\r
-#define GIRQ17_LED1_BITPOS (27)\r
-#define GIRQ17_LED2_BITPOS (28)\r
-#define GIRQ17_MBC_ERR_BITPOS (29)\r
-#define GIRQ17_MBC_BUSY_BITPOS (30)\r
-//\r
-#define GIRQ17_MASK (0x7FF3FC7Ful)\r
-#define GIRQ17_WAKE_CAPABLE_MASK (0x0230007Cul)\r
-//\r
-\r
-// GIRQ18 Bit Positions \r
-#define GIRQ18_SPI0_TX_BITPOS (0)\r
-#define GIRQ18_SPI0_RX_BITPOS (1)\r
-#define GIRQ18_SPI1_TX_BITPOS (2)\r
-#define GIRQ18_SPI1_RX_BITPOS (3)\r
-#define GIRQ18_LED3_BITPOS (4) // NVIC 85\r
-#define GIRQ18_PKE_ERR_BITPOS (5) // NVIC 86\r
-#define GIRQ18_PKE_END_BITPOS (6) // NVIC 87\r
-#define GIRQ18_TRNG_BITPOS (7) // NVIC 88\r
-#define GIRQ18_AES_BITPOS (8) // NVIC 89\r
-#define GIRQ18_HASH_BITPOS (9) // NVIC 90\r
-//\r
-#define GIRQ18_MASK (0x0FFul)\r
-#define GIRQ18_WAKE_CAPABLE_MASK (0x000ul)\r
-//\r
-\r
-// GIRQ19 Bit Positions \r
-#define GIRQ19_LRESET_BITPOS (0)\r
-#define GIRQ19_VCC_PWRGD_BITPOS (1)\r
-//\r
-#define GIRQ19_MASK (0x03ul)\r
-#define GIRQ19_WAKE_CAPABLE_MASK (0x03ul)\r
-//\r
-\r
-// GIRQ20 Bit Positions \r
-#define GIRQ20_GPIO_0200_BITPOS (0)\r
-#define GIRQ20_GPIO_0201_BITPOS (1)\r
-#define GIRQ20_GPIO_0202_BITPOS (2)\r
-#define GIRQ20_GPIO_0203_BITPOS (3)\r
-#define GIRQ20_GPIO_0204_BITPOS (4)\r
-//#define GIRQ20_GPIO_0205_BITPOS (5)\r
-#define GIRQ20_GPIO_0206_BITPOS (6)\r
-//#define GIRQ20_GPIO_0207_BITPOS (7)\r
-//\r
-#define GIRQ20_GPIO_0210_BITPOS (8)\r
-#define GIRQ20_GPIO_0211_BITPOS (9)\r
-#define GIRQ20_GPIO_0212_BITPOS (10)\r
-#define GIRQ20_GPIO_0213_BITPOS (11)\r
-// \r
-#define GIRQ20_MASK (0x0F5Ful)\r
-#define GIRQ20_WAKE_CAPABLE_MASK (0x0F5Ful)\r
-//\r
-\r
-// GIRQ21 Bit Positions \r
-#define GIRQ21_MASK (0x00ul)\r
-#define GIRQ21_WAKE_CAPABLE_MASK (0x00ul)\r
-\r
-// GIRQ22 Bit Positions \r
-#define GIRQ22_MASK (0x00ul)\r
-#define GIRQ22_WAKE_CAPABLE_MASK (0x00ul)\r
-\r
-// GIRQ23 Bit Positions \r
-#define GIRQ23_TMR0_BITPOS (0)\r
-#define GIRQ23_TMR1_BITPOS (1)\r
-#define GIRQ23_TMR2_BITPOS (2)\r
-#define GIRQ23_TMR3_BITPOS (3)\r
-#define GIRQ23_TMR4_BITPOS (4)\r
-#define GIRQ23_TMR5_BITPOS (5)\r
-//\r
-#define GIRQ23_MASK (0x03Ful)\r
-#define GIRQ23_WAKE_CAPABLE_MASK (0x000ul)\r
-//\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* NVIC,ECIA Routing Policy for Direct Mode */\r
-/* ------------------------------------------------------------------------------- */\r
-/* In Direct Mode, some interrupts could be configured to be used as aggregated.\r
- * Configuration:\r
- * 1. Always set ECS Interrupt Direct enable bit. \r
- * 2. If GIRQn aggregated set Block Enable bit.\r
- * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.\r
- * Switching issues:\r
- * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.\r
- * Also requires set/clear of individual NVIC Enables.\r
- * \r
- * Note: interrupt_is_girq_direct() internal function uses this policy to detect \r
- * if any interrupt is configured as direct or aggregated\r
-*/\r
-\r
-/** Initialize EC Interrupt Aggregator\r
- * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode \r
- * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated \r
- * This parameter is only applicable in direct mode.\r
- * @note All GPIO's and wake capable sources are always \r
- * aggregated! GPIO's interrupts will still work in direct mode.\r
- * Block wakes are not be routed to the processor in direct \r
- * mode. \r
- * Note2: This function disables and enables global interrupt \r
- */\r
-void interrupt_init(uint8_t mode, uint32_t girq_bitmask);\r
-\r
-/** Set interrupt routing mode to aggregated or direct. \r
- * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated \r
- * @note In direct mode, one could enable certain GIRQs as aggregated using \r
- * p_interrupt_ecia_block_enable_set function\r
- */\r
-void interrupt_mode_set(uint8_t mode);\r
-\r
-/** Clears all individual interrupts Enables and Source in ECIA,\r
- * and Clears all NVIC external enables and pending bits \r
- */\r
-void interrupt_reset(void);\r
-\r
-/** Enables interrupt for a device \r
- * @param dev_iroute - source IROUTING information \r
- * @note This function disables and enables global interrupt \r
- */\r
-void interrupt_device_enable(uint32_t dev_iroute);\r
-\r
-/** Disables interrupt for a device\r
- * @param dev_iroute - source IROUTING information \r
- * @note This function disables and enables global interrupt \r
- */\r
-void interrupt_device_disable(uint32_t dev_iroute);\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* ECIA APIs using device IROUTE() as input */ \r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Clear Source in the ECIA for the device \r
- * @param devi - device IROUTING value \r
- */\r
-void interrupt_device_ecia_source_clear(const uint32_t dev_iroute);\r
-\r
-/** Get the Source bit in the ECIA for the device \r
- * @param devi - device IROUTING value \r
- * @return 0 if source bit not set; else non-zero value\r
- */\r
-uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute);\r
-\r
-/** Get the Result bit in the ECIA for the device \r
- * @param devi - device IROUTING value \r
- * @return 0 if result bit not set; else non-zero value\r
- */\r
-uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute);\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* NVIC APIs using device IROUTE() as input */ \r
-/* ------------------------------------------------------------------------------- */\r
-/* Note that if the device interrupt is aggregated, then these APIs would affect the \r
- * NVIC corresponding to the aggregated GIRQ \r
- */\r
-\r
-/** Enable/Disable the NVIC (in the NVIC controller) for the device\r
- * @param dev_iroute : source IROUTING information (encoded in a uint32_t)\r
- * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ \r
- * @note Recommended to use interrupt_device_enable, interrupt_device_disable\r
- * to enable/disable interrupts for the device, since those APIs configure ECIA as well\r
- */\r
-void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag);\r
-\r
-/** Set NVIC priority for specified peripheral interrupt source\r
- * @param dev_iroute - source IROUTING information (encoded in a uint32_t)\r
- * @param nvic_pri - NVIC Priority\r
- * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt \r
- * sources in the GIRQ. \r
- * 2. This function disables and enables global interrupt \r
- */\r
-void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri);\r
-\r
-/** Return NVIC priority for interrupt source\r
- * @param dev_iroute - source IROUTING information \r
- * @return uint32_t NVIC priority \r
- */\r
-uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute);\r
-\r
-/** Return NVIC pending for interrupt source\r
- * @param dev_iroute - source IROUTING information \r
- * @return uint8_t 0(not pending), 1 (pending in NVIC) \r
- * \r
- */\r
-uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute);\r
-\r
-/** Set NVIC pending for interrupt source\r
- * @param dev_iroute - source IROUTING information \r
- */\r
-void interrupt_device_nvic_pending_set(const uint32_t dev_iroute);\r
-\r
-/** Clears NVIC pending for interrupt source\r
- * @param dev_iroute - source IROUTING information \r
- * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear \r
- * @note This function disables and enables global interrupt \r
- */\r
-uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute);\r
- \r
-/* ------------------------------------------------------------------------------- */\r
-/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear *\r
- * and Status Register */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Enable specified GIRQ in ECIA block\r
- * @param girq_id - enum MEC_GIRQ_IDS \r
- */\r
- void p_interrupt_ecia_block_enable_set(uint8_t girq_id);\r
- \r
- /** Enable GIRQs in ECIA Block \r
- * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block \r
- */\r
-void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask);\r
-\r
-/** Check if specified GIRQ block enabled or not\r
- * @param girq_id - enum MEC_GIRQ_IDS \r
- * @return retVal - 1 if the particular GIRQ block enabled, else 0\r
- */\r
-uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id);\r
-\r
-/** Set all GIRQ block enables */\r
-void p_interrupt_ecia_block_enable_all_set(void);\r
-\r
-/** Clear specified GIRQ in ECIA Block \r
- * @param girq_id - enum MEC_GIRQ_IDS \r
- */\r
-void p_interrupt_ecia_block_enable_clr(uint8_t girq_id);\r
-\r
-/** Clear GIRQs in ECIA Block \r
- * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block \r
- */\r
-void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask);\r
-\r
-/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */\r
-void p_interrupt_ecia_block_enable_all_clr(void);\r
- \r
- /** Get status of GIRQ in ECIA Block\r
- * @param girq_id - enum MEC_GIRQ_IDS \r
- * @return 0 if status bit not set; else non-zero value\r
- */\r
-uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id);\r
-\r
-/** Reads the Block IRQ Vector Register\r
- * @return 32-bit value\r
- */\r
-uint32_t p_interrupt_ecia_block_irq_all_status_get(void);\r
-\r
-/* ---------------------------------------------------------------------------- */\r
-/* Peripheral Functions - Operations on GIRQx Source, Enable, Result *\r
- * and Enable Registers */\r
-/* ---------------------------------------------------------------------------- */\r
-\r
-/** Clear specified interrupt source bit in GIRQx\r
- * @param girq_id - enum MEC_GIRQ_IDS\r
- * @param bitnum -[0, 31]\r
- */\r
-void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum);\r
-\r
-/** Read the specified interrupt source bit in GIRQx\r
- * @param girq_id - enum MEC_GIRQ_IDS\r
- * @param bitnum -[0, 31]\r
- * @return 0 if source bit not set; else non-zero value\r
- */\r
-uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum);\r
-\r
-/** Enable the specified interrupt in GIRQx\r
- * girq_id - enum MEC_GIRQ_IDS\r
- * bitnum = [0, 31]\r
- */\r
-void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum);\r
-\r
-/** Disable the specified interrupt in GIRQx\r
- * girq_id - enum MEC_GIRQ_IDS\r
- * bitnum = [0, 31]\r
- */\r
-void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum);\r
-\r
-/** Read the status of the specified interrupt in GIRQx\r
- * girq_id - enum MEC_GIRQ_IDS\r
- * bitnum = [0, 31]\r
- * @return 0 if enable bit not set; else non-zero value\r
- */\r
-uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum);\r
-\r
-/** Read the result bit of the interrupt in GIRQx\r
- * @param girq_id - enum MEC_GIRQ_IDS\r
- * @param bitnum -[0, 31]\r
- * @return 0 if enable bit not set; else non-zero value\r
- */\r
-uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum);\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* Peripheral Function - Operations on all GIRQs */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Clear all aggregator GIRQn status registers */\r
-void p_interrupt_ecia_girqs_source_reset(void);\r
-\r
-/** Clear all aggregator GIRQn enables */\r
- void p_interrupt_ecia_girqs_enable_reset(void);\r
- \r
-/* ------------------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to set interrupt control */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Set interrupt control \r
- * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
- */\r
- void p_interrupt_control_set(uint8_t nvic_en_flag);\r
- \r
- /** Read interrupt control \r
- * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
- */\r
-uint8_t p_interrupt_control_get(void);\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* Peripheral Functions - NVIC */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller\r
- * @param nvic_num : NVIC number (see enum IRQn_Type)\r
- * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ\r
- * @note Application should perform this operation\r
- */\r
- void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag);\r
- \r
- /** ecia_nvic_clr_en - Clear all NVIC external enables */ \r
-void p_interrupt_nvic_extEnables_clr(void);\r
-\r
-/** Clear all NVIC external enables and pending bits */\r
-void p_interrupt_nvic_enpend_clr(void);\r
-\r
-/** Set NVIC external priorities to POR value */\r
-void p_interrupt_nvic_priorities_default_set(void);\r
-\r
-/** Set NVIC external priorities to specified priority (0 - 7)\r
- * @param zero-based 3-bit priority value: 0=highest, 7=lowest.\r
- * @note NVIC highest priority is the value 0, lowest is all 1's.\r
- * Each external interrupt has an 8-bit register and the priority \r
- * is left justified in the registers. MECxxx implements 8 priority \r
- * levels or bits [7:5] in the register. Lowest priority = 0xE0\r
- */\r
-void p_interrupt_nvic_priorities_set(uint8_t new_pri);\r
-\r
-#endif /*_INTERRUPT_H_*/\r
-\r
-/** @}\r
- */\r
-\r
-\r
-\r
+/*****************************************************************************
+* © 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $
+$DateTime: 2016/04/08 10:18:28 $
+$Author: pramans $
+Last Change: Corrected several header definations
+******************************************************************************/
+/** @file interrupt.h
+* \brief Interrupt Header File
+* \author jvasanth
+*
+* This file implements the Interrupt Module Header file
+******************************************************************************/
+
+/** @defgroup Interrupt
+ * @{
+ */
+
+#ifndef _INTERRUPT_H
+#define _INTERRUPT_H
+
+// GIRQ IDs for EC Interrupt Aggregator
+enum MEC_GIRQ_IDS
+{
+ MEC_GIRQ08_ID = 0,
+ MEC_GIRQ09_ID,
+ MEC_GIRQ10_ID,
+ MEC_GIRQ11_ID,
+ MEC_GIRQ12_ID,
+ MEC_GIRQ13_ID,
+ MEC_GIRQ14_ID,
+ MEC_GIRQ15_ID,
+ MEC_GIRQ16_ID,
+ MEC_GIRQ17_ID,
+ MEC_GIRQ18_ID,
+ MEC_GIRQ19_ID,
+ MEC_GIRQ20_ID,
+ MEC_GIRQ21_ID,
+ MEC_GIRQ22_ID,
+ MEC_GIRQ23_ID,
+ MEC_GIRQ_ID_MAX
+};
+
+//Bitmask of GIRQ in ECIA Block Registers
+#define MEC_GIRQ08_BITMASK (1UL << (MEC_GIRQ08_ID + 8))
+#define MEC_GIRQ09_BITMASK (1UL << (MEC_GIRQ09_ID + 8))
+#define MEC_GIRQ10_BITMASK (1UL << (MEC_GIRQ10_ID + 8))
+#define MEC_GIRQ11_BITMASK (1UL << (MEC_GIRQ11_ID + 8))
+#define MEC_GIRQ12_BITMASK (1UL << (MEC_GIRQ12_ID + 8))
+#define MEC_GIRQ13_BITMASK (1UL << (MEC_GIRQ13_ID + 8))
+#define MEC_GIRQ14_BITMASK (1UL << (MEC_GIRQ14_ID + 8))
+#define MEC_GIRQ15_BITMASK (1UL << (MEC_GIRQ15_ID + 8))
+#define MEC_GIRQ16_BITMASK (1UL << (MEC_GIRQ16_ID + 8))
+#define MEC_GIRQ17_BITMASK (1UL << (MEC_GIRQ17_ID + 8))
+#define MEC_GIRQ18_BITMASK (1UL << (MEC_GIRQ18_ID + 8))
+#define MEC_GIRQ19_BITMASK (1UL << (MEC_GIRQ19_ID + 8))
+#define MEC_GIRQ20_BITMASK (1UL << (MEC_GIRQ20_ID + 8))
+#define MEC_GIRQ21_BITMASK (1UL << (MEC_GIRQ21_ID + 8))
+#define MEC_GIRQ22_BITMASK (1UL << (MEC_GIRQ22_ID + 8))
+#define MEC_GIRQ23_BITMASK (1UL << (MEC_GIRQ23_ID + 8))
+
+#define INTERRUPT_MODE_ALL_AGGREGATED (0u)
+#define INTERRUPT_MODE_DIRECT (1u)
+
+// Bit map of GIRQs whose sources can be directly connected to the NVIC
+// GIRQs 12 - 18, 23
+#define ECIA_GIRQ_DIRECT_BITMAP (0x0087F000ul)
+
+/*
+ * n = b[7:0] = zero-based direct mapped NVIC ID
+ * m = b[15:8] = zero-based aggregated NVIC ID
+ * a = b[23:16] = block Aggregator register block ID
+ * b = b[31:24] = block bit position in Aggregator registers
+*/
+#define IROUTE(b,a,m,n) (((uint32_t)(n)&0xFFul) + \
+ (((uint32_t)(m)&0xFFul)<<8u) + \
+ ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \
+ (((uint32_t)(b)&0x1Ful)<<24))
+
+#define ECIA_NVIC_ID_BITPOS (0u)
+#define ECIA_IA_NVIC_ID_BITPOS (8u)
+#define ECIA_GIRQ_ID_BITPOS (16u)
+#define ECIA_GIRQ_BIT_BITPOS (24u)
+
+//
+// GIRQ08
+//
+#define GPIO_0140_IROUTE IROUTE(0,8,57,57)
+#define GPIO_0141_IROUTE IROUTE(1,8,57,57)
+#define GPIO_0142_IROUTE IROUTE(2,8,57,57)
+#define GPIO_0143_IROUTE IROUTE(3,8,57,57)
+#define GPIO_0144_IROUTE IROUTE(4,8,57,57)
+#define GPIO_0145_IROUTE IROUTE(5,8,57,57)
+#define GPIO_0146_IROUTE IROUTE(6,8,57,57)
+#define GPIO_0147_IROUTE IROUTE(7,8,57,57)
+//
+#define GPIO_0150_IROUTE IROUTE(8,8,57,57)
+#define GPIO_0151_IROUTE IROUTE(9,8,57,57)
+#define GPIO_0152_IROUTE IROUTE(10,8,57,57)
+#define GPIO_0153_IROUTE IROUTE(11,8,57,57)
+#define GPIO_0154_IROUTE IROUTE(12,8,57,57)
+#define GPIO_0155_IROUTE IROUTE(13,8,57,57)
+#define GPIO_0156_IROUTE IROUTE(14,8,57,57)
+#define GPIO_0157_IROUTE IROUTE(15,8,57,57)
+//
+#define GPIO_0160_IROUTE IROUTE(16,8,57,57)
+#define GPIO_0161_IROUTE IROUTE(17,8,57,57)
+#define GPIO_0162_IROUTE IROUTE(18,8,57,57)
+#define GPIO_0163_IROUTE IROUTE(19,8,57,57)
+#define GPIO_0164_IROUTE IROUTE(20,8,57,57)
+#define GPIO_0165_IROUTE IROUTE(21,8,57,57)
+
+//
+// GIRQ09
+//
+#define GPIO_0100_IROUTE IROUTE(0,9,58,58)
+#define GPIO_0101_IROUTE IROUTE(1,9,58,58)
+#define GPIO_0102_IROUTE IROUTE(2,9,58,58)
+#define GPIO_0103_IROUTE IROUTE(3,9,58,58)
+#define GPIO_0104_IROUTE IROUTE(4,9,58,58)
+#define GPIO_0105_IROUTE IROUTE(5,9,58,58)
+#define GPIO_0106_IROUTE IROUTE(6,9,58,58)
+#define GPIO_0107_IROUTE IROUTE(7,9,58,58)
+//
+#define GPIO_0110_IROUTE IROUTE(8,9,58,58)
+#define GPIO_0111_IROUTE IROUTE(9,9,58,58)
+#define GPIO_0112_IROUTE IROUTE(10,9,58,58)
+#define GPIO_0113_IROUTE IROUTE(11,9,58,58)
+#define GPIO_0114_IROUTE IROUTE(12,9,58,58)
+#define GPIO_0115_IROUTE IROUTE(13,9,58,58)
+#define GPIO_0116_IROUTE IROUTE(14,9,58,58)
+#define GPIO_0117_IROUTE IROUTE(15,9,58,58)
+//
+#define GPIO_0120_IROUTE IROUTE(16,9,58,58)
+#define GPIO_0121_IROUTE IROUTE(17,9,58,58)
+#define GPIO_0122_IROUTE IROUTE(18,9,58,58)
+#define GPIO_0124_IROUTE IROUTE(20,9,58,58)
+#define GPIO_0125_IROUTE IROUTE(21,9,58,58)
+#define GPIO_0126_IROUTE IROUTE(22,9,58,58)
+#define GPIO_0127_IROUTE IROUTE(23,9,58,58)
+//
+#define GPIO_0130_IROUTE IROUTE(24,9,58,58)
+#define GPIO_0131_IROUTE IROUTE(25,9,58,58)
+#define GPIO_0132_IROUTE IROUTE(26,9,58,58)
+#define GPIO_0133_IROUTE IROUTE(27,9,58,58)
+#define GPIO_0134_IROUTE IROUTE(28,9,58,58)
+#define GPIO_0135_IROUTE IROUTE(29,9,58,58)
+#define GPIO_0136_IROUTE IROUTE(30,9,58,58)
+
+//
+// GIRQ10
+//
+#define GPIO_0040_IROUTE IROUTE(0,10,59,59)
+#define GPIO_0041_IROUTE IROUTE(1,10,59,59)
+#define GPIO_0042_IROUTE IROUTE(2,10,59,59)
+#define GPIO_0043_IROUTE IROUTE(3,10,59,59)
+#define GPIO_0044_IROUTE IROUTE(4,10,59,59)
+#define GPIO_0045_IROUTE IROUTE(5,10,59,59)
+#define GPIO_0046_IROUTE IROUTE(6,10,59,59)
+#define GPIO_0047_IROUTE IROUTE(7,10,59,59)
+//
+#define GPIO_0050_IROUTE IROUTE(8,10,59,59)
+#define GPIO_0051_IROUTE IROUTE(9,10,59,59)
+#define GPIO_0052_IROUTE IROUTE(10,10,59,59)
+#define GPIO_0053_IROUTE IROUTE(11,10,59,59)
+#define GPIO_0054_IROUTE IROUTE(12,10,59,59)
+#define GPIO_0055_IROUTE IROUTE(13,10,59,59)
+#define GPIO_0056_IROUTE IROUTE(14,10,59,59)
+#define GPIO_0057_IROUTE IROUTE(15,10,59,59)
+//
+#define GPIO_0060_IROUTE IROUTE(16,10,59,59)
+#define GPIO_0061_IROUTE IROUTE(17,10,59,59)
+#define GPIO_0062_IROUTE IROUTE(18,10,59,59)
+#define GPIO_0063_IROUTE IROUTE(19,10,59,59)
+#define GPIO_0064_IROUTE IROUTE(20,10,59,59)
+#define GPIO_0065_IROUTE IROUTE(21,10,59,59)
+#define GPIO_0066_IROUTE IROUTE(22,10,59,59)
+#define GPIO_0067_IROUTE IROUTE(23,10,59,59)
+
+//
+// GIRQ11
+//
+#define GPIO_0000_IROUTE IROUTE(0,11,60,60)
+#define GPIO_0001_IROUTE IROUTE(1,11,60,60)
+#define GPIO_0002_IROUTE IROUTE(2,11,60,60)
+#define GPIO_0003_IROUTE IROUTE(3,11,60,60)
+#define GPIO_0004_IROUTE IROUTE(4,11,60,60)
+#define GPIO_0005_IROUTE IROUTE(5,11,60,60)
+#define GPIO_0006_IROUTE IROUTE(6,11,60,60)
+#define GPIO_0007_IROUTE IROUTE(7,11,60,60)
+//
+#define GPIO_0010_IROUTE IROUTE(8,11,60,60)
+#define GPIO_0011_IROUTE IROUTE(9,11,60,60)
+#define GPIO_0012_IROUTE IROUTE(10,11,60,60)
+#define GPIO_0013_IROUTE IROUTE(11,11,60,60)
+#define GPIO_0014_IROUTE IROUTE(12,11,60,60)
+#define GPIO_0015_IROUTE IROUTE(13,11,60,60)
+#define GPIO_0016_IROUTE IROUTE(14,11,60,60)
+#define GPIO_0017_IROUTE IROUTE(15,11,60,60)
+//
+#define GPIO_0020_IROUTE IROUTE(16,11,60,60)
+#define GPIO_0021_IROUTE IROUTE(17,11,60,60)
+#define GPIO_0022_IROUTE IROUTE(18,11,60,60)
+#define GPIO_0023_IROUTE IROUTE(19,11,60,60)
+#define GPIO_0024_IROUTE IROUTE(20,11,60,60)
+#define GPIO_0025_IROUTE IROUTE(21,11,60,60)
+#define GPIO_0026_IROUTE IROUTE(22,11,60,60)
+#define GPIO_0027_IROUTE IROUTE(23,11,60,60)
+//
+#define GPIO_0030_IROUTE IROUTE(24,11,60,60)
+#define GPIO_0031_IROUTE IROUTE(25,11,60,60)
+#define GPIO_0032_IROUTE IROUTE(26,11,60,60)
+#define GPIO_0033_IROUTE IROUTE(27,11,60,60)
+#define GPIO_0034_IROUTE IROUTE(28,11,60,60)
+#define GPIO_0035_IROUTE IROUTE(29,11,60,60)
+#define GPIO_0036_IROUTE IROUTE(30,11,60,60)
+
+//
+// GIRQ12
+//
+#define SMB0_IROUTE IROUTE(0,12,61,0)
+#define SMB1_IROUTE IROUTE(1,12,61,1)
+#define SMB2_IROUTE IROUTE(2,12,61,2)
+#define SMB3_IROUTE IROUTE(3,12,61,3)
+#define I2C0_0_WAKE_IROUTE IROUTE(4,12,61,61)
+#define I2C0_1_WAKE_IROUTE IROUTE(5,12,61,61)
+#define I2C2_0_WAKE_IROUTE IROUTE(6,12,61,61)
+#define I2C1_0_WAKE_IROUTE IROUTE(7,12,61,61)
+#define I2C3_0_WAKE_IROUTE IROUTE(8,12,61,61)
+
+//
+// GIRQ13
+//
+#define DMA0_IROUTE IROUTE(16,13,62,4)
+#define DMA1_IROUTE IROUTE(17,13,62,5)
+#define DMA2_IROUTE IROUTE(18,13,62,6)
+#define DMA3_IROUTE IROUTE(19,13,62,7)
+#define DMA4_IROUTE IROUTE(20,13,62,8)
+#define DMA5_IROUTE IROUTE(21,13,62,9)
+#define DMA6_IROUTE IROUTE(22,13,62,10)
+#define DMA7_IROUTE IROUTE(23,13,62,11)
+#define DMA8_IROUTE IROUTE(24,13,62,81)
+#define DMA9_IROUTE IROUTE(25,13,62,82)
+#define DMA10_IROUTE IROUTE(26,13,62,83)
+#define DMA11_IROUTE IROUTE(27,13,62,84)
+
+//
+// GIRQ14
+//
+#define LPC_BERR_IROUTE IROUTE(2,14,63,12)
+
+//
+// GIRQ15
+//
+#define UART0_IROUTE IROUTE(0,15,64,13)
+#define EMI0_IROUTE IROUTE(2,15,64,14)
+#define ACPI_EC0_IBF_IROUTE IROUTE(6,15,64,15)
+#define ACPI_EC0_OBF_IROUTE IROUTE(7,15,64,16)
+#define ACPI_EC1_IBF_IROUTE IROUTE(8,15,64,17)
+#define ACPI_EC1_OBF_IROUTE IROUTE(9,15,64,18)
+#define ACPI_PM1_CTL_IROUTE IROUTE(10,15,64,19)
+#define ACPI_PM1_EN_IROUTE IROUTE(11,15,64,20)
+#define ACPI_PM1_STS_IROUTE IROUTE(12,15,64,21)
+#define EM8042_OBF_IROUTE IROUTE(13,15,64,22)
+#define EM8042_IBF_IROUTE IROUTE(14,15,64,23)
+#define MBOX_IROUTE IROUTE(15,15,64,24)
+#define MBOX_DATA_IROUTE IROUTE(16,15,64,40)
+
+//
+// GIRQ16
+//
+#define PECI_IROUTE IROUTE(3,16,65,25)
+
+//
+// GIRQ17
+//
+#define TACH0_IROUTE IROUTE(0,17,66,26)
+#define TACH1_IROUTE IROUTE(1,17,66,27)
+#define PS2_0_WAKE_IROUTE IROUTE(2,17,66,66)
+#define PS2_1_WAKE_IROUTE IROUTE(3,17,66,66)
+#define PS2_2_WAKE_IROUTE IROUTE(4,17,66,66)
+#define PS2_3_WAKE_IROUTE IROUTE(5,17,66,66)
+#define BC_WAKE_IROUTE IROUTE(6,17,66,66)
+#define ADC_SNGL_IROUTE IROUTE(10,17,66,28)
+#define ADC_RPT_IROUTE IROUTE(11,17,66,29)
+#define ADC2PWM1_IROUTE IROUTE(12,17,66,30)
+#define ADC2PWM2_IROUTE IROUTE(13,17,66,31)
+#define PS2_0_IROUTE IROUTE(14,17,66,32)
+#define PS2_1_IROUTE IROUTE(15,17,66,33)
+#define PS2_2_IROUTE IROUTE(16,17,66,34)
+#define PS2_3_IROUTE IROUTE(17,17,66,35)
+#define RTC_IROUTE IROUTE(18,17,66,91)
+#define RTC_ALARM_IROUTE IROUTE(19,17,66,92)
+#define HTIMER_IROUTE IROUTE(20,17,66,38)
+#define KSC_IROUTE IROUTE(21,17,66,39)
+#define KSC_WAKE_IROUTE IROUTE(22,17,66,66)
+#define RPM_STALL_IROUTE IROUTE(23,17,66,41)
+#define RPM_SPIN_IROUTE IROUTE(24,17,66,42)
+#define PFR_IROUTE IROUTE(25,17,66,43)
+#define PWM_WDT_0_IROUTE IROUTE(26,17,66,44)
+#define PWM_WDT_1_IROUTE IROUTE(27,17,66,45)
+#define PWM_WDT_2_IROUTE IROUTE(28,17,66,46)
+#define BCM_ERR_IROUTE IROUTE(29,17,66,47)
+#define BCM_BUSY_IROUTE IROUTE(30,17,66,48)
+
+//
+// GIRQ18
+//
+#define SPI0_TX_IROUTE IROUTE(0,18,67,36)
+#define SPI0_RX_IROUTE IROUTE(1,18,67,37)
+#define SPI1_TX_IROUTE IROUTE(2,18,67,55)
+#define SPI1_RX_IROUTE IROUTE(3,18,67,56)
+#define LED3_IROUTE IROUTE(4,18,67,85)
+#define PKE_ERR_IROUTE IROUTE(5,18,67,86)
+#define PKE_END_IROUTE IROUTE(6,18,67,87)
+#define NDRNG_IROUTE IROUTE(7,18,67,88)
+#define AES_IROUTE IROUTE(8,18,67,89)
+#define HASH_IROUTE IROUTE(9,18,67,90)
+
+//
+// GIRQ19, Aggregated only
+//
+#define VCC_PWRGD_IROUTE IROUTE(0,19,68,68)
+#define LRESET_IROUTE IROUTE(1,19,68,68)
+
+//
+// GIRQ20, Aggregated only
+//
+#define GPIO_0200_IROUTE IROUTE(0,20,69,69)
+#define GPIO_0201_IROUTE IROUTE(1,20,69,69)
+#define GPIO_0202_IROUTE IROUTE(2,20,69,69)
+#define GPIO_0203_IROUTE IROUTE(3,20,69,69)
+#define GPIO_0204_IROUTE IROUTE(4,20,69,69)
+//
+#define GPIO_0206_IROUTE IROUTE(6,20,69,69)
+//
+#define GPIO_0210_IROUTE IROUTE(8,20,69,69)
+#define GPIO_0211_IROUTE IROUTE(9,20,69,69)
+#define GPIO_0212_IROUTE IROUTE(10,20,69,69)
+#define GPIO_0213_IROUTE IROUTE(11,20,69,69)
+
+//
+// GIRQ21
+//
+// No sources
+
+//
+// GIRQ22
+//
+// No sources
+
+//
+// GIRQ23
+//
+#define BTMR0_IROUTE IROUTE(0,23,72,49)
+#define BTMR1_IROUTE IROUTE(1,23,72,50)
+#define BTMR2_IROUTE IROUTE(2,23,72,51)
+#define BTMR3_IROUTE IROUTE(3,23,72,52)
+#define BTMR4_IROUTE IROUTE(4,23,72,53)
+#define BTMR5_IROUTE IROUTE(5,23,72,54)
+
+
+//
+// GIRQ08 Bit Positions
+//
+#define GIRQ08_GPIO_0140_BITPOS (0)
+#define GIRQ08_GPIO_0141_BITPOS (1)
+#define GIRQ08_GPIO_0142_BITPOS (2)
+#define GIRQ08_GPIO_0143_BITPOS (3)
+#define GIRQ08_GPIO_0144_BITPOS (4)
+#define GIRQ08_GPIO_0145_BITPOS (5)
+#define GIRQ08_GPIO_0146_BITPOS (6)
+#define GIRQ08_GPIO_0147_BITPOS (7)
+//
+#define GIRQ08_GPIO_0150_BITPOS (8)
+#define GIRQ08_GPIO_0151_BITPOS (9)
+#define GIRQ08_GPIO_0152_BITPOS (10)
+#define GIRQ08_GPIO_0153_BITPOS (11)
+#define GIRQ08_GPIO_0154_BITPOS (12)
+#define GIRQ08_GPIO_0155_BITPOS (13)
+#define GIRQ08_GPIO_0156_BITPOS (14)
+#define GIRQ08_GPIO_0157_BITPOS (15)
+//
+#define GIRQ08_GPIO_0160_BITPOS (16)
+#define GIRQ08_GPIO_0161_BITPOS (17)
+#define GIRQ08_GPIO_0162_BITPOS (18)
+#define GIRQ08_GPIO_0163_BITPOS (19)
+#define GIRQ08_GPIO_0164_BITPOS (20)
+#define GIRQ08_GPIO_0165_BITPOS (21)
+#define GIRQ08_GPIO_0166_BITPOS (22)
+#define GIRQ08_GPIO_0167_BITPOS (23)
+//
+#define GIRQ08_MASK (0x00FFFFBFul)
+#define GIRQ08_WAKE_CAPABLE_MASK (0x00FFFFBFul)
+//
+
+//
+// GIRQ09 Bit Positions
+//
+#define GIRQ09_GPIO_0100_BITPOS (0)
+#define GIRQ09_GPIO_0101_BITPOS (1)
+#define GIRQ09_GPIO_0102_BITPOS (2)
+#define GIRQ09_GPIO_0103_BITPOS (3)
+#define GIRQ09_GPIO_0104_BITPOS (4)
+#define GIRQ09_GPIO_0105_BITPOS (5)
+#define GIRQ09_GPIO_0106_BITPOS (6)
+#define GIRQ09_GPIO_0107_BITPOS (7)
+//
+#define GIRQ09_GPIO_0110_BITPOS (8)
+#define GIRQ09_GPIO_0111_BITPOS (9)
+#define GIRQ09_GPIO_0112_BITPOS (10)
+#define GIRQ09_GPIO_0113_BITPOS (11)
+#define GIRQ09_GPIO_0114_BITPOS (12)
+#define GIRQ09_GPIO_0115_BITPOS (13)
+#define GIRQ09_GPIO_0116_BITPOS (14)
+#define GIRQ09_GPIO_0117_BITPOS (15)
+//
+#define GIRQ09_GPIO_0120_BITPOS (16)
+#define GIRQ09_GPIO_0121_BITPOS (17)
+#define GIRQ09_GPIO_0122_BITPOS (18)
+#define GIRQ09_GPIO_0123_BITPOS (19)
+#define GIRQ09_GPIO_0124_BITPOS (20)
+#define GIRQ09_GPIO_0125_BITPOS (21)
+#define GIRQ09_GPIO_0126_BITPOS (22)
+#define GIRQ09_GPIO_0127_BITPOS (23)
+//
+#define GIRQ09_GPIO_0130_BITPOS (24)
+#define GIRQ09_GPIO_0131_BITPOS (25)
+#define GIRQ09_GPIO_0132_BITPOS (26)
+#define GIRQ09_GPIO_0133_BITPOS (27)
+#define GIRQ09_GPIO_0134_BITPOS (28)
+#define GIRQ09_GPIO_0135_BITPOS (29)
+#define GIRQ09_GPIO_0136_BITPOS (30)
+//
+#define GIRQ09_MASK (0x7FF7FFFFul)
+#define GIRQ09_WAKE_CAPABLE_MASK (0x7FF7FFFFul)
+//
+
+//
+// GIRQ10 Bit Positions
+//
+#define GIRQ10_GPIO_0040_BITPOS (0)
+#define GIRQ10_GPIO_0041_BITPOS (1)
+#define GIRQ10_GPIO_0042_BITPOS (2)
+#define GIRQ10_GPIO_0043_BITPOS (3)
+#define GIRQ10_GPIO_0044_BITPOS (4)
+#define GIRQ10_GPIO_0045_BITPOS (5)
+#define GIRQ10_GPIO_0046_BITPOS (6)
+#define GIRQ10_GPIO_0047_BITPOS (7)
+//
+#define GIRQ10_GPIO_0050_BITPOS (8)
+#define GIRQ10_GPIO_0051_BITPOS (9)
+#define GIRQ10_GPIO_0052_BITPOS (10)
+#define GIRQ10_GPIO_0053_BITPOS (11)
+#define GIRQ10_GPIO_0054_BITPOS (12)
+#define GIRQ10_GPIO_0055_BITPOS (13)
+#define GIRQ10_GPIO_0056_BITPOS (14)
+#define GIRQ10_GPIO_0057_BITPOS (15)
+//
+#define GIRQ10_GPIO_0060_BITPOS (16)
+#define GIRQ10_GPIO_0061_BITPOS (17)
+#define GIRQ10_GPIO_0062_BITPOS (18)
+#define GIRQ10_GPIO_0063_BITPOS (19)
+#define GIRQ10_GPIO_0064_BITPOS (20)
+#define GIRQ10_GPIO_0065_BITPOS (21)
+#define GIRQ10_GPIO_0066_BITPOS (22)
+#define GIRQ10_GPIO_0067_BITPOS (23)
+//
+#define GIRQ10_MASK (0x7FFFFFFFul)
+#define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul)
+//
+
+// GIRQ11 Bit Positions
+#define GIRQ11_GPIO_0000_BITPOS (0)
+#define GIRQ11_GPIO_0001_BITPOS (1)
+#define GIRQ11_GPIO_0002_BITPOS (2)
+#define GIRQ11_GPIO_0003_BITPOS (3)
+#define GIRQ11_GPIO_0004_BITPOS (4)
+#define GIRQ11_GPIO_0005_BITPOS (5)
+#define GIRQ11_GPIO_0006_BITPOS (6)
+#define GIRQ11_GPIO_0007_BITPOS (7)
+//
+#define GIRQ11_GPIO_0010_BITPOS (8)
+#define GIRQ11_GPIO_0011_BITPOS (9)
+#define GIRQ11_GPIO_0012_BITPOS (10)
+#define GIRQ11_GPIO_0013_BITPOS (11)
+#define GIRQ11_GPIO_0014_BITPOS (12)
+#define GIRQ11_GPIO_0015_BITPOS (13)
+#define GIRQ11_GPIO_0016_BITPOS (14)
+#define GIRQ11_GPIO_0017_BITPOS (15)
+//
+#define GIRQ11_GPIO_0020_BITPOS (16)
+#define GIRQ11_GPIO_0021_BITPOS (17)
+#define GIRQ11_GPIO_0022_BITPOS (18)
+#define GIRQ11_GPIO_0023_BITPOS (19)
+#define GIRQ11_GPIO_0024_BITPOS (20)
+#define GIRQ11_GPIO_0025_BITPOS (21)
+#define GIRQ11_GPIO_0026_BITPOS (22)
+#define GIRQ11_GPIO_0027_BITPOS (23)
+//
+#define GIRQ11_GPIO_0030_BITPOS (24)
+#define GIRQ11_GPIO_0031_BITPOS (25)
+#define GIRQ11_GPIO_0032_BITPOS (26)
+#define GIRQ11_GPIO_0033_BITPOS (27)
+#define GIRQ11_GPIO_0034_BITPOS (28)
+#define GIRQ11_GPIO_0035_BITPOS (29)
+#define GIRQ11_GPIO_0036_BITPOS (30)
+//
+#define GIRQ11_MASK (0x7FFFFFFFul)
+#define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul)
+//
+
+// GIRQ12 Bit Positions
+#define GIRQ12_SMBUS0_BITPOS (0)
+#define GIRQ12_SMBUS1_BITPOS (1)
+#define GIRQ12_SMBUS2_BITPOS (2)
+#define GIRQ12_SMBUS3_BITPOS (3)
+#define GIRQ12_I2C0_0_WAKE_BITPOS (4)
+#define GIRQ12_I2C0_1_WAKE_BITPOS (5)
+#define GIRQ12_I2C2_0_WAKE_BITPOS (6)
+#define GIRQ12_I2C1_0_WAKE_BITPOS (7)
+#define GIRQ12_I2C3_0_WAKE_BITPOS (8)
+//
+#define GIRQ12_MASK (0x01FFul)
+#define GIRQ12_WAKE_CAPABLE_MASK (0x01F0ul)
+//
+
+//
+// GIRQ13 Bit Positions
+//
+#define GIRQ13_DMA0_BITPOS (16)
+#define GIRQ13_DMA1_BITPOS (17)
+#define GIRQ13_DMA2_BITPOS (18)
+#define GIRQ13_DMA3_BITPOS (19)
+#define GIRQ13_DMA4_BITPOS (20)
+#define GIRQ13_DMA5_BITPOS (21)
+#define GIRQ13_DMA6_BITPOS (22)
+#define GIRQ13_DMA7_BITPOS (23)
+#define GIRQ13_DMA8_BITPOS (24)
+#define GIRQ13_DMA9_BITPOS (25)
+#define GIRQ13_DMA10_BITPOS (26)
+#define GIRQ13_DMA11_BITPOS (27)
+//
+#define GIRQ13_MASK (0x0FFF0000ul)
+#define GIRQ13_WAKE_CAPABLE_MASK (0x00000000ul)
+//
+
+//
+// GIRQ14 Bit Positions
+//
+#define GIRQ14_LPC_BITPOS (2)
+//
+#define GIRQ14_MASK (0x04ul)
+#define GIRQ14_WAKE_CAPABLE_MASK (0x00ul)
+//
+
+//
+// GIRQ15 Bit Positions
+//
+#define GIRQ15_UART0_BITPOS (0)
+#define GIRQ15_IMAP_BITPOS (2)
+#define GIRQ15_ACPI0_IBF_BITPOS (6)
+#define GIRQ15_ACPI0_OBF_BITPOS (7)
+#define GIRQ15_ACPI1_IBF_BITPOS (8)
+#define GIRQ15_ACPI1_OBF_BITPOS (9)
+#define GIRQ15_ACPI_PM1CTL_BITPOS (10)
+#define GIRQ15_ACPI_PM1EN_BITPOS (11)
+#define GIRQ15_ACPI_PM1STS_BITPOS (12)
+#define GIRQ15_MF8042_OBF_BITPOS (13)
+#define GIRQ15_MF8042_IBF_BITPOS (14)
+#define GIRQ15_MAILBOX_BITPOS (15)
+#define GIRQ15_MAILBOX_DATA_BITPOS (16)
+//
+#define GIRQ15_MASK (0x01FFDDul)
+#define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul)
+//
+
+//
+// GIRQ16 Bit Positions
+//
+#define GIRQ16_PECI_BITPOS (3)
+//
+#define GIRQ16_MASK (0x08ul)
+#define GIRQ16_WAKE_CAPABLE_MASK (0x00ul)
+//
+
+//
+// GIRQ17 Bit Positions
+//
+#define GIRQ17_TACH0_BITPOS (0)
+#define GIRQ17_TACH1_BITPOS (1)
+#define GIRQ17_PS2_0_WAKE_BITPOS (2)
+#define GIRQ17_PS2_1_WAKE_BITPOS (3)
+#define GIRQ17_PS2_2_WAKE_BITPOS (4)
+#define GIRQ17_PS2_3_WAKE_BITPOS (5)
+#define GIRQ17_BC_WAKE_BITPOS (6)
+// RESERVED b[9:7]
+#define GIRQ17_ADC_INT0_BITPOS (10)
+#define GIRQ17_ADC_INT1_BITPOS (11)
+#define GIRQ17_V2P_INT0_BITPOS (12)
+#define GIRQ17_V2P_INT1_BITPOS (13)
+#define GIRQ17_PS2_0_BITPOS (14)
+#define GIRQ17_PS2_1_BITPOS (15)
+#define GIRQ17_PS2_2_BITPOS (16)
+#define GIRQ17_PS2_3_BITPOS (17)
+#define GIRQ17_RTC_BITPOS (18)
+#define GIRQ17_RTC_ALARM_BITPOS (19)
+#define GIRQ17_HIBTMR_BITPOS (20)
+#define GIRQ17_KEY_INT_BITPOS (21)
+#define GIRQ17_KEY_INT_WAKE_BITPOS (22)
+#define GIRQ17_RPM_STALL_BITPOS (23)
+#define GIRQ17_RPM_SPIN_BITPOS (24)
+#define GIRQ17_VBAT_BITPOS (25)
+#define GIRQ17_PWM_WDT_0_BITPOS (26)
+#define GIRQ17_PWM_WDT_1_BITPOS (27)
+#define GIRQ17_PWM_WDT_2_BITPOS (28)
+#define GIRQ17_MBC_ERR_BITPOS (29)
+#define GIRQ17_MBC_BUSY_BITPOS (30)
+//
+#define GIRQ17_MASK (0x7FF3FC7Ful)
+#define GIRQ17_WAKE_CAPABLE_MASK (0x0230007Cul)
+//
+
+//
+// GIRQ18 Bit Positions
+//
+#define GIRQ18_SPI0_TX_BITPOS (0)
+#define GIRQ18_SPI0_RX_BITPOS (1)
+#define GIRQ18_SPI1_TX_BITPOS (2)
+#define GIRQ18_SPI1_RX_BITPOS (3)
+#define GIRQ18_PWM_WDT_3_BITPOS (4) // NVIC 85
+#define GIRQ18_PKE_ERR_BITPOS (5) // NVIC 86
+#define GIRQ18_PKE_END_BITPOS (6) // NVIC 87
+#define GIRQ18_TRNG_BITPOS (7) // NVIC 88
+#define GIRQ18_AES_BITPOS (8) // NVIC 89
+#define GIRQ18_HASH_BITPOS (9) // NVIC 90
+//
+#define GIRQ18_MASK (0x0FFul)
+#define GIRQ18_WAKE_CAPABLE_MASK (0x000ul)
+//
+
+//
+// GIRQ19 Bit Positions
+//
+#define GIRQ19_VCC_PWRGD_BITPOS (0)
+#define GIRQ19_LRESET_BITPOS (1)
+//
+#define GIRQ19_MASK (0x03ul)
+#define GIRQ19_WAKE_CAPABLE_MASK (0x03ul)
+//
+
+//
+// GIRQ20 Bit Positions
+//
+#define GIRQ20_GPIO_0200_BITPOS (0)
+#define GIRQ20_GPIO_0201_BITPOS (1)
+#define GIRQ20_GPIO_0202_BITPOS (2)
+#define GIRQ20_GPIO_0203_BITPOS (3)
+#define GIRQ20_GPIO_0204_BITPOS (4)
+//
+#define GIRQ20_GPIO_0206_BITPOS (6)
+//
+#define GIRQ20_GPIO_0210_BITPOS (8)
+#define GIRQ20_GPIO_0211_BITPOS (9)
+#define GIRQ20_GPIO_0212_BITPOS (10)
+#define GIRQ20_GPIO_0213_BITPOS (11)
+//
+#define GIRQ20_MASK (0x0F5Ful)
+#define GIRQ20_WAKE_CAPABLE_MASK (0x0F5Ful)
+//
+
+//
+// GIRQ21 Bit Positions
+//
+#define GIRQ21_MASK (0x00ul)
+#define GIRQ21_WAKE_CAPABLE_MASK (0x00ul)
+
+//
+// GIRQ22 Bit Positions
+//
+#define GIRQ22_MASK (0x00ul)
+#define GIRQ22_WAKE_CAPABLE_MASK (0x00ul)
+
+//
+// GIRQ23 Bit Positions
+//
+#define GIRQ23_TMR0_BITPOS (0)
+#define GIRQ23_TMR1_BITPOS (1)
+#define GIRQ23_TMR2_BITPOS (2)
+#define GIRQ23_TMR3_BITPOS (3)
+#define GIRQ23_TMR4_BITPOS (4)
+#define GIRQ23_TMR5_BITPOS (5)
+//
+#define GIRQ23_MASK (0x03Ful)
+#define GIRQ23_WAKE_CAPABLE_MASK (0x000ul)
+//
+
+
+/* ------------------------------------------------------------------------------- */
+/* NVIC,ECIA Routing Policy for Direct Mode */
+/* ------------------------------------------------------------------------------- */
+/* In Direct Mode, some interrupts could be configured to be used as aggregated.
+ * Configuration:
+ * 1. Always set ECS Interrupt Direct enable bit.
+ * 2. If GIRQn aggregated set Block Enable bit.
+ * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.
+ * Switching issues:
+ * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.
+ * Also requires set/clear of individual NVIC Enables.
+ *
+ * Note: interrupt_is_girq_direct() internal function uses this policy to detect
+ * if any interrupt is configured as direct or aggregated
+*/
+
+/** Initialize EC Interrupt Aggregator
+ * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode
+ * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated
+ * This parameter is only applicable in direct mode.
+ * @note All GPIO's and wake capable sources are always
+ * aggregated! GPIO's interrupts will still work in direct mode.
+ * Block wakes are not be routed to the processor in direct
+ * mode.
+ * Note2: This function disables and enables global interrupt
+ */
+void interrupt_init(uint8_t mode, uint32_t girq_bitmask);
+
+/** Set interrupt routing mode to aggregated or direct.
+ * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated
+ * @note In direct mode, one could enable certain GIRQs as aggregated using
+ * p_interrupt_ecia_block_enable_set function
+ */
+void interrupt_mode_set(uint8_t mode);
+
+/** Clears all individual interrupts Enables and Source in ECIA,
+ * and Clears all NVIC external enables and pending bits
+ */
+void interrupt_reset(void);
+
+/** Enables interrupt for a device
+ * @param dev_iroute - source IROUTING information
+ * @note This function disables and enables global interrupt
+ */
+void interrupt_device_enable(uint32_t dev_iroute);
+
+/** Disables interrupt for a device
+ * @param dev_iroute - source IROUTING information
+ * @note This function disables and enables global interrupt
+ */
+void interrupt_device_disable(uint32_t dev_iroute);
+
+/* ------------------------------------------------------------------------------- */
+/* ECIA APIs using device IROUTE() as input */
+/* ------------------------------------------------------------------------------- */
+
+/** Clear Source in the ECIA for the device
+ * @param devi - device IROUTING value
+ */
+void interrupt_device_ecia_source_clear(const uint32_t dev_iroute);
+
+/** Get the Source bit in the ECIA for the device
+ * @param devi - device IROUTING value
+ * @return 0 if source bit not set; else non-zero value
+ */
+uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute);
+
+/** Get the Result bit in the ECIA for the device
+ * @param devi - device IROUTING value
+ * @return 0 if result bit not set; else non-zero value
+ */
+uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute);
+
+/* ------------------------------------------------------------------------------- */
+/* NVIC APIs using device IROUTE() as input */
+/* ------------------------------------------------------------------------------- */
+/* Note that if the device interrupt is aggregated, then these APIs would affect the
+ * NVIC corresponding to the aggregated GIRQ
+ */
+
+/** Enable/Disable the NVIC (in the NVIC controller) for the device
+ * @param dev_iroute : source IROUTING information (encoded in a uint32_t)
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ
+ * @note Recommended to use interrupt_device_enable, interrupt_device_disable
+ * to enable/disable interrupts for the device, since those APIs configure ECIA as well
+ */
+void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag);
+
+/** Set NVIC priority for specified peripheral interrupt source
+ * @param dev_iroute - source IROUTING information (encoded in a uint32_t)
+ * @param nvic_pri - NVIC Priority
+ * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt
+ * sources in the GIRQ.
+ * 2. This function disables and enables global interrupt
+ */
+void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri);
+
+/** Return NVIC priority for interrupt source
+ * @param dev_iroute - source IROUTING information
+ * @return uint32_t NVIC priority
+ */
+uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute);
+
+/** Return NVIC pending for interrupt source
+ * @param dev_iroute - source IROUTING information
+ * @return uint8_t 0(not pending), 1 (pending in NVIC)
+ *
+ */
+uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute);
+
+/** Set NVIC pending for interrupt source
+ * @param dev_iroute - source IROUTING information
+ */
+void interrupt_device_nvic_pending_set(const uint32_t dev_iroute);
+
+/** Clears NVIC pending for interrupt source
+ * @param dev_iroute - source IROUTING information
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear
+ * @note This function disables and enables global interrupt
+ */
+uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute);
+
+/* ------------------------------------------------------------------------------- */
+/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear *
+ * and Status Register */
+/* ------------------------------------------------------------------------------- */
+
+/** Enable specified GIRQ in ECIA block
+ * @param girq_id - enum MEC_GIRQ_IDS
+ */
+ void p_interrupt_ecia_block_enable_set(uint8_t girq_id);
+
+ /** Enable GIRQs in ECIA Block
+ * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block
+ */
+void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask);
+
+/** Check if specified GIRQ block enabled or not
+ * @param girq_id - enum MEC_GIRQ_IDS
+ * @return retVal - 1 if the particular GIRQ block enabled, else 0
+ */
+uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id);
+
+/** Set all GIRQ block enables */
+void p_interrupt_ecia_block_enable_all_set(void);
+
+/** Clear specified GIRQ in ECIA Block
+ * @param girq_id - enum MEC_GIRQ_IDS
+ */
+void p_interrupt_ecia_block_enable_clr(uint8_t girq_id);
+
+/** Clear GIRQs in ECIA Block
+ * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block
+ */
+void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask);
+
+/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */
+void p_interrupt_ecia_block_enable_all_clr(void);
+
+ /** Get status of GIRQ in ECIA Block
+ * @param girq_id - enum MEC_GIRQ_IDS
+ * @return 0 if status bit not set; else non-zero value
+ */
+uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id);
+
+/** Reads the Block IRQ Vector Register
+ * @return 32-bit value
+ */
+uint32_t p_interrupt_ecia_block_irq_all_status_get(void);
+
+/* ---------------------------------------------------------------------------- */
+/* Peripheral Functions - Operations on GIRQx Source, Enable, Result *
+ * and Enable Registers */
+/* ---------------------------------------------------------------------------- */
+
+/** Clear specified interrupt source bit in GIRQx
+ * @param girq_id - enum MEC_GIRQ_IDS
+ * @param bitnum -[0, 31]
+ */
+void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum);
+
+/** Read the specified interrupt source bit in GIRQx
+ * @param girq_id - enum MEC_GIRQ_IDS
+ * @param bitnum -[0, 31]
+ * @return 0 if source bit not set; else non-zero value
+ */
+uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum);
+
+/** Enable the specified interrupt in GIRQx
+ * girq_id - enum MEC_GIRQ_IDS
+ * bitnum = [0, 31]
+ */
+void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum);
+
+/** Disable the specified interrupt in GIRQx
+ * girq_id - enum MEC_GIRQ_IDS
+ * bitnum = [0, 31]
+ */
+void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum);
+
+/** Read the status of the specified interrupt in GIRQx
+ * girq_id - enum MEC_GIRQ_IDS
+ * bitnum = [0, 31]
+ * @return 0 if enable bit not set; else non-zero value
+ */
+uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum);
+
+/** Read the result bit of the interrupt in GIRQx
+ * @param girq_id - enum MEC_GIRQ_IDS
+ * @param bitnum -[0, 31]
+ * @return 0 if enable bit not set; else non-zero value
+ */
+uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum);
+
+/* ------------------------------------------------------------------------------- */
+/* Peripheral Function - Operations on all GIRQs */
+/* ------------------------------------------------------------------------------- */
+
+/** Clear all aggregator GIRQn status registers */
+void p_interrupt_ecia_girqs_source_reset(void);
+
+/** Clear all aggregator GIRQn enables */
+ void p_interrupt_ecia_girqs_enable_reset(void);
+
+/* ------------------------------------------------------------------------------- */
+/* Peripheral Function - Function to set interrupt control */
+/* ------------------------------------------------------------------------------- */
+
+/** Set interrupt control
+ * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled
+ */
+void p_interrupt_control_set(uint8_t nvic_en_flag);
+
+ /** Read interrupt control
+ * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled
+ */
+uint8_t p_interrupt_control_get(void);
+
+/* ------------------------------------------------------------------------------- */
+/* Peripheral Functions - NVIC */
+/* ------------------------------------------------------------------------------- */
+
+/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller
+ * @param nvic_num : NVIC number (see enum IRQn_Type)
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ
+ * @note Application should perform this operation
+ */
+void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag);
+
+ /** ecia_nvic_clr_en - Clear all NVIC external enables */
+void p_interrupt_nvic_extEnables_clr(void);
+
+/** Clear all NVIC external enables and pending bits */
+void p_interrupt_nvic_enpend_clr(void);
+
+/** Set NVIC external priorities to POR value */
+void p_interrupt_nvic_priorities_default_set(void);
+
+/** Set NVIC external priorities to specified priority (0 - 7)
+ * @param zero-based 3-bit priority value: 0=highest, 7=lowest.
+ * @note NVIC highest priority is the value 0, lowest is all 1's.
+ * Each external interrupt has an 8-bit register and the priority
+ * is left justified in the registers. MECxxx implements 8 priority
+ * levels or bits [7:5] in the register. Lowest priority = 0xE0
+ */
+void p_interrupt_nvic_priorities_set(uint8_t new_pri);
+
+#endif // #ifndef _INTERRUPT_H
+/* end interrupt.h */
+/** @}
+ */
+
+
+
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/11/24 06:28:28 $ \r
-$Author: amohandas $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file pcr.h\r
-* \brief Power, Clocks, and Resets Header file\r
-* \author jvasanth\r
-* \r
-* This file is the PCR header file \r
-******************************************************************************/\r
-\r
-/** @defgroup PCR\r
- * @{\r
- */\r
-\r
-#ifndef _PCR_H\r
-#define _PCR_H\r
-\r
-\r
-/******************************************************************************/\r
-/** PCR Register IDS \r
- *******************************************************************************/\r
-enum _PCR_REGSET_ID_\r
-{\r
- PCR_REG_CHIP_SLEEP_ENABLE =0,\r
- PCR_REG_CHIP_CLK_REQD_STS,\r
- PCR_REG_EC_SLEEP_ENABLE,\r
- PCR_REG_EC_CLK_REQD_STS,\r
- PCR_REG_HOST_SLEEP_ENABLE,\r
- PCR_REG_HOST_CLK_REQD_STS,\r
- PCR_REG_SYSTEM_SLEEP_CTRL, \r
- PCR_REG_PROCESSOR_CLK_CTRL = 8,\r
- PCR_REG_EC_SLEEP_ENABLE_2,\r
- PCR_REG_EC_CLK_REQD_STS_2,\r
- PCR_REG_SLOW_CLK_CTRL,\r
- PCR_REG_OSCILLATOR_ID,\r
- PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS,\r
- PCR_REG_CHIP_RESET_ENABLE,\r
- PCR_REG_HOST_RESET_ENABLE,\r
- PCR_REG_EC_RESET_ENABLE,\r
- PCR_REG_EC_RESET_ENABLE_2,\r
- PCR_REG_PWR_RESET_CTRL\r
-};\r
-/* ---------------------------------------------------------------------- */\r
-\r
-// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable\r
-//PCR register group 0 - CHIP\r
-#define PCR0_REGS_CHIP (((uint32_t)(PCR_REG_CHIP_SLEEP_ENABLE) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_CHIP_CLK_REQD_STS) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_CHIP_RESET_ENABLE) & 0xFF)<<16u))\r
-\r
-//PCR register group 1 - EC\r
-#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))\r
-\r
-//PCR register group 2 - HOST\r
-#define PCR2_REGS_HOST (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))\r
-\r
-//PCR register group 3 - EC 2\r
-#define PCR3_REGS_EC2 (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))\r
- \r
- \r
-//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR1_EC_INT_BITPOS (0u)\r
-#define PCR1_EC_PECI_BITPOS (1u)\r
-#define PCR1_EC_TACH0_BITPOS (2u)\r
-#define PCR1_EC_PWM0_BITPOS (4u)\r
-#define PCR1_EC_PMC_BITPOS (5u)\r
-#define PCR1_EC_DMA_BITPOS (6u)\r
-#define PCR1_EC_TFDP_BITPOS (7u)\r
-#define PCR1_EC_CPU_BITPOS (8u)\r
-#define PCR1_EC_WDT_BITPOS (9u)\r
-#define PCR1_EC_SMB0_BITPOS (10u)\r
-#define PCR1_EC_TACH1_BITPOS (11u)\r
-#define PCR1_EC_PWM1_BITPOS (20u)\r
-#define PCR1_EC_PWM2_BITPOS (21u)\r
-#define PCR1_EC_PWM3_BITPOS (22u)\r
-#define PCR1_EC_REG_BITPOS (29u)\r
-#define PCR1_EC_BTIMER0_BITPOS (30u)\r
-#define PCR1_EC_BTIMER1_BITPOS (31u)\r
-\r
-//PCR2_HOST -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR2_HOST_LPC_BITPOS (0u)\r
-#define PCR2_HOST_UART0_BITPOS (1u)\r
-#define PCR2_HOST_GLBL_CFG_BITPOS (12u)\r
-#define PCR2_HOST_ACPI_EC0_BITPOS (13u)\r
-#define PCR2_HOST_ACPI_EC1_BITPOS (14u)\r
-#define PCR2_HOST_ACPI_PM1_BITPOS (15u)\r
-#define PCR2_HOST_8042EM_BITPOS (16u)\r
-#define PCR2_HOST_RTC_BITPOS (18u)\r
-\r
-//PCR3_EC2 -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR3_EC2_ADC_BITPOS (3u)\r
-#define PCR3_EC2_PS2_0_BITPOS (5u)\r
-#define PCR3_EC2_PS2_1_BITPOS (6u)\r
-#define PCR3_EC2_PS2_2_BITPOS (7u)\r
-#define PCR3_EC2_PS2_3_BITPOS (8u)\r
-#define PCR3_EC2_SPI0_BITPOS (9u)\r
-#define PCR3_EC2_HTIMER_BITPOS (10u)\r
-#define PCR3_EC2_KEYSCAN_BITPOS (11u)\r
-#define PCR3_EC2_RPM_PWM_BITPOS (12u)\r
-#define PCR3_EC2_SMB1_BITPOS (13u)\r
-#define PCR3_EC2_SMB2_BITPOS (14u)\r
-#define PCR3_EC2_SMB3_BITPOS (15u)\r
-#define PCR3_EC2_LED0_BITPOS (16u)\r
-#define PCR3_EC2_LED1_BITPOS (17u)\r
-#define PCR3_EC2_LED2_BITPOS (18u)\r
-#define PCR3_EC2_BCM_BITPOS (19u)\r
-#define PCR3_EC2_SPI1_BITPOS (20u)\r
-#define PCR3_EC2_BTIMER2_BITPOS (21u)\r
-#define PCR3_EC2_BTIMER3_BITPOS (22u)\r
-#define PCR3_EC2_BTIMER4_BITPOS (23u)\r
-#define PCR3_EC2_BTIMER5_BITPOS (24u)\r
-#define PCR3_EC2_LED3_BITPOS (25u)\r
-\r
-/*\r
- * n = b[7:0] = PCR Reg Bit Position\r
- * m = b[31:8] = PCRx Regs IDs\r
- */\r
-//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul)) \r
-\r
-//PCRx_REGS_BIT positions \r
-#define PCRx_REGS_POS_SLEEP_ENABLE (8u)\r
-#define PCRx_REGS_POS_CLK_REQD_STS (16u)\r
-#define PCRx_REGS_POS_RESET_ENABLE (24u) \r
-\r
-\r
-/******************************************************************************/\r
-/** PCR Block IDS. \r
- * These IDs are used to directly refer to a block \r
- *******************************************************************************/\r
-typedef enum {\r
- PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)), \r
- PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)), \r
- PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)), \r
- PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)), \r
- PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)), \r
- PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)), \r
- PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)), \r
- PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)), \r
- PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)), \r
- PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)), \r
- PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)), \r
- PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)), \r
- PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)), \r
- PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)), \r
- PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)), \r
- PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)), \r
- PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)), \r
- PCR_LPC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_LPC_BITPOS & 0xFFu)),\r
- PCR_UART0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_UART0_BITPOS & 0xFFu)),\r
- PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_GLBL_CFG_BITPOS & 0xFFu)),\r
- PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC0_BITPOS & 0xFFu)),\r
- PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC1_BITPOS & 0xFFu)),\r
- PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_PM1_BITPOS & 0xFFu)),\r
- PCR_8042EM = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_8042EM_BITPOS & 0xFFu)),\r
- PCR_RTC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_RTC_BITPOS & 0xFFu)),\r
- PCR_ADC = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_ADC_BITPOS & 0xFFu)),\r
- PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_0_BITPOS & 0xFFu)), \r
- PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_1_BITPOS & 0xFFu)), \r
- PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_2_BITPOS & 0xFFu)), \r
- PCR_PS2_3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_3_BITPOS & 0xFFu)), \r
- PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI0_BITPOS & 0xFFu)), \r
- PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_HTIMER_BITPOS & 0xFFu)), \r
- PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_KEYSCAN_BITPOS & 0xFFu)), \r
- PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_RPM_PWM_BITPOS & 0xFFu)), \r
- PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB1_BITPOS & 0xFFu)), \r
- PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB2_BITPOS & 0xFFu)), \r
- PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB3_BITPOS & 0xFFu)), \r
- PCR_LED0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED0_BITPOS & 0xFFu)), \r
- PCR_LED1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED1_BITPOS & 0xFFu)), \r
- PCR_LED2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED2_BITPOS & 0xFFu)), \r
- PCR_BCM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BCM_BITPOS & 0xFFu)), \r
- PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI1_BITPOS & 0xFFu)), \r
- PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER2_BITPOS & 0xFFu)), \r
- PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER3_BITPOS & 0xFFu)), \r
- PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER4_BITPOS & 0xFFu)), \r
- PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER5_BITPOS & 0xFFu)), \r
- PCR_LED3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED3_BITPOS & 0xFFu)), \r
-} PCR_BLK_ID;\r
-\r
-\r
-/******************************************************************************/\r
-/** PCR Processor ClK Divide Values \r
- *******************************************************************************/\r
-enum PROCESSOR_CLK_DIVIDE_VALUE\r
-{\r
- PCR_CPU_CLK_DIVIDE_1 = 1,\r
- PCR_CPU_CLK_DIVIDE_4 = 4,\r
- PCR_CPU_CLK_DIVIDE_16 = 16,\r
- PCR_CPU_CLK_DIVIDE_48 = 48 \r
-};\r
-\r
-/******************************************************************************/\r
-/** System Sleep Modes \r
- *******************************************************************************/\r
-enum SYSTEM_SLEEP_MODES\r
-{\r
- SYSTEM_HEAVY_SLEEP_1 = 0, \r
- SYSTEM_HEAVY_SLEEP_3 = 1,\r
- SYSTEM_HEAVY_SLEEP_2 = 2,\r
- SYSTEM_DEEPEST_SLEEP = 5 \r
-};\r
-\r
-/* Bitmask for System Sleep Control Register */\r
-#define PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK (1UL<<0)\r
-#define PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK (1UL<<1)\r
-#define PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK (1UL<<2)\r
-\r
-/* Bitmask for Chip Sub-system Power Reset Status Register */\r
-#define PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK (1UL<<2)\r
-#define PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK (1UL<<3)\r
-#define PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK (1UL<<5)\r
-#define PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK (1UL<<6)\r
-#define PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK (1UL<<10)\r
-#define PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK (1UL<<11)\r
-\r
-/* Bitmask for Processor Clock Control Register */\r
-#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8)\r
-\r
-/* Bitmask for Power Reset Control Register */\r
-#define PCR_iRESET_OUT_BITMASK (1UL<<0)\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions to program Sleep Enable, CLK Reqd Status, *\r
- * Reset Enable for a block *\r
- * ---------------------------------------------------------------------- */\r
- /** Sets or Clears block specific bit in PCR Sleep Enable Register\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register\r
- */\r
-void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);\r
-\r
-/** Get Clock Required Status for the block\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @return uint8_t - 1 if Clock Required Status set, else 0\r
- */\r
-uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);\r
-\r
-/** Sets or Clears Reset Enable register bit for the block\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register\r
- */\r
-void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for entering low power modes */\r
-/* ---------------------------------------------------------------------- */\r
-/** Instructs all blocks to sleep by setting the Sleep Enable bits */\r
-void pcr_all_blocks_sleep(void);\r
-\r
-/** Clears the Sleep Enable bits for all blocks */\r
-void pcr_all_blocks_wake(void);\r
-\r
-/** Programs required sleep mode in System Sleep Control Register\r
- * @param sleep_mode - see enum SYSTEM_SLEEP_MODES\r
- */\r
-void pcr_system_sleep(uint8_t sleep_mode);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to program and read 32-bit values *\r
- * from PCR Registers *\r
- * ---------------------------------------------------------------------- */\r
- /** Write 32-bit value in the PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param value - 32-bit value\r
- */\r
-void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);\r
-\r
-/** Reads 32-bit value from the PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @return value - 32-bit value\r
- */\r
-uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to set, clr and get bits in *\r
- * PCR Registers * \r
- * ---------------------------------------------------------------------- */\r
- /** Sets bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to set \r
- */\r
-void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);\r
-\r
-/** Clears bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to clear \r
- */\r
-void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);\r
-\r
-/** Read bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to read \r
- * @return value - 32-bit value\r
- */\r
-uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);\r
-\r
-/** Sets or Clears bits in a PCR Register - Helper Function\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to set or clear\r
- * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register\r
- */\r
-void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);\r
- \r
-//Functions to operate on System Sleep Control Register \r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to operate on System Sleep Control *\r
- * Register * \r
- * ---------------------------------------------------------------------- */\r
-/** Sets/Clears the Ring oscillator power down bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag);\r
-\r
-/** Sets/Clears the Ring oscillator output gate bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag);\r
-\r
-/** Sets/Clears the Core regulator standby bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag);\r
-\r
-/** Writes required sleep mode in System Sleep Control Register\r
- * @param sleep_value - System Sleep control value - [D2, D1, D0]\r
- */\r
-void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);\r
-\r
-/** Reads the System Sleep Control PCR Register\r
- * @return value - byte 0 of the system sleep control PCR register\r
- */\r
-uint8_t p_pcr_system_sleep_ctrl_read(void);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to program to CLK Divide Value * \r
- * ---------------------------------------------------------------------- */\r
- /** Writes the clock divide value in the Processor Clock Control Register\r
- * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
- */\r
-void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to program the Slow Clock Control *\r
- * Register *\r
- * ---------------------------------------------------------------------- */\r
- /** Write the slow clock divide value in the Slow Clock Control Register\r
- * @param slow_clk_divide_value - slow clk divide value\r
- */\r
-void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to read the Oscillator Lock Status */ \r
-/* ---------------------------------------------------------------------- */\r
-/** Reads the Oscillator Lock status bit in the Oscillator ID Register\r
- * @return 1 if Oscillator Lock Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_oscillator_lock_sts_get(void);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to read various power status in *\r
- * Chip Sub-System register *\r
- * ---------------------------------------------------------------------- */\r
- /** Reads the VCC Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VCC Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void);\r
-\r
-/** Reads the SIO Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if SIO Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void);\r
-\r
-/** Reads the VBAT Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VBAT Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void);\r
-\r
-/** Clears the VBAT Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register \r
- */\r
-void p_pcr_chip_subsystem_vbat_reset_sts_clr(void);\r
-\r
-/** Reads the VCC1 Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VCC1 Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void);\r
-\r
-/** Clears the VCC1 Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register \r
- */\r
-void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void);\r
-\r
-/** Reads the 32K_ACTIVE status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if 32_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void);\r
-\r
-/** Reads the PCICLK_ACTIVE status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if CICLK_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions for Power Reset Control Register */ \r
-/* ---------------------------------------------------------------------- */\r
-/** Reads the iRESET_OUT bit in the Power Reset Control Register\r
- * @return 1 if iRESET_OUT bit is set, else 0\r
- */\r
-uint8_t p_pcr_iReset_Out_get(void);\r
-\r
-/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register\r
- * @param 1 Set iRESET_OUT bit; 0 - Clear the bit\r
- */\r
-void p_pcr_iReset_Out(uint8_t set_clr_flag);\r
-\r
-#endif // #ifndef _PCR_H\r
-/* end pcr.h */\r
-/** @}\r
- */\r
-\r
-\r
-\r
+/*****************************************************************************
+* © 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $
+$DateTime: 2016/04/08 10:18:28 $
+$Author: pramans $
+Last Change: Updated for tabs
+******************************************************************************/
+/** @file pcr.h
+* \brief Power, Clocks, and Resets Header file
+* \author jvasanth
+*
+* This file is the PCR header file
+******************************************************************************/
+
+/** @defgroup PCR
+ * @{
+ */
+
+#ifndef _PCR_H
+#define _PCR_H
+
+
+/******************************************************************************/
+/** PCR Register IDS
+ *******************************************************************************/
+enum _PCR_REGSET_ID_
+{
+ PCR_REG_CHIP_SLEEP_ENABLE =0,
+ PCR_REG_CHIP_CLK_REQD_STS,
+ PCR_REG_EC_SLEEP_ENABLE,
+ PCR_REG_EC_CLK_REQD_STS,
+ PCR_REG_HOST_SLEEP_ENABLE,
+ PCR_REG_HOST_CLK_REQD_STS,
+ PCR_REG_SYSTEM_SLEEP_CTRL,
+ PCR_REG_PROCESSOR_CLK_CTRL = 8,
+ PCR_REG_EC_SLEEP_ENABLE_2,
+ PCR_REG_EC_CLK_REQD_STS_2,
+ PCR_REG_SLOW_CLK_CTRL,
+ PCR_REG_OSCILLATOR_ID,
+ PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS,
+ PCR_REG_CHIP_RESET_ENABLE,
+ PCR_REG_HOST_RESET_ENABLE,
+ PCR_REG_EC_RESET_ENABLE,
+ PCR_REG_EC_RESET_ENABLE_2,
+ PCR_REG_PWR_RESET_CTRL
+};
+/* ---------------------------------------------------------------------- */
+
+// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable
+//PCR register group 0 - CHIP
+#define PCR0_REGS_CHIP (((uint32_t)(PCR_REG_CHIP_SLEEP_ENABLE) & 0xFF) + \
+ (((uint32_t)(PCR_REG_CHIP_CLK_REQD_STS) & 0xFF)<<8u) + \
+ (((uint32_t)(PCR_REG_CHIP_RESET_ENABLE) & 0xFF)<<16u))
+
+//PCR register group 1 - EC
+#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))
+
+//PCR register group 2 - HOST
+#define PCR2_REGS_HOST (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))
+
+//PCR register group 3 - EC 2
+#define PCR3_REGS_EC2 (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))
+
+
+//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
+#define PCR1_EC_INT_BITPOS (0u)
+#define PCR1_EC_PECI_BITPOS (1u)
+#define PCR1_EC_TACH0_BITPOS (2u)
+#define PCR1_EC_PWM0_BITPOS (4u)
+#define PCR1_EC_PMC_BITPOS (5u)
+#define PCR1_EC_DMA_BITPOS (6u)
+#define PCR1_EC_TFDP_BITPOS (7u)
+#define PCR1_EC_CPU_BITPOS (8u)
+#define PCR1_EC_WDT_BITPOS (9u)
+#define PCR1_EC_SMB0_BITPOS (10u)
+#define PCR1_EC_TACH1_BITPOS (11u)
+#define PCR1_EC_PWM1_BITPOS (20u)
+#define PCR1_EC_PWM2_BITPOS (21u)
+#define PCR1_EC_PWM3_BITPOS (22u)
+#define PCR1_EC_REG_BITPOS (29u)
+#define PCR1_EC_BTIMER0_BITPOS (30u)
+#define PCR1_EC_BTIMER1_BITPOS (31u)
+
+//PCR2_HOST -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
+#define PCR2_HOST_LPC_BITPOS (0u)
+#define PCR2_HOST_UART0_BITPOS (1u)
+#define PCR2_HOST_GLBL_CFG_BITPOS (12u)
+#define PCR2_HOST_ACPI_EC0_BITPOS (13u)
+#define PCR2_HOST_ACPI_EC1_BITPOS (14u)
+#define PCR2_HOST_ACPI_PM1_BITPOS (15u)
+#define PCR2_HOST_8042EM_BITPOS (16u)
+#define PCR2_HOST_RTC_BITPOS (18u)
+
+//PCR3_EC2 -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
+#define PCR3_EC2_ADC_BITPOS (3u)
+#define PCR3_EC2_PS2_0_BITPOS (5u)
+#define PCR3_EC2_PS2_1_BITPOS (6u)
+#define PCR3_EC2_PS2_2_BITPOS (7u)
+#define PCR3_EC2_PS2_3_BITPOS (8u)
+#define PCR3_EC2_SPI0_BITPOS (9u)
+#define PCR3_EC2_HTIMER_BITPOS (10u)
+#define PCR3_EC2_KEYSCAN_BITPOS (11u)
+#define PCR3_EC2_RPM_PWM_BITPOS (12u)
+#define PCR3_EC2_SMB1_BITPOS (13u)
+#define PCR3_EC2_SMB2_BITPOS (14u)
+#define PCR3_EC2_SMB3_BITPOS (15u)
+#define PCR3_EC2_LED0_BITPOS (16u)
+#define PCR3_EC2_LED1_BITPOS (17u)
+#define PCR3_EC2_LED2_BITPOS (18u)
+#define PCR3_EC2_BCM_BITPOS (19u)
+#define PCR3_EC2_SPI1_BITPOS (20u)
+#define PCR3_EC2_BTIMER2_BITPOS (21u)
+#define PCR3_EC2_BTIMER3_BITPOS (22u)
+#define PCR3_EC2_BTIMER4_BITPOS (23u)
+#define PCR3_EC2_BTIMER5_BITPOS (24u)
+#define PCR3_EC2_LED3_BITPOS (25u)
+
+/*
+ * n = b[7:0] = PCR Reg Bit Position
+ * m = b[31:8] = PCRx Regs IDs
+ */
+//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul))
+
+//PCRx_REGS_BIT positions
+#define PCRx_REGS_POS_SLEEP_ENABLE (8u)
+#define PCRx_REGS_POS_CLK_REQD_STS (16u)
+#define PCRx_REGS_POS_RESET_ENABLE (24u)
+
+
+/******************************************************************************/
+/** PCR Block IDS.
+ * These IDs are used to directly refer to a block
+ *******************************************************************************/
+typedef enum {
+ PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)),
+ PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)),
+ PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)),
+ PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)),
+ PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)),
+ PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)),
+ PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)),
+ PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)),
+ PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)),
+ PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)),
+ PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)),
+ PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)),
+ PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)),
+ PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)),
+ PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)),
+ PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)),
+ PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)),
+ PCR_LPC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_LPC_BITPOS & 0xFFu)),
+ PCR_UART0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_UART0_BITPOS & 0xFFu)),
+ PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_GLBL_CFG_BITPOS & 0xFFu)),
+ PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC0_BITPOS & 0xFFu)),
+ PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC1_BITPOS & 0xFFu)),
+ PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_PM1_BITPOS & 0xFFu)),
+ PCR_8042EM = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_8042EM_BITPOS & 0xFFu)),
+ PCR_RTC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_RTC_BITPOS & 0xFFu)),
+ PCR_ADC = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_ADC_BITPOS & 0xFFu)),
+ PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_0_BITPOS & 0xFFu)),
+ PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_1_BITPOS & 0xFFu)),
+ PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_2_BITPOS & 0xFFu)),
+ PCR_PS2_3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_3_BITPOS & 0xFFu)),
+ PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI0_BITPOS & 0xFFu)),
+ PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_HTIMER_BITPOS & 0xFFu)),
+ PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_KEYSCAN_BITPOS & 0xFFu)),
+ PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_RPM_PWM_BITPOS & 0xFFu)),
+ PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB1_BITPOS & 0xFFu)),
+ PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB2_BITPOS & 0xFFu)),
+ PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB3_BITPOS & 0xFFu)),
+ PCR_LED0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED0_BITPOS & 0xFFu)),
+ PCR_LED1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED1_BITPOS & 0xFFu)),
+ PCR_LED2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED2_BITPOS & 0xFFu)),
+ PCR_BCM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BCM_BITPOS & 0xFFu)),
+ PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI1_BITPOS & 0xFFu)),
+ PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER2_BITPOS & 0xFFu)),
+ PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER3_BITPOS & 0xFFu)),
+ PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER4_BITPOS & 0xFFu)),
+ PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER5_BITPOS & 0xFFu)),
+ PCR_LED3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED3_BITPOS & 0xFFu)),
+} PCR_BLK_ID;
+
+
+/******************************************************************************/
+/** PCR Processor ClK Divide Values
+ *******************************************************************************/
+enum PROCESSOR_CLK_DIVIDE_VALUE
+{
+ PCR_CPU_CLK_DIVIDE_1 = 1,
+ PCR_CPU_CLK_DIVIDE_4 = 4,
+ PCR_CPU_CLK_DIVIDE_16 = 16,
+ PCR_CPU_CLK_DIVIDE_48 = 48
+};
+
+/******************************************************************************/
+/** System Sleep Modes
+ *******************************************************************************/
+enum SYSTEM_SLEEP_MODES
+{
+ SYSTEM_HEAVY_SLEEP_1 = 0,
+ SYSTEM_HEAVY_SLEEP_3 = 1,
+ SYSTEM_HEAVY_SLEEP_2 = 2,
+ SYSTEM_DEEPEST_SLEEP = 5
+};
+
+/* Bitmask for System Sleep Control Register */
+#define PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK (1UL<<0)
+#define PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK (1UL<<1)
+#define PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK (1UL<<2)
+
+/* Bitmask for Chip Sub-system Power Reset Status Register */
+#define PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK (1UL<<2)
+#define PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK (1UL<<3)
+#define PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK (1UL<<5)
+#define PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK (1UL<<6)
+#define PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK (1UL<<10)
+#define PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK (1UL<<11)
+
+/* Bitmask for Processor Clock Control Register */
+#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8)
+
+/* Bitmask for Power Reset Control Register */
+#define PCR_iRESET_OUT_BITMASK (1UL<<0)
+
+/* ---------------------------------------------------------------------- */
+/* API - Functions to program Sleep Enable, CLK Reqd Status, *
+ * Reset Enable for a block *
+ * ---------------------------------------------------------------------- */
+ /** Sets or Clears block specific bit in PCR Sleep Enable Register
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
+ */
+void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
+
+/** Get Clock Required Status for the block
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
+ * @return uint8_t - 1 if Clock Required Status set, else 0
+ */
+uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);
+
+/** Sets or Clears Reset Enable register bit for the block
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
+ */
+void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
+
+/* ---------------------------------------------------------------------- */
+/* API - Functions for entering low power modes */
+/* ---------------------------------------------------------------------- */
+/** Instructs all blocks to sleep by setting the Sleep Enable bits */
+void pcr_all_blocks_sleep(void);
+
+/** Clears the Sleep Enable bits for all blocks */
+void pcr_all_blocks_wake(void);
+
+/** Programs required sleep mode in System Sleep Control Register
+ * @param sleep_mode - see enum SYSTEM_SLEEP_MODES
+ */
+void pcr_system_sleep(uint8_t sleep_mode);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions to program and read 32-bit values *
+ * from PCR Registers *
+ * ---------------------------------------------------------------------- */
+ /** Write 32-bit value in the PCR Register
+ * @param pcr_reg_id - pcr register id
+ * @param value - 32-bit value
+ */
+void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);
+
+/** Reads 32-bit value from the PCR Register
+ * @param pcr_reg_id - pcr register id
+ * @return value - 32-bit value
+ */
+uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions to set, clr and get bits in *
+ * PCR Registers *
+ * ---------------------------------------------------------------------- */
+ /** Sets bits in a PCR Register
+ * @param pcr_reg_id - pcr register id
+ * @param bit_mask - Bit mask of bits to set
+ */
+void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);
+
+/** Clears bits in a PCR Register
+ * @param pcr_reg_id - pcr register id
+ * @param bit_mask - Bit mask of bits to clear
+ */
+void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);
+
+/** Read bits in a PCR Register
+ * @param pcr_reg_id - pcr register id
+ * @param bit_mask - Bit mask of bits to read
+ * @return value - 32-bit value
+ */
+uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);
+
+/** Sets or Clears bits in a PCR Register - Helper Function
+ * @param pcr_reg_id - pcr register id
+ * @param bit_mask - Bit mask of bits to set or clear
+ * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
+ */
+void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);
+
+//Functions to operate on System Sleep Control Register
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions to operate on System Sleep Control *
+ * Register *
+ * ---------------------------------------------------------------------- */
+/** Sets/Clears the Ring oscillator power down bit
+ * in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag);
+
+/** Sets/Clears the Ring oscillator output gate bit
+ * in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag);
+
+/** Sets/Clears the Core regulator standby bit
+ * in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag);
+
+/** Writes required sleep mode in System Sleep Control Register
+ * @param sleep_value - System Sleep control value - [D2, D1, D0]
+ */
+void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);
+
+/** Reads the System Sleep Control PCR Register
+ * @return value - byte 0 of the system sleep control PCR register
+ */
+uint8_t p_pcr_system_sleep_ctrl_read(void);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Function to program to CLK Divide Value *
+ * ---------------------------------------------------------------------- */
+ /** Writes the clock divide value in the Processor Clock Control Register
+ * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
+ */
+void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Function to program the Slow Clock Control *
+ * Register *
+ * ---------------------------------------------------------------------- */
+ /** Write the slow clock divide value in the Slow Clock Control Register
+ * @param slow_clk_divide_value - slow clk divide value
+ */
+void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Function to read the Oscillator Lock Status */
+/* ---------------------------------------------------------------------- */
+/** Reads the Oscillator Lock status bit in the Oscillator ID Register
+ * @return 1 if Oscillator Lock Status bit is set, else 0
+ */
+uint8_t p_pcr_oscillator_lock_sts_get(void);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions to read various power status in *
+ * Chip Sub-System register *
+ * ---------------------------------------------------------------------- */
+ /** Reads the VCC Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VCC Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void);
+
+/** Reads the SIO Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if SIO Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void);
+
+/** Reads the VBAT Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VBAT Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void);
+
+/** Clears the VBAT Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ */
+void p_pcr_chip_subsystem_vbat_reset_sts_clr(void);
+
+/** Reads the VCC1 Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VCC1 Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void);
+
+/** Clears the VCC1 Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ */
+void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void);
+
+/** Reads the 32K_ACTIVE status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if 32_ACTIVE bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void);
+
+/** Reads the PCICLK_ACTIVE status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if CICLK_ACTIVE bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void);
+
+/* ---------------------------------------------------------------------- */
+/* Peripheral Function - Functions for Power Reset Control Register */
+/* ---------------------------------------------------------------------- */
+/** Reads the iRESET_OUT bit in the Power Reset Control Register
+ * @return 1 if iRESET_OUT bit is set, else 0
+ */
+uint8_t p_pcr_iReset_Out_get(void);
+
+/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register
+ * @param 1 Set iRESET_OUT bit; 0 - Clear the bit
+ */
+void p_pcr_iReset_Out(uint8_t set_clr_flag);
+
+#endif // #ifndef _PCR_H
+/* end pcr.h */
+/** @}
+ */
+
+
+
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/11/24 06:28:28 $ \r
-$Author: amohandas $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file pcr_api.c\r
-* \brief Power, Clocks, and Resets API Source file\r
-* \author jvasanth\r
-* \r
-* This file implements the PCR APIs \r
-******************************************************************************/\r
-\r
-/** @defgroup PCR\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "pcr.h"\r
-\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Sets or Clears block specific bit in PCR Sleep Enable Register\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register\r
- */\r
-void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)\r
-{\r
- uint32_t bit_mask;\r
- uint8_t pcr_reg_id; \r
- \r
- bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
- pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu);\r
-\r
- p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); \r
-}\r
-\r
-\r
-/** Get Clock Required Status for the block\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @return uint8_t - 1 if Clock Required Status set, else 0\r
- */\r
-uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id)\r
-{\r
- uint32_t bit_mask;\r
- uint8_t pcr_reg_id, retVal; \r
- \r
- bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
- pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu);\r
-\r
- retVal = 0;\r
- if (p_pcr_reg_get(pcr_reg_id, bit_mask))\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal;\r
-}\r
-\r
-/** Sets or Clears Reset Enable register bit for the block\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register\r
- */\r
-void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)\r
-{\r
- uint32_t bit_mask;\r
- uint8_t pcr_reg_id; \r
- \r
- bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
- pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu);\r
-\r
- p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); \r
-}\r
-\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* Functions for entering low power modes */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Instructs all blocks to sleep by setting the Sleep Enable bits */\r
-void pcr_all_blocks_sleep(void)\r
-{\r
- p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0xFFFFFFFF);\r
- p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0xFFFFFFFF);\r
- p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0xFFFFFFFF);\r
- p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF); \r
-}\r
-\r
-/** Clears the Sleep Enable bits for all blocks */\r
- void pcr_all_blocks_wake(void)\r
-{\r
- p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0);\r
- p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0);\r
- p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0);\r
- p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0); \r
-}\r
-\r
-/** Programs required sleep mode in System Sleep Control Register\r
- * @param sleep_mode - see enum SYSTEM_SLEEP_MODES\r
- */\r
-void pcr_system_sleep(uint8_t sleep_mode)\r
-{\r
- p_pcr_system_sleep_ctrl_write(sleep_mode);\r
-}\r
-\r
-\r
-/* end pcr_api.c */\r
-/** @}\r
- */\r
+/*****************************************************************************
+* © 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $
+$DateTime: 2016/04/08 10:18:28 $
+$Author: pramans $
+Last Change: Updated for tabs
+******************************************************************************/
+/** @file pcr_api.c
+* \brief Power, Clocks, and Resets API Source file
+* \author jvasanth
+*
+* This file implements the PCR APIs
+******************************************************************************/
+
+/** @defgroup PCR
+ * @{
+ */
+
+#include "common_lib.h"
+#include "pcr.h"
+
+
+/* ------------------------------------------------------------------------------- */
+/* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */
+/* ------------------------------------------------------------------------------- */
+
+/** Sets or Clears block specific bit in PCR Sleep Enable Register
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
+ */
+void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
+{
+ uint32_t bit_mask;
+ uint8_t pcr_reg_id;
+
+ bit_mask = 1UL<<(pcr_block_id & 0xFFu);
+ pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu);
+
+ p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);
+}
+
+
+/** Get Clock Required Status for the block
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
+ * @return uint8_t - 1 if Clock Required Status set, else 0
+ */
+uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id)
+{
+ uint32_t bit_mask;
+ uint8_t pcr_reg_id, retVal;
+
+ bit_mask = 1UL<<(pcr_block_id & 0xFFu);
+ pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu);
+
+ retVal = 0;
+ if (p_pcr_reg_get(pcr_reg_id, bit_mask))
+ {
+ retVal = 1;
+ }
+
+ return retVal;
+}
+
+/** Sets or Clears Reset Enable register bit for the block
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
+ */
+void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
+{
+ uint32_t bit_mask;
+ uint8_t pcr_reg_id;
+
+ bit_mask = 1UL<<(pcr_block_id & 0xFFu);
+ pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu);
+
+ p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);
+}
+
+
+/* ------------------------------------------------------------------------------- */
+/* Functions for entering low power modes */
+/* ------------------------------------------------------------------------------- */
+
+/** Instructs all blocks to sleep by setting the Sleep Enable bits */
+void pcr_all_blocks_sleep(void)
+{
+ p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0xFFFFFFFF);
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0xFFFFFFFF);
+ p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0xFFFFFFFF);
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF);
+}
+
+/** Clears the Sleep Enable bits for all blocks */
+ void pcr_all_blocks_wake(void)
+{
+ p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0);
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0);
+ p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0);
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0);
+}
+
+/** Programs required sleep mode in System Sleep Control Register
+ * @param sleep_mode - see enum SYSTEM_SLEEP_MODES
+ */
+void pcr_system_sleep(uint8_t sleep_mode)
+{
+ p_pcr_system_sleep_ctrl_write(sleep_mode);
+}
+
+
+/* end pcr_api.c */
+/** @}
+ */
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/11/24 06:28:28 $ \r
-$Author: amohandas $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file pcr_perphl.c\r
-* \brief Power, Clocks, and Resets Peripheral Source file\r
-* \author jvasanth\r
-* \r
-* This file implements the PCR Peripheral functions \r
-******************************************************************************/\r
-\r
-/** @defgroup PCR\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "pcr.h"\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Generic functions to program and read 32-bit values from PCR Registers */\r
-/* ---------------------------------------------------------------------- */\r
-/** Writes 32-bit value in the PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param value - 32-bit value\r
- */\r
-void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE); \r
-\r
- pPCR_Reg += pcr_reg_id;\r
-\r
- *pPCR_Reg = value; \r
-}\r
-\r
-/** Reads 32-bit value from the PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @return value - 32-bit value\r
- */\r
-uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint32_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE); \r
-\r
- pPCR_Reg += pcr_reg_id; \r
-\r
- retVal = *pPCR_Reg;\r
-\r
- return retVal;\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to set, clr and get bits in PCR Registers */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Sets bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to set \r
- */\r
-void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE); \r
-\r
- pPCR_Reg += pcr_reg_id;\r
-\r
- *pPCR_Reg |= bit_mask; \r
-}\r
-\r
-/** Clears bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to clear \r
- */\r
-void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE); \r
-\r
- pPCR_Reg += pcr_reg_id;\r
-\r
- *pPCR_Reg &= ~bit_mask; \r
-}\r
-\r
-/** Read bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to read \r
- * @return value - 32-bit value\r
- */\r
-uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint32_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE); \r
-\r
- pPCR_Reg += pcr_reg_id; \r
-\r
- retVal = (*pPCR_Reg) & bit_mask;\r
-\r
- return retVal;\r
-}\r
-\r
-/** Sets or Clears bits in a PCR Register - Helper Function\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to set or clear\r
- * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register\r
- */\r
-void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)\r
-{\r
- if (set_clr_flag)\r
- {\r
- p_pcr_reg_set(pcr_reg_id, bit_mask);\r
- }\r
- else\r
- {\r
- p_pcr_reg_clr(pcr_reg_id, bit_mask);\r
- } \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to operate on System Sleep Control Register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/**\r
- * Sets/Clears the Ring oscillator power down bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
- \r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;\r
-\r
- if (set_clr_flag)\r
- {\r
- *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK; \r
- }\r
- else\r
- {\r
- *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK; \r
- }\r
-}\r
-\r
-/** Sets/Clears the Ring oscillator output gate bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
- \r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;\r
-\r
- if (set_clr_flag)\r
- {\r
- *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK; \r
- }\r
- else\r
- {\r
- *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK; \r
- }\r
-}\r
-\r
-/** Sets/Clears the Core regulator standby bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
- \r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;\r
-\r
- if (set_clr_flag)\r
- {\r
- *pPCR_Reg |= PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK; \r
- }\r
- else\r
- {\r
- *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK; \r
- }\r
-}\r
-\r
-/** Writes required sleep mode in System Sleep Control Register\r
- * @param sleep_value - System Sleep control value - [D2, D1, D0]\r
- */\r
-void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
- \r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; \r
-\r
- *pPCR_Reg = (sleep_value & 0x7); \r
-}\r
-\r
-/** Reads the System Sleep Control PCR Register\r
- * @return value - byte 0 of the system sleep control PCR register\r
- */\r
-uint8_t p_pcr_system_sleep_ctrl_read(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
- \r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; \r
-\r
- retVal = (uint8_t)((*pPCR_Reg) & 0xFF);\r
-\r
- return retVal;\r
-}\r
-\r
-\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to program to CLK Divide Value */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Writes the clock divide value in the Processor Clock Control Register\r
- * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
- */\r
-void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; \r
-\r
- *pPCR_Reg = (clk_divide_value & 0xFF); \r
- \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to program the slow clock divide value */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Write the slow clock divide value in the Slow Clock Control Register\r
- * @param slow_clk_divide_value - slow clk divide value\r
- */\r
-void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL; \r
-\r
- *pPCR_Reg = (slow_clk_divide_value & 0x3FF); \r
-\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to read the Oscillator Lock Status */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Reads the Oscillator Lock status bit in the Oscillator ID Register\r
- * @return 1 if Oscillator Lock Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_oscillator_lock_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal;\r
- \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to read various power status in Chip Sub-System register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Reads the VCC Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VCC Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal; \r
-}\r
-\r
-/** Reads the SIO Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if SIO Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal; \r
-}\r
-\r
-/** Reads the VBAT Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VBAT Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal; \r
-}\r
-\r
-/** Clears the VBAT Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register \r
- */\r
-void p_pcr_chip_subsystem_vbat_reset_sts_clr(void)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;\r
-\r
- // Write to clear\r
- *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK;\r
- \r
-}\r
-\r
-/** Reads the VCC1 Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VCC1 Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal; \r
-}\r
-\r
-/** Clears the VCC1 Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register \r
- */\r
-void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;\r
-\r
- // Write to clear\r
- *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK;\r
- \r
-}\r
-\r
-/** Reads the 32K_ACTIVE status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if 32_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal; \r
-}\r
-\r
-/** Reads the PCICLK_ACTIVE status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if CICLK_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- } \r
- return retVal; \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for Power Reset Control Register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Reads the iRESET_OUT bit in the Power Reset Control Register\r
- * @return 1 if iRESET_OUT bit is set, else 0\r
- */\r
-uint8_t p_pcr_iReset_Out_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_iRESET_OUT_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal;\r
- \r
-}\r
-\r
-/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register\r
- * @param 1 Set iRESET_OUT bit; 0 - Clear the bit\r
- */\r
-void p_pcr_iReset_Out(uint8_t set_clr_flag)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;\r
-\r
- *pPCR_Reg = (set_clr_flag & 0x1); \r
-}\r
-\r
-\r
-/* end pcr_perphl.c */\r
-/** @}\r
- */\r
+/*****************************************************************************
+* © 2015 Microchip Technology Inc. and its subsidiaries.
+* You may use this software and any derivatives exclusively with
+* Microchip products.
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
+* OF THESE TERMS.
+******************************************************************************
+
+Version Control Information (Perforce)
+******************************************************************************
+$Revision: #1 $
+$DateTime: 2016/04/08 10:18:28 $
+$Author: pramans $
+Last Change: Updated for tabs
+******************************************************************************/
+/** @file pcr_perphl.c
+* \brief Power, Clocks, and Resets Peripheral Source file
+* \author jvasanth
+*
+* This file implements the PCR Peripheral functions
+******************************************************************************/
+
+/** @defgroup PCR
+ * @{
+ */
+
+#include "common_lib.h"
+#include "pcr.h"
+
+/* ---------------------------------------------------------------------- */
+/* Generic functions to program and read 32-bit values from PCR Registers */
+/* ---------------------------------------------------------------------- */
+/** Writes 32-bit value in the PCR Register
+ * @param pcr_reg_id - pcr register id
+ * @param value - 32-bit value
+ */
+void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE);
+
+ pPCR_Reg += pcr_reg_id;
+
+ *pPCR_Reg = value;
+}
+
+/** Reads 32-bit value from the PCR Register
+ * @param pcr_reg_id - pcr register id
+ * @return value - 32-bit value
+ */
+uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint32_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE);
+
+ pPCR_Reg += pcr_reg_id;
+
+ retVal = *pPCR_Reg;
+
+ return retVal;
+}
+
+/* ---------------------------------------------------------------------- */
+/* Functions to set, clr and get bits in PCR Registers */
+/* ---------------------------------------------------------------------- */
+
+/** Sets bits in a PCR Register
+ * @param pcr_reg_id - pcr register id
+ * @param bit_mask - Bit mask of bits to set
+ */
+void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE);
+
+ pPCR_Reg += pcr_reg_id;
+
+ *pPCR_Reg |= bit_mask;
+}
+
+/** Clears bits in a PCR Register
+ * @param pcr_reg_id - pcr register id
+ * @param bit_mask - Bit mask of bits to clear
+ */
+void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE);
+
+ pPCR_Reg += pcr_reg_id;
+
+ *pPCR_Reg &= ~bit_mask;
+}
+
+/** Read bits in a PCR Register
+ * @param pcr_reg_id - pcr register id
+ * @param bit_mask - Bit mask of bits to read
+ * @return value - 32-bit value
+ */
+uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint32_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE);
+
+ pPCR_Reg += pcr_reg_id;
+
+ retVal = (*pPCR_Reg) & bit_mask;
+
+ return retVal;
+}
+
+/** Sets or Clears bits in a PCR Register - Helper Function
+ * @param pcr_reg_id - pcr register id
+ * @param bit_mask - Bit mask of bits to set or clear
+ * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
+ */
+void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)
+{
+ if (set_clr_flag)
+ {
+ p_pcr_reg_set(pcr_reg_id, bit_mask);
+ }
+ else
+ {
+ p_pcr_reg_clr(pcr_reg_id, bit_mask);
+ }
+}
+
+/* ---------------------------------------------------------------------- */
+/* Functions to operate on System Sleep Control Register */
+/* ---------------------------------------------------------------------- */
+
+/**
+ * Sets/Clears the Ring oscillator power down bit
+ * in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
+
+ if (set_clr_flag)
+ {
+ *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK;
+ }
+ else
+ {
+ *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK;
+ }
+}
+
+/** Sets/Clears the Ring oscillator output gate bit
+ * in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
+
+ if (set_clr_flag)
+ {
+ *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK;
+ }
+ else
+ {
+ *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK;
+ }
+}
+
+/** Sets/Clears the Core regulator standby bit
+ * in System Sleep Control Register
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
+ */
+void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
+
+ if (set_clr_flag)
+ {
+ *pPCR_Reg |= PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK;
+ }
+ else
+ {
+ *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK;
+ }
+}
+
+/** Writes required sleep mode in System Sleep Control Register
+ * @param sleep_value - System Sleep control value - [D2, D1, D0]
+ */
+void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
+
+ *pPCR_Reg = (sleep_value & 0x7);
+}
+
+/** Reads the System Sleep Control PCR Register
+ * @return value - byte 0 of the system sleep control PCR register
+ */
+uint8_t p_pcr_system_sleep_ctrl_read(void)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint8_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
+
+ retVal = (uint8_t)((*pPCR_Reg) & 0xFF);
+
+ return retVal;
+}
+
+
+
+/* ---------------------------------------------------------------------- */
+/* Function to program to CLK Divide Value */
+/* ---------------------------------------------------------------------- */
+
+/** Writes the clock divide value in the Processor Clock Control Register
+ * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
+ */
+void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL;
+
+ *pPCR_Reg = (clk_divide_value & 0xFF);
+
+}
+
+/* ---------------------------------------------------------------------- */
+/* Function to program the slow clock divide value */
+/* ---------------------------------------------------------------------- */
+
+/** Write the slow clock divide value in the Slow Clock Control Register
+ * @param slow_clk_divide_value - slow clk divide value
+ */
+void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL;
+
+ *pPCR_Reg = (slow_clk_divide_value & 0x3FF);
+
+}
+
+/* ---------------------------------------------------------------------- */
+/* Function to read the Oscillator Lock Status */
+/* ---------------------------------------------------------------------- */
+
+/** Reads the Oscillator Lock status bit in the Oscillator ID Register
+ * @return 1 if Oscillator Lock Status bit is set, else 0
+ */
+uint8_t p_pcr_oscillator_lock_sts_get(void)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint8_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID;
+
+ retVal = 0;
+ if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)
+ {
+ retVal = 1;
+ }
+
+ return retVal;
+
+}
+
+/* ---------------------------------------------------------------------- */
+/* Functions to read various power status in Chip Sub-System register */
+/* ---------------------------------------------------------------------- */
+
+/** Reads the VCC Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VCC Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint8_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
+
+ retVal = 0;
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK)
+ {
+ retVal = 1;
+ }
+
+ return retVal;
+}
+
+/** Reads the SIO Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if SIO Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint8_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
+
+ retVal = 0;
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK)
+ {
+ retVal = 1;
+ }
+
+ return retVal;
+}
+
+/** Reads the VBAT Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VBAT Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint8_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
+
+ retVal = 0;
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK)
+ {
+ retVal = 1;
+ }
+
+ return retVal;
+}
+
+/** Clears the VBAT Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ */
+void p_pcr_chip_subsystem_vbat_reset_sts_clr(void)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
+
+ // Write to clear
+ *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK;
+
+}
+
+/** Reads the VCC1 Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if VCC1 Reset Status bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint8_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
+
+ retVal = 0;
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK)
+ {
+ retVal = 1;
+ }
+
+ return retVal;
+}
+
+/** Clears the VCC1 Reset Status bit
+ * in the Chip Subsystem Power Reset Status Register
+ */
+void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
+
+ // Write to clear
+ *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK;
+
+}
+
+/** Reads the 32K_ACTIVE status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if 32_ACTIVE bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint8_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
+
+ retVal = 0;
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK)
+ {
+ retVal = 1;
+ }
+
+ return retVal;
+}
+
+/** Reads the PCICLK_ACTIVE status bit
+ * in the Chip Subsystem Power Reset Status Register
+ * @return 1 if CICLK_ACTIVE bit is set, else 0
+ */
+uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint8_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
+
+ retVal = 0;
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK)
+ {
+ retVal = 1;
+ }
+ return retVal;
+}
+
+/* ---------------------------------------------------------------------- */
+/* Functions for Power Reset Control Register */
+/* ---------------------------------------------------------------------- */
+
+/** Reads the iRESET_OUT bit in the Power Reset Control Register
+ * @return 1 if iRESET_OUT bit is set, else 0
+ */
+uint8_t p_pcr_iReset_Out_get(void)
+{
+ __IO uint32_t *pPCR_Reg;
+ uint8_t retVal;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
+
+ retVal = 0;
+ if (*pPCR_Reg & PCR_iRESET_OUT_BITMASK)
+ {
+ retVal = 1;
+ }
+
+ return retVal;
+
+}
+
+/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register
+ * @param 1 Set iRESET_OUT bit; 0 - Clear the bit
+ */
+void p_pcr_iReset_Out(uint8_t set_clr_flag)
+{
+ __IO uint32_t *pPCR_Reg;
+
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
+
+ *pPCR_Reg = (set_clr_flag & 0x1);
+}
+
+
+/* end pcr_perphl.c */
+/** @}
+ */
/*******************************************************************************\r
* SMSC version control information (Perforce):\r
*\r
- * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/platform.h $\r
+ * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_PLIB_CLIB/release5/Source/hw_blks/common/include/platform.h $\r
* REVISION: $Revision: #1 $\r
- * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
- * AUTHOR: $Author: akrishnan $\r
+ * DATETIME: $DateTime: 2016/04/08 10:18:28 $\r
+ * AUTHOR: $Author: pramans $\r
*\r
* Revision history (latest first):\r
* #xx\r
#ifndef _PLATFORM_H_\r
#define _PLATFORM_H_\r
#include <stdint.h>\r
+\r
+/* Enable any one of the below flag which enables either Aggregated or Disaggregated Interrupts */\r
+#define DISAGGREGATED_INPT_DEFINED 1\r
+//#define AGGREGATED_INPT_DEFINED 1\r
+\r
+\r
/* Platform Configuration PreProcessor Conditions */\r
#define TOOLKEIL 1\r
#define TOOLPC 2\r
\r
typedef void VOID;\r
\r
+typedef volatile unsigned char VUINT8;\r
+typedef volatile unsigned short int VUINT16;\r
+typedef volatile unsigned long int VUINT32;\r
+\r
/* union types */\r
typedef union _BITS_8\r
{\r
#define FUNC_NEVER_RETURNS\r
#define BEGIN_SMALL_DATA_BLOCK(x)\r
#define END_SMALL_DATA_BLOCK()\r
-UINT32 soft_norm(UINT32 val);\r
+uint32_t soft_norm(uint32_t val);\r
#define NORM(x) soft_norm(x)\r
//\r
#define USE_FUNC_REPLACEMENT 0\r
#define FUNC_NEVER_RETURNS\r
#define BEGIN_SMALL_DATA_BLOCK(x)\r
#define END_SMALL_DATA_BLOCK()\r
-UINT32 soft_norm(UINT32 val);\r
+uint32_t soft_norm(uint32_t val);\r
#define NORM(x) soft_norm(x)\r
//\r
#define USE_FUNC_REPLACEMENT 0\r
#else\r
/* for ARM MDK */\r
#define FUNC_NEVER_RETURNS\r
-UINT32 soft_norm(UINT32 val);\r
+uint32_t soft_norm(uint32_t val);\r
#define NORM(x) soft_norm(x)\r
#endif\r
#endif\r
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