2 ******************************************************************************
\r
3 * @file stm32h745xx.h
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4 * @author MCD Application Team
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5 * @brief CMSIS STM32H745xx Device Peripheral Access Layer Header File.
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7 * This file contains:
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8 * - Data structures and the address mapping for all peripherals
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9 * - Peripheral's registers declarations and bits definition
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10 * - Macros to access peripheral's registers hardware
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12 ******************************************************************************
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15 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
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16 * All rights reserved.</center></h2>
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18 * This software component is licensed by ST under BSD 3-Clause license,
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19 * the "License"; You may not use this file except in compliance with the
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20 * License. You may obtain a copy of the License at:
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21 * opensource.org/licenses/BSD-3-Clause
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23 ******************************************************************************
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26 /** @addtogroup CMSIS_Device
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30 /** @addtogroup stm32h745xx
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34 #ifndef STM32H745xx_H
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35 #define STM32H745xx_H
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39 #endif /* __cplusplus */
\r
41 /** @addtogroup Peripheral_interrupt_number_definition
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46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
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47 * in @ref Library_configuration_section
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51 /****** Cortex-M Processor Exceptions Numbers *****************************************************************/
\r
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
\r
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
\r
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
\r
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
\r
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
\r
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
\r
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
\r
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
\r
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
\r
61 /****** STM32 specific Interrupt Numbers **********************************************************************/
\r
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
\r
63 PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
\r
64 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
\r
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
\r
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
\r
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
\r
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
\r
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
\r
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
\r
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
\r
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
\r
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
\r
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
\r
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
\r
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
\r
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
\r
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
\r
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
\r
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
\r
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
\r
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
\r
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
\r
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
\r
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
\r
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
\r
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
\r
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
\r
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
\r
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
\r
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
\r
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
\r
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
\r
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
\r
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
\r
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
\r
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
\r
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
\r
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
\r
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
\r
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
\r
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
\r
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
\r
104 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
\r
105 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
\r
106 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
\r
107 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
\r
108 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
\r
109 FMC_IRQn = 48, /*!< FMC global Interrupt */
\r
110 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
\r
111 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
\r
112 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
\r
113 UART4_IRQn = 52, /*!< UART4 global Interrupt */
\r
114 UART5_IRQn = 53, /*!< UART5 global Interrupt */
\r
115 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
\r
116 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
\r
117 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
\r
118 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
\r
119 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
\r
120 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
\r
121 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
\r
122 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
\r
123 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
\r
124 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
\r
125 CM7_SEV_IRQn = 64, /*!< CM7 Send event interrupt for CM4 */
\r
126 CM4_SEV_IRQn = 65, /*!< CM4 Send event interrupt for CM7 */
\r
127 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
\r
128 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
\r
129 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
\r
130 USART6_IRQn = 71, /*!< USART6 global interrupt */
\r
131 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
\r
132 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
\r
133 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
\r
134 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
\r
135 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
\r
136 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
\r
137 DCMI_IRQn = 78, /*!< DCMI global interrupt */
\r
138 RNG_IRQn = 80, /*!< RNG global interrupt */
\r
139 FPU_IRQn = 81, /*!< FPU global interrupt */
\r
140 UART7_IRQn = 82, /*!< UART7 global interrupt */
\r
141 UART8_IRQn = 83, /*!< UART8 global interrupt */
\r
142 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
\r
143 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
\r
144 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
\r
145 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
\r
146 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
\r
147 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
\r
148 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
\r
149 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
\r
150 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
\r
151 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
\r
152 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
\r
153 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
\r
154 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
\r
155 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
\r
156 OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
\r
157 OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
\r
158 OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
\r
159 OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
\r
160 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
\r
161 HRTIM1_Master_IRQn = 103, /*!< HRTIM Master Timer global Interrupts */
\r
162 HRTIM1_TIMA_IRQn = 104, /*!< HRTIM Timer A global Interrupt */
\r
163 HRTIM1_TIMB_IRQn = 105, /*!< HRTIM Timer B global Interrupt */
\r
164 HRTIM1_TIMC_IRQn = 106, /*!< HRTIM Timer C global Interrupt */
\r
165 HRTIM1_TIMD_IRQn = 107, /*!< HRTIM Timer D global Interrupt */
\r
166 HRTIM1_TIME_IRQn = 108, /*!< HRTIM Timer E global Interrupt */
\r
167 HRTIM1_FLT_IRQn = 109, /*!< HRTIM Fault global Interrupt */
\r
168 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
\r
169 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
\r
170 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
\r
171 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
\r
172 SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
\r
173 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
\r
174 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
\r
175 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
\r
176 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
\r
177 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
\r
178 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
\r
179 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
\r
180 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
\r
181 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
\r
182 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
\r
183 HSEM2_IRQn = 126, /*!< HSEM2 global Interrupt */
\r
184 ADC3_IRQn = 127, /*!< ADC3 global Interrupt */
\r
185 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
\r
186 BDMA_Channel0_IRQn = 129, /*!< BDMA Channel 0 global Interrupt */
\r
187 BDMA_Channel1_IRQn = 130, /*!< BDMA Channel 1 global Interrupt */
\r
188 BDMA_Channel2_IRQn = 131, /*!< BDMA Channel 2 global Interrupt */
\r
189 BDMA_Channel3_IRQn = 132, /*!< BDMA Channel 3 global Interrupt */
\r
190 BDMA_Channel4_IRQn = 133, /*!< BDMA Channel 4 global Interrupt */
\r
191 BDMA_Channel5_IRQn = 134, /*!< BDMA Channel 5 global Interrupt */
\r
192 BDMA_Channel6_IRQn = 135, /*!< BDMA Channel 6 global Interrupt */
\r
193 BDMA_Channel7_IRQn = 136, /*!< BDMA Channel 7 global Interrupt */
\r
194 COMP_IRQn = 137 , /*!< COMP global Interrupt */
\r
195 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
\r
196 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
\r
197 LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
\r
198 LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
\r
199 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
\r
200 WWDG_RST_IRQn = 143, /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
\r
201 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
\r
202 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
\r
203 SAI4_IRQn = 146, /*!< SAI4 global interrupt */
\r
204 HOLD_CORE_IRQn = 148, /*!< Hold core interrupt */
\r
205 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
\r
212 /** @addtogroup Configuration_section_for_CMSIS
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215 #define DUAL_CORE /*!< Dual core line feature */
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217 #define SMPS /*!< Switched mode power supply feature */
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222 * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
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225 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
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226 #define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
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227 #define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
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228 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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229 #define __FPU_PRESENT 1 /*!< FPU present */
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231 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
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232 #else /* CORE_CM7 */
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234 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
\r
235 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
\r
236 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
\r
237 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
\r
238 #define __FPU_PRESENT 1 /*!< FPU present */
\r
239 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
\r
240 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
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241 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
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242 #else /* UNKNOWN_CORE */
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243 #error Please #define CORE_CM4 or CORE_CM7
\r
244 #endif /* CORE_CM7 */
\r
245 #endif /* CORE_CM4 */
\r
255 #include "system_stm32h7xx.h"
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256 #include <stdint.h>
\r
258 /** @addtogroup Peripheral_registers_structures
\r
263 * @brief Analog to Digital Converter
\r
268 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
\r
269 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
\r
270 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
\r
271 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
\r
272 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
\r
273 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
\r
274 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
\r
275 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
\r
276 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
\r
277 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
\r
278 uint32_t RESERVED1; /*!< Reserved, 0x028 */
\r
279 uint32_t RESERVED2; /*!< Reserved, 0x02C */
\r
280 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
\r
281 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
\r
282 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
\r
283 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
\r
284 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
\r
285 uint32_t RESERVED3; /*!< Reserved, 0x044 */
\r
286 uint32_t RESERVED4; /*!< Reserved, 0x048 */
\r
287 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
\r
288 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
\r
289 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
\r
290 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
\r
291 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
\r
292 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
\r
293 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
\r
294 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
\r
295 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
\r
296 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
\r
297 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
\r
298 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
\r
299 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
\r
300 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
\r
301 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
\r
302 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
\r
303 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
\r
304 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
\r
305 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
\r
306 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
\r
307 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
\r
308 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
\r
309 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
\r
315 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
\r
316 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
\r
317 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
\r
318 __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
\r
319 __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
\r
321 } ADC_Common_TypeDef;
\r
329 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
\r
330 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
\r
335 * @brief FD Controller Area Network
\r
340 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
\r
341 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
\r
342 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
\r
343 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
\r
344 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
\r
345 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
\r
346 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
\r
347 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
\r
348 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
\r
349 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
\r
350 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
\r
351 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
\r
352 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
\r
353 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
\r
354 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
\r
355 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
\r
356 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
\r
357 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
\r
358 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
\r
359 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
\r
360 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
\r
361 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
\r
362 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
\r
363 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
\r
364 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
\r
365 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
\r
366 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
\r
367 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
\r
368 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
\r
369 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
\r
370 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
\r
371 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
\r
372 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
\r
373 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
\r
374 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
\r
375 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
\r
376 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
\r
377 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
\r
378 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
\r
379 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
\r
380 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
\r
381 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
\r
382 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
\r
383 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
\r
384 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
\r
385 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
\r
386 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
\r
387 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
\r
388 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
\r
389 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
\r
390 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
\r
391 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
\r
392 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
\r
393 } FDCAN_GlobalTypeDef;
\r
396 * @brief TTFD Controller Area Network
\r
401 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
\r
402 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
\r
403 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
\r
404 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
\r
405 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
\r
406 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
\r
407 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
\r
408 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
\r
409 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
\r
410 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
\r
411 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
\r
412 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
\r
413 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
\r
414 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
\r
415 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
\r
416 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
\r
417 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
\r
418 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
\r
419 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
\r
423 * @brief FD Controller Area Network
\r
428 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
\r
429 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
\r
430 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
\r
431 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
\r
432 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
\r
433 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
\r
434 } FDCAN_ClockCalibrationUnit_TypeDef;
\r
438 * @brief Consumer Electronics Control
\r
443 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
\r
444 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
\r
445 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
\r
446 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
\r
447 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
\r
448 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
\r
452 * @brief CRC calculation unit
\r
457 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
\r
458 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
\r
459 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
\r
460 uint32_t RESERVED2; /*!< Reserved, 0x0C */
\r
461 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
\r
462 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
\r
467 * @brief Clock Recovery System
\r
471 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
\r
472 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
\r
473 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
\r
474 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
\r
479 * @brief Digital to Analog Converter
\r
484 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
\r
485 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
\r
486 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
\r
487 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
\r
488 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
\r
489 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
\r
490 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
\r
491 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
\r
492 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
\r
493 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
\r
494 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
\r
495 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
\r
496 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
\r
497 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
\r
498 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
\r
499 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
\r
500 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
\r
501 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
\r
502 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
\r
503 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
\r
507 * @brief DFSDM module registers
\r
511 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
\r
512 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
\r
513 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
\r
514 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
\r
515 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
\r
516 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
\r
517 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
\r
518 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
\r
519 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
\r
520 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
\r
521 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
\r
522 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
\r
523 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
\r
524 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
\r
525 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
\r
526 } DFSDM_Filter_TypeDef;
\r
529 * @brief DFSDM channel configuration registers
\r
533 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
\r
534 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
\r
535 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
\r
536 short circuit detector register, Address offset: 0x08 */
\r
537 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
\r
538 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
\r
539 } DFSDM_Channel_TypeDef;
\r
546 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
\r
547 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
\r
548 __IO uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
\r
549 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
\r
550 __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register, Address offset: 0x38 */
\r
551 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
\r
552 __IO uint32_t APB1LFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x40 */
\r
553 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
\r
554 __IO uint32_t APB1HFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x48 */
\r
555 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
\r
556 __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register, Address offset: 0x50 */
\r
557 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
\r
558 __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register, Address offset: 0x58 */
\r
567 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
\r
568 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
\r
569 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
\r
570 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
\r
571 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
\r
572 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
\r
573 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
\r
574 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
\r
575 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
\r
576 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
\r
577 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
\r
581 * @brief DMA Controller
\r
586 __IO uint32_t CR; /*!< DMA stream x configuration register */
\r
587 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
\r
588 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
\r
589 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
\r
590 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
\r
591 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
\r
592 } DMA_Stream_TypeDef;
\r
596 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
\r
597 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
\r
598 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
\r
599 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
\r
604 __IO uint32_t CCR; /*!< DMA channel x configuration register */
\r
605 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
\r
606 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
\r
607 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
\r
608 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
\r
609 } BDMA_Channel_TypeDef;
\r
613 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
\r
614 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
\r
619 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
\r
620 }DMAMUX_Channel_TypeDef;
\r
624 __IO uint32_t CSR; /*!< DMA Channel Status Register */
\r
625 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
\r
626 }DMAMUX_ChannelStatus_TypeDef;
\r
630 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
\r
631 }DMAMUX_RequestGen_TypeDef;
\r
635 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
\r
636 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
\r
637 }DMAMUX_RequestGenStatus_TypeDef;
\r
640 * @brief MDMA Controller
\r
644 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
\r
649 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
\r
650 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
\r
651 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
\r
652 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
\r
653 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
\r
654 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
\r
655 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
\r
656 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
\r
657 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
\r
658 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
\r
659 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
\r
660 uint32_t RESERVED0; /*!< Reserved, 0x68 */
\r
661 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
\r
662 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
\r
663 }MDMA_Channel_TypeDef;
\r
666 * @brief DMA2D Controller
\r
671 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
\r
672 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
\r
673 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
\r
674 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
\r
675 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
\r
676 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
\r
677 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
\r
678 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
\r
679 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
\r
680 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
\r
681 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
\r
682 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
\r
683 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
\r
684 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
\r
685 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
\r
686 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
\r
687 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
\r
688 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
\r
689 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
\r
690 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
\r
691 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
\r
692 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
\r
693 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
\r
698 * @brief Ethernet MAC
\r
702 __IO uint32_t MACCR;
\r
703 __IO uint32_t MACECR;
\r
704 __IO uint32_t MACPFR;
\r
705 __IO uint32_t MACWTR;
\r
706 __IO uint32_t MACHT0R;
\r
707 __IO uint32_t MACHT1R;
\r
708 uint32_t RESERVED1[14];
\r
709 __IO uint32_t MACVTR;
\r
710 uint32_t RESERVED2;
\r
711 __IO uint32_t MACVHTR;
\r
712 uint32_t RESERVED3;
\r
713 __IO uint32_t MACVIR;
\r
714 __IO uint32_t MACIVIR;
\r
715 uint32_t RESERVED4[2];
\r
716 __IO uint32_t MACTFCR;
\r
717 uint32_t RESERVED5[7];
\r
718 __IO uint32_t MACRFCR;
\r
719 uint32_t RESERVED6[7];
\r
720 __IO uint32_t MACISR;
\r
721 __IO uint32_t MACIER;
\r
722 __IO uint32_t MACRXTXSR;
\r
723 uint32_t RESERVED7;
\r
724 __IO uint32_t MACPCSR;
\r
725 __IO uint32_t MACRWKPFR;
\r
726 uint32_t RESERVED8[2];
\r
727 __IO uint32_t MACLCSR;
\r
728 __IO uint32_t MACLTCR;
\r
729 __IO uint32_t MACLETR;
\r
730 __IO uint32_t MAC1USTCR;
\r
731 uint32_t RESERVED9[12];
\r
732 __IO uint32_t MACVR;
\r
733 __IO uint32_t MACDR;
\r
734 uint32_t RESERVED10;
\r
735 __IO uint32_t MACHWF0R;
\r
736 __IO uint32_t MACHWF1R;
\r
737 __IO uint32_t MACHWF2R;
\r
738 uint32_t RESERVED11[54];
\r
739 __IO uint32_t MACMDIOAR;
\r
740 __IO uint32_t MACMDIODR;
\r
741 uint32_t RESERVED12[2];
\r
742 __IO uint32_t MACARPAR;
\r
743 uint32_t RESERVED13[59];
\r
744 __IO uint32_t MACA0HR;
\r
745 __IO uint32_t MACA0LR;
\r
746 __IO uint32_t MACA1HR;
\r
747 __IO uint32_t MACA1LR;
\r
748 __IO uint32_t MACA2HR;
\r
749 __IO uint32_t MACA2LR;
\r
750 __IO uint32_t MACA3HR;
\r
751 __IO uint32_t MACA3LR;
\r
752 uint32_t RESERVED14[248];
\r
753 __IO uint32_t MMCCR;
\r
754 __IO uint32_t MMCRIR;
\r
755 __IO uint32_t MMCTIR;
\r
756 __IO uint32_t MMCRIMR;
\r
757 __IO uint32_t MMCTIMR;
\r
758 uint32_t RESERVED15[14];
\r
759 __IO uint32_t MMCTSCGPR;
\r
760 __IO uint32_t MMCTMCGPR;
\r
761 int32_t RESERVED16[5];
\r
762 __IO uint32_t MMCTPCGR;
\r
763 uint32_t RESERVED17[10];
\r
764 __IO uint32_t MMCRCRCEPR;
\r
765 __IO uint32_t MMCRAEPR;
\r
766 uint32_t RESERVED18[10];
\r
767 __IO uint32_t MMCRUPGR;
\r
768 uint32_t RESERVED19[9];
\r
769 __IO uint32_t MMCTLPIMSTR;
\r
770 __IO uint32_t MMCTLPITCR;
\r
771 __IO uint32_t MMCRLPIMSTR;
\r
772 __IO uint32_t MMCRLPITCR;
\r
773 uint32_t RESERVED20[65];
\r
774 __IO uint32_t MACL3L4C0R;
\r
775 __IO uint32_t MACL4A0R;
\r
776 uint32_t RESERVED21[2];
\r
777 __IO uint32_t MACL3A0R0R;
\r
778 __IO uint32_t MACL3A1R0R;
\r
779 __IO uint32_t MACL3A2R0R;
\r
780 __IO uint32_t MACL3A3R0R;
\r
781 uint32_t RESERVED22[4];
\r
782 __IO uint32_t MACL3L4C1R;
\r
783 __IO uint32_t MACL4A1R;
\r
784 uint32_t RESERVED23[2];
\r
785 __IO uint32_t MACL3A0R1R;
\r
786 __IO uint32_t MACL3A1R1R;
\r
787 __IO uint32_t MACL3A2R1R;
\r
788 __IO uint32_t MACL3A3R1R;
\r
789 uint32_t RESERVED24[108];
\r
790 __IO uint32_t MACTSCR;
\r
791 __IO uint32_t MACSSIR;
\r
792 __IO uint32_t MACSTSR;
\r
793 __IO uint32_t MACSTNR;
\r
794 __IO uint32_t MACSTSUR;
\r
795 __IO uint32_t MACSTNUR;
\r
796 __IO uint32_t MACTSAR;
\r
797 uint32_t RESERVED25;
\r
798 __IO uint32_t MACTSSR;
\r
799 uint32_t RESERVED26[3];
\r
800 __IO uint32_t MACTTSSNR;
\r
801 __IO uint32_t MACTTSSSR;
\r
802 uint32_t RESERVED27[2];
\r
803 __IO uint32_t MACACR;
\r
804 uint32_t RESERVED28;
\r
805 __IO uint32_t MACATSNR;
\r
806 __IO uint32_t MACATSSR;
\r
807 __IO uint32_t MACTSIACR;
\r
808 __IO uint32_t MACTSEACR;
\r
809 __IO uint32_t MACTSICNR;
\r
810 __IO uint32_t MACTSECNR;
\r
811 uint32_t RESERVED29[4];
\r
812 __IO uint32_t MACPPSCR;
\r
813 uint32_t RESERVED30[3];
\r
814 __IO uint32_t MACPPSTTSR;
\r
815 __IO uint32_t MACPPSTTNR;
\r
816 __IO uint32_t MACPPSIR;
\r
817 __IO uint32_t MACPPSWR;
\r
818 uint32_t RESERVED31[12];
\r
819 __IO uint32_t MACPOCR;
\r
820 __IO uint32_t MACSPI0R;
\r
821 __IO uint32_t MACSPI1R;
\r
822 __IO uint32_t MACSPI2R;
\r
823 __IO uint32_t MACLMIR;
\r
824 uint32_t RESERVED32[11];
\r
825 __IO uint32_t MTLOMR;
\r
826 uint32_t RESERVED33[7];
\r
827 __IO uint32_t MTLISR;
\r
828 uint32_t RESERVED34[55];
\r
829 __IO uint32_t MTLTQOMR;
\r
830 __IO uint32_t MTLTQUR;
\r
831 __IO uint32_t MTLTQDR;
\r
832 uint32_t RESERVED35[8];
\r
833 __IO uint32_t MTLQICSR;
\r
834 __IO uint32_t MTLRQOMR;
\r
835 __IO uint32_t MTLRQMPOCR;
\r
836 __IO uint32_t MTLRQDR;
\r
837 uint32_t RESERVED36[177];
\r
838 __IO uint32_t DMAMR;
\r
839 __IO uint32_t DMASBMR;
\r
840 __IO uint32_t DMAISR;
\r
841 __IO uint32_t DMADSR;
\r
842 uint32_t RESERVED37[60];
\r
843 __IO uint32_t DMACCR;
\r
844 __IO uint32_t DMACTCR;
\r
845 __IO uint32_t DMACRCR;
\r
846 uint32_t RESERVED38[2];
\r
847 __IO uint32_t DMACTDLAR;
\r
848 uint32_t RESERVED39;
\r
849 __IO uint32_t DMACRDLAR;
\r
850 __IO uint32_t DMACTDTPR;
\r
851 uint32_t RESERVED40;
\r
852 __IO uint32_t DMACRDTPR;
\r
853 __IO uint32_t DMACTDRLR;
\r
854 __IO uint32_t DMACRDRLR;
\r
855 __IO uint32_t DMACIER;
\r
856 __IO uint32_t DMACRIWTR;
\r
857 __IO uint32_t DMACSFCSR;
\r
858 uint32_t RESERVED41;
\r
859 __IO uint32_t DMACCATDR;
\r
860 uint32_t RESERVED42;
\r
861 __IO uint32_t DMACCARDR;
\r
862 uint32_t RESERVED43;
\r
863 __IO uint32_t DMACCATBR;
\r
864 uint32_t RESERVED44;
\r
865 __IO uint32_t DMACCARBR;
\r
866 __IO uint32_t DMACSR;
\r
867 uint32_t RESERVED45[2];
\r
868 __IO uint32_t DMACMFCR;
\r
871 * @brief External Interrupt/Event Controller
\r
876 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
\r
877 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
\r
878 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
\r
879 __IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
\r
880 __IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
\r
881 __IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
\r
882 uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
\r
883 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
\r
884 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
\r
885 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
\r
886 __IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
\r
887 __IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
\r
888 __IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
\r
889 uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
\r
890 __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
\r
891 __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
\r
892 __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
\r
893 __IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
\r
894 __IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
\r
895 __IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
\r
896 uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
\r
897 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
\r
898 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
\r
899 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
\r
900 uint32_t RESERVED4; /*!< Reserved, 0x8C */
\r
901 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
\r
902 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
\r
903 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
\r
904 uint32_t RESERVED5; /*!< Reserved, 0x9C */
\r
905 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
\r
906 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
\r
907 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
\r
908 uint32_t RESERVED6[5]; /*!< Reserved, 0xAC to 0xBC */
\r
909 __IO uint32_t C2IMR1; /*!< EXTI Interrupt mask register, Address offset: 0xC0 */
\r
910 __IO uint32_t C2EMR1; /*!< EXTI Event mask register, Address offset: 0xC4 */
\r
911 __IO uint32_t C2PR1; /*!< EXTI Pending register, Address offset: 0xC8 */
\r
912 uint32_t RESERVED7; /*!< Reserved, 0xCC */
\r
913 __IO uint32_t C2IMR2; /*!< EXTI Interrupt mask register, Address offset: 0xD0 */
\r
914 __IO uint32_t C2EMR2; /*!< EXTI Event mask register, Address offset: 0xD4 */
\r
915 __IO uint32_t C2PR2; /*!< EXTI Pending register, Address offset: 0xD8 */
\r
916 uint32_t RESERVED8; /*!< Reserved, 0xDC */
\r
917 __IO uint32_t C2IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xE0 */
\r
918 __IO uint32_t C2EMR3; /*!< EXTI Event mask register, Address offset: 0xE4 */
\r
919 __IO uint32_t C2PR3; /*!< EXTI Pending register, Address offset: 0xE8 */
\r
925 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
\r
926 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
\r
927 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
\r
928 uint32_t RESERVED1; /*!< Reserved, 0x0C */
\r
929 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
\r
930 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
\r
931 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
\r
932 uint32_t RESERVED2; /*!< Reserved, 0x1C */
\r
933 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
\r
934 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
\r
935 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
\r
936 }EXTI_Core_TypeDef;
\r
940 * @brief FLASH Registers
\r
945 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
\r
946 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
\r
947 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
\r
948 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
\r
949 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
\r
950 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
\r
951 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
\r
952 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
\r
953 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
\r
954 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
\r
955 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
\r
956 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
\r
957 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
\r
958 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
\r
959 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
\r
960 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
\r
961 __IO uint32_t BOOT7_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
\r
962 __IO uint32_t BOOT7_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
\r
963 __IO uint32_t BOOT4_CUR; /*!< Flash Current Boot Address for M4 Core Register, Address offset: 0x48 */
\r
964 __IO uint32_t BOOT4_PRG; /*!< Flash Boot Address to Program for M4 Core Register, Address offset: 0x4C */
\r
965 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
\r
966 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
\r
967 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
\r
968 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
\r
969 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
\r
970 uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
\r
971 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
\r
972 uint32_t RESERVED2; /*!< Reserved, 0x108 */
\r
973 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
\r
974 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
\r
975 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
\r
976 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
\r
977 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
\r
978 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
\r
979 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
\r
980 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
\r
981 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
\r
982 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
\r
983 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
\r
984 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
\r
985 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
\r
986 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
\r
987 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
\r
988 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
\r
992 * @brief Flexible Memory Controller
\r
997 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
\r
998 } FMC_Bank1_TypeDef;
\r
1001 * @brief Flexible Memory Controller Bank1E
\r
1006 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
\r
1007 } FMC_Bank1E_TypeDef;
\r
1010 * @brief Flexible Memory Controller Bank2
\r
1015 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
\r
1016 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
\r
1017 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
\r
1018 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
\r
1019 uint32_t RESERVED0; /*!< Reserved, 0x70 */
\r
1020 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
\r
1021 } FMC_Bank2_TypeDef;
\r
1024 * @brief Flexible Memory Controller Bank3
\r
1029 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
\r
1030 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
\r
1031 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
\r
1032 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
\r
1033 uint32_t RESERVED; /*!< Reserved, 0x90 */
\r
1034 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
\r
1035 } FMC_Bank3_TypeDef;
\r
1038 * @brief Flexible Memory Controller Bank5 and 6
\r
1044 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
\r
1045 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
\r
1046 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
\r
1047 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
\r
1048 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
\r
1049 } FMC_Bank5_6_TypeDef;
\r
1052 * @brief General Purpose I/O
\r
1057 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
\r
1058 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
\r
1059 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
\r
1060 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
\r
1061 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
\r
1062 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
\r
1063 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
\r
1064 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
\r
1065 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
\r
1069 * @brief Operational Amplifier (OPAMP)
\r
1074 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
\r
1075 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
\r
1076 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
\r
1080 * @brief System configuration controller
\r
1085 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
\r
1086 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
\r
1087 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
\r
1088 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
\r
1089 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
\r
1090 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
\r
1091 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
\r
1092 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
\r
1093 __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */
\r
1094 uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */
\r
1095 __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
\r
1096 uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
\r
1097 __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
\r
1098 __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
\r
1099 __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
\r
1100 __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
\r
1101 __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
\r
1102 __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
\r
1103 __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
\r
1104 __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
\r
1105 __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
\r
1106 __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
\r
1107 __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
\r
1108 __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
\r
1109 __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
\r
1110 __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
\r
1111 __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
\r
1112 __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
\r
1113 __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
\r
1114 __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
\r
1119 * @brief Inter-integrated Circuit Interface
\r
1124 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
\r
1125 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
\r
1126 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
\r
1127 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
\r
1128 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
\r
1129 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
\r
1130 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
\r
1131 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
\r
1132 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
\r
1133 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
\r
1134 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
\r
1138 * @brief Independent WATCHDOG
\r
1143 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
\r
1144 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
\r
1145 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
\r
1146 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
\r
1147 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
\r
1152 * @brief JPEG Codec
\r
1156 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
\r
1157 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
\r
1158 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
\r
1159 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
\r
1160 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
\r
1161 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
\r
1162 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
\r
1163 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
\r
1164 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
\r
1165 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
\r
1166 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
\r
1167 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
\r
1168 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
\r
1169 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
\r
1170 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
\r
1171 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
\r
1172 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
\r
1173 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
\r
1174 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
\r
1175 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
\r
1176 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
\r
1177 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
\r
1178 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
\r
1179 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
\r
1180 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
\r
1181 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
\r
1182 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
\r
1183 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
\r
1184 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
\r
1189 * @brief LCD-TFT Display Controller
\r
1194 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
\r
1195 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
\r
1196 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
\r
1197 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
\r
1198 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
\r
1199 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
\r
1200 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
\r
1201 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
\r
1202 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
\r
1203 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
\r
1204 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
\r
1205 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
\r
1206 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
\r
1207 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
\r
1208 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
\r
1209 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
\r
1210 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
\r
1214 * @brief LCD-TFT Display layer x Controller
\r
1219 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
\r
1220 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
\r
1221 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
\r
1222 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
\r
1223 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
\r
1224 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
\r
1225 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
\r
1226 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
\r
1227 uint32_t RESERVED0[2]; /*!< Reserved */
\r
1228 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
\r
1229 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
\r
1230 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
\r
1231 uint32_t RESERVED1[3]; /*!< Reserved */
\r
1232 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
\r
1234 } LTDC_Layer_TypeDef;
\r
1237 * @brief Power Control
\r
1242 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
\r
1243 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
\r
1244 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
\r
1245 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
\r
1246 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
\r
1247 __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */
\r
1248 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
\r
1249 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
\r
1250 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
\r
1251 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
\r
1252 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
\r
1256 * @brief Reset and Clock Control
\r
1261 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
\r
1262 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
\r
1263 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
\r
1264 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
\r
1265 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
\r
1266 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
\r
1267 __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
\r
1268 __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
\r
1269 __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
\r
1270 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
\r
1271 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
\r
1272 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
\r
1273 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
\r
1274 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
\r
1275 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
\r
1276 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
\r
1277 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
\r
1278 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
\r
1279 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
\r
1280 __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
\r
1281 __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
\r
1282 __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
\r
1283 __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
\r
1284 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
\r
1285 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
\r
1286 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
\r
1287 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
\r
1288 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
\r
1289 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
\r
1290 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
\r
1291 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
\r
1292 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
\r
1293 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
\r
1294 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
\r
1295 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
\r
1296 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
\r
1297 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
\r
1298 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
\r
1299 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
\r
1300 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
\r
1301 __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
\r
1302 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
\r
1303 __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
\r
1304 uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
\r
1305 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
\r
1306 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
\r
1307 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
\r
1308 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
\r
1309 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
\r
1310 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
\r
1311 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
\r
1312 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
\r
1313 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
\r
1314 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
\r
1315 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
\r
1316 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
\r
1317 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
\r
1318 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
\r
1319 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
\r
1320 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
\r
1321 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
\r
1322 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
\r
1323 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
\r
1324 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
\r
1325 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
\r
1331 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0x00 */
\r
1332 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x04 */
\r
1333 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x08 */
\r
1334 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x0C */
\r
1335 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x10 */
\r
1336 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x14 */
\r
1337 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0x18 */
\r
1338 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0x1C */
\r
1339 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x20 */
\r
1340 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0x24 */
\r
1341 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x28 */
\r
1342 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0x3C */
\r
1343 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x40 */
\r
1344 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x44 */
\r
1345 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x48 */
\r
1346 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x4C */
\r
1347 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50 */
\r
1348 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54 */
\r
1349 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x58 */
\r
1350 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x5C */
\r
1351 uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C Address offset: 0x60 */
\r
1353 } RCC_Core_TypeDef;
\r
1356 * @brief Real-Time Clock
\r
1360 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
\r
1361 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
\r
1362 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
\r
1363 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
\r
1364 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
\r
1365 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
\r
1366 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
\r
1367 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
\r
1368 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
\r
1369 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
\r
1370 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
\r
1371 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
\r
1372 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
\r
1373 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
\r
1374 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
\r
1375 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
\r
1376 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
\r
1377 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
\r
1378 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
\r
1379 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
\r
1380 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
\r
1381 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
\r
1382 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
\r
1383 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
\r
1384 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
\r
1385 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
\r
1386 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
\r
1387 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
\r
1388 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
\r
1389 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
\r
1390 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
\r
1391 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
\r
1392 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
\r
1393 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
\r
1394 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
\r
1395 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
\r
1396 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
\r
1397 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
\r
1398 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
\r
1399 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
\r
1400 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
\r
1401 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
\r
1402 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
\r
1403 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
\r
1404 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
\r
1405 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
\r
1406 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
\r
1407 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
\r
1408 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
\r
1409 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
\r
1410 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
\r
1411 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
\r
1415 * @brief Serial Audio Interface
\r
1420 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
\r
1421 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
\r
1422 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
\r
1423 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
\r
1428 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
\r
1429 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
\r
1430 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
\r
1431 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
\r
1432 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
\r
1433 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
\r
1434 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
\r
1435 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
\r
1436 } SAI_Block_TypeDef;
\r
1439 * @brief SPDIF-RX Interface
\r
1444 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
\r
1445 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
\r
1446 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
\r
1447 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
\r
1448 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
\r
1449 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
\r
1450 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
\r
1451 uint32_t RESERVED2; /*!< Reserved, 0x1A */
\r
1452 } SPDIFRX_TypeDef;
\r
1456 * @brief Secure digital input/output Interface
\r
1461 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
\r
1462 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
\r
1463 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
\r
1464 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
\r
1465 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
\r
1466 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
\r
1467 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
\r
1468 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
\r
1469 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
\r
1470 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
\r
1471 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
\r
1472 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
\r
1473 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
\r
1474 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
\r
1475 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
\r
1476 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
\r
1477 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
\r
1478 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
\r
1479 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
\r
1480 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
\r
1481 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
\r
1482 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
\r
1483 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
\r
1484 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
\r
1485 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
\r
1486 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
\r
1491 * @brief Delay Block DLYB
\r
1496 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
\r
1497 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
\r
1501 * @brief HW Semaphore HSEM
\r
1506 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
\r
1507 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
\r
1508 __IO uint32_t C1IER; /*!< HSEM Interrupt 0 enable register , Address offset: 100h */
\r
1509 __IO uint32_t C1ICR; /*!< HSEM Interrupt 0 clear register , Address offset: 104h */
\r
1510 __IO uint32_t C1ISR; /*!< HSEM Interrupt 0 Status register , Address offset: 108h */
\r
1511 __IO uint32_t C1MISR; /*!< HSEM Interrupt 0 Masked Status register , Address offset: 10Ch */
\r
1512 __IO uint32_t C2IER; /*!< HSEM Interrupt 1 enable register , Address offset: 110h */
\r
1513 __IO uint32_t C2ICR; /*!< HSEM Interrupt 1 clear register , Address offset: 114h */
\r
1514 __IO uint32_t C2ISR; /*!< HSEM Interrupt 1 Status register , Address offset: 118h */
\r
1515 __IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch */
\r
1516 uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
\r
1517 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
\r
1518 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
\r
1524 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
\r
1525 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
\r
1526 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
\r
1527 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
\r
1528 } HSEM_Common_TypeDef;
\r
1531 * @brief Serial Peripheral Interface
\r
1536 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
\r
1537 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
\r
1538 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
\r
1539 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
\r
1540 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
\r
1541 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
\r
1542 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
\r
1543 uint32_t RESERVED0; /*!< Reserved, 0x1C */
\r
1544 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
\r
1545 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
\r
1546 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
\r
1547 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
\r
1548 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
\r
1549 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
\r
1550 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
\r
1551 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
\r
1552 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
\r
1556 * @brief QUAD Serial Peripheral Interface
\r
1561 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
\r
1562 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
\r
1563 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
\r
1564 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
\r
1565 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
\r
1566 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
\r
1567 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
\r
1568 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
\r
1569 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
\r
1570 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
\r
1571 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
\r
1572 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
\r
1573 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
\r
1574 } QUADSPI_TypeDef;
\r
1582 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
\r
1583 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
\r
1584 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
\r
1585 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
\r
1586 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
\r
1587 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
\r
1588 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
\r
1589 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
\r
1590 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
\r
1591 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
\r
1592 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
\r
1593 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
\r
1594 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
\r
1595 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
\r
1596 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
\r
1597 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
\r
1598 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
\r
1599 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
\r
1600 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
\r
1601 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
\r
1602 uint32_t RESERVED1; /*!< Reserved, 0x50 */
\r
1603 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
\r
1604 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
\r
1605 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
\r
1606 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
\r
1607 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
\r
1608 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
\r
1612 * @brief LPTIMIMER
\r
1616 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
\r
1617 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
\r
1618 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
\r
1619 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
\r
1620 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
\r
1621 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
\r
1622 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
\r
1623 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
\r
1624 uint32_t RESERVED1; /*!< Reserved, 0x20 */
\r
1625 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
\r
1629 * @brief Comparator
\r
1633 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
\r
1634 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
\r
1635 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
\r
1636 } COMPOPT_TypeDef;
\r
1640 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
\r
1645 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
\r
1646 } COMP_Common_TypeDef;
\r
1648 * @brief Universal Synchronous Asynchronous Receiver Transmitter
\r
1653 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
\r
1654 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
\r
1655 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
\r
1656 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
\r
1657 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
\r
1658 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
\r
1659 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
\r
1660 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
\r
1661 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
\r
1662 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
\r
1663 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
\r
1664 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
\r
1668 * @brief Single Wire Protocol Master Interface SPWMI
\r
1672 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
\r
1673 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
\r
1674 uint32_t RESERVED1; /*!< Reserved, 0x08 */
\r
1675 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
\r
1676 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
\r
1677 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
\r
1678 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
\r
1679 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
\r
1680 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
\r
1681 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
\r
1685 * @brief Window WATCHDOG
\r
1690 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
\r
1691 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
\r
1692 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
\r
1697 * @brief RAM_ECC_Specific_Registers
\r
1701 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
\r
1702 __IO uint32_t SR; /*!< RAMECC monitor status register */
\r
1703 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
\r
1704 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
\r
1705 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
\r
1706 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
\r
1707 } RAMECC_MonitorTypeDef;
\r
1711 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
\r
1720 * @brief High resolution Timer (HRTIM)
\r
1722 /* HRTIM master registers definition */
\r
1725 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
\r
1726 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
\r
1727 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
\r
1728 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
\r
1729 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
\r
1730 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
\r
1731 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
\r
1732 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
\r
1733 uint32_t RESERVED0; /*!< Reserved, 0x20 */
\r
1734 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
\r
1735 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
\r
1736 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
\r
1737 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
\r
1738 }HRTIM_Master_TypeDef;
\r
1740 /* HRTIM Timer A to E registers definition */
\r
1743 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
\r
1744 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
\r
1745 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
\r
1746 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
\r
1747 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
\r
1748 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
\r
1749 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
\r
1750 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
\r
1751 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
\r
1752 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
\r
1753 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
\r
1754 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
\r
1755 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
\r
1756 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
\r
1757 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
\r
1758 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
\r
1759 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
\r
1760 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
\r
1761 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
\r
1762 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
\r
1763 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
\r
1764 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
\r
1765 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
\r
1766 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
\r
1767 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
\r
1768 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
\r
1769 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
\r
1770 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
\r
1771 }HRTIM_Timerx_TypeDef;
\r
1773 /* HRTIM common register definition */
\r
1776 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
\r
1777 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
\r
1778 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
\r
1779 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
\r
1780 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
\r
1781 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
\r
1782 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
\r
1783 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
\r
1784 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
\r
1785 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
\r
1786 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
\r
1787 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
\r
1788 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
\r
1789 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
\r
1790 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
\r
1791 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
\r
1792 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
\r
1793 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
\r
1794 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
\r
1795 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */
\r
1796 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
\r
1797 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
\r
1798 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
\r
1799 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
\r
1800 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
\r
1801 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
\r
1802 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
\r
1803 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
\r
1804 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
\r
1805 }HRTIM_Common_TypeDef;
\r
1807 /* HRTIM register definition */
\r
1809 HRTIM_Master_TypeDef sMasterRegs;
\r
1810 HRTIM_Timerx_TypeDef sTimerxRegs[5];
\r
1811 uint32_t RESERVED0[32];
\r
1812 HRTIM_Common_TypeDef sCommonRegs;
\r
1820 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
\r
1821 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
\r
1822 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
\r
1832 __IO uint32_t WRFR;
\r
1833 __IO uint32_t CWRFR;
\r
1834 __IO uint32_t RDFR;
\r
1835 __IO uint32_t CRDFR;
\r
1837 __IO uint32_t CLRFR;
\r
1838 uint32_t RESERVED[57];
\r
1839 __IO uint32_t DINR0;
\r
1840 __IO uint32_t DINR1;
\r
1841 __IO uint32_t DINR2;
\r
1842 __IO uint32_t DINR3;
\r
1843 __IO uint32_t DINR4;
\r
1844 __IO uint32_t DINR5;
\r
1845 __IO uint32_t DINR6;
\r
1846 __IO uint32_t DINR7;
\r
1847 __IO uint32_t DINR8;
\r
1848 __IO uint32_t DINR9;
\r
1849 __IO uint32_t DINR10;
\r
1850 __IO uint32_t DINR11;
\r
1851 __IO uint32_t DINR12;
\r
1852 __IO uint32_t DINR13;
\r
1853 __IO uint32_t DINR14;
\r
1854 __IO uint32_t DINR15;
\r
1855 __IO uint32_t DINR16;
\r
1856 __IO uint32_t DINR17;
\r
1857 __IO uint32_t DINR18;
\r
1858 __IO uint32_t DINR19;
\r
1859 __IO uint32_t DINR20;
\r
1860 __IO uint32_t DINR21;
\r
1861 __IO uint32_t DINR22;
\r
1862 __IO uint32_t DINR23;
\r
1863 __IO uint32_t DINR24;
\r
1864 __IO uint32_t DINR25;
\r
1865 __IO uint32_t DINR26;
\r
1866 __IO uint32_t DINR27;
\r
1867 __IO uint32_t DINR28;
\r
1868 __IO uint32_t DINR29;
\r
1869 __IO uint32_t DINR30;
\r
1870 __IO uint32_t DINR31;
\r
1871 __IO uint32_t DOUTR0;
\r
1872 __IO uint32_t DOUTR1;
\r
1873 __IO uint32_t DOUTR2;
\r
1874 __IO uint32_t DOUTR3;
\r
1875 __IO uint32_t DOUTR4;
\r
1876 __IO uint32_t DOUTR5;
\r
1877 __IO uint32_t DOUTR6;
\r
1878 __IO uint32_t DOUTR7;
\r
1879 __IO uint32_t DOUTR8;
\r
1880 __IO uint32_t DOUTR9;
\r
1881 __IO uint32_t DOUTR10;
\r
1882 __IO uint32_t DOUTR11;
\r
1883 __IO uint32_t DOUTR12;
\r
1884 __IO uint32_t DOUTR13;
\r
1885 __IO uint32_t DOUTR14;
\r
1886 __IO uint32_t DOUTR15;
\r
1887 __IO uint32_t DOUTR16;
\r
1888 __IO uint32_t DOUTR17;
\r
1889 __IO uint32_t DOUTR18;
\r
1890 __IO uint32_t DOUTR19;
\r
1891 __IO uint32_t DOUTR20;
\r
1892 __IO uint32_t DOUTR21;
\r
1893 __IO uint32_t DOUTR22;
\r
1894 __IO uint32_t DOUTR23;
\r
1895 __IO uint32_t DOUTR24;
\r
1896 __IO uint32_t DOUTR25;
\r
1897 __IO uint32_t DOUTR26;
\r
1898 __IO uint32_t DOUTR27;
\r
1899 __IO uint32_t DOUTR28;
\r
1900 __IO uint32_t DOUTR29;
\r
1901 __IO uint32_t DOUTR30;
\r
1902 __IO uint32_t DOUTR31;
\r
1907 * @brief USB_OTG_Core_Registers
\r
1911 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
\r
1912 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
\r
1913 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
\r
1914 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
\r
1915 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
\r
1916 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
\r
1917 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
\r
1918 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
\r
1919 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
\r
1920 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
\r
1921 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
\r
1922 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
\r
1923 uint32_t Reserved30[2]; /*!< Reserved 030h */
\r
1924 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
\r
1925 __IO uint32_t CID; /*!< User ID Register 03Ch */
\r
1926 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
\r
1927 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
\r
1928 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
\r
1929 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
\r
1930 uint32_t Reserved6; /*!< Reserved 050h */
\r
1931 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
\r
1932 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
\r
1933 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
\r
1934 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
\r
1935 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
\r
1936 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
\r
1937 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
\r
1938 } USB_OTG_GlobalTypeDef;
\r
1942 * @brief USB_OTG_device_Registers
\r
1946 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
\r
1947 __IO uint32_t DCTL; /*!< dev Control Register 804h */
\r
1948 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
\r
1949 uint32_t Reserved0C; /*!< Reserved 80Ch */
\r
1950 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
\r
1951 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
\r
1952 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
\r
1953 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
\r
1954 uint32_t Reserved20; /*!< Reserved 820h */
\r
1955 uint32_t Reserved9; /*!< Reserved 824h */
\r
1956 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
\r
1957 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
\r
1958 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
\r
1959 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
\r
1960 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
\r
1961 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
\r
1962 uint32_t Reserved40; /*!< dedicated EP mask 840h */
\r
1963 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
\r
1964 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
\r
1965 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
\r
1966 } USB_OTG_DeviceTypeDef;
\r
1970 * @brief USB_OTG_IN_Endpoint-Specific_Register
\r
1974 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
\r
1975 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
\r
1976 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
\r
1977 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
\r
1978 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
\r
1979 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
\r
1980 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
\r
1981 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
\r
1982 } USB_OTG_INEndpointTypeDef;
\r
1986 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
\r
1990 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
\r
1991 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
\r
1992 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
\r
1993 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
\r
1994 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
\r
1995 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
\r
1996 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
\r
1997 } USB_OTG_OUTEndpointTypeDef;
\r
2001 * @brief USB_OTG_Host_Mode_Register_Structures
\r
2005 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
\r
2006 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
\r
2007 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
\r
2008 uint32_t Reserved40C; /*!< Reserved 40Ch */
\r
2009 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
\r
2010 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
\r
2011 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
\r
2012 } USB_OTG_HostTypeDef;
\r
2015 * @brief USB_OTG_Host_Channel_Specific_Registers
\r
2019 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
\r
2020 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
\r
2021 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
\r
2022 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
\r
2023 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
\r
2024 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
\r
2025 uint32_t Reserved[2]; /*!< Reserved */
\r
2026 } USB_OTG_HostChannelTypeDef;
\r
2032 /** @addtogroup Peripheral_memory_map
\r
2035 #define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
\r
2036 #define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
\r
2037 #define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */
\r
2038 #define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
\r
2039 #define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
\r
2040 #define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
\r
2042 #define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
\r
2043 #define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
\r
2045 #define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
\r
2046 #define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
\r
2048 #define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */
\r
2049 #define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */
\r
2051 #define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
\r
2052 #define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
\r
2053 #define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
\r
2055 /* Legacy define */
\r
2056 #define FLASH_BASE FLASH_BANK1_BASE
\r
2058 /*!< Device electronic signature memory map */
\r
2059 #define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */
\r
2060 #define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */
\r
2063 /*!< Peripheral memory map */
\r
2064 #define D2_APB1PERIPH_BASE PERIPH_BASE
\r
2065 #define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
\r
2066 #define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
\r
2067 #define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
\r
2069 #define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
\r
2070 #define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
\r
2072 #define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
\r
2073 #define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
\r
2075 /*!< Legacy Peripheral memory map */
\r
2076 #define APB1PERIPH_BASE PERIPH_BASE
\r
2077 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
\r
2078 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
\r
2079 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
\r
2082 /*!< D1_AHB1PERIPH peripherals */
\r
2084 #define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
\r
2085 #define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
\r
2086 #define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)
\r
2087 #define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
\r
2088 #define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
\r
2089 #define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
\r
2090 #define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
\r
2091 #define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
\r
2092 #define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
\r
2093 #define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
\r
2095 /*!< D2_AHB1PERIPH peripherals */
\r
2097 #define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
\r
2098 #define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
\r
2099 #define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
\r
2100 #define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
\r
2101 #define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
\r
2102 #define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
\r
2103 #define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL)
\r
2104 #define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
\r
2105 #define ETH_MAC_BASE (ETH_BASE)
\r
2107 /*!< USB registers base address */
\r
2108 #define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
\r
2109 #define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
\r
2110 #define USB_OTG_GLOBAL_BASE (0x000UL)
\r
2111 #define USB_OTG_DEVICE_BASE (0x800UL)
\r
2112 #define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
\r
2113 #define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
\r
2114 #define USB_OTG_EP_REG_SIZE (0x20UL)
\r
2115 #define USB_OTG_HOST_BASE (0x400UL)
\r
2116 #define USB_OTG_HOST_PORT_BASE (0x440UL)
\r
2117 #define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
\r
2118 #define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
\r
2119 #define USB_OTG_PCGCCTL_BASE (0xE00UL)
\r
2120 #define USB_OTG_FIFO_BASE (0x1000UL)
\r
2121 #define USB_OTG_FIFO_SIZE (0x1000UL)
\r
2123 /*!< D2_AHB2PERIPH peripherals */
\r
2125 #define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
\r
2126 #define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
\r
2127 #define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
\r
2128 #define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
\r
2129 #define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
\r
2131 /*!< D3_AHB1PERIPH peripherals */
\r
2132 #define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
\r
2133 #define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
\r
2134 #define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
\r
2135 #define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
\r
2136 #define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
\r
2137 #define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
\r
2138 #define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
\r
2139 #define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
\r
2140 #define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
\r
2141 #define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
\r
2142 #define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
\r
2143 #define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
\r
2144 #define RCC_C1_BASE (RCC_BASE + 0x130UL)
\r
2145 #define RCC_C2_BASE (RCC_BASE + 0x190UL)
\r
2146 #define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
\r
2147 #define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
\r
2148 #define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
\r
2149 #define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
\r
2150 #define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
\r
2151 #define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
\r
2152 #define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
\r
2153 #define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
\r
2155 /*!< D1_APB1PERIPH peripherals */
\r
2156 #define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
\r
2157 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
\r
2158 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
\r
2159 #define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
\r
2161 /*!< D2_APB1PERIPH peripherals */
\r
2162 #define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
\r
2163 #define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
\r
2164 #define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
\r
2165 #define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
\r
2166 #define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
\r
2167 #define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
\r
2168 #define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
\r
2169 #define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
\r
2170 #define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
\r
2171 #define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
\r
2173 #define WWDG2_BASE (D2_APB1PERIPH_BASE + 0x2C00UL)
\r
2175 #define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
\r
2176 #define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
\r
2177 #define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
\r
2178 #define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
\r
2179 #define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
\r
2180 #define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
\r
2181 #define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
\r
2182 #define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
\r
2183 #define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
\r
2184 #define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
\r
2185 #define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
\r
2186 #define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
\r
2187 #define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
\r
2188 #define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
\r
2189 #define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
\r
2190 #define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
\r
2191 #define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
\r
2192 #define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
\r
2193 #define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
\r
2194 #define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
\r
2195 #define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
\r
2196 #define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
\r
2197 #define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
\r
2198 #define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
\r
2200 /*!< D2_APB2PERIPH peripherals */
\r
2202 #define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
\r
2203 #define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
\r
2204 #define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
\r
2205 #define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
\r
2206 #define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
\r
2207 #define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
\r
2208 #define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
\r
2209 #define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
\r
2210 #define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
\r
2211 #define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
\r
2212 #define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
\r
2213 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
\r
2214 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
\r
2215 #define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
\r
2216 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
\r
2217 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
\r
2218 #define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
\r
2219 #define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
\r
2220 #define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
\r
2221 #define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
\r
2222 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
\r
2223 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
\r
2224 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
\r
2225 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
\r
2226 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
\r
2227 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
\r
2228 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
\r
2229 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
\r
2230 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
\r
2231 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
\r
2232 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
\r
2233 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
\r
2234 #define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
\r
2235 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
\r
2236 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
\r
2237 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
\r
2238 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
\r
2239 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
\r
2240 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
\r
2243 /*!< D3_APB1PERIPH peripherals */
\r
2244 #define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
\r
2245 #define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
\r
2246 #define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
\r
2247 #define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
\r
2248 #define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
\r
2249 #define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
\r
2250 #define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
\r
2251 #define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
\r
2252 #define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
\r
2253 #define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
\r
2254 #define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
\r
2255 #define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
\r
2256 #define COMP1_BASE (COMP12_BASE + 0x0CUL)
\r
2257 #define COMP2_BASE (COMP12_BASE + 0x10UL)
\r
2258 #define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
\r
2259 #define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
\r
2260 #define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
\r
2262 #define IWDG2_BASE (D3_APB1PERIPH_BASE + 0x4C00UL)
\r
2264 #define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
\r
2265 #define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
\r
2266 #define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
\r
2271 #define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
\r
2272 #define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
\r
2273 #define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
\r
2274 #define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
\r
2275 #define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
\r
2276 #define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
\r
2277 #define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
\r
2278 #define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
\r
2280 #define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
\r
2281 #define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
\r
2282 #define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
\r
2283 #define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
\r
2284 #define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
\r
2285 #define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
\r
2286 #define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
\r
2287 #define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
\r
2289 #define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
\r
2290 #define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
\r
2291 #define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
\r
2292 #define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
\r
2293 #define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
\r
2294 #define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
\r
2295 #define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
\r
2296 #define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
\r
2298 #define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
\r
2299 #define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
\r
2301 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
\r
2302 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
\r
2303 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
\r
2304 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
\r
2305 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
\r
2306 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
\r
2307 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
\r
2308 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
\r
2310 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
\r
2311 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
\r
2312 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
\r
2313 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
\r
2314 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
\r
2315 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
\r
2316 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
\r
2317 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
\r
2319 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
\r
2320 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
\r
2321 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
\r
2322 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
\r
2323 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
\r
2324 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
\r
2325 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
\r
2326 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
\r
2327 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
\r
2328 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
\r
2329 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
\r
2330 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
\r
2331 #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
\r
2332 #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
\r
2333 #define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
\r
2334 #define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
\r
2336 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
\r
2337 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
\r
2338 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
\r
2339 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
\r
2340 #define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
\r
2341 #define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
\r
2342 #define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
\r
2343 #define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
\r
2345 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
\r
2346 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
\r
2348 /*!< FMC Banks registers base address */
\r
2349 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
\r
2350 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
\r
2351 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
\r
2352 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
\r
2353 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
\r
2355 /* Debug MCU registers base address */
\r
2356 #define DBGMCU_BASE (0x5C001000UL)
\r
2358 #define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
\r
2359 #define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
\r
2360 #define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
\r
2361 #define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
\r
2362 #define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
\r
2363 #define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
\r
2364 #define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
\r
2365 #define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
\r
2366 #define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
\r
2367 #define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
\r
2368 #define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
\r
2369 #define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
\r
2370 #define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
\r
2371 #define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
\r
2372 #define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
\r
2373 #define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
\r
2375 #define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
\r
2376 #define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
\r
2377 #define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
\r
2378 #define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
\r
2379 #define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
\r
2381 #define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
\r
2382 #define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
\r
2383 #define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
\r
2384 #define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
\r
2385 #define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
\r
2387 #define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
\r
2388 #define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
\r
2395 /** @addtogroup Peripheral_declaration
\r
2398 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
\r
2399 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
\r
2400 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
\r
2401 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
\r
2402 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
\r
2403 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
\r
2404 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
\r
2405 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
\r
2406 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
\r
2407 #define RTC ((RTC_TypeDef *) RTC_BASE)
\r
2408 #define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
\r
2410 #define WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)
\r
2411 #define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)
\r
2413 #define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
\r
2414 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
\r
2415 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
\r
2416 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
\r
2417 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
\r
2418 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
\r
2419 #define USART2 ((USART_TypeDef *) USART2_BASE)
\r
2420 #define USART3 ((USART_TypeDef *) USART3_BASE)
\r
2421 #define USART6 ((USART_TypeDef *) USART6_BASE)
\r
2422 #define UART7 ((USART_TypeDef *) UART7_BASE)
\r
2423 #define UART8 ((USART_TypeDef *) UART8_BASE)
\r
2424 #define CRS ((CRS_TypeDef *) CRS_BASE)
\r
2425 #define UART4 ((USART_TypeDef *) UART4_BASE)
\r
2426 #define UART5 ((USART_TypeDef *) UART5_BASE)
\r
2427 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
\r
2428 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
\r
2429 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
\r
2430 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
\r
2431 #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
\r
2432 #define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
\r
2433 #define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
\r
2434 #define CEC ((CEC_TypeDef *) CEC_BASE)
\r
2435 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
\r
2436 #define PWR ((PWR_TypeDef *) PWR_BASE)
\r
2437 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
\r
2438 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
\r
2439 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
\r
2440 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
\r
2441 #define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
\r
2442 #define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
\r
2443 #define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
\r
2445 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
\r
2446 #define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
\r
2447 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
\r
2448 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
\r
2449 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
\r
2450 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
\r
2451 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
\r
2452 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
\r
2455 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
\r
2456 #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
\r
2457 #define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
\r
2458 #define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE)
\r
2459 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
\r
2460 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
\r
2461 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
\r
2462 #define USART1 ((USART_TypeDef *) USART1_BASE)
\r
2463 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
\r
2464 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
\r
2465 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
\r
2466 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
\r
2467 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
\r
2468 #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
\r
2469 #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
\r
2470 #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
\r
2471 #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
\r
2472 #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
\r
2473 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
\r
2474 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
\r
2475 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
\r
2476 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
\r
2477 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
\r
2478 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
\r
2479 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
\r
2480 #define SAI3 ((SAI_TypeDef *) SAI3_BASE)
\r
2481 #define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
\r
2482 #define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
\r
2483 #define SAI4 ((SAI_TypeDef *) SAI4_BASE)
\r
2484 #define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
\r
2485 #define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
\r
2487 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
\r
2488 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
\r
2489 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
\r
2490 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
\r
2491 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
\r
2492 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
\r
2493 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
\r
2494 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
\r
2495 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
\r
2496 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
\r
2497 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
\r
2498 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
\r
2499 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
\r
2500 #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
\r
2501 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
\r
2502 #define RCC ((RCC_TypeDef *) RCC_BASE)
\r
2503 #define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
\r
2504 #define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)
\r
2505 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
\r
2506 #define CRC ((CRC_TypeDef *) CRC_BASE)
\r
2508 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
\r
2509 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
\r
2510 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
\r
2511 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
\r
2512 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
\r
2513 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
\r
2514 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
\r
2515 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
\r
2516 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
\r
2517 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
\r
2518 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
\r
2520 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
\r
2521 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
\r
2522 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
\r
2523 #define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
\r
2524 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
\r
2526 #define RNG ((RNG_TypeDef *) RNG_BASE)
\r
2527 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
\r
2528 #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
\r
2530 #define BDMA ((BDMA_TypeDef *) BDMA_BASE)
\r
2531 #define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
\r
2532 #define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
\r
2533 #define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
\r
2534 #define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
\r
2535 #define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
\r
2536 #define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
\r
2537 #define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
\r
2538 #define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
\r
2540 #define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
\r
2541 #define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
\r
2542 #define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
\r
2543 #define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
\r
2544 #define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
\r
2545 #define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
\r
2547 #define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
\r
2548 #define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
\r
2549 #define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
\r
2550 #define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
\r
2551 #define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
\r
2552 #define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
\r
2554 #define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
\r
2555 #define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
\r
2556 #define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
\r
2558 #define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
\r
2559 #define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
\r
2560 #define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
\r
2561 #define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
\r
2562 #define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
\r
2563 #define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
\r
2564 #define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
\r
2565 #define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
\r
2566 #define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
\r
2569 #define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
\r
2570 #define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
\r
2571 #define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
\r
2572 #define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
\r
2573 #define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
\r
2574 #define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
\r
2575 #define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
\r
2576 #define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
\r
2578 #define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
\r
2579 #define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
\r
2581 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
\r
2582 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
\r
2583 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
\r
2584 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
\r
2585 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
\r
2586 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
\r
2587 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
\r
2588 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
\r
2589 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
\r
2591 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
\r
2592 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
\r
2593 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
\r
2594 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
\r
2595 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
\r
2596 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
\r
2597 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
\r
2598 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
\r
2599 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
\r
2602 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
\r
2603 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
\r
2604 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
\r
2605 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
\r
2606 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
\r
2607 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
\r
2608 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
\r
2609 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
\r
2610 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
\r
2611 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
\r
2612 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
\r
2613 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
\r
2614 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
\r
2615 #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
\r
2616 #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
\r
2617 #define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
\r
2618 #define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
\r
2620 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
\r
2621 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
\r
2622 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
\r
2623 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
\r
2624 #define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
\r
2625 #define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
\r
2626 #define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
\r
2627 #define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
\r
2629 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
\r
2630 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
\r
2633 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
\r
2634 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
\r
2635 #define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
\r
2636 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
\r
2637 #define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
\r
2640 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
\r
2641 #define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
\r
2642 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
\r
2643 #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
\r
2645 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
\r
2647 #define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
\r
2648 #define HSEM ((HSEM_TypeDef *) HSEM_BASE)
\r
2649 #if defined(CORE_CM4)
\r
2650 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))
\r
2651 #else /* CORE_CM7 */
\r
2652 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
\r
2653 #endif /* CORE_CM4 */
\r
2655 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
\r
2656 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
\r
2657 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
\r
2659 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
\r
2661 #define ETH ((ETH_TypeDef *)ETH_BASE)
\r
2662 #define MDMA ((MDMA_TypeDef *)MDMA_BASE)
\r
2663 #define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
\r
2664 #define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
\r
2665 #define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
\r
2666 #define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
\r
2667 #define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
\r
2668 #define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
\r
2669 #define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
\r
2670 #define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
\r
2671 #define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
\r
2672 #define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
\r
2673 #define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
\r
2674 #define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
\r
2675 #define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
\r
2676 #define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
\r
2677 #define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
\r
2678 #define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
\r
2681 #define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
\r
2682 #define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
\r
2684 /* Legacy defines */
\r
2685 #define USB_OTG_HS USB1_OTG_HS
\r
2686 #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
\r
2687 #define USB_OTG_FS USB2_OTG_FS
\r
2688 #define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
\r
2694 /** @addtogroup Exported_constants
\r
2698 /** @addtogroup Peripheral_Registers_Bits_Definition
\r
2702 /******************************************************************************/
\r
2703 /* Peripheral Registers_Bits_Definition */
\r
2704 /******************************************************************************/
\r
2706 /******************************************************************************/
\r
2708 /* Analog to Digital Converter */
\r
2710 /******************************************************************************/
\r
2711 /******************************* ADC VERSION ********************************/
\r
2712 #define ADC_VER_V5_X
\r
2713 /******************** Bit definition for ADC_ISR register ********************/
\r
2714 #define ADC_ISR_ADRDY_Pos (0U)
\r
2715 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
\r
2716 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
\r
2717 #define ADC_ISR_EOSMP_Pos (1U)
\r
2718 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
\r
2719 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
\r
2720 #define ADC_ISR_EOC_Pos (2U)
\r
2721 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
\r
2722 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
\r
2723 #define ADC_ISR_EOS_Pos (3U)
\r
2724 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
\r
2725 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
\r
2726 #define ADC_ISR_OVR_Pos (4U)
\r
2727 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
\r
2728 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
\r
2729 #define ADC_ISR_JEOC_Pos (5U)
\r
2730 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
\r
2731 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
\r
2732 #define ADC_ISR_JEOS_Pos (6U)
\r
2733 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
\r
2734 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
\r
2735 #define ADC_ISR_AWD1_Pos (7U)
\r
2736 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
\r
2737 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
\r
2738 #define ADC_ISR_AWD2_Pos (8U)
\r
2739 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
\r
2740 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
\r
2741 #define ADC_ISR_AWD3_Pos (9U)
\r
2742 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
\r
2743 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
\r
2744 #define ADC_ISR_JQOVF_Pos (10U)
\r
2745 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
\r
2746 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
\r
2748 /******************** Bit definition for ADC_IER register ********************/
\r
2749 #define ADC_IER_ADRDYIE_Pos (0U)
\r
2750 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
\r
2751 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
\r
2752 #define ADC_IER_EOSMPIE_Pos (1U)
\r
2753 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
\r
2754 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
\r
2755 #define ADC_IER_EOCIE_Pos (2U)
\r
2756 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
\r
2757 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
\r
2758 #define ADC_IER_EOSIE_Pos (3U)
\r
2759 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
\r
2760 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
\r
2761 #define ADC_IER_OVRIE_Pos (4U)
\r
2762 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
\r
2763 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
\r
2764 #define ADC_IER_JEOCIE_Pos (5U)
\r
2765 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
\r
2766 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
\r
2767 #define ADC_IER_JEOSIE_Pos (6U)
\r
2768 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
\r
2769 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
\r
2770 #define ADC_IER_AWD1IE_Pos (7U)
\r
2771 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
\r
2772 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
\r
2773 #define ADC_IER_AWD2IE_Pos (8U)
\r
2774 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
\r
2775 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
\r
2776 #define ADC_IER_AWD3IE_Pos (9U)
\r
2777 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
\r
2778 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
\r
2779 #define ADC_IER_JQOVFIE_Pos (10U)
\r
2780 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
\r
2781 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
\r
2783 /******************** Bit definition for ADC_CR register ********************/
\r
2784 #define ADC_CR_ADEN_Pos (0U)
\r
2785 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
\r
2786 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
\r
2787 #define ADC_CR_ADDIS_Pos (1U)
\r
2788 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
\r
2789 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
\r
2790 #define ADC_CR_ADSTART_Pos (2U)
\r
2791 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
\r
2792 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
\r
2793 #define ADC_CR_JADSTART_Pos (3U)
\r
2794 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
\r
2795 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
\r
2796 #define ADC_CR_ADSTP_Pos (4U)
\r
2797 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
\r
2798 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
\r
2799 #define ADC_CR_JADSTP_Pos (5U)
\r
2800 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
\r
2801 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
\r
2802 #define ADC_CR_BOOST_Pos (8U)
\r
2803 #define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
\r
2804 #define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
\r
2805 #define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
\r
2806 #define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
\r
2807 #define ADC_CR_ADCALLIN_Pos (16U)
\r
2808 #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
\r
2809 #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
\r
2810 #define ADC_CR_LINCALRDYW1_Pos (22U)
\r
2811 #define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
\r
2812 #define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
\r
2813 #define ADC_CR_LINCALRDYW2_Pos (23U)
\r
2814 #define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
\r
2815 #define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
\r
2816 #define ADC_CR_LINCALRDYW3_Pos (24U)
\r
2817 #define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
\r
2818 #define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
\r
2819 #define ADC_CR_LINCALRDYW4_Pos (25U)
\r
2820 #define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
\r
2821 #define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
\r
2822 #define ADC_CR_LINCALRDYW5_Pos (26U)
\r
2823 #define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
\r
2824 #define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
\r
2825 #define ADC_CR_LINCALRDYW6_Pos (27U)
\r
2826 #define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
\r
2827 #define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
\r
2828 #define ADC_CR_ADVREGEN_Pos (28U)
\r
2829 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
\r
2830 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
\r
2831 #define ADC_CR_DEEPPWD_Pos (29U)
\r
2832 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
\r
2833 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
\r
2834 #define ADC_CR_ADCALDIF_Pos (30U)
\r
2835 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
\r
2836 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
\r
2837 #define ADC_CR_ADCAL_Pos (31U)
\r
2838 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
\r
2839 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
\r
2841 /******************** Bit definition for ADC_CFGR register ********************/
\r
2842 #define ADC_CFGR_DMNGT_Pos (0U)
\r
2843 #define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
\r
2844 #define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
\r
2845 #define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
\r
2846 #define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
\r
2848 #define ADC_CFGR_RES_Pos (2U)
\r
2849 #define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
\r
2850 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
\r
2851 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
\r
2852 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
\r
2853 #define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
\r
2855 #define ADC_CFGR_EXTSEL_Pos (5U)
\r
2856 #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
\r
2857 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
\r
2858 #define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
\r
2859 #define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
\r
2860 #define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
\r
2861 #define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
\r
2862 #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
\r
2864 #define ADC_CFGR_EXTEN_Pos (10U)
\r
2865 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
\r
2866 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
\r
2867 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
\r
2868 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
\r
2870 #define ADC_CFGR_OVRMOD_Pos (12U)
\r
2871 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
\r
2872 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
\r
2873 #define ADC_CFGR_CONT_Pos (13U)
\r
2874 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
\r
2875 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
\r
2876 #define ADC_CFGR_AUTDLY_Pos (14U)
\r
2877 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
\r
2878 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
\r
2880 #define ADC_CFGR_DISCEN_Pos (16U)
\r
2881 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
\r
2882 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
\r
2884 #define ADC_CFGR_DISCNUM_Pos (17U)
\r
2885 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
\r
2886 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
\r
2887 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
\r
2888 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
\r
2889 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
\r
2891 #define ADC_CFGR_JDISCEN_Pos (20U)
\r
2892 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
\r
2893 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
\r
2894 #define ADC_CFGR_JQM_Pos (21U)
\r
2895 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
\r
2896 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
\r
2897 #define ADC_CFGR_AWD1SGL_Pos (22U)
\r
2898 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
\r
2899 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
\r
2900 #define ADC_CFGR_AWD1EN_Pos (23U)
\r
2901 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
\r
2902 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
\r
2903 #define ADC_CFGR_JAWD1EN_Pos (24U)
\r
2904 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
\r
2905 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
\r
2906 #define ADC_CFGR_JAUTO_Pos (25U)
\r
2907 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
\r
2908 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
\r
2910 #define ADC_CFGR_AWD1CH_Pos (26U)
\r
2911 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
\r
2912 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
\r
2913 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
\r
2914 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
\r
2915 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
\r
2916 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
\r
2917 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
\r
2919 #define ADC_CFGR_JQDIS_Pos (31U)
\r
2920 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
\r
2921 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
\r
2923 /******************** Bit definition for ADC_CFGR2 register ********************/
\r
2924 #define ADC_CFGR2_ROVSE_Pos (0U)
\r
2925 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
\r
2926 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
\r
2927 #define ADC_CFGR2_JOVSE_Pos (1U)
\r
2928 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
\r
2929 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
\r
2931 #define ADC_CFGR2_OVSS_Pos (5U)
\r
2932 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
\r
2933 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
\r
2934 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
\r
2935 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
\r
2936 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
\r
2937 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
\r
2939 #define ADC_CFGR2_TROVS_Pos (9U)
\r
2940 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
\r
2941 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
\r
2942 #define ADC_CFGR2_ROVSM_Pos (10U)
\r
2943 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
\r
2944 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
\r
2946 #define ADC_CFGR2_RSHIFT1_Pos (11U)
\r
2947 #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
\r
2948 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
\r
2949 #define ADC_CFGR2_RSHIFT2_Pos (12U)
\r
2950 #define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
\r
2951 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
\r
2952 #define ADC_CFGR2_RSHIFT3_Pos (13U)
\r
2953 #define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
\r
2954 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
\r
2955 #define ADC_CFGR2_RSHIFT4_Pos (14U)
\r
2956 #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
\r
2957 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
\r
2959 #define ADC_CFGR2_OVSR_Pos (16U)
\r
2960 #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
\r
2961 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
\r
2962 #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
\r
2963 #define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
\r
2964 #define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
\r
2965 #define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
\r
2966 #define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
\r
2967 #define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
\r
2968 #define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
\r
2969 #define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
\r
2970 #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
\r
2971 #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
\r
2973 #define ADC_CFGR2_LSHIFT_Pos (28U)
\r
2974 #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
\r
2975 #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
\r
2976 #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
\r
2977 #define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
\r
2978 #define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
\r
2979 #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
\r
2981 /******************** Bit definition for ADC_SMPR1 register ********************/
\r
2982 #define ADC_SMPR1_SMP0_Pos (0U)
\r
2983 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
\r
2984 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
\r
2985 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
\r
2986 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
\r
2987 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
\r
2989 #define ADC_SMPR1_SMP1_Pos (3U)
\r
2990 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
\r
2991 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
\r
2992 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
\r
2993 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
\r
2994 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
\r
2996 #define ADC_SMPR1_SMP2_Pos (6U)
\r
2997 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
\r
2998 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
\r
2999 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
\r
3000 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
\r
3001 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
\r
3003 #define ADC_SMPR1_SMP3_Pos (9U)
\r
3004 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
\r
3005 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
\r
3006 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
\r
3007 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
\r
3008 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
\r
3010 #define ADC_SMPR1_SMP4_Pos (12U)
\r
3011 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
\r
3012 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
\r
3013 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
\r
3014 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
\r
3015 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
\r
3017 #define ADC_SMPR1_SMP5_Pos (15U)
\r
3018 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
\r
3019 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
\r
3020 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
\r
3021 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
\r
3022 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
\r
3024 #define ADC_SMPR1_SMP6_Pos (18U)
\r
3025 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
\r
3026 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
\r
3027 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
\r
3028 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
\r
3029 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
\r
3031 #define ADC_SMPR1_SMP7_Pos (21U)
\r
3032 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
\r
3033 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
\r
3034 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
\r
3035 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
\r
3036 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
\r
3038 #define ADC_SMPR1_SMP8_Pos (24U)
\r
3039 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
\r
3040 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
\r
3041 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
\r
3042 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
\r
3043 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
\r
3045 #define ADC_SMPR1_SMP9_Pos (27U)
\r
3046 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
\r
3047 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
\r
3048 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
\r
3049 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
\r
3050 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
\r
3052 /******************** Bit definition for ADC_SMPR2 register ********************/
\r
3053 #define ADC_SMPR2_SMP10_Pos (0U)
\r
3054 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
\r
3055 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
\r
3056 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
\r
3057 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
\r
3058 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
\r
3060 #define ADC_SMPR2_SMP11_Pos (3U)
\r
3061 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
\r
3062 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
\r
3063 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
\r
3064 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
\r
3065 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
\r
3067 #define ADC_SMPR2_SMP12_Pos (6U)
\r
3068 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
\r
3069 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
\r
3070 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
\r
3071 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
\r
3072 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
\r
3074 #define ADC_SMPR2_SMP13_Pos (9U)
\r
3075 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
\r
3076 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
\r
3077 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
\r
3078 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
\r
3079 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
\r
3081 #define ADC_SMPR2_SMP14_Pos (12U)
\r
3082 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
\r
3083 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
\r
3084 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
\r
3085 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
\r
3086 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
\r
3088 #define ADC_SMPR2_SMP15_Pos (15U)
\r
3089 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
\r
3090 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
\r
3091 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
\r
3092 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
\r
3093 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
\r
3095 #define ADC_SMPR2_SMP16_Pos (18U)
\r
3096 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
\r
3097 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
\r
3098 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
\r
3099 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
\r
3100 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
\r
3102 #define ADC_SMPR2_SMP17_Pos (21U)
\r
3103 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
\r
3104 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
\r
3105 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
\r
3106 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
\r
3107 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
\r
3109 #define ADC_SMPR2_SMP18_Pos (24U)
\r
3110 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
\r
3111 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
\r
3112 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
\r
3113 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
\r
3114 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
\r
3116 #define ADC_SMPR2_SMP19_Pos (27U)
\r
3117 #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
\r
3118 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
\r
3119 #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
\r
3120 #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
\r
3121 #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
\r
3123 /******************** Bit definition for ADC_PCSEL register ********************/
\r
3124 #define ADC_PCSEL_PCSEL_Pos (0U)
\r
3125 #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
\r
3126 #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
\r
3127 #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
\r
3128 #define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
\r
3129 #define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
\r
3130 #define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
\r
3131 #define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
\r
3132 #define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
\r
3133 #define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
\r
3134 #define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
\r
3135 #define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
\r
3136 #define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
\r
3137 #define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
\r
3138 #define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
\r
3139 #define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
\r
3140 #define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
\r
3141 #define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
\r
3142 #define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
\r
3143 #define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
\r
3144 #define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
\r
3145 #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
\r
3146 #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
\r
3148 /***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
\r
3149 #define ADC_LTR_LT_Pos (0U)
\r
3150 #define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
\r
3151 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
\r
3153 /***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
\r
3154 #define ADC_HTR_HT_Pos (0U)
\r
3155 #define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
\r
3156 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
\r
3158 /******************** Bit definition for ADC_SQR1 register ********************/
\r
3159 #define ADC_SQR1_L_Pos (0U)
\r
3160 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
\r
3161 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
\r
3162 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
\r
3163 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
\r
3164 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
\r
3165 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
\r
3167 #define ADC_SQR1_SQ1_Pos (6U)
\r
3168 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
\r
3169 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
\r
3170 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
\r
3171 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
\r
3172 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
\r
3173 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
\r
3174 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
\r
3176 #define ADC_SQR1_SQ2_Pos (12U)
\r
3177 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
\r
3178 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
\r
3179 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
\r
3180 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
\r
3181 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
\r
3182 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
\r
3183 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
\r
3185 #define ADC_SQR1_SQ3_Pos (18U)
\r
3186 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
\r
3187 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
\r
3188 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
\r
3189 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
\r
3190 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
\r
3191 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
\r
3192 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
\r
3194 #define ADC_SQR1_SQ4_Pos (24U)
\r
3195 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
\r
3196 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
\r
3197 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
\r
3198 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
\r
3199 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
\r
3200 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
\r
3201 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
\r
3203 /******************** Bit definition for ADC_SQR2 register ********************/
\r
3204 #define ADC_SQR2_SQ5_Pos (0U)
\r
3205 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
\r
3206 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
\r
3207 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
\r
3208 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
\r
3209 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
\r
3210 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
\r
3211 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
\r
3213 #define ADC_SQR2_SQ6_Pos (6U)
\r
3214 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
\r
3215 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
\r
3216 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
\r
3217 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
\r
3218 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
\r
3219 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
\r
3220 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
\r
3222 #define ADC_SQR2_SQ7_Pos (12U)
\r
3223 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
\r
3224 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
\r
3225 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
\r
3226 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
\r
3227 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
\r
3228 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
\r
3229 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
\r
3231 #define ADC_SQR2_SQ8_Pos (18U)
\r
3232 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
\r
3233 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
\r
3234 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
\r
3235 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
\r
3236 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
\r
3237 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
\r
3238 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
\r
3240 #define ADC_SQR2_SQ9_Pos (24U)
\r
3241 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
\r
3242 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
\r
3243 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
\r
3244 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
\r
3245 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
\r
3246 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
\r
3247 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
\r
3249 /******************** Bit definition for ADC_SQR3 register ********************/
\r
3250 #define ADC_SQR3_SQ10_Pos (0U)
\r
3251 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
\r
3252 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
\r
3253 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
\r
3254 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
\r
3255 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
\r
3256 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
\r
3257 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
\r
3259 #define ADC_SQR3_SQ11_Pos (6U)
\r
3260 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
\r
3261 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
\r
3262 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
\r
3263 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
\r
3264 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
\r
3265 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
\r
3266 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
\r
3268 #define ADC_SQR3_SQ12_Pos (12U)
\r
3269 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
\r
3270 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
\r
3271 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
\r
3272 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
\r
3273 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
\r
3274 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
\r
3275 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
\r
3277 #define ADC_SQR3_SQ13_Pos (18U)
\r
3278 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
\r
3279 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
\r
3280 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
\r
3281 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
\r
3282 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
\r
3283 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
\r
3284 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
\r
3286 #define ADC_SQR3_SQ14_Pos (24U)
\r
3287 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
\r
3288 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
\r
3289 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
\r
3290 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
\r
3291 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
\r
3292 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
\r
3293 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
\r
3295 /******************** Bit definition for ADC_SQR4 register ********************/
\r
3296 #define ADC_SQR4_SQ15_Pos (0U)
\r
3297 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
\r
3298 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
\r
3299 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
\r
3300 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
\r
3301 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
\r
3302 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
\r
3303 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
\r
3305 #define ADC_SQR4_SQ16_Pos (6U)
\r
3306 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
\r
3307 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
\r
3308 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
\r
3309 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
\r
3310 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
\r
3311 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
\r
3312 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
\r
3313 /******************** Bit definition for ADC_DR register ********************/
\r
3314 #define ADC_DR_RDATA_Pos (0U)
\r
3315 #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
\r
3316 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
\r
3318 /******************** Bit definition for ADC_JSQR register ********************/
\r
3319 #define ADC_JSQR_JL_Pos (0U)
\r
3320 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
\r
3321 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
\r
3322 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
\r
3323 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
\r
3325 #define ADC_JSQR_JEXTSEL_Pos (2U)
\r
3326 #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
\r
3327 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
\r
3328 #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
\r
3329 #define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
\r
3330 #define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
\r
3331 #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
\r
3332 #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
\r
3334 #define ADC_JSQR_JEXTEN_Pos (7U)
\r
3335 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
\r
3336 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
\r
3337 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
\r
3338 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
\r
3340 #define ADC_JSQR_JSQ1_Pos (9U)
\r
3341 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
\r
3342 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
\r
3343 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
\r
3344 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
\r
3345 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
\r
3346 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
\r
3347 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
\r
3349 #define ADC_JSQR_JSQ2_Pos (15U)
\r
3350 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
\r
3351 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
\r
3352 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
\r
3353 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
\r
3354 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
\r
3355 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
\r
3356 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
\r
3358 #define ADC_JSQR_JSQ3_Pos (21U)
\r
3359 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
\r
3360 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
\r
3361 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
\r
3362 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
\r
3363 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
\r
3364 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
\r
3365 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
\r
3367 #define ADC_JSQR_JSQ4_Pos (27U)
\r
3368 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
\r
3369 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
\r
3370 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
\r
3371 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
\r
3372 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
\r
3373 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
\r
3374 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
\r
3376 /******************** Bit definition for ADC_OFR1 register ********************/
\r
3377 #define ADC_OFR1_OFFSET1_Pos (0U)
\r
3378 #define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
\r
3379 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
\r
3380 #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
\r
3381 #define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
\r
3382 #define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
\r
3383 #define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
\r
3384 #define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
\r
3385 #define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
\r
3386 #define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
\r
3387 #define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
\r
3388 #define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
\r
3389 #define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
\r
3390 #define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
\r
3391 #define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
\r
3392 #define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
\r
3393 #define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
\r
3394 #define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
\r
3395 #define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
\r
3396 #define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
\r
3397 #define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
\r
3398 #define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
\r
3399 #define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
\r
3400 #define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
\r
3401 #define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
\r
3402 #define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
\r
3403 #define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
\r
3404 #define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
\r
3405 #define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
\r
3407 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
\r
3408 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
\r
3409 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
\r
3410 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
\r
3411 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
\r
3412 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
\r
3413 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
\r
3414 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
\r
3416 #define ADC_OFR1_SSATE_Pos (31U)
\r
3417 #define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
\r
3418 #define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
\r
3420 /******************** Bit definition for ADC_OFR2 register ********************/
\r
3421 #define ADC_OFR2_OFFSET2_Pos (0U)
\r
3422 #define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
\r
3423 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
\r
3424 #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
\r
3425 #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
\r
3426 #define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
\r
3427 #define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
\r
3428 #define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
\r
3429 #define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
\r
3430 #define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
\r
3431 #define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
\r
3432 #define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
\r
3433 #define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
\r
3434 #define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
\r
3435 #define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
\r
3436 #define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
\r
3437 #define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
\r
3438 #define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
\r
3439 #define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
\r
3440 #define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
\r
3441 #define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
\r
3442 #define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
\r
3443 #define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
\r
3444 #define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
\r
3445 #define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
\r
3446 #define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
\r
3447 #define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
\r
3448 #define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
\r
3449 #define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
\r
3451 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
\r
3452 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
\r
3453 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
\r
3454 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
\r
3455 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
\r
3456 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
\r
3457 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
\r
3458 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
\r
3460 #define ADC_OFR2_SSATE_Pos (31U)
\r
3461 #define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
\r
3462 #define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
\r
3464 /******************** Bit definition for ADC_OFR3 register ********************/
\r
3465 #define ADC_OFR3_OFFSET3_Pos (0U)
\r
3466 #define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
\r
3467 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
\r
3468 #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
\r
3469 #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
\r
3470 #define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
\r
3471 #define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
\r
3472 #define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
\r
3473 #define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
\r
3474 #define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
\r
3475 #define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
\r
3476 #define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
\r
3477 #define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
\r
3478 #define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
\r
3479 #define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
\r
3480 #define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
\r
3481 #define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
\r
3482 #define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
\r
3483 #define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
\r
3484 #define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
\r
3485 #define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
\r
3486 #define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
\r
3487 #define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
\r
3488 #define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
\r
3489 #define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
\r
3490 #define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
\r
3491 #define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
\r
3492 #define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
\r
3493 #define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
\r
3495 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
\r
3496 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
\r
3497 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
\r
3498 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
\r
3499 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
\r
3500 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
\r
3501 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
\r
3502 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
\r
3504 #define ADC_OFR3_SSATE_Pos (31U)
\r
3505 #define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
\r
3506 #define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
\r
3508 /******************** Bit definition for ADC_OFR4 register ********************/
\r
3509 #define ADC_OFR4_OFFSET4_Pos (0U)
\r
3510 #define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
\r
3511 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
\r
3512 #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
\r
3513 #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
\r
3514 #define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
\r
3515 #define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
\r
3516 #define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
\r
3517 #define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
\r
3518 #define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
\r
3519 #define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
\r
3520 #define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
\r
3521 #define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
\r
3522 #define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
\r
3523 #define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
\r
3524 #define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
\r
3525 #define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
\r
3526 #define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
\r
3527 #define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
\r
3528 #define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
\r
3529 #define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
\r
3530 #define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
\r
3531 #define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
\r
3532 #define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
\r
3533 #define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
\r
3534 #define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
\r
3535 #define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
\r
3536 #define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
\r
3537 #define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
\r
3539 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
\r
3540 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
\r
3541 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
\r
3542 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
\r
3543 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
\r
3544 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
\r
3545 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
\r
3546 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
\r
3548 #define ADC_OFR4_SSATE_Pos (31U)
\r
3549 #define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
\r
3550 #define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
\r
3552 /******************** Bit definition for ADC_JDR1 register ********************/
\r
3553 #define ADC_JDR1_JDATA_Pos (0U)
\r
3554 #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
\r
3555 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
\r
3556 #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
\r
3557 #define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
\r
3558 #define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
\r
3559 #define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
\r
3560 #define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
\r
3561 #define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
\r
3562 #define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
\r
3563 #define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
\r
3564 #define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
\r
3565 #define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
\r
3566 #define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
\r
3567 #define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
\r
3568 #define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
\r
3569 #define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
\r
3570 #define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
\r
3571 #define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
\r
3572 #define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
\r
3573 #define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
\r
3574 #define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
\r
3575 #define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
\r
3576 #define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
\r
3577 #define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
\r
3578 #define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
\r
3579 #define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
\r
3580 #define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
\r
3581 #define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
\r
3582 #define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
\r
3583 #define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
\r
3584 #define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
\r
3585 #define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
\r
3586 #define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
\r
3587 #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
\r
3589 /******************** Bit definition for ADC_JDR2 register ********************/
\r
3590 #define ADC_JDR2_JDATA_Pos (0U)
\r
3591 #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
\r
3592 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
\r
3593 #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
\r
3594 #define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
\r
3595 #define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
\r
3596 #define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
\r
3597 #define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
\r
3598 #define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
\r
3599 #define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
\r
3600 #define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
\r
3601 #define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
\r
3602 #define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
\r
3603 #define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
\r
3604 #define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
\r
3605 #define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
\r
3606 #define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
\r
3607 #define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
\r
3608 #define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
\r
3609 #define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
\r
3610 #define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
\r
3611 #define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
\r
3612 #define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
\r
3613 #define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
\r
3614 #define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
\r
3615 #define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
\r
3616 #define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
\r
3617 #define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
\r
3618 #define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
\r
3619 #define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
\r
3620 #define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
\r
3621 #define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
\r
3622 #define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
\r
3623 #define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
\r
3624 #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
\r
3626 /******************** Bit definition for ADC_JDR3 register ********************/
\r
3627 #define ADC_JDR3_JDATA_Pos (0U)
\r
3628 #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
\r
3629 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
\r
3630 #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
\r
3631 #define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
\r
3632 #define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
\r
3633 #define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
\r
3634 #define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
\r
3635 #define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
\r
3636 #define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
\r
3637 #define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
\r
3638 #define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
\r
3639 #define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
\r
3640 #define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
\r
3641 #define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
\r
3642 #define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
\r
3643 #define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
\r
3644 #define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
\r
3645 #define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
\r
3646 #define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
\r
3647 #define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
\r
3648 #define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
\r
3649 #define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
\r
3650 #define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
\r
3651 #define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
\r
3652 #define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
\r
3653 #define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
\r
3654 #define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
\r
3655 #define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
\r
3656 #define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
\r
3657 #define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
\r
3658 #define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
\r
3659 #define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
\r
3660 #define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
\r
3661 #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
\r
3663 /******************** Bit definition for ADC_JDR4 register ********************/
\r
3664 #define ADC_JDR4_JDATA_Pos (0U)
\r
3665 #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
\r
3666 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
\r
3667 #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
\r
3668 #define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
\r
3669 #define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
\r
3670 #define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
\r
3671 #define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
\r
3672 #define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
\r
3673 #define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
\r
3674 #define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
\r
3675 #define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
\r
3676 #define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
\r
3677 #define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
\r
3678 #define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
\r
3679 #define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
\r
3680 #define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
\r
3681 #define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
\r
3682 #define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
\r
3683 #define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
\r
3684 #define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
\r
3685 #define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
\r
3686 #define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
\r
3687 #define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
\r
3688 #define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
\r
3689 #define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
\r
3690 #define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
\r
3691 #define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
\r
3692 #define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
\r
3693 #define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
\r
3694 #define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
\r
3695 #define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
\r
3696 #define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
\r
3697 #define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
\r
3698 #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
\r
3700 /******************** Bit definition for ADC_AWD2CR register ********************/
\r
3701 #define ADC_AWD2CR_AWD2CH_Pos (0U)
\r
3702 #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
\r
3703 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
\r
3704 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
\r
3705 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
\r
3706 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
\r
3707 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
\r
3708 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
\r
3709 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
\r
3710 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
\r
3711 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
\r
3712 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
\r
3713 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
\r
3714 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
\r
3715 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
\r
3716 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
\r
3717 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
\r
3718 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
\r
3719 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
\r
3720 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
\r
3721 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
\r
3722 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
\r
3723 #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
\r
3725 /******************** Bit definition for ADC_AWD3CR register ********************/
\r
3726 #define ADC_AWD3CR_AWD3CH_Pos (0U)
\r
3727 #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
\r
3728 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
\r
3729 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
\r
3730 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
\r
3731 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
\r
3732 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
\r
3733 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
\r
3734 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
\r
3735 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
\r
3736 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
\r
3737 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
\r
3738 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
\r
3739 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
\r
3740 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
\r
3741 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
\r
3742 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
\r
3743 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
\r
3744 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
\r
3745 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
\r
3746 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
\r
3747 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
\r
3748 #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
\r
3750 /******************** Bit definition for ADC_DIFSEL register ********************/
\r
3751 #define ADC_DIFSEL_DIFSEL_Pos (0U)
\r
3752 #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
\r
3753 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
\r
3754 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
\r
3755 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
\r
3756 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
\r
3757 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
\r
3758 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
\r
3759 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
\r
3760 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
\r
3761 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
\r
3762 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
\r
3763 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
\r
3764 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
\r
3765 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
\r
3766 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
\r
3767 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
\r
3768 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
\r
3769 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
\r
3770 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
\r
3771 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
\r
3772 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
\r
3773 #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
\r
3775 /******************** Bit definition for ADC_CALFACT register ********************/
\r
3776 #define ADC_CALFACT_CALFACT_S_Pos (0U)
\r
3777 #define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
\r
3778 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
\r
3779 #define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
\r
3780 #define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
\r
3781 #define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
\r
3782 #define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
\r
3783 #define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
\r
3784 #define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
\r
3785 #define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
\r
3786 #define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
\r
3787 #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
\r
3788 #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
\r
3789 #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
\r
3790 #define ADC_CALFACT_CALFACT_D_Pos (16U)
\r
3791 #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
\r
3792 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
\r
3793 #define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
\r
3794 #define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
\r
3795 #define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
\r
3796 #define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
\r
3797 #define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
\r
3798 #define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
\r
3799 #define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
\r
3800 #define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
\r
3801 #define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
\r
3802 #define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
\r
3803 #define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
\r
3805 /******************** Bit definition for ADC_CALFACT2 register ********************/
\r
3806 #define ADC_CALFACT2_LINCALFACT_Pos (0U)
\r
3807 #define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
\r
3808 #define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
\r
3809 #define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
\r
3810 #define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
\r
3811 #define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
\r
3812 #define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
\r
3813 #define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
\r
3814 #define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
\r
3815 #define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
\r
3816 #define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
\r
3817 #define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
\r
3818 #define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
\r
3819 #define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
\r
3820 #define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
\r
3821 #define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
\r
3822 #define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
\r
3823 #define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
\r
3824 #define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
\r
3825 #define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
\r
3826 #define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
\r
3827 #define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
\r
3828 #define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
\r
3829 #define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
\r
3830 #define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
\r
3831 #define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
\r
3832 #define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
\r
3833 #define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
\r
3834 #define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
\r
3835 #define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
\r
3836 #define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
\r
3837 #define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
\r
3838 #define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
\r
3840 /************************* ADC Common registers *****************************/
\r
3841 /******************** Bit definition for ADC_CSR register ********************/
\r
3842 #define ADC_CSR_ADRDY_MST_Pos (0U)
\r
3843 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
\r
3844 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
\r
3845 #define ADC_CSR_EOSMP_MST_Pos (1U)
\r
3846 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
\r
3847 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
\r
3848 #define ADC_CSR_EOC_MST_Pos (2U)
\r
3849 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
\r
3850 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
\r
3851 #define ADC_CSR_EOS_MST_Pos (3U)
\r
3852 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
\r
3853 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
\r
3854 #define ADC_CSR_OVR_MST_Pos (4U)
\r
3855 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
\r
3856 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
\r
3857 #define ADC_CSR_JEOC_MST_Pos (5U)
\r
3858 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
\r
3859 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
\r
3860 #define ADC_CSR_JEOS_MST_Pos (6U)
\r
3861 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
\r
3862 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
\r
3863 #define ADC_CSR_AWD1_MST_Pos (7U)
\r
3864 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
\r
3865 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
\r
3866 #define ADC_CSR_AWD2_MST_Pos (8U)
\r
3867 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
\r
3868 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
\r
3869 #define ADC_CSR_AWD3_MST_Pos (9U)
\r
3870 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
\r
3871 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
\r
3872 #define ADC_CSR_JQOVF_MST_Pos (10U)
\r
3873 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
\r
3874 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
\r
3875 #define ADC_CSR_ADRDY_SLV_Pos (16U)
\r
3876 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
\r
3877 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
\r
3878 #define ADC_CSR_EOSMP_SLV_Pos (17U)
\r
3879 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
\r
3880 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
\r
3881 #define ADC_CSR_EOC_SLV_Pos (18U)
\r
3882 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
\r
3883 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
\r
3884 #define ADC_CSR_EOS_SLV_Pos (19U)
\r
3885 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
\r
3886 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
\r
3887 #define ADC_CSR_OVR_SLV_Pos (20U)
\r
3888 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
\r
3889 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
\r
3890 #define ADC_CSR_JEOC_SLV_Pos (21U)
\r
3891 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
\r
3892 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
\r
3893 #define ADC_CSR_JEOS_SLV_Pos (22U)
\r
3894 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
\r
3895 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
\r
3896 #define ADC_CSR_AWD1_SLV_Pos (23U)
\r
3897 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
\r
3898 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
\r
3899 #define ADC_CSR_AWD2_SLV_Pos (24U)
\r
3900 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
\r
3901 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
\r
3902 #define ADC_CSR_AWD3_SLV_Pos (25U)
\r
3903 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
\r
3904 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
\r
3905 #define ADC_CSR_JQOVF_SLV_Pos (26U)
\r
3906 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
\r
3907 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
\r
3909 /******************** Bit definition for ADC_CCR register ********************/
\r
3910 #define ADC_CCR_DUAL_Pos (0U)
\r
3911 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
\r
3912 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
\r
3913 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
\r
3914 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
\r
3915 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
\r
3916 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
\r
3917 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
\r
3919 #define ADC_CCR_DELAY_Pos (8U)
\r
3920 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
\r
3921 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
\r
3922 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
\r
3923 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
\r
3924 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
\r
3925 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
\r
3928 #define ADC_CCR_DAMDF_Pos (14U)
\r
3929 #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
\r
3930 #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
\r
3931 #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
\r
3932 #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
\r
3934 #define ADC_CCR_CKMODE_Pos (16U)
\r
3935 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
\r
3936 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
\r
3937 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
\r
3938 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
\r
3940 #define ADC_CCR_PRESC_Pos (18U)
\r
3941 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
\r
3942 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
\r
3943 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
\r
3944 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
\r
3945 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
\r
3946 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
\r
3948 #define ADC_CCR_VREFEN_Pos (22U)
\r
3949 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
\r
3950 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
\r
3951 #define ADC_CCR_TSEN_Pos (23U)
\r
3952 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
\r
3953 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
\r
3954 #define ADC_CCR_VBATEN_Pos (24U)
\r
3955 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
\r
3956 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
\r
3958 /******************** Bit definition for ADC_CDR register *******************/
\r
3959 #define ADC_CDR_RDATA_MST_Pos (0U)
\r
3960 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
\r
3961 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
\r
3963 #define ADC_CDR_RDATA_SLV_Pos (16U)
\r
3964 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
\r
3965 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
\r
3967 /******************** Bit definition for ADC_CDR2 register ******************/
\r
3968 #define ADC_CDR2_RDATA_ALT_Pos (0U)
\r
3969 #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
\r
3970 #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
\r
3972 /******************************************************************************/
\r
3976 /******************************************************************************/
\r
3977 /******************* Bit definition for VREFBUF_CSR register ****************/
\r
3978 #define VREFBUF_CSR_ENVR_Pos (0U)
\r
3979 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
\r
3980 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
\r
3981 #define VREFBUF_CSR_HIZ_Pos (1U)
\r
3982 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
\r
3983 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
\r
3984 #define VREFBUF_CSR_VRR_Pos (3U)
\r
3985 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
\r
3986 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
\r
3987 #define VREFBUF_CSR_VRS_Pos (4U)
\r
3988 #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
\r
3989 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
\r
3991 #define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
\r
3992 #define VREFBUF_CSR_VRS_OUT2_Pos (4U)
\r
3993 #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
\r
3994 #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
\r
3995 #define VREFBUF_CSR_VRS_OUT3_Pos (5U)
\r
3996 #define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
\r
3997 #define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
\r
3998 #define VREFBUF_CSR_VRS_OUT4_Pos (4U)
\r
3999 #define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
\r
4000 #define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
\r
4002 /******************* Bit definition for VREFBUF_CCR register ****************/
\r
4003 #define VREFBUF_CCR_TRIM_Pos (0U)
\r
4004 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
\r
4005 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
\r
4007 /******************************************************************************/
\r
4009 /* Flexible Datarate Controller Area Network */
\r
4011 /******************************************************************************/
\r
4012 /*!<FDCAN control and status registers */
\r
4013 /***************** Bit definition for FDCAN_CREL register *******************/
\r
4014 #define FDCAN_CREL_DAY_Pos (0U)
\r
4015 #define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
\r
4016 #define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
\r
4017 #define FDCAN_CREL_MON_Pos (8U)
\r
4018 #define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
\r
4019 #define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
\r
4020 #define FDCAN_CREL_YEAR_Pos (16U)
\r
4021 #define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
\r
4022 #define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
\r
4023 #define FDCAN_CREL_SUBSTEP_Pos (20U)
\r
4024 #define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
\r
4025 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
\r
4026 #define FDCAN_CREL_STEP_Pos (24U)
\r
4027 #define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
\r
4028 #define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
\r
4029 #define FDCAN_CREL_REL_Pos (28U)
\r
4030 #define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
\r
4031 #define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
\r
4033 /***************** Bit definition for FDCAN_ENDN register *******************/
\r
4034 #define FDCAN_ENDN_ETV_Pos (0U)
\r
4035 #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
\r
4036 #define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
\r
4038 /***************** Bit definition for FDCAN_DBTP register *******************/
\r
4039 #define FDCAN_DBTP_DSJW_Pos (0U)
\r
4040 #define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
\r
4041 #define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
\r
4042 #define FDCAN_DBTP_DTSEG2_Pos (4U)
\r
4043 #define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
\r
4044 #define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
\r
4045 #define FDCAN_DBTP_DTSEG1_Pos (8U)
\r
4046 #define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
\r
4047 #define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
\r
4048 #define FDCAN_DBTP_DBRP_Pos (16U)
\r
4049 #define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
\r
4050 #define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
\r
4051 #define FDCAN_DBTP_TDC_Pos (23U)
\r
4052 #define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
\r
4053 #define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
\r
4055 /***************** Bit definition for FDCAN_TEST register *******************/
\r
4056 #define FDCAN_TEST_LBCK_Pos (4U)
\r
4057 #define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
\r
4058 #define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
\r
4059 #define FDCAN_TEST_TX_Pos (5U)
\r
4060 #define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
\r
4061 #define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
\r
4062 #define FDCAN_TEST_RX_Pos (7U)
\r
4063 #define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
\r
4064 #define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
\r
4066 /***************** Bit definition for FDCAN_RWD register ********************/
\r
4067 #define FDCAN_RWD_WDC_Pos (0U)
\r
4068 #define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
\r
4069 #define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
\r
4070 #define FDCAN_RWD_WDV_Pos (8U)
\r
4071 #define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
\r
4072 #define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
\r
4074 /***************** Bit definition for FDCAN_CCCR register ********************/
\r
4075 #define FDCAN_CCCR_INIT_Pos (0U)
\r
4076 #define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
\r
4077 #define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
\r
4078 #define FDCAN_CCCR_CCE_Pos (1U)
\r
4079 #define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
\r
4080 #define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
\r
4081 #define FDCAN_CCCR_ASM_Pos (2U)
\r
4082 #define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
\r
4083 #define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
\r
4084 #define FDCAN_CCCR_CSA_Pos (3U)
\r
4085 #define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
\r
4086 #define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
\r
4087 #define FDCAN_CCCR_CSR_Pos (4U)
\r
4088 #define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
\r
4089 #define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
\r
4090 #define FDCAN_CCCR_MON_Pos (5U)
\r
4091 #define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
\r
4092 #define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
\r
4093 #define FDCAN_CCCR_DAR_Pos (6U)
\r
4094 #define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
\r
4095 #define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
\r
4096 #define FDCAN_CCCR_TEST_Pos (7U)
\r
4097 #define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
\r
4098 #define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
\r
4099 #define FDCAN_CCCR_FDOE_Pos (8U)
\r
4100 #define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
\r
4101 #define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
\r
4102 #define FDCAN_CCCR_BRSE_Pos (9U)
\r
4103 #define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
\r
4104 #define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
\r
4105 #define FDCAN_CCCR_PXHD_Pos (12U)
\r
4106 #define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
\r
4107 #define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
\r
4108 #define FDCAN_CCCR_EFBI_Pos (13U)
\r
4109 #define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
\r
4110 #define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
\r
4111 #define FDCAN_CCCR_TXP_Pos (14U)
\r
4112 #define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
\r
4113 #define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
\r
4114 #define FDCAN_CCCR_NISO_Pos (15U)
\r
4115 #define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
\r
4116 #define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
\r
4118 /***************** Bit definition for FDCAN_NBTP register ********************/
\r
4119 #define FDCAN_NBTP_NTSEG2_Pos (0U)
\r
4120 #define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
\r
4121 #define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
\r
4122 #define FDCAN_NBTP_NTSEG1_Pos (8U)
\r
4123 #define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
\r
4124 #define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
\r
4125 #define FDCAN_NBTP_NBRP_Pos (16U)
\r
4126 #define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
\r
4127 #define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
\r
4128 #define FDCAN_NBTP_NSJW_Pos (25U)
\r
4129 #define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
\r
4130 #define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
\r
4132 /***************** Bit definition for FDCAN_TSCC register ********************/
\r
4133 #define FDCAN_TSCC_TSS_Pos (0U)
\r
4134 #define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
\r
4135 #define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
\r
4136 #define FDCAN_TSCC_TCP_Pos (16U)
\r
4137 #define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
\r
4138 #define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
\r
4140 /***************** Bit definition for FDCAN_TSCV register ********************/
\r
4141 #define FDCAN_TSCV_TSC_Pos (0U)
\r
4142 #define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
\r
4143 #define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
\r
4145 /***************** Bit definition for FDCAN_TOCC register ********************/
\r
4146 #define FDCAN_TOCC_ETOC_Pos (0U)
\r
4147 #define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
\r
4148 #define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
\r
4149 #define FDCAN_TOCC_TOS_Pos (1U)
\r
4150 #define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
\r
4151 #define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
\r
4152 #define FDCAN_TOCC_TOP_Pos (16U)
\r
4153 #define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
\r
4154 #define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
\r
4156 /***************** Bit definition for FDCAN_TOCV register ********************/
\r
4157 #define FDCAN_TOCV_TOC_Pos (0U)
\r
4158 #define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
\r
4159 #define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
\r
4161 /***************** Bit definition for FDCAN_ECR register *********************/
\r
4162 #define FDCAN_ECR_TEC_Pos (0U)
\r
4163 #define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
\r
4164 #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
\r
4165 #define FDCAN_ECR_REC_Pos (8U)
\r
4166 #define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
\r
4167 #define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
\r
4168 #define FDCAN_ECR_RP_Pos (15U)
\r
4169 #define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
\r
4170 #define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
\r
4171 #define FDCAN_ECR_CEL_Pos (16U)
\r
4172 #define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
\r
4173 #define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
\r
4175 /***************** Bit definition for FDCAN_PSR register *********************/
\r
4176 #define FDCAN_PSR_LEC_Pos (0U)
\r
4177 #define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
\r
4178 #define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
\r
4179 #define FDCAN_PSR_ACT_Pos (3U)
\r
4180 #define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
\r
4181 #define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
\r
4182 #define FDCAN_PSR_EP_Pos (5U)
\r
4183 #define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
\r
4184 #define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
\r
4185 #define FDCAN_PSR_EW_Pos (6U)
\r
4186 #define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
\r
4187 #define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
\r
4188 #define FDCAN_PSR_BO_Pos (7U)
\r
4189 #define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
\r
4190 #define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
\r
4191 #define FDCAN_PSR_DLEC_Pos (8U)
\r
4192 #define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
\r
4193 #define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
\r
4194 #define FDCAN_PSR_RESI_Pos (11U)
\r
4195 #define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
\r
4196 #define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
\r
4197 #define FDCAN_PSR_RBRS_Pos (12U)
\r
4198 #define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
\r
4199 #define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
\r
4200 #define FDCAN_PSR_REDL_Pos (13U)
\r
4201 #define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
\r
4202 #define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
\r
4203 #define FDCAN_PSR_PXE_Pos (14U)
\r
4204 #define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
\r
4205 #define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
\r
4206 #define FDCAN_PSR_TDCV_Pos (16U)
\r
4207 #define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
\r
4208 #define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
\r
4210 /***************** Bit definition for FDCAN_TDCR register ********************/
\r
4211 #define FDCAN_TDCR_TDCF_Pos (0U)
\r
4212 #define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
\r
4213 #define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
\r
4214 #define FDCAN_TDCR_TDCO_Pos (8U)
\r
4215 #define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
\r
4216 #define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
\r
4218 /***************** Bit definition for FDCAN_IR register **********************/
\r
4219 #define FDCAN_IR_RF0N_Pos (0U)
\r
4220 #define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
\r
4221 #define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
\r
4222 #define FDCAN_IR_RF0W_Pos (1U)
\r
4223 #define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
\r
4224 #define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
\r
4225 #define FDCAN_IR_RF0F_Pos (2U)
\r
4226 #define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
\r
4227 #define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
\r
4228 #define FDCAN_IR_RF0L_Pos (3U)
\r
4229 #define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
\r
4230 #define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
\r
4231 #define FDCAN_IR_RF1N_Pos (4U)
\r
4232 #define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
\r
4233 #define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
\r
4234 #define FDCAN_IR_RF1W_Pos (5U)
\r
4235 #define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
\r
4236 #define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
\r
4237 #define FDCAN_IR_RF1F_Pos (6U)
\r
4238 #define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
\r
4239 #define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
\r
4240 #define FDCAN_IR_RF1L_Pos (7U)
\r
4241 #define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
\r
4242 #define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
\r
4243 #define FDCAN_IR_HPM_Pos (8U)
\r
4244 #define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
\r
4245 #define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
\r
4246 #define FDCAN_IR_TC_Pos (9U)
\r
4247 #define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
\r
4248 #define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
\r
4249 #define FDCAN_IR_TCF_Pos (10U)
\r
4250 #define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
\r
4251 #define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
\r
4252 #define FDCAN_IR_TFE_Pos (11U)
\r
4253 #define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
\r
4254 #define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
\r
4255 #define FDCAN_IR_TEFN_Pos (12U)
\r
4256 #define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
\r
4257 #define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
\r
4258 #define FDCAN_IR_TEFW_Pos (13U)
\r
4259 #define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
\r
4260 #define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
\r
4261 #define FDCAN_IR_TEFF_Pos (14U)
\r
4262 #define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
\r
4263 #define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
\r
4264 #define FDCAN_IR_TEFL_Pos (15U)
\r
4265 #define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
\r
4266 #define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
\r
4267 #define FDCAN_IR_TSW_Pos (16U)
\r
4268 #define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
\r
4269 #define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
\r
4270 #define FDCAN_IR_MRAF_Pos (17U)
\r
4271 #define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
\r
4272 #define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
\r
4273 #define FDCAN_IR_TOO_Pos (18U)
\r
4274 #define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
\r
4275 #define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
\r
4276 #define FDCAN_IR_DRX_Pos (19U)
\r
4277 #define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
\r
4278 #define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
\r
4279 #define FDCAN_IR_ELO_Pos (22U)
\r
4280 #define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
\r
4281 #define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
\r
4282 #define FDCAN_IR_EP_Pos (23U)
\r
4283 #define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
\r
4284 #define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
\r
4285 #define FDCAN_IR_EW_Pos (24U)
\r
4286 #define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
\r
4287 #define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
\r
4288 #define FDCAN_IR_BO_Pos (25U)
\r
4289 #define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
\r
4290 #define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
\r
4291 #define FDCAN_IR_WDI_Pos (26U)
\r
4292 #define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
\r
4293 #define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
\r
4294 #define FDCAN_IR_PEA_Pos (27U)
\r
4295 #define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
\r
4296 #define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
\r
4297 #define FDCAN_IR_PED_Pos (28U)
\r
4298 #define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
\r
4299 #define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
\r
4300 #define FDCAN_IR_ARA_Pos (29U)
\r
4301 #define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
\r
4302 #define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
\r
4304 /***************** Bit definition for FDCAN_IE register **********************/
\r
4305 #define FDCAN_IE_RF0NE_Pos (0U)
\r
4306 #define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
\r
4307 #define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
\r
4308 #define FDCAN_IE_RF0WE_Pos (1U)
\r
4309 #define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
\r
4310 #define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
\r
4311 #define FDCAN_IE_RF0FE_Pos (2U)
\r
4312 #define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
\r
4313 #define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
\r
4314 #define FDCAN_IE_RF0LE_Pos (3U)
\r
4315 #define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
\r
4316 #define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
\r
4317 #define FDCAN_IE_RF1NE_Pos (4U)
\r
4318 #define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
\r
4319 #define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
\r
4320 #define FDCAN_IE_RF1WE_Pos (5U)
\r
4321 #define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
\r
4322 #define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
\r
4323 #define FDCAN_IE_RF1FE_Pos (6U)
\r
4324 #define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
\r
4325 #define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
\r
4326 #define FDCAN_IE_RF1LE_Pos (7U)
\r
4327 #define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
\r
4328 #define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
\r
4329 #define FDCAN_IE_HPME_Pos (8U)
\r
4330 #define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
\r
4331 #define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
\r
4332 #define FDCAN_IE_TCE_Pos (9U)
\r
4333 #define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
\r
4334 #define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
\r
4335 #define FDCAN_IE_TCFE_Pos (10U)
\r
4336 #define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
\r
4337 #define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
\r
4338 #define FDCAN_IE_TFEE_Pos (11U)
\r
4339 #define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
\r
4340 #define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
\r
4341 #define FDCAN_IE_TEFNE_Pos (12U)
\r
4342 #define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
\r
4343 #define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
\r
4344 #define FDCAN_IE_TEFWE_Pos (13U)
\r
4345 #define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
\r
4346 #define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
\r
4347 #define FDCAN_IE_TEFFE_Pos (14U)
\r
4348 #define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
\r
4349 #define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
\r
4350 #define FDCAN_IE_TEFLE_Pos (15U)
\r
4351 #define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
\r
4352 #define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
\r
4353 #define FDCAN_IE_TSWE_Pos (16U)
\r
4354 #define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
\r
4355 #define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
\r
4356 #define FDCAN_IE_MRAFE_Pos (17U)
\r
4357 #define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
\r
4358 #define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
\r
4359 #define FDCAN_IE_TOOE_Pos (18U)
\r
4360 #define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
\r
4361 #define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
\r
4362 #define FDCAN_IE_DRXE_Pos (19U)
\r
4363 #define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
\r
4364 #define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
\r
4365 #define FDCAN_IE_BECE_Pos (20U)
\r
4366 #define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
\r
4367 #define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
\r
4368 #define FDCAN_IE_BEUE_Pos (21U)
\r
4369 #define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
\r
4370 #define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
\r
4371 #define FDCAN_IE_ELOE_Pos (22U)
\r
4372 #define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
\r
4373 #define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
\r
4374 #define FDCAN_IE_EPE_Pos (23U)
\r
4375 #define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
\r
4376 #define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
\r
4377 #define FDCAN_IE_EWE_Pos (24U)
\r
4378 #define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
\r
4379 #define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
\r
4380 #define FDCAN_IE_BOE_Pos (25U)
\r
4381 #define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
\r
4382 #define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
\r
4383 #define FDCAN_IE_WDIE_Pos (26U)
\r
4384 #define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
\r
4385 #define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
\r
4386 #define FDCAN_IE_PEAE_Pos (27U)
\r
4387 #define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
\r
4388 #define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
\r
4389 #define FDCAN_IE_PEDE_Pos (28U)
\r
4390 #define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
\r
4391 #define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
\r
4392 #define FDCAN_IE_ARAE_Pos (29U)
\r
4393 #define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
\r
4394 #define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
\r
4396 /***************** Bit definition for FDCAN_ILS register **********************/
\r
4397 #define FDCAN_ILS_RF0NL_Pos (0U)
\r
4398 #define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
\r
4399 #define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
\r
4400 #define FDCAN_ILS_RF0WL_Pos (1U)
\r
4401 #define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
\r
4402 #define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
\r
4403 #define FDCAN_ILS_RF0FL_Pos (2U)
\r
4404 #define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
\r
4405 #define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
\r
4406 #define FDCAN_ILS_RF0LL_Pos (3U)
\r
4407 #define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
\r
4408 #define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
\r
4409 #define FDCAN_ILS_RF1NL_Pos (4U)
\r
4410 #define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
\r
4411 #define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
\r
4412 #define FDCAN_ILS_RF1WL_Pos (5U)
\r
4413 #define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
\r
4414 #define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
\r
4415 #define FDCAN_ILS_RF1FL_Pos (6U)
\r
4416 #define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
\r
4417 #define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
\r
4418 #define FDCAN_ILS_RF1LL_Pos (7U)
\r
4419 #define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
\r
4420 #define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
\r
4421 #define FDCAN_ILS_HPML_Pos (8U)
\r
4422 #define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
\r
4423 #define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
\r
4424 #define FDCAN_ILS_TCL_Pos (9U)
\r
4425 #define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
\r
4426 #define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
\r
4427 #define FDCAN_ILS_TCFL_Pos (10U)
\r
4428 #define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
\r
4429 #define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
\r
4430 #define FDCAN_ILS_TFEL_Pos (11U)
\r
4431 #define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
\r
4432 #define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
\r
4433 #define FDCAN_ILS_TEFNL_Pos (12U)
\r
4434 #define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
\r
4435 #define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
\r
4436 #define FDCAN_ILS_TEFWL_Pos (13U)
\r
4437 #define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
\r
4438 #define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
\r
4439 #define FDCAN_ILS_TEFFL_Pos (14U)
\r
4440 #define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
\r
4441 #define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
\r
4442 #define FDCAN_ILS_TEFLL_Pos (15U)
\r
4443 #define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
\r
4444 #define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
\r
4445 #define FDCAN_ILS_TSWL_Pos (16U)
\r
4446 #define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
\r
4447 #define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
\r
4448 #define FDCAN_ILS_MRAFE_Pos (17U)
\r
4449 #define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
\r
4450 #define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
\r
4451 #define FDCAN_ILS_TOOE_Pos (18U)
\r
4452 #define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
\r
4453 #define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
\r
4454 #define FDCAN_ILS_DRXE_Pos (19U)
\r
4455 #define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
\r
4456 #define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
\r
4457 #define FDCAN_ILS_BECE_Pos (20U)
\r
4458 #define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
\r
4459 #define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
\r
4460 #define FDCAN_ILS_BEUE_Pos (21U)
\r
4461 #define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
\r
4462 #define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
\r
4463 #define FDCAN_ILS_ELOE_Pos (22U)
\r
4464 #define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
\r
4465 #define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
\r
4466 #define FDCAN_ILS_EPE_Pos (23U)
\r
4467 #define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
\r
4468 #define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
\r
4469 #define FDCAN_ILS_EWE_Pos (24U)
\r
4470 #define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
\r
4471 #define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
\r
4472 #define FDCAN_ILS_BOE_Pos (25U)
\r
4473 #define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
\r
4474 #define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
\r
4475 #define FDCAN_ILS_WDIE_Pos (26U)
\r
4476 #define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
\r
4477 #define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
\r
4478 #define FDCAN_ILS_PEAE_Pos (27U)
\r
4479 #define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
\r
4480 #define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
\r
4481 #define FDCAN_ILS_PEDE_Pos (28U)
\r
4482 #define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
\r
4483 #define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
\r
4484 #define FDCAN_ILS_ARAE_Pos (29U)
\r
4485 #define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
\r
4486 #define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
\r
4488 /***************** Bit definition for FDCAN_ILE register **********************/
\r
4489 #define FDCAN_ILE_EINT0_Pos (0U)
\r
4490 #define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
\r
4491 #define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
\r
4492 #define FDCAN_ILE_EINT1_Pos (1U)
\r
4493 #define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
\r
4494 #define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
\r
4496 /***************** Bit definition for FDCAN_GFC register **********************/
\r
4497 #define FDCAN_GFC_RRFE_Pos (0U)
\r
4498 #define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
\r
4499 #define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
\r
4500 #define FDCAN_GFC_RRFS_Pos (1U)
\r
4501 #define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
\r
4502 #define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
\r
4503 #define FDCAN_GFC_ANFE_Pos (2U)
\r
4504 #define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
\r
4505 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
\r
4506 #define FDCAN_GFC_ANFS_Pos (4U)
\r
4507 #define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
\r
4508 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
\r
4510 /***************** Bit definition for FDCAN_SIDFC register ********************/
\r
4511 #define FDCAN_SIDFC_FLSSA_Pos (2U)
\r
4512 #define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
\r
4513 #define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
\r
4514 #define FDCAN_SIDFC_LSS_Pos (16U)
\r
4515 #define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
\r
4516 #define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
\r
4518 /***************** Bit definition for FDCAN_XIDFC register ********************/
\r
4519 #define FDCAN_XIDFC_FLESA_Pos (2U)
\r
4520 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
\r
4521 #define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
\r
4522 #define FDCAN_XIDFC_LSE_Pos (16U)
\r
4523 #define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
\r
4524 #define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
\r
4526 /***************** Bit definition for FDCAN_XIDAM register ********************/
\r
4527 #define FDCAN_XIDAM_EIDM_Pos (0U)
\r
4528 #define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
\r
4529 #define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
\r
4531 /***************** Bit definition for FDCAN_HPMS register *********************/
\r
4532 #define FDCAN_HPMS_BIDX_Pos (0U)
\r
4533 #define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
\r
4534 #define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
\r
4535 #define FDCAN_HPMS_MSI_Pos (6U)
\r
4536 #define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
\r
4537 #define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
\r
4538 #define FDCAN_HPMS_FIDX_Pos (8U)
\r
4539 #define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
\r
4540 #define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
\r
4541 #define FDCAN_HPMS_FLST_Pos (15U)
\r
4542 #define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
\r
4543 #define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
\r
4545 /***************** Bit definition for FDCAN_NDAT1 register ********************/
\r
4546 #define FDCAN_NDAT1_ND0_Pos (0U)
\r
4547 #define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
\r
4548 #define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
\r
4549 #define FDCAN_NDAT1_ND1_Pos (1U)
\r
4550 #define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
\r
4551 #define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
\r
4552 #define FDCAN_NDAT1_ND2_Pos (2U)
\r
4553 #define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
\r
4554 #define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
\r
4555 #define FDCAN_NDAT1_ND3_Pos (3U)
\r
4556 #define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
\r
4557 #define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
\r
4558 #define FDCAN_NDAT1_ND4_Pos (4U)
\r
4559 #define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
\r
4560 #define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
\r
4561 #define FDCAN_NDAT1_ND5_Pos (5U)
\r
4562 #define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
\r
4563 #define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
\r
4564 #define FDCAN_NDAT1_ND6_Pos (6U)
\r
4565 #define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
\r
4566 #define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
\r
4567 #define FDCAN_NDAT1_ND7_Pos (7U)
\r
4568 #define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
\r
4569 #define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
\r
4570 #define FDCAN_NDAT1_ND8_Pos (8U)
\r
4571 #define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
\r
4572 #define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
\r
4573 #define FDCAN_NDAT1_ND9_Pos (9U)
\r
4574 #define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
\r
4575 #define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
\r
4576 #define FDCAN_NDAT1_ND10_Pos (10U)
\r
4577 #define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
\r
4578 #define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
\r
4579 #define FDCAN_NDAT1_ND11_Pos (11U)
\r
4580 #define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
\r
4581 #define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
\r
4582 #define FDCAN_NDAT1_ND12_Pos (12U)
\r
4583 #define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
\r
4584 #define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
\r
4585 #define FDCAN_NDAT1_ND13_Pos (13U)
\r
4586 #define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
\r
4587 #define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
\r
4588 #define FDCAN_NDAT1_ND14_Pos (14U)
\r
4589 #define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
\r
4590 #define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
\r
4591 #define FDCAN_NDAT1_ND15_Pos (15U)
\r
4592 #define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
\r
4593 #define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
\r
4594 #define FDCAN_NDAT1_ND16_Pos (16U)
\r
4595 #define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
\r
4596 #define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
\r
4597 #define FDCAN_NDAT1_ND17_Pos (17U)
\r
4598 #define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
\r
4599 #define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
\r
4600 #define FDCAN_NDAT1_ND18_Pos (18U)
\r
4601 #define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
\r
4602 #define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
\r
4603 #define FDCAN_NDAT1_ND19_Pos (19U)
\r
4604 #define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
\r
4605 #define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
\r
4606 #define FDCAN_NDAT1_ND20_Pos (20U)
\r
4607 #define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
\r
4608 #define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
\r
4609 #define FDCAN_NDAT1_ND21_Pos (21U)
\r
4610 #define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
\r
4611 #define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
\r
4612 #define FDCAN_NDAT1_ND22_Pos (22U)
\r
4613 #define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
\r
4614 #define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
\r
4615 #define FDCAN_NDAT1_ND23_Pos (23U)
\r
4616 #define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
\r
4617 #define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
\r
4618 #define FDCAN_NDAT1_ND24_Pos (24U)
\r
4619 #define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
\r
4620 #define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
\r
4621 #define FDCAN_NDAT1_ND25_Pos (25U)
\r
4622 #define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
\r
4623 #define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
\r
4624 #define FDCAN_NDAT1_ND26_Pos (26U)
\r
4625 #define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
\r
4626 #define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
\r
4627 #define FDCAN_NDAT1_ND27_Pos (27U)
\r
4628 #define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
\r
4629 #define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
\r
4630 #define FDCAN_NDAT1_ND28_Pos (28U)
\r
4631 #define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
\r
4632 #define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
\r
4633 #define FDCAN_NDAT1_ND29_Pos (29U)
\r
4634 #define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
\r
4635 #define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
\r
4636 #define FDCAN_NDAT1_ND30_Pos (30U)
\r
4637 #define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
\r
4638 #define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
\r
4639 #define FDCAN_NDAT1_ND31_Pos (31U)
\r
4640 #define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
\r
4641 #define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
\r
4643 /***************** Bit definition for FDCAN_NDAT2 register ********************/
\r
4644 #define FDCAN_NDAT2_ND32_Pos (0U)
\r
4645 #define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
\r
4646 #define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
\r
4647 #define FDCAN_NDAT2_ND33_Pos (1U)
\r
4648 #define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
\r
4649 #define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
\r
4650 #define FDCAN_NDAT2_ND34_Pos (2U)
\r
4651 #define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
\r
4652 #define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
\r
4653 #define FDCAN_NDAT2_ND35_Pos (3U)
\r
4654 #define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
\r
4655 #define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
\r
4656 #define FDCAN_NDAT2_ND36_Pos (4U)
\r
4657 #define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
\r
4658 #define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
\r
4659 #define FDCAN_NDAT2_ND37_Pos (5U)
\r
4660 #define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
\r
4661 #define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
\r
4662 #define FDCAN_NDAT2_ND38_Pos (6U)
\r
4663 #define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
\r
4664 #define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
\r
4665 #define FDCAN_NDAT2_ND39_Pos (7U)
\r
4666 #define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
\r
4667 #define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
\r
4668 #define FDCAN_NDAT2_ND40_Pos (8U)
\r
4669 #define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
\r
4670 #define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
\r
4671 #define FDCAN_NDAT2_ND41_Pos (9U)
\r
4672 #define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
\r
4673 #define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
\r
4674 #define FDCAN_NDAT2_ND42_Pos (10U)
\r
4675 #define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
\r
4676 #define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
\r
4677 #define FDCAN_NDAT2_ND43_Pos (11U)
\r
4678 #define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
\r
4679 #define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
\r
4680 #define FDCAN_NDAT2_ND44_Pos (12U)
\r
4681 #define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
\r
4682 #define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
\r
4683 #define FDCAN_NDAT2_ND45_Pos (13U)
\r
4684 #define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
\r
4685 #define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
\r
4686 #define FDCAN_NDAT2_ND46_Pos (14U)
\r
4687 #define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
\r
4688 #define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
\r
4689 #define FDCAN_NDAT2_ND47_Pos (15U)
\r
4690 #define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
\r
4691 #define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
\r
4692 #define FDCAN_NDAT2_ND48_Pos (16U)
\r
4693 #define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
\r
4694 #define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
\r
4695 #define FDCAN_NDAT2_ND49_Pos (17U)
\r
4696 #define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
\r
4697 #define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
\r
4698 #define FDCAN_NDAT2_ND50_Pos (18U)
\r
4699 #define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
\r
4700 #define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
\r
4701 #define FDCAN_NDAT2_ND51_Pos (19U)
\r
4702 #define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
\r
4703 #define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
\r
4704 #define FDCAN_NDAT2_ND52_Pos (20U)
\r
4705 #define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
\r
4706 #define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
\r
4707 #define FDCAN_NDAT2_ND53_Pos (21U)
\r
4708 #define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
\r
4709 #define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
\r
4710 #define FDCAN_NDAT2_ND54_Pos (22U)
\r
4711 #define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
\r
4712 #define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
\r
4713 #define FDCAN_NDAT2_ND55_Pos (23U)
\r
4714 #define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
\r
4715 #define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
\r
4716 #define FDCAN_NDAT2_ND56_Pos (24U)
\r
4717 #define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
\r
4718 #define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
\r
4719 #define FDCAN_NDAT2_ND57_Pos (25U)
\r
4720 #define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
\r
4721 #define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
\r
4722 #define FDCAN_NDAT2_ND58_Pos (26U)
\r
4723 #define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
\r
4724 #define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
\r
4725 #define FDCAN_NDAT2_ND59_Pos (27U)
\r
4726 #define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
\r
4727 #define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
\r
4728 #define FDCAN_NDAT2_ND60_Pos (28U)
\r
4729 #define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
\r
4730 #define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
\r
4731 #define FDCAN_NDAT2_ND61_Pos (29U)
\r
4732 #define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
\r
4733 #define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
\r
4734 #define FDCAN_NDAT2_ND62_Pos (30U)
\r
4735 #define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
\r
4736 #define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
\r
4737 #define FDCAN_NDAT2_ND63_Pos (31U)
\r
4738 #define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
\r
4739 #define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
\r
4741 /***************** Bit definition for FDCAN_RXF0C register ********************/
\r
4742 #define FDCAN_RXF0C_F0SA_Pos (2U)
\r
4743 #define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
\r
4744 #define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
\r
4745 #define FDCAN_RXF0C_F0S_Pos (16U)
\r
4746 #define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
\r
4747 #define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
\r
4748 #define FDCAN_RXF0C_F0WM_Pos (24U)
\r
4749 #define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
\r
4750 #define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
\r
4751 #define FDCAN_RXF0C_F0OM_Pos (31U)
\r
4752 #define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
\r
4753 #define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
\r
4755 /***************** Bit definition for FDCAN_RXF0S register ********************/
\r
4756 #define FDCAN_RXF0S_F0FL_Pos (0U)
\r
4757 #define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
\r
4758 #define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
\r
4759 #define FDCAN_RXF0S_F0GI_Pos (8U)
\r
4760 #define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
\r
4761 #define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
\r
4762 #define FDCAN_RXF0S_F0PI_Pos (16U)
\r
4763 #define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
\r
4764 #define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
\r
4765 #define FDCAN_RXF0S_F0F_Pos (24U)
\r
4766 #define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
\r
4767 #define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
\r
4768 #define FDCAN_RXF0S_RF0L_Pos (25U)
\r
4769 #define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
\r
4770 #define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
\r
4772 /***************** Bit definition for FDCAN_RXF0A register ********************/
\r
4773 #define FDCAN_RXF0A_F0AI_Pos (0U)
\r
4774 #define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
\r
4775 #define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
\r
4777 /***************** Bit definition for FDCAN_RXBC register ********************/
\r
4778 #define FDCAN_RXBC_RBSA_Pos (2U)
\r
4779 #define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
\r
4780 #define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
\r
4782 /***************** Bit definition for FDCAN_RXF1C register ********************/
\r
4783 #define FDCAN_RXF1C_F1SA_Pos (2U)
\r
4784 #define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
\r
4785 #define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
\r
4786 #define FDCAN_RXF1C_F1S_Pos (16U)
\r
4787 #define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
\r
4788 #define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
\r
4789 #define FDCAN_RXF1C_F1WM_Pos (24U)
\r
4790 #define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
\r
4791 #define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
\r
4792 #define FDCAN_RXF1C_F1OM_Pos (31U)
\r
4793 #define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
\r
4794 #define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
\r
4796 /***************** Bit definition for FDCAN_RXF1S register ********************/
\r
4797 #define FDCAN_RXF1S_F1FL_Pos (0U)
\r
4798 #define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
\r
4799 #define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
\r
4800 #define FDCAN_RXF1S_F1GI_Pos (8U)
\r
4801 #define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
\r
4802 #define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
\r
4803 #define FDCAN_RXF1S_F1PI_Pos (16U)
\r
4804 #define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
\r
4805 #define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
\r
4806 #define FDCAN_RXF1S_F1F_Pos (24U)
\r
4807 #define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
\r
4808 #define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
\r
4809 #define FDCAN_RXF1S_RF1L_Pos (25U)
\r
4810 #define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
\r
4811 #define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
\r
4813 /***************** Bit definition for FDCAN_RXF1A register ********************/
\r
4814 #define FDCAN_RXF1A_F1AI_Pos (0U)
\r
4815 #define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
\r
4816 #define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
\r
4818 /***************** Bit definition for FDCAN_RXESC register ********************/
\r
4819 #define FDCAN_RXESC_F0DS_Pos (0U)
\r
4820 #define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
\r
4821 #define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
\r
4822 #define FDCAN_RXESC_F1DS_Pos (4U)
\r
4823 #define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
\r
4824 #define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
\r
4825 #define FDCAN_RXESC_RBDS_Pos (8U)
\r
4826 #define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
\r
4827 #define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
\r
4829 /***************** Bit definition for FDCAN_TXBC register *********************/
\r
4830 #define FDCAN_TXBC_TBSA_Pos (2U)
\r
4831 #define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
\r
4832 #define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
\r
4833 #define FDCAN_TXBC_NDTB_Pos (16U)
\r
4834 #define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
\r
4835 #define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
\r
4836 #define FDCAN_TXBC_TFQS_Pos (24U)
\r
4837 #define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
\r
4838 #define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
\r
4839 #define FDCAN_TXBC_TFQM_Pos (30U)
\r
4840 #define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
\r
4841 #define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
\r
4843 /***************** Bit definition for FDCAN_TXFQS register *********************/
\r
4844 #define FDCAN_TXFQS_TFFL_Pos (0U)
\r
4845 #define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
\r
4846 #define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
\r
4847 #define FDCAN_TXFQS_TFGI_Pos (8U)
\r
4848 #define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
\r
4849 #define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
\r
4850 #define FDCAN_TXFQS_TFQPI_Pos (16U)
\r
4851 #define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
\r
4852 #define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
\r
4853 #define FDCAN_TXFQS_TFQF_Pos (21U)
\r
4854 #define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
\r
4855 #define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
\r
4857 /***************** Bit definition for FDCAN_TXESC register *********************/
\r
4858 #define FDCAN_TXESC_TBDS_Pos (0U)
\r
4859 #define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
\r
4860 #define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
\r
4862 /***************** Bit definition for FDCAN_TXBRP register *********************/
\r
4863 #define FDCAN_TXBRP_TRP_Pos (0U)
\r
4864 #define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
\r
4865 #define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
\r
4867 /***************** Bit definition for FDCAN_TXBAR register *********************/
\r
4868 #define FDCAN_TXBAR_AR_Pos (0U)
\r
4869 #define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
\r
4870 #define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
\r
4872 /***************** Bit definition for FDCAN_TXBCR register *********************/
\r
4873 #define FDCAN_TXBCR_CR_Pos (0U)
\r
4874 #define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
\r
4875 #define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
\r
4877 /***************** Bit definition for FDCAN_TXBTO register *********************/
\r
4878 #define FDCAN_TXBTO_TO_Pos (0U)
\r
4879 #define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
\r
4880 #define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
\r
4882 /***************** Bit definition for FDCAN_TXBCF register *********************/
\r
4883 #define FDCAN_TXBCF_CF_Pos (0U)
\r
4884 #define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
\r
4885 #define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
\r
4887 /***************** Bit definition for FDCAN_TXBTIE register ********************/
\r
4888 #define FDCAN_TXBTIE_TIE_Pos (0U)
\r
4889 #define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
\r
4890 #define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
\r
4892 /***************** Bit definition for FDCAN_ TXBCIE register *******************/
\r
4893 #define FDCAN_TXBCIE_CFIE_Pos (0U)
\r
4894 #define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
\r
4895 #define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
\r
4897 /***************** Bit definition for FDCAN_TXEFC register *********************/
\r
4898 #define FDCAN_TXEFC_EFSA_Pos (2U)
\r
4899 #define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
\r
4900 #define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
\r
4901 #define FDCAN_TXEFC_EFS_Pos (16U)
\r
4902 #define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
\r
4903 #define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
\r
4904 #define FDCAN_TXEFC_EFWM_Pos (24U)
\r
4905 #define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
\r
4906 #define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
\r
4908 /***************** Bit definition for FDCAN_TXEFS register *********************/
\r
4909 #define FDCAN_TXEFS_EFFL_Pos (0U)
\r
4910 #define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
\r
4911 #define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
\r
4912 #define FDCAN_TXEFS_EFGI_Pos (8U)
\r
4913 #define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
\r
4914 #define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
\r
4915 #define FDCAN_TXEFS_EFPI_Pos (16U)
\r
4916 #define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
\r
4917 #define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
\r
4918 #define FDCAN_TXEFS_EFF_Pos (24U)
\r
4919 #define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
\r
4920 #define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
\r
4921 #define FDCAN_TXEFS_TEFL_Pos (25U)
\r
4922 #define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
\r
4923 #define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
\r
4925 /***************** Bit definition for FDCAN_TXEFA register *********************/
\r
4926 #define FDCAN_TXEFA_EFAI_Pos (0U)
\r
4927 #define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
\r
4928 #define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
\r
4930 /***************** Bit definition for FDCAN_TTTMC register *********************/
\r
4931 #define FDCAN_TTTMC_TMSA_Pos (2U)
\r
4932 #define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
\r
4933 #define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
\r
4934 #define FDCAN_TTTMC_TME_Pos (16U)
\r
4935 #define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
\r
4936 #define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
\r
4938 /***************** Bit definition for FDCAN_TTRMC register *********************/
\r
4939 #define FDCAN_TTRMC_RID_Pos (0U)
\r
4940 #define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
\r
4941 #define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
\r
4942 #define FDCAN_TTRMC_XTD_Pos (30U)
\r
4943 #define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
\r
4944 #define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
\r
4945 #define FDCAN_TTRMC_RMPS_Pos (31U)
\r
4946 #define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
\r
4947 #define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
\r
4949 /***************** Bit definition for FDCAN_TTOCF register *********************/
\r
4950 #define FDCAN_TTOCF_OM_Pos (0U)
\r
4951 #define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
\r
4952 #define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
\r
4953 #define FDCAN_TTOCF_GEN_Pos (3U)
\r
4954 #define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
\r
4955 #define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
\r
4956 #define FDCAN_TTOCF_TM_Pos (4U)
\r
4957 #define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
\r
4958 #define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
\r
4959 #define FDCAN_TTOCF_LDSDL_Pos (5U)
\r
4960 #define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
\r
4961 #define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
\r
4962 #define FDCAN_TTOCF_IRTO_Pos (8U)
\r
4963 #define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
\r
4964 #define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
\r
4965 #define FDCAN_TTOCF_EECS_Pos (15U)
\r
4966 #define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
\r
4967 #define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
\r
4968 #define FDCAN_TTOCF_AWL_Pos (16U)
\r
4969 #define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
\r
4970 #define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
\r
4971 #define FDCAN_TTOCF_EGTF_Pos (24U)
\r
4972 #define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
\r
4973 #define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
\r
4974 #define FDCAN_TTOCF_ECC_Pos (25U)
\r
4975 #define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
\r
4976 #define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
\r
4977 #define FDCAN_TTOCF_EVTP_Pos (26U)
\r
4978 #define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
\r
4979 #define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
\r
4981 /***************** Bit definition for FDCAN_TTMLM register *********************/
\r
4982 #define FDCAN_TTMLM_CCM_Pos (0U)
\r
4983 #define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
\r
4984 #define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
\r
4985 #define FDCAN_TTMLM_CSS_Pos (6U)
\r
4986 #define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
\r
4987 #define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
\r
4988 #define FDCAN_TTMLM_TXEW_Pos (8U)
\r
4989 #define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
\r
4990 #define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
\r
4991 #define FDCAN_TTMLM_ENTT_Pos (16U)
\r
4992 #define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
\r
4993 #define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
\r
4995 /***************** Bit definition for FDCAN_TURCF register *********************/
\r
4996 #define FDCAN_TURCF_NCL_Pos (0U)
\r
4997 #define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
\r
4998 #define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
\r
4999 #define FDCAN_TURCF_DC_Pos (16U)
\r
5000 #define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
\r
5001 #define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
\r
5002 #define FDCAN_TURCF_ELT_Pos (31U)
\r
5003 #define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
\r
5004 #define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
\r
5006 /***************** Bit definition for FDCAN_TTOCN register ********************/
\r
5007 #define FDCAN_TTOCN_SGT_Pos (0U)
\r
5008 #define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
\r
5009 #define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
\r
5010 #define FDCAN_TTOCN_ECS_Pos (1U)
\r
5011 #define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
\r
5012 #define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
\r
5013 #define FDCAN_TTOCN_SWP_Pos (2U)
\r
5014 #define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
\r
5015 #define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
\r
5016 #define FDCAN_TTOCN_SWS_Pos (3U)
\r
5017 #define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
\r
5018 #define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
\r
5019 #define FDCAN_TTOCN_RTIE_Pos (5U)
\r
5020 #define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
\r
5021 #define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
\r
5022 #define FDCAN_TTOCN_TMC_Pos (6U)
\r
5023 #define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
\r
5024 #define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
\r
5025 #define FDCAN_TTOCN_TTIE_Pos (8U)
\r
5026 #define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
\r
5027 #define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
\r
5028 #define FDCAN_TTOCN_GCS_Pos (9U)
\r
5029 #define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
\r
5030 #define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
\r
5031 #define FDCAN_TTOCN_FGP_Pos (10U)
\r
5032 #define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
\r
5033 #define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
\r
5034 #define FDCAN_TTOCN_TMG_Pos (11U)
\r
5035 #define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
\r
5036 #define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
\r
5037 #define FDCAN_TTOCN_NIG_Pos (12U)
\r
5038 #define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
\r
5039 #define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
\r
5040 #define FDCAN_TTOCN_ESCN_Pos (13U)
\r
5041 #define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
\r
5042 #define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
\r
5043 #define FDCAN_TTOCN_LCKC_Pos (15U)
\r
5044 #define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
\r
5045 #define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
\r
5047 /***************** Bit definition for FDCAN_TTGTP register ********************/
\r
5048 #define FDCAN_TTGTP_TP_Pos (0U)
\r
5049 #define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
\r
5050 #define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
\r
5051 #define FDCAN_TTGTP_CTP_Pos (16U)
\r
5052 #define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
\r
5053 #define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
\r
5055 /***************** Bit definition for FDCAN_TTTMK register ********************/
\r
5056 #define FDCAN_TTTMK_TM_Pos (0U)
\r
5057 #define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
\r
5058 #define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
\r
5059 #define FDCAN_TTTMK_TICC_Pos (16U)
\r
5060 #define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
\r
5061 #define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
\r
5062 #define FDCAN_TTTMK_LCKM_Pos (31U)
\r
5063 #define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
\r
5064 #define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
\r
5066 /***************** Bit definition for FDCAN_TTIR register ********************/
\r
5067 #define FDCAN_TTIR_SBC_Pos (0U)
\r
5068 #define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
\r
5069 #define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
\r
5070 #define FDCAN_TTIR_SMC_Pos (1U)
\r
5071 #define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
\r
5072 #define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
\r
5073 #define FDCAN_TTIR_CSM_Pos (2U)
\r
5074 #define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
\r
5075 #define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
\r
5076 #define FDCAN_TTIR_SOG_Pos (3U)
\r
5077 #define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
\r
5078 #define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
\r
5079 #define FDCAN_TTIR_RTMI_Pos (4U)
\r
5080 #define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
\r
5081 #define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
\r
5082 #define FDCAN_TTIR_TTMI_Pos (5U)
\r
5083 #define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
\r
5084 #define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
\r
5085 #define FDCAN_TTIR_SWE_Pos (6U)
\r
5086 #define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
\r
5087 #define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
\r
5088 #define FDCAN_TTIR_GTW_Pos (7U)
\r
5089 #define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
\r
5090 #define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
\r
5091 #define FDCAN_TTIR_GTD_Pos (8U)
\r
5092 #define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
\r
5093 #define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
\r
5094 #define FDCAN_TTIR_GTE_Pos (9U)
\r
5095 #define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
\r
5096 #define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
\r
5097 #define FDCAN_TTIR_TXU_Pos (10U)
\r
5098 #define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
\r
5099 #define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
\r
5100 #define FDCAN_TTIR_TXO_Pos (11U)
\r
5101 #define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
\r
5102 #define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
\r
5103 #define FDCAN_TTIR_SE1_Pos (12U)
\r
5104 #define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
\r
5105 #define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
\r
5106 #define FDCAN_TTIR_SE2_Pos (13U)
\r
5107 #define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
\r
5108 #define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
\r
5109 #define FDCAN_TTIR_ELC_Pos (14U)
\r
5110 #define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
\r
5111 #define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
\r
5112 #define FDCAN_TTIR_IWT_Pos (15U)
\r
5113 #define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
\r
5114 #define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
\r
5115 #define FDCAN_TTIR_WT_Pos (16U)
\r
5116 #define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
\r
5117 #define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
\r
5118 #define FDCAN_TTIR_AW_Pos (17U)
\r
5119 #define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
\r
5120 #define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
\r
5121 #define FDCAN_TTIR_CER_Pos (18U)
\r
5122 #define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
\r
5123 #define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
\r
5125 /***************** Bit definition for FDCAN_TTIE register ********************/
\r
5126 #define FDCAN_TTIE_SBCE_Pos (0U)
\r
5127 #define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
\r
5128 #define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
\r
5129 #define FDCAN_TTIE_SMCE_Pos (1U)
\r
5130 #define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
\r
5131 #define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
\r
5132 #define FDCAN_TTIE_CSME_Pos (2U)
\r
5133 #define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
\r
5134 #define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
\r
5135 #define FDCAN_TTIE_SOGE_Pos (3U)
\r
5136 #define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
\r
5137 #define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
\r
5138 #define FDCAN_TTIE_RTMIE_Pos (4U)
\r
5139 #define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
\r
5140 #define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
\r
5141 #define FDCAN_TTIE_TTMIE_Pos (5U)
\r
5142 #define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
\r
5143 #define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
\r
5144 #define FDCAN_TTIE_SWEE_Pos (6U)
\r
5145 #define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
\r
5146 #define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
\r
5147 #define FDCAN_TTIE_GTWE_Pos (7U)
\r
5148 #define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
\r
5149 #define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
\r
5150 #define FDCAN_TTIE_GTDE_Pos (8U)
\r
5151 #define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
\r
5152 #define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
\r
5153 #define FDCAN_TTIE_GTEE_Pos (9U)
\r
5154 #define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
\r
5155 #define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
\r
5156 #define FDCAN_TTIE_TXUE_Pos (10U)
\r
5157 #define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
\r
5158 #define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
\r
5159 #define FDCAN_TTIE_TXOE_Pos (11U)
\r
5160 #define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
\r
5161 #define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
\r
5162 #define FDCAN_TTIE_SE1E_Pos (12U)
\r
5163 #define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
\r
5164 #define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
\r
5165 #define FDCAN_TTIE_SE2E_Pos (13U)
\r
5166 #define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
\r
5167 #define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
\r
5168 #define FDCAN_TTIE_ELCE_Pos (14U)
\r
5169 #define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
\r
5170 #define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
\r
5171 #define FDCAN_TTIE_IWTE_Pos (15U)
\r
5172 #define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
\r
5173 #define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
\r
5174 #define FDCAN_TTIE_WTE_Pos (16U)
\r
5175 #define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
\r
5176 #define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
\r
5177 #define FDCAN_TTIE_AWE_Pos (17U)
\r
5178 #define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
\r
5179 #define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
\r
5180 #define FDCAN_TTIE_CERE_Pos (18U)
\r
5181 #define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
\r
5182 #define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
\r
5184 /***************** Bit definition for FDCAN_TTILS register ********************/
\r
5185 #define FDCAN_TTILS_SBCS_Pos (0U)
\r
5186 #define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
\r
5187 #define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
\r
5188 #define FDCAN_TTILS_SMCS_Pos (1U)
\r
5189 #define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
\r
5190 #define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
\r
5191 #define FDCAN_TTILS_CSMS_Pos (2U)
\r
5192 #define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
\r
5193 #define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
\r
5194 #define FDCAN_TTILS_SOGS_Pos (3U)
\r
5195 #define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
\r
5196 #define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
\r
5197 #define FDCAN_TTILS_RTMIS_Pos (4U)
\r
5198 #define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
\r
5199 #define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
\r
5200 #define FDCAN_TTILS_TTMIS_Pos (5U)
\r
5201 #define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
\r
5202 #define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
\r
5203 #define FDCAN_TTILS_SWES_Pos (6U)
\r
5204 #define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
\r
5205 #define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
\r
5206 #define FDCAN_TTILS_GTWS_Pos (7U)
\r
5207 #define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
\r
5208 #define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
\r
5209 #define FDCAN_TTILS_GTDS_Pos (8U)
\r
5210 #define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
\r
5211 #define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
\r
5212 #define FDCAN_TTILS_GTES_Pos (9U)
\r
5213 #define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
\r
5214 #define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
\r
5215 #define FDCAN_TTILS_TXUS_Pos (10U)
\r
5216 #define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
\r
5217 #define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
\r
5218 #define FDCAN_TTILS_TXOS_Pos (11U)
\r
5219 #define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
\r
5220 #define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
\r
5221 #define FDCAN_TTILS_SE1S_Pos (12U)
\r
5222 #define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
\r
5223 #define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
\r
5224 #define FDCAN_TTILS_SE2S_Pos (13U)
\r
5225 #define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
\r
5226 #define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
\r
5227 #define FDCAN_TTILS_ELCS_Pos (14U)
\r
5228 #define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
\r
5229 #define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
\r
5230 #define FDCAN_TTILS_IWTS_Pos (15U)
\r
5231 #define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
\r
5232 #define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
\r
5233 #define FDCAN_TTILS_WTS_Pos (16U)
\r
5234 #define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
\r
5235 #define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
\r
5236 #define FDCAN_TTILS_AWS_Pos (17U)
\r
5237 #define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
\r
5238 #define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
\r
5239 #define FDCAN_TTILS_CERS_Pos (18U)
\r
5240 #define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
\r
5241 #define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
\r
5243 /***************** Bit definition for FDCAN_TTOST register ********************/
\r
5244 #define FDCAN_TTOST_EL_Pos (0U)
\r
5245 #define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
\r
5246 #define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
\r
5247 #define FDCAN_TTOST_MS_Pos (2U)
\r
5248 #define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
\r
5249 #define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
\r
5250 #define FDCAN_TTOST_SYS_Pos (4U)
\r
5251 #define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
\r
5252 #define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
\r
5253 #define FDCAN_TTOST_QGTP_Pos (6U)
\r
5254 #define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
\r
5255 #define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
\r
5256 #define FDCAN_TTOST_QCS_Pos (7U)
\r
5257 #define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
\r
5258 #define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
\r
5259 #define FDCAN_TTOST_RTO_Pos (8U)
\r
5260 #define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
\r
5261 #define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
\r
5262 #define FDCAN_TTOST_WGTD_Pos (22U)
\r
5263 #define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
\r
5264 #define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
\r
5265 #define FDCAN_TTOST_GFI_Pos (23U)
\r
5266 #define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
\r
5267 #define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
\r
5268 #define FDCAN_TTOST_TMP_Pos (24U)
\r
5269 #define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
\r
5270 #define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
\r
5271 #define FDCAN_TTOST_GSI_Pos (27U)
\r
5272 #define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
\r
5273 #define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
\r
5274 #define FDCAN_TTOST_WFE_Pos (28U)
\r
5275 #define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
\r
5276 #define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
\r
5277 #define FDCAN_TTOST_AWE_Pos (29U)
\r
5278 #define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
\r
5279 #define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
\r
5280 #define FDCAN_TTOST_WECS_Pos (30U)
\r
5281 #define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
\r
5282 #define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
\r
5283 #define FDCAN_TTOST_SPL_Pos (31U)
\r
5284 #define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
\r
5285 #define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
\r
5287 /***************** Bit definition for FDCAN_TURNA register ********************/
\r
5288 #define FDCAN_TURNA_NAV_Pos (0U)
\r
5289 #define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
\r
5290 #define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
\r
5292 /***************** Bit definition for FDCAN_TTLGT register ********************/
\r
5293 #define FDCAN_TTLGT_LT_Pos (0U)
\r
5294 #define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
\r
5295 #define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
\r
5296 #define FDCAN_TTLGT_GT_Pos (16U)
\r
5297 #define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
\r
5298 #define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
\r
5300 /***************** Bit definition for FDCAN_TTCTC register ********************/
\r
5301 #define FDCAN_TTCTC_CT_Pos (0U)
\r
5302 #define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
\r
5303 #define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
\r
5304 #define FDCAN_TTCTC_CC_Pos (16U)
\r
5305 #define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
\r
5306 #define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
\r
5308 /***************** Bit definition for FDCAN_TTCPT register ********************/
\r
5309 #define FDCAN_TTCPT_CCV_Pos (0U)
\r
5310 #define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
\r
5311 #define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
\r
5312 #define FDCAN_TTCPT_SWV_Pos (16U)
\r
5313 #define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
\r
5314 #define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
\r
5316 /***************** Bit definition for FDCAN_TTCSM register ********************/
\r
5317 #define FDCAN_TTCSM_CSM_Pos (0U)
\r
5318 #define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
\r
5319 #define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
\r
5321 /***************** Bit definition for FDCAN_TTTS register *********************/
\r
5322 #define FDCAN_TTTS_SWTSEL_Pos (0U)
\r
5323 #define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
\r
5324 #define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
\r
5325 #define FDCAN_TTTS_EVTSEL_Pos (4U)
\r
5326 #define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
\r
5327 #define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
\r
5329 /********************************************************************************/
\r
5331 /* FDCANCCU (Clock Calibration unit) */
\r
5333 /********************************************************************************/
\r
5335 /***************** Bit definition for FDCANCCU_CREL register ******************/
\r
5336 #define FDCANCCU_CREL_DAY_Pos (0U)
\r
5337 #define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
\r
5338 #define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
\r
5339 #define FDCANCCU_CREL_MON_Pos (8U)
\r
5340 #define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
\r
5341 #define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
\r
5342 #define FDCANCCU_CREL_YEAR_Pos (16U)
\r
5343 #define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
\r
5344 #define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
\r
5345 #define FDCANCCU_CREL_SUBSTEP_Pos (20U)
\r
5346 #define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
\r
5347 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
\r
5348 #define FDCANCCU_CREL_STEP_Pos (24U)
\r
5349 #define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
\r
5350 #define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
\r
5351 #define FDCANCCU_CREL_REL_Pos (28U)
\r
5352 #define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
\r
5353 #define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
\r
5355 /***************** Bit definition for FDCANCCU_CCFG register ******************/
\r
5356 #define FDCANCCU_CCFG_TQBT_Pos (0U)
\r
5357 #define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
\r
5358 #define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
\r
5359 #define FDCANCCU_CCFG_BCC_Pos (6U)
\r
5360 #define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
\r
5361 #define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
\r
5362 #define FDCANCCU_CCFG_CFL_Pos (7U)
\r
5363 #define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
\r
5364 #define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
\r
5365 #define FDCANCCU_CCFG_OCPM_Pos (8U)
\r
5366 #define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
\r
5367 #define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
\r
5368 #define FDCANCCU_CCFG_CDIV_Pos (16U)
\r
5369 #define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
\r
5370 #define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
\r
5371 #define FDCANCCU_CCFG_SWR_Pos (31U)
\r
5372 #define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
\r
5373 #define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
\r
5375 /***************** Bit definition for FDCANCCU_CSTAT register *****************/
\r
5376 #define FDCANCCU_CSTAT_OCPC_Pos (0U)
\r
5377 #define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
\r
5378 #define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
\r
5379 #define FDCANCCU_CSTAT_TQC_Pos (18U)
\r
5380 #define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
\r
5381 #define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
\r
5382 #define FDCANCCU_CSTAT_CALS_Pos (30U)
\r
5383 #define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
\r
5384 #define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
\r
5386 /****************** Bit definition for FDCANCCU_CWD register ******************/
\r
5387 #define FDCANCCU_CWD_WDC_Pos (0U)
\r
5388 #define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
\r
5389 #define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
\r
5390 #define FDCANCCU_CWD_WDV_Pos (16U)
\r
5391 #define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
\r
5392 #define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
\r
5394 /****************** Bit definition for FDCANCCU_IR register *******************/
\r
5395 #define FDCANCCU_IR_CWE_Pos (0U)
\r
5396 #define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
\r
5397 #define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
\r
5398 #define FDCANCCU_IR_CSC_Pos (1U)
\r
5399 #define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
\r
5400 #define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
\r
5402 /****************** Bit definition for FDCANCCU_IE register *******************/
\r
5403 #define FDCANCCU_IE_CWEE_Pos (0U)
\r
5404 #define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
\r
5405 #define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
\r
5406 #define FDCANCCU_IE_CSCE_Pos (1U)
\r
5407 #define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
\r
5408 #define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
\r
5410 /******************************************************************************/
\r
5412 /* HDMI-CEC (CEC) */
\r
5414 /******************************************************************************/
\r
5416 /******************* Bit definition for CEC_CR register *********************/
\r
5417 #define CEC_CR_CECEN_Pos (0U)
\r
5418 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
\r
5419 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
\r
5420 #define CEC_CR_TXSOM_Pos (1U)
\r
5421 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
\r
5422 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
\r
5423 #define CEC_CR_TXEOM_Pos (2U)
\r
5424 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
\r
5425 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
\r
5427 /******************* Bit definition for CEC_CFGR register *******************/
\r
5428 #define CEC_CFGR_SFT_Pos (0U)
\r
5429 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
\r
5430 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
\r
5431 #define CEC_CFGR_RXTOL_Pos (3U)
\r
5432 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
\r
5433 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
\r
5434 #define CEC_CFGR_BRESTP_Pos (4U)
\r
5435 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
\r
5436 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
\r
5437 #define CEC_CFGR_BREGEN_Pos (5U)
\r
5438 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
\r
5439 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
\r
5440 #define CEC_CFGR_LBPEGEN_Pos (6U)
\r
5441 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
\r
5442 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
\r
5443 #define CEC_CFGR_SFTOPT_Pos (8U)
\r
5444 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
\r
5445 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
\r
5446 #define CEC_CFGR_BRDNOGEN_Pos (7U)
\r
5447 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
\r
5448 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
\r
5449 #define CEC_CFGR_OAR_Pos (16U)
\r
5450 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
\r
5451 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
\r
5452 #define CEC_CFGR_LSTN_Pos (31U)
\r
5453 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
\r
5454 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
\r
5456 /******************* Bit definition for CEC_TXDR register *******************/
\r
5457 #define CEC_TXDR_TXD_Pos (0U)
\r
5458 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
\r
5459 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
\r
5461 /******************* Bit definition for CEC_RXDR register *******************/
\r
5462 #define CEC_RXDR_RXD_Pos (0U)
\r
5463 #define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
\r
5464 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
\r
5466 /******************* Bit definition for CEC_ISR register ********************/
\r
5467 #define CEC_ISR_RXBR_Pos (0U)
\r
5468 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
\r
5469 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
\r
5470 #define CEC_ISR_RXEND_Pos (1U)
\r
5471 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
\r
5472 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
\r
5473 #define CEC_ISR_RXOVR_Pos (2U)
\r
5474 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
\r
5475 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
\r
5476 #define CEC_ISR_BRE_Pos (3U)
\r
5477 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
\r
5478 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
\r
5479 #define CEC_ISR_SBPE_Pos (4U)
\r
5480 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
\r
5481 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
\r
5482 #define CEC_ISR_LBPE_Pos (5U)
\r
5483 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
\r
5484 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
\r
5485 #define CEC_ISR_RXACKE_Pos (6U)
\r
5486 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
\r
5487 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
\r
5488 #define CEC_ISR_ARBLST_Pos (7U)
\r
5489 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
\r
5490 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
\r
5491 #define CEC_ISR_TXBR_Pos (8U)
\r
5492 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
\r
5493 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
\r
5494 #define CEC_ISR_TXEND_Pos (9U)
\r
5495 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
\r
5496 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
\r
5497 #define CEC_ISR_TXUDR_Pos (10U)
\r
5498 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
\r
5499 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
\r
5500 #define CEC_ISR_TXERR_Pos (11U)
\r
5501 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
\r
5502 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
\r
5503 #define CEC_ISR_TXACKE_Pos (12U)
\r
5504 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
\r
5505 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
\r
5507 /******************* Bit definition for CEC_IER register ********************/
\r
5508 #define CEC_IER_RXBRIE_Pos (0U)
\r
5509 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
\r
5510 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
\r
5511 #define CEC_IER_RXENDIE_Pos (1U)
\r
5512 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
\r
5513 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
\r
5514 #define CEC_IER_RXOVRIE_Pos (2U)
\r
5515 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
\r
5516 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
\r
5517 #define CEC_IER_BREIE_Pos (3U)
\r
5518 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
\r
5519 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
\r
5520 #define CEC_IER_SBPEIE_Pos (4U)
\r
5521 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
\r
5522 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
\r
5523 #define CEC_IER_LBPEIE_Pos (5U)
\r
5524 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
\r
5525 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
\r
5526 #define CEC_IER_RXACKEIE_Pos (6U)
\r
5527 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
\r
5528 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
\r
5529 #define CEC_IER_ARBLSTIE_Pos (7U)
\r
5530 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
\r
5531 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
\r
5532 #define CEC_IER_TXBRIE_Pos (8U)
\r
5533 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
\r
5534 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
\r
5535 #define CEC_IER_TXENDIE_Pos (9U)
\r
5536 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
\r
5537 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
\r
5538 #define CEC_IER_TXUDRIE_Pos (10U)
\r
5539 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
\r
5540 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
\r
5541 #define CEC_IER_TXERRIE_Pos (11U)
\r
5542 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
\r
5543 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
\r
5544 #define CEC_IER_TXACKEIE_Pos (12U)
\r
5545 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
\r
5546 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
\r
5548 /******************************************************************************/
\r
5550 /* CRC calculation unit */
\r
5552 /******************************************************************************/
\r
5553 /******************* Bit definition for CRC_DR register *********************/
\r
5554 #define CRC_DR_DR_Pos (0U)
\r
5555 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
\r
5556 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
\r
5558 /******************* Bit definition for CRC_IDR register ********************/
\r
5559 #define CRC_IDR_IDR_Pos (0U)
\r
5560 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
\r
5561 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
\r
5563 /******************** Bit definition for CRC_CR register ********************/
\r
5564 #define CRC_CR_RESET_Pos (0U)
\r
5565 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
\r
5566 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
\r
5567 #define CRC_CR_POLYSIZE_Pos (3U)
\r
5568 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
\r
5569 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
\r
5570 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
\r
5571 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
\r
5572 #define CRC_CR_REV_IN_Pos (5U)
\r
5573 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
\r
5574 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
\r
5575 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
\r
5576 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
\r
5577 #define CRC_CR_REV_OUT_Pos (7U)
\r
5578 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
\r
5579 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
\r
5581 /******************* Bit definition for CRC_INIT register *******************/
\r
5582 #define CRC_INIT_INIT_Pos (0U)
\r
5583 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
\r
5584 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
\r
5586 /******************* Bit definition for CRC_POL register ********************/
\r
5587 #define CRC_POL_POL_Pos (0U)
\r
5588 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
\r
5589 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
\r
5591 /******************************************************************************/
\r
5593 /* CRS Clock Recovery System */
\r
5594 /******************************************************************************/
\r
5596 /******************* Bit definition for CRS_CR register *********************/
\r
5597 #define CRS_CR_SYNCOKIE_Pos (0U)
\r
5598 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
\r
5599 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
\r
5600 #define CRS_CR_SYNCWARNIE_Pos (1U)
\r
5601 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
\r
5602 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
\r
5603 #define CRS_CR_ERRIE_Pos (2U)
\r
5604 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
\r
5605 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
\r
5606 #define CRS_CR_ESYNCIE_Pos (3U)
\r
5607 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
\r
5608 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
\r
5609 #define CRS_CR_CEN_Pos (5U)
\r
5610 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
\r
5611 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
\r
5612 #define CRS_CR_AUTOTRIMEN_Pos (6U)
\r
5613 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
\r
5614 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
\r
5615 #define CRS_CR_SWSYNC_Pos (7U)
\r
5616 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
\r
5617 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
\r
5618 #define CRS_CR_TRIM_Pos (8U)
\r
5619 #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
\r
5620 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
\r
5622 /******************* Bit definition for CRS_CFGR register *********************/
\r
5623 #define CRS_CFGR_RELOAD_Pos (0U)
\r
5624 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
\r
5625 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
\r
5626 #define CRS_CFGR_FELIM_Pos (16U)
\r
5627 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
\r
5628 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
\r
5630 #define CRS_CFGR_SYNCDIV_Pos (24U)
\r
5631 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
\r
5632 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
\r
5633 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
\r
5634 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
\r
5635 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
\r
5637 #define CRS_CFGR_SYNCSRC_Pos (28U)
\r
5638 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
\r
5639 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
\r
5640 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
\r
5641 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
\r
5643 #define CRS_CFGR_SYNCPOL_Pos (31U)
\r
5644 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
\r
5645 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
\r
5647 /******************* Bit definition for CRS_ISR register *********************/
\r
5648 #define CRS_ISR_SYNCOKF_Pos (0U)
\r
5649 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
\r
5650 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
\r
5651 #define CRS_ISR_SYNCWARNF_Pos (1U)
\r
5652 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
\r
5653 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
\r
5654 #define CRS_ISR_ERRF_Pos (2U)
\r
5655 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
\r
5656 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
\r
5657 #define CRS_ISR_ESYNCF_Pos (3U)
\r
5658 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
\r
5659 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
\r
5660 #define CRS_ISR_SYNCERR_Pos (8U)
\r
5661 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
\r
5662 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
\r
5663 #define CRS_ISR_SYNCMISS_Pos (9U)
\r
5664 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
\r
5665 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
\r
5666 #define CRS_ISR_TRIMOVF_Pos (10U)
\r
5667 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
\r
5668 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
\r
5669 #define CRS_ISR_FEDIR_Pos (15U)
\r
5670 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
\r
5671 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
\r
5672 #define CRS_ISR_FECAP_Pos (16U)
\r
5673 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
\r
5674 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
\r
5676 /******************* Bit definition for CRS_ICR register *********************/
\r
5677 #define CRS_ICR_SYNCOKC_Pos (0U)
\r
5678 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
\r
5679 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
\r
5680 #define CRS_ICR_SYNCWARNC_Pos (1U)
\r
5681 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
\r
5682 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
\r
5683 #define CRS_ICR_ERRC_Pos (2U)
\r
5684 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
\r
5685 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
\r
5686 #define CRS_ICR_ESYNCC_Pos (3U)
\r
5687 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
\r
5688 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
\r
5690 /******************************************************************************/
\r
5692 /* Digital to Analog Converter */
\r
5694 /******************************************************************************/
\r
5695 /******************** Bit definition for DAC_CR register ********************/
\r
5696 #define DAC_CR_EN1_Pos (0U)
\r
5697 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
\r
5698 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
\r
5699 #define DAC_CR_TEN1_Pos (1U)
\r
5700 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
\r
5701 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
\r
5703 #define DAC_CR_TSEL1_Pos (2U)
\r
5704 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
\r
5705 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
\r
5706 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
\r
5707 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
\r
5708 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
\r
5709 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
\r
5712 #define DAC_CR_WAVE1_Pos (6U)
\r
5713 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
\r
5714 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
\r
5715 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
\r
5716 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
\r
5718 #define DAC_CR_MAMP1_Pos (8U)
\r
5719 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
\r
5720 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
\r
5721 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
\r
5722 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
\r
5723 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
\r
5724 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
\r
5726 #define DAC_CR_DMAEN1_Pos (12U)
\r
5727 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
\r
5728 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
\r
5729 #define DAC_CR_DMAUDRIE1_Pos (13U)
\r
5730 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
\r
5731 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
\r
5732 #define DAC_CR_CEN1_Pos (14U)
\r
5733 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
\r
5734 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
\r
5736 #define DAC_CR_EN2_Pos (16U)
\r
5737 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
\r
5738 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
\r
5739 #define DAC_CR_TEN2_Pos (17U)
\r
5740 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
\r
5741 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
\r
5743 #define DAC_CR_TSEL2_Pos (18U)
\r
5744 #define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
\r
5745 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
\r
5746 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
\r
5747 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
\r
5748 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
\r
5749 #define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
\r
5752 #define DAC_CR_WAVE2_Pos (22U)
\r
5753 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
\r
5754 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
\r
5755 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
\r
5756 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
\r
5758 #define DAC_CR_MAMP2_Pos (24U)
\r
5759 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
\r
5760 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
\r
5761 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
\r
5762 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
\r
5763 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
\r
5764 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
\r
5766 #define DAC_CR_DMAEN2_Pos (28U)
\r
5767 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
\r
5768 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
\r
5769 #define DAC_CR_DMAUDRIE2_Pos (29U)
\r
5770 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
\r
5771 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
\r
5772 #define DAC_CR_CEN2_Pos (30U)
\r
5773 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
\r
5774 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
\r
5776 /***************** Bit definition for DAC_SWTRIGR register ******************/
\r
5777 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
\r
5778 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
\r
5779 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
\r
5780 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
\r
5781 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
\r
5782 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
\r
5784 /***************** Bit definition for DAC_DHR12R1 register ******************/
\r
5785 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
\r
5786 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
\r
5787 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
\r
5789 /***************** Bit definition for DAC_DHR12L1 register ******************/
\r
5790 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
\r
5791 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
\r
5792 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
\r
5794 /****************** Bit definition for DAC_DHR8R1 register ******************/
\r
5795 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
\r
5796 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
\r
5797 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
\r
5799 /***************** Bit definition for DAC_DHR12R2 register ******************/
\r
5800 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
\r
5801 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
\r
5802 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
\r
5804 /***************** Bit definition for DAC_DHR12L2 register ******************/
\r
5805 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
\r
5806 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
\r
5807 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
\r
5809 /****************** Bit definition for DAC_DHR8R2 register ******************/
\r
5810 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
\r
5811 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
\r
5812 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
\r
5814 /***************** Bit definition for DAC_DHR12RD register ******************/
\r
5815 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
\r
5816 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
\r
5817 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
\r
5818 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
\r
5819 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
\r
5820 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
\r
5822 /***************** Bit definition for DAC_DHR12LD register ******************/
\r
5823 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
\r
5824 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
\r
5825 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
\r
5826 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
\r
5827 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
\r
5828 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
\r
5830 /****************** Bit definition for DAC_DHR8RD register ******************/
\r
5831 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
\r
5832 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
\r
5833 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
\r
5834 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
\r
5835 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
\r
5836 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
\r
5838 /******************* Bit definition for DAC_DOR1 register *******************/
\r
5839 #define DAC_DOR1_DACC1DOR_Pos (0U)
\r
5840 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
\r
5841 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
\r
5843 /******************* Bit definition for DAC_DOR2 register *******************/
\r
5844 #define DAC_DOR2_DACC2DOR_Pos (0U)
\r
5845 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
\r
5846 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
\r
5848 /******************** Bit definition for DAC_SR register ********************/
\r
5849 #define DAC_SR_DMAUDR1_Pos (13U)
\r
5850 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
\r
5851 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
\r
5852 #define DAC_SR_CAL_FLAG1_Pos (14U)
\r
5853 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
\r
5854 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
\r
5855 #define DAC_SR_BWST1_Pos (15U)
\r
5856 #define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
\r
5857 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
\r
5859 #define DAC_SR_DMAUDR2_Pos (29U)
\r
5860 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
\r
5861 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
\r
5862 #define DAC_SR_CAL_FLAG2_Pos (30U)
\r
5863 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
\r
5864 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
\r
5865 #define DAC_SR_BWST2_Pos (31U)
\r
5866 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
\r
5867 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
\r
5869 /******************* Bit definition for DAC_CCR register ********************/
\r
5870 #define DAC_CCR_OTRIM1_Pos (0U)
\r
5871 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
\r
5872 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
\r
5873 #define DAC_CCR_OTRIM2_Pos (16U)
\r
5874 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
\r
5875 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
\r
5877 /******************* Bit definition for DAC_MCR register *******************/
\r
5878 #define DAC_MCR_MODE1_Pos (0U)
\r
5879 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
\r
5880 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
\r
5881 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
\r
5882 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
\r
5883 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
\r
5885 #define DAC_MCR_MODE2_Pos (16U)
\r
5886 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
\r
5887 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
\r
5888 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
\r
5889 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
\r
5890 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
\r
5892 /****************** Bit definition for DAC_SHSR1 register ******************/
\r
5893 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
\r
5894 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
\r
5895 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
\r
5897 /****************** Bit definition for DAC_SHSR2 register ******************/
\r
5898 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
\r
5899 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
\r
5900 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
\r
5902 /****************** Bit definition for DAC_SHHR register ******************/
\r
5903 #define DAC_SHHR_THOLD1_Pos (0U)
\r
5904 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
\r
5905 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
\r
5906 #define DAC_SHHR_THOLD2_Pos (16U)
\r
5907 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
\r
5908 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
\r
5910 /****************** Bit definition for DAC_SHRR register ******************/
\r
5911 #define DAC_SHRR_TREFRESH1_Pos (0U)
\r
5912 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
\r
5913 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
\r
5914 #define DAC_SHRR_TREFRESH2_Pos (16U)
\r
5915 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
\r
5916 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
\r
5918 /******************************************************************************/
\r
5922 /******************************************************************************/
\r
5923 /******************** Bits definition for DCMI_CR register ******************/
\r
5924 #define DCMI_CR_CAPTURE_Pos (0U)
\r
5925 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
\r
5926 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
\r
5927 #define DCMI_CR_CM_Pos (1U)
\r
5928 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
\r
5929 #define DCMI_CR_CM DCMI_CR_CM_Msk
\r
5930 #define DCMI_CR_CROP_Pos (2U)
\r
5931 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
\r
5932 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
\r
5933 #define DCMI_CR_JPEG_Pos (3U)
\r
5934 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
\r
5935 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
\r
5936 #define DCMI_CR_ESS_Pos (4U)
\r
5937 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
\r
5938 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
\r
5939 #define DCMI_CR_PCKPOL_Pos (5U)
\r
5940 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
\r
5941 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
\r
5942 #define DCMI_CR_HSPOL_Pos (6U)
\r
5943 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
\r
5944 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
\r
5945 #define DCMI_CR_VSPOL_Pos (7U)
\r
5946 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
\r
5947 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
\r
5948 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
\r
5949 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
\r
5950 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
\r
5951 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
\r
5952 #define DCMI_CR_CRE_Pos (12U)
\r
5953 #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
\r
5954 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
\r
5955 #define DCMI_CR_ENABLE_Pos (14U)
\r
5956 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
\r
5957 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
\r
5958 #define DCMI_CR_BSM_Pos (16U)
\r
5959 #define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
\r
5960 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
\r
5961 #define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
\r
5962 #define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
\r
5963 #define DCMI_CR_OEBS_Pos (18U)
\r
5964 #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
\r
5965 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
\r
5966 #define DCMI_CR_LSM_Pos (19U)
\r
5967 #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
\r
5968 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
\r
5969 #define DCMI_CR_OELS_Pos (20U)
\r
5970 #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
\r
5971 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
\r
5973 /******************** Bits definition for DCMI_SR register ******************/
\r
5974 #define DCMI_SR_HSYNC_Pos (0U)
\r
5975 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
\r
5976 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
\r
5977 #define DCMI_SR_VSYNC_Pos (1U)
\r
5978 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
\r
5979 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
\r
5980 #define DCMI_SR_FNE_Pos (2U)
\r
5981 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
\r
5982 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
\r
5984 /******************** Bits definition for DCMI_RIS register ****************/
\r
5985 #define DCMI_RIS_FRAME_RIS_Pos (0U)
\r
5986 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
\r
5987 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
\r
5988 #define DCMI_RIS_OVR_RIS_Pos (1U)
\r
5989 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
\r
5990 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
\r
5991 #define DCMI_RIS_ERR_RIS_Pos (2U)
\r
5992 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
\r
5993 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
\r
5994 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
\r
5995 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
\r
5996 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
\r
5997 #define DCMI_RIS_LINE_RIS_Pos (4U)
\r
5998 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
\r
5999 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
\r
6001 /******************** Bits definition for DCMI_IER register *****************/
\r
6002 #define DCMI_IER_FRAME_IE_Pos (0U)
\r
6003 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
\r
6004 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
\r
6005 #define DCMI_IER_OVR_IE_Pos (1U)
\r
6006 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
\r
6007 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
\r
6008 #define DCMI_IER_ERR_IE_Pos (2U)
\r
6009 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
\r
6010 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
\r
6011 #define DCMI_IER_VSYNC_IE_Pos (3U)
\r
6012 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
\r
6013 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
\r
6014 #define DCMI_IER_LINE_IE_Pos (4U)
\r
6015 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
\r
6016 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
\r
6019 /******************** Bits definition for DCMI_MIS register *****************/
\r
6020 #define DCMI_MIS_FRAME_MIS_Pos (0U)
\r
6021 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
\r
6022 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
\r
6023 #define DCMI_MIS_OVR_MIS_Pos (1U)
\r
6024 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
\r
6025 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
\r
6026 #define DCMI_MIS_ERR_MIS_Pos (2U)
\r
6027 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
\r
6028 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
\r
6029 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
\r
6030 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
\r
6031 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
\r
6032 #define DCMI_MIS_LINE_MIS_Pos (4U)
\r
6033 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
\r
6034 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
\r
6037 /******************** Bits definition for DCMI_ICR register *****************/
\r
6038 #define DCMI_ICR_FRAME_ISC_Pos (0U)
\r
6039 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
\r
6040 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
\r
6041 #define DCMI_ICR_OVR_ISC_Pos (1U)
\r
6042 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
\r
6043 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
\r
6044 #define DCMI_ICR_ERR_ISC_Pos (2U)
\r
6045 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
\r
6046 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
\r
6047 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
\r
6048 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
\r
6049 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
\r
6050 #define DCMI_ICR_LINE_ISC_Pos (4U)
\r
6051 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
\r
6052 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
\r
6055 /******************** Bits definition for DCMI_ESCR register ******************/
\r
6056 #define DCMI_ESCR_FSC_Pos (0U)
\r
6057 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
\r
6058 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
\r
6059 #define DCMI_ESCR_LSC_Pos (8U)
\r
6060 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
\r
6061 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
\r
6062 #define DCMI_ESCR_LEC_Pos (16U)
\r
6063 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
\r
6064 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
\r
6065 #define DCMI_ESCR_FEC_Pos (24U)
\r
6066 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
\r
6067 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
\r
6069 /******************** Bits definition for DCMI_ESUR register ******************/
\r
6070 #define DCMI_ESUR_FSU_Pos (0U)
\r
6071 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
\r
6072 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
\r
6073 #define DCMI_ESUR_LSU_Pos (8U)
\r
6074 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
\r
6075 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
\r
6076 #define DCMI_ESUR_LEU_Pos (16U)
\r
6077 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
\r
6078 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
\r
6079 #define DCMI_ESUR_FEU_Pos (24U)
\r
6080 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
\r
6081 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
\r
6083 /******************** Bits definition for DCMI_CWSTRT register ******************/
\r
6084 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
\r
6085 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
\r
6086 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
\r
6087 #define DCMI_CWSTRT_VST_Pos (16U)
\r
6088 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
\r
6089 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
\r
6091 /******************** Bits definition for DCMI_CWSIZE register ******************/
\r
6092 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
\r
6093 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
\r
6094 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
\r
6095 #define DCMI_CWSIZE_VLINE_Pos (16U)
\r
6096 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
\r
6097 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
\r
6099 /******************** Bits definition for DCMI_DR register ******************/
\r
6100 #define DCMI_DR_BYTE0_Pos (0U)
\r
6101 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
\r
6102 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
\r
6103 #define DCMI_DR_BYTE1_Pos (8U)
\r
6104 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
\r
6105 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
\r
6106 #define DCMI_DR_BYTE2_Pos (16U)
\r
6107 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
\r
6108 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
\r
6109 #define DCMI_DR_BYTE3_Pos (24U)
\r
6110 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
\r
6111 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
\r
6113 /******************************************************************************/
\r
6115 /* Digital Filter for Sigma Delta Modulators */
\r
6117 /******************************************************************************/
\r
6119 /**************** DFSDM channel configuration registers ********************/
\r
6121 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
\r
6122 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
\r
6123 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
\r
6124 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
\r
6125 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
\r
6126 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
\r
6127 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
\r
6128 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
\r
6129 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
\r
6130 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
\r
6131 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
\r
6132 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
\r
6133 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
\r
6134 #define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
\r
6135 #define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
\r
6136 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
\r
6137 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
\r
6138 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
\r
6139 #define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
\r
6140 #define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
\r
6141 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
\r
6142 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
\r
6143 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
\r
6144 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
\r
6145 #define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
\r
6146 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
\r
6147 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
\r
6148 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
\r
6149 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
\r
6150 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
\r
6151 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
\r
6152 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
\r
6153 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
\r
6154 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
\r
6155 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
\r
6156 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
\r
6157 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
\r
6158 #define DFSDM_CHCFGR1_SITP_Pos (0U)
\r
6159 #define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
\r
6160 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
\r
6161 #define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
\r
6162 #define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
\r
6164 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
\r
6165 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
\r
6166 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
\r
6167 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
\r
6168 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
\r
6169 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
\r
6170 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
\r
6172 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
\r
6173 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
\r
6174 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
\r
6175 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
\r
6176 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
\r
6177 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
\r
6178 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
\r
6179 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
\r
6180 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
\r
6181 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
\r
6182 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
\r
6183 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
\r
6184 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
\r
6185 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
\r
6186 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
\r
6188 /**************** Bit definition for DFSDM_CHWDATR register *******************/
\r
6189 #define DFSDM_CHWDATR_WDATA_Pos (0U)
\r
6190 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
\r
6191 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
\r
6193 /**************** Bit definition for DFSDM_CHDATINR register *****************/
\r
6194 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
\r
6195 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
\r
6196 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
\r
6197 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
\r
6198 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
\r
6199 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
\r
6201 /************************ DFSDM module registers ****************************/
\r
6203 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
\r
6204 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
\r
6205 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
\r
6206 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
\r
6207 #define DFSDM_FLTCR1_FAST_Pos (29U)
\r
6208 #define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
\r
6209 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
\r
6210 #define DFSDM_FLTCR1_RCH_Pos (24U)
\r
6211 #define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
\r
6212 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
\r
6213 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
\r
6214 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
\r
6215 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
\r
6216 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
\r
6217 #define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
\r
6218 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
\r
6219 #define DFSDM_FLTCR1_RCONT_Pos (18U)
\r
6220 #define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
\r
6221 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
\r
6222 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
\r
6223 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
\r
6224 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
\r
6225 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
\r
6226 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
\r
6227 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
\r
6228 #define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
\r
6229 #define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
\r
6230 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
\r
6231 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
\r
6232 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
\r
6233 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
\r
6234 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
\r
6235 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
\r
6236 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
\r
6237 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
\r
6239 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
\r
6240 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
\r
6241 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
\r
6242 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
\r
6243 #define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
\r
6244 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
\r
6245 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
\r
6246 #define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
\r
6247 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
\r
6248 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
\r
6249 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
\r
6250 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
\r
6251 #define DFSDM_FLTCR1_DFEN_Pos (0U)
\r
6252 #define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
\r
6253 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
\r
6255 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
\r
6256 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
\r
6257 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
\r
6258 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
\r
6259 #define DFSDM_FLTCR2_EXCH_Pos (8U)
\r
6260 #define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
\r
6261 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
\r
6262 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
\r
6263 #define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
\r
6264 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
\r
6265 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
\r
6266 #define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
\r
6267 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
\r
6268 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
\r
6269 #define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
\r
6270 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
\r
6271 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
\r
6272 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
\r
6273 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
\r
6274 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
\r
6275 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
\r
6276 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
\r
6277 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
\r
6278 #define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
\r
6279 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
\r
6280 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
\r
6281 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
\r
6282 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
\r
6284 /******************** Bit definition for DFSDM_FLTISR register *******************/
\r
6285 #define DFSDM_FLTISR_SCDF_Pos (24U)
\r
6286 #define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
\r
6287 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
\r
6288 #define DFSDM_FLTISR_CKABF_Pos (16U)
\r
6289 #define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
\r
6290 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
\r
6291 #define DFSDM_FLTISR_RCIP_Pos (14U)
\r
6292 #define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
\r
6293 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
\r
6294 #define DFSDM_FLTISR_JCIP_Pos (13U)
\r
6295 #define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
\r
6296 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
\r
6297 #define DFSDM_FLTISR_AWDF_Pos (4U)
\r
6298 #define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
\r
6299 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
\r
6300 #define DFSDM_FLTISR_ROVRF_Pos (3U)
\r
6301 #define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
\r
6302 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
\r
6303 #define DFSDM_FLTISR_JOVRF_Pos (2U)
\r
6304 #define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
\r
6305 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
\r
6306 #define DFSDM_FLTISR_REOCF_Pos (1U)
\r
6307 #define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
\r
6308 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
\r
6309 #define DFSDM_FLTISR_JEOCF_Pos (0U)
\r
6310 #define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
\r
6311 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
\r
6313 /******************** Bit definition for DFSDM_FLTICR register *******************/
\r
6314 #define DFSDM_FLTICR_CLRSCDF_Pos (24U)
\r
6315 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
\r
6316 #define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
\r
6317 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
\r
6318 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
\r
6319 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
\r
6320 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
\r
6321 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
\r
6322 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
\r
6323 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
\r
6324 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
\r
6325 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
\r
6327 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
\r
6328 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
\r
6329 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
\r
6330 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
\r
6332 /******************** Bit definition for DFSDM_FLTFCR register *******************/
\r
6333 #define DFSDM_FLTFCR_FORD_Pos (29U)
\r
6334 #define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
\r
6335 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
\r
6336 #define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
\r
6337 #define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
\r
6338 #define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
\r
6339 #define DFSDM_FLTFCR_FOSR_Pos (16U)
\r
6340 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
\r
6341 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
\r
6342 #define DFSDM_FLTFCR_IOSR_Pos (0U)
\r
6343 #define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
\r
6344 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
\r
6346 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
\r
6347 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
\r
6348 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
\r
6349 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
\r
6350 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
\r
6351 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
\r
6352 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
\r
6354 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
\r
6355 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
\r
6356 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
\r
6357 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
\r
6358 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
\r
6359 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
\r
6360 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
\r
6361 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
\r
6362 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
\r
6363 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
\r
6365 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
\r
6366 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
\r
6367 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
\r
6368 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
\r
6369 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
\r
6370 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
\r
6371 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
\r
6373 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
\r
6374 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
\r
6375 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
\r
6376 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */
\r
6377 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
\r
6378 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
\r
6379 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
\r
6381 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
\r
6382 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
\r
6383 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
\r
6384 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
\r
6385 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
\r
6386 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
\r
6387 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
\r
6389 /****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
\r
6390 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
\r
6391 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
\r
6392 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
\r
6393 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
\r
6394 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
\r
6395 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
\r
6397 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
\r
6398 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
\r
6399 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
\r
6400 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
\r
6401 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
\r
6402 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
\r
6403 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
\r
6405 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
\r
6406 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
\r
6407 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
\r
6408 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
\r
6409 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
\r
6410 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
\r
6411 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
\r
6413 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
\r
6414 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
\r
6415 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
\r
6416 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
\r
6418 /******************************************************************************/
\r
6420 /* BDMA Controller */
\r
6422 /******************************************************************************/
\r
6424 /******************* Bit definition for BDMA_ISR register ********************/
\r
6425 #define BDMA_ISR_GIF0_Pos (0U)
\r
6426 #define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */
\r
6427 #define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */
\r
6428 #define BDMA_ISR_TCIF0_Pos (1U)
\r
6429 #define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */
\r
6430 #define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */
\r
6431 #define BDMA_ISR_HTIF0_Pos (2U)
\r
6432 #define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */
\r
6433 #define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */
\r
6434 #define BDMA_ISR_TEIF0_Pos (3U)
\r
6435 #define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */
\r
6436 #define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */
\r
6437 #define BDMA_ISR_GIF1_Pos (4U)
\r
6438 #define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */
\r
6439 #define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
\r
6440 #define BDMA_ISR_TCIF1_Pos (5U)
\r
6441 #define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */
\r
6442 #define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
\r
6443 #define BDMA_ISR_HTIF1_Pos (6U)
\r
6444 #define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */
\r
6445 #define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
\r
6446 #define BDMA_ISR_TEIF1_Pos (7U)
\r
6447 #define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */
\r
6448 #define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
\r
6449 #define BDMA_ISR_GIF2_Pos (8U)
\r
6450 #define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */
\r
6451 #define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
\r
6452 #define BDMA_ISR_TCIF2_Pos (9U)
\r
6453 #define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */
\r
6454 #define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
\r
6455 #define BDMA_ISR_HTIF2_Pos (10U)
\r
6456 #define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */
\r
6457 #define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
\r
6458 #define BDMA_ISR_TEIF2_Pos (11U)
\r
6459 #define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */
\r
6460 #define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
\r
6461 #define BDMA_ISR_GIF3_Pos (12U)
\r
6462 #define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */
\r
6463 #define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
\r
6464 #define BDMA_ISR_TCIF3_Pos (13U)
\r
6465 #define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */
\r
6466 #define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
\r
6467 #define BDMA_ISR_HTIF3_Pos (14U)
\r
6468 #define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */
\r
6469 #define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
\r
6470 #define BDMA_ISR_TEIF3_Pos (15U)
\r
6471 #define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */
\r
6472 #define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
\r
6473 #define BDMA_ISR_GIF4_Pos (16U)
\r
6474 #define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */
\r
6475 #define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
\r
6476 #define BDMA_ISR_TCIF4_Pos (17U)
\r
6477 #define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */
\r
6478 #define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
\r
6479 #define BDMA_ISR_HTIF4_Pos (18U)
\r
6480 #define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */
\r
6481 #define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
\r
6482 #define BDMA_ISR_TEIF4_Pos (19U)
\r
6483 #define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */
\r
6484 #define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
\r
6485 #define BDMA_ISR_GIF5_Pos (20U)
\r
6486 #define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */
\r
6487 #define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
\r
6488 #define BDMA_ISR_TCIF5_Pos (21U)
\r
6489 #define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */
\r
6490 #define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
\r
6491 #define BDMA_ISR_HTIF5_Pos (22U)
\r
6492 #define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */
\r
6493 #define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
\r
6494 #define BDMA_ISR_TEIF5_Pos (23U)
\r
6495 #define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */
\r
6496 #define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
\r
6497 #define BDMA_ISR_GIF6_Pos (24U)
\r
6498 #define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */
\r
6499 #define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
\r
6500 #define BDMA_ISR_TCIF6_Pos (25U)
\r
6501 #define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */
\r
6502 #define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
\r
6503 #define BDMA_ISR_HTIF6_Pos (26U)
\r
6504 #define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */
\r
6505 #define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
\r
6506 #define BDMA_ISR_TEIF6_Pos (27U)
\r
6507 #define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */
\r
6508 #define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
\r
6509 #define BDMA_ISR_GIF7_Pos (28U)
\r
6510 #define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */
\r
6511 #define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
\r
6512 #define BDMA_ISR_TCIF7_Pos (29U)
\r
6513 #define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */
\r
6514 #define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
\r
6515 #define BDMA_ISR_HTIF7_Pos (30U)
\r
6516 #define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */
\r
6517 #define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
\r
6518 #define BDMA_ISR_TEIF7_Pos (31U)
\r
6519 #define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */
\r
6520 #define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
\r
6522 /******************* Bit definition for BDMA_IFCR register *******************/
\r
6523 #define BDMA_IFCR_CGIF0_Pos (0U)
\r
6524 #define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */
\r
6525 #define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */
\r
6526 #define BDMA_IFCR_CTCIF0_Pos (1U)
\r
6527 #define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */
\r
6528 #define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */
\r
6529 #define BDMA_IFCR_CHTIF0_Pos (2U)
\r
6530 #define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */
\r
6531 #define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */
\r
6532 #define BDMA_IFCR_CTEIF0_Pos (3U)
\r
6533 #define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */
\r
6534 #define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */
\r
6535 #define BDMA_IFCR_CGIF1_Pos (4U)
\r
6536 #define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */
\r
6537 #define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
\r
6538 #define BDMA_IFCR_CTCIF1_Pos (5U)
\r
6539 #define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */
\r
6540 #define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
\r
6541 #define BDMA_IFCR_CHTIF1_Pos (6U)
\r
6542 #define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */
\r
6543 #define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
\r
6544 #define BDMA_IFCR_CTEIF1_Pos (7U)
\r
6545 #define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */
\r
6546 #define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
\r
6547 #define BDMA_IFCR_CGIF2_Pos (8U)
\r
6548 #define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */
\r
6549 #define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
\r
6550 #define BDMA_IFCR_CTCIF2_Pos (9U)
\r
6551 #define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */
\r
6552 #define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
\r
6553 #define BDMA_IFCR_CHTIF2_Pos (10U)
\r
6554 #define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */
\r
6555 #define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
\r
6556 #define BDMA_IFCR_CTEIF2_Pos (11U)
\r
6557 #define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */
\r
6558 #define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
\r
6559 #define BDMA_IFCR_CGIF3_Pos (12U)
\r
6560 #define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */
\r
6561 #define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
\r
6562 #define BDMA_IFCR_CTCIF3_Pos (13U)
\r
6563 #define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */
\r
6564 #define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
\r
6565 #define BDMA_IFCR_CHTIF3_Pos (14U)
\r
6566 #define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */
\r
6567 #define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
\r
6568 #define BDMA_IFCR_CTEIF3_Pos (15U)
\r
6569 #define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */
\r
6570 #define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
\r
6571 #define BDMA_IFCR_CGIF4_Pos (16U)
\r
6572 #define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */
\r
6573 #define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
\r
6574 #define BDMA_IFCR_CTCIF4_Pos (17U)
\r
6575 #define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */
\r
6576 #define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
\r
6577 #define BDMA_IFCR_CHTIF4_Pos (18U)
\r
6578 #define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */
\r
6579 #define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
\r
6580 #define BDMA_IFCR_CTEIF4_Pos (19U)
\r
6581 #define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */
\r
6582 #define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
\r
6583 #define BDMA_IFCR_CGIF5_Pos (20U)
\r
6584 #define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */
\r
6585 #define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
\r
6586 #define BDMA_IFCR_CTCIF5_Pos (21U)
\r
6587 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
\r
6588 #define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
\r
6589 #define BDMA_IFCR_CHTIF5_Pos (22U)
\r
6590 #define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */
\r
6591 #define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
\r
6592 #define BDMA_IFCR_CTEIF5_Pos (23U)
\r
6593 #define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */
\r
6594 #define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
\r
6595 #define BDMA_IFCR_CGIF6_Pos (24U)
\r
6596 #define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */
\r
6597 #define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
\r
6598 #define BDMA_IFCR_CTCIF6_Pos (25U)
\r
6599 #define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */
\r
6600 #define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
\r
6601 #define BDMA_IFCR_CHTIF6_Pos (26U)
\r
6602 #define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */
\r
6603 #define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
\r
6604 #define BDMA_IFCR_CTEIF6_Pos (27U)
\r
6605 #define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */
\r
6606 #define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
\r
6607 #define BDMA_IFCR_CGIF7_Pos (28U)
\r
6608 #define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */
\r
6609 #define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
\r
6610 #define BDMA_IFCR_CTCIF7_Pos (29U)
\r
6611 #define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */
\r
6612 #define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
\r
6613 #define BDMA_IFCR_CHTIF7_Pos (30U)
\r
6614 #define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */
\r
6615 #define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
\r
6616 #define BDMA_IFCR_CTEIF7_Pos (31U)
\r
6617 #define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */
\r
6618 #define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
\r
6620 /******************* Bit definition for BDMA_CCR register ********************/
\r
6621 #define BDMA_CCR_EN_Pos (0U)
\r
6622 #define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) /*!< 0x00000001 */
\r
6623 #define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */
\r
6624 #define BDMA_CCR_TCIE_Pos (1U)
\r
6625 #define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */
\r
6626 #define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
\r
6627 #define BDMA_CCR_HTIE_Pos (2U)
\r
6628 #define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */
\r
6629 #define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
\r
6630 #define BDMA_CCR_TEIE_Pos (3U)
\r
6631 #define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */
\r
6632 #define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
\r
6633 #define BDMA_CCR_DIR_Pos (4U)
\r
6634 #define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */
\r
6635 #define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */
\r
6636 #define BDMA_CCR_CIRC_Pos (5U)
\r
6637 #define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */
\r
6638 #define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */
\r
6639 #define BDMA_CCR_PINC_Pos (6U)
\r
6640 #define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */
\r
6641 #define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */
\r
6642 #define BDMA_CCR_MINC_Pos (7U)
\r
6643 #define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */
\r
6644 #define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */
\r
6646 #define BDMA_CCR_PSIZE_Pos (8U)
\r
6647 #define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
\r
6648 #define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
\r
6649 #define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
\r
6650 #define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
\r
6652 #define BDMA_CCR_MSIZE_Pos (10U)
\r
6653 #define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
\r
6654 #define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
\r
6655 #define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
\r
6656 #define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
\r
6658 #define BDMA_CCR_PL_Pos (12U)
\r
6659 #define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) /*!< 0x00003000 */
\r
6660 #define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
\r
6661 #define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) /*!< 0x00001000 */
\r
6662 #define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) /*!< 0x00002000 */
\r
6664 #define BDMA_CCR_MEM2MEM_Pos (14U)
\r
6665 #define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
\r
6666 #define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
\r
6667 #define BDMA_CCR_DBM_Pos (15U)
\r
6668 #define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) /*!< 0x0000A000 */
\r
6669 #define BDMA_CCR_DBM BDMA_CCR_DBM_Msk /*!< Memory to memory mode */
\r
6670 #define BDMA_CCR_CT_Pos (16U)
\r
6671 #define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) /*!< 0x00010000 */
\r
6672 #define BDMA_CCR_CT BDMA_CCR_CT_Msk /*!< Memory to memory mode */
\r
6674 /****************** Bit definition for BDMA_CNDTR register *******************/
\r
6675 #define BDMA_CNDTR_NDT_Pos (0U)
\r
6676 #define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
\r
6677 #define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
\r
6679 /****************** Bit definition for BDMA_CPAR register ********************/
\r
6680 #define BDMA_CPAR_PA_Pos (0U)
\r
6681 #define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
\r
6682 #define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */
\r
6684 /****************** Bit definition for BDMA_CM0AR register ********************/
\r
6685 #define BDMA_CM0AR_MA_Pos (0U)
\r
6686 #define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */
\r
6687 #define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk /*!< Memory Address */
\r
6689 /****************** Bit definition for BDMA_CM1AR register ********************/
\r
6690 #define BDMA_CM1AR_MA_Pos (0U)
\r
6691 #define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */
\r
6692 #define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk /*!< Memory Address */
\r
6694 /******************************************************************************/
\r
6696 /* Ethernet MAC Registers bits definitions */
\r
6698 /******************************************************************************/
\r
6699 /* Bit definition for Ethernet MAC Configuration Register register */
\r
6700 #define ETH_MACCR_ARP_Pos (31U)
\r
6701 #define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
\r
6702 #define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
\r
6703 #define ETH_MACCR_SARC_Pos (28U)
\r
6704 #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
\r
6705 #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
\r
6706 #define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
\r
6707 #define ETH_MACCR_SARC_INSADDR0_Pos (29U)
\r
6708 #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
\r
6709 #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
\r
6710 #define ETH_MACCR_SARC_INSADDR1_Pos (29U)
\r
6711 #define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
\r
6712 #define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
\r
6713 #define ETH_MACCR_SARC_REPADDR0_Pos (28U)
\r
6714 #define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
\r
6715 #define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
\r
6716 #define ETH_MACCR_SARC_REPADDR1_Pos (28U)
\r
6717 #define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
\r
6718 #define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
\r
6719 #define ETH_MACCR_IPC_Pos (27U)
\r
6720 #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
\r
6721 #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
\r
6722 #define ETH_MACCR_IPG_Pos (24U)
\r
6723 #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
\r
6724 #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
\r
6725 #define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
\r
6726 #define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
\r
6727 #define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
\r
6728 #define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
\r
6729 #define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
\r
6730 #define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
\r
6731 #define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
\r
6732 #define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
\r
6733 #define ETH_MACCR_GPSLCE_Pos (23U)
\r
6734 #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
\r
6735 #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
\r
6736 #define ETH_MACCR_S2KP_Pos (22U)
\r
6737 #define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
\r
6738 #define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
\r
6739 #define ETH_MACCR_CST_Pos (21U)
\r
6740 #define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
\r
6741 #define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
\r
6742 #define ETH_MACCR_ACS_Pos (20U)
\r
6743 #define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
\r
6744 #define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
\r
6745 #define ETH_MACCR_WD_Pos (19U)
\r
6746 #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
\r
6747 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
\r
6748 #define ETH_MACCR_JD_Pos (17U)
\r
6749 #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
\r
6750 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
\r
6751 #define ETH_MACCR_JE_Pos (16U)
\r
6752 #define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
\r
6753 #define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
\r
6754 #define ETH_MACCR_FES_Pos (14U)
\r
6755 #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
\r
6756 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
\r
6757 #define ETH_MACCR_DM_Pos (13U)
\r
6758 #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
\r
6759 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
\r
6760 #define ETH_MACCR_LM_Pos (12U)
\r
6761 #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
\r
6762 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
\r
6763 #define ETH_MACCR_ECRSFD_Pos (11U)
\r
6764 #define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
\r
6765 #define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
\r
6766 #define ETH_MACCR_DO_Pos (10U)
\r
6767 #define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
\r
6768 #define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
\r
6769 #define ETH_MACCR_DCRS_Pos (9U)
\r
6770 #define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
\r
6771 #define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
\r
6772 #define ETH_MACCR_DR_Pos (8U)
\r
6773 #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
\r
6774 #define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
\r
6775 #define ETH_MACCR_BL_Pos (5U)
\r
6776 #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
\r
6777 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
\r
6778 #define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
\r
6779 #define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
\r
6780 #define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
\r
6781 #define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
\r
6782 #define ETH_MACCR_DC_Pos (4U)
\r
6783 #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
\r
6784 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
\r
6785 #define ETH_MACCR_PRELEN_Pos (2U)
\r
6786 #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
\r
6787 #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
\r
6788 #define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
\r
6789 #define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
\r
6790 #define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
\r
6791 #define ETH_MACCR_TE_Pos (1U)
\r
6792 #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
\r
6793 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
\r
6794 #define ETH_MACCR_RE_Pos (0U)
\r
6795 #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
\r
6796 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
\r
6798 /* Bit definition for Ethernet MAC Extended Configuration Register register */
\r
6799 #define ETH_MACECR_EIPG_Pos (25U)
\r
6800 #define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
\r
6801 #define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
\r
6802 #define ETH_MACECR_EIPGEN_Pos (24U)
\r
6803 #define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
\r
6804 #define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
\r
6805 #define ETH_MACECR_USP_Pos (18U)
\r
6806 #define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
\r
6807 #define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
\r
6808 #define ETH_MACECR_SPEN_Pos (17U)
\r
6809 #define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
\r
6810 #define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
\r
6811 #define ETH_MACECR_DCRCC_Pos (16U)
\r
6812 #define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
\r
6813 #define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
\r
6814 #define ETH_MACECR_GPSL_Pos (0U)
\r
6815 #define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
\r
6816 #define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
\r
6818 /* Bit definition for Ethernet MAC Packet Filter Register */
\r
6819 #define ETH_MACPFR_RA_Pos (31U)
\r
6820 #define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
\r
6821 #define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
\r
6822 #define ETH_MACPFR_DNTU_Pos (21U)
\r
6823 #define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
\r
6824 #define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
\r
6825 #define ETH_MACPFR_IPFE_Pos (20U)
\r
6826 #define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
\r
6827 #define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
\r
6828 #define ETH_MACPFR_VTFE_Pos (16U)
\r
6829 #define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
\r
6830 #define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
\r
6831 #define ETH_MACPFR_HPF_Pos (10U)
\r
6832 #define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
\r
6833 #define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
\r
6834 #define ETH_MACPFR_SAF_Pos (9U)
\r
6835 #define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
\r
6836 #define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
\r
6837 #define ETH_MACPFR_SAIF_Pos (8U)
\r
6838 #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
\r
6839 #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
\r
6840 #define ETH_MACPFR_PCF_Pos (6U)
\r
6841 #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
\r
6842 #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
\r
6843 #define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
\r
6844 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
\r
6845 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
\r
6846 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
\r
6847 #define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
\r
6848 #define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
\r
6849 #define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
\r
6850 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
\r
6851 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
\r
6852 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
\r
6853 #define ETH_MACPFR_DBF_Pos (5U)
\r
6854 #define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
\r
6855 #define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
\r
6856 #define ETH_MACPFR_PM_Pos (4U)
\r
6857 #define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
\r
6858 #define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
\r
6859 #define ETH_MACPFR_DAIF_Pos (3U)
\r
6860 #define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
\r
6861 #define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
\r
6862 #define ETH_MACPFR_HMC_Pos (2U)
\r
6863 #define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
\r
6864 #define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
\r
6865 #define ETH_MACPFR_HUC_Pos (1U)
\r
6866 #define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
\r
6867 #define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
\r
6868 #define ETH_MACPFR_PR_Pos (0U)
\r
6869 #define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
\r
6870 #define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
\r
6872 /* Bit definition for Ethernet MAC Watchdog Timeout Register */
\r
6873 #define ETH_MACWTR_PWE_Pos (8U)
\r
6874 #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
\r
6875 #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
\r
6876 #define ETH_MACWTR_WTO_Pos (0U)
\r
6877 #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
\r
6878 #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
\r
6879 #define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
\r
6880 #define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
\r
6881 #define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
\r
6882 #define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
\r
6883 #define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
\r
6884 #define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
\r
6885 #define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
\r
6886 #define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
\r
6887 #define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
\r
6888 #define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
\r
6889 #define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
\r
6890 #define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
\r
6891 #define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
\r
6892 #define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
\r
6893 #define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
\r
6895 /* Bit definition for Ethernet MAC Hash Table High Register */
\r
6896 #define ETH_MACHTHR_HTH_Pos (0U)
\r
6897 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
\r
6898 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
\r
6900 /* Bit definition for Ethernet MAC Hash Table Low Register */
\r
6901 #define ETH_MACHTLR_HTL_Pos (0U)
\r
6902 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
\r
6903 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
\r
6905 /* Bit definition for Ethernet MAC VLAN Tag Register */
\r
6906 #define ETH_MACVTR_EIVLRXS_Pos (31U)
\r
6907 #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
\r
6908 #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
\r
6909 #define ETH_MACVTR_EIVLS_Pos (28U)
\r
6910 #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
\r
6911 #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
\r
6912 #define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
\r
6913 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
\r
6914 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
\r
6915 #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
\r
6916 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
\r
6917 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
\r
6918 #define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
\r
6919 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
\r
6920 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
\r
6921 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
\r
6922 #define ETH_MACVTR_ERIVLT_Pos (27U)
\r
6923 #define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
\r
6924 #define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
\r
6925 #define ETH_MACVTR_EDVLP_Pos (26U)
\r
6926 #define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
\r
6927 #define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
\r
6928 #define ETH_MACVTR_VTHM_Pos (25U)
\r
6929 #define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
\r
6930 #define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
\r
6931 #define ETH_MACVTR_EVLRXS_Pos (24U)
\r
6932 #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
\r
6933 #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
\r
6934 #define ETH_MACVTR_EVLS_Pos (21U)
\r
6935 #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
\r
6936 #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
\r
6937 #define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
\r
6938 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
\r
6939 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
\r
6940 #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
\r
6941 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
\r
6942 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
\r
6943 #define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
\r
6944 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
\r
6945 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
\r
6946 #define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
\r
6947 #define ETH_MACVTR_DOVLTC_Pos (20U)
\r
6948 #define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
\r
6949 #define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
\r
6950 #define ETH_MACVTR_ERSVLM_Pos (19U)
\r
6951 #define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
\r
6952 #define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
\r
6953 #define ETH_MACVTR_ESVL_Pos (18U)
\r
6954 #define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
\r
6955 #define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
\r
6956 #define ETH_MACVTR_VTIM_Pos (17U)
\r
6957 #define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
\r
6958 #define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
\r
6959 #define ETH_MACVTR_ETV_Pos (16U)
\r
6960 #define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
\r
6961 #define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
\r
6962 #define ETH_MACVTR_VL_Pos (0U)
\r
6963 #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
\r
6964 #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
\r
6965 #define ETH_MACVTR_VL_UP_Pos (13U)
\r
6966 #define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
\r
6967 #define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
\r
6968 #define ETH_MACVTR_VL_CFIDEI_Pos (12U)
\r
6969 #define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
\r
6970 #define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
\r
6971 #define ETH_MACVTR_VL_VID_Pos (0U)
\r
6972 #define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
\r
6973 #define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
\r
6975 /* Bit definition for Ethernet MAC VLAN Hash Table Register */
\r
6976 #define ETH_MACVHTR_VLHT_Pos (0U)
\r
6977 #define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
\r
6978 #define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
\r
6980 /* Bit definition for Ethernet MAC VLAN Incl Register */
\r
6981 #define ETH_MACVIR_VLTI_Pos (20U)
\r
6982 #define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
\r
6983 #define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
\r
6984 #define ETH_MACVIR_CSVL_Pos (19U)
\r
6985 #define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
\r
6986 #define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
\r
6987 #define ETH_MACVIR_VLP_Pos (18U)
\r
6988 #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
\r
6989 #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
\r
6990 #define ETH_MACVIR_VLC_Pos (16U)
\r
6991 #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
\r
6992 #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
\r
6993 #define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
\r
6994 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
\r
6995 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
\r
6996 #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
\r
6997 #define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
\r
6998 #define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
\r
6999 #define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
\r
7000 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
\r
7001 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
\r
7002 #define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
\r
7003 #define ETH_MACVIR_VLT_Pos (0U)
\r
7004 #define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
\r
7005 #define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
\r
7006 #define ETH_MACVIR_VLT_UP_Pos (13U)
\r
7007 #define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
\r
7008 #define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
\r
7009 #define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
\r
7010 #define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
\r
7011 #define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
\r
7012 #define ETH_MACVIR_VLT_VID_Pos (0U)
\r
7013 #define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
\r
7014 #define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
\r
7016 /* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
\r
7017 #define ETH_MACIVIR_VLTI_Pos (20U)
\r
7018 #define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
\r
7019 #define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
\r
7020 #define ETH_MACIVIR_CSVL_Pos (19U)
\r
7021 #define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
\r
7022 #define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
\r
7023 #define ETH_MACIVIR_VLP_Pos (18U)
\r
7024 #define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
\r
7025 #define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
\r
7026 #define ETH_MACIVIR_VLC_Pos (16U)
\r
7027 #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
\r
7028 #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
\r
7029 #define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
\r
7030 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
\r
7031 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
\r
7032 #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
\r
7033 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
\r
7034 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
\r
7035 #define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
\r
7036 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
\r
7037 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
\r
7038 #define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
\r
7039 #define ETH_MACIVIR_VLT_Pos (0U)
\r
7040 #define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
\r
7041 #define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
\r
7042 #define ETH_MACIVIR_VLT_UP_Pos (13U)
\r
7043 #define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
\r
7044 #define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
\r
7045 #define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
\r
7046 #define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
\r
7047 #define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
\r
7048 #define ETH_MACIVIR_VLT_VID_Pos (0U)
\r
7049 #define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
\r
7050 #define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
\r
7052 /* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
\r
7053 #define ETH_MACTFCR_PT_Pos (16U)
\r
7054 #define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
\r
7055 #define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
\r
7056 #define ETH_MACTFCR_DZPQ_Pos (7U)
\r
7057 #define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
\r
7058 #define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
\r
7059 #define ETH_MACTFCR_PLT_Pos (4U)
\r
7060 #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
\r
7061 #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
\r
7062 #define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
\r
7063 #define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
\r
7064 #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
\r
7065 #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
\r
7066 #define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
\r
7067 #define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
\r
7068 #define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
\r
7069 #define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
\r
7070 #define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
\r
7071 #define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
\r
7072 #define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
\r
7073 #define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
\r
7074 #define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
\r
7075 #define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
\r
7076 #define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
\r
7077 #define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
\r
7078 #define ETH_MACTFCR_TFE_Pos (1U)
\r
7079 #define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
\r
7080 #define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
\r
7081 #define ETH_MACTFCR_FCB_Pos (0U)
\r
7082 #define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
\r
7083 #define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
\r
7085 /* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
\r
7086 #define ETH_MACRFCR_UP_Pos (1U)
\r
7087 #define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
\r
7088 #define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
\r
7089 #define ETH_MACRFCR_RFE_Pos (0U)
\r
7090 #define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
\r
7091 #define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
\r
7093 /* Bit definition for Ethernet MAC Interrupt Status Register */
\r
7094 #define ETH_MACISR_RXSTSIS_Pos (14U)
\r
7095 #define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
\r
7096 #define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
\r
7097 #define ETH_MACISR_TXSTSIS_Pos (13U)
\r
7098 #define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
\r
7099 #define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
\r
7100 #define ETH_MACISR_TSIS_Pos (12U)
\r
7101 #define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
\r
7102 #define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
\r
7103 #define ETH_MACISR_MMCTXIS_Pos (10U)
\r
7104 #define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
\r
7105 #define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
\r
7106 #define ETH_MACISR_MMCRXIS_Pos (9U)
\r
7107 #define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
\r
7108 #define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
\r
7109 #define ETH_MACISR_MMCIS_Pos (8U)
\r
7110 #define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
\r
7111 #define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
\r
7112 #define ETH_MACISR_LPIIS_Pos (5U)
\r
7113 #define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
\r
7114 #define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
\r
7115 #define ETH_MACISR_PMTIS_Pos (4U)
\r
7116 #define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
\r
7117 #define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
\r
7118 #define ETH_MACISR_PHYIS_Pos (3U)
\r
7119 #define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
\r
7120 #define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
\r
7122 /* Bit definition for Ethernet MAC Interrupt Enable Register */
\r
7123 #define ETH_MACIER_RXSTSIE_Pos (14U)
\r
7124 #define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
\r
7125 #define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
\r
7126 #define ETH_MACIER_TXSTSIE_Pos (13U)
\r
7127 #define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
\r
7128 #define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
\r
7129 #define ETH_MACIER_TSIE_Pos (12U)
\r
7130 #define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
\r
7131 #define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
\r
7132 #define ETH_MACIER_LPIIE_Pos (5U)
\r
7133 #define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
\r
7134 #define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
\r
7135 #define ETH_MACIER_PMTIE_Pos (4U)
\r
7136 #define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
\r
7137 #define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
\r
7138 #define ETH_MACIER_PHYIE_Pos (3U)
\r
7139 #define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
\r
7140 #define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
\r
7142 /* Bit definition for Ethernet MAC Rx Tx Status Register */
\r
7143 #define ETH_MACRXTXSR_RWT_Pos (8U)
\r
7144 #define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
\r
7145 #define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
\r
7146 #define ETH_MACRXTXSR_EXCOL_Pos (5U)
\r
7147 #define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
\r
7148 #define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
\r
7149 #define ETH_MACRXTXSR_LCOL_Pos (4U)
\r
7150 #define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
\r
7151 #define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
\r
7152 #define ETH_MACRXTXSR_EXDEF_Pos (3U)
\r
7153 #define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
\r
7154 #define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
\r
7155 #define ETH_MACRXTXSR_LCARR_Pos (2U)
\r
7156 #define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
\r
7157 #define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
\r
7158 #define ETH_MACRXTXSR_NCARR_Pos (1U)
\r
7159 #define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
\r
7160 #define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
\r
7161 #define ETH_MACRXTXSR_TJT_Pos (0U)
\r
7162 #define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
\r
7163 #define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
\r
7165 /* Bit definition for Ethernet MAC PMT Control Status Register */
\r
7166 #define ETH_MACPCSR_RWKFILTRST_Pos (31U)
\r
7167 #define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
\r
7168 #define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
\r
7169 #define ETH_MACPCSR_RWKPTR_Pos (24U)
\r
7170 #define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
\r
7171 #define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
\r
7172 #define ETH_MACPCSR_RWKPFE_Pos (10U)
\r
7173 #define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
\r
7174 #define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
\r
7175 #define ETH_MACPCSR_GLBLUCAST_Pos (9U)
\r
7176 #define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
\r
7177 #define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
\r
7178 #define ETH_MACPCSR_RWKPRCVD_Pos (6U)
\r
7179 #define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
\r
7180 #define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
\r
7181 #define ETH_MACPCSR_MGKPRCVD_Pos (5U)
\r
7182 #define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
\r
7183 #define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
\r
7184 #define ETH_MACPCSR_RWKPKTEN_Pos (2U)
\r
7185 #define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
\r
7186 #define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
\r
7187 #define ETH_MACPCSR_MGKPKTEN_Pos (1U)
\r
7188 #define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
\r
7189 #define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
\r
7190 #define ETH_MACPCSR_PWRDWN_Pos (0U)
\r
7191 #define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
\r
7192 #define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
\r
7194 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
\r
7195 #define ETH_MACRWUPFR_D_Pos (0U)
\r
7196 #define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
\r
7197 #define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
\r
7199 /* Bit definition for Ethernet MAC LPI Control Status Register */
\r
7200 #define ETH_MACLCSR_LPITCSE_Pos (21U)
\r
7201 #define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
\r
7202 #define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
\r
7203 #define ETH_MACLCSR_LPITE_Pos (20U)
\r
7204 #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
\r
7205 #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
\r
7206 #define ETH_MACLCSR_LPITXA_Pos (19U)
\r
7207 #define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
\r
7208 #define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
\r
7209 #define ETH_MACLCSR_PLS_Pos (17U)
\r
7210 #define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
\r
7211 #define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
\r
7212 #define ETH_MACLCSR_LPIEN_Pos (16U)
\r
7213 #define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
\r
7214 #define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
\r
7215 #define ETH_MACLCSR_RLPIST_Pos (9U)
\r
7216 #define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
\r
7217 #define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
\r
7218 #define ETH_MACLCSR_TLPIST_Pos (8U)
\r
7219 #define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
\r
7220 #define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
\r
7221 #define ETH_MACLCSR_RLPIEX_Pos (3U)
\r
7222 #define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
\r
7223 #define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
\r
7224 #define ETH_MACLCSR_RLPIEN_Pos (2U)
\r
7225 #define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
\r
7226 #define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
\r
7227 #define ETH_MACLCSR_TLPIEX_Pos (1U)
\r
7228 #define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
\r
7229 #define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
\r
7230 #define ETH_MACLCSR_TLPIEN_Pos (0U)
\r
7231 #define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
\r
7232 #define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
\r
7234 /* Bit definition for Ethernet MAC LPI Timers Control Register */
\r
7235 #define ETH_MACLTCR_LST_Pos (16U)
\r
7236 #define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
\r
7237 #define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
\r
7238 #define ETH_MACLTCR_TWT_Pos (0U)
\r
7239 #define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
\r
7240 #define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
\r
7242 /* Bit definition for Ethernet MAC LPI Entry Timer Register */
\r
7243 #define ETH_MACLETR_LPIET_Pos (0U)
\r
7244 #define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
\r
7245 #define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
\r
7247 /* Bit definition for Ethernet MAC 1US Tic Counter Register */
\r
7248 #define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
\r
7249 #define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
\r
7250 #define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
\r
7252 /* Bit definition for Ethernet MAC Version Register */
\r
7253 #define ETH_MACVR_USERVER_Pos (8U)
\r
7254 #define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
\r
7255 #define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
\r
7256 #define ETH_MACVR_SNPSVER_Pos (0U)
\r
7257 #define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
\r
7258 #define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
\r
7260 /* Bit definition for Ethernet MAC Debug Register */
\r
7261 #define ETH_MACDR_TFCSTS_Pos (17U)
\r
7262 #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
\r
7263 #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
\r
7264 #define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
\r
7265 #define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
\r
7266 #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
\r
7267 #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
\r
7268 #define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
\r
7269 #define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
\r
7270 #define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
\r
7271 #define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
\r
7272 #define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
\r
7273 #define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
\r
7274 #define ETH_MACDR_TPESTS_Pos (16U)
\r
7275 #define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
\r
7276 #define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
\r
7277 #define ETH_MACDR_RFCFCSTS_Pos (1U)
\r
7278 #define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
\r
7279 #define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
\r
7280 #define ETH_MACDR_RPESTS_Pos (0U)
\r
7281 #define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
\r
7282 #define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
\r
7284 /* Bit definition for Ethernet MAC HW Feature0 Register */
\r
7285 #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
\r
7286 #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
\r
7287 #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
\r
7288 #define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
\r
7289 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
\r
7290 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
\r
7291 #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
\r
7292 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
\r
7293 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
\r
7294 #define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
\r
7295 #define ETH_MACHWF0R_SAVLANINS_Pos (27U)
\r
7296 #define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
\r
7297 #define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
\r
7298 #define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
\r
7299 #define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
\r
7300 #define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
\r
7301 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
\r
7302 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
\r
7303 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
\r
7304 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
\r
7305 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
\r
7306 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
\r
7307 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
\r
7308 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
\r
7309 #define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
\r
7310 #define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
\r
7311 #define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
\r
7312 #define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
\r
7313 #define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
\r
7314 #define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
\r
7315 #define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
\r
7316 #define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
\r
7317 #define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
\r
7318 #define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
\r
7319 #define ETH_MACHWF0R_RXCOESEL_Pos (16U)
\r
7320 #define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
\r
7321 #define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
\r
7322 #define ETH_MACHWF0R_TXCOESEL_Pos (14U)
\r
7323 #define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
\r
7324 #define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
\r
7325 #define ETH_MACHWF0R_EEESEL_Pos (13U)
\r
7326 #define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
\r
7327 #define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
\r
7328 #define ETH_MACHWF0R_TSSEL_Pos (12U)
\r
7329 #define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
\r
7330 #define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
\r
7331 #define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
\r
7332 #define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
\r
7333 #define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
\r
7334 #define ETH_MACHWF0R_MMCSEL_Pos (8U)
\r
7335 #define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
\r
7336 #define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
\r
7337 #define ETH_MACHWF0R_MGKSEL_Pos (7U)
\r
7338 #define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
\r
7339 #define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
\r
7340 #define ETH_MACHWF0R_RWKSEL_Pos (6U)
\r
7341 #define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
\r
7342 #define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
\r
7343 #define ETH_MACHWF0R_SMASEL_Pos (5U)
\r
7344 #define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
\r
7345 #define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
\r
7346 #define ETH_MACHWF0R_VLHASH_Pos (4U)
\r
7347 #define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
\r
7348 #define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
\r
7349 #define ETH_MACHWF0R_PCSSEL_Pos (3U)
\r
7350 #define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
\r
7351 #define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
\r
7352 #define ETH_MACHWF0R_HDSEL_Pos (2U)
\r
7353 #define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
\r
7354 #define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
\r
7355 #define ETH_MACHWF0R_GMIISEL_Pos (1U)
\r
7356 #define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
\r
7357 #define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
\r
7358 #define ETH_MACHWF0R_MIISEL_Pos (0U)
\r
7359 #define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
\r
7360 #define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
\r
7362 /* Bit definition for Ethernet MAC HW Feature1 Register */
\r
7363 #define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
\r
7364 #define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
\r
7365 #define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
\r
7366 #define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
\r
7367 #define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
\r
7368 #define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
\r
7369 #define ETH_MACHWF1R_AVSEL_Pos (20U)
\r
7370 #define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
\r
7371 #define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
\r
7372 #define ETH_MACHWF1R_DBGMEMA_Pos (19U)
\r
7373 #define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
\r
7374 #define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
\r
7375 #define ETH_MACHWF1R_TSOEN_Pos (18U)
\r
7376 #define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
\r
7377 #define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
\r
7378 #define ETH_MACHWF1R_SPHEN_Pos (17U)
\r
7379 #define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
\r
7380 #define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
\r
7381 #define ETH_MACHWF1R_DCBEN_Pos (16U)
\r
7382 #define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
\r
7383 #define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
\r
7384 #define ETH_MACHWF1R_ADDR64_Pos (14U)
\r
7385 #define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
\r
7386 #define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
\r
7387 #define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
\r
7388 #define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
\r
7389 #define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
\r
7390 #define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
\r
7391 #define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
\r
7392 #define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
\r
7393 #define ETH_MACHWF1R_PTOEN_Pos (12U)
\r
7394 #define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
\r
7395 #define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
\r
7396 #define ETH_MACHWF1R_OSTEN_Pos (11U)
\r
7397 #define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
\r
7398 #define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
\r
7399 #define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
\r
7400 #define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
\r
7401 #define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
\r
7402 #define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
\r
7403 #define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
\r
7404 #define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
\r
7406 /* Bit definition for Ethernet MAC HW Feature2 Register */
\r
7407 #define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
\r
7408 #define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
\r
7409 #define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
\r
7410 #define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
\r
7411 #define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
\r
7412 #define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
\r
7413 #define ETH_MACHWF2R_TXCHCNT_Pos (18U)
\r
7414 #define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
\r
7415 #define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
\r
7416 #define ETH_MACHWF2R_RXCHCNT_Pos (13U)
\r
7417 #define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
\r
7418 #define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
\r
7419 #define ETH_MACHWF2R_TXQCNT_Pos (6U)
\r
7420 #define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
\r
7421 #define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
\r
7422 #define ETH_MACHWF2R_RXQCNT_Pos (0U)
\r
7423 #define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
\r
7424 #define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
\r
7426 /* Bit definition for Ethernet MAC MDIO Address Register */
\r
7427 #define ETH_MACMDIOAR_PSE_Pos (27U)
\r
7428 #define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
\r
7429 #define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
\r
7430 #define ETH_MACMDIOAR_BTB_Pos (26U)
\r
7431 #define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
\r
7432 #define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
\r
7433 #define ETH_MACMDIOAR_PA_Pos (21U)
\r
7434 #define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
\r
7435 #define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
\r
7436 #define ETH_MACMDIOAR_RDA_Pos (16U)
\r
7437 #define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
\r
7438 #define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
\r
7439 #define ETH_MACMDIOAR_NTC_Pos (12U)
\r
7440 #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
\r
7441 #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
\r
7442 #define ETH_MACMDIOAR_CR_Pos (8U)
\r
7443 #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
\r
7444 #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
\r
7445 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
\r
7446 #define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
\r
7447 #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
\r
7448 #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
\r
7449 #define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
\r
7450 #define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
\r
7451 #define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
\r
7452 #define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
\r
7453 #define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
\r
7454 #define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
\r
7455 #define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
\r
7456 #define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
\r
7457 #define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
\r
7458 #define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
\r
7459 #define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
\r
7460 #define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
\r
7461 #define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
\r
7462 #define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
\r
7463 #define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
\r
7464 #define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
\r
7465 #define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
\r
7466 #define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
\r
7467 #define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
\r
7468 #define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
\r
7469 #define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
\r
7470 #define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
\r
7471 #define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
\r
7472 #define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
\r
7473 #define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
\r
7474 #define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
\r
7475 #define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
\r
7476 #define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
\r
7477 #define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
\r
7478 #define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
\r
7479 #define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
\r
7480 #define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
\r
7481 #define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
\r
7482 #define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
\r
7483 #define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
\r
7484 #define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
\r
7485 #define ETH_MACMDIOAR_SKAP_Pos (4U)
\r
7486 #define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
\r
7487 #define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
\r
7488 #define ETH_MACMDIOAR_MOC_Pos (2U)
\r
7489 #define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
\r
7490 #define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
\r
7491 #define ETH_MACMDIOAR_MOC_WR_Pos (2U)
\r
7492 #define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
\r
7493 #define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
\r
7494 #define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
\r
7495 #define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
\r
7496 #define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
\r
7497 #define ETH_MACMDIOAR_MOC_RD_Pos (2U)
\r
7498 #define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
\r
7499 #define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
\r
7500 #define ETH_MACMDIOAR_C45E_Pos (1U)
\r
7501 #define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
\r
7502 #define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
\r
7503 #define ETH_MACMDIOAR_MB_Pos (0U)
\r
7504 #define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
\r
7505 #define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
\r
7507 /* Bit definition for Ethernet MAC MDIO Data Register */
\r
7508 #define ETH_MACMDIODR_RA_Pos (16U)
\r
7509 #define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
\r
7510 #define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
\r
7511 #define ETH_MACMDIODR_MD_Pos (0U)
\r
7512 #define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
\r
7513 #define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
\r
7515 /* Bit definition for Ethernet ARP Address Register */
\r
7516 #define ETH_MACARPAR_ARPPA_Pos (0U)
\r
7517 #define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
\r
7518 #define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
\r
7520 /* Bit definition for Ethernet MAC Address 0 High Register */
\r
7521 #define ETH_MACA0HR_AE_Pos (31U)
\r
7522 #define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
\r
7523 #define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
\r
7524 #define ETH_MACA0HR_ADDRHI_Pos (0U)
\r
7525 #define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
\r
7526 #define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
\r
7528 /* Bit definition for Ethernet MAC Address 0 Low Register */
\r
7529 #define ETH_MACA0LR_ADDRLO_Pos (0U)
\r
7530 #define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
\r
7531 #define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
\r
7533 /* Bit definition for Ethernet MAC Address 1 High Register */
\r
7534 #define ETH_MACA1HR_AE_Pos (31U)
\r
7535 #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
\r
7536 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/
\r
7537 #define ETH_MACA1HR_SA_Pos (30U)
\r
7538 #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
\r
7539 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */
\r
7540 #define ETH_MACA1HR_MBC_Pos (24U)
\r
7541 #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
\r
7542 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
\r
7543 #define ETH_MACA1HR_ADDRHI_Pos (0U)
\r
7544 #define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
\r
7545 #define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
\r
7547 /* Bit definition for Ethernet MAC Address 1 Low Register */
\r
7548 #define ETH_MACA1LR_ADDRLO_Pos (0U)
\r
7549 #define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
\r
7550 #define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
\r
7552 /* Bit definition for Ethernet MAC Address 2 High Register */
\r
7553 #define ETH_MACA2HR_AE_Pos (31U)
\r
7554 #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
\r
7555 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/
\r
7556 #define ETH_MACA2HR_SA_Pos (30U)
\r
7557 #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
\r
7558 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */
\r
7559 #define ETH_MACA2HR_MBC_Pos (24U)
\r
7560 #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
\r
7561 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
\r
7562 #define ETH_MACA2HR_ADDRHI_Pos (0U)
\r
7563 #define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
\r
7564 #define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
\r
7566 /* Bit definition for Ethernet MAC Address 2 Low Register */
\r
7567 #define ETH_MACA2LR_ADDRLO_Pos (0U)
\r
7568 #define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
\r
7569 #define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
\r
7571 /* Bit definition for Ethernet MAC Address 3 High Register */
\r
7572 #define ETH_MACA3HR_AE_Pos (31U)
\r
7573 #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
\r
7574 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/
\r
7575 #define ETH_MACA3HR_SA_Pos (30U)
\r
7576 #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
\r
7577 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */
\r
7578 #define ETH_MACA3HR_MBC_Pos (24U)
\r
7579 #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
\r
7580 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
\r
7581 #define ETH_MACA3HR_ADDRHI_Pos (0U)
\r
7582 #define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
\r
7583 #define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
\r
7585 /* Bit definition for Ethernet MAC Address 3 Low Register */
\r
7586 #define ETH_MACA3LR_ADDRLO_Pos (0U)
\r
7587 #define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
\r
7588 #define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
\r
7590 /* Bit definition for Ethernet MAC Address High Register */
\r
7591 #define ETH_MACAHR_AE_Pos (31U)
\r
7592 #define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
\r
7593 #define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
\r
7594 #define ETH_MACAHR_SA_Pos (30U)
\r
7595 #define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
\r
7596 #define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
\r
7597 #define ETH_MACAHR_MBC_Pos (24U)
\r
7598 #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
\r
7599 #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
\r
7600 #define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
\r
7601 #define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
\r
7602 #define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
\r
7603 #define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
\r
7604 #define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
\r
7605 #define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
\r
7606 #define ETH_MACAHR_MACAH_Pos (0U)
\r
7607 #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
\r
7608 #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
\r
7610 /* Bit definition for Ethernet MAC Address Low Register */
\r
7611 #define ETH_MACALR_MACAL_Pos (0U)
\r
7612 #define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
\r
7613 #define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
\r
7615 /* Bit definition for Ethernet MMC Control Register */
\r
7616 #define ETH_MMCCR_UCDBC_Pos (8U)
\r
7617 #define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
\r
7618 #define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
\r
7619 #define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
\r
7620 #define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
\r
7621 #define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
\r
7622 #define ETH_MMCCR_CNTPRST_Pos (4U)
\r
7623 #define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
\r
7624 #define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
\r
7625 #define ETH_MMCCR_CNTFREEZ_Pos (3U)
\r
7626 #define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
\r
7627 #define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
\r
7628 #define ETH_MMCCR_RSTONRD_Pos (2U)
\r
7629 #define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
\r
7630 #define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
\r
7631 #define ETH_MMCCR_CNTSTOPRO_Pos (1U)
\r
7632 #define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
\r
7633 #define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
\r
7634 #define ETH_MMCCR_CNTRST_Pos (0U)
\r
7635 #define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
\r
7636 #define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
\r
7638 /* Bit definition for Ethernet MMC Rx Interrupt Register */
\r
7639 #define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
\r
7640 #define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
\r
7641 #define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
\r
7642 #define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
\r
7643 #define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
\r
7644 #define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
\r
7645 #define ETH_MMCRIR_RXUCGPIS_Pos (17U)
\r
7646 #define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
\r
7647 #define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
\r
7648 #define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
\r
7649 #define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
\r
7650 #define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
\r
7651 #define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
\r
7652 #define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
\r
7653 #define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
\r
7655 /* Bit definition for Ethernet MMC Tx Interrupt Register */
\r
7656 #define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
\r
7657 #define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
\r
7658 #define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
\r
7659 #define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
\r
7660 #define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
\r
7661 #define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
\r
7662 #define ETH_MMCTIR_TXGPKTIS_Pos (21U)
\r
7663 #define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
\r
7664 #define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
\r
7665 #define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
\r
7666 #define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
\r
7667 #define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
\r
7668 #define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
\r
7669 #define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
\r
7670 #define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
\r
7672 /* Bit definition for Ethernet MMC Rx interrupt Mask register */
\r
7673 #define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
\r
7674 #define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
\r
7675 #define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
\r
7676 #define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
\r
7677 #define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
\r
7678 #define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
\r
7679 #define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
\r
7680 #define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
\r
7681 #define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
\r
7682 #define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
\r
7683 #define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
\r
7684 #define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
\r
7685 #define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
\r
7686 #define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
\r
7687 #define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
\r
7689 /* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
\r
7690 #define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
\r
7691 #define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
\r
7692 #define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
\r
7693 #define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
\r
7694 #define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
\r
7695 #define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
\r
7696 #define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
\r
7697 #define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
\r
7698 #define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
\r
7699 #define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
\r
7700 #define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
\r
7701 #define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
\r
7702 #define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
\r
7703 #define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
\r
7704 #define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
\r
7706 /* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
\r
7707 #define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
\r
7708 #define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
\r
7709 #define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
\r
7711 /* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
\r
7712 #define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
\r
7713 #define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
\r
7714 #define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
\r
7716 /* Bit definition for Ethernet MMC Tx Packet Count Good Register */
\r
7717 #define ETH_MMCTPCGR_TXPKTG_Pos (0U)
\r
7718 #define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
\r
7719 #define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
\r
7721 /* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
\r
7722 #define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
\r
7723 #define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
\r
7724 #define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
\r
7726 /* Bit definition for Ethernet MMC Rx alignment error packets register */
\r
7727 #define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
\r
7728 #define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
\r
7729 #define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
\r
7731 /* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
\r
7732 #define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
\r
7733 #define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
\r
7734 #define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
\r
7736 /* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
\r
7737 #define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
\r
7738 #define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
\r
7739 #define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
\r
7741 /* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
\r
7742 #define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
\r
7743 #define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
\r
7744 #define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
\r
7746 /* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
\r
7747 #define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
\r
7748 #define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
\r
7749 #define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
\r
7751 /* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
\r
7752 #define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
\r
7753 #define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
\r
7754 #define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
\r
7756 /* Bit definition for Ethernet MAC L3 L4 Control Register */
\r
7757 #define ETH_MACL3L4CR_L4DPIM_Pos (21U)
\r
7758 #define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
\r
7759 #define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
\r
7760 #define ETH_MACL3L4CR_L4DPM_Pos (20U)
\r
7761 #define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
\r
7762 #define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
\r
7763 #define ETH_MACL3L4CR_L4SPIM_Pos (19U)
\r
7764 #define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
\r
7765 #define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
\r
7766 #define ETH_MACL3L4CR_L4SPM_Pos (18U)
\r
7767 #define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
\r
7768 #define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
\r
7769 #define ETH_MACL3L4CR_L4PEN_Pos (16U)
\r
7770 #define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
\r
7771 #define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
\r
7772 #define ETH_MACL3L4CR_L3HDBM_Pos (11U)
\r
7773 #define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
\r
7774 #define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
\r
7775 #define ETH_MACL3L4CR_L3HSBM_Pos (6U)
\r
7776 #define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
\r
7777 #define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
\r
7778 #define ETH_MACL3L4CR_L3DAIM_Pos (5U)
\r
7779 #define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
\r
7780 #define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
\r
7781 #define ETH_MACL3L4CR_L3DAM_Pos (4U)
\r
7782 #define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
\r
7783 #define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
\r
7784 #define ETH_MACL3L4CR_L3SAIM_Pos (3U)
\r
7785 #define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
\r
7786 #define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
\r
7787 #define ETH_MACL3L4CR_L3SAM_Pos (2U)
\r
7788 #define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
\r
7789 #define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
\r
7790 #define ETH_MACL3L4CR_L3PEN_Pos (0U)
\r
7791 #define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
\r
7792 #define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
\r
7794 /* Bit definition for Ethernet MAC L4 Address Register */
\r
7795 #define ETH_MACL4AR_L4DP_Pos (16U)
\r
7796 #define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
\r
7797 #define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
\r
7798 #define ETH_MACL4AR_L4SP_Pos (0U)
\r
7799 #define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
\r
7800 #define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
\r
7802 /* Bit definition for Ethernet MAC L3 Address0 Register */
\r
7803 #define ETH_MACL3A0R_L3A0_Pos (0U)
\r
7804 #define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
\r
7805 #define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
\r
7807 /* Bit definition for Ethernet MAC L4 Address1 Register */
\r
7808 #define ETH_MACL3A1R_L3A1_Pos (0U)
\r
7809 #define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
\r
7810 #define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
\r
7812 /* Bit definition for Ethernet MAC L4 Address2 Register */
\r
7813 #define ETH_MACL3A2R_L3A2_Pos (0U)
\r
7814 #define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
\r
7815 #define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
\r
7817 /* Bit definition for Ethernet MAC L4 Address3 Register */
\r
7818 #define ETH_MACL3A3R_L3A3_Pos (0U)
\r
7819 #define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
\r
7820 #define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
\r
7822 /* Bit definition for Ethernet MAC Timestamp Control Register */
\r
7823 #define ETH_MACTSCR_TXTSSTSM_Pos (24U)
\r
7824 #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
\r
7825 #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
\r
7826 #define ETH_MACTSCR_CSC_Pos (19U)
\r
7827 #define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
\r
7828 #define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
\r
7829 #define ETH_MACTSCR_TSENMACADDR_Pos (18U)
\r
7830 #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
\r
7831 #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
\r
7832 #define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
\r
7833 #define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
\r
7834 #define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
\r
7835 #define ETH_MACTSCR_TSMSTRENA_Pos (15U)
\r
7836 #define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
\r
7837 #define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
\r
7838 #define ETH_MACTSCR_TSEVNTENA_Pos (14U)
\r
7839 #define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
\r
7840 #define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
\r
7841 #define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
\r
7842 #define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
\r
7843 #define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
\r
7844 #define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
\r
7845 #define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
\r
7846 #define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
\r
7847 #define ETH_MACTSCR_TSIPENA_Pos (11U)
\r
7848 #define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
\r
7849 #define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
\r
7850 #define ETH_MACTSCR_TSVER2ENA_Pos (10U)
\r
7851 #define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
\r
7852 #define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
\r
7853 #define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
\r
7854 #define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
\r
7855 #define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
\r
7856 #define ETH_MACTSCR_TSENALL_Pos (8U)
\r
7857 #define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
\r
7858 #define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
\r
7859 #define ETH_MACTSCR_TSADDREG_Pos (5U)
\r
7860 #define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
\r
7861 #define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
\r
7862 #define ETH_MACTSCR_TSUPDT_Pos (3U)
\r
7863 #define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
\r
7864 #define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
\r
7865 #define ETH_MACTSCR_TSINIT_Pos (2U)
\r
7866 #define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
\r
7867 #define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
\r
7868 #define ETH_MACTSCR_TSCFUPDT_Pos (1U)
\r
7869 #define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
\r
7870 #define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
\r
7871 #define ETH_MACTSCR_TSENA_Pos (0U)
\r
7872 #define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
\r
7873 #define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
\r
7875 /* Bit definition for Ethernet MAC Sub-second Increment Register */
\r
7876 #define ETH_MACMACSSIR_SSINC_Pos (16U)
\r
7877 #define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
\r
7878 #define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
\r
7879 #define ETH_MACMACSSIR_SNSINC_Pos (8U)
\r
7880 #define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
\r
7881 #define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
\r
7883 /* Bit definition for Ethernet MAC System Time Seconds Register */
\r
7884 #define ETH_MACSTSR_TSS_Pos (0U)
\r
7885 #define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
\r
7886 #define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
\r
7888 /* Bit definition for Ethernet MAC System Time Nanoseconds Register */
\r
7889 #define ETH_MACSTNR_TSSS_Pos (0U)
\r
7890 #define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
\r
7891 #define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
\r
7893 /* Bit definition for Ethernet MAC System Time Seconds Update Register */
\r
7894 #define ETH_MACSTSUR_TSS_Pos (0U)
\r
7895 #define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
\r
7896 #define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
\r
7898 /* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
\r
7899 #define ETH_MACSTNUR_ADDSUB_Pos (31U)
\r
7900 #define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
\r
7901 #define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
\r
7902 #define ETH_MACSTNUR_TSSS_Pos (0U)
\r
7903 #define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
\r
7904 #define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
\r
7906 /* Bit definition for Ethernet MAC Timestamp Addend Register */
\r
7907 #define ETH_MACTSAR_TSAR_Pos (0U)
\r
7908 #define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
\r
7909 #define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
\r
7911 /* Bit definition for Ethernet MAC Timestamp Status Register */
\r
7912 #define ETH_MACTSSR_ATSNS_Pos (25U)
\r
7913 #define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
\r
7914 #define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
\r
7915 #define ETH_MACTSSR_ATSSTM_Pos (24U)
\r
7916 #define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
\r
7917 #define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
\r
7918 #define ETH_MACTSSR_ATSSTN_Pos (16U)
\r
7919 #define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
\r
7920 #define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
\r
7921 #define ETH_MACTSSR_TXTSSIS_Pos (15U)
\r
7922 #define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
\r
7923 #define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
\r
7924 #define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
\r
7925 #define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
\r
7926 #define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
\r
7927 #define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
\r
7928 #define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
\r
7929 #define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
\r
7930 #define ETH_MACTSSR_TSTARGT0_Pos (1U)
\r
7931 #define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
\r
7932 #define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
\r
7933 #define ETH_MACTSSR_TSSOVF_Pos (0U)
\r
7934 #define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
\r
7935 #define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
\r
7937 /* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
\r
7938 #define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)
\r
7939 #define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
\r
7940 #define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
\r
7941 #define ETH_MACTTSSNR_TXTSSLO_Pos (0U)
\r
7942 #define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
\r
7943 #define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
\r
7945 /* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
\r
7946 #define ETH_MACTTSSSR_TXTSSHI_Pos (0U)
\r
7947 #define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
\r
7948 #define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
\r
7950 /* Bit definition for Ethernet MAC Auxiliary Control Register*/
\r
7951 #define ETH_MACACR_ATSEN3_Pos (7U)
\r
7952 #define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
\r
7953 #define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
\r
7954 #define ETH_MACACR_ATSEN2_Pos (6U)
\r
7955 #define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
\r
7956 #define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
\r
7957 #define ETH_MACACR_ATSEN1_Pos (5U)
\r
7958 #define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
\r
7959 #define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
\r
7960 #define ETH_MACACR_ATSEN0_Pos (4U)
\r
7961 #define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
\r
7962 #define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
\r
7963 #define ETH_MACACR_ATSFC_Pos (0U)
\r
7964 #define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
\r
7965 #define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
\r
7967 /* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
\r
7968 #define ETH_MACATSNR_AUXTSLO_Pos (0U)
\r
7969 #define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
\r
7970 #define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
\r
7972 /* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
\r
7973 #define ETH_MACATSSR_AUXTSHI_Pos (0U)
\r
7974 #define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
\r
7975 #define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
\r
7977 /* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
\r
7978 #define ETH_MACTSIACR_OSTIAC_Pos (0U)
\r
7979 #define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
\r
7980 #define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
\r
7982 /* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
\r
7983 #define ETH_MACTSEACR_OSTEAC_Pos (0U)
\r
7984 #define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
\r
7985 #define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
\r
7987 /* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
\r
7988 #define ETH_MACTSICNR_TSIC_Pos (0U)
\r
7989 #define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
\r
7990 #define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
\r
7992 /* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
\r
7993 #define ETH_MACTSECNR_TSEC_Pos (0U)
\r
7994 #define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
\r
7995 #define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
\r
7997 /* Bit definition for Ethernet MAC PPS Control Register */
\r
7998 #define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
\r
7999 #define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
\r
8000 #define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
\r
8001 #define ETH_MACPPSCR_PPSEN0_Pos (4U)
\r
8002 #define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
\r
8003 #define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
\r
8004 #define ETH_MACPPSCR_PPSCTRL_Pos (0U)
\r
8005 #define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
\r
8006 #define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
\r
8008 /* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
\r
8009 #define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
\r
8010 #define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
\r
8011 #define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
\r
8013 /* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
\r
8014 #define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
\r
8015 #define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
\r
8016 #define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
\r
8017 #define ETH_MACPPSTTNR_TTSL0_Pos (0U)
\r
8018 #define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
\r
8019 #define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
\r
8021 /* Bit definition for Ethernet MAC PPS Interval Register */
\r
8022 #define ETH_MACPPSIR_PPSINT0_Pos (0U)
\r
8023 #define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
\r
8024 #define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
\r
8026 /* Bit definition for Ethernet MAC PPS Width Register */
\r
8027 #define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
\r
8028 #define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
\r
8029 #define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
\r
8031 /* Bit definition for Ethernet MAC PTP Offload Control Register */
\r
8032 #define ETH_MACPOCR_DN_Pos (8U)
\r
8033 #define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
\r
8034 #define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
\r
8035 #define ETH_MACPOCR_DRRDIS_Pos (6U)
\r
8036 #define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
\r
8037 #define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
\r
8038 #define ETH_MACPOCR_APDREQTRIG_Pos (5U)
\r
8039 #define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
\r
8040 #define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
\r
8041 #define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
\r
8042 #define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
\r
8043 #define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
\r
8044 #define ETH_MACPOCR_APDREQEN_Pos (2U)
\r
8045 #define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
\r
8046 #define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
\r
8047 #define ETH_MACPOCR_ASYNCEN_Pos (1U)
\r
8048 #define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
\r
8049 #define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
\r
8050 #define ETH_MACPOCR_PTOEN_Pos (0U)
\r
8051 #define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
\r
8052 #define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
\r
8054 /* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
\r
8055 #define ETH_MACSPI0R_SPI0_Pos (0U)
\r
8056 #define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
\r
8057 #define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
\r
8059 /* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
\r
8060 #define ETH_MACSPI1R_SPI1_Pos (0U)
\r
8061 #define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
\r
8062 #define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
\r
8064 /* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
\r
8065 #define ETH_MACSPI2R_SPI2_Pos (0U)
\r
8066 #define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
\r
8067 #define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
\r
8069 /* Bit definition for Ethernet MAC Log Message Interval Register */
\r
8070 #define ETH_MACLMIR_LMPDRI_Pos (24U)
\r
8071 #define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
\r
8072 #define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
\r
8073 #define ETH_MACLMIR_DRSYNCR_Pos (8U)
\r
8074 #define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
\r
8075 #define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
\r
8076 #define ETH_MACLMIR_LSI_Pos (0U)
\r
8077 #define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
\r
8078 #define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
\r
8080 /* Bit definition for Ethernet MTL Operation Mode Register */
\r
8081 #define ETH_MTLOMR_CNTCLR_Pos (9U)
\r
8082 #define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
\r
8083 #define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
\r
8084 #define ETH_MTLOMR_CNTPRST_Pos (8U)
\r
8085 #define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
\r
8086 #define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
\r
8087 #define ETH_MTLOMR_DTXSTS_Pos (1U)
\r
8088 #define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
\r
8089 #define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
\r
8091 /* Bit definition for Ethernet MTL Interrupt Status Register */
\r
8092 #define ETH_MTLISR_MACIS_Pos (16U)
\r
8093 #define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
\r
8094 #define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
\r
8095 #define ETH_MTLISR_QIS_Pos (0U)
\r
8096 #define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
\r
8097 #define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
\r
8099 /* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
\r
8100 #define ETH_MTLTQOMR_TTC_Pos (4U)
\r
8101 #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
\r
8102 #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
\r
8103 #define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
\r
8104 #define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
\r
8105 #define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
\r
8106 #define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
\r
8107 #define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
\r
8108 #define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
\r
8109 #define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
\r
8110 #define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
\r
8111 #define ETH_MTLTQOMR_TSF_Pos (1U)
\r
8112 #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
\r
8113 #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
\r
8114 #define ETH_MTLTQOMR_FTQ_Pos (0U)
\r
8115 #define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
\r
8116 #define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
\r
8118 /* Bit definition for Ethernet MTL Tx Queue Underflow Register */
\r
8119 #define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
\r
8120 #define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
\r
8121 #define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
\r
8122 #define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
\r
8123 #define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
\r
8124 #define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
\r
8126 /* Bit definition for Ethernet MTL Tx Queue Debug Register */
\r
8127 #define ETH_MTLTQDR_STXSTSF_Pos (20U)
\r
8128 #define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
\r
8129 #define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
\r
8130 #define ETH_MTLTQDR_PTXQ_Pos (16U)
\r
8131 #define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
\r
8132 #define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
\r
8133 #define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
\r
8134 #define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
\r
8135 #define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
\r
8136 #define ETH_MTLTQDR_TXQSTS_Pos (4U)
\r
8137 #define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
\r
8138 #define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
\r
8139 #define ETH_MTLTQDR_TWCSTS_Pos (3U)
\r
8140 #define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
\r
8141 #define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
\r
8142 #define ETH_MTLTQDR_TRCSTS_Pos (1U)
\r
8143 #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
\r
8144 #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
\r
8145 #define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
\r
8146 #define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
\r
8147 #define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
\r
8148 #define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
\r
8149 #define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
\r
8150 #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
\r
8151 #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
\r
8153 /* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
\r
8154 #define ETH_MTLQICSR_RXOIE_Pos (24U)
\r
8155 #define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
\r
8156 #define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
\r
8157 #define ETH_MTLQICSR_RXOVFIS_Pos (16U)
\r
8158 #define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
\r
8159 #define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
\r
8160 #define ETH_MTLQICSR_TXUIE_Pos (8U)
\r
8161 #define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
\r
8162 #define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
\r
8163 #define ETH_MTLQICSR_TXUNFIS_Pos (0U)
\r
8164 #define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
\r
8165 #define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
\r
8167 /* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
\r
8168 #define ETH_MTLRQOMR_RQS_Pos (20U)
\r
8169 #define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
\r
8170 #define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
\r
8171 #define ETH_MTLRQOMR_RFD_Pos (14U)
\r
8172 #define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
\r
8173 #define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
\r
8174 #define ETH_MTLRQOMR_RFA_Pos (8U)
\r
8175 #define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
\r
8176 #define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
\r
8177 #define ETH_MTLRQOMR_EHFC_Pos (7U)
\r
8178 #define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
\r
8179 #define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
\r
8180 #define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
\r
8181 #define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
\r
8182 #define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
\r
8183 #define ETH_MTLRQOMR_RSF_Pos (5U)
\r
8184 #define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
\r
8185 #define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
\r
8186 #define ETH_MTLRQOMR_FEP_Pos (4U)
\r
8187 #define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
\r
8188 #define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
\r
8189 #define ETH_MTLRQOMR_FUP_Pos (3U)
\r
8190 #define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
\r
8191 #define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
\r
8192 #define ETH_MTLRQOMR_RTC_Pos (0U)
\r
8193 #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
\r
8194 #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
\r
8195 #define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
\r
8196 #define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
\r
8197 #define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
\r
8198 #define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
\r
8200 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
\r
8201 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
\r
8202 #define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
\r
8203 #define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
\r
8204 #define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
\r
8205 #define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
\r
8206 #define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
\r
8207 #define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
\r
8208 #define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
\r
8209 #define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
\r
8210 #define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
\r
8211 #define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
\r
8212 #define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
\r
8214 /* Bit definition for Ethernet MTL Rx Queue Debug Register */
\r
8215 #define ETH_MTLRQDR_PRXQ_Pos (16U)
\r
8216 #define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
\r
8217 #define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
\r
8218 #define ETH_MTLRQDR_RXQSTS_Pos (4U)
\r
8219 #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
\r
8220 #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
\r
8221 #define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
\r
8222 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
\r
8223 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
\r
8224 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
\r
8225 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
\r
8226 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
\r
8227 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
\r
8228 #define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
\r
8229 #define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
\r
8230 #define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
\r
8231 #define ETH_MTLRQDR_RRCSTS_Pos (1U)
\r
8232 #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
\r
8233 #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
\r
8234 #define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
\r
8235 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
\r
8236 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
\r
8237 #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
\r
8238 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
\r
8239 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
\r
8240 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
\r
8241 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
\r
8242 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
\r
8243 #define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
\r
8244 #define ETH_MTLRQDR_RWCSTS_Pos (0U)
\r
8245 #define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
\r
8246 #define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
\r
8248 /* Bit definition for Ethernet MTL Rx Queue Control Register */
\r
8249 #define ETH_MTLRQCR_RQPA_Pos (3U)
\r
8250 #define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
\r
8251 #define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
\r
8252 #define ETH_MTLRQCR_RQW_Pos (0U)
\r
8253 #define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
\r
8254 #define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
\r
8256 /* Bit definition for Ethernet DMA Mode Register */
\r
8257 #define ETH_DMAMR_INTM_Pos (16U)
\r
8258 #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
\r
8259 #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
\r
8260 #define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
\r
8261 #define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
\r
8262 #define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
\r
8263 #define ETH_DMAMR_PR_Pos (12U)
\r
8264 #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
\r
8265 #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
\r
8266 #define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
\r
8267 #define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
\r
8268 #define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
\r
8269 #define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
\r
8270 #define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
\r
8271 #define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
\r
8272 #define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
\r
8273 #define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
\r
8274 #define ETH_DMAMR_TXPR_Pos (11U)
\r
8275 #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
\r
8276 #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
\r
8277 #define ETH_DMAMR_DA_Pos (1U)
\r
8278 #define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
\r
8279 #define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
\r
8280 #define ETH_DMAMR_SWR_Pos (0U)
\r
8281 #define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
\r
8282 #define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
\r
8284 /* Bit definition for Ethernet DMA SysBus Mode Register */
\r
8285 #define ETH_DMASBMR_RB_Pos (15U)
\r
8286 #define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
\r
8287 #define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
\r
8288 #define ETH_DMASBMR_MB_Pos (14U)
\r
8289 #define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
\r
8290 #define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
\r
8291 #define ETH_DMASBMR_AAL_Pos (12U)
\r
8292 #define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
\r
8293 #define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
\r
8294 #define ETH_DMASBMR_FB_Pos (0U)
\r
8295 #define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
\r
8296 #define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
\r
8298 /* Bit definition for Ethernet DMA Interrupt Status Register */
\r
8299 #define ETH_DMAISR_MACIS_Pos (17U)
\r
8300 #define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
\r
8301 #define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
\r
8302 #define ETH_DMAISR_MTLIS_Pos (16U)
\r
8303 #define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
\r
8304 #define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
\r
8305 #define ETH_DMAISR_DMACIS_Pos (0U)
\r
8306 #define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
\r
8307 #define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
\r
8309 /* Bit definition for Ethernet DMA Debug Status Register */
\r
8310 #define ETH_DMADSR_TPS_Pos (12U)
\r
8311 #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
\r
8312 #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
\r
8313 #define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
\r
8314 #define ETH_DMADSR_TPS_FETCHING_Pos (12U)
\r
8315 #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
\r
8316 #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
\r
8317 #define ETH_DMADSR_TPS_WAITING_Pos (13U)
\r
8318 #define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
\r
8319 #define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
\r
8320 #define ETH_DMADSR_TPS_READING_Pos (12U)
\r
8321 #define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
\r
8322 #define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
\r
8323 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
\r
8324 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
\r
8325 #define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
\r
8326 #define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
\r
8327 #define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
\r
8328 #define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
\r
8329 #define ETH_DMADSR_TPS_CLOSING_Pos (12U)
\r
8330 #define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
\r
8331 #define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
\r
8332 #define ETH_DMADSR_RPS_Pos (8U)
\r
8333 #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
\r
8334 #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
\r
8335 #define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
\r
8336 #define ETH_DMADSR_RPS_FETCHING_Pos (12U)
\r
8337 #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
\r
8338 #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
\r
8339 #define ETH_DMADSR_RPS_WAITING_Pos (12U)
\r
8340 #define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
\r
8341 #define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
\r
8342 #define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
\r
8343 #define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
\r
8344 #define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
\r
8345 #define ETH_DMADSR_RPS_CLOSING_Pos (12U)
\r
8346 #define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
\r
8347 #define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
\r
8348 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
\r
8349 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
\r
8350 #define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
\r
8351 #define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
\r
8352 #define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
\r
8353 #define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
\r
8355 /* Bit definition for Ethernet DMA Channel Control Register */
\r
8356 #define ETH_DMACCR_DSL_Pos (18U)
\r
8357 #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
\r
8358 #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
\r
8359 #define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
\r
8360 #define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
\r
8361 #define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
\r
8362 #define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
\r
8363 #define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
\r
8364 #define ETH_DMACCR_MSS_Pos (0U)
\r
8365 #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
\r
8366 #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
\r
8368 /* Bit definition for Ethernet DMA Channel Tx Control Register */
\r
8369 #define ETH_DMACTCR_TPBL_Pos (16U)
\r
8370 #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
\r
8371 #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
\r
8372 #define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
\r
8373 #define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
\r
8374 #define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
\r
8375 #define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
\r
8376 #define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
\r
8377 #define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
\r
8378 #define ETH_DMACTCR_TSE_Pos (12U)
\r
8379 #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
\r
8380 #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
\r
8381 #define ETH_DMACTCR_OSP_Pos (4U)
\r
8382 #define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
\r
8383 #define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
\r
8384 #define ETH_DMACTCR_ST_Pos (0U)
\r
8385 #define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
\r
8386 #define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
\r
8388 /* Bit definition for Ethernet DMA Channel Rx Control Register */
\r
8389 #define ETH_DMACRCR_RPF_Pos (31U)
\r
8390 #define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
\r
8391 #define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
\r
8392 #define ETH_DMACRCR_RPBL_Pos (16U)
\r
8393 #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
\r
8394 #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
\r
8395 #define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
\r
8396 #define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
\r
8397 #define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
\r
8398 #define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
\r
8399 #define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
\r
8400 #define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
\r
8401 #define ETH_DMACRCR_RBSZ_Pos (1U)
\r
8402 #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
\r
8403 #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
\r
8404 #define ETH_DMACRCR_SR_Pos (0U)
\r
8405 #define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
\r
8406 #define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
\r
8408 /* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
\r
8409 #define ETH_DMACTDLAR_TDESLA_Pos (2U)
\r
8410 #define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
\r
8411 #define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
\r
8413 /* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
\r
8414 #define ETH_DMACRDLAR_RDESLA_Pos (2U)
\r
8415 #define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
\r
8416 #define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
\r
8418 /* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
\r
8419 #define ETH_DMACTDTPR_TDT_Pos (2U)
\r
8420 #define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
\r
8421 #define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
\r
8423 /* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
\r
8424 #define ETH_DMACRDTPR_RDT_Pos (2U)
\r
8425 #define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
\r
8426 #define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
\r
8428 /* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
\r
8429 #define ETH_DMACTDRLR_TDRL_Pos (0U)
\r
8430 #define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
\r
8431 #define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
\r
8433 /* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
\r
8434 #define ETH_DMACRDRLR_RDRL_Pos (0U)
\r
8435 #define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
\r
8436 #define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
\r
8438 /* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
\r
8439 #define ETH_DMACIER_NIE_Pos (15U)
\r
8440 #define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
\r
8441 #define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
\r
8442 #define ETH_DMACIER_AIE_Pos (14U)
\r
8443 #define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
\r
8444 #define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
\r
8445 #define ETH_DMACIER_CDEE_Pos (13U)
\r
8446 #define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
\r
8447 #define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
\r
8448 #define ETH_DMACIER_FBEE_Pos (12U)
\r
8449 #define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
\r
8450 #define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
\r
8451 #define ETH_DMACIER_ERIE_Pos (11U)
\r
8452 #define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
\r
8453 #define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
\r
8454 #define ETH_DMACIER_ETIE_Pos (10U)
\r
8455 #define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
\r
8456 #define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
\r
8457 #define ETH_DMACIER_RWTE_Pos (9U)
\r
8458 #define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
\r
8459 #define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
\r
8460 #define ETH_DMACIER_RSE_Pos (8U)
\r
8461 #define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
\r
8462 #define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
\r
8463 #define ETH_DMACIER_RBUE_Pos (7U)
\r
8464 #define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
\r
8465 #define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
\r
8466 #define ETH_DMACIER_RIE_Pos (6U)
\r
8467 #define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
\r
8468 #define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
\r
8469 #define ETH_DMACIER_TBUE_Pos (2U)
\r
8470 #define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
\r
8471 #define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
\r
8472 #define ETH_DMACIER_TXSE_Pos (1U)
\r
8473 #define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
\r
8474 #define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
\r
8475 #define ETH_DMACIER_TIE_Pos (0U)
\r
8476 #define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
\r
8477 #define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
\r
8479 /* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
\r
8480 #define ETH_DMACRIWTR_RWT_Pos (0U)
\r
8481 #define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
\r
8482 #define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
\r
8484 /* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
\r
8485 #define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
\r
8486 #define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
\r
8487 #define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
\r
8489 /* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
\r
8490 #define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
\r
8491 #define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
\r
8492 #define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
\r
8494 /* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
\r
8495 #define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
\r
8496 #define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
\r
8497 #define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
\r
8499 /* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
\r
8500 #define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
\r
8501 #define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
\r
8502 #define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
\r
8504 /* Bit definition for Ethernet DMA Channel Status Register */
\r
8505 #define ETH_DMACSR_REB_Pos (19U)
\r
8506 #define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
\r
8507 #define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
\r
8508 #define ETH_DMACSR_TEB_Pos (16U)
\r
8509 #define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
\r
8510 #define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
\r
8511 #define ETH_DMACSR_NIS_Pos (15U)
\r
8512 #define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
\r
8513 #define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
\r
8514 #define ETH_DMACSR_AIS_Pos (14U)
\r
8515 #define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
\r
8516 #define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
\r
8517 #define ETH_DMACSR_CDE_Pos (13U)
\r
8518 #define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
\r
8519 #define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
\r
8520 #define ETH_DMACSR_FBE_Pos (12U)
\r
8521 #define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
\r
8522 #define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
\r
8523 #define ETH_DMACSR_ERI_Pos (11U)
\r
8524 #define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
\r
8525 #define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
\r
8526 #define ETH_DMACSR_ETI_Pos (10U)
\r
8527 #define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
\r
8528 #define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
\r
8529 #define ETH_DMACSR_RWT_Pos (9U)
\r
8530 #define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
\r
8531 #define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
\r
8532 #define ETH_DMACSR_RPS_Pos (8U)
\r
8533 #define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
\r
8534 #define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
\r
8535 #define ETH_DMACSR_RBU_Pos (7U)
\r
8536 #define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
\r
8537 #define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
\r
8538 #define ETH_DMACSR_RI_Pos (6U)
\r
8539 #define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
\r
8540 #define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
\r
8541 #define ETH_DMACSR_TBU_Pos (2U)
\r
8542 #define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
\r
8543 #define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
\r
8544 #define ETH_DMACSR_TPS_Pos (1U)
\r
8545 #define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
\r
8546 #define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
\r
8547 #define ETH_DMACSR_TI_Pos (0U)
\r
8548 #define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
\r
8549 #define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
\r
8551 /* Bit definition for Ethernet DMA Channel missed frame count register */
\r
8552 #define ETH_DMACMFCR_MFCO_Pos (15U)
\r
8553 #define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
\r
8554 #define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
\r
8555 #define ETH_DMACMFCR_MFC_Pos (0U)
\r
8556 #define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
\r
8557 #define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
\r
8559 /******************************************************************************/
\r
8561 /* DMA Controller */
\r
8563 /******************************************************************************/
\r
8564 /******************** Bits definition for DMA_SxCR register *****************/
\r
8565 #define DMA_SxCR_MBURST_Pos (23U)
\r
8566 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
\r
8567 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk /*!< Memory burst transfer configuration */
\r
8568 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
\r
8569 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
\r
8570 #define DMA_SxCR_PBURST_Pos (21U)
\r
8571 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
\r
8572 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
\r
8573 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
\r
8574 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
\r
8575 #define DMA_SxCR_CT_Pos (19U)
\r
8576 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
\r
8577 #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
\r
8578 #define DMA_SxCR_DBM_Pos (18U)
\r
8579 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
\r
8580 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk /*!< Double buffer mode */
\r
8581 #define DMA_SxCR_PL_Pos (16U)
\r
8582 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
\r
8583 #define DMA_SxCR_PL DMA_SxCR_PL_Msk /*!< Priority level */
\r
8584 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
\r
8585 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
\r
8586 #define DMA_SxCR_PINCOS_Pos (15U)
\r
8587 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
\r
8588 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk /*!< Peripheral increment offset size */
\r
8589 #define DMA_SxCR_MSIZE_Pos (13U)
\r
8590 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
\r
8591 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk /*!< Memory data size */
\r
8592 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
\r
8593 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
\r
8594 #define DMA_SxCR_PSIZE_Pos (11U)
\r
8595 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
\r
8596 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
\r
8597 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
\r
8598 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
\r
8599 #define DMA_SxCR_MINC_Pos (10U)
\r
8600 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
\r
8601 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk /*!< Memory increment mode */
\r
8602 #define DMA_SxCR_PINC_Pos (9U)
\r
8603 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
\r
8604 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk /*!< Peripheral increment mode */
\r
8605 #define DMA_SxCR_CIRC_Pos (8U)
\r
8606 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
\r
8607 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk /*!< Circular mode */
\r
8608 #define DMA_SxCR_DIR_Pos (6U)
\r
8609 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
\r
8610 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk /*!< Data transfer direction */
\r
8611 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
\r
8612 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
\r
8613 #define DMA_SxCR_PFCTRL_Pos (5U)
\r
8614 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
\r
8615 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk /*!< Peripheral flow controller */
\r
8616 #define DMA_SxCR_TCIE_Pos (4U)
\r
8617 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
\r
8618 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk /*!< Transfer complete interrupt enable */
\r
8619 #define DMA_SxCR_HTIE_Pos (3U)
\r
8620 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
\r
8621 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk /*!< Half transfer interrupt enable */
\r
8622 #define DMA_SxCR_TEIE_Pos (2U)
\r
8623 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
\r
8624 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk /*!< Transfer error interrupt enable */
\r
8625 #define DMA_SxCR_DMEIE_Pos (1U)
\r
8626 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
\r
8627 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk /*!< Direct mode error interrupt enable */
\r
8628 #define DMA_SxCR_EN_Pos (0U)
\r
8629 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
\r
8630 #define DMA_SxCR_EN DMA_SxCR_EN_Msk /*!< Stream enable / flag stream ready when read low */
\r
8632 /******************** Bits definition for DMA_SxCNDTR register **************/
\r
8633 #define DMA_SxNDT_Pos (0U)
\r
8634 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
\r
8635 #define DMA_SxNDT DMA_SxNDT_Msk /*!< Number of data items to transfer */
\r
8636 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
\r
8637 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
\r
8638 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
\r
8639 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
\r
8640 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
\r
8641 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
\r
8642 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
\r
8643 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
\r
8644 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
\r
8645 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
\r
8646 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
\r
8647 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
\r
8648 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
\r
8649 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
\r
8650 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
\r
8651 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
\r
8653 /******************** Bits definition for DMA_SxFCR register ****************/
\r
8654 #define DMA_SxFCR_FEIE_Pos (7U)
\r
8655 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
\r
8656 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk /*!< FIFO error interrupt enable */
\r
8657 #define DMA_SxFCR_FS_Pos (3U)
\r
8658 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
\r
8659 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk /*!< FIFO status */
\r
8660 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
\r
8661 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
\r
8662 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
\r
8663 #define DMA_SxFCR_DMDIS_Pos (2U)
\r
8664 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
\r
8665 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk /*!< Direct mode disable */
\r
8666 #define DMA_SxFCR_FTH_Pos (0U)
\r
8667 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
\r
8668 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk /*!< FIFO threshold selection */
\r
8669 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
\r
8670 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
\r
8672 /******************** Bits definition for DMA_LISR register *****************/
\r
8673 #define DMA_LISR_TCIF3_Pos (27U)
\r
8674 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
\r
8675 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk /*!< Stream 3 transfer complete interrupt flag */
\r
8676 #define DMA_LISR_HTIF3_Pos (26U)
\r
8677 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
\r
8678 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk /*!< Stream 3 half transfer interrupt flag */
\r
8679 #define DMA_LISR_TEIF3_Pos (25U)
\r
8680 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
\r
8681 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk /*!< Stream 3 transfer error interrupt flag */
\r
8682 #define DMA_LISR_DMEIF3_Pos (24U)
\r
8683 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
\r
8684 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk /*!< Stream 3 direct mode error interrupt flag */
\r
8685 #define DMA_LISR_FEIF3_Pos (22U)
\r
8686 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
\r
8687 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk /*!< Stream 3 FIFO error interrupt flag */
\r
8688 #define DMA_LISR_TCIF2_Pos (21U)
\r
8689 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
\r
8690 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk /*!< Stream 2 transfer complete interrupt flag */
\r
8691 #define DMA_LISR_HTIF2_Pos (20U)
\r
8692 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
\r
8693 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk /*!< Stream 2 half transfer interrupt flag */
\r
8694 #define DMA_LISR_TEIF2_Pos (19U)
\r
8695 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
\r
8696 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk /*!< Stream 2 transfer error interrupt flag */
\r
8697 #define DMA_LISR_DMEIF2_Pos (18U)
\r
8698 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
\r
8699 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk /*!< Stream 2 direct mode error interrupt flag */
\r
8700 #define DMA_LISR_FEIF2_Pos (16U)
\r
8701 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
\r
8702 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk /*!< Stream 2 FIFO error interrupt flag */
\r
8703 #define DMA_LISR_TCIF1_Pos (11U)
\r
8704 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
\r
8705 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk /*!< Stream 1 transfer complete interrupt flag */
\r
8706 #define DMA_LISR_HTIF1_Pos (10U)
\r
8707 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
\r
8708 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk /*!< Stream 1 half transfer interrupt flag */
\r
8709 #define DMA_LISR_TEIF1_Pos (9U)
\r
8710 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
\r
8711 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk /*!< Stream 1 transfer error interrupt flag */
\r
8712 #define DMA_LISR_DMEIF1_Pos (8U)
\r
8713 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
\r
8714 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk /*!< Stream 1 direct mode error interrupt flag */
\r
8715 #define DMA_LISR_FEIF1_Pos (6U)
\r
8716 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
\r
8717 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk /*!< Stream 1 FIFO error interrupt flag */
\r
8718 #define DMA_LISR_TCIF0_Pos (5U)
\r
8719 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
\r
8720 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk /*!< Stream 0 transfer complete interrupt flag */
\r
8721 #define DMA_LISR_HTIF0_Pos (4U)
\r
8722 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
\r
8723 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk /*!< Stream 0 half transfer interrupt flag */
\r
8724 #define DMA_LISR_TEIF0_Pos (3U)
\r
8725 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
\r
8726 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk /*!< Stream 0 transfer error interrupt flag */
\r
8727 #define DMA_LISR_DMEIF0_Pos (2U)
\r
8728 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
\r
8729 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk /*!< Stream 0 direct mode error interrupt flag */
\r
8730 #define DMA_LISR_FEIF0_Pos (0U)
\r
8731 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
\r
8732 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /*!< Stream 0 FIFO error interrupt flag */
\r
8734 /******************** Bits definition for DMA_HISR register *****************/
\r
8735 #define DMA_HISR_TCIF7_Pos (27U)
\r
8736 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
\r
8737 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk /*!< Stream 7 transfer complete interrupt flag */
\r
8738 #define DMA_HISR_HTIF7_Pos (26U)
\r
8739 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
\r
8740 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk /*!< Stream 7 half transfer interrupt flag */
\r
8741 #define DMA_HISR_TEIF7_Pos (25U)
\r
8742 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
\r
8743 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk /*!< Stream 7 transfer error interrupt flag */
\r
8744 #define DMA_HISR_DMEIF7_Pos (24U)
\r
8745 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
\r
8746 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk /*!< Stream 7 direct mode error interrupt flag */
\r
8747 #define DMA_HISR_FEIF7_Pos (22U)
\r
8748 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
\r
8749 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk /*!< Stream 7 FIFO error interrupt flag */
\r
8750 #define DMA_HISR_TCIF6_Pos (21U)
\r
8751 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
\r
8752 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk /*!< Stream 6 transfer complete interrupt flag */
\r
8753 #define DMA_HISR_HTIF6_Pos (20U)
\r
8754 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
\r
8755 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk /*!< Stream 6 half transfer interrupt flag */
\r
8756 #define DMA_HISR_TEIF6_Pos (19U)
\r
8757 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
\r
8758 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk /*!< Stream 6 transfer error interrupt flag */
\r
8759 #define DMA_HISR_DMEIF6_Pos (18U)
\r
8760 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
\r
8761 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk /*!< Stream 6 direct mode error interrupt flag */
\r
8762 #define DMA_HISR_FEIF6_Pos (16U)
\r
8763 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
\r
8764 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk /*!< Stream 6 FIFO error interrupt flag */
\r
8765 #define DMA_HISR_TCIF5_Pos (11U)
\r
8766 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
\r
8767 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk /*!< Stream 5 transfer complete interrupt flag */
\r
8768 #define DMA_HISR_HTIF5_Pos (10U)
\r
8769 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
\r
8770 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk /*!< Stream 5 half transfer interrupt flag */
\r
8771 #define DMA_HISR_TEIF5_Pos (9U)
\r
8772 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
\r
8773 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk /*!< Stream 5 transfer error interrupt flag */
\r
8774 #define DMA_HISR_DMEIF5_Pos (8U)
\r
8775 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
\r
8776 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk /*!< Stream 5 direct mode error interrupt flag */
\r
8777 #define DMA_HISR_FEIF5_Pos (6U)
\r
8778 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
\r
8779 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk /*!< Stream 5 FIFO error interrupt flag */
\r
8780 #define DMA_HISR_TCIF4_Pos (5U)
\r
8781 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
\r
8782 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk /*!< Stream 4 transfer complete interrupt flag */
\r
8783 #define DMA_HISR_HTIF4_Pos (4U)
\r
8784 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
\r
8785 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk /*!< Stream 4 half transfer interrupt flag */
\r
8786 #define DMA_HISR_TEIF4_Pos (3U)
\r
8787 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
\r
8788 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk /*!< Stream 4 transfer error interrupt flag */
\r
8789 #define DMA_HISR_DMEIF4_Pos (2U)
\r
8790 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
\r
8791 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk /*!< Stream 4 direct mode error interrupt flag */
\r
8792 #define DMA_HISR_FEIF4_Pos (0U)
\r
8793 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
\r
8794 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /*!< Stream 4 FIFO error interrupt flag */
\r
8796 /******************** Bits definition for DMA_LIFCR register ****************/
\r
8797 #define DMA_LIFCR_CTCIF3_Pos (27U)
\r
8798 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
\r
8799 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk /*!< Stream 3 clear transfer complete interrupt flag */
\r
8800 #define DMA_LIFCR_CHTIF3_Pos (26U)
\r
8801 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
\r
8802 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk /*!< Stream 3 clear half transfer interrupt flag */
\r
8803 #define DMA_LIFCR_CTEIF3_Pos (25U)
\r
8804 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
\r
8805 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk /*!< Stream 3 clear transfer error interrupt flag */
\r
8806 #define DMA_LIFCR_CDMEIF3_Pos (24U)
\r
8807 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
\r
8808 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk /*!< Stream 3 clear direct mode error interrupt flag */
\r
8809 #define DMA_LIFCR_CFEIF3_Pos (22U)
\r
8810 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
\r
8811 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk /*!< Stream 3 clear FIFO error interrupt flag */
\r
8812 #define DMA_LIFCR_CTCIF2_Pos (21U)
\r
8813 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
\r
8814 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk /*!< Stream 2 clear transfer complete interrupt flag */
\r
8815 #define DMA_LIFCR_CHTIF2_Pos (20U)
\r
8816 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
\r
8817 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk /*!< Stream 2 clear half transfer interrupt flag */
\r
8818 #define DMA_LIFCR_CTEIF2_Pos (19U)
\r
8819 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
\r
8820 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk /*!< Stream 2 clear transfer error interrupt flag */
\r
8821 #define DMA_LIFCR_CDMEIF2_Pos (18U)
\r
8822 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
\r
8823 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk /*!< Stream 2 clear direct mode error interrupt flag */
\r
8824 #define DMA_LIFCR_CFEIF2_Pos (16U)
\r
8825 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
\r
8826 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk /*!< Stream 2 clear FIFO error interrupt flag */
\r
8827 #define DMA_LIFCR_CTCIF1_Pos (11U)
\r
8828 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
\r
8829 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk /*!< Stream 1 clear transfer complete interrupt flag */
\r
8830 #define DMA_LIFCR_CHTIF1_Pos (10U)
\r
8831 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
\r
8832 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk /*!< Stream 1 clear half transfer interrupt flag */
\r
8833 #define DMA_LIFCR_CTEIF1_Pos (9U)
\r
8834 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
\r
8835 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk /*!< Stream 1 clear transfer error interrupt flag */
\r
8836 #define DMA_LIFCR_CDMEIF1_Pos (8U)
\r
8837 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
\r
8838 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk /*!< Stream 1 clear direct mode error interrupt flag */
\r
8839 #define DMA_LIFCR_CFEIF1_Pos (6U)
\r
8840 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
\r
8841 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk /*!< Stream 1 clear FIFO error interrupt flag */
\r
8842 #define DMA_LIFCR_CTCIF0_Pos (5U)
\r
8843 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
\r
8844 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk /*!< Stream 0 clear transfer complete interrupt flag */
\r
8845 #define DMA_LIFCR_CHTIF0_Pos (4U)
\r
8846 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
\r
8847 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk /*!< Stream 0 clear half transfer interrupt flag */
\r
8848 #define DMA_LIFCR_CTEIF0_Pos (3U)
\r
8849 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
\r
8850 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk /*!< Stream 0 clear transfer error interrupt flag */
\r
8851 #define DMA_LIFCR_CDMEIF0_Pos (2U)
\r
8852 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
\r
8853 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk /*!< Stream 0 clear direct mode error interrupt flag */
\r
8854 #define DMA_LIFCR_CFEIF0_Pos (0U)
\r
8855 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
\r
8856 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /*!< Stream 0 clear FIFO error interrupt flag */
\r
8858 /******************** Bits definition for DMA_HIFCR register ****************/
\r
8859 #define DMA_HIFCR_CTCIF7_Pos (27U)
\r
8860 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
\r
8861 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk /*!< Stream 7 clear transfer complete interrupt flag */
\r
8862 #define DMA_HIFCR_CHTIF7_Pos (26U)
\r
8863 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
\r
8864 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk /*!< Stream 7 clear half transfer interrupt flag */
\r
8865 #define DMA_HIFCR_CTEIF7_Pos (25U)
\r
8866 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
\r
8867 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk /*!< Stream 7 clear transfer error interrupt flag */
\r
8868 #define DMA_HIFCR_CDMEIF7_Pos (24U)
\r
8869 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
\r
8870 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk /*!< Stream 7 clear direct mode error interrupt flag */
\r
8871 #define DMA_HIFCR_CFEIF7_Pos (22U)
\r
8872 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
\r
8873 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk /*!< Stream 7 clear FIFO error interrupt flag */
\r
8874 #define DMA_HIFCR_CTCIF6_Pos (21U)
\r
8875 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
\r
8876 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk /*!< Stream 6 clear transfer complete interrupt flag */
\r
8877 #define DMA_HIFCR_CHTIF6_Pos (20U)
\r
8878 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
\r
8879 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk /*!< Stream 6 clear half transfer interrupt flag */
\r
8880 #define DMA_HIFCR_CTEIF6_Pos (19U)
\r
8881 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
\r
8882 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk /*!< Stream 6 clear transfer error interrupt flag */
\r
8883 #define DMA_HIFCR_CDMEIF6_Pos (18U)
\r
8884 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
\r
8885 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk /*!< Stream 6 clear direct mode error interrupt flag */
\r
8886 #define DMA_HIFCR_CFEIF6_Pos (16U)
\r
8887 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
\r
8888 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk /*!< Stream 6 clear FIFO error interrupt flag */
\r
8889 #define DMA_HIFCR_CTCIF5_Pos (11U)
\r
8890 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
\r
8891 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk /*!< Stream 5 clear transfer complete interrupt flag */
\r
8892 #define DMA_HIFCR_CHTIF5_Pos (10U)
\r
8893 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
\r
8894 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk /*!< Stream 5 clear half transfer interrupt flag */
\r
8895 #define DMA_HIFCR_CTEIF5_Pos (9U)
\r
8896 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
\r
8897 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk /*!< Stream 5 clear transfer error interrupt flag */
\r
8898 #define DMA_HIFCR_CDMEIF5_Pos (8U)
\r
8899 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
\r
8900 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk /*!< Stream 5 clear direct mode error interrupt flag */
\r
8901 #define DMA_HIFCR_CFEIF5_Pos (6U)
\r
8902 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
\r
8903 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk /*!< Stream 5 clear FIFO error interrupt flag */
\r
8904 #define DMA_HIFCR_CTCIF4_Pos (5U)
\r
8905 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
\r
8906 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk /*!< Stream 4 clear transfer complete interrupt flag */
\r
8907 #define DMA_HIFCR_CHTIF4_Pos (4U)
\r
8908 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
\r
8909 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk /*!< Stream 4 clear half transfer interrupt flag */
\r
8910 #define DMA_HIFCR_CTEIF4_Pos (3U)
\r
8911 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
\r
8912 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk /*!< Stream 4 clear transfer error interrupt flag */
\r
8913 #define DMA_HIFCR_CDMEIF4_Pos (2U)
\r
8914 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
\r
8915 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk /*!< Stream 4 clear direct mode error interrupt flag */
\r
8916 #define DMA_HIFCR_CFEIF4_Pos (0U)
\r
8917 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
\r
8918 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /*!< Stream 4 clear FIFO error interrupt flag */
\r
8920 /****************** Bit definition for DMA_SxPAR register ********************/
\r
8921 #define DMA_SxPAR_PA_Pos (0U)
\r
8922 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
\r
8923 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
\r
8925 /****************** Bit definition for DMA_SxM0AR register ********************/
\r
8926 #define DMA_SxM0AR_M0A_Pos (0U)
\r
8927 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
\r
8928 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory 0 Address */
\r
8930 /****************** Bit definition for DMA_SxM1AR register ********************/
\r
8931 #define DMA_SxM1AR_M1A_Pos (0U)
\r
8932 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
\r
8933 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory 1 Address */
\r
8935 /******************************************************************************/
\r
8937 /* DMAMUX Controller */
\r
8939 /******************************************************************************/
\r
8940 /******************** Bits definition for DMAMUX_CxCR register **************/
\r
8941 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
\r
8942 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
\r
8943 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA request identification */
\r
8944 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
\r
8945 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
\r
8946 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
\r
8947 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
\r
8948 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
\r
8949 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
\r
8950 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
\r
8951 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
\r
8952 #define DMAMUX_CxCR_SOIE_Pos (8U)
\r
8953 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
\r
8954 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchronization overrun interrupt enable */
\r
8955 #define DMAMUX_CxCR_EGE_Pos (9U)
\r
8956 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
\r
8957 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation enable */
\r
8958 #define DMAMUX_CxCR_SE_Pos (16U)
\r
8959 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
\r
8960 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
\r
8961 #define DMAMUX_CxCR_SPOL_Pos (17U)
\r
8962 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
\r
8963 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
\r
8964 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
\r
8965 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
\r
8966 #define DMAMUX_CxCR_NBREQ_Pos (19U)
\r
8967 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
\r
8968 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of DMA requests minus 1 to forward */
\r
8969 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
\r
8970 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
\r
8971 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
\r
8972 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
\r
8973 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
\r
8974 #define DMAMUX_CxCR_SYNC_ID_Pos (24U)
\r
8975 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
\r
8976 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization identification */
\r
8977 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
\r
8978 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
\r
8979 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
\r
8980 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
\r
8981 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
\r
8983 /******************** Bits definition for DMAMUX_CSR register **************/
\r
8984 #define DMAMUX_CSR_SOF0_Pos (0U)
\r
8985 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
\r
8986 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Channel 0 Synchronization overrun event flag */
\r
8987 #define DMAMUX_CSR_SOF1_Pos (1U)
\r
8988 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
\r
8989 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Channel 1 Synchronization overrun event flag */
\r
8990 #define DMAMUX_CSR_SOF2_Pos (2U)
\r
8991 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
\r
8992 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Channel 2 Synchronization overrun event flag */
\r
8993 #define DMAMUX_CSR_SOF3_Pos (3U)
\r
8994 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
\r
8995 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Channel 3 Synchronization overrun event flag */
\r
8996 #define DMAMUX_CSR_SOF4_Pos (4U)
\r
8997 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
\r
8998 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Channel 4 Synchronization overrun event flag */
\r
8999 #define DMAMUX_CSR_SOF5_Pos (5U)
\r
9000 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
\r
9001 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Channel 5 Synchronization overrun event flag */
\r
9002 #define DMAMUX_CSR_SOF6_Pos (6U)
\r
9003 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
\r
9004 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Channel 6 Synchronization overrun event flag */
\r
9005 #define DMAMUX_CSR_SOF7_Pos (7U)
\r
9006 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
\r
9007 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Channel 7 Synchronization overrun event flag */
\r
9008 #define DMAMUX_CSR_SOF8_Pos (8U)
\r
9009 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
\r
9010 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Channel 8 Synchronization overrun event flag */
\r
9011 #define DMAMUX_CSR_SOF9_Pos (9U)
\r
9012 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
\r
9013 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Channel 9 Synchronization overrun event flag */
\r
9014 #define DMAMUX_CSR_SOF10_Pos (10U)
\r
9015 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
\r
9016 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Channel 10 Synchronization overrun event flag */
\r
9017 #define DMAMUX_CSR_SOF11_Pos (11U)
\r
9018 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
\r
9019 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Channel 11 Synchronization overrun event flag */
\r
9020 #define DMAMUX_CSR_SOF12_Pos (12U)
\r
9021 #define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
\r
9022 #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Channel 12 Synchronization overrun event flag */
\r
9023 #define DMAMUX_CSR_SOF13_Pos (13U)
\r
9024 #define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
\r
9025 #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Channel 13 Synchronization overrun event flag */
\r
9026 #define DMAMUX_CSR_SOF14_Pos (14U)
\r
9027 #define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
\r
9028 #define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk /*!< Channel 14 Synchronization overrun event flag */
\r
9029 #define DMAMUX_CSR_SOF15_Pos (15U)
\r
9030 #define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
\r
9031 #define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk /*!< Channel 15 Synchronization overrun event flag */
\r
9033 /******************** Bits definition for DMAMUX_CFR register **************/
\r
9034 #define DMAMUX_CFR_CSOF0_Pos (0U)
\r
9035 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
\r
9036 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Channel 0 Clear synchronization overrun event flag */
\r
9037 #define DMAMUX_CFR_CSOF1_Pos (1U)
\r
9038 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
\r
9039 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Channel 1 Clear synchronization overrun event flag */
\r
9040 #define DMAMUX_CFR_CSOF2_Pos (2U)
\r
9041 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
\r
9042 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Channel 2 Clear synchronization overrun event flag */
\r
9043 #define DMAMUX_CFR_CSOF3_Pos (3U)
\r
9044 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
\r
9045 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Channel 3 Clear synchronization overrun event flag */
\r
9046 #define DMAMUX_CFR_CSOF4_Pos (4U)
\r
9047 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
\r
9048 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Channel 4 Clear synchronization overrun event flag */
\r
9049 #define DMAMUX_CFR_CSOF5_Pos (5U)
\r
9050 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
\r
9051 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Channel 5 Clear synchronization overrun event flag */
\r
9052 #define DMAMUX_CFR_CSOF6_Pos (6U)
\r
9053 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
\r
9054 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Channel 6 Clear synchronization overrun event flag */
\r
9055 #define DMAMUX_CFR_CSOF7_Pos (7U)
\r
9056 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
\r
9057 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Channel 7 Clear synchronization overrun event flag */
\r
9058 #define DMAMUX_CFR_CSOF8_Pos (8U)
\r
9059 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
\r
9060 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Channel 8 Clear synchronization overrun event flag */
\r
9061 #define DMAMUX_CFR_CSOF9_Pos (9U)
\r
9062 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
\r
9063 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Channel 9 Clear synchronization overrun event flag */
\r
9064 #define DMAMUX_CFR_CSOF10_Pos (10U)
\r
9065 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
\r
9066 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Channel 10 Clear synchronization overrun event flag */
\r
9067 #define DMAMUX_CFR_CSOF11_Pos (11U)
\r
9068 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
\r
9069 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Channel 11 Clear synchronization overrun event flag */
\r
9070 #define DMAMUX_CFR_CSOF12_Pos (12U)
\r
9071 #define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
\r
9072 #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Channel 12 Clear synchronization overrun event flag */
\r
9073 #define DMAMUX_CFR_CSOF13_Pos (13U)
\r
9074 #define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
\r
9075 #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Channel 13 Clear synchronization overrun event flag */
\r
9076 #define DMAMUX_CFR_CSOF14_Pos (14U)
\r
9077 #define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
\r
9078 #define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk /*!< Channel 14 Clear synchronization overrun event flag */
\r
9079 #define DMAMUX_CFR_CSOF15_Pos (15U)
\r
9080 #define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
\r
9081 #define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk /*!< Channel 15 Clear synchronization overrun event flag */
\r
9083 /******************** Bits definition for DMAMUX_RGxCR register ************/
\r
9084 #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
\r
9085 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
\r
9086 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal identification */
\r
9087 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
\r
9088 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
\r
9089 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
\r
9090 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
\r
9091 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
\r
9092 #define DMAMUX_RGxCR_OIE_Pos (8U)
\r
9093 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
\r
9094 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Trigger overrun interrupt enable */
\r
9095 #define DMAMUX_RGxCR_GE_Pos (16U)
\r
9096 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
\r
9097 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< DMA request generator enable */
\r
9098 #define DMAMUX_RGxCR_GPOL_Pos (17U)
\r
9099 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
\r
9100 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< DMA request generator trigger polarity */
\r
9101 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
\r
9102 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
\r
9103 #define DMAMUX_RGxCR_GNBREQ_Pos (19U)
\r
9104 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
\r
9105 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
\r
9106 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
\r
9107 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
\r
9108 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
\r
9109 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
\r
9110 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
\r
9112 /******************** Bits definition for DMAMUX_RGSR register **************/
\r
9113 #define DMAMUX_RGSR_OF0_Pos (0U)
\r
9114 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
\r
9115 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Request generator channel 0 Trigger overrun event flag */
\r
9116 #define DMAMUX_RGSR_OF1_Pos (1U)
\r
9117 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
\r
9118 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Request generator channel 1 Trigger overrun event flag */
\r
9119 #define DMAMUX_RGSR_OF2_Pos (2U)
\r
9120 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
\r
9121 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Request generator channel 2 Trigger overrun event flag */
\r
9122 #define DMAMUX_RGSR_OF3_Pos (3U)
\r
9123 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
\r
9124 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Request generator channel 3 Trigger overrun event flag */
\r
9125 #define DMAMUX_RGSR_OF4_Pos (4U)
\r
9126 #define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
\r
9127 #define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk /*!< Request generator channel 4 Trigger overrun event flag */
\r
9128 #define DMAMUX_RGSR_OF5_Pos (5U)
\r
9129 #define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
\r
9130 #define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk /*!< Request generator channel 5 Trigger overrun event flag */
\r
9131 #define DMAMUX_RGSR_OF6_Pos (6U)
\r
9132 #define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
\r
9133 #define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk /*!< Request generator channel 6 Trigger overrun event flag */
\r
9134 #define DMAMUX_RGSR_OF7_Pos (7U)
\r
9135 #define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
\r
9136 #define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk /*!< Request generator channel 7 Trigger overrun event flag */
\r
9138 /******************** Bits definition for DMAMUX_RGCFR register **************/
\r
9139 #define DMAMUX_RGCFR_COF0_Pos (0U)
\r
9140 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
\r
9141 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Request generator channel 0 Clear trigger overrun event flag */
\r
9142 #define DMAMUX_RGCFR_COF1_Pos (1U)
\r
9143 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
\r
9144 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Request generator channel 1 Clear trigger overrun event flag */
\r
9145 #define DMAMUX_RGCFR_COF2_Pos (2U)
\r
9146 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
\r
9147 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Request generator channel 2 Clear trigger overrun event flag */
\r
9148 #define DMAMUX_RGCFR_COF3_Pos (3U)
\r
9149 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
\r
9150 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Request generator channel 3 Clear trigger overrun event flag */
\r
9151 #define DMAMUX_RGCFR_COF4_Pos (4U)
\r
9152 #define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
\r
9153 #define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk /*!< Request generator channel 4 Clear trigger overrun event flag */
\r
9154 #define DMAMUX_RGCFR_COF5_Pos (5U)
\r
9155 #define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
\r
9156 #define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk /*!< Request generator channel 5 Clear trigger overrun event flag */
\r
9157 #define DMAMUX_RGCFR_COF6_Pos (6U)
\r
9158 #define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
\r
9159 #define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk /*!< Request generator channel 6 Clear trigger overrun event flag */
\r
9160 #define DMAMUX_RGCFR_COF7_Pos (7U)
\r
9161 #define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
\r
9162 #define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk /*!< Request generator channel 7 Clear trigger overrun event flag */
\r
9164 /******************************************************************************/
\r
9166 /* AHB Master DMA2D Controller (DMA2D) */
\r
9168 /******************************************************************************/
\r
9170 /******************** Bit definition for DMA2D_CR register ******************/
\r
9172 #define DMA2D_CR_START_Pos (0U)
\r
9173 #define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
\r
9174 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
\r
9175 #define DMA2D_CR_SUSP_Pos (1U)
\r
9176 #define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
\r
9177 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
\r
9178 #define DMA2D_CR_ABORT_Pos (2U)
\r
9179 #define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
\r
9180 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
\r
9181 #define DMA2D_CR_TEIE_Pos (8U)
\r
9182 #define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
\r
9183 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
\r
9184 #define DMA2D_CR_TCIE_Pos (9U)
\r
9185 #define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
\r
9186 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
\r
9187 #define DMA2D_CR_TWIE_Pos (10U)
\r
9188 #define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
\r
9189 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
\r
9190 #define DMA2D_CR_CAEIE_Pos (11U)
\r
9191 #define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
\r
9192 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
\r
9193 #define DMA2D_CR_CTCIE_Pos (12U)
\r
9194 #define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
\r
9195 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
\r
9196 #define DMA2D_CR_CEIE_Pos (13U)
\r
9197 #define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
\r
9198 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
\r
9199 #define DMA2D_CR_MODE_Pos (16U)
\r
9200 #define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
\r
9201 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
\r
9202 #define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
\r
9203 #define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
\r
9205 /******************** Bit definition for DMA2D_ISR register *****************/
\r
9207 #define DMA2D_ISR_TEIF_Pos (0U)
\r
9208 #define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
\r
9209 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
\r
9210 #define DMA2D_ISR_TCIF_Pos (1U)
\r
9211 #define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
\r
9212 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
\r
9213 #define DMA2D_ISR_TWIF_Pos (2U)
\r
9214 #define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
\r
9215 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
\r
9216 #define DMA2D_ISR_CAEIF_Pos (3U)
\r
9217 #define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
\r
9218 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
\r
9219 #define DMA2D_ISR_CTCIF_Pos (4U)
\r
9220 #define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
\r
9221 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
\r
9222 #define DMA2D_ISR_CEIF_Pos (5U)
\r
9223 #define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
\r
9224 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
\r
9226 /******************** Bit definition for DMA2D_IFCR register ****************/
\r
9228 #define DMA2D_IFCR_CTEIF_Pos (0U)
\r
9229 #define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
\r
9230 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
\r
9231 #define DMA2D_IFCR_CTCIF_Pos (1U)
\r
9232 #define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
\r
9233 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
\r
9234 #define DMA2D_IFCR_CTWIF_Pos (2U)
\r
9235 #define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
\r
9236 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
\r
9237 #define DMA2D_IFCR_CAECIF_Pos (3U)
\r
9238 #define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
\r
9239 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
\r
9240 #define DMA2D_IFCR_CCTCIF_Pos (4U)
\r
9241 #define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
\r
9242 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
\r
9243 #define DMA2D_IFCR_CCEIF_Pos (5U)
\r
9244 #define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
\r
9245 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
\r
9247 /******************** Bit definition for DMA2D_FGMAR register ***************/
\r
9249 #define DMA2D_FGMAR_MA_Pos (0U)
\r
9250 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
\r
9251 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */
\r
9253 /******************** Bit definition for DMA2D_FGOR register ****************/
\r
9255 #define DMA2D_FGOR_LO_Pos (0U)
\r
9256 #define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
\r
9257 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
\r
9259 /******************** Bit definition for DMA2D_BGMAR register ***************/
\r
9261 #define DMA2D_BGMAR_MA_Pos (0U)
\r
9262 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
\r
9263 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */
\r
9265 /******************** Bit definition for DMA2D_BGOR register ****************/
\r
9267 #define DMA2D_BGOR_LO_Pos (0U)
\r
9268 #define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
\r
9269 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
\r
9271 /******************** Bit definition for DMA2D_FGPFCCR register *************/
\r
9273 #define DMA2D_FGPFCCR_CM_Pos (0U)
\r
9274 #define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
\r
9275 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
\r
9276 #define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
\r
9277 #define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
\r
9278 #define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
\r
9279 #define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
\r
9280 #define DMA2D_FGPFCCR_CCM_Pos (4U)
\r
9281 #define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
\r
9282 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
\r
9283 #define DMA2D_FGPFCCR_START_Pos (5U)
\r
9284 #define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
\r
9285 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
\r
9286 #define DMA2D_FGPFCCR_CS_Pos (8U)
\r
9287 #define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
\r
9288 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
\r
9289 #define DMA2D_FGPFCCR_AM_Pos (16U)
\r
9290 #define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
\r
9291 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
\r
9292 #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
\r
9293 #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
\r
9294 #define DMA2D_FGPFCCR_CSS_Pos (18U)
\r
9295 #define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
\r
9296 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
\r
9297 #define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
\r
9298 #define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
\r
9299 #define DMA2D_FGPFCCR_AI_Pos (20U)
\r
9300 #define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
\r
9301 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
\r
9302 #define DMA2D_FGPFCCR_RBS_Pos (21U)
\r
9303 #define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
\r
9304 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
\r
9305 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
\r
9306 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
\r
9307 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
\r
9309 /******************** Bit definition for DMA2D_FGCOLR register **************/
\r
9311 #define DMA2D_FGCOLR_BLUE_Pos (0U)
\r
9312 #define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
\r
9313 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */
\r
9314 #define DMA2D_FGCOLR_GREEN_Pos (8U)
\r
9315 #define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
\r
9316 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */
\r
9317 #define DMA2D_FGCOLR_RED_Pos (16U)
\r
9318 #define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
\r
9319 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */
\r
9321 /******************** Bit definition for DMA2D_BGPFCCR register *************/
\r
9323 #define DMA2D_BGPFCCR_CM_Pos (0U)
\r
9324 #define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
\r
9325 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
\r
9326 #define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
\r
9327 #define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
\r
9328 #define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
\r
9329 #define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
\r
9330 #define DMA2D_BGPFCCR_CCM_Pos (4U)
\r
9331 #define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
\r
9332 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
\r
9333 #define DMA2D_BGPFCCR_START_Pos (5U)
\r
9334 #define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
\r
9335 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
\r
9336 #define DMA2D_BGPFCCR_CS_Pos (8U)
\r
9337 #define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
\r
9338 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
\r
9339 #define DMA2D_BGPFCCR_AM_Pos (16U)
\r
9340 #define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
\r
9341 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
\r
9342 #define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
\r
9343 #define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
\r
9344 #define DMA2D_BGPFCCR_AI_Pos (20U)
\r
9345 #define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
\r
9346 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
\r
9347 #define DMA2D_BGPFCCR_RBS_Pos (21U)
\r
9348 #define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
\r
9349 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
\r
9350 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
\r
9351 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
\r
9352 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
\r
9354 /******************** Bit definition for DMA2D_BGCOLR register **************/
\r
9356 #define DMA2D_BGCOLR_BLUE_Pos (0U)
\r
9357 #define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
\r
9358 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */
\r
9359 #define DMA2D_BGCOLR_GREEN_Pos (8U)
\r
9360 #define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
\r
9361 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */
\r
9362 #define DMA2D_BGCOLR_RED_Pos (16U)
\r
9363 #define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
\r
9364 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */
\r
9366 /******************** Bit definition for DMA2D_FGCMAR register **************/
\r
9368 #define DMA2D_FGCMAR_MA_Pos (0U)
\r
9369 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
\r
9370 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */
\r
9372 /******************** Bit definition for DMA2D_BGCMAR register **************/
\r
9374 #define DMA2D_BGCMAR_MA_Pos (0U)
\r
9375 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
\r
9376 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */
\r
9378 /******************** Bit definition for DMA2D_OPFCCR register **************/
\r
9380 #define DMA2D_OPFCCR_CM_Pos (0U)
\r
9381 #define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
\r
9382 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */
\r
9383 #define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
\r
9384 #define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
\r
9385 #define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
\r
9386 #define DMA2D_OPFCCR_AI_Pos (20U)
\r
9387 #define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
\r
9388 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
\r
9389 #define DMA2D_OPFCCR_RBS_Pos (21U)
\r
9390 #define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
\r
9391 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
\r
9393 /******************** Bit definition for DMA2D_OCOLR register ***************/
\r
9395 /*!<Mode_ARGB8888/RGB888 */
\r
9397 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FFU) /*!< Output BLUE Value */
\r
9398 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00U) /*!< Output GREEN Value */
\r
9399 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000U) /*!< Output Red Value */
\r
9400 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000U) /*!< Output Alpha Channel Value */
\r
9402 /*!<Mode_RGB565 */
\r
9403 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */
\r
9404 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0U) /*!< Output GREEN Value */
\r
9405 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800U) /*!< Output Red Value */
\r
9407 /*!<Mode_ARGB1555 */
\r
9408 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */
\r
9409 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0U) /*!< Output GREEN Value */
\r
9410 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00U) /*!< Output Red Value */
\r
9411 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000U) /*!< Output Alpha Channel Value */
\r
9413 /*!<Mode_ARGB4444 */
\r
9414 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000FU) /*!< Output BLUE Value */
\r
9415 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0U) /*!< Output GREEN Value */
\r
9416 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00U) /*!< Output Red Value */
\r
9417 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000U) /*!< Output Alpha Channel Value */
\r
9419 /******************** Bit definition for DMA2D_OMAR register ****************/
\r
9421 #define DMA2D_OMAR_MA_Pos (0U)
\r
9422 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
\r
9423 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Output Memory Address */
\r
9425 /******************** Bit definition for DMA2D_OOR register *****************/
\r
9427 #define DMA2D_OOR_LO_Pos (0U)
\r
9428 #define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
\r
9429 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
\r
9431 /******************** Bit definition for DMA2D_NLR register *****************/
\r
9433 #define DMA2D_NLR_NL_Pos (0U)
\r
9434 #define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
\r
9435 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
\r
9436 #define DMA2D_NLR_PL_Pos (16U)
\r
9437 #define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
\r
9438 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
\r
9440 /******************** Bit definition for DMA2D_LWR register *****************/
\r
9442 #define DMA2D_LWR_LW_Pos (0U)
\r
9443 #define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
\r
9444 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
\r
9446 /******************** Bit definition for DMA2D_AMTCR register ***************/
\r
9448 #define DMA2D_AMTCR_EN_Pos (0U)
\r
9449 #define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
\r
9450 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
\r
9451 #define DMA2D_AMTCR_DT_Pos (8U)
\r
9452 #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
\r
9453 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
\r
9456 /******************** Bit definition for DMA2D_FGCLUT register **************/
\r
9458 /******************** Bit definition for DMA2D_BGCLUT register **************/
\r
9461 /******************************************************************************/
\r
9463 /* External Interrupt/Event Controller */
\r
9465 /******************************************************************************/
\r
9466 /****************** Bit definition for EXTI_RTSR1 register *******************/
\r
9467 #define EXTI_RTSR1_TR_Pos (0U)
\r
9468 #define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) /*!< 0x003FFFFF */
\r
9469 #define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk /*!< Rising trigger event configuration bit */
\r
9470 #define EXTI_RTSR1_TR0_Pos (0U)
\r
9471 #define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
\r
9472 #define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
\r
9473 #define EXTI_RTSR1_TR1_Pos (1U)
\r
9474 #define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
\r
9475 #define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
\r
9476 #define EXTI_RTSR1_TR2_Pos (2U)
\r
9477 #define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
\r
9478 #define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
\r
9479 #define EXTI_RTSR1_TR3_Pos (3U)
\r
9480 #define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
\r
9481 #define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
\r
9482 #define EXTI_RTSR1_TR4_Pos (4U)
\r
9483 #define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
\r
9484 #define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
\r
9485 #define EXTI_RTSR1_TR5_Pos (5U)
\r
9486 #define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
\r
9487 #define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
\r
9488 #define EXTI_RTSR1_TR6_Pos (6U)
\r
9489 #define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
\r
9490 #define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
\r
9491 #define EXTI_RTSR1_TR7_Pos (7U)
\r
9492 #define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
\r
9493 #define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
\r
9494 #define EXTI_RTSR1_TR8_Pos (8U)
\r
9495 #define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
\r
9496 #define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
\r
9497 #define EXTI_RTSR1_TR9_Pos (9U)
\r
9498 #define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
\r
9499 #define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
\r
9500 #define EXTI_RTSR1_TR10_Pos (10U)
\r
9501 #define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
\r
9502 #define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
\r
9503 #define EXTI_RTSR1_TR11_Pos (11U)
\r
9504 #define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
\r
9505 #define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
\r
9506 #define EXTI_RTSR1_TR12_Pos (12U)
\r
9507 #define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
\r
9508 #define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
\r
9509 #define EXTI_RTSR1_TR13_Pos (13U)
\r
9510 #define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
\r
9511 #define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
\r
9512 #define EXTI_RTSR1_TR14_Pos (14U)
\r
9513 #define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
\r
9514 #define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
\r
9515 #define EXTI_RTSR1_TR15_Pos (15U)
\r
9516 #define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
\r
9517 #define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
\r
9518 #define EXTI_RTSR1_TR16_Pos (16U)
\r
9519 #define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
\r
9520 #define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
\r
9521 #define EXTI_RTSR1_TR17_Pos (17U)
\r
9522 #define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
\r
9523 #define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
\r
9524 #define EXTI_RTSR1_TR18_Pos (18U)
\r
9525 #define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
\r
9526 #define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
\r
9527 #define EXTI_RTSR1_TR19_Pos (19U)
\r
9528 #define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
\r
9529 #define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
\r
9530 #define EXTI_RTSR1_TR20_Pos (20U)
\r
9531 #define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
\r
9532 #define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
\r
9533 #define EXTI_RTSR1_TR21_Pos (21U)
\r
9534 #define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
\r
9535 #define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
\r
9537 /****************** Bit definition for EXTI_FTSR1 register *******************/
\r
9538 #define EXTI_FTSR1_TR_Pos (0U)
\r
9539 #define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) /*!< 0x003FFFFF */
\r
9540 #define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk /*!< Falling trigger event configuration bit */
\r
9541 #define EXTI_FTSR1_TR0_Pos (0U)
\r
9542 #define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
\r
9543 #define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
\r
9544 #define EXTI_FTSR1_TR1_Pos (1U)
\r
9545 #define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
\r
9546 #define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
\r
9547 #define EXTI_FTSR1_TR2_Pos (2U)
\r
9548 #define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
\r
9549 #define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
\r
9550 #define EXTI_FTSR1_TR3_Pos (3U)
\r
9551 #define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
\r
9552 #define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
\r
9553 #define EXTI_FTSR1_TR4_Pos (4U)
\r
9554 #define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
\r
9555 #define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
\r
9556 #define EXTI_FTSR1_TR5_Pos (5U)
\r
9557 #define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
\r
9558 #define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
\r
9559 #define EXTI_FTSR1_TR6_Pos (6U)
\r
9560 #define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
\r
9561 #define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
\r
9562 #define EXTI_FTSR1_TR7_Pos (7U)
\r
9563 #define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
\r
9564 #define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
\r
9565 #define EXTI_FTSR1_TR8_Pos (8U)
\r
9566 #define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
\r
9567 #define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
\r
9568 #define EXTI_FTSR1_TR9_Pos (9U)
\r
9569 #define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
\r
9570 #define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
\r
9571 #define EXTI_FTSR1_TR10_Pos (10U)
\r
9572 #define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
\r
9573 #define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
\r
9574 #define EXTI_FTSR1_TR11_Pos (11U)
\r
9575 #define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
\r
9576 #define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
\r
9577 #define EXTI_FTSR1_TR12_Pos (12U)
\r
9578 #define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
\r
9579 #define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
\r
9580 #define EXTI_FTSR1_TR13_Pos (13U)
\r
9581 #define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
\r
9582 #define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
\r
9583 #define EXTI_FTSR1_TR14_Pos (14U)
\r
9584 #define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
\r
9585 #define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
\r
9586 #define EXTI_FTSR1_TR15_Pos (15U)
\r
9587 #define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
\r
9588 #define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
\r
9589 #define EXTI_FTSR1_TR16_Pos (16U)
\r
9590 #define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
\r
9591 #define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
\r
9592 #define EXTI_FTSR1_TR17_Pos (17U)
\r
9593 #define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
\r
9594 #define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
\r
9595 #define EXTI_FTSR1_TR18_Pos (18U)
\r
9596 #define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
\r
9597 #define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
\r
9598 #define EXTI_FTSR1_TR19_Pos (19U)
\r
9599 #define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
\r
9600 #define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
\r
9601 #define EXTI_FTSR1_TR20_Pos (20U)
\r
9602 #define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
\r
9603 #define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
\r
9604 #define EXTI_FTSR1_TR21_Pos (21U)
\r
9605 #define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
\r
9606 #define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
\r
9608 /****************** Bit definition for EXTI_SWIER1 register ******************/
\r
9609 #define EXTI_SWIER1_SWIER0_Pos (0U)
\r
9610 #define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
\r
9611 #define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
\r
9612 #define EXTI_SWIER1_SWIER1_Pos (1U)
\r
9613 #define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
\r
9614 #define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
\r
9615 #define EXTI_SWIER1_SWIER2_Pos (2U)
\r
9616 #define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
\r
9617 #define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
\r
9618 #define EXTI_SWIER1_SWIER3_Pos (3U)
\r
9619 #define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
\r
9620 #define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
\r
9621 #define EXTI_SWIER1_SWIER4_Pos (4U)
\r
9622 #define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
\r
9623 #define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
\r
9624 #define EXTI_SWIER1_SWIER5_Pos (5U)
\r
9625 #define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
\r
9626 #define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
\r
9627 #define EXTI_SWIER1_SWIER6_Pos (6U)
\r
9628 #define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
\r
9629 #define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
\r
9630 #define EXTI_SWIER1_SWIER7_Pos (7U)
\r
9631 #define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
\r
9632 #define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
\r
9633 #define EXTI_SWIER1_SWIER8_Pos (8U)
\r
9634 #define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
\r
9635 #define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
\r
9636 #define EXTI_SWIER1_SWIER9_Pos (9U)
\r
9637 #define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
\r
9638 #define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
\r
9639 #define EXTI_SWIER1_SWIER10_Pos (10U)
\r
9640 #define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
\r
9641 #define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
\r
9642 #define EXTI_SWIER1_SWIER11_Pos (11U)
\r
9643 #define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
\r
9644 #define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
\r
9645 #define EXTI_SWIER1_SWIER12_Pos (12U)
\r
9646 #define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
\r
9647 #define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
\r
9648 #define EXTI_SWIER1_SWIER13_Pos (13U)
\r
9649 #define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
\r
9650 #define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
\r
9651 #define EXTI_SWIER1_SWIER14_Pos (14U)
\r
9652 #define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
\r
9653 #define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
\r
9654 #define EXTI_SWIER1_SWIER15_Pos (15U)
\r
9655 #define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
\r
9656 #define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
\r
9657 #define EXTI_SWIER1_SWIER16_Pos (16U)
\r
9658 #define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
\r
9659 #define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
\r
9660 #define EXTI_SWIER1_SWIER17_Pos (17U)
\r
9661 #define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
\r
9662 #define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
\r
9663 #define EXTI_SWIER1_SWIER18_Pos (18U)
\r
9664 #define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
\r
9665 #define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
\r
9666 #define EXTI_SWIER1_SWIER19_Pos (19U)
\r
9667 #define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
\r
9668 #define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
\r
9669 #define EXTI_SWIER1_SWIER20_Pos (20U)
\r
9670 #define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
\r
9671 #define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
\r
9672 #define EXTI_SWIER1_SWIER21_Pos (21U)
\r
9673 #define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
\r
9674 #define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
\r
9676 /****************** Bit definition for EXTI_D3PMR1 register ******************/
\r
9677 #define EXTI_D3PMR1_MR0_Pos (0U)
\r
9678 #define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) /*!< 0x00000001 */
\r
9679 #define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk /*!< Pending Mask Event for line 0 */
\r
9680 #define EXTI_D3PMR1_MR1_Pos (1U)
\r
9681 #define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) /*!< 0x00000002 */
\r
9682 #define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk /*!< Pending Mask Event for line 1 */
\r
9683 #define EXTI_D3PMR1_MR2_Pos (2U)
\r
9684 #define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) /*!< 0x00000004 */
\r
9685 #define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk /*!< Pending Mask Event for line 2 */
\r
9686 #define EXTI_D3PMR1_MR3_Pos (3U)
\r
9687 #define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) /*!< 0x00000008 */
\r
9688 #define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk /*!< Pending Mask Event for line 3 */
\r
9689 #define EXTI_D3PMR1_MR4_Pos (4U)
\r
9690 #define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) /*!< 0x00000010 */
\r
9691 #define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk /*!< Pending Mask Event for line 4 */
\r
9692 #define EXTI_D3PMR1_MR5_Pos (5U)
\r
9693 #define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) /*!< 0x00000020 */
\r
9694 #define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk /*!< Pending Mask Event for line 5 */
\r
9695 #define EXTI_D3PMR1_MR6_Pos (6U)
\r
9696 #define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) /*!< 0x00000040 */
\r
9697 #define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk /*!< Pending Mask Event for line 6 */
\r
9698 #define EXTI_D3PMR1_MR7_Pos (7U)
\r
9699 #define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) /*!< 0x00000080 */
\r
9700 #define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk /*!< Pending Mask Event for line 7 */
\r
9701 #define EXTI_D3PMR1_MR8_Pos (8U)
\r
9702 #define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) /*!< 0x00000100 */
\r
9703 #define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk /*!< Pending Mask Event for line 8 */
\r
9704 #define EXTI_D3PMR1_MR9_Pos (9U)
\r
9705 #define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) /*!< 0x00000200 */
\r
9706 #define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk /*!< Pending Mask Event for line 9 */
\r
9707 #define EXTI_D3PMR1_MR10_Pos (10U)
\r
9708 #define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) /*!< 0x00000400 */
\r
9709 #define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk /*!< Pending Mask Event for line 10 */
\r
9710 #define EXTI_D3PMR1_MR11_Pos (11U)
\r
9711 #define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) /*!< 0x00000800 */
\r
9712 #define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk /*!< Pending Mask Event for line 11 */
\r
9713 #define EXTI_D3PMR1_MR12_Pos (12U)
\r
9714 #define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) /*!< 0x00001000 */
\r
9715 #define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk /*!< Pending Mask Event for line 12 */
\r
9716 #define EXTI_D3PMR1_MR13_Pos (13U)
\r
9717 #define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) /*!< 0x00002000 */
\r
9718 #define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk /*!< Pending Mask Event for line 13 */
\r
9719 #define EXTI_D3PMR1_MR14_Pos (14U)
\r
9720 #define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) /*!< 0x00004000 */
\r
9721 #define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk /*!< Pending Mask Event for line 14 */
\r
9722 #define EXTI_D3PMR1_MR15_Pos (15U)
\r
9723 #define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) /*!< 0x00008000 */
\r
9724 #define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk /*!< Pending Mask Event for line 15 */
\r
9725 #define EXTI_D3PMR1_MR19_Pos (19U)
\r
9726 #define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) /*!< 0x00080000 */
\r
9727 #define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk /*!< Pending Mask Event for line 19 */
\r
9728 #define EXTI_D3PMR1_MR20_Pos (20U)
\r
9729 #define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) /*!< 0x00100000 */
\r
9730 #define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk /*!< Pending Mask Event for line 20 */
\r
9731 #define EXTI_D3PMR1_MR21_Pos (21U)
\r
9732 #define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) /*!< 0x00200000 */
\r
9733 #define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk /*!< Pending Mask Event for line 21 */
\r
9734 #define EXTI_D3PMR1_MR25_Pos (24U)
\r
9735 #define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) /*!< 0x01000000 */
\r
9736 #define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk /*!< Pending Mask Event for line 25 */
\r
9738 /******************* Bit definition for EXTI_D3PCR1L register ****************/
\r
9739 #define EXTI_D3PCR1L_PCS0_Pos (0U)
\r
9740 #define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) /*!< 0x00000003 */
\r
9741 #define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk /*!< D3 Pending request clear input signal selection on line 0 */
\r
9742 #define EXTI_D3PCR1L_PCS1_Pos (2U)
\r
9743 #define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) /*!< 0x000000C0 */
\r
9744 #define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk /*!< D3 Pending request clear input signal selection on line 1 */
\r
9745 #define EXTI_D3PCR1L_PCS2_Pos (4U)
\r
9746 #define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) /*!< 0x00000030 */
\r
9747 #define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk /*!< D3 Pending request clear input signal selection on line 2 */
\r
9748 #define EXTI_D3PCR1L_PCS3_Pos (6U)
\r
9749 #define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) /*!< 0x000000C0 */
\r
9750 #define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk /*!< D3 Pending request clear input signal selection on line 3 */
\r
9751 #define EXTI_D3PCR1L_PCS4_Pos (8U)
\r
9752 #define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) /*!< 0x00000300 */
\r
9753 #define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk /*!< D3 Pending request clear input signal selection on line 4 */
\r
9754 #define EXTI_D3PCR1L_PCS5_Pos (10U)
\r
9755 #define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) /*!< 0x00000C00 */
\r
9756 #define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk /*!< D3 Pending request clear input signal selection on line 5 */
\r
9757 #define EXTI_D3PCR1L_PCS6_Pos (12U)
\r
9758 #define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos) /*!< 0x00003000 */
\r
9759 #define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk /*!< D3 Pending request clear input signal selection on line 6 */
\r
9760 #define EXTI_D3PCR1L_PCS7_Pos (14U)
\r
9761 #define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos) /*!< 0x0000C000 */
\r
9762 #define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk /*!< D3 Pending request clear input signal selection on line 7 */
\r
9763 #define EXTI_D3PCR1L_PCS8_Pos (16U)
\r
9764 #define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos) /*!< 0x00030000 */
\r
9765 #define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk /*!< D3 Pending request clear input signal selection on line 8 */
\r
9766 #define EXTI_D3PCR1L_PCS9_Pos (18U)
\r
9767 #define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos) /*!< 0x000C0000 */
\r
9768 #define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk /*!< D3 Pending request clear input signal selection on line 9 */
\r
9769 #define EXTI_D3PCR1L_PCS10_Pos (20U)
\r
9770 #define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos) /*!< 0x00300000 */
\r
9771 #define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk /*!< D3 Pending request clear input signal selection on line 10*/
\r
9772 #define EXTI_D3PCR1L_PCS11_Pos (22U)
\r
9773 #define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos) /*!< 0x00C00000 */
\r
9774 #define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk /*!< D3 Pending request clear input signal selection on line 11*/
\r
9775 #define EXTI_D3PCR1L_PCS12_Pos (24U)
\r
9776 #define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos) /*!< 0x03000000 */
\r
9777 #define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk /*!< D3 Pending request clear input signal selection on line 12*/
\r
9778 #define EXTI_D3PCR1L_PCS13_Pos (26U)
\r
9779 #define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos) /*!< 0x0C000000 */
\r
9780 #define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk /*!< D3 Pending request clear input signal selection on line 13*/
\r
9781 #define EXTI_D3PCR1L_PCS14_Pos (28U)
\r
9782 #define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos) /*!< 0x30000000 */
\r
9783 #define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk /*!< D3 Pending request clear input signal selection on line 14*/
\r
9784 #define EXTI_D3PCR1L_PCS15_Pos (30U)
\r
9785 #define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos) /*!< 0xC0000000 */
\r
9786 #define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk /*!< D3 Pending request clear input signal selection on line 15*/
\r
9788 /******************* Bit definition for EXTI_D3PCR1H register ****************/
\r
9789 #define EXTI_D3PCR1H_PCS19_Pos (6U)
\r
9790 #define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos) /*!< 0x000000C0 */
\r
9791 #define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk /*!< D3 Pending request clear input signal selection on line 19 */
\r
9792 #define EXTI_D3PCR1H_PCS20_Pos (8U)
\r
9793 #define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos) /*!< 0x00000300 */
\r
9794 #define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk /*!< D3 Pending request clear input signal selection on line 20 */
\r
9795 #define EXTI_D3PCR1H_PCS21_Pos (10U)
\r
9796 #define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos) /*!< 0x00000C00 */
\r
9797 #define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk /*!< D3 Pending request clear input signal selection on line 21 */
\r
9798 #define EXTI_D3PCR1H_PCS25_Pos (18U)
\r
9799 #define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos) /*!< 0x000C0000 */
\r
9800 #define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk /*!< D3 Pending request clear input signal selection on line 25 */
\r
9802 /****************** Bit definition for EXTI_RTSR2 register *******************/
\r
9803 #define EXTI_RTSR2_TR_Pos (17U)
\r
9804 #define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos) /*!< 0x000A0000 */
\r
9805 #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
\r
9806 #define EXTI_RTSR2_TR49_Pos (17U)
\r
9807 #define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */
\r
9808 #define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */
\r
9809 #define EXTI_RTSR2_TR51_Pos (19U)
\r
9810 #define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */
\r
9811 #define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */
\r
9813 /****************** Bit definition for EXTI_FTSR2 register *******************/
\r
9814 #define EXTI_FTSR2_TR_Pos (17U)
\r
9815 #define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos) /*!< 0x000A0000 */
\r
9816 #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
\r
9817 #define EXTI_FTSR2_TR49_Pos (17U)
\r
9818 #define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */
\r
9819 #define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */
\r
9820 #define EXTI_FTSR2_TR51_Pos (19U)
\r
9821 #define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */
\r
9822 #define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */
\r
9824 /****************** Bit definition for EXTI_SWIER2 register ******************/
\r
9825 #define EXTI_SWIER2_SWIER49_Pos (17U)
\r
9826 #define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */
\r
9827 #define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */
\r
9828 #define EXTI_SWIER2_SWIER51_Pos (19U)
\r
9829 #define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */
\r
9830 #define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */
\r
9832 /****************** Bit definition for EXTI_D3PMR2 register ******************/
\r
9833 #define EXTI_D3PMR2_MR34_Pos (2U)
\r
9834 #define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos) /*!< 0x00000004 */
\r
9835 #define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk /*!< Pending Mask Event for line 34 */
\r
9836 #define EXTI_D3PMR2_MR35_Pos (3U)
\r
9837 #define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos) /*!< 0x00000008 */
\r
9838 #define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk /*!< Pending Mask Event for line 35 */
\r
9839 #define EXTI_D3PMR2_MR41_Pos (9U)
\r
9840 #define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos) /*!< 0x00000200 */
\r
9841 #define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk /*!< Pending Mask Event for line 41 */
\r
9842 #define EXTI_D3PMR2_MR48_Pos (16U)
\r
9843 #define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos) /*!< 0x00010000 */
\r
9844 #define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk /*!< Pending Mask Event for line 48 */
\r
9845 #define EXTI_D3PMR2_MR49_Pos (17U)
\r
9846 #define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos) /*!< 0x00020000 */
\r
9847 #define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk /*!< Pending Mask Event for line 49 */
\r
9848 #define EXTI_D3PMR2_MR50_Pos (18U)
\r
9849 #define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos) /*!< 0x00040000 */
\r
9850 #define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk /*!< Pending Mask Event for line 50 */
\r
9851 #define EXTI_D3PMR2_MR51_Pos (19U)
\r
9852 #define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos) /*!< 0x00080000 */
\r
9853 #define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk /*!< Pending Mask Event for line 51 */
\r
9854 #define EXTI_D3PMR2_MR52_Pos (20U)
\r
9855 #define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos) /*!< 0x00100000 */
\r
9856 #define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk /*!< Pending Mask Event for line 52 */
\r
9857 #define EXTI_D3PMR2_MR53_Pos (21U)
\r
9858 #define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos) /*!< 0x00200000 */
\r
9859 #define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk /*!< Pending Mask Event for line 53 */
\r
9860 /******************* Bit definition for EXTI_D3PCR2L register ****************/
\r
9861 #define EXTI_D3PCR2L_PCS34_Pos (4U)
\r
9862 #define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos) /*!< 0x00000030 */
\r
9863 #define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk /*!< D3 Pending request clear input signal selection on line 34 */
\r
9864 #define EXTI_D3PCR2L_PCS35_Pos (6U)
\r
9865 #define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos) /*!< 0x000000C0 */
\r
9866 #define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk /*!< D3 Pending request clear input signal selection on line 35 */
\r
9867 #define EXTI_D3PCR2L_PCS41_Pos (18U)
\r
9868 #define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos) /*!< 0x000C0000 */
\r
9869 #define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk /*!< D3 Pending request clear input signal selection on line 41 */
\r
9872 /******************* Bit definition for EXTI_D3PCR2H register ****************/
\r
9873 #define EXTI_D3PCR2H_PCS48_Pos (0U)
\r
9874 #define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos) /*!< 0x00000003 */
\r
9875 #define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk /*!< D3 Pending request clear input signal selection on line 48 */
\r
9876 #define EXTI_D3PCR2H_PCS49_Pos (2U)
\r
9877 #define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos) /*!< 0x0000000C */
\r
9878 #define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk /*!< D3 Pending request clear input signal selection on line 49 */
\r
9879 #define EXTI_D3PCR2H_PCS50_Pos (4U)
\r
9880 #define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos) /*!< 0x00000030 */
\r
9881 #define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk /*!< D3 Pending request clear input signal selection on line 50 */
\r
9882 #define EXTI_D3PCR2H_PCS51_Pos (6U)
\r
9883 #define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos) /*!< 0x000000C0 */
\r
9884 #define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk /*!< D3 Pending request clear input signal selection on line 51 */
\r
9885 #define EXTI_D3PCR2H_PCS52_Pos (8U)
\r
9886 #define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos) /*!< 0x00000300 */
\r
9887 #define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk /*!< D3 Pending request clear input signal selection on line 52 */
\r
9888 #define EXTI_D3PCR2H_PCS53_Pos (10U)
\r
9889 #define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos) /*!< 0x00000C00 */
\r
9890 #define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk /*!< D3 Pending request clear input signal selection on line 53 */
\r
9891 /****************** Bit definition for EXTI_RTSR3 register *******************/
\r
9892 #define EXTI_RTSR3_TR_Pos (18U)
\r
9893 #define EXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos) /*!< 0x00740000 */
\r
9894 #define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk /*!< Rising trigger event configuration bit */
\r
9895 #define EXTI_RTSR3_TR82_Pos (18U)
\r
9896 #define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos) /*!< 0x00040000 */
\r
9897 #define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk /*!< Rising trigger event configuration bit of line 82 */
\r
9898 #define EXTI_RTSR3_TR84_Pos (20U)
\r
9899 #define EXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos) /*!< 0x00100000 */
\r
9900 #define EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk /*!< Rising trigger event configuration bit of line 84 */
\r
9901 #define EXTI_RTSR3_TR85_Pos (21U)
\r
9902 #define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */
\r
9903 #define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */
\r
9904 #define EXTI_RTSR3_TR86_Pos (22U)
\r
9905 #define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos) /*!< 0x00400000 */
\r
9906 #define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk /*!< Rising trigger event configuration bit of line 86 */
\r
9908 /****************** Bit definition for EXTI_FTSR3 register *******************/
\r
9909 #define EXTI_FTSR3_TR_Pos (18U)
\r
9910 #define EXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos) /*!< 0x00740000 */
\r
9911 #define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk /*!< Falling trigger event configuration bit */
\r
9912 #define EXTI_FTSR3_TR82_Pos (18U)
\r
9913 #define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos) /*!< 0x00040000 */
\r
9914 #define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk /*!< Falling trigger event configuration bit of line 82 */
\r
9915 #define EXTI_FTSR3_TR84_Pos (20U)
\r
9916 #define EXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos) /*!< 0x00100000 */
\r
9917 #define EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk /*!< Falling trigger event configuration bit of line 84 */
\r
9918 #define EXTI_FTSR3_TR85_Pos (21U)
\r
9919 #define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */
\r
9920 #define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */
\r
9921 #define EXTI_FTSR3_TR86_Pos (22U)
\r
9922 #define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos) /*!< 0x00400000 */
\r
9923 #define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk /*!< Falling trigger event configuration bit of line 86 */
\r
9925 /****************** Bit definition for EXTI_SWIER3 register ******************/
\r
9926 #define EXTI_SWIER3_SWI_Pos (18U)
\r
9927 #define EXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos) /*!< 0x00740000 */
\r
9928 #define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk /*!< Software Interrupt event bit */
\r
9929 #define EXTI_SWIER3_SWIER82_Pos (18U)
\r
9930 #define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos) /*!< 0x00040000 */
\r
9931 #define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk /*!< Software Interrupt on line 82 */
\r
9932 #define EXTI_SWIER3_SWIER84_Pos (20U)
\r
9933 #define EXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos) /*!< 0x00100000 */
\r
9934 #define EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk /*!< Software Interrupt on line 84 */
\r
9935 #define EXTI_SWIER3_SWIER85_Pos (21U)
\r
9936 #define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */
\r
9937 #define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */
\r
9938 #define EXTI_SWIER3_SWIER86_Pos (22U)
\r
9939 #define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos) /*!< 0x00400000 */
\r
9940 #define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk /*!< Software Interrupt on line 86 */
\r
9942 /******************* Bit definition for EXTI_IMR1 register *******************/
\r
9943 #define EXTI_IMR1_IM_Pos (0U)
\r
9944 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
\r
9945 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask */
\r
9946 #define EXTI_IMR1_IM0_Pos (0U)
\r
9947 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
\r
9948 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
\r
9949 #define EXTI_IMR1_IM1_Pos (1U)
\r
9950 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
\r
9951 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
\r
9952 #define EXTI_IMR1_IM2_Pos (2U)
\r
9953 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
\r
9954 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
\r
9955 #define EXTI_IMR1_IM3_Pos (3U)
\r
9956 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
\r
9957 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
\r
9958 #define EXTI_IMR1_IM4_Pos (4U)
\r
9959 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
\r
9960 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
\r
9961 #define EXTI_IMR1_IM5_Pos (5U)
\r
9962 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
\r
9963 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
\r
9964 #define EXTI_IMR1_IM6_Pos (6U)
\r
9965 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
\r
9966 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
\r
9967 #define EXTI_IMR1_IM7_Pos (7U)
\r
9968 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
\r
9969 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
\r
9970 #define EXTI_IMR1_IM8_Pos (8U)
\r
9971 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
\r
9972 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
\r
9973 #define EXTI_IMR1_IM9_Pos (9U)
\r
9974 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
\r
9975 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
\r
9976 #define EXTI_IMR1_IM10_Pos (10U)
\r
9977 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
\r
9978 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
\r
9979 #define EXTI_IMR1_IM11_Pos (11U)
\r
9980 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
\r
9981 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
\r
9982 #define EXTI_IMR1_IM12_Pos (12U)
\r
9983 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
\r
9984 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
\r
9985 #define EXTI_IMR1_IM13_Pos (13U)
\r
9986 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
\r
9987 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
\r
9988 #define EXTI_IMR1_IM14_Pos (14U)
\r
9989 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
\r
9990 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
\r
9991 #define EXTI_IMR1_IM15_Pos (15U)
\r
9992 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
\r
9993 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
\r
9994 #define EXTI_IMR1_IM16_Pos (16U)
\r
9995 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
\r
9996 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
\r
9997 #define EXTI_IMR1_IM17_Pos (17U)
\r
9998 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
\r
9999 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
\r
10000 #define EXTI_IMR1_IM18_Pos (18U)
\r
10001 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
\r
10002 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
\r
10003 #define EXTI_IMR1_IM19_Pos (19U)
\r
10004 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
\r
10005 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
\r
10006 #define EXTI_IMR1_IM20_Pos (20U)
\r
10007 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
\r
10008 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
\r
10009 #define EXTI_IMR1_IM21_Pos (21U)
\r
10010 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
\r
10011 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
\r
10012 #define EXTI_IMR1_IM22_Pos (22U)
\r
10013 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
\r
10014 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
\r
10015 #define EXTI_IMR1_IM23_Pos (23U)
\r
10016 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
\r
10017 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
\r
10018 #define EXTI_IMR1_IM24_Pos (24U)
\r
10019 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
\r
10020 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
\r
10021 #define EXTI_IMR1_IM25_Pos (25U)
\r
10022 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
\r
10023 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
\r
10024 #define EXTI_IMR1_IM26_Pos (26U)
\r
10025 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
\r
10026 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
\r
10027 #define EXTI_IMR1_IM27_Pos (27U)
\r
10028 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
\r
10029 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
\r
10030 #define EXTI_IMR1_IM28_Pos (28U)
\r
10031 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
\r
10032 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
\r
10033 #define EXTI_IMR1_IM29_Pos (29U)
\r
10034 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
\r
10035 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
\r
10036 #define EXTI_IMR1_IM30_Pos (30U)
\r
10037 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
\r
10038 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
\r
10039 #define EXTI_IMR1_IM31_Pos (31U)
\r
10040 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
\r
10041 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
\r
10043 /******************* Bit definition for EXTI_EMR1 register *******************/
\r
10044 #define EXTI_EMR1_EM_Pos (0U)
\r
10045 #define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) /*!< 0xFFFFFFFF */
\r
10046 #define EXTI_EMR1_EM EXTI_EMR1_EM_Msk /*!< Event Mask */
\r
10047 #define EXTI_EMR1_EM0_Pos (0U)
\r
10048 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
\r
10049 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
\r
10050 #define EXTI_EMR1_EM1_Pos (1U)
\r
10051 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
\r
10052 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
\r
10053 #define EXTI_EMR1_EM2_Pos (2U)
\r
10054 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
\r
10055 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
\r
10056 #define EXTI_EMR1_EM3_Pos (3U)
\r
10057 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
\r
10058 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
\r
10059 #define EXTI_EMR1_EM4_Pos (4U)
\r
10060 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
\r
10061 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
\r
10062 #define EXTI_EMR1_EM5_Pos (5U)
\r
10063 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
\r
10064 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
\r
10065 #define EXTI_EMR1_EM6_Pos (6U)
\r
10066 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
\r
10067 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
\r
10068 #define EXTI_EMR1_EM7_Pos (7U)
\r
10069 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
\r
10070 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
\r
10071 #define EXTI_EMR1_EM8_Pos (8U)
\r
10072 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
\r
10073 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
\r
10074 #define EXTI_EMR1_EM9_Pos (9U)
\r
10075 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
\r
10076 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
\r
10077 #define EXTI_EMR1_EM10_Pos (10U)
\r
10078 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
\r
10079 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
\r
10080 #define EXTI_EMR1_EM11_Pos (11U)
\r
10081 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
\r
10082 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
\r
10083 #define EXTI_EMR1_EM12_Pos (12U)
\r
10084 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
\r
10085 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
\r
10086 #define EXTI_EMR1_EM13_Pos (13U)
\r
10087 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
\r
10088 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
\r
10089 #define EXTI_EMR1_EM14_Pos (14U)
\r
10090 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
\r
10091 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
\r
10092 #define EXTI_EMR1_EM15_Pos (15U)
\r
10093 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
\r
10094 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
\r
10095 #define EXTI_EMR1_EM16_Pos (16U)
\r
10096 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
\r
10097 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
\r
10098 #define EXTI_EMR1_EM17_Pos (17U)
\r
10099 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
\r
10100 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
\r
10101 #define EXTI_EMR1_EM18_Pos (18U)
\r
10102 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
\r
10103 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
\r
10104 #define EXTI_EMR1_EM20_Pos (20U)
\r
10105 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
\r
10106 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
\r
10107 #define EXTI_EMR1_EM21_Pos (21U)
\r
10108 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
\r
10109 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
\r
10110 #define EXTI_EMR1_EM22_Pos (22U)
\r
10111 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
\r
10112 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
\r
10113 #define EXTI_EMR1_EM23_Pos (23U)
\r
10114 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
\r
10115 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
\r
10116 #define EXTI_EMR1_EM24_Pos (24U)
\r
10117 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
\r
10118 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
\r
10119 #define EXTI_EMR1_EM25_Pos (25U)
\r
10120 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
\r
10121 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
\r
10122 #define EXTI_EMR1_EM26_Pos (26U)
\r
10123 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
\r
10124 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
\r
10125 #define EXTI_EMR1_EM27_Pos (27U)
\r
10126 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
\r
10127 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
\r
10128 #define EXTI_EMR1_EM28_Pos (28U)
\r
10129 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
\r
10130 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
\r
10131 #define EXTI_EMR1_EM29_Pos (29U)
\r
10132 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
\r
10133 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
\r
10134 #define EXTI_EMR1_EM30_Pos (30U)
\r
10135 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
\r
10136 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
\r
10137 #define EXTI_EMR1_EM31_Pos (31U)
\r
10138 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
\r
10139 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
\r
10141 /******************* Bit definition for EXTI_PR1 register ********************/
\r
10142 #define EXTI_PR1_PR_Pos (0U)
\r
10143 #define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos) /*!< 0x003FFFFF */
\r
10144 #define EXTI_PR1_PR EXTI_PR1_PR_Msk /*!< Pending bit */
\r
10145 #define EXTI_PR1_PR0_Pos (0U)
\r
10146 #define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */
\r
10147 #define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */
\r
10148 #define EXTI_PR1_PR1_Pos (1U)
\r
10149 #define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */
\r
10150 #define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */
\r
10151 #define EXTI_PR1_PR2_Pos (2U)
\r
10152 #define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */
\r
10153 #define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */
\r
10154 #define EXTI_PR1_PR3_Pos (3U)
\r
10155 #define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */
\r
10156 #define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */
\r
10157 #define EXTI_PR1_PR4_Pos (4U)
\r
10158 #define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */
\r
10159 #define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */
\r
10160 #define EXTI_PR1_PR5_Pos (5U)
\r
10161 #define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */
\r
10162 #define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */
\r
10163 #define EXTI_PR1_PR6_Pos (6U)
\r
10164 #define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */
\r
10165 #define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */
\r
10166 #define EXTI_PR1_PR7_Pos (7U)
\r
10167 #define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */
\r
10168 #define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */
\r
10169 #define EXTI_PR1_PR8_Pos (8U)
\r
10170 #define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */
\r
10171 #define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */
\r
10172 #define EXTI_PR1_PR9_Pos (9U)
\r
10173 #define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */
\r
10174 #define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */
\r
10175 #define EXTI_PR1_PR10_Pos (10U)
\r
10176 #define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */
\r
10177 #define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */
\r
10178 #define EXTI_PR1_PR11_Pos (11U)
\r
10179 #define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */
\r
10180 #define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */
\r
10181 #define EXTI_PR1_PR12_Pos (12U)
\r
10182 #define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */
\r
10183 #define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */
\r
10184 #define EXTI_PR1_PR13_Pos (13U)
\r
10185 #define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */
\r
10186 #define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */
\r
10187 #define EXTI_PR1_PR14_Pos (14U)
\r
10188 #define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */
\r
10189 #define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */
\r
10190 #define EXTI_PR1_PR15_Pos (15U)
\r
10191 #define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */
\r
10192 #define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */
\r
10193 #define EXTI_PR1_PR16_Pos (16U)
\r
10194 #define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */
\r
10195 #define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */
\r
10196 #define EXTI_PR1_PR17_Pos (17U)
\r
10197 #define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos) /*!< 0x00020000 */
\r
10198 #define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk /*!< Pending bit for line 17 */
\r
10199 #define EXTI_PR1_PR18_Pos (18U)
\r
10200 #define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos) /*!< 0x00040000 */
\r
10201 #define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk /*!< Pending bit for line 18 */
\r
10202 #define EXTI_PR1_PR19_Pos (19U)
\r
10203 #define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos) /*!< 0x00080000 */
\r
10204 #define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk /*!< Pending bit for line 19 */
\r
10205 #define EXTI_PR1_PR20_Pos (20U)
\r
10206 #define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos) /*!< 0x00100000 */
\r
10207 #define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk /*!< Pending bit for line 20 */
\r
10208 #define EXTI_PR1_PR21_Pos (21U)
\r
10209 #define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos) /*!< 0x00200000 */
\r
10210 #define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk /*!< Pending bit for line 21 */
\r
10212 /******************* Bit definition for EXTI_IMR2 register *******************/
\r
10213 #define EXTI_IMR2_IM_Pos (0U)
\r
10214 #define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos) /*!< 0xFFFFDFFF */
\r
10215 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask */
\r
10216 #define EXTI_IMR2_IM32_Pos (0U)
\r
10217 #define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
\r
10218 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
\r
10219 #define EXTI_IMR2_IM33_Pos (1U)
\r
10220 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
\r
10221 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
\r
10222 #define EXTI_IMR2_IM34_Pos (2U)
\r
10223 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
\r
10224 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
\r
10225 #define EXTI_IMR2_IM35_Pos (3U)
\r
10226 #define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
\r
10227 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
\r
10228 #define EXTI_IMR2_IM36_Pos (4U)
\r
10229 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
\r
10230 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
\r
10231 #define EXTI_IMR2_IM37_Pos (5U)
\r
10232 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
\r
10233 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
\r
10234 #define EXTI_IMR2_IM38_Pos (6U)
\r
10235 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
\r
10236 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
\r
10237 #define EXTI_IMR2_IM39_Pos (7U)
\r
10238 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
\r
10239 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
\r
10240 #define EXTI_IMR2_IM40_Pos (8U)
\r
10241 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
\r
10242 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
\r
10243 #define EXTI_IMR2_IM41_Pos (9U)
\r
10244 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
\r
10245 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
\r
10246 #define EXTI_IMR2_IM42_Pos (10U)
\r
10247 #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
\r
10248 #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
\r
10249 #define EXTI_IMR2_IM43_Pos (11U)
\r
10250 #define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
\r
10251 #define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
\r
10252 #define EXTI_IMR2_IM44_Pos (12U)
\r
10253 #define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
\r
10254 #define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
\r
10255 #define EXTI_IMR2_IM46_Pos (14U)
\r
10256 #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
\r
10257 #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
\r
10258 #define EXTI_IMR2_IM47_Pos (15U)
\r
10259 #define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
\r
10260 #define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
\r
10261 #define EXTI_IMR2_IM48_Pos (16U)
\r
10262 #define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
\r
10263 #define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
\r
10264 #define EXTI_IMR2_IM49_Pos (17U)
\r
10265 #define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
\r
10266 #define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
\r
10267 #define EXTI_IMR2_IM50_Pos (18U)
\r
10268 #define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
\r
10269 #define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
\r
10270 #define EXTI_IMR2_IM51_Pos (19U)
\r
10271 #define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
\r
10272 #define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
\r
10273 #define EXTI_IMR2_IM52_Pos (20U)
\r
10274 #define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
\r
10275 #define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
\r
10276 #define EXTI_IMR2_IM53_Pos (21U)
\r
10277 #define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
\r
10278 #define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
\r
10279 #define EXTI_IMR2_IM54_Pos (22U)
\r
10280 #define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
\r
10281 #define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
\r
10282 #define EXTI_IMR2_IM55_Pos (23U)
\r
10283 #define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
\r
10284 #define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
\r
10285 #define EXTI_IMR2_IM56_Pos (24U)
\r
10286 #define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
\r
10287 #define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
\r
10288 #define EXTI_IMR2_IM57_Pos (25U)
\r
10289 #define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
\r
10290 #define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
\r
10291 #define EXTI_IMR2_IM58_Pos (26U)
\r
10292 #define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
\r
10293 #define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
\r
10294 #define EXTI_IMR2_IM59_Pos (27U)
\r
10295 #define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */
\r
10296 #define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */
\r
10297 #define EXTI_IMR2_IM60_Pos (28U)
\r
10298 #define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
\r
10299 #define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
\r
10300 #define EXTI_IMR2_IM61_Pos (29U)
\r
10301 #define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
\r
10302 #define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
\r
10303 #define EXTI_IMR2_IM62_Pos (30U)
\r
10304 #define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
\r
10305 #define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
\r
10306 #define EXTI_IMR2_IM63_Pos (31U)
\r
10307 #define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
\r
10308 #define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
\r
10310 /******************* Bit definition for EXTI_EMR2 register *******************/
\r
10311 #define EXTI_EMR2_EM_Pos (0U)
\r
10312 #define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos) /*!< 0xFFFFDFFF */
\r
10313 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask */
\r
10314 #define EXTI_EMR2_EM32_Pos (0U)
\r
10315 #define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
\r
10316 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/
\r
10317 #define EXTI_EMR2_EM33_Pos (1U)
\r
10318 #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
\r
10319 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/
\r
10320 #define EXTI_EMR2_EM34_Pos (2U)
\r
10321 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
\r
10322 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/
\r
10323 #define EXTI_EMR2_EM35_Pos (3U)
\r
10324 #define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
\r
10325 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/
\r
10326 #define EXTI_EMR2_EM36_Pos (4U)
\r
10327 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
\r
10328 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/
\r
10329 #define EXTI_EMR2_EM37_Pos (5U)
\r
10330 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
\r
10331 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/
\r
10332 #define EXTI_EMR2_EM38_Pos (6U)
\r
10333 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
\r
10334 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/
\r
10335 #define EXTI_EMR2_EM39_Pos (7U)
\r
10336 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
\r
10337 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/
\r
10338 #define EXTI_EMR2_EM40_Pos (8U)
\r
10339 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
\r
10340 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/
\r
10341 #define EXTI_EMR2_EM41_Pos (9U)
\r
10342 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
\r
10343 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/
\r
10344 #define EXTI_EMR2_EM42_Pos (10U)
\r
10345 #define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
\r
10346 #define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
\r
10347 #define EXTI_EMR2_EM43_Pos (11U)
\r
10348 #define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
\r
10349 #define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
\r
10350 #define EXTI_EMR2_EM44_Pos (12U)
\r
10351 #define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
\r
10352 #define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
\r
10353 #define EXTI_EMR2_EM46_Pos (14U)
\r
10354 #define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
\r
10355 #define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
\r
10356 #define EXTI_EMR2_EM47_Pos (15U)
\r
10357 #define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
\r
10358 #define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
\r
10359 #define EXTI_EMR2_EM48_Pos (16U)
\r
10360 #define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
\r
10361 #define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
\r
10362 #define EXTI_EMR2_EM49_Pos (17U)
\r
10363 #define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
\r
10364 #define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
\r
10365 #define EXTI_EMR2_EM50_Pos (18U)
\r
10366 #define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
\r
10367 #define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
\r
10368 #define EXTI_EMR2_EM51_Pos (19U)
\r
10369 #define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
\r
10370 #define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
\r
10371 #define EXTI_EMR2_EM52_Pos (20U)
\r
10372 #define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
\r
10373 #define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
\r
10374 #define EXTI_EMR2_EM53_Pos (21U)
\r
10375 #define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
\r
10376 #define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
\r
10377 #define EXTI_EMR2_EM54_Pos (22U)
\r
10378 #define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
\r
10379 #define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
\r
10380 #define EXTI_EMR2_EM55_Pos (23U)
\r
10381 #define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
\r
10382 #define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
\r
10383 #define EXTI_EMR2_EM56_Pos (24U)
\r
10384 #define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
\r
10385 #define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
\r
10386 #define EXTI_EMR2_EM57_Pos (25U)
\r
10387 #define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
\r
10388 #define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
\r
10389 #define EXTI_EMR2_EM58_Pos (26U)
\r
10390 #define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
\r
10391 #define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
\r
10392 #define EXTI_EMR2_EM59_Pos (27U)
\r
10393 #define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */
\r
10394 #define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */
\r
10395 #define EXTI_EMR2_EM60_Pos (28U)
\r
10396 #define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
\r
10397 #define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
\r
10398 #define EXTI_EMR2_EM61_Pos (29U)
\r
10399 #define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */
\r
10400 #define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */
\r
10401 #define EXTI_EMR2_EM62_Pos (30U)
\r
10402 #define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */
\r
10403 #define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */
\r
10404 #define EXTI_EMR2_EM63_Pos (31U)
\r
10405 #define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */
\r
10406 #define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */
\r
10408 /******************* Bit definition for EXTI_PR2 register ********************/
\r
10409 #define EXTI_PR2_PR_Pos (17U)
\r
10410 #define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos) /*!< 0x000A0000 */
\r
10411 #define EXTI_PR2_PR EXTI_PR2_PR_Msk /*!< Pending bit */
\r
10412 #define EXTI_PR2_PR49_Pos (17U)
\r
10413 #define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos) /*!< 0x00020000 */
\r
10414 #define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk /*!< Pending bit for line 49 */
\r
10415 #define EXTI_PR2_PR51_Pos (19U)
\r
10416 #define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos) /*!< 0x00080000 */
\r
10417 #define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk /*!< Pending bit for line 51 */
\r
10419 /******************* Bit definition for EXTI_IMR3 register *******************/
\r
10420 #define EXTI_IMR3_IM_Pos (0U)
\r
10421 #define EXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos) /*!< 0x00F5FFFF */
\r
10422 #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
\r
10423 #define EXTI_IMR3_IM64_Pos (0U)
\r
10424 #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
\r
10425 #define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
\r
10426 #define EXTI_IMR3_IM65_Pos (1U)
\r
10427 #define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
\r
10428 #define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
\r
10429 #define EXTI_IMR3_IM66_Pos (2U)
\r
10430 #define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
\r
10431 #define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
\r
10432 #define EXTI_IMR3_IM67_Pos (3U)
\r
10433 #define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */
\r
10434 #define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */
\r
10435 #define EXTI_IMR3_IM68_Pos (4U)
\r
10436 #define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
\r
10437 #define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
\r
10438 #define EXTI_IMR3_IM69_Pos (5U)
\r
10439 #define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
\r
10440 #define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
\r
10441 #define EXTI_IMR3_IM70_Pos (6U)
\r
10442 #define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
\r
10443 #define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
\r
10444 #define EXTI_IMR3_IM71_Pos (7U)
\r
10445 #define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
\r
10446 #define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
\r
10447 #define EXTI_IMR3_IM72_Pos (8U)
\r
10448 #define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
\r
10449 #define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
\r
10450 #define EXTI_IMR3_IM73_Pos (9U)
\r
10451 #define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
\r
10452 #define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
\r
10453 #define EXTI_IMR3_IM74_Pos (10U)
\r
10454 #define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
\r
10455 #define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
\r
10456 #define EXTI_IMR3_IM75_Pos (11U)
\r
10457 #define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos) /*!< 0x00000800 */
\r
10458 #define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk /*!< Interrupt Mask on line 75 */
\r
10459 #define EXTI_IMR3_IM76_Pos (12U)
\r
10460 #define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos) /*!< 0x00001000 */
\r
10461 #define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk /*!< Interrupt Mask on line 76 */
\r
10462 #define EXTI_IMR3_IM77_Pos (13U)
\r
10463 #define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
\r
10464 #define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
\r
10465 #define EXTI_IMR3_IM78_Pos (14U)
\r
10466 #define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos) /*!< 0x00004000 */
\r
10467 #define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk /*!< Interrupt Mask on line 78 */
\r
10468 #define EXTI_IMR3_IM79_Pos (15U)
\r
10469 #define EXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos) /*!< 0x00008000 */
\r
10470 #define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk /*!< Interrupt Mask on line 79 */
\r
10471 #define EXTI_IMR3_IM80_Pos (16U)
\r
10472 #define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */
\r
10473 #define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */
\r
10474 #define EXTI_IMR3_IM82_Pos (18U)
\r
10475 #define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */
\r
10476 #define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */
\r
10477 #define EXTI_IMR3_IM84_Pos (20U)
\r
10478 #define EXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos) /*!< 0x00100000 */
\r
10479 #define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk /*!< Interrupt Mask on line 84 */
\r
10480 #define EXTI_IMR3_IM85_Pos (21U)
\r
10481 #define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */
\r
10482 #define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */
\r
10483 #define EXTI_IMR3_IM86_Pos (22U)
\r
10484 #define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos) /*!< 0x00400000 */
\r
10485 #define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk /*!< Interrupt Mask on line 86 */
\r
10486 #define EXTI_IMR3_IM87_Pos (23U)
\r
10487 #define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */
\r
10488 #define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */
\r
10491 /******************* Bit definition for EXTI_EMR3 register *******************/
\r
10492 #define EXTI_EMR3_EM_Pos (0U)
\r
10493 #define EXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos) /*!< 0x00F5FFFF */
\r
10494 #define EXTI_EMR3_EM EXTI_EMR3_EM_Msk /*!< Event Mask */
\r
10495 #define EXTI_EMR3_EM64_Pos (0U)
\r
10496 #define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
\r
10497 #define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/
\r
10498 #define EXTI_EMR3_EM65_Pos (1U)
\r
10499 #define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
\r
10500 #define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/
\r
10501 #define EXTI_EMR3_EM66_Pos (2U)
\r
10502 #define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
\r
10503 #define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/
\r
10504 #define EXTI_EMR3_EM67_Pos (3U)
\r
10505 #define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */
\r
10506 #define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/
\r
10507 #define EXTI_EMR3_EM68_Pos (4U)
\r
10508 #define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
\r
10509 #define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/
\r
10510 #define EXTI_EMR3_EM69_Pos (5U)
\r
10511 #define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
\r
10512 #define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/
\r
10513 #define EXTI_EMR3_EM70_Pos (6U)
\r
10514 #define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
\r
10515 #define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/
\r
10516 #define EXTI_EMR3_EM71_Pos (7U)
\r
10517 #define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
\r
10518 #define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/
\r
10519 #define EXTI_EMR3_EM72_Pos (8U)
\r
10520 #define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
\r
10521 #define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/
\r
10522 #define EXTI_EMR3_EM73_Pos (9U)
\r
10523 #define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
\r
10524 #define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/
\r
10525 #define EXTI_EMR3_EM74_Pos (10U)
\r
10526 #define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
\r
10527 #define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
\r
10528 #define EXTI_EMR3_EM75_Pos (11U)
\r
10529 #define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos) /*!< 0x00000800 */
\r
10530 #define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk /*!< Event Mask on line 75 */
\r
10531 #define EXTI_EMR3_EM76_Pos (12U)
\r
10532 #define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos) /*!< 0x00001000 */
\r
10533 #define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk /*!< Event Mask on line 76 */
\r
10534 #define EXTI_EMR3_EM77_Pos (13U)
\r
10535 #define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
\r
10536 #define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
\r
10537 #define EXTI_EMR3_EM78_Pos (14U)
\r
10538 #define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos) /*!< 0x00004000 */
\r
10539 #define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk /*!< Event Mask on line 78 */
\r
10540 #define EXTI_EMR3_EM79_Pos (15U)
\r
10541 #define EXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos) /*!< 0x00008000 */
\r
10542 #define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk /*!< Event Mask on line 79 */
\r
10543 #define EXTI_EMR3_EM80_Pos (16U)
\r
10544 #define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */
\r
10545 #define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */
\r
10546 #define EXTI_EMR3_EM81_Pos (17U)
\r
10547 #define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */
\r
10548 #define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */
\r
10549 #define EXTI_EMR3_EM82_Pos (18U)
\r
10550 #define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */
\r
10551 #define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */
\r
10552 #define EXTI_EMR3_EM84_Pos (20U)
\r
10553 #define EXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos) /*!< 0x00100000 */
\r
10554 #define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk /*!< Event Mask on line 84 */
\r
10555 #define EXTI_EMR3_EM85_Pos (21U)
\r
10556 #define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */
\r
10557 #define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */
\r
10558 #define EXTI_EMR3_EM86_Pos (22U)
\r
10559 #define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos) /*!< 0x00400000 */
\r
10560 #define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk /*!< Event Mask on line 86 */
\r
10561 #define EXTI_EMR3_EM87_Pos (23U)
\r
10562 #define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */
\r
10563 #define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */
\r
10565 /******************* Bit definition for EXTI_PR3 register ********************/
\r
10566 #define EXTI_PR3_PR_Pos (18U)
\r
10567 #define EXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos) /*!< 0x00740000 */
\r
10568 #define EXTI_PR3_PR EXTI_PR3_PR_Msk /*!< Pending bit */
\r
10569 #define EXTI_PR3_PR82_Pos (18U)
\r
10570 #define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos) /*!< 0x00040000 */
\r
10571 #define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk /*!< Pending bit for line 82 */
\r
10572 #define EXTI_PR3_PR84_Pos (20U)
\r
10573 #define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos) /*!< 0x00100000 */
\r
10574 #define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk /*!< Pending bit for line 84 */
\r
10575 #define EXTI_PR3_PR85_Pos (21U)
\r
10576 #define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos) /*!< 0x00200000 */
\r
10577 #define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk /*!< Pending bit for line 85 */
\r
10578 #define EXTI_PR3_PR86_Pos (22U)
\r
10579 #define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos) /*!< 0x00400000 */
\r
10580 #define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk /*!< Pending bit for line 86 */
\r
10581 /******************************************************************************/
\r
10585 /******************************************************************************/
\r
10587 * @brief FLASH Total Sectors Number
\r
10589 #define FLASH_SECTOR_TOTAL 8U
\r
10590 #define FLASH_NB_32BITWORD_IN_FLASHWORD 8U
\r
10592 /******************* Bits definition for FLASH_ACR register **********************/
\r
10593 #define FLASH_ACR_LATENCY_Pos (0U)
\r
10594 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
\r
10595 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
\r
10596 #define FLASH_ACR_LATENCY_0WS (0x00000000UL)
\r
10597 #define FLASH_ACR_LATENCY_1WS (0x00000001UL)
\r
10598 #define FLASH_ACR_LATENCY_2WS (0x00000002UL)
\r
10599 #define FLASH_ACR_LATENCY_3WS (0x00000003UL)
\r
10600 #define FLASH_ACR_LATENCY_4WS (0x00000004UL)
\r
10601 #define FLASH_ACR_LATENCY_5WS (0x00000005UL)
\r
10602 #define FLASH_ACR_LATENCY_6WS (0x00000006UL)
\r
10603 #define FLASH_ACR_LATENCY_7WS (0x00000007UL)
\r
10604 #define FLASH_ACR_LATENCY_8WS (0x00000008UL)
\r
10605 #define FLASH_ACR_LATENCY_9WS (0x00000009UL)
\r
10606 #define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
\r
10607 #define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
\r
10608 #define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
\r
10609 #define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
\r
10610 #define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
\r
10611 #define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
\r
10612 #define FLASH_ACR_WRHIGHFREQ_Pos (4U)
\r
10613 #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
\r
10614 #define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk
\r
10615 #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
\r
10616 #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
\r
10618 /******************* Bits definition for FLASH_CR register ***********************/
\r
10619 #define FLASH_CR_LOCK_Pos (0U)
\r
10620 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
\r
10621 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
\r
10622 #define FLASH_CR_PG_Pos (1U)
\r
10623 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */
\r
10624 #define FLASH_CR_PG FLASH_CR_PG_Msk
\r
10625 #define FLASH_CR_SER_Pos (2U)
\r
10626 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */
\r
10627 #define FLASH_CR_SER FLASH_CR_SER_Msk
\r
10628 #define FLASH_CR_BER_Pos (3U)
\r
10629 #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */
\r
10630 #define FLASH_CR_BER FLASH_CR_BER_Msk
\r
10631 #define FLASH_CR_PSIZE_Pos (4U)
\r
10632 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */
\r
10633 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
\r
10634 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */
\r
10635 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */
\r
10636 #define FLASH_CR_FW_Pos (6U)
\r
10637 #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */
\r
10638 #define FLASH_CR_FW FLASH_CR_FW_Msk
\r
10639 #define FLASH_CR_START_Pos (7U)
\r
10640 #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */
\r
10641 #define FLASH_CR_START FLASH_CR_START_Msk
\r
10642 #define FLASH_CR_SNB_Pos (8U)
\r
10643 #define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */
\r
10644 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
\r
10645 #define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */
\r
10646 #define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */
\r
10647 #define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */
\r
10648 #define FLASH_CR_CRC_EN_Pos (15U)
\r
10649 #define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */
\r
10650 #define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk
\r
10651 #define FLASH_CR_EOPIE_Pos (16U)
\r
10652 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */
\r
10653 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
\r
10654 #define FLASH_CR_WRPERRIE_Pos (17U)
\r
10655 #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */
\r
10656 #define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk
\r
10657 #define FLASH_CR_PGSERRIE_Pos (18U)
\r
10658 #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */
\r
10659 #define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk
\r
10660 #define FLASH_CR_STRBERRIE_Pos (19U)
\r
10661 #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
\r
10662 #define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk
\r
10663 #define FLASH_CR_INCERRIE_Pos (21U)
\r
10664 #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */
\r
10665 #define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk
\r
10666 #define FLASH_CR_OPERRIE_Pos (22U)
\r
10667 #define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */
\r
10668 #define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk
\r
10669 #define FLASH_CR_RDPERRIE_Pos (23U)
\r
10670 #define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */
\r
10671 #define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk
\r
10672 #define FLASH_CR_RDSERRIE_Pos (24U)
\r
10673 #define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */
\r
10674 #define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk
\r
10675 #define FLASH_CR_SNECCERRIE_Pos (25U)
\r
10676 #define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
\r
10677 #define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk
\r
10678 #define FLASH_CR_DBECCERRIE_Pos (26U)
\r
10679 #define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
\r
10680 #define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk
\r
10681 #define FLASH_CR_CRCENDIE_Pos (27U)
\r
10682 #define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */
\r
10683 #define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk
\r
10684 #define FLASH_CR_CRCRDERRIE_Pos (28U)
\r
10685 #define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
\r
10686 #define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk
\r
10688 /******************* Bits definition for FLASH_SR register ***********************/
\r
10689 #define FLASH_SR_BSY_Pos (0U)
\r
10690 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
\r
10691 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
\r
10692 #define FLASH_SR_WBNE_Pos (1U)
\r
10693 #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */
\r
10694 #define FLASH_SR_WBNE FLASH_SR_WBNE_Msk
\r
10695 #define FLASH_SR_QW_Pos (2U)
\r
10696 #define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */
\r
10697 #define FLASH_SR_QW FLASH_SR_QW_Msk
\r
10698 #define FLASH_SR_CRC_BUSY_Pos (3U)
\r
10699 #define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */
\r
10700 #define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk
\r
10701 #define FLASH_SR_EOP_Pos (16U)
\r
10702 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */
\r
10703 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
\r
10704 #define FLASH_SR_WRPERR_Pos (17U)
\r
10705 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */
\r
10706 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
\r
10707 #define FLASH_SR_PGSERR_Pos (18U)
\r
10708 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */
\r
10709 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
\r
10710 #define FLASH_SR_STRBERR_Pos (19U)
\r
10711 #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */
\r
10712 #define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk
\r
10713 #define FLASH_SR_INCERR_Pos (21U)
\r
10714 #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */
\r
10715 #define FLASH_SR_INCERR FLASH_SR_INCERR_Msk
\r
10716 #define FLASH_SR_OPERR_Pos (22U)
\r
10717 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */
\r
10718 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
\r
10719 #define FLASH_SR_RDPERR_Pos (23U)
\r
10720 #define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */
\r
10721 #define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk
\r
10722 #define FLASH_SR_RDSERR_Pos (24U)
\r
10723 #define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */
\r
10724 #define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk
\r
10725 #define FLASH_SR_SNECCERR_Pos (25U)
\r
10726 #define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */
\r
10727 #define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk
\r
10728 #define FLASH_SR_DBECCERR_Pos (26U)
\r
10729 #define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */
\r
10730 #define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk
\r
10731 #define FLASH_SR_CRCEND_Pos (27U)
\r
10732 #define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */
\r
10733 #define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk
\r
10734 #define FLASH_SR_CRCRDERR_Pos (28U)
\r
10735 #define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */
\r
10736 #define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk
\r
10738 /******************* Bits definition for FLASH_CCR register *******************/
\r
10739 #define FLASH_CCR_CLR_EOP_Pos (16U)
\r
10740 #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */
\r
10741 #define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk
\r
10742 #define FLASH_CCR_CLR_WRPERR_Pos (17U)
\r
10743 #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
\r
10744 #define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk
\r
10745 #define FLASH_CCR_CLR_PGSERR_Pos (18U)
\r
10746 #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
\r
10747 #define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk
\r
10748 #define FLASH_CCR_CLR_STRBERR_Pos (19U)
\r
10749 #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
\r
10750 #define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk
\r
10751 #define FLASH_CCR_CLR_INCERR_Pos (21U)
\r
10752 #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
\r
10753 #define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk
\r
10754 #define FLASH_CCR_CLR_OPERR_Pos (22U)
\r
10755 #define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
\r
10756 #define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk
\r
10757 #define FLASH_CCR_CLR_RDPERR_Pos (23U)
\r
10758 #define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
\r
10759 #define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk
\r
10760 #define FLASH_CCR_CLR_RDSERR_Pos (24U)
\r
10761 #define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
\r
10762 #define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk
\r
10763 #define FLASH_CCR_CLR_SNECCERR_Pos (25U)
\r
10764 #define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
\r
10765 #define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk
\r
10766 #define FLASH_CCR_CLR_DBECCERR_Pos (26U)
\r
10767 #define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
\r
10768 #define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk
\r
10769 #define FLASH_CCR_CLR_CRCEND_Pos (27U)
\r
10770 #define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
\r
10771 #define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk
\r
10772 #define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
\r
10773 #define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
\r
10774 #define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk
\r
10776 /******************* Bits definition for FLASH_OPTCR register *******************/
\r
10777 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
\r
10778 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
\r
10779 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
\r
10780 #define FLASH_OPTCR_OPTSTART_Pos (1U)
\r
10781 #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
\r
10782 #define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk
\r
10783 #define FLASH_OPTCR_MER_Pos (4U)
\r
10784 #define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */
\r
10785 #define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk
\r
10786 #define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
\r
10787 #define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
\r
10788 #define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk
\r
10789 #define FLASH_OPTCR_SWAP_BANK_Pos (31U)
\r
10790 #define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
\r
10791 #define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk
\r
10793 /******************* Bits definition for FLASH_OPTSR register ***************/
\r
10794 #define FLASH_OPTSR_OPT_BUSY_Pos (0U)
\r
10795 #define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
\r
10796 #define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk
\r
10797 #define FLASH_OPTSR_BOR_LEV_Pos (2U)
\r
10798 #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
\r
10799 #define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk
\r
10800 #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
\r
10801 #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
\r
10802 #define FLASH_OPTSR_IWDG1_SW_Pos (4U)
\r
10803 #define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
\r
10804 #define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk
\r
10805 #define FLASH_OPTSR_IWDG2_SW_Pos (5U)
\r
10806 #define FLASH_OPTSR_IWDG2_SW_Msk (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */
\r
10807 #define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk
\r
10808 #define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
\r
10809 #define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
\r
10810 #define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk
\r
10811 #define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
\r
10812 #define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
\r
10813 #define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk
\r
10814 #define FLASH_OPTSR_RDP_Pos (8U)
\r
10815 #define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */
\r
10816 #define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk
\r
10817 #define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
\r
10818 #define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
\r
10819 #define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk
\r
10820 #define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
\r
10821 #define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
\r
10822 #define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk
\r
10823 #define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
\r
10824 #define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
\r
10825 #define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk
\r
10826 #define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
\r
10827 #define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
\r
10828 #define FLASH_OPTSR_SECURITY_Pos (21U)
\r
10829 #define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
\r
10830 #define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk
\r
10831 #define FLASH_OPTSR_BCM4_Pos (22U)
\r
10832 #define FLASH_OPTSR_BCM4_Msk (0x1UL << FLASH_OPTSR_BCM4_Pos) /*!< 0x00400000 */
\r
10833 #define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk
\r
10834 #define FLASH_OPTSR_BCM7_Pos (23U)
\r
10835 #define FLASH_OPTSR_BCM7_Msk (0x1UL << FLASH_OPTSR_BCM7_Pos) /*!< 0x00800000 */
\r
10836 #define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk
\r
10837 #define FLASH_OPTSR_NRST_STOP_D2_Pos (24U)
\r
10838 #define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */
\r
10839 #define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk
\r
10840 #define FLASH_OPTSR_NRST_STBY_D2_Pos (25U)
\r
10841 #define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */
\r
10842 #define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk
\r
10843 #define FLASH_OPTSR_IO_HSLV_Pos (29U)
\r
10844 #define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
\r
10845 #define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk
\r
10846 #define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
\r
10847 #define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
\r
10848 #define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk
\r
10849 #define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
\r
10850 #define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
\r
10851 #define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk
\r
10853 /******************* Bits definition for FLASH_OPTCCR register *******************/
\r
10854 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
\r
10855 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
\r
10856 #define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
\r
10858 /******************* Bits definition for FLASH_PRAR register *********************/
\r
10859 #define FLASH_PRAR_PROT_AREA_START_Pos (0U)
\r
10860 #define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
\r
10861 #define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk
\r
10862 #define FLASH_PRAR_PROT_AREA_END_Pos (16U)
\r
10863 #define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
\r
10864 #define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk
\r
10865 #define FLASH_PRAR_DMEP_Pos (31U)
\r
10866 #define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */
\r
10867 #define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk
\r
10869 /******************* Bits definition for FLASH_SCAR register *********************/
\r
10870 #define FLASH_SCAR_SEC_AREA_START_Pos (0U)
\r
10871 #define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
\r
10872 #define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk
\r
10873 #define FLASH_SCAR_SEC_AREA_END_Pos (16U)
\r
10874 #define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
\r
10875 #define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk
\r
10876 #define FLASH_SCAR_DMES_Pos (31U)
\r
10877 #define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */
\r
10878 #define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk
\r
10880 /******************* Bits definition for FLASH_WPSN register *********************/
\r
10881 #define FLASH_WPSN_WRPSN_Pos (0U)
\r
10882 #define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */
\r
10883 #define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk
\r
10885 /******************* Bits definition for FLASH_BOOT7_CUR register ****************/
\r
10886 #define FLASH_BOOT7_BCM7_ADD0_Pos (0U)
\r
10887 #define FLASH_BOOT7_BCM7_ADD0_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */
\r
10888 #define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk
\r
10889 #define FLASH_BOOT7_BCM7_ADD1_Pos (16U)
\r
10890 #define FLASH_BOOT7_BCM7_ADD1_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */
\r
10891 #define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk
\r
10893 /******************* Bits definition for FLASH_BOOT4 register ********************/
\r
10894 #define FLASH_BOOT4_BCM4_ADD0_Pos (0U)
\r
10895 #define FLASH_BOOT4_BCM4_ADD0_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */
\r
10896 #define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk
\r
10897 #define FLASH_BOOT4_BCM4_ADD1_Pos (16U)
\r
10898 #define FLASH_BOOT4_BCM4_ADD1_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */
\r
10899 #define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk
\r
10901 /******************* Bits definition for FLASH_CRCCR register ********************/
\r
10902 #define FLASH_CRCCR_CRC_SECT_Pos (0U)
\r
10903 #define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
\r
10904 #define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk
\r
10905 #define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
\r
10906 #define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
\r
10907 #define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk
\r
10908 #define FLASH_CRCCR_ADD_SECT_Pos (9U)
\r
10909 #define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
\r
10910 #define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk
\r
10911 #define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
\r
10912 #define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
\r
10913 #define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk
\r
10914 #define FLASH_CRCCR_START_CRC_Pos (16U)
\r
10915 #define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
\r
10916 #define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk
\r
10917 #define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
\r
10918 #define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
\r
10919 #define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk
\r
10920 #define FLASH_CRCCR_CRC_BURST_Pos (20U)
\r
10921 #define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
\r
10922 #define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk
\r
10923 #define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
\r
10924 #define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
\r
10925 #define FLASH_CRCCR_ALL_BANK_Pos (22U)
\r
10926 #define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
\r
10927 #define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk
\r
10929 /******************* Bits definition for FLASH_CRCSADD register ****************/
\r
10930 #define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
\r
10931 #define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
\r
10932 #define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk
\r
10934 /******************* Bits definition for FLASH_CRCEADD register ****************/
\r
10935 #define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
\r
10936 #define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
\r
10937 #define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk
\r
10939 /******************* Bits definition for FLASH_CRCDATA register ***************/
\r
10940 #define FLASH_CRCDATA_CRC_DATA_Pos (0U)
\r
10941 #define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
\r
10942 #define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk
\r
10944 /******************* Bits definition for FLASH_ECC_FA register *******************/
\r
10945 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
\r
10946 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
\r
10947 #define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
\r
10949 /******************************************************************************/
\r
10951 /* Flexible Memory Controller */
\r
10953 /******************************************************************************/
\r
10954 /****************** Bit definition for FMC_BCR1 register *******************/
\r
10955 #define FMC_BCR1_CCLKEN_Pos (20U)
\r
10956 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
\r
10957 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
\r
10958 #define FMC_BCR1_WFDIS_Pos (21U)
\r
10959 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
\r
10960 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
\r
10962 #define FMC_BCR1_BMAP_Pos (24U)
\r
10963 #define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos) /*!< 0x03000000 */
\r
10964 #define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk /*!<BMAP[1:0] FMC bank mapping */
\r
10965 #define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos) /*!< 0x01000000 */
\r
10966 #define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos) /*!< 0x02000000 */
\r
10968 #define FMC_BCR1_FMCEN_Pos (31U)
\r
10969 #define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */
\r
10970 #define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller Enable */
\r
10971 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
\r
10972 #define FMC_BCRx_MBKEN_Pos (0U)
\r
10973 #define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
\r
10974 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
\r
10975 #define FMC_BCRx_MUXEN_Pos (1U)
\r
10976 #define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
\r
10977 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
\r
10979 #define FMC_BCRx_MTYP_Pos (2U)
\r
10980 #define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
\r
10981 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
\r
10982 #define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
\r
10983 #define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
\r
10985 #define FMC_BCRx_MWID_Pos (4U)
\r
10986 #define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
\r
10987 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
\r
10988 #define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
\r
10989 #define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
\r
10991 #define FMC_BCRx_FACCEN_Pos (6U)
\r
10992 #define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
\r
10993 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
\r
10994 #define FMC_BCRx_BURSTEN_Pos (8U)
\r
10995 #define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
\r
10996 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
\r
10997 #define FMC_BCRx_WAITPOL_Pos (9U)
\r
10998 #define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
\r
10999 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
\r
11000 #define FMC_BCRx_WAITCFG_Pos (11U)
\r
11001 #define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
\r
11002 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
\r
11003 #define FMC_BCRx_WREN_Pos (12U)
\r
11004 #define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
\r
11005 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
\r
11006 #define FMC_BCRx_WAITEN_Pos (13U)
\r
11007 #define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
\r
11008 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
\r
11009 #define FMC_BCRx_EXTMOD_Pos (14U)
\r
11010 #define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
\r
11011 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
\r
11012 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
\r
11013 #define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
\r
11014 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
\r
11016 #define FMC_BCRx_CPSIZE_Pos (16U)
\r
11017 #define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
\r
11018 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
\r
11019 #define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
\r
11020 #define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
\r
11021 #define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
\r
11023 #define FMC_BCRx_CBURSTRW_Pos (19U)
\r
11024 #define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
\r
11025 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
\r
11027 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
\r
11028 #define FMC_BTRx_ADDSET_Pos (0U)
\r
11029 #define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
\r
11030 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
11031 #define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
\r
11032 #define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
\r
11033 #define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
\r
11034 #define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
\r
11036 #define FMC_BTRx_ADDHLD_Pos (4U)
\r
11037 #define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
\r
11038 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
11039 #define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
\r
11040 #define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
\r
11041 #define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
\r
11042 #define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
\r
11044 #define FMC_BTRx_DATAST_Pos (8U)
\r
11045 #define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
\r
11046 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
\r
11047 #define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
\r
11048 #define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
\r
11049 #define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
\r
11050 #define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
\r
11051 #define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
\r
11052 #define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
\r
11053 #define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
\r
11054 #define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
\r
11056 #define FMC_BTRx_BUSTURN_Pos (16U)
\r
11057 #define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
\r
11058 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
11059 #define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
\r
11060 #define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
\r
11061 #define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
\r
11062 #define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
\r
11064 #define FMC_BTRx_CLKDIV_Pos (20U)
\r
11065 #define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
\r
11066 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
\r
11067 #define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
\r
11068 #define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
\r
11069 #define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
\r
11070 #define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
\r
11072 #define FMC_BTRx_DATLAT_Pos (24U)
\r
11073 #define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
\r
11074 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
\r
11075 #define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
\r
11076 #define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
\r
11077 #define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
\r
11078 #define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
\r
11080 #define FMC_BTRx_ACCMOD_Pos (28U)
\r
11081 #define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
\r
11082 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
\r
11083 #define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
\r
11084 #define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
\r
11086 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
\r
11087 #define FMC_BWTRx_ADDSET_Pos (0U)
\r
11088 #define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
\r
11089 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
\r
11090 #define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
\r
11091 #define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
\r
11092 #define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
\r
11093 #define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
\r
11095 #define FMC_BWTRx_ADDHLD_Pos (4U)
\r
11096 #define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
\r
11097 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
\r
11098 #define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
\r
11099 #define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
\r
11100 #define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
\r
11101 #define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
\r
11103 #define FMC_BWTRx_DATAST_Pos (8U)
\r
11104 #define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
\r
11105 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
\r
11106 #define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
\r
11107 #define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
\r
11108 #define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
\r
11109 #define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
\r
11110 #define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
\r
11111 #define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
\r
11112 #define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
\r
11113 #define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
\r
11115 #define FMC_BWTRx_BUSTURN_Pos (16U)
\r
11116 #define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
\r
11117 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
\r
11118 #define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
\r
11119 #define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
\r
11120 #define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
\r
11121 #define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
\r
11123 #define FMC_BWTRx_ACCMOD_Pos (28U)
\r
11124 #define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
\r
11125 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
\r
11126 #define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
\r
11127 #define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
\r
11129 /****************** Bit definition for FMC_PCR register *******************/
\r
11130 #define FMC_PCR_PWAITEN_Pos (1U)
\r
11131 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
\r
11132 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
\r
11133 #define FMC_PCR_PBKEN_Pos (2U)
\r
11134 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
\r
11135 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
\r
11137 #define FMC_PCR_PWID_Pos (4U)
\r
11138 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
\r
11139 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
\r
11140 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
\r
11141 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
\r
11143 #define FMC_PCR_ECCEN_Pos (6U)
\r
11144 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
\r
11145 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
\r
11147 #define FMC_PCR_TCLR_Pos (9U)
\r
11148 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
\r
11149 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
\r
11150 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
\r
11151 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
\r
11152 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
\r
11153 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
\r
11155 #define FMC_PCR_TAR_Pos (13U)
\r
11156 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
\r
11157 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
\r
11158 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
\r
11159 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
\r
11160 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
\r
11161 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
\r
11163 #define FMC_PCR_ECCPS_Pos (17U)
\r
11164 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
\r
11165 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
\r
11166 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
\r
11167 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
\r
11168 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
\r
11170 /******************* Bit definition for FMC_SR register *******************/
\r
11171 #define FMC_SR_IRS_Pos (0U)
\r
11172 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
\r
11173 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
\r
11174 #define FMC_SR_ILS_Pos (1U)
\r
11175 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
\r
11176 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
\r
11177 #define FMC_SR_IFS_Pos (2U)
\r
11178 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
\r
11179 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
\r
11180 #define FMC_SR_IREN_Pos (3U)
\r
11181 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
\r
11182 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
\r
11183 #define FMC_SR_ILEN_Pos (4U)
\r
11184 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
\r
11185 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
\r
11186 #define FMC_SR_IFEN_Pos (5U)
\r
11187 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
\r
11188 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
\r
11189 #define FMC_SR_FEMPT_Pos (6U)
\r
11190 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
\r
11191 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
\r
11193 /****************** Bit definition for FMC_PMEM register ******************/
\r
11194 #define FMC_PMEM_MEMSET_Pos (0U)
\r
11195 #define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
\r
11196 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
\r
11197 #define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
\r
11198 #define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
\r
11199 #define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
\r
11200 #define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
\r
11201 #define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
\r
11202 #define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
\r
11203 #define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
\r
11204 #define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
\r
11206 #define FMC_PMEM_MEMWAIT_Pos (8U)
\r
11207 #define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
\r
11208 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
\r
11209 #define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
\r
11210 #define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
\r
11211 #define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
\r
11212 #define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
\r
11213 #define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
\r
11214 #define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
\r
11215 #define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
\r
11216 #define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
\r
11218 #define FMC_PMEM_MEMHOLD_Pos (16U)
\r
11219 #define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
\r
11220 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
\r
11221 #define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
\r
11222 #define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
\r
11223 #define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
\r
11224 #define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
\r
11225 #define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
\r
11226 #define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
\r
11227 #define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
\r
11228 #define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
\r
11230 #define FMC_PMEM_MEMHIZ_Pos (24U)
\r
11231 #define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
\r
11232 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
\r
11233 #define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
\r
11234 #define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
\r
11235 #define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
\r
11236 #define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
\r
11237 #define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
\r
11238 #define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
\r
11239 #define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
\r
11240 #define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
\r
11242 /****************** Bit definition for FMC_PATT register ******************/
\r
11243 #define FMC_PATT_ATTSET_Pos (0U)
\r
11244 #define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
\r
11245 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
\r
11246 #define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
\r
11247 #define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
\r
11248 #define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
\r
11249 #define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
\r
11250 #define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
\r
11251 #define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
\r
11252 #define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
\r
11253 #define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
\r
11255 #define FMC_PATT_ATTWAIT_Pos (8U)
\r
11256 #define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
\r
11257 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
\r
11258 #define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
\r
11259 #define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
\r
11260 #define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
\r
11261 #define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
\r
11262 #define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
\r
11263 #define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
\r
11264 #define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
\r
11265 #define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
\r
11267 #define FMC_PATT_ATTHOLD_Pos (16U)
\r
11268 #define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
\r
11269 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
\r
11270 #define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
\r
11271 #define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
\r
11272 #define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
\r
11273 #define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
\r
11274 #define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
\r
11275 #define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
\r
11276 #define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
\r
11277 #define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
\r
11279 #define FMC_PATT_ATTHIZ_Pos (24U)
\r
11280 #define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
\r
11281 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
\r
11282 #define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
\r
11283 #define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
\r
11284 #define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
\r
11285 #define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
\r
11286 #define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
\r
11287 #define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
\r
11288 #define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
\r
11289 #define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
\r
11291 /****************** Bit definition for FMC_ECCR3 register ******************/
\r
11292 #define FMC_ECCR3_ECC3_Pos (0U)
\r
11293 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
\r
11294 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
\r
11296 /****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
\r
11297 #define FMC_SDCRx_NC_Pos (0U)
\r
11298 #define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) /*!< 0x00000003 */
\r
11299 #define FMC_SDCRx_NC FMC_SDCRx_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
\r
11300 #define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) /*!< 0x00000001 */
\r
11301 #define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) /*!< 0x00000002 */
\r
11303 #define FMC_SDCRx_NR_Pos (2U)
\r
11304 #define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) /*!< 0x0000000C */
\r
11305 #define FMC_SDCRx_NR FMC_SDCRx_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
\r
11306 #define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) /*!< 0x00000004 */
\r
11307 #define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) /*!< 0x00000008 */
\r
11309 #define FMC_SDCRx_MWID_Pos (4U)
\r
11310 #define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000030 */
\r
11311 #define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
\r
11312 #define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000010 */
\r
11313 #define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000020 */
\r
11315 #define FMC_SDCRx_NB_Pos (6U)
\r
11316 #define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) /*!< 0x00000040 */
\r
11317 #define FMC_SDCRx_NB FMC_SDCRx_NB_Msk /*!<Number of internal bank */
\r
11319 #define FMC_SDCRx_CAS_Pos (7U)
\r
11320 #define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000180 */
\r
11321 #define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
\r
11322 #define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000080 */
\r
11323 #define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000100 */
\r
11325 #define FMC_SDCRx_WP_Pos (9U)
\r
11326 #define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) /*!< 0x00000200 */
\r
11327 #define FMC_SDCRx_WP FMC_SDCRx_WP_Msk /*!<Write protection */
\r
11329 #define FMC_SDCRx_SDCLK_Pos (10U)
\r
11330 #define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000C00 */
\r
11331 #define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk /*!<SDRAM clock configuration */
\r
11332 #define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000400 */
\r
11333 #define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000800 */
\r
11335 #define FMC_SDCRx_RBURST_Pos (12U)
\r
11336 #define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos) /*!< 0x00001000 */
\r
11337 #define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk /*!<Read burst */
\r
11339 #define FMC_SDCRx_RPIPE_Pos (13U)
\r
11340 #define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00006000 */
\r
11341 #define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk /*!<Write protection */
\r
11342 #define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00002000 */
\r
11343 #define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00004000 */
\r
11345 /****************** Bit definition for FMC_SDTRx(1,2) register ******************/
\r
11346 #define FMC_SDTRx_TMRD_Pos (0U)
\r
11347 #define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) /*!< 0x0000000F */
\r
11348 #define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
\r
11349 #define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000001 */
\r
11350 #define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000002 */
\r
11351 #define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000004 */
\r
11352 #define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000008 */
\r
11354 #define FMC_SDTRx_TXSR_Pos (4U)
\r
11355 #define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) /*!< 0x000000F0 */
\r
11356 #define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
\r
11357 #define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000010 */
\r
11358 #define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000020 */
\r
11359 #define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000040 */
\r
11360 #define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000080 */
\r
11362 #define FMC_SDTRx_TRAS_Pos (8U)
\r
11363 #define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000F00 */
\r
11364 #define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
\r
11365 #define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000100 */
\r
11366 #define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000200 */
\r
11367 #define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000400 */
\r
11368 #define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000800 */
\r
11370 #define FMC_SDTRx_TRC_Pos (12U)
\r
11371 #define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) /*!< 0x0000F000 */
\r
11372 #define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
\r
11373 #define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) /*!< 0x00001000 */
\r
11374 #define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) /*!< 0x00002000 */
\r
11375 #define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) /*!< 0x00004000 */
\r
11377 #define FMC_SDTRx_TWR_Pos (16U)
\r
11378 #define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) /*!< 0x000F0000 */
\r
11379 #define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
\r
11380 #define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) /*!< 0x00010000 */
\r
11381 #define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) /*!< 0x00020000 */
\r
11382 #define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) /*!< 0x00040000 */
\r
11384 #define FMC_SDTRx_TRP_Pos (20U)
\r
11385 #define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) /*!< 0x00F00000 */
\r
11386 #define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
\r
11387 #define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) /*!< 0x00100000 */
\r
11388 #define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) /*!< 0x00200000 */
\r
11389 #define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) /*!< 0x00400000 */
\r
11391 #define FMC_SDTRx_TRCD_Pos (24U)
\r
11392 #define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) /*!< 0x0F000000 */
\r
11393 #define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
\r
11394 #define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) /*!< 0x01000000 */
\r
11395 #define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) /*!< 0x02000000 */
\r
11396 #define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) /*!< 0x04000000 */
\r
11398 /****************** Bit definition for FMC_SDCMR register ******************/
\r
11399 #define FMC_SDCMR_MODE_Pos (0U)
\r
11400 #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
\r
11401 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
\r
11402 #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
\r
11403 #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
\r
11404 #define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
\r
11406 #define FMC_SDCMR_CTB2_Pos (3U)
\r
11407 #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
\r
11408 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
\r
11410 #define FMC_SDCMR_CTB1_Pos (4U)
\r
11411 #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
\r
11412 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
\r
11414 #define FMC_SDCMR_NRFS_Pos (5U)
\r
11415 #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
\r
11416 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
\r
11417 #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
\r
11418 #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
\r
11419 #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
\r
11420 #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
\r
11422 #define FMC_SDCMR_MRD_Pos (9U)
\r
11423 #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
\r
11424 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
\r
11426 /****************** Bit definition for FMC_SDRTR register ******************/
\r
11427 #define FMC_SDRTR_CRE_Pos (0U)
\r
11428 #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
\r
11429 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
\r
11431 #define FMC_SDRTR_COUNT_Pos (1U)
\r
11432 #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
\r
11433 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
\r
11435 #define FMC_SDRTR_REIE_Pos (14U)
\r
11436 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
\r
11437 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
\r
11439 /****************** Bit definition for FMC_SDSR register ******************/
\r
11440 #define FMC_SDSR_RE_Pos (0U)
\r
11441 #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
\r
11442 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
\r
11444 #define FMC_SDSR_MODES1_Pos (1U)
\r
11445 #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
\r
11446 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
\r
11447 #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
\r
11448 #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
\r
11450 #define FMC_SDSR_MODES2_Pos (3U)
\r
11451 #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
\r
11452 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
\r
11453 #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
\r
11454 #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
\r
11456 /******************************************************************************/
\r
11458 /* General Purpose I/O */
\r
11460 /******************************************************************************/
\r
11461 /****************** Bits definition for GPIO_MODER register *****************/
\r
11462 #define GPIO_MODER_MODE0_Pos (0U)
\r
11463 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
\r
11464 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
\r
11465 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
\r
11466 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
\r
11468 #define GPIO_MODER_MODE1_Pos (2U)
\r
11469 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
\r
11470 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
\r
11471 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
\r
11472 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
\r
11474 #define GPIO_MODER_MODE2_Pos (4U)
\r
11475 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
\r
11476 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
\r
11477 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
\r
11478 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
\r
11480 #define GPIO_MODER_MODE3_Pos (6U)
\r
11481 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
\r
11482 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
\r
11483 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
\r
11484 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
\r
11486 #define GPIO_MODER_MODE4_Pos (8U)
\r
11487 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
\r
11488 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
\r
11489 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
\r
11490 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
\r
11492 #define GPIO_MODER_MODE5_Pos (10U)
\r
11493 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
\r
11494 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
\r
11495 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
\r
11496 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
\r
11498 #define GPIO_MODER_MODE6_Pos (12U)
\r
11499 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
\r
11500 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
\r
11501 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
\r
11502 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
\r
11504 #define GPIO_MODER_MODE7_Pos (14U)
\r
11505 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
\r
11506 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
\r
11507 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
\r
11508 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
\r
11510 #define GPIO_MODER_MODE8_Pos (16U)
\r
11511 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
\r
11512 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
\r
11513 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
\r
11514 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
\r
11516 #define GPIO_MODER_MODE9_Pos (18U)
\r
11517 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
\r
11518 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
\r
11519 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
\r
11520 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
\r
11522 #define GPIO_MODER_MODE10_Pos (20U)
\r
11523 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
\r
11524 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
\r
11525 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
\r
11526 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
\r
11528 #define GPIO_MODER_MODE11_Pos (22U)
\r
11529 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
\r
11530 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
\r
11531 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
\r
11532 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
\r
11534 #define GPIO_MODER_MODE12_Pos (24U)
\r
11535 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
\r
11536 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
\r
11537 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
\r
11538 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
\r
11540 #define GPIO_MODER_MODE13_Pos (26U)
\r
11541 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
\r
11542 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
\r
11543 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
\r
11544 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
\r
11546 #define GPIO_MODER_MODE14_Pos (28U)
\r
11547 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
\r
11548 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
\r
11549 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
\r
11550 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
\r
11552 #define GPIO_MODER_MODE15_Pos (30U)
\r
11553 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
\r
11554 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
\r
11555 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
\r
11556 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
\r
11558 /****************** Bits definition for GPIO_OTYPER register ****************/
\r
11559 #define GPIO_OTYPER_OT0_Pos (0U)
\r
11560 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
\r
11561 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
\r
11562 #define GPIO_OTYPER_OT1_Pos (1U)
\r
11563 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
\r
11564 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
\r
11565 #define GPIO_OTYPER_OT2_Pos (2U)
\r
11566 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
\r
11567 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
\r
11568 #define GPIO_OTYPER_OT3_Pos (3U)
\r
11569 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
\r
11570 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
\r
11571 #define GPIO_OTYPER_OT4_Pos (4U)
\r
11572 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
\r
11573 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
\r
11574 #define GPIO_OTYPER_OT5_Pos (5U)
\r
11575 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
\r
11576 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
\r
11577 #define GPIO_OTYPER_OT6_Pos (6U)
\r
11578 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
\r
11579 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
\r
11580 #define GPIO_OTYPER_OT7_Pos (7U)
\r
11581 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
\r
11582 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
\r
11583 #define GPIO_OTYPER_OT8_Pos (8U)
\r
11584 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
\r
11585 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
\r
11586 #define GPIO_OTYPER_OT9_Pos (9U)
\r
11587 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
\r
11588 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
\r
11589 #define GPIO_OTYPER_OT10_Pos (10U)
\r
11590 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
\r
11591 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
\r
11592 #define GPIO_OTYPER_OT11_Pos (11U)
\r
11593 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
\r
11594 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
\r
11595 #define GPIO_OTYPER_OT12_Pos (12U)
\r
11596 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
\r
11597 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
\r
11598 #define GPIO_OTYPER_OT13_Pos (13U)
\r
11599 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
\r
11600 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
\r
11601 #define GPIO_OTYPER_OT14_Pos (14U)
\r
11602 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
\r
11603 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
\r
11604 #define GPIO_OTYPER_OT15_Pos (15U)
\r
11605 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
\r
11606 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
\r
11608 /****************** Bits definition for GPIO_OSPEEDR register ***************/
\r
11609 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
\r
11610 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
\r
11611 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
\r
11612 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
\r
11613 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
\r
11615 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
\r
11616 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
\r
11617 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
\r
11618 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
\r
11619 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
\r
11621 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
\r
11622 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
\r
11623 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
\r
11624 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
\r
11625 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
\r
11627 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
\r
11628 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
\r
11629 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
\r
11630 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
\r
11631 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
\r
11633 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
\r
11634 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
\r
11635 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
\r
11636 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
\r
11637 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
\r
11639 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
\r
11640 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
\r
11641 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
\r
11642 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
\r
11643 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
\r
11645 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
\r
11646 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
\r
11647 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
\r
11648 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
\r
11649 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
\r
11651 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
\r
11652 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
\r
11653 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
\r
11654 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
\r
11655 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
\r
11657 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
\r
11658 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
\r
11659 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
\r
11660 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
\r
11661 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
\r
11663 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
\r
11664 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
\r
11665 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
\r
11666 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
\r
11667 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
\r
11669 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
\r
11670 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
\r
11671 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
\r
11672 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
\r
11673 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
\r
11675 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
\r
11676 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
\r
11677 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
\r
11678 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
\r
11679 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
\r
11681 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
\r
11682 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
\r
11683 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
\r
11684 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
\r
11685 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
\r
11687 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
\r
11688 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
\r
11689 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
\r
11690 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
\r
11691 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
\r
11693 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
\r
11694 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
\r
11695 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
\r
11696 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
\r
11697 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
\r
11699 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
\r
11700 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
\r
11701 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
\r
11702 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
\r
11703 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
\r
11705 /****************** Bits definition for GPIO_PUPDR register *****************/
\r
11706 #define GPIO_PUPDR_PUPD0_Pos (0U)
\r
11707 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
\r
11708 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
\r
11709 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
\r
11710 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
\r
11712 #define GPIO_PUPDR_PUPD1_Pos (2U)
\r
11713 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
\r
11714 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
\r
11715 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
\r
11716 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
\r
11718 #define GPIO_PUPDR_PUPD2_Pos (4U)
\r
11719 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
\r
11720 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
\r
11721 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
\r
11722 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
\r
11724 #define GPIO_PUPDR_PUPD3_Pos (6U)
\r
11725 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
\r
11726 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
\r
11727 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
\r
11728 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
\r
11730 #define GPIO_PUPDR_PUPD4_Pos (8U)
\r
11731 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
\r
11732 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
\r
11733 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
\r
11734 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
\r
11736 #define GPIO_PUPDR_PUPD5_Pos (10U)
\r
11737 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
\r
11738 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
\r
11739 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
\r
11740 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
\r
11742 #define GPIO_PUPDR_PUPD6_Pos (12U)
\r
11743 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
\r
11744 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
\r
11745 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
\r
11746 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
\r
11748 #define GPIO_PUPDR_PUPD7_Pos (14U)
\r
11749 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
\r
11750 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
\r
11751 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
\r
11752 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
\r
11754 #define GPIO_PUPDR_PUPD8_Pos (16U)
\r
11755 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
\r
11756 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
\r
11757 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
\r
11758 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
\r
11760 #define GPIO_PUPDR_PUPD9_Pos (18U)
\r
11761 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
\r
11762 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
\r
11763 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
\r
11764 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
\r
11766 #define GPIO_PUPDR_PUPD10_Pos (20U)
\r
11767 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
\r
11768 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
\r
11769 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
\r
11770 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
\r
11772 #define GPIO_PUPDR_PUPD11_Pos (22U)
\r
11773 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
\r
11774 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
\r
11775 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
\r
11776 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
\r
11778 #define GPIO_PUPDR_PUPD12_Pos (24U)
\r
11779 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
\r
11780 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
\r
11781 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
\r
11782 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
\r
11784 #define GPIO_PUPDR_PUPD13_Pos (26U)
\r
11785 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
\r
11786 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
\r
11787 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
\r
11788 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
\r
11790 #define GPIO_PUPDR_PUPD14_Pos (28U)
\r
11791 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
\r
11792 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
\r
11793 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
\r
11794 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
\r
11796 #define GPIO_PUPDR_PUPD15_Pos (30U)
\r
11797 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
\r
11798 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
\r
11799 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
\r
11800 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
\r
11802 /****************** Bits definition for GPIO_IDR register *******************/
\r
11803 #define GPIO_IDR_ID0_Pos (0U)
\r
11804 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
\r
11805 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
\r
11806 #define GPIO_IDR_ID1_Pos (1U)
\r
11807 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
\r
11808 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
\r
11809 #define GPIO_IDR_ID2_Pos (2U)
\r
11810 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
\r
11811 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
\r
11812 #define GPIO_IDR_ID3_Pos (3U)
\r
11813 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
\r
11814 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
\r
11815 #define GPIO_IDR_ID4_Pos (4U)
\r
11816 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
\r
11817 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
\r
11818 #define GPIO_IDR_ID5_Pos (5U)
\r
11819 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
\r
11820 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
\r
11821 #define GPIO_IDR_ID6_Pos (6U)
\r
11822 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
\r
11823 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
\r
11824 #define GPIO_IDR_ID7_Pos (7U)
\r
11825 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
\r
11826 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
\r
11827 #define GPIO_IDR_ID8_Pos (8U)
\r
11828 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
\r
11829 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
\r
11830 #define GPIO_IDR_ID9_Pos (9U)
\r
11831 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
\r
11832 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
\r
11833 #define GPIO_IDR_ID10_Pos (10U)
\r
11834 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
\r
11835 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
\r
11836 #define GPIO_IDR_ID11_Pos (11U)
\r
11837 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
\r
11838 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
\r
11839 #define GPIO_IDR_ID12_Pos (12U)
\r
11840 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
\r
11841 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
\r
11842 #define GPIO_IDR_ID13_Pos (13U)
\r
11843 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
\r
11844 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
\r
11845 #define GPIO_IDR_ID14_Pos (14U)
\r
11846 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
\r
11847 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
\r
11848 #define GPIO_IDR_ID15_Pos (15U)
\r
11849 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
\r
11850 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
\r
11852 /****************** Bits definition for GPIO_ODR register *******************/
\r
11853 #define GPIO_ODR_OD0_Pos (0U)
\r
11854 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
\r
11855 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
\r
11856 #define GPIO_ODR_OD1_Pos (1U)
\r
11857 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
\r
11858 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
\r
11859 #define GPIO_ODR_OD2_Pos (2U)
\r
11860 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
\r
11861 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
\r
11862 #define GPIO_ODR_OD3_Pos (3U)
\r
11863 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
\r
11864 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
\r
11865 #define GPIO_ODR_OD4_Pos (4U)
\r
11866 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
\r
11867 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
\r
11868 #define GPIO_ODR_OD5_Pos (5U)
\r
11869 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
\r
11870 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
\r
11871 #define GPIO_ODR_OD6_Pos (6U)
\r
11872 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
\r
11873 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
\r
11874 #define GPIO_ODR_OD7_Pos (7U)
\r
11875 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
\r
11876 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
\r
11877 #define GPIO_ODR_OD8_Pos (8U)
\r
11878 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
\r
11879 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
\r
11880 #define GPIO_ODR_OD9_Pos (9U)
\r
11881 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
\r
11882 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
\r
11883 #define GPIO_ODR_OD10_Pos (10U)
\r
11884 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
\r
11885 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
\r
11886 #define GPIO_ODR_OD11_Pos (11U)
\r
11887 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
\r
11888 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
\r
11889 #define GPIO_ODR_OD12_Pos (12U)
\r
11890 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
\r
11891 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
\r
11892 #define GPIO_ODR_OD13_Pos (13U)
\r
11893 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
\r
11894 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
\r
11895 #define GPIO_ODR_OD14_Pos (14U)
\r
11896 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
\r
11897 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
\r
11898 #define GPIO_ODR_OD15_Pos (15U)
\r
11899 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
\r
11900 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
\r
11902 /****************** Bits definition for GPIO_BSRR register ******************/
\r
11903 #define GPIO_BSRR_BS0_Pos (0U)
\r
11904 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
\r
11905 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
\r
11906 #define GPIO_BSRR_BS1_Pos (1U)
\r
11907 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
\r
11908 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
\r
11909 #define GPIO_BSRR_BS2_Pos (2U)
\r
11910 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
\r
11911 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
\r
11912 #define GPIO_BSRR_BS3_Pos (3U)
\r
11913 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
\r
11914 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
\r
11915 #define GPIO_BSRR_BS4_Pos (4U)
\r
11916 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
\r
11917 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
\r
11918 #define GPIO_BSRR_BS5_Pos (5U)
\r
11919 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
\r
11920 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
\r
11921 #define GPIO_BSRR_BS6_Pos (6U)
\r
11922 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
\r
11923 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
\r
11924 #define GPIO_BSRR_BS7_Pos (7U)
\r
11925 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
\r
11926 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
\r
11927 #define GPIO_BSRR_BS8_Pos (8U)
\r
11928 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
\r
11929 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
\r
11930 #define GPIO_BSRR_BS9_Pos (9U)
\r
11931 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
\r
11932 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
\r
11933 #define GPIO_BSRR_BS10_Pos (10U)
\r
11934 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
\r
11935 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
\r
11936 #define GPIO_BSRR_BS11_Pos (11U)
\r
11937 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
\r
11938 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
\r
11939 #define GPIO_BSRR_BS12_Pos (12U)
\r
11940 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
\r
11941 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
\r
11942 #define GPIO_BSRR_BS13_Pos (13U)
\r
11943 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
\r
11944 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
\r
11945 #define GPIO_BSRR_BS14_Pos (14U)
\r
11946 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
\r
11947 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
\r
11948 #define GPIO_BSRR_BS15_Pos (15U)
\r
11949 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
\r
11950 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
\r
11951 #define GPIO_BSRR_BR0_Pos (16U)
\r
11952 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
\r
11953 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
\r
11954 #define GPIO_BSRR_BR1_Pos (17U)
\r
11955 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
\r
11956 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
\r
11957 #define GPIO_BSRR_BR2_Pos (18U)
\r
11958 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
\r
11959 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
\r
11960 #define GPIO_BSRR_BR3_Pos (19U)
\r
11961 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
\r
11962 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
\r
11963 #define GPIO_BSRR_BR4_Pos (20U)
\r
11964 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
\r
11965 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
\r
11966 #define GPIO_BSRR_BR5_Pos (21U)
\r
11967 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
\r
11968 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
\r
11969 #define GPIO_BSRR_BR6_Pos (22U)
\r
11970 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
\r
11971 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
\r
11972 #define GPIO_BSRR_BR7_Pos (23U)
\r
11973 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
\r
11974 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
\r
11975 #define GPIO_BSRR_BR8_Pos (24U)
\r
11976 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
\r
11977 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
\r
11978 #define GPIO_BSRR_BR9_Pos (25U)
\r
11979 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
\r
11980 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
\r
11981 #define GPIO_BSRR_BR10_Pos (26U)
\r
11982 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
\r
11983 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
\r
11984 #define GPIO_BSRR_BR11_Pos (27U)
\r
11985 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
\r
11986 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
\r
11987 #define GPIO_BSRR_BR12_Pos (28U)
\r
11988 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
\r
11989 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
\r
11990 #define GPIO_BSRR_BR13_Pos (29U)
\r
11991 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
\r
11992 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
\r
11993 #define GPIO_BSRR_BR14_Pos (30U)
\r
11994 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
\r
11995 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
\r
11996 #define GPIO_BSRR_BR15_Pos (31U)
\r
11997 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
\r
11998 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
\r
12000 /****************** Bit definition for GPIO_LCKR register *********************/
\r
12001 #define GPIO_LCKR_LCK0_Pos (0U)
\r
12002 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
\r
12003 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
\r
12004 #define GPIO_LCKR_LCK1_Pos (1U)
\r
12005 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
\r
12006 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
\r
12007 #define GPIO_LCKR_LCK2_Pos (2U)
\r
12008 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
\r
12009 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
\r
12010 #define GPIO_LCKR_LCK3_Pos (3U)
\r
12011 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
\r
12012 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
\r
12013 #define GPIO_LCKR_LCK4_Pos (4U)
\r
12014 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
\r
12015 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
\r
12016 #define GPIO_LCKR_LCK5_Pos (5U)
\r
12017 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
\r
12018 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
\r
12019 #define GPIO_LCKR_LCK6_Pos (6U)
\r
12020 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
\r
12021 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
\r
12022 #define GPIO_LCKR_LCK7_Pos (7U)
\r
12023 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
\r
12024 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
\r
12025 #define GPIO_LCKR_LCK8_Pos (8U)
\r
12026 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
\r
12027 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
\r
12028 #define GPIO_LCKR_LCK9_Pos (9U)
\r
12029 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
\r
12030 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
\r
12031 #define GPIO_LCKR_LCK10_Pos (10U)
\r
12032 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
\r
12033 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
\r
12034 #define GPIO_LCKR_LCK11_Pos (11U)
\r
12035 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
\r
12036 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
\r
12037 #define GPIO_LCKR_LCK12_Pos (12U)
\r
12038 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
\r
12039 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
\r
12040 #define GPIO_LCKR_LCK13_Pos (13U)
\r
12041 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
\r
12042 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
\r
12043 #define GPIO_LCKR_LCK14_Pos (14U)
\r
12044 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
\r
12045 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
\r
12046 #define GPIO_LCKR_LCK15_Pos (15U)
\r
12047 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
\r
12048 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
\r
12049 #define GPIO_LCKR_LCKK_Pos (16U)
\r
12050 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
\r
12051 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
\r
12053 /****************** Bit definition for GPIO_AFRL register ********************/
\r
12054 #define GPIO_AFRL_AFSEL0_Pos (0U)
\r
12055 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
\r
12056 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
\r
12057 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
\r
12058 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
\r
12059 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
\r
12060 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
\r
12061 #define GPIO_AFRL_AFSEL1_Pos (4U)
\r
12062 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
\r
12063 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
\r
12064 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
\r
12065 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
\r
12066 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
\r
12067 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
\r
12068 #define GPIO_AFRL_AFSEL2_Pos (8U)
\r
12069 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
\r
12070 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
\r
12071 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
\r
12072 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
\r
12073 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
\r
12074 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
\r
12075 #define GPIO_AFRL_AFSEL3_Pos (12U)
\r
12076 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
\r
12077 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
\r
12078 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
\r
12079 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
\r
12080 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
\r
12081 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
\r
12082 #define GPIO_AFRL_AFSEL4_Pos (16U)
\r
12083 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
\r
12084 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
\r
12085 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
\r
12086 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
\r
12087 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
\r
12088 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
\r
12089 #define GPIO_AFRL_AFSEL5_Pos (20U)
\r
12090 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
\r
12091 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
\r
12092 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
\r
12093 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
\r
12094 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
\r
12095 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
\r
12096 #define GPIO_AFRL_AFSEL6_Pos (24U)
\r
12097 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
\r
12098 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
\r
12099 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
\r
12100 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
\r
12101 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
\r
12102 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
\r
12103 #define GPIO_AFRL_AFSEL7_Pos (28U)
\r
12104 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
\r
12105 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
\r
12106 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
\r
12107 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
\r
12108 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
\r
12109 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
\r
12111 /* Legacy defines */
\r
12112 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
\r
12113 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
\r
12114 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
\r
12115 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
\r
12116 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
\r
12117 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
\r
12118 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
\r
12119 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
\r
12121 /****************** Bit definition for GPIO_AFRH register ********************/
\r
12122 #define GPIO_AFRH_AFSEL8_Pos (0U)
\r
12123 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
\r
12124 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
\r
12125 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
\r
12126 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
\r
12127 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
\r
12128 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
\r
12129 #define GPIO_AFRH_AFSEL9_Pos (4U)
\r
12130 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
\r
12131 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
\r
12132 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
\r
12133 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
\r
12134 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
\r
12135 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
\r
12136 #define GPIO_AFRH_AFSEL10_Pos (8U)
\r
12137 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
\r
12138 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
\r
12139 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
\r
12140 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
\r
12141 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
\r
12142 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
\r
12143 #define GPIO_AFRH_AFSEL11_Pos (12U)
\r
12144 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
\r
12145 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
\r
12146 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
\r
12147 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
\r
12148 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
\r
12149 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
\r
12150 #define GPIO_AFRH_AFSEL12_Pos (16U)
\r
12151 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
\r
12152 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
\r
12153 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
\r
12154 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
\r
12155 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
\r
12156 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
\r
12157 #define GPIO_AFRH_AFSEL13_Pos (20U)
\r
12158 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
\r
12159 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
\r
12160 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
\r
12161 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
\r
12162 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
\r
12163 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
\r
12164 #define GPIO_AFRH_AFSEL14_Pos (24U)
\r
12165 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
\r
12166 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
\r
12167 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
\r
12168 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
\r
12169 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
\r
12170 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
\r
12171 #define GPIO_AFRH_AFSEL15_Pos (28U)
\r
12172 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
\r
12173 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
\r
12174 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
\r
12175 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
\r
12176 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
\r
12177 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
\r
12179 /* Legacy defines */
\r
12180 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
\r
12181 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
\r
12182 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
\r
12183 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
\r
12184 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
\r
12185 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
\r
12186 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
\r
12187 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
\r
12189 /******************************************************************************/
\r
12191 /* HSEM HW Semaphore */
\r
12193 /******************************************************************************/
\r
12194 /******************** Bit definition for HSEM_R register ********************/
\r
12195 #define HSEM_R_PROCID_Pos (0U)
\r
12196 #define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
\r
12197 #define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
\r
12198 #define HSEM_R_COREID_Pos (8U)
\r
12199 #define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) /*!< 0x0000FF00 */
\r
12200 #define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */
\r
12201 #define HSEM_R_LOCK_Pos (31U)
\r
12202 #define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
\r
12203 #define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
\r
12205 /******************** Bit definition for HSEM_RLR register ******************/
\r
12206 #define HSEM_RLR_PROCID_Pos (0U)
\r
12207 #define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
\r
12208 #define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
\r
12209 #define HSEM_RLR_COREID_Pos (8U)
\r
12210 #define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) /*!< 0x0000FF00 */
\r
12211 #define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */
\r
12212 #define HSEM_RLR_LOCK_Pos (31U)
\r
12213 #define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
\r
12214 #define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
\r
12216 /******************** Bit definition for HSEM_C1IER register *****************/
\r
12217 #define HSEM_C1IER_ISE0_Pos (0U)
\r
12218 #define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */
\r
12219 #define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */
\r
12220 #define HSEM_C1IER_ISE1_Pos (1U)
\r
12221 #define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */
\r
12222 #define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */
\r
12223 #define HSEM_C1IER_ISE2_Pos (2U)
\r
12224 #define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */
\r
12225 #define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */
\r
12226 #define HSEM_C1IER_ISE3_Pos (3U)
\r
12227 #define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */
\r
12228 #define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */
\r
12229 #define HSEM_C1IER_ISE4_Pos (4U)
\r
12230 #define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */
\r
12231 #define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */
\r
12232 #define HSEM_C1IER_ISE5_Pos (5U)
\r
12233 #define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */
\r
12234 #define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 interrupt 0 enable bit. */
\r
12235 #define HSEM_C1IER_ISE6_Pos (6U)
\r
12236 #define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */
\r
12237 #define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 interrupt 0 enable bit. */
\r
12238 #define HSEM_C1IER_ISE7_Pos (7U)
\r
12239 #define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */
\r
12240 #define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 interrupt 0 enable bit. */
\r
12241 #define HSEM_C1IER_ISE8_Pos (8U)
\r
12242 #define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */
\r
12243 #define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 interrupt 0 enable bit. */
\r
12244 #define HSEM_C1IER_ISE9_Pos (9U)
\r
12245 #define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */
\r
12246 #define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 interrupt 0 enable bit. */
\r
12247 #define HSEM_C1IER_ISE10_Pos (10U)
\r
12248 #define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */
\r
12249 #define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 interrupt 0 enable bit. */
\r
12250 #define HSEM_C1IER_ISE11_Pos (11U)
\r
12251 #define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */
\r
12252 #define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 interrupt 0 enable bit. */
\r
12253 #define HSEM_C1IER_ISE12_Pos (12U)
\r
12254 #define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */
\r
12255 #define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 interrupt 0 enable bit. */
\r
12256 #define HSEM_C1IER_ISE13_Pos (13U)
\r
12257 #define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */
\r
12258 #define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 interrupt 0 enable bit. */
\r
12259 #define HSEM_C1IER_ISE14_Pos (14U)
\r
12260 #define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */
\r
12261 #define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 interrupt 0 enable bit. */
\r
12262 #define HSEM_C1IER_ISE15_Pos (15U)
\r
12263 #define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */
\r
12264 #define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 interrupt 0 enable bit. */
\r
12265 #define HSEM_C1IER_ISE16_Pos (16U)
\r
12266 #define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */
\r
12267 #define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 interrupt 0 enable bit. */
\r
12268 #define HSEM_C1IER_ISE17_Pos (17U)
\r
12269 #define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */
\r
12270 #define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 interrupt 0 enable bit. */
\r
12271 #define HSEM_C1IER_ISE18_Pos (18U)
\r
12272 #define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */
\r
12273 #define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 interrupt 0 enable bit. */
\r
12274 #define HSEM_C1IER_ISE19_Pos (19U)
\r
12275 #define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */
\r
12276 #define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 interrupt 0 enable bit. */
\r
12277 #define HSEM_C1IER_ISE20_Pos (20U)
\r
12278 #define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */
\r
12279 #define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 interrupt 0 enable bit. */
\r
12280 #define HSEM_C1IER_ISE21_Pos (21U)
\r
12281 #define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */
\r
12282 #define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 interrupt 0 enable bit. */
\r
12283 #define HSEM_C1IER_ISE22_Pos (22U)
\r
12284 #define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */
\r
12285 #define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 interrupt 0 enable bit. */
\r
12286 #define HSEM_C1IER_ISE23_Pos (23U)
\r
12287 #define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */
\r
12288 #define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 interrupt 0 enable bit. */
\r
12289 #define HSEM_C1IER_ISE24_Pos (24U)
\r
12290 #define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */
\r
12291 #define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 interrupt 0 enable bit. */
\r
12292 #define HSEM_C1IER_ISE25_Pos (25U)
\r
12293 #define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */
\r
12294 #define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 interrupt 0 enable bit. */
\r
12295 #define HSEM_C1IER_ISE26_Pos (26U)
\r
12296 #define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */
\r
12297 #define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 interrupt 0 enable bit. */
\r
12298 #define HSEM_C1IER_ISE27_Pos (27U)
\r
12299 #define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */
\r
12300 #define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 interrupt 0 enable bit. */
\r
12301 #define HSEM_C1IER_ISE28_Pos (28U)
\r
12302 #define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */
\r
12303 #define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 interrupt 0 enable bit. */
\r
12304 #define HSEM_C1IER_ISE29_Pos (29U)
\r
12305 #define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */
\r
12306 #define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 interrupt 0 enable bit. */
\r
12307 #define HSEM_C1IER_ISE30_Pos (30U)
\r
12308 #define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */
\r
12309 #define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 interrupt 0 enable bit. */
\r
12310 #define HSEM_C1IER_ISE31_Pos (31U)
\r
12311 #define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */
\r
12312 #define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 interrupt 0 enable bit. */
\r
12314 /******************** Bit definition for HSEM_C1ICR register *****************/
\r
12315 #define HSEM_C1ICR_ISC0_Pos (0U)
\r
12316 #define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */
\r
12317 #define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */
\r
12318 #define HSEM_C1ICR_ISC1_Pos (1U)
\r
12319 #define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */
\r
12320 #define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */
\r
12321 #define HSEM_C1ICR_ISC2_Pos (2U)
\r
12322 #define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */
\r
12323 #define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */
\r
12324 #define HSEM_C1ICR_ISC3_Pos (3U)
\r
12325 #define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */
\r
12326 #define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */
\r
12327 #define HSEM_C1ICR_ISC4_Pos (4U)
\r
12328 #define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */
\r
12329 #define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */
\r
12330 #define HSEM_C1ICR_ISC5_Pos (5U)
\r
12331 #define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */
\r
12332 #define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 interrupt 0 clear bit. */
\r
12333 #define HSEM_C1ICR_ISC6_Pos (6U)
\r
12334 #define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */
\r
12335 #define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 interrupt 0 clear bit. */
\r
12336 #define HSEM_C1ICR_ISC7_Pos (7U)
\r
12337 #define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */
\r
12338 #define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 interrupt 0 clear bit. */
\r
12339 #define HSEM_C1ICR_ISC8_Pos (8U)
\r
12340 #define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */
\r
12341 #define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 interrupt 0 clear bit. */
\r
12342 #define HSEM_C1ICR_ISC9_Pos (9U)
\r
12343 #define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */
\r
12344 #define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 interrupt 0 clear bit. */
\r
12345 #define HSEM_C1ICR_ISC10_Pos (10U)
\r
12346 #define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */
\r
12347 #define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 interrupt 0 clear bit. */
\r
12348 #define HSEM_C1ICR_ISC11_Pos (11U)
\r
12349 #define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */
\r
12350 #define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 interrupt 0 clear bit. */
\r
12351 #define HSEM_C1ICR_ISC12_Pos (12U)
\r
12352 #define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */
\r
12353 #define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 interrupt 0 clear bit. */
\r
12354 #define HSEM_C1ICR_ISC13_Pos (13U)
\r
12355 #define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */
\r
12356 #define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 interrupt 0 clear bit. */
\r
12357 #define HSEM_C1ICR_ISC14_Pos (14U)
\r
12358 #define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */
\r
12359 #define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 interrupt 0 clear bit. */
\r
12360 #define HSEM_C1ICR_ISC15_Pos (15U)
\r
12361 #define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */
\r
12362 #define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 interrupt 0 clear bit. */
\r
12363 #define HSEM_C1ICR_ISC16_Pos (16U)
\r
12364 #define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */
\r
12365 #define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 interrupt 0 clear bit. */
\r
12366 #define HSEM_C1ICR_ISC17_Pos (17U)
\r
12367 #define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */
\r
12368 #define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 interrupt 0 clear bit. */
\r
12369 #define HSEM_C1ICR_ISC18_Pos (18U)
\r
12370 #define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */
\r
12371 #define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 interrupt 0 clear bit. */
\r
12372 #define HSEM_C1ICR_ISC19_Pos (19U)
\r
12373 #define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */
\r
12374 #define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 interrupt 0 clear bit. */
\r
12375 #define HSEM_C1ICR_ISC20_Pos (20U)
\r
12376 #define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */
\r
12377 #define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 interrupt 0 clear bit. */
\r
12378 #define HSEM_C1ICR_ISC21_Pos (21U)
\r
12379 #define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */
\r
12380 #define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 interrupt 0 clear bit. */
\r
12381 #define HSEM_C1ICR_ISC22_Pos (22U)
\r
12382 #define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */
\r
12383 #define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 interrupt 0 clear bit. */
\r
12384 #define HSEM_C1ICR_ISC23_Pos (23U)
\r
12385 #define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */
\r
12386 #define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 interrupt 0 clear bit. */
\r
12387 #define HSEM_C1ICR_ISC24_Pos (24U)
\r
12388 #define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */
\r
12389 #define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 interrupt 0 clear bit. */
\r
12390 #define HSEM_C1ICR_ISC25_Pos (25U)
\r
12391 #define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */
\r
12392 #define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 interrupt 0 clear bit. */
\r
12393 #define HSEM_C1ICR_ISC26_Pos (26U)
\r
12394 #define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */
\r
12395 #define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 interrupt 0 clear bit. */
\r
12396 #define HSEM_C1ICR_ISC27_Pos (27U)
\r
12397 #define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */
\r
12398 #define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 interrupt 0 clear bit. */
\r
12399 #define HSEM_C1ICR_ISC28_Pos (28U)
\r
12400 #define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */
\r
12401 #define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 interrupt 0 clear bit. */
\r
12402 #define HSEM_C1ICR_ISC29_Pos (29U)
\r
12403 #define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */
\r
12404 #define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 interrupt 0 clear bit. */
\r
12405 #define HSEM_C1ICR_ISC30_Pos (30U)
\r
12406 #define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */
\r
12407 #define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 interrupt 0 clear bit. */
\r
12408 #define HSEM_C1ICR_ISC31_Pos (31U)
\r
12409 #define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */
\r
12410 #define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 interrupt 0 clear bit. */
\r
12412 /******************** Bit definition for HSEM_C1ISR register *****************/
\r
12413 #define HSEM_C1ISR_ISF0_Pos (0U)
\r
12414 #define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */
\r
12415 #define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 interrupt 0 status bit. */
\r
12416 #define HSEM_C1ISR_ISF1_Pos (1U)
\r
12417 #define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */
\r
12418 #define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 interrupt 0 status bit. */
\r
12419 #define HSEM_C1ISR_ISF2_Pos (2U)
\r
12420 #define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */
\r
12421 #define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 interrupt 0 status bit. */
\r
12422 #define HSEM_C1ISR_ISF3_Pos (3U)
\r
12423 #define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */
\r
12424 #define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 interrupt 0 status bit. */
\r
12425 #define HSEM_C1ISR_ISF4_Pos (4U)
\r
12426 #define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */
\r
12427 #define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 interrupt 0 status bit. */
\r
12428 #define HSEM_C1ISR_ISF5_Pos (5U)
\r
12429 #define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */
\r
12430 #define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 interrupt 0 status bit. */
\r
12431 #define HSEM_C1ISR_ISF6_Pos (6U)
\r
12432 #define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */
\r
12433 #define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 interrupt 0 status bit. */
\r
12434 #define HSEM_C1ISR_ISF7_Pos (7U)
\r
12435 #define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */
\r
12436 #define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 interrupt 0 status bit. */
\r
12437 #define HSEM_C1ISR_ISF8_Pos (8U)
\r
12438 #define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */
\r
12439 #define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 interrupt 0 status bit. */
\r
12440 #define HSEM_C1ISR_ISF9_Pos (9U)
\r
12441 #define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */
\r
12442 #define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 interrupt 0 status bit. */
\r
12443 #define HSEM_C1ISR_ISF10_Pos (10U)
\r
12444 #define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */
\r
12445 #define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 interrupt 0 status bit. */
\r
12446 #define HSEM_C1ISR_ISF11_Pos (11U)
\r
12447 #define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */
\r
12448 #define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 interrupt 0 status bit. */
\r
12449 #define HSEM_C1ISR_ISF12_Pos (12U)
\r
12450 #define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */
\r
12451 #define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 interrupt 0 status bit. */
\r
12452 #define HSEM_C1ISR_ISF13_Pos (13U)
\r
12453 #define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */
\r
12454 #define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 interrupt 0 status bit. */
\r
12455 #define HSEM_C1ISR_ISF14_Pos (14U)
\r
12456 #define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */
\r
12457 #define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 interrupt 0 status bit. */
\r
12458 #define HSEM_C1ISR_ISF15_Pos (15U)
\r
12459 #define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */
\r
12460 #define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 interrupt 0 status bit. */
\r
12461 #define HSEM_C1ISR_ISF16_Pos (16U)
\r
12462 #define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */
\r
12463 #define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 interrupt 0 status bit. */
\r
12464 #define HSEM_C1ISR_ISF17_Pos (17U)
\r
12465 #define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */
\r
12466 #define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 interrupt 0 status bit. */
\r
12467 #define HSEM_C1ISR_ISF18_Pos (18U)
\r
12468 #define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */
\r
12469 #define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 interrupt 0 status bit. */
\r
12470 #define HSEM_C1ISR_ISF19_Pos (19U)
\r
12471 #define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */
\r
12472 #define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 interrupt 0 status bit. */
\r
12473 #define HSEM_C1ISR_ISF20_Pos (20U)
\r
12474 #define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */
\r
12475 #define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 interrupt 0 status bit. */
\r
12476 #define HSEM_C1ISR_ISF21_Pos (21U)
\r
12477 #define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */
\r
12478 #define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 interrupt 0 status bit. */
\r
12479 #define HSEM_C1ISR_ISF22_Pos (22U)
\r
12480 #define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */
\r
12481 #define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 interrupt 0 status bit. */
\r
12482 #define HSEM_C1ISR_ISF23_Pos (23U)
\r
12483 #define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */
\r
12484 #define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 interrupt 0 status bit. */
\r
12485 #define HSEM_C1ISR_ISF24_Pos (24U)
\r
12486 #define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */
\r
12487 #define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 interrupt 0 status bit. */
\r
12488 #define HSEM_C1ISR_ISF25_Pos (25U)
\r
12489 #define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */
\r
12490 #define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 interrupt 0 status bit. */
\r
12491 #define HSEM_C1ISR_ISF26_Pos (26U)
\r
12492 #define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */
\r
12493 #define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 interrupt 0 status bit. */
\r
12494 #define HSEM_C1ISR_ISF27_Pos (27U)
\r
12495 #define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */
\r
12496 #define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 interrupt 0 status bit. */
\r
12497 #define HSEM_C1ISR_ISF28_Pos (28U)
\r
12498 #define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */
\r
12499 #define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 interrupt 0 status bit. */
\r
12500 #define HSEM_C1ISR_ISF29_Pos (29U)
\r
12501 #define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */
\r
12502 #define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 interrupt 0 status bit. */
\r
12503 #define HSEM_C1ISR_ISF30_Pos (30U)
\r
12504 #define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */
\r
12505 #define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 interrupt 0 status bit. */
\r
12506 #define HSEM_C1ISR_ISF31_Pos (31U)
\r
12507 #define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */
\r
12508 #define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 interrupt 0 status bit. */
\r
12510 /******************** Bit definition for HSEM_C1MISR register *****************/
\r
12511 #define HSEM_C1MISR_MISF0_Pos (0U)
\r
12512 #define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */
\r
12513 #define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */
\r
12514 #define HSEM_C1MISR_MISF1_Pos (1U)
\r
12515 #define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */
\r
12516 #define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */
\r
12517 #define HSEM_C1MISR_MISF2_Pos (2U)
\r
12518 #define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */
\r
12519 #define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */
\r
12520 #define HSEM_C1MISR_MISF3_Pos (3U)
\r
12521 #define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */
\r
12522 #define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */
\r
12523 #define HSEM_C1MISR_MISF4_Pos (4U)
\r
12524 #define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */
\r
12525 #define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */
\r
12526 #define HSEM_C1MISR_MISF5_Pos (5U)
\r
12527 #define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */
\r
12528 #define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */
\r
12529 #define HSEM_C1MISR_MISF6_Pos (6U)
\r
12530 #define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */
\r
12531 #define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */
\r
12532 #define HSEM_C1MISR_MISF7_Pos (7U)
\r
12533 #define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */
\r
12534 #define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */
\r
12535 #define HSEM_C1MISR_MISF8_Pos (8U)
\r
12536 #define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */
\r
12537 #define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */
\r
12538 #define HSEM_C1MISR_MISF9_Pos (9U)
\r
12539 #define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */
\r
12540 #define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */
\r
12541 #define HSEM_C1MISR_MISF10_Pos (10U)
\r
12542 #define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */
\r
12543 #define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */
\r
12544 #define HSEM_C1MISR_MISF11_Pos (11U)
\r
12545 #define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */
\r
12546 #define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */
\r
12547 #define HSEM_C1MISR_MISF12_Pos (12U)
\r
12548 #define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */
\r
12549 #define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */
\r
12550 #define HSEM_C1MISR_MISF13_Pos (13U)
\r
12551 #define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */
\r
12552 #define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */
\r
12553 #define HSEM_C1MISR_MISF14_Pos (14U)
\r
12554 #define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */
\r
12555 #define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */
\r
12556 #define HSEM_C1MISR_MISF15_Pos (15U)
\r
12557 #define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */
\r
12558 #define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */
\r
12559 #define HSEM_C1MISR_MISF16_Pos (16U)
\r
12560 #define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */
\r
12561 #define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */
\r
12562 #define HSEM_C1MISR_MISF17_Pos (17U)
\r
12563 #define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */
\r
12564 #define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */
\r
12565 #define HSEM_C1MISR_MISF18_Pos (18U)
\r
12566 #define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */
\r
12567 #define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */
\r
12568 #define HSEM_C1MISR_MISF19_Pos (19U)
\r
12569 #define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */
\r
12570 #define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */
\r
12571 #define HSEM_C1MISR_MISF20_Pos (20U)
\r
12572 #define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */
\r
12573 #define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */
\r
12574 #define HSEM_C1MISR_MISF21_Pos (21U)
\r
12575 #define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */
\r
12576 #define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */
\r
12577 #define HSEM_C1MISR_MISF22_Pos (22U)
\r
12578 #define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */
\r
12579 #define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */
\r
12580 #define HSEM_C1MISR_MISF23_Pos (23U)
\r
12581 #define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */
\r
12582 #define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */
\r
12583 #define HSEM_C1MISR_MISF24_Pos (24U)
\r
12584 #define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */
\r
12585 #define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */
\r
12586 #define HSEM_C1MISR_MISF25_Pos (25U)
\r
12587 #define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */
\r
12588 #define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */
\r
12589 #define HSEM_C1MISR_MISF26_Pos (26U)
\r
12590 #define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */
\r
12591 #define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */
\r
12592 #define HSEM_C1MISR_MISF27_Pos (27U)
\r
12593 #define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */
\r
12594 #define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */
\r
12595 #define HSEM_C1MISR_MISF28_Pos (28U)
\r
12596 #define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */
\r
12597 #define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */
\r
12598 #define HSEM_C1MISR_MISF29_Pos (29U)
\r
12599 #define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */
\r
12600 #define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */
\r
12601 #define HSEM_C1MISR_MISF30_Pos (30U)
\r
12602 #define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */
\r
12603 #define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */
\r
12604 #define HSEM_C1MISR_MISF31_Pos (31U)
\r
12605 #define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */
\r
12606 #define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */
\r
12608 /******************** Bit definition for HSEM_C2IER register *****************/
\r
12609 #define HSEM_C2IER_ISE0_Pos (0U)
\r
12610 #define HSEM_C2IER_ISE0_Msk (0x1UL << HSEM_C2IER_ISE0_Pos) /*!< 0x00000001 */
\r
12611 #define HSEM_C2IER_ISE0 HSEM_C2IER_ISE0_Msk /*!<semaphore 0 , interrupt 1 enable bit. */
\r
12612 #define HSEM_C2IER_ISE1_Pos (1U)
\r
12613 #define HSEM_C2IER_ISE1_Msk (0x1UL << HSEM_C2IER_ISE1_Pos) /*!< 0x00000002 */
\r
12614 #define HSEM_C2IER_ISE1 HSEM_C2IER_ISE1_Msk /*!<semaphore 1 , interrupt 1 enable bit. */
\r
12615 #define HSEM_C2IER_ISE2_Pos (2U)
\r
12616 #define HSEM_C2IER_ISE2_Msk (0x1UL << HSEM_C2IER_ISE2_Pos) /*!< 0x00000004 */
\r
12617 #define HSEM_C2IER_ISE2 HSEM_C2IER_ISE2_Msk /*!<semaphore 2 , interrupt 1 enable bit. */
\r
12618 #define HSEM_C2IER_ISE3_Pos (3U)
\r
12619 #define HSEM_C2IER_ISE3_Msk (0x1UL << HSEM_C2IER_ISE3_Pos) /*!< 0x00000008 */
\r
12620 #define HSEM_C2IER_ISE3 HSEM_C2IER_ISE3_Msk /*!<semaphore 3 , interrupt 1 enable bit. */
\r
12621 #define HSEM_C2IER_ISE4_Pos (4U)
\r
12622 #define HSEM_C2IER_ISE4_Msk (0x1UL << HSEM_C2IER_ISE4_Pos) /*!< 0x00000010 */
\r
12623 #define HSEM_C2IER_ISE4 HSEM_C2IER_ISE4_Msk /*!<semaphore 4 , interrupt 1 enable bit. */
\r
12624 #define HSEM_C2IER_ISE5_Pos (5U)
\r
12625 #define HSEM_C2IER_ISE5_Msk (0x1UL << HSEM_C2IER_ISE5_Pos) /*!< 0x00000020 */
\r
12626 #define HSEM_C2IER_ISE5 HSEM_C2IER_ISE5_Msk /*!<semaphore 5 interrupt 1 enable bit. */
\r
12627 #define HSEM_C2IER_ISE6_Pos (6U)
\r
12628 #define HSEM_C2IER_ISE6_Msk (0x1UL << HSEM_C2IER_ISE6_Pos) /*!< 0x00000040 */
\r
12629 #define HSEM_C2IER_ISE6 HSEM_C2IER_ISE6_Msk /*!<semaphore 6 interrupt 1 enable bit. */
\r
12630 #define HSEM_C2IER_ISE7_Pos (7U)
\r
12631 #define HSEM_C2IER_ISE7_Msk (0x1UL << HSEM_C2IER_ISE7_Pos) /*!< 0x00000080 */
\r
12632 #define HSEM_C2IER_ISE7 HSEM_C2IER_ISE7_Msk /*!<semaphore 7 interrupt 1 enable bit. */
\r
12633 #define HSEM_C2IER_ISE8_Pos (8U)
\r
12634 #define HSEM_C2IER_ISE8_Msk (0x1UL << HSEM_C2IER_ISE8_Pos) /*!< 0x00000100 */
\r
12635 #define HSEM_C2IER_ISE8 HSEM_C2IER_ISE8_Msk /*!<semaphore 8 interrupt 1 enable bit. */
\r
12636 #define HSEM_C2IER_ISE9_Pos (9U)
\r
12637 #define HSEM_C2IER_ISE9_Msk (0x1UL << HSEM_C2IER_ISE9_Pos) /*!< 0x00000200 */
\r
12638 #define HSEM_C2IER_ISE9 HSEM_C2IER_ISE9_Msk /*!<semaphore 9 interrupt 1 enable bit. */
\r
12639 #define HSEM_C2IER_ISE10_Pos (10U)
\r
12640 #define HSEM_C2IER_ISE10_Msk (0x1UL << HSEM_C2IER_ISE10_Pos) /*!< 0x00000400 */
\r
12641 #define HSEM_C2IER_ISE10 HSEM_C2IER_ISE10_Msk /*!<semaphore 10 interrupt 1 enable bit. */
\r
12642 #define HSEM_C2IER_ISE11_Pos (11U)
\r
12643 #define HSEM_C2IER_ISE11_Msk (0x1UL << HSEM_C2IER_ISE11_Pos) /*!< 0x00000800 */
\r
12644 #define HSEM_C2IER_ISE11 HSEM_C2IER_ISE11_Msk /*!<semaphore 11 interrupt 1 enable bit. */
\r
12645 #define HSEM_C2IER_ISE12_Pos (12U)
\r
12646 #define HSEM_C2IER_ISE12_Msk (0x1UL << HSEM_C2IER_ISE12_Pos) /*!< 0x00001000 */
\r
12647 #define HSEM_C2IER_ISE12 HSEM_C2IER_ISE12_Msk /*!<semaphore 12 interrupt 1 enable bit. */
\r
12648 #define HSEM_C2IER_ISE13_Pos (13U)
\r
12649 #define HSEM_C2IER_ISE13_Msk (0x1UL << HSEM_C2IER_ISE13_Pos) /*!< 0x00002000 */
\r
12650 #define HSEM_C2IER_ISE13 HSEM_C2IER_ISE13_Msk /*!<semaphore 13 interrupt 1 enable bit. */
\r
12651 #define HSEM_C2IER_ISE14_Pos (14U)
\r
12652 #define HSEM_C2IER_ISE14_Msk (0x1UL << HSEM_C2IER_ISE14_Pos) /*!< 0x00004000 */
\r
12653 #define HSEM_C2IER_ISE14 HSEM_C2IER_ISE14_Msk /*!<semaphore 14 interrupt 1 enable bit. */
\r
12654 #define HSEM_C2IER_ISE15_Pos (15U)
\r
12655 #define HSEM_C2IER_ISE15_Msk (0x1UL << HSEM_C2IER_ISE15_Pos) /*!< 0x00008000 */
\r
12656 #define HSEM_C2IER_ISE15 HSEM_C2IER_ISE15_Msk /*!<semaphore 15 interrupt 1 enable bit. */
\r
12657 #define HSEM_C2IER_ISE16_Pos (16U)
\r
12658 #define HSEM_C2IER_ISE16_Msk (0x1UL << HSEM_C2IER_ISE16_Pos) /*!< 0x00010000 */
\r
12659 #define HSEM_C2IER_ISE16 HSEM_C2IER_ISE16_Msk /*!<semaphore 16 interrupt 1 enable bit. */
\r
12660 #define HSEM_C2IER_ISE17_Pos (17U)
\r
12661 #define HSEM_C2IER_ISE17_Msk (0x1UL << HSEM_C2IER_ISE17_Pos) /*!< 0x00020000 */
\r
12662 #define HSEM_C2IER_ISE17 HSEM_C2IER_ISE17_Msk /*!<semaphore 17 interrupt 1 enable bit. */
\r
12663 #define HSEM_C2IER_ISE18_Pos (18U)
\r
12664 #define HSEM_C2IER_ISE18_Msk (0x1UL << HSEM_C2IER_ISE18_Pos) /*!< 0x00040000 */
\r
12665 #define HSEM_C2IER_ISE18 HSEM_C2IER_ISE18_Msk /*!<semaphore 18 interrupt 1 enable bit. */
\r
12666 #define HSEM_C2IER_ISE19_Pos (19U)
\r
12667 #define HSEM_C2IER_ISE19_Msk (0x1UL << HSEM_C2IER_ISE19_Pos) /*!< 0x00080000 */
\r
12668 #define HSEM_C2IER_ISE19 HSEM_C2IER_ISE19_Msk /*!<semaphore 19 interrupt 1 enable bit. */
\r
12669 #define HSEM_C2IER_ISE20_Pos (20U)
\r
12670 #define HSEM_C2IER_ISE20_Msk (0x1UL << HSEM_C2IER_ISE20_Pos) /*!< 0x00100000 */
\r
12671 #define HSEM_C2IER_ISE20 HSEM_C2IER_ISE20_Msk /*!<semaphore 20 interrupt 1 enable bit. */
\r
12672 #define HSEM_C2IER_ISE21_Pos (21U)
\r
12673 #define HSEM_C2IER_ISE21_Msk (0x1UL << HSEM_C2IER_ISE21_Pos) /*!< 0x00200000 */
\r
12674 #define HSEM_C2IER_ISE21 HSEM_C2IER_ISE21_Msk /*!<semaphore 21 interrupt 1 enable bit. */
\r
12675 #define HSEM_C2IER_ISE22_Pos (22U)
\r
12676 #define HSEM_C2IER_ISE22_Msk (0x1UL << HSEM_C2IER_ISE22_Pos) /*!< 0x00400000 */
\r
12677 #define HSEM_C2IER_ISE22 HSEM_C2IER_ISE22_Msk /*!<semaphore 22 interrupt 1 enable bit. */
\r
12678 #define HSEM_C2IER_ISE23_Pos (23U)
\r
12679 #define HSEM_C2IER_ISE23_Msk (0x1UL << HSEM_C2IER_ISE23_Pos) /*!< 0x00800000 */
\r
12680 #define HSEM_C2IER_ISE23 HSEM_C2IER_ISE23_Msk /*!<semaphore 23 interrupt 1 enable bit. */
\r
12681 #define HSEM_C2IER_ISE24_Pos (24U)
\r
12682 #define HSEM_C2IER_ISE24_Msk (0x1UL << HSEM_C2IER_ISE24_Pos) /*!< 0x01000000 */
\r
12683 #define HSEM_C2IER_ISE24 HSEM_C2IER_ISE24_Msk /*!<semaphore 24 interrupt 1 enable bit. */
\r
12684 #define HSEM_C2IER_ISE25_Pos (25U)
\r
12685 #define HSEM_C2IER_ISE25_Msk (0x1UL << HSEM_C2IER_ISE25_Pos) /*!< 0x02000000 */
\r
12686 #define HSEM_C2IER_ISE25 HSEM_C2IER_ISE25_Msk /*!<semaphore 25 interrupt 1 enable bit. */
\r
12687 #define HSEM_C2IER_ISE26_Pos (26U)
\r
12688 #define HSEM_C2IER_ISE26_Msk (0x1UL << HSEM_C2IER_ISE26_Pos) /*!< 0x04000000 */
\r
12689 #define HSEM_C2IER_ISE26 HSEM_C2IER_ISE26_Msk /*!<semaphore 26 interrupt 1 enable bit. */
\r
12690 #define HSEM_C2IER_ISE27_Pos (27U)
\r
12691 #define HSEM_C2IER_ISE27_Msk (0x1UL << HSEM_C2IER_ISE27_Pos) /*!< 0x08000000 */
\r
12692 #define HSEM_C2IER_ISE27 HSEM_C2IER_ISE27_Msk /*!<semaphore 27 interrupt 1 enable bit. */
\r
12693 #define HSEM_C2IER_ISE28_Pos (28U)
\r
12694 #define HSEM_C2IER_ISE28_Msk (0x1UL << HSEM_C2IER_ISE28_Pos) /*!< 0x10000000 */
\r
12695 #define HSEM_C2IER_ISE28 HSEM_C2IER_ISE28_Msk /*!<semaphore 28 interrupt 1 enable bit. */
\r
12696 #define HSEM_C2IER_ISE29_Pos (29U)
\r
12697 #define HSEM_C2IER_ISE29_Msk (0x1UL << HSEM_C2IER_ISE29_Pos) /*!< 0x20000000 */
\r
12698 #define HSEM_C2IER_ISE29 HSEM_C2IER_ISE29_Msk /*!<semaphore 29 interrupt 1 enable bit. */
\r
12699 #define HSEM_C2IER_ISE30_Pos (30U)
\r
12700 #define HSEM_C2IER_ISE30_Msk (0x1UL << HSEM_C2IER_ISE30_Pos) /*!< 0x40000000 */
\r
12701 #define HSEM_C2IER_ISE30 HSEM_C2IER_ISE30_Msk /*!<semaphore 30 interrupt 1 enable bit. */
\r
12702 #define HSEM_C2IER_ISE31_Pos (31U)
\r
12703 #define HSEM_C2IER_ISE31_Msk (0x1UL << HSEM_C2IER_ISE31_Pos) /*!< 0x80000000 */
\r
12704 #define HSEM_C2IER_ISE31 HSEM_C2IER_ISE31_Msk /*!<semaphore 31 interrupt 1 enable bit. */
\r
12706 /******************** Bit definition for HSEM_C2ICR register *****************/
\r
12707 #define HSEM_C2ICR_ISC0_Pos (0U)
\r
12708 #define HSEM_C2ICR_ISC0_Msk (0x1UL << HSEM_C2ICR_ISC0_Pos) /*!< 0x00000001 */
\r
12709 #define HSEM_C2ICR_ISC0 HSEM_C2ICR_ISC0_Msk /*!<semaphore 0 , interrupt 1 clear bit. */
\r
12710 #define HSEM_C2ICR_ISC1_Pos (1U)
\r
12711 #define HSEM_C2ICR_ISC1_Msk (0x1UL << HSEM_C2ICR_ISC1_Pos) /*!< 0x00000002 */
\r
12712 #define HSEM_C2ICR_ISC1 HSEM_C2ICR_ISC1_Msk /*!<semaphore 1 , interrupt 1 clear bit. */
\r
12713 #define HSEM_C2ICR_ISC2_Pos (2U)
\r
12714 #define HSEM_C2ICR_ISC2_Msk (0x1UL << HSEM_C2ICR_ISC2_Pos) /*!< 0x00000004 */
\r
12715 #define HSEM_C2ICR_ISC2 HSEM_C2ICR_ISC2_Msk /*!<semaphore 2 , interrupt 1 clear bit. */
\r
12716 #define HSEM_C2ICR_ISC3_Pos (3U)
\r
12717 #define HSEM_C2ICR_ISC3_Msk (0x1UL << HSEM_C2ICR_ISC3_Pos) /*!< 0x00000008 */
\r
12718 #define HSEM_C2ICR_ISC3 HSEM_C2ICR_ISC3_Msk /*!<semaphore 3 , interrupt 1 clear bit. */
\r
12719 #define HSEM_C2ICR_ISC4_Pos (4U)
\r
12720 #define HSEM_C2ICR_ISC4_Msk (0x1UL << HSEM_C2ICR_ISC4_Pos) /*!< 0x00000010 */
\r
12721 #define HSEM_C2ICR_ISC4 HSEM_C2ICR_ISC4_Msk /*!<semaphore 4 , interrupt 1 clear bit. */
\r
12722 #define HSEM_C2ICR_ISC5_Pos (5U)
\r
12723 #define HSEM_C2ICR_ISC5_Msk (0x1UL << HSEM_C2ICR_ISC5_Pos) /*!< 0x00000020 */
\r
12724 #define HSEM_C2ICR_ISC5 HSEM_C2ICR_ISC5_Msk /*!<semaphore 5 interrupt 1 clear bit. */
\r
12725 #define HSEM_C2ICR_ISC6_Pos (6U)
\r
12726 #define HSEM_C2ICR_ISC6_Msk (0x1UL << HSEM_C2ICR_ISC6_Pos) /*!< 0x00000040 */
\r
12727 #define HSEM_C2ICR_ISC6 HSEM_C2ICR_ISC6_Msk /*!<semaphore 6 interrupt 1 clear bit. */
\r
12728 #define HSEM_C2ICR_ISC7_Pos (7U)
\r
12729 #define HSEM_C2ICR_ISC7_Msk (0x1UL << HSEM_C2ICR_ISC7_Pos) /*!< 0x00000080 */
\r
12730 #define HSEM_C2ICR_ISC7 HSEM_C2ICR_ISC7_Msk /*!<semaphore 7 interrupt 1 clear bit. */
\r
12731 #define HSEM_C2ICR_ISC8_Pos (8U)
\r
12732 #define HSEM_C2ICR_ISC8_Msk (0x1UL << HSEM_C2ICR_ISC8_Pos) /*!< 0x00000100 */
\r
12733 #define HSEM_C2ICR_ISC8 HSEM_C2ICR_ISC8_Msk /*!<semaphore 8 interrupt 1 clear bit. */
\r
12734 #define HSEM_C2ICR_ISC9_Pos (9U)
\r
12735 #define HSEM_C2ICR_ISC9_Msk (0x1UL << HSEM_C2ICR_ISC9_Pos) /*!< 0x00000200 */
\r
12736 #define HSEM_C2ICR_ISC9 HSEM_C2ICR_ISC9_Msk /*!<semaphore 9 interrupt 1 clear bit. */
\r
12737 #define HSEM_C2ICR_ISC10_Pos (10U)
\r
12738 #define HSEM_C2ICR_ISC10_Msk (0x1UL << HSEM_C2ICR_ISC10_Pos) /*!< 0x00000400 */
\r
12739 #define HSEM_C2ICR_ISC10 HSEM_C2ICR_ISC10_Msk /*!<semaphore 10 interrupt 1 clear bit. */
\r
12740 #define HSEM_C2ICR_ISC11_Pos (11U)
\r
12741 #define HSEM_C2ICR_ISC11_Msk (0x1UL << HSEM_C2ICR_ISC11_Pos) /*!< 0x00000800 */
\r
12742 #define HSEM_C2ICR_ISC11 HSEM_C2ICR_ISC11_Msk /*!<semaphore 11 interrupt 1 clear bit. */
\r
12743 #define HSEM_C2ICR_ISC12_Pos (12U)
\r
12744 #define HSEM_C2ICR_ISC12_Msk (0x1UL << HSEM_C2ICR_ISC12_Pos) /*!< 0x00001000 */
\r
12745 #define HSEM_C2ICR_ISC12 HSEM_C2ICR_ISC12_Msk /*!<semaphore 12 interrupt 1 clear bit. */
\r
12746 #define HSEM_C2ICR_ISC13_Pos (13U)
\r
12747 #define HSEM_C2ICR_ISC13_Msk (0x1UL << HSEM_C2ICR_ISC13_Pos) /*!< 0x00002000 */
\r
12748 #define HSEM_C2ICR_ISC13 HSEM_C2ICR_ISC13_Msk /*!<semaphore 13 interrupt 1 clear bit. */
\r
12749 #define HSEM_C2ICR_ISC14_Pos (14U)
\r
12750 #define HSEM_C2ICR_ISC14_Msk (0x1UL << HSEM_C2ICR_ISC14_Pos) /*!< 0x00004000 */
\r
12751 #define HSEM_C2ICR_ISC14 HSEM_C2ICR_ISC14_Msk /*!<semaphore 14 interrupt 1 clear bit. */
\r
12752 #define HSEM_C2ICR_ISC15_Pos (15U)
\r
12753 #define HSEM_C2ICR_ISC15_Msk (0x1UL << HSEM_C2ICR_ISC15_Pos) /*!< 0x00008000 */
\r
12754 #define HSEM_C2ICR_ISC15 HSEM_C2ICR_ISC15_Msk /*!<semaphore 15 interrupt 1 clear bit. */
\r
12755 #define HSEM_C2ICR_ISC16_Pos (16U)
\r
12756 #define HSEM_C2ICR_ISC16_Msk (0x1UL << HSEM_C2ICR_ISC16_Pos) /*!< 0x00010000 */
\r
12757 #define HSEM_C2ICR_ISC16 HSEM_C2ICR_ISC16_Msk /*!<semaphore 16 interrupt 1 clear bit. */
\r
12758 #define HSEM_C2ICR_ISC17_Pos (17U)
\r
12759 #define HSEM_C2ICR_ISC17_Msk (0x1UL << HSEM_C2ICR_ISC17_Pos) /*!< 0x00020000 */
\r
12760 #define HSEM_C2ICR_ISC17 HSEM_C2ICR_ISC17_Msk /*!<semaphore 17 interrupt 1 clear bit. */
\r
12761 #define HSEM_C2ICR_ISC18_Pos (18U)
\r
12762 #define HSEM_C2ICR_ISC18_Msk (0x1UL << HSEM_C2ICR_ISC18_Pos) /*!< 0x00040000 */
\r
12763 #define HSEM_C2ICR_ISC18 HSEM_C2ICR_ISC18_Msk /*!<semaphore 18 interrupt 1 clear bit. */
\r
12764 #define HSEM_C2ICR_ISC19_Pos (19U)
\r
12765 #define HSEM_C2ICR_ISC19_Msk (0x1UL << HSEM_C2ICR_ISC19_Pos) /*!< 0x00080000 */
\r
12766 #define HSEM_C2ICR_ISC19 HSEM_C2ICR_ISC19_Msk /*!<semaphore 19 interrupt 1 clear bit. */
\r
12767 #define HSEM_C2ICR_ISC20_Pos (20U)
\r
12768 #define HSEM_C2ICR_ISC20_Msk (0x1UL << HSEM_C2ICR_ISC20_Pos) /*!< 0x00100000 */
\r
12769 #define HSEM_C2ICR_ISC20 HSEM_C2ICR_ISC20_Msk /*!<semaphore 20 interrupt 1 clear bit. */
\r
12770 #define HSEM_C2ICR_ISC21_Pos (21U)
\r
12771 #define HSEM_C2ICR_ISC21_Msk (0x1UL << HSEM_C2ICR_ISC21_Pos) /*!< 0x00200000 */
\r
12772 #define HSEM_C2ICR_ISC21 HSEM_C2ICR_ISC21_Msk /*!<semaphore 21 interrupt 1 clear bit. */
\r
12773 #define HSEM_C2ICR_ISC22_Pos (22U)
\r
12774 #define HSEM_C2ICR_ISC22_Msk (0x1UL << HSEM_C2ICR_ISC22_Pos) /*!< 0x00400000 */
\r
12775 #define HSEM_C2ICR_ISC22 HSEM_C2ICR_ISC22_Msk /*!<semaphore 22 interrupt 1 clear bit. */
\r
12776 #define HSEM_C2ICR_ISC23_Pos (23U)
\r
12777 #define HSEM_C2ICR_ISC23_Msk (0x1UL << HSEM_C2ICR_ISC23_Pos) /*!< 0x00800000 */
\r
12778 #define HSEM_C2ICR_ISC23 HSEM_C2ICR_ISC23_Msk /*!<semaphore 23 interrupt 1 clear bit. */
\r
12779 #define HSEM_C2ICR_ISC24_Pos (24U)
\r
12780 #define HSEM_C2ICR_ISC24_Msk (0x1UL << HSEM_C2ICR_ISC24_Pos) /*!< 0x01000000 */
\r
12781 #define HSEM_C2ICR_ISC24 HSEM_C2ICR_ISC24_Msk /*!<semaphore 24 interrupt 1 clear bit. */
\r
12782 #define HSEM_C2ICR_ISC25_Pos (25U)
\r
12783 #define HSEM_C2ICR_ISC25_Msk (0x1UL << HSEM_C2ICR_ISC25_Pos) /*!< 0x02000000 */
\r
12784 #define HSEM_C2ICR_ISC25 HSEM_C2ICR_ISC25_Msk /*!<semaphore 25 interrupt 1 clear bit. */
\r
12785 #define HSEM_C2ICR_ISC26_Pos (26U)
\r
12786 #define HSEM_C2ICR_ISC26_Msk (0x1UL << HSEM_C2ICR_ISC26_Pos) /*!< 0x04000000 */
\r
12787 #define HSEM_C2ICR_ISC26 HSEM_C2ICR_ISC26_Msk /*!<semaphore 26 interrupt 1 clear bit. */
\r
12788 #define HSEM_C2ICR_ISC27_Pos (27U)
\r
12789 #define HSEM_C2ICR_ISC27_Msk (0x1UL << HSEM_C2ICR_ISC27_Pos) /*!< 0x08000000 */
\r
12790 #define HSEM_C2ICR_ISC27 HSEM_C2ICR_ISC27_Msk /*!<semaphore 27 interrupt 1 clear bit. */
\r
12791 #define HSEM_C2ICR_ISC28_Pos (28U)
\r
12792 #define HSEM_C2ICR_ISC28_Msk (0x1UL << HSEM_C2ICR_ISC28_Pos) /*!< 0x10000000 */
\r
12793 #define HSEM_C2ICR_ISC28 HSEM_C2ICR_ISC28_Msk /*!<semaphore 28 interrupt 1 clear bit. */
\r
12794 #define HSEM_C2ICR_ISC29_Pos (29U)
\r
12795 #define HSEM_C2ICR_ISC29_Msk (0x1UL << HSEM_C2ICR_ISC29_Pos) /*!< 0x20000000 */
\r
12796 #define HSEM_C2ICR_ISC29 HSEM_C2ICR_ISC29_Msk /*!<semaphore 29 interrupt 1 clear bit. */
\r
12797 #define HSEM_C2ICR_ISC30_Pos (30U)
\r
12798 #define HSEM_C2ICR_ISC30_Msk (0x1UL << HSEM_C2ICR_ISC30_Pos) /*!< 0x40000000 */
\r
12799 #define HSEM_C2ICR_ISC30 HSEM_C2ICR_ISC30_Msk /*!<semaphore 30 interrupt 1 clear bit. */
\r
12800 #define HSEM_C2ICR_ISC31_Pos (31U)
\r
12801 #define HSEM_C2ICR_ISC31_Msk (0x1UL << HSEM_C2ICR_ISC31_Pos) /*!< 0x80000000 */
\r
12802 #define HSEM_C2ICR_ISC31 HSEM_C2ICR_ISC31_Msk /*!<semaphore 31 interrupt 1 clear bit. */
\r
12804 /******************** Bit definition for HSEM_C2ISR register *****************/
\r
12805 #define HSEM_C2ISR_ISF0_Pos (0U)
\r
12806 #define HSEM_C2ISR_ISF0_Msk (0x1UL << HSEM_C2ISR_ISF0_Pos) /*!< 0x00000001 */
\r
12807 #define HSEM_C2ISR_ISF0 HSEM_C2ISR_ISF0_Msk /*!<semaphore 0 interrupt 1 status bit. */
\r
12808 #define HSEM_C2ISR_ISF1_Pos (1U)
\r
12809 #define HSEM_C2ISR_ISF1_Msk (0x1UL << HSEM_C2ISR_ISF1_Pos) /*!< 0x00000002 */
\r
12810 #define HSEM_C2ISR_ISF1 HSEM_C2ISR_ISF1_Msk /*!<semaphore 1 interrupt 1 status bit. */
\r
12811 #define HSEM_C2ISR_ISF2_Pos (2U)
\r
12812 #define HSEM_C2ISR_ISF2_Msk (0x1UL << HSEM_C2ISR_ISF2_Pos) /*!< 0x00000004 */
\r
12813 #define HSEM_C2ISR_ISF2 HSEM_C2ISR_ISF2_Msk /*!<semaphore 2 interrupt 1 status bit. */
\r
12814 #define HSEM_C2ISR_ISF3_Pos (3U)
\r
12815 #define HSEM_C2ISR_ISF3_Msk (0x1UL << HSEM_C2ISR_ISF3_Pos) /*!< 0x00000008 */
\r
12816 #define HSEM_C2ISR_ISF3 HSEM_C2ISR_ISF3_Msk /*!<semaphore 3 interrupt 1 status bit. */
\r
12817 #define HSEM_C2ISR_ISF4_Pos (4U)
\r
12818 #define HSEM_C2ISR_ISF4_Msk (0x1UL << HSEM_C2ISR_ISF4_Pos) /*!< 0x00000010 */
\r
12819 #define HSEM_C2ISR_ISF4 HSEM_C2ISR_ISF4_Msk /*!<semaphore 4 interrupt 1 status bit. */
\r
12820 #define HSEM_C2ISR_ISF5_Pos (5U)
\r
12821 #define HSEM_C2ISR_ISF5_Msk (0x1UL << HSEM_C2ISR_ISF5_Pos) /*!< 0x00000020 */
\r
12822 #define HSEM_C2ISR_ISF5 HSEM_C2ISR_ISF5_Msk /*!<semaphore 5 interrupt 1 status bit. */
\r
12823 #define HSEM_C2ISR_ISF6_Pos (6U)
\r
12824 #define HSEM_C2ISR_ISF6_Msk (0x1UL << HSEM_C2ISR_ISF6_Pos) /*!< 0x00000040 */
\r
12825 #define HSEM_C2ISR_ISF6 HSEM_C2ISR_ISF6_Msk /*!<semaphore 6 interrupt 1 status bit. */
\r
12826 #define HSEM_C2ISR_ISF7_Pos (7U)
\r
12827 #define HSEM_C2ISR_ISF7_Msk (0x1UL << HSEM_C2ISR_ISF7_Pos) /*!< 0x00000080 */
\r
12828 #define HSEM_C2ISR_ISF7 HSEM_C2ISR_ISF7_Msk /*!<semaphore 7 interrupt 1 status bit. */
\r
12829 #define HSEM_C2ISR_ISF8_Pos (8U)
\r
12830 #define HSEM_C2ISR_ISF8_Msk (0x1UL << HSEM_C2ISR_ISF8_Pos) /*!< 0x00000100 */
\r
12831 #define HSEM_C2ISR_ISF8 HSEM_C2ISR_ISF8_Msk /*!<semaphore 8 interrupt 1 status bit. */
\r
12832 #define HSEM_C2ISR_ISF9_Pos (9U)
\r
12833 #define HSEM_C2ISR_ISF9_Msk (0x1UL << HSEM_C2ISR_ISF9_Pos) /*!< 0x00000200 */
\r
12834 #define HSEM_C2ISR_ISF9 HSEM_C2ISR_ISF9_Msk /*!<semaphore 9 interrupt 1 status bit. */
\r
12835 #define HSEM_C2ISR_ISF10_Pos (10U)
\r
12836 #define HSEM_C2ISR_ISF10_Msk (0x1UL << HSEM_C2ISR_ISF10_Pos) /*!< 0x00000400 */
\r
12837 #define HSEM_C2ISR_ISF10 HSEM_C2ISR_ISF10_Msk /*!<semaphore 10 interrupt 1 status bit. */
\r
12838 #define HSEM_C2ISR_ISF11_Pos (11U)
\r
12839 #define HSEM_C2ISR_ISF11_Msk (0x1UL << HSEM_C2ISR_ISF11_Pos) /*!< 0x00000800 */
\r
12840 #define HSEM_C2ISR_ISF11 HSEM_C2ISR_ISF11_Msk /*!<semaphore 11 interrupt 1 status bit. */
\r
12841 #define HSEM_C2ISR_ISF12_Pos (12U)
\r
12842 #define HSEM_C2ISR_ISF12_Msk (0x1UL << HSEM_C2ISR_ISF12_Pos) /*!< 0x00001000 */
\r
12843 #define HSEM_C2ISR_ISF12 HSEM_C2ISR_ISF12_Msk /*!<semaphore 12 interrupt 1 status bit. */
\r
12844 #define HSEM_C2ISR_ISF13_Pos (13U)
\r
12845 #define HSEM_C2ISR_ISF13_Msk (0x1UL << HSEM_C2ISR_ISF13_Pos) /*!< 0x00002000 */
\r
12846 #define HSEM_C2ISR_ISF13 HSEM_C2ISR_ISF13_Msk /*!<semaphore 13 interrupt 1 status bit. */
\r
12847 #define HSEM_C2ISR_ISF14_Pos (14U)
\r
12848 #define HSEM_C2ISR_ISF14_Msk (0x1UL << HSEM_C2ISR_ISF14_Pos) /*!< 0x00004000 */
\r
12849 #define HSEM_C2ISR_ISF14 HSEM_C2ISR_ISF14_Msk /*!<semaphore 14 interrupt 1 status bit. */
\r
12850 #define HSEM_C2ISR_ISF15_Pos (15U)
\r
12851 #define HSEM_C2ISR_ISF15_Msk (0x1UL << HSEM_C2ISR_ISF15_Pos) /*!< 0x00008000 */
\r
12852 #define HSEM_C2ISR_ISF15 HSEM_C2ISR_ISF15_Msk /*!<semaphore 15 interrupt 1 status bit. */
\r
12853 #define HSEM_C2ISR_ISF16_Pos (16U)
\r
12854 #define HSEM_C2ISR_ISF16_Msk (0x1UL << HSEM_C2ISR_ISF16_Pos) /*!< 0x00010000 */
\r
12855 #define HSEM_C2ISR_ISF16 HSEM_C2ISR_ISF16_Msk /*!<semaphore 16 interrupt 1 status bit. */
\r
12856 #define HSEM_C2ISR_ISF17_Pos (17U)
\r
12857 #define HSEM_C2ISR_ISF17_Msk (0x1UL << HSEM_C2ISR_ISF17_Pos) /*!< 0x00020000 */
\r
12858 #define HSEM_C2ISR_ISF17 HSEM_C2ISR_ISF17_Msk /*!<semaphore 17 interrupt 1 status bit. */
\r
12859 #define HSEM_C2ISR_ISF18_Pos (18U)
\r
12860 #define HSEM_C2ISR_ISF18_Msk (0x1UL << HSEM_C2ISR_ISF18_Pos) /*!< 0x00040000 */
\r
12861 #define HSEM_C2ISR_ISF18 HSEM_C2ISR_ISF18_Msk /*!<semaphore 18 interrupt 1 status bit. */
\r
12862 #define HSEM_C2ISR_ISF19_Pos (19U)
\r
12863 #define HSEM_C2ISR_ISF19_Msk (0x1UL << HSEM_C2ISR_ISF19_Pos) /*!< 0x00080000 */
\r
12864 #define HSEM_C2ISR_ISF19 HSEM_C2ISR_ISF19_Msk /*!<semaphore 19 interrupt 1 status bit. */
\r
12865 #define HSEM_C2ISR_ISF20_Pos (20U)
\r
12866 #define HSEM_C2ISR_ISF20_Msk (0x1UL << HSEM_C2ISR_ISF20_Pos) /*!< 0x00100000 */
\r
12867 #define HSEM_C2ISR_ISF20 HSEM_C2ISR_ISF20_Msk /*!<semaphore 20 interrupt 1 status bit. */
\r
12868 #define HSEM_C2ISR_ISF21_Pos (21U)
\r
12869 #define HSEM_C2ISR_ISF21_Msk (0x1UL << HSEM_C2ISR_ISF21_Pos) /*!< 0x00200000 */
\r
12870 #define HSEM_C2ISR_ISF21 HSEM_C2ISR_ISF21_Msk /*!<semaphore 21 interrupt 1 status bit. */
\r
12871 #define HSEM_C2ISR_ISF22_Pos (22U)
\r
12872 #define HSEM_C2ISR_ISF22_Msk (0x1UL << HSEM_C2ISR_ISF22_Pos) /*!< 0x00400000 */
\r
12873 #define HSEM_C2ISR_ISF22 HSEM_C2ISR_ISF22_Msk /*!<semaphore 22 interrupt 1 status bit. */
\r
12874 #define HSEM_C2ISR_ISF23_Pos (23U)
\r
12875 #define HSEM_C2ISR_ISF23_Msk (0x1UL << HSEM_C2ISR_ISF23_Pos) /*!< 0x00800000 */
\r
12876 #define HSEM_C2ISR_ISF23 HSEM_C2ISR_ISF23_Msk /*!<semaphore 23 interrupt 1 status bit. */
\r
12877 #define HSEM_C2ISR_ISF24_Pos (24U)
\r
12878 #define HSEM_C2ISR_ISF24_Msk (0x1UL << HSEM_C2ISR_ISF24_Pos) /*!< 0x01000000 */
\r
12879 #define HSEM_C2ISR_ISF24 HSEM_C2ISR_ISF24_Msk /*!<semaphore 24 interrupt 1 status bit. */
\r
12880 #define HSEM_C2ISR_ISF25_Pos (25U)
\r
12881 #define HSEM_C2ISR_ISF25_Msk (0x1UL << HSEM_C2ISR_ISF25_Pos) /*!< 0x02000000 */
\r
12882 #define HSEM_C2ISR_ISF25 HSEM_C2ISR_ISF25_Msk /*!<semaphore 25 interrupt 1 status bit. */
\r
12883 #define HSEM_C2ISR_ISF26_Pos (26U)
\r
12884 #define HSEM_C2ISR_ISF26_Msk (0x1UL << HSEM_C2ISR_ISF26_Pos) /*!< 0x04000000 */
\r
12885 #define HSEM_C2ISR_ISF26 HSEM_C2ISR_ISF26_Msk /*!<semaphore 26 interrupt 1 status bit. */
\r
12886 #define HSEM_C2ISR_ISF27_Pos (27U)
\r
12887 #define HSEM_C2ISR_ISF27_Msk (0x1UL << HSEM_C2ISR_ISF27_Pos) /*!< 0x08000000 */
\r
12888 #define HSEM_C2ISR_ISF27 HSEM_C2ISR_ISF27_Msk /*!<semaphore 27 interrupt 1 status bit. */
\r
12889 #define HSEM_C2ISR_ISF28_Pos (28U)
\r
12890 #define HSEM_C2ISR_ISF28_Msk (0x1UL << HSEM_C2ISR_ISF28_Pos) /*!< 0x10000000 */
\r
12891 #define HSEM_C2ISR_ISF28 HSEM_C2ISR_ISF28_Msk /*!<semaphore 28 interrupt 1 status bit. */
\r
12892 #define HSEM_C2ISR_ISF29_Pos (29U)
\r
12893 #define HSEM_C2ISR_ISF29_Msk (0x1UL << HSEM_C2ISR_ISF29_Pos) /*!< 0x20000000 */
\r
12894 #define HSEM_C2ISR_ISF29 HSEM_C2ISR_ISF29_Msk /*!<semaphore 29 interrupt 1 status bit. */
\r
12895 #define HSEM_C2ISR_ISF30_Pos (30U)
\r
12896 #define HSEM_C2ISR_ISF30_Msk (0x1UL << HSEM_C2ISR_ISF30_Pos) /*!< 0x40000000 */
\r
12897 #define HSEM_C2ISR_ISF30 HSEM_C2ISR_ISF30_Msk /*!<semaphore 30 interrupt 1 status bit. */
\r
12898 #define HSEM_C2ISR_ISF31_Pos (31U)
\r
12899 #define HSEM_C2ISR_ISF31_Msk (0x1UL << HSEM_C2ISR_ISF31_Pos) /*!< 0x80000000 */
\r
12900 #define HSEM_C2ISR_ISF31 HSEM_C2ISR_ISF31_Msk /*!<semaphore 31 interrupt 1 status bit. */
\r
12902 /******************** Bit definition for HSEM_C2MISR register *****************/
\r
12903 #define HSEM_C2MISR_MISF0_Pos (0U)
\r
12904 #define HSEM_C2MISR_MISF0_Msk (0x1UL << HSEM_C2MISR_MISF0_Pos) /*!< 0x00000001 */
\r
12905 #define HSEM_C2MISR_MISF0 HSEM_C2MISR_MISF0_Msk /*!<semaphore 0 interrupt 1 masked status bit. */
\r
12906 #define HSEM_C2MISR_MISF1_Pos (1U)
\r
12907 #define HSEM_C2MISR_MISF1_Msk (0x1UL << HSEM_C2MISR_MISF1_Pos) /*!< 0x00000002 */
\r
12908 #define HSEM_C2MISR_MISF1 HSEM_C2MISR_MISF1_Msk /*!<semaphore 1 interrupt 1 masked status bit. */
\r
12909 #define HSEM_C2MISR_MISF2_Pos (2U)
\r
12910 #define HSEM_C2MISR_MISF2_Msk (0x1UL << HSEM_C2MISR_MISF2_Pos) /*!< 0x00000004 */
\r
12911 #define HSEM_C2MISR_MISF2 HSEM_C2MISR_MISF2_Msk /*!<semaphore 2 interrupt 1 masked status bit. */
\r
12912 #define HSEM_C2MISR_MISF3_Pos (3U)
\r
12913 #define HSEM_C2MISR_MISF3_Msk (0x1UL << HSEM_C2MISR_MISF3_Pos) /*!< 0x00000008 */
\r
12914 #define HSEM_C2MISR_MISF3 HSEM_C2MISR_MISF3_Msk /*!<semaphore 3 interrupt 1 masked status bit. */
\r
12915 #define HSEM_C2MISR_MISF4_Pos (4U)
\r
12916 #define HSEM_C2MISR_MISF4_Msk (0x1UL << HSEM_C2MISR_MISF4_Pos) /*!< 0x00000010 */
\r
12917 #define HSEM_C2MISR_MISF4 HSEM_C2MISR_MISF4_Msk /*!<semaphore 4 interrupt 1 masked status bit. */
\r
12918 #define HSEM_C2MISR_MISF5_Pos (5U)
\r
12919 #define HSEM_C2MISR_MISF5_Msk (0x1UL << HSEM_C2MISR_MISF5_Pos) /*!< 0x00000020 */
\r
12920 #define HSEM_C2MISR_MISF5 HSEM_C2MISR_MISF5_Msk /*!<semaphore 5 interrupt 1 masked status bit. */
\r
12921 #define HSEM_C2MISR_MISF6_Pos (6U)
\r
12922 #define HSEM_C2MISR_MISF6_Msk (0x1UL << HSEM_C2MISR_MISF6_Pos) /*!< 0x00000040 */
\r
12923 #define HSEM_C2MISR_MISF6 HSEM_C2MISR_MISF6_Msk /*!<semaphore 6 interrupt 1 masked status bit. */
\r
12924 #define HSEM_C2MISR_MISF7_Pos (7U)
\r
12925 #define HSEM_C2MISR_MISF7_Msk (0x1UL << HSEM_C2MISR_MISF7_Pos) /*!< 0x00000080 */
\r
12926 #define HSEM_C2MISR_MISF7 HSEM_C2MISR_MISF7_Msk /*!<semaphore 7 interrupt 1 masked status bit. */
\r
12927 #define HSEM_C2MISR_MISF8_Pos (8U)
\r
12928 #define HSEM_C2MISR_MISF8_Msk (0x1UL << HSEM_C2MISR_MISF8_Pos) /*!< 0x00000100 */
\r
12929 #define HSEM_C2MISR_MISF8 HSEM_C2MISR_MISF8_Msk /*!<semaphore 8 interrupt 1 masked status bit. */
\r
12930 #define HSEM_C2MISR_MISF9_Pos (9U)
\r
12931 #define HSEM_C2MISR_MISF9_Msk (0x1UL << HSEM_C2MISR_MISF9_Pos) /*!< 0x00000200 */
\r
12932 #define HSEM_C2MISR_MISF9 HSEM_C2MISR_MISF9_Msk /*!<semaphore 9 interrupt 1 masked status bit. */
\r
12933 #define HSEM_C2MISR_MISF10_Pos (10U)
\r
12934 #define HSEM_C2MISR_MISF10_Msk (0x1UL << HSEM_C2MISR_MISF10_Pos) /*!< 0x00000400 */
\r
12935 #define HSEM_C2MISR_MISF10 HSEM_C2MISR_MISF10_Msk /*!<semaphore 10 interrupt 1 masked status bit. */
\r
12936 #define HSEM_C2MISR_MISF11_Pos (11U)
\r
12937 #define HSEM_C2MISR_MISF11_Msk (0x1UL << HSEM_C2MISR_MISF11_Pos) /*!< 0x00000800 */
\r
12938 #define HSEM_C2MISR_MISF11 HSEM_C2MISR_MISF11_Msk /*!<semaphore 11 interrupt 1 masked status bit. */
\r
12939 #define HSEM_C2MISR_MISF12_Pos (12U)
\r
12940 #define HSEM_C2MISR_MISF12_Msk (0x1UL << HSEM_C2MISR_MISF12_Pos) /*!< 0x00001000 */
\r
12941 #define HSEM_C2MISR_MISF12 HSEM_C2MISR_MISF12_Msk /*!<semaphore 12 interrupt 1 masked status bit. */
\r
12942 #define HSEM_C2MISR_MISF13_Pos (13U)
\r
12943 #define HSEM_C2MISR_MISF13_Msk (0x1UL << HSEM_C2MISR_MISF13_Pos) /*!< 0x00002000 */
\r
12944 #define HSEM_C2MISR_MISF13 HSEM_C2MISR_MISF13_Msk /*!<semaphore 13 interrupt 1 masked status bit. */
\r
12945 #define HSEM_C2MISR_MISF14_Pos (14U)
\r
12946 #define HSEM_C2MISR_MISF14_Msk (0x1UL << HSEM_C2MISR_MISF14_Pos) /*!< 0x00004000 */
\r
12947 #define HSEM_C2MISR_MISF14 HSEM_C2MISR_MISF14_Msk /*!<semaphore 14 interrupt 1 masked status bit. */
\r
12948 #define HSEM_C2MISR_MISF15_Pos (15U)
\r
12949 #define HSEM_C2MISR_MISF15_Msk (0x1UL << HSEM_C2MISR_MISF15_Pos) /*!< 0x00008000 */
\r
12950 #define HSEM_C2MISR_MISF15 HSEM_C2MISR_MISF15_Msk /*!<semaphore 15 interrupt 1 masked status bit. */
\r
12951 #define HSEM_C2MISR_MISF16_Pos (16U)
\r
12952 #define HSEM_C2MISR_MISF16_Msk (0x1UL << HSEM_C2MISR_MISF16_Pos) /*!< 0x00010000 */
\r
12953 #define HSEM_C2MISR_MISF16 HSEM_C2MISR_MISF16_Msk /*!<semaphore 16 interrupt 1 masked status bit. */
\r
12954 #define HSEM_C2MISR_MISF17_Pos (17U)
\r
12955 #define HSEM_C2MISR_MISF17_Msk (0x1UL << HSEM_C2MISR_MISF17_Pos) /*!< 0x00020000 */
\r
12956 #define HSEM_C2MISR_MISF17 HSEM_C2MISR_MISF17_Msk /*!<semaphore 17 interrupt 1 masked status bit. */
\r
12957 #define HSEM_C2MISR_MISF18_Pos (18U)
\r
12958 #define HSEM_C2MISR_MISF18_Msk (0x1UL << HSEM_C2MISR_MISF18_Pos) /*!< 0x00040000 */
\r
12959 #define HSEM_C2MISR_MISF18 HSEM_C2MISR_MISF18_Msk /*!<semaphore 18 interrupt 1 masked status bit. */
\r
12960 #define HSEM_C2MISR_MISF19_Pos (19U)
\r
12961 #define HSEM_C2MISR_MISF19_Msk (0x1UL << HSEM_C2MISR_MISF19_Pos) /*!< 0x00080000 */
\r
12962 #define HSEM_C2MISR_MISF19 HSEM_C2MISR_MISF19_Msk /*!<semaphore 19 interrupt 1 masked status bit. */
\r
12963 #define HSEM_C2MISR_MISF20_Pos (20U)
\r
12964 #define HSEM_C2MISR_MISF20_Msk (0x1UL << HSEM_C2MISR_MISF20_Pos) /*!< 0x00100000 */
\r
12965 #define HSEM_C2MISR_MISF20 HSEM_C2MISR_MISF20_Msk /*!<semaphore 20 interrupt 1 masked status bit. */
\r
12966 #define HSEM_C2MISR_MISF21_Pos (21U)
\r
12967 #define HSEM_C2MISR_MISF21_Msk (0x1UL << HSEM_C2MISR_MISF21_Pos) /*!< 0x00200000 */
\r
12968 #define HSEM_C2MISR_MISF21 HSEM_C2MISR_MISF21_Msk /*!<semaphore 21 interrupt 1 masked status bit. */
\r
12969 #define HSEM_C2MISR_MISF22_Pos (22U)
\r
12970 #define HSEM_C2MISR_MISF22_Msk (0x1UL << HSEM_C2MISR_MISF22_Pos) /*!< 0x00400000 */
\r
12971 #define HSEM_C2MISR_MISF22 HSEM_C2MISR_MISF22_Msk /*!<semaphore 22 interrupt 1 masked status bit. */
\r
12972 #define HSEM_C2MISR_MISF23_Pos (23U)
\r
12973 #define HSEM_C2MISR_MISF23_Msk (0x1UL << HSEM_C2MISR_MISF23_Pos) /*!< 0x00800000 */
\r
12974 #define HSEM_C2MISR_MISF23 HSEM_C2MISR_MISF23_Msk /*!<semaphore 23 interrupt 1 masked status bit. */
\r
12975 #define HSEM_C2MISR_MISF24_Pos (24U)
\r
12976 #define HSEM_C2MISR_MISF24_Msk (0x1UL << HSEM_C2MISR_MISF24_Pos) /*!< 0x01000000 */
\r
12977 #define HSEM_C2MISR_MISF24 HSEM_C2MISR_MISF24_Msk /*!<semaphore 24 interrupt 1 masked status bit. */
\r
12978 #define HSEM_C2MISR_MISF25_Pos (25U)
\r
12979 #define HSEM_C2MISR_MISF25_Msk (0x1UL << HSEM_C2MISR_MISF25_Pos) /*!< 0x02000000 */
\r
12980 #define HSEM_C2MISR_MISF25 HSEM_C2MISR_MISF25_Msk /*!<semaphore 25 interrupt 1 masked status bit. */
\r
12981 #define HSEM_C2MISR_MISF26_Pos (26U)
\r
12982 #define HSEM_C2MISR_MISF26_Msk (0x1UL << HSEM_C2MISR_MISF26_Pos) /*!< 0x04000000 */
\r
12983 #define HSEM_C2MISR_MISF26 HSEM_C2MISR_MISF26_Msk /*!<semaphore 26 interrupt 1 masked status bit. */
\r
12984 #define HSEM_C2MISR_MISF27_Pos (27U)
\r
12985 #define HSEM_C2MISR_MISF27_Msk (0x1UL << HSEM_C2MISR_MISF27_Pos) /*!< 0x08000000 */
\r
12986 #define HSEM_C2MISR_MISF27 HSEM_C2MISR_MISF27_Msk /*!<semaphore 27 interrupt 1 masked status bit. */
\r
12987 #define HSEM_C2MISR_MISF28_Pos (28U)
\r
12988 #define HSEM_C2MISR_MISF28_Msk (0x1UL << HSEM_C2MISR_MISF28_Pos) /*!< 0x10000000 */
\r
12989 #define HSEM_C2MISR_MISF28 HSEM_C2MISR_MISF28_Msk /*!<semaphore 28 interrupt 1 masked status bit. */
\r
12990 #define HSEM_C2MISR_MISF29_Pos (29U)
\r
12991 #define HSEM_C2MISR_MISF29_Msk (0x1UL << HSEM_C2MISR_MISF29_Pos) /*!< 0x20000000 */
\r
12992 #define HSEM_C2MISR_MISF29 HSEM_C2MISR_MISF29_Msk /*!<semaphore 29 interrupt 1 masked status bit. */
\r
12993 #define HSEM_C2MISR_MISF30_Pos (30U)
\r
12994 #define HSEM_C2MISR_MISF30_Msk (0x1UL << HSEM_C2MISR_MISF30_Pos) /*!< 0x40000000 */
\r
12995 #define HSEM_C2MISR_MISF30 HSEM_C2MISR_MISF30_Msk /*!<semaphore 30 interrupt 1 masked status bit. */
\r
12996 #define HSEM_C2MISR_MISF31_Pos (31U)
\r
12997 #define HSEM_C2MISR_MISF31_Msk (0x1UL << HSEM_C2MISR_MISF31_Pos) /*!< 0x80000000 */
\r
12998 #define HSEM_C2MISR_MISF31 HSEM_C2MISR_MISF31_Msk /*!<semaphore 31 interrupt 1 masked status bit. */
\r
12999 /******************** Bit definition for HSEM_CR register *****************/
\r
13000 #define HSEM_CR_COREID_Pos (8U)
\r
13001 #define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) /*!< 0x0000FF00 */
\r
13002 #define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */
\r
13003 #define HSEM_CR_KEY_Pos (16U)
\r
13004 #define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
\r
13005 #define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
\r
13007 /******************** Bit definition for HSEM_KEYR register *****************/
\r
13008 #define HSEM_KEYR_KEY_Pos (16U)
\r
13009 #define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
\r
13010 #define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
\r
13012 /******************************************************************************/
\r
13014 /* Inter-integrated Circuit Interface (I2C) */
\r
13016 /******************************************************************************/
\r
13017 /******************* Bit definition for I2C_CR1 register *******************/
\r
13018 #define I2C_CR1_PE_Pos (0U)
\r
13019 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
\r
13020 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
\r
13021 #define I2C_CR1_TXIE_Pos (1U)
\r
13022 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
\r
13023 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
\r
13024 #define I2C_CR1_RXIE_Pos (2U)
\r
13025 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
\r
13026 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
\r
13027 #define I2C_CR1_ADDRIE_Pos (3U)
\r
13028 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
\r
13029 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
\r
13030 #define I2C_CR1_NACKIE_Pos (4U)
\r
13031 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
\r
13032 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
\r
13033 #define I2C_CR1_STOPIE_Pos (5U)
\r
13034 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
\r
13035 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
\r
13036 #define I2C_CR1_TCIE_Pos (6U)
\r
13037 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
\r
13038 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
\r
13039 #define I2C_CR1_ERRIE_Pos (7U)
\r
13040 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
\r
13041 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
\r
13042 #define I2C_CR1_DNF_Pos (8U)
\r
13043 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
\r
13044 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
\r
13045 #define I2C_CR1_ANFOFF_Pos (12U)
\r
13046 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
\r
13047 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
\r
13048 #define I2C_CR1_TXDMAEN_Pos (14U)
\r
13049 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
\r
13050 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
\r
13051 #define I2C_CR1_RXDMAEN_Pos (15U)
\r
13052 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
\r
13053 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
\r
13054 #define I2C_CR1_SBC_Pos (16U)
\r
13055 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
\r
13056 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
\r
13057 #define I2C_CR1_NOSTRETCH_Pos (17U)
\r
13058 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
\r
13059 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
\r
13060 #define I2C_CR1_WUPEN_Pos (18U)
\r
13061 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
\r
13062 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
\r
13063 #define I2C_CR1_GCEN_Pos (19U)
\r
13064 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
\r
13065 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
\r
13066 #define I2C_CR1_SMBHEN_Pos (20U)
\r
13067 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
\r
13068 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
\r
13069 #define I2C_CR1_SMBDEN_Pos (21U)
\r
13070 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
\r
13071 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
\r
13072 #define I2C_CR1_ALERTEN_Pos (22U)
\r
13073 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
\r
13074 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
\r
13075 #define I2C_CR1_PECEN_Pos (23U)
\r
13076 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
\r
13077 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
\r
13079 /****************** Bit definition for I2C_CR2 register ********************/
\r
13080 #define I2C_CR2_SADD_Pos (0U)
\r
13081 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
\r
13082 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
\r
13083 #define I2C_CR2_RD_WRN_Pos (10U)
\r
13084 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
\r
13085 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
\r
13086 #define I2C_CR2_ADD10_Pos (11U)
\r
13087 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
\r
13088 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
\r
13089 #define I2C_CR2_HEAD10R_Pos (12U)
\r
13090 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
\r
13091 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
\r
13092 #define I2C_CR2_START_Pos (13U)
\r
13093 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
\r
13094 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
\r
13095 #define I2C_CR2_STOP_Pos (14U)
\r
13096 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
\r
13097 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
\r
13098 #define I2C_CR2_NACK_Pos (15U)
\r
13099 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
\r
13100 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
\r
13101 #define I2C_CR2_NBYTES_Pos (16U)
\r
13102 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
\r
13103 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
\r
13104 #define I2C_CR2_RELOAD_Pos (24U)
\r
13105 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
\r
13106 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
\r
13107 #define I2C_CR2_AUTOEND_Pos (25U)
\r
13108 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
\r
13109 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
\r
13110 #define I2C_CR2_PECBYTE_Pos (26U)
\r
13111 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
\r
13112 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
\r
13114 /******************* Bit definition for I2C_OAR1 register ******************/
\r
13115 #define I2C_OAR1_OA1_Pos (0U)
\r
13116 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
\r
13117 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
\r
13118 #define I2C_OAR1_OA1MODE_Pos (10U)
\r
13119 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
\r
13120 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
\r
13121 #define I2C_OAR1_OA1EN_Pos (15U)
\r
13122 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
\r
13123 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
\r
13125 /******************* Bit definition for I2C_OAR2 register ******************/
\r
13126 #define I2C_OAR2_OA2_Pos (1U)
\r
13127 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
\r
13128 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
\r
13129 #define I2C_OAR2_OA2MSK_Pos (8U)
\r
13130 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
\r
13131 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
\r
13132 #define I2C_OAR2_OA2NOMASK 0x00000000UL /*!< No mask */
\r
13133 #define I2C_OAR2_OA2MASK01_Pos (8U)
\r
13134 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
\r
13135 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
\r
13136 #define I2C_OAR2_OA2MASK02_Pos (9U)
\r
13137 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
\r
13138 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
\r
13139 #define I2C_OAR2_OA2MASK03_Pos (8U)
\r
13140 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
\r
13141 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
\r
13142 #define I2C_OAR2_OA2MASK04_Pos (10U)
\r
13143 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
\r
13144 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
\r
13145 #define I2C_OAR2_OA2MASK05_Pos (8U)
\r
13146 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
\r
13147 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
\r
13148 #define I2C_OAR2_OA2MASK06_Pos (9U)
\r
13149 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
\r
13150 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
\r
13151 #define I2C_OAR2_OA2MASK07_Pos (8U)
\r
13152 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
\r
13153 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
\r
13154 #define I2C_OAR2_OA2EN_Pos (15U)
\r
13155 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
\r
13156 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
\r
13158 /******************* Bit definition for I2C_TIMINGR register *******************/
\r
13159 #define I2C_TIMINGR_SCLL_Pos (0U)
\r
13160 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
\r
13161 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
\r
13162 #define I2C_TIMINGR_SCLH_Pos (8U)
\r
13163 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
\r
13164 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
\r
13165 #define I2C_TIMINGR_SDADEL_Pos (16U)
\r
13166 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
\r
13167 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
\r
13168 #define I2C_TIMINGR_SCLDEL_Pos (20U)
\r
13169 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
\r
13170 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
\r
13171 #define I2C_TIMINGR_PRESC_Pos (28U)
\r
13172 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
\r
13173 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
\r
13175 /******************* Bit definition for I2C_TIMEOUTR register *******************/
\r
13176 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
\r
13177 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
\r
13178 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
\r
13179 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
\r
13180 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
\r
13181 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
\r
13182 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
\r
13183 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
\r
13184 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
\r
13185 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
\r
13186 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
\r
13187 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
\r
13188 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
\r
13189 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
\r
13190 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
\r
13192 /****************** Bit definition for I2C_ISR register *********************/
\r
13193 #define I2C_ISR_TXE_Pos (0U)
\r
13194 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
\r
13195 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
\r
13196 #define I2C_ISR_TXIS_Pos (1U)
\r
13197 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
\r
13198 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
\r
13199 #define I2C_ISR_RXNE_Pos (2U)
\r
13200 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
\r
13201 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
\r
13202 #define I2C_ISR_ADDR_Pos (3U)
\r
13203 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
\r
13204 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
\r
13205 #define I2C_ISR_NACKF_Pos (4U)
\r
13206 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
\r
13207 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
\r
13208 #define I2C_ISR_STOPF_Pos (5U)
\r
13209 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
\r
13210 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
\r
13211 #define I2C_ISR_TC_Pos (6U)
\r
13212 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
\r
13213 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
\r
13214 #define I2C_ISR_TCR_Pos (7U)
\r
13215 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
\r
13216 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
\r
13217 #define I2C_ISR_BERR_Pos (8U)
\r
13218 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
\r
13219 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
\r
13220 #define I2C_ISR_ARLO_Pos (9U)
\r
13221 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
\r
13222 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
\r
13223 #define I2C_ISR_OVR_Pos (10U)
\r
13224 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
\r
13225 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
\r
13226 #define I2C_ISR_PECERR_Pos (11U)
\r
13227 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
\r
13228 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
\r
13229 #define I2C_ISR_TIMEOUT_Pos (12U)
\r
13230 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
\r
13231 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
\r
13232 #define I2C_ISR_ALERT_Pos (13U)
\r
13233 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
\r
13234 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
\r
13235 #define I2C_ISR_BUSY_Pos (15U)
\r
13236 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
\r
13237 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
\r
13238 #define I2C_ISR_DIR_Pos (16U)
\r
13239 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
\r
13240 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
\r
13241 #define I2C_ISR_ADDCODE_Pos (17U)
\r
13242 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
\r
13243 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
\r
13245 /****************** Bit definition for I2C_ICR register *********************/
\r
13246 #define I2C_ICR_ADDRCF_Pos (3U)
\r
13247 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
\r
13248 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
\r
13249 #define I2C_ICR_NACKCF_Pos (4U)
\r
13250 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
\r
13251 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
\r
13252 #define I2C_ICR_STOPCF_Pos (5U)
\r
13253 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
\r
13254 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
\r
13255 #define I2C_ICR_BERRCF_Pos (8U)
\r
13256 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
\r
13257 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
\r
13258 #define I2C_ICR_ARLOCF_Pos (9U)
\r
13259 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
\r
13260 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
\r
13261 #define I2C_ICR_OVRCF_Pos (10U)
\r
13262 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
\r
13263 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
\r
13264 #define I2C_ICR_PECCF_Pos (11U)
\r
13265 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
\r
13266 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
\r
13267 #define I2C_ICR_TIMOUTCF_Pos (12U)
\r
13268 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
\r
13269 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
\r
13270 #define I2C_ICR_ALERTCF_Pos (13U)
\r
13271 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
\r
13272 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
\r
13274 /****************** Bit definition for I2C_PECR register *********************/
\r
13275 #define I2C_PECR_PEC_Pos (0U)
\r
13276 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
\r
13277 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
\r
13279 /****************** Bit definition for I2C_RXDR register *********************/
\r
13280 #define I2C_RXDR_RXDATA_Pos (0U)
\r
13281 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
\r
13282 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
\r
13284 /****************** Bit definition for I2C_TXDR register *********************/
\r
13285 #define I2C_TXDR_TXDATA_Pos (0U)
\r
13286 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
\r
13287 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
\r
13289 /******************************************************************************/
\r
13291 /* Independent WATCHDOG */
\r
13293 /******************************************************************************/
\r
13294 /******************* Bit definition for IWDG_KR register ********************/
\r
13295 #define IWDG_KR_KEY_Pos (0U)
\r
13296 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
\r
13297 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
\r
13299 /******************* Bit definition for IWDG_PR register ********************/
\r
13300 #define IWDG_PR_PR_Pos (0U)
\r
13301 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
\r
13302 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
\r
13303 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
\r
13304 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
\r
13305 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
\r
13307 /******************* Bit definition for IWDG_RLR register *******************/
\r
13308 #define IWDG_RLR_RL_Pos (0U)
\r
13309 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
\r
13310 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
\r
13312 /******************* Bit definition for IWDG_SR register ********************/
\r
13313 #define IWDG_SR_PVU_Pos (0U)
\r
13314 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
\r
13315 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
\r
13316 #define IWDG_SR_RVU_Pos (1U)
\r
13317 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
\r
13318 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
\r
13319 #define IWDG_SR_WVU_Pos (2U)
\r
13320 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
\r
13321 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
\r
13323 /******************* Bit definition for IWDG_KR register ********************/
\r
13324 #define IWDG_WINR_WIN_Pos (0U)
\r
13325 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
\r
13326 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
\r
13328 /******************************************************************************/
\r
13330 /* JPEG Encoder/Decoder */
\r
13332 /******************************************************************************/
\r
13333 /******************** Bit definition for CONFR0 register ********************/
\r
13334 #define JPEG_CONFR0_START_Pos (0U)
\r
13335 #define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
\r
13336 #define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
\r
13338 /******************** Bit definition for CONFR1 register ********************/
\r
13339 #define JPEG_CONFR1_NF_Pos (0U)
\r
13340 #define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
\r
13341 #define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
\r
13342 #define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
\r
13343 #define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
\r
13344 #define JPEG_CONFR1_DE_Pos (3U)
\r
13345 #define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
\r
13346 #define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
\r
13347 #define JPEG_CONFR1_COLORSPACE_Pos (4U)
\r
13348 #define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
\r
13349 #define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
\r
13350 #define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
\r
13351 #define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
\r
13352 #define JPEG_CONFR1_NS_Pos (6U)
\r
13353 #define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
\r
13354 #define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
\r
13355 #define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
\r
13356 #define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
\r
13357 #define JPEG_CONFR1_HDR_Pos (8U)
\r
13358 #define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
\r
13359 #define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
\r
13360 #define JPEG_CONFR1_YSIZE_Pos (16U)
\r
13361 #define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
\r
13362 #define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
\r
13364 /******************** Bit definition for CONFR2 register ********************/
\r
13365 #define JPEG_CONFR2_NMCU_Pos (0U)
\r
13366 #define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
\r
13367 #define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
\r
13369 /******************** Bit definition for CONFR3 register ********************/
\r
13370 #define JPEG_CONFR3_XSIZE_Pos (16U)
\r
13371 #define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
\r
13372 #define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
\r
13374 /******************** Bit definition for CONFR4 register ********************/
\r
13375 #define JPEG_CONFR4_HD_Pos (0U)
\r
13376 #define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
\r
13377 #define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
\r
13378 #define JPEG_CONFR4_HA_Pos (1U)
\r
13379 #define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
\r
13380 #define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
\r
13381 #define JPEG_CONFR4_QT_Pos (2U)
\r
13382 #define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
\r
13383 #define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
\r
13384 #define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
\r
13385 #define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
\r
13386 #define JPEG_CONFR4_NB_Pos (4U)
\r
13387 #define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
\r
13388 #define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
\r
13389 #define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
\r
13390 #define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
\r
13391 #define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
\r
13392 #define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
\r
13393 #define JPEG_CONFR4_VSF_Pos (8U)
\r
13394 #define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
\r
13395 #define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
\r
13396 #define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
\r
13397 #define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
\r
13398 #define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
\r
13399 #define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
\r
13400 #define JPEG_CONFR4_HSF_Pos (12U)
\r
13401 #define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
\r
13402 #define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
\r
13403 #define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
\r
13404 #define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
\r
13405 #define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
\r
13406 #define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
\r
13408 /******************** Bit definition for CONFR5 register ********************/
\r
13409 #define JPEG_CONFR5_HD_Pos (0U)
\r
13410 #define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
\r
13411 #define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
\r
13412 #define JPEG_CONFR5_HA_Pos (1U)
\r
13413 #define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
\r
13414 #define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
\r
13415 #define JPEG_CONFR5_QT_Pos (2U)
\r
13416 #define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
\r
13417 #define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
\r
13418 #define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
\r
13419 #define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
\r
13420 #define JPEG_CONFR5_NB_Pos (4U)
\r
13421 #define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
\r
13422 #define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
\r
13423 #define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
\r
13424 #define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
\r
13425 #define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
\r
13426 #define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
\r
13427 #define JPEG_CONFR5_VSF_Pos (8U)
\r
13428 #define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
\r
13429 #define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
\r
13430 #define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
\r
13431 #define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
\r
13432 #define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
\r
13433 #define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
\r
13434 #define JPEG_CONFR5_HSF_Pos (12U)
\r
13435 #define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
\r
13436 #define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
\r
13437 #define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
\r
13438 #define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
\r
13439 #define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
\r
13440 #define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
\r
13442 /******************** Bit definition for CONFR6 register ********************/
\r
13443 #define JPEG_CONFR6_HD_Pos (0U)
\r
13444 #define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
\r
13445 #define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
\r
13446 #define JPEG_CONFR6_HA_Pos (1U)
\r
13447 #define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
\r
13448 #define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
\r
13449 #define JPEG_CONFR6_QT_Pos (2U)
\r
13450 #define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
\r
13451 #define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
\r
13452 #define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
\r
13453 #define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
\r
13454 #define JPEG_CONFR6_NB_Pos (4U)
\r
13455 #define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
\r
13456 #define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
\r
13457 #define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
\r
13458 #define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
\r
13459 #define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
\r
13460 #define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
\r
13461 #define JPEG_CONFR6_VSF_Pos (8U)
\r
13462 #define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
\r
13463 #define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
\r
13464 #define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
\r
13465 #define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
\r
13466 #define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
\r
13467 #define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
\r
13468 #define JPEG_CONFR6_HSF_Pos (12U)
\r
13469 #define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
\r
13470 #define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
\r
13471 #define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
\r
13472 #define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
\r
13473 #define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
\r
13474 #define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
\r
13476 /******************** Bit definition for CONFR7 register ********************/
\r
13477 #define JPEG_CONFR7_HD_Pos (0U)
\r
13478 #define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
\r
13479 #define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
\r
13480 #define JPEG_CONFR7_HA_Pos (1U)
\r
13481 #define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
\r
13482 #define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
\r
13483 #define JPEG_CONFR7_QT_Pos (2U)
\r
13484 #define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
\r
13485 #define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
\r
13486 #define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
\r
13487 #define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
\r
13488 #define JPEG_CONFR7_NB_Pos (4U)
\r
13489 #define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
\r
13490 #define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
\r
13491 #define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
\r
13492 #define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
\r
13493 #define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
\r
13494 #define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
\r
13495 #define JPEG_CONFR7_VSF_Pos (8U)
\r
13496 #define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
\r
13497 #define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
\r
13498 #define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
\r
13499 #define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
\r
13500 #define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
\r
13501 #define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
\r
13502 #define JPEG_CONFR7_HSF_Pos (12U)
\r
13503 #define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
\r
13504 #define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
\r
13505 #define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
\r
13506 #define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
\r
13507 #define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
\r
13508 #define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
\r
13510 /******************** Bit definition for CR register ********************/
\r
13511 #define JPEG_CR_JCEN_Pos (0U)
\r
13512 #define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
\r
13513 #define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
\r
13514 #define JPEG_CR_IFTIE_Pos (1U)
\r
13515 #define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
\r
13516 #define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
\r
13517 #define JPEG_CR_IFNFIE_Pos (2U)
\r
13518 #define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
\r
13519 #define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
\r
13520 #define JPEG_CR_OFTIE_Pos (3U)
\r
13521 #define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
\r
13522 #define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
\r
13523 #define JPEG_CR_OFNEIE_Pos (4U)
\r
13524 #define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
\r
13525 #define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
\r
13526 #define JPEG_CR_EOCIE_Pos (5U)
\r
13527 #define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
\r
13528 #define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
\r
13529 #define JPEG_CR_HPDIE_Pos (6U)
\r
13530 #define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
\r
13531 #define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
\r
13532 #define JPEG_CR_IFF_Pos (13U)
\r
13533 #define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
\r
13534 #define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
\r
13535 #define JPEG_CR_OFF_Pos (14U)
\r
13536 #define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
\r
13537 #define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
\r
13539 /******************** Bit definition for SR register ********************/
\r
13540 #define JPEG_SR_IFTF_Pos (1U)
\r
13541 #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
\r
13542 #define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
\r
13543 #define JPEG_SR_IFNFF_Pos (2U)
\r
13544 #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
\r
13545 #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
\r
13546 #define JPEG_SR_OFTF_Pos (3U)
\r
13547 #define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
\r
13548 #define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
\r
13549 #define JPEG_SR_OFNEF_Pos (4U)
\r
13550 #define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000010 */
\r
13551 #define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
\r
13552 #define JPEG_SR_EOCF_Pos (5U)
\r
13553 #define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000020 */
\r
13554 #define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
\r
13555 #define JPEG_SR_HPDF_Pos (6U)
\r
13556 #define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000040 */
\r
13557 #define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
\r
13558 #define JPEG_SR_COF_Pos (7U)
\r
13559 #define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000080 */
\r
13560 #define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
\r
13562 /******************** Bit definition for CFR register ********************/
\r
13563 #define JPEG_CFR_CEOCF_Pos (4U)
\r
13564 #define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000010 */
\r
13565 #define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
\r
13566 #define JPEG_CFR_CHPDF_Pos (5U)
\r
13567 #define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000020 */
\r
13568 #define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
\r
13570 /******************** Bit definition for DIR register ********************/
\r
13571 #define JPEG_DIR_DATAIN_Pos (0U)
\r
13572 #define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
\r
13573 #define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
\r
13575 /******************** Bit definition for DOR register ********************/
\r
13576 #define JPEG_DOR_DATAOUT_Pos (0U)
\r
13577 #define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
\r
13578 #define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
\r
13580 /******************************************************************************/
\r
13582 /* LCD-TFT Display Controller (LTDC) */
\r
13584 /******************************************************************************/
\r
13586 /******************** Bit definition for LTDC_SSCR register *****************/
\r
13588 #define LTDC_SSCR_VSH_Pos (0U)
\r
13589 #define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
\r
13590 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
\r
13591 #define LTDC_SSCR_HSW_Pos (16U)
\r
13592 #define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
\r
13593 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
\r
13595 /******************** Bit definition for LTDC_BPCR register *****************/
\r
13597 #define LTDC_BPCR_AVBP_Pos (0U)
\r
13598 #define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
\r
13599 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
\r
13600 #define LTDC_BPCR_AHBP_Pos (16U)
\r
13601 #define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
\r
13602 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
\r
13604 /******************** Bit definition for LTDC_AWCR register *****************/
\r
13606 #define LTDC_AWCR_AAH_Pos (0U)
\r
13607 #define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
\r
13608 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
\r
13609 #define LTDC_AWCR_AAW_Pos (16U)
\r
13610 #define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
\r
13611 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
\r
13613 /******************** Bit definition for LTDC_TWCR register *****************/
\r
13615 #define LTDC_TWCR_TOTALH_Pos (0U)
\r
13616 #define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
\r
13617 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
\r
13618 #define LTDC_TWCR_TOTALW_Pos (16U)
\r
13619 #define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
\r
13620 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
\r
13622 /******************** Bit definition for LTDC_GCR register ******************/
\r
13624 #define LTDC_GCR_LTDCEN_Pos (0U)
\r
13625 #define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
\r
13626 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
\r
13627 #define LTDC_GCR_DBW_Pos (4U)
\r
13628 #define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
\r
13629 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
\r
13630 #define LTDC_GCR_DGW_Pos (8U)
\r
13631 #define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
\r
13632 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
\r
13633 #define LTDC_GCR_DRW_Pos (12U)
\r
13634 #define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
\r
13635 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
\r
13636 #define LTDC_GCR_DEN_Pos (16U)
\r
13637 #define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
\r
13638 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
\r
13639 #define LTDC_GCR_PCPOL_Pos (28U)
\r
13640 #define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
\r
13641 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
\r
13642 #define LTDC_GCR_DEPOL_Pos (29U)
\r
13643 #define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
\r
13644 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
\r
13645 #define LTDC_GCR_VSPOL_Pos (30U)
\r
13646 #define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
\r
13647 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
\r
13648 #define LTDC_GCR_HSPOL_Pos (31U)
\r
13649 #define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
\r
13650 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
\r
13653 /******************** Bit definition for LTDC_SRCR register *****************/
\r
13655 #define LTDC_SRCR_IMR_Pos (0U)
\r
13656 #define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
\r
13657 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
\r
13658 #define LTDC_SRCR_VBR_Pos (1U)
\r
13659 #define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
\r
13660 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
\r
13662 /******************** Bit definition for LTDC_BCCR register *****************/
\r
13664 #define LTDC_BCCR_BCBLUE_Pos (0U)
\r
13665 #define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
\r
13666 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
\r
13667 #define LTDC_BCCR_BCGREEN_Pos (8U)
\r
13668 #define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
\r
13669 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
\r
13670 #define LTDC_BCCR_BCRED_Pos (16U)
\r
13671 #define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
\r
13672 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
\r
13674 /******************** Bit definition for LTDC_IER register ******************/
\r
13676 #define LTDC_IER_LIE_Pos (0U)
\r
13677 #define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
\r
13678 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
\r
13679 #define LTDC_IER_FUIE_Pos (1U)
\r
13680 #define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
\r
13681 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
\r
13682 #define LTDC_IER_TERRIE_Pos (2U)
\r
13683 #define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
\r
13684 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
\r
13685 #define LTDC_IER_RRIE_Pos (3U)
\r
13686 #define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
\r
13687 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
\r
13689 /******************** Bit definition for LTDC_ISR register ******************/
\r
13691 #define LTDC_ISR_LIF_Pos (0U)
\r
13692 #define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
\r
13693 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
\r
13694 #define LTDC_ISR_FUIF_Pos (1U)
\r
13695 #define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
\r
13696 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
\r
13697 #define LTDC_ISR_TERRIF_Pos (2U)
\r
13698 #define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
\r
13699 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
\r
13700 #define LTDC_ISR_RRIF_Pos (3U)
\r
13701 #define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
\r
13702 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
\r
13704 /******************** Bit definition for LTDC_ICR register ******************/
\r
13706 #define LTDC_ICR_CLIF_Pos (0U)
\r
13707 #define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
\r
13708 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
\r
13709 #define LTDC_ICR_CFUIF_Pos (1U)
\r
13710 #define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
\r
13711 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
\r
13712 #define LTDC_ICR_CTERRIF_Pos (2U)
\r
13713 #define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
\r
13714 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
\r
13715 #define LTDC_ICR_CRRIF_Pos (3U)
\r
13716 #define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
\r
13717 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
\r
13719 /******************** Bit definition for LTDC_LIPCR register ****************/
\r
13721 #define LTDC_LIPCR_LIPOS_Pos (0U)
\r
13722 #define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
\r
13723 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
\r
13725 /******************** Bit definition for LTDC_CPSR register *****************/
\r
13727 #define LTDC_CPSR_CYPOS_Pos (0U)
\r
13728 #define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
\r
13729 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
\r
13730 #define LTDC_CPSR_CXPOS_Pos (16U)
\r
13731 #define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
\r
13732 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
\r
13734 /******************** Bit definition for LTDC_CDSR register *****************/
\r
13736 #define LTDC_CDSR_VDES_Pos (0U)
\r
13737 #define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
\r
13738 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
\r
13739 #define LTDC_CDSR_HDES_Pos (1U)
\r
13740 #define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
\r
13741 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
\r
13742 #define LTDC_CDSR_VSYNCS_Pos (2U)
\r
13743 #define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
\r
13744 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
\r
13745 #define LTDC_CDSR_HSYNCS_Pos (3U)
\r
13746 #define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
\r
13747 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
\r
13749 /******************** Bit definition for LTDC_LxCR register *****************/
\r
13751 #define LTDC_LxCR_LEN_Pos (0U)
\r
13752 #define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
\r
13753 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
\r
13754 #define LTDC_LxCR_COLKEN_Pos (1U)
\r
13755 #define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
\r
13756 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
\r
13757 #define LTDC_LxCR_CLUTEN_Pos (4U)
\r
13758 #define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
\r
13759 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
\r
13761 /******************** Bit definition for LTDC_LxWHPCR register **************/
\r
13763 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
\r
13764 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
\r
13765 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
\r
13766 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
\r
13767 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
\r
13768 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
\r
13770 /******************** Bit definition for LTDC_LxWVPCR register **************/
\r
13772 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
\r
13773 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
\r
13774 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
\r
13775 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
\r
13776 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
\r
13777 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
\r
13779 /******************** Bit definition for LTDC_LxCKCR register ***************/
\r
13781 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
\r
13782 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
\r
13783 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
\r
13784 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
\r
13785 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
\r
13786 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
\r
13787 #define LTDC_LxCKCR_CKRED_Pos (16U)
\r
13788 #define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
\r
13789 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
\r
13791 /******************** Bit definition for LTDC_LxPFCR register ***************/
\r
13793 #define LTDC_LxPFCR_PF_Pos (0U)
\r
13794 #define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
\r
13795 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
\r
13797 /******************** Bit definition for LTDC_LxCACR register ***************/
\r
13799 #define LTDC_LxCACR_CONSTA_Pos (0U)
\r
13800 #define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
\r
13801 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
\r
13803 /******************** Bit definition for LTDC_LxDCCR register ***************/
\r
13805 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
\r
13806 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
\r
13807 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
\r
13808 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
\r
13809 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
\r
13810 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
\r
13811 #define LTDC_LxDCCR_DCRED_Pos (16U)
\r
13812 #define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
\r
13813 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
\r
13814 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
\r
13815 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
\r
13816 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
\r
13818 /******************** Bit definition for LTDC_LxBFCR register ***************/
\r
13820 #define LTDC_LxBFCR_BF2_Pos (0U)
\r
13821 #define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
\r
13822 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
\r
13823 #define LTDC_LxBFCR_BF1_Pos (8U)
\r
13824 #define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
\r
13825 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
\r
13827 /******************** Bit definition for LTDC_LxCFBAR register **************/
\r
13829 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
\r
13830 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
\r
13831 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
\r
13833 /******************** Bit definition for LTDC_LxCFBLR register **************/
\r
13835 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
\r
13836 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
\r
13837 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
\r
13838 #define LTDC_LxCFBLR_CFBP_Pos (16U)
\r
13839 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
\r
13840 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
\r
13842 /******************** Bit definition for LTDC_LxCFBLNR register *************/
\r
13844 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
\r
13845 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
\r
13846 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
\r
13848 /******************** Bit definition for LTDC_LxCLUTWR register *************/
\r
13850 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
\r
13851 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
\r
13852 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
\r
13853 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
\r
13854 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
\r
13855 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
\r
13856 #define LTDC_LxCLUTWR_RED_Pos (16U)
\r
13857 #define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
\r
13858 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
\r
13859 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
\r
13860 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
\r
13861 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
\r
13863 /******************************************************************************/
\r
13867 /******************************************************************************/
\r
13868 /******************** Bit definition for MDMA_GISR0 register ****************/
\r
13869 #define MDMA_GISR0_GIF0_Pos (0U)
\r
13870 #define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */
\r
13871 #define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */
\r
13872 #define MDMA_GISR0_GIF1_Pos (1U)
\r
13873 #define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */
\r
13874 #define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */
\r
13875 #define MDMA_GISR0_GIF2_Pos (2U)
\r
13876 #define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */
\r
13877 #define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */
\r
13878 #define MDMA_GISR0_GIF3_Pos (3U)
\r
13879 #define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */
\r
13880 #define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */
\r
13881 #define MDMA_GISR0_GIF4_Pos (4U)
\r
13882 #define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */
\r
13883 #define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */
\r
13884 #define MDMA_GISR0_GIF5_Pos (5U)
\r
13885 #define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */
\r
13886 #define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */
\r
13887 #define MDMA_GISR0_GIF6_Pos (6U)
\r
13888 #define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */
\r
13889 #define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */
\r
13890 #define MDMA_GISR0_GIF7_Pos (7U)
\r
13891 #define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */
\r
13892 #define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */
\r
13893 #define MDMA_GISR0_GIF8_Pos (8U)
\r
13894 #define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */
\r
13895 #define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */
\r
13896 #define MDMA_GISR0_GIF9_Pos (9U)
\r
13897 #define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */
\r
13898 #define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */
\r
13899 #define MDMA_GISR0_GIF10_Pos (10U)
\r
13900 #define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */
\r
13901 #define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */
\r
13902 #define MDMA_GISR0_GIF11_Pos (11U)
\r
13903 #define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */
\r
13904 #define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */
\r
13905 #define MDMA_GISR0_GIF12_Pos (12U)
\r
13906 #define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */
\r
13907 #define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */
\r
13908 #define MDMA_GISR0_GIF13_Pos (13U)
\r
13909 #define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */
\r
13910 #define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */
\r
13911 #define MDMA_GISR0_GIF14_Pos (14U)
\r
13912 #define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */
\r
13913 #define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */
\r
13914 #define MDMA_GISR0_GIF15_Pos (15U)
\r
13915 #define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */
\r
13916 #define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */
\r
13918 /******************** Bit definition for MDMA_CxISR register ****************/
\r
13919 #define MDMA_CISR_TEIF_Pos (0U)
\r
13920 #define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */
\r
13921 #define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */
\r
13922 #define MDMA_CISR_CTCIF_Pos (1U)
\r
13923 #define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */
\r
13924 #define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */
\r
13925 #define MDMA_CISR_BRTIF_Pos (2U)
\r
13926 #define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */
\r
13927 #define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */
\r
13928 #define MDMA_CISR_BTIF_Pos (3U)
\r
13929 #define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */
\r
13930 #define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */
\r
13931 #define MDMA_CISR_TCIF_Pos (4U)
\r
13932 #define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */
\r
13933 #define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
\r
13934 #define MDMA_CISR_CRQA_Pos (16U)
\r
13935 #define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
\r
13936 #define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
\r
13938 /******************** Bit definition for MDMA_CxIFCR register ****************/
\r
13939 #define MDMA_CIFCR_CTEIF_Pos (0U)
\r
13940 #define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */
\r
13941 #define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */
\r
13942 #define MDMA_CIFCR_CCTCIF_Pos (1U)
\r
13943 #define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */
\r
13944 #define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */
\r
13945 #define MDMA_CIFCR_CBRTIF_Pos (2U)
\r
13946 #define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */
\r
13947 #define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */
\r
13948 #define MDMA_CIFCR_CBTIF_Pos (3U)
\r
13949 #define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */
\r
13950 #define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */
\r
13951 #define MDMA_CIFCR_CLTCIF_Pos (4U)
\r
13952 #define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */
\r
13953 #define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
\r
13955 /******************** Bit definition for MDMA_CxESR register ****************/
\r
13956 #define MDMA_CESR_TEA_Pos (0U)
\r
13957 #define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */
\r
13958 #define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */
\r
13959 #define MDMA_CESR_TED_Pos (7U)
\r
13960 #define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos) /*!< 0x00000080 */
\r
13961 #define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */
\r
13962 #define MDMA_CESR_TELD_Pos (8U)
\r
13963 #define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */
\r
13964 #define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */
\r
13965 #define MDMA_CESR_TEMD_Pos (9U)
\r
13966 #define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */
\r
13967 #define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */
\r
13968 #define MDMA_CESR_ASE_Pos (10U)
\r
13969 #define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */
\r
13970 #define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */
\r
13971 #define MDMA_CESR_BSE_Pos (11U)
\r
13972 #define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */
\r
13973 #define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */
\r
13975 /******************** Bit definition for MDMA_CxCR register ****************/
\r
13976 #define MDMA_CCR_EN_Pos (0U)
\r
13977 #define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos) /*!< 0x00000001 */
\r
13978 #define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */
\r
13979 #define MDMA_CCR_TEIE_Pos (1U)
\r
13980 #define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */
\r
13981 #define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
\r
13982 #define MDMA_CCR_CTCIE_Pos (2U)
\r
13983 #define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */
\r
13984 #define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */
\r
13985 #define MDMA_CCR_BRTIE_Pos (3U)
\r
13986 #define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */
\r
13987 #define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */
\r
13988 #define MDMA_CCR_BTIE_Pos (4U)
\r
13989 #define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */
\r
13990 #define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */
\r
13991 #define MDMA_CCR_TCIE_Pos (5U)
\r
13992 #define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */
\r
13993 #define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */
\r
13994 #define MDMA_CCR_PL_Pos (6U)
\r
13995 #define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */
\r
13996 #define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */
\r
13997 #define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos) /*!< 0x00000040 */
\r
13998 #define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
\r
13999 #define MDMA_CCR_BEX_Pos (12U)
\r
14000 #define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
\r
14001 #define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
\r
14002 #define MDMA_CCR_HEX_Pos (13U)
\r
14003 #define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
\r
14004 #define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
\r
14005 #define MDMA_CCR_WEX_Pos (14U)
\r
14006 #define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
\r
14007 #define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
\r
14008 #define MDMA_CCR_SWRQ_Pos (16U)
\r
14009 #define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
\r
14010 #define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
\r
14012 /******************** Bit definition for MDMA_CxTCR register ****************/
\r
14013 #define MDMA_CTCR_SINC_Pos (0U)
\r
14014 #define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */
\r
14015 #define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */
\r
14016 #define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */
\r
14017 #define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */
\r
14018 #define MDMA_CTCR_DINC_Pos (2U)
\r
14019 #define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */
\r
14020 #define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */
\r
14021 #define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */
\r
14022 #define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */
\r
14023 #define MDMA_CTCR_SSIZE_Pos (4U)
\r
14024 #define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */
\r
14025 #define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */
\r
14026 #define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */
\r
14027 #define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */
\r
14028 #define MDMA_CTCR_DSIZE_Pos (6U)
\r
14029 #define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */
\r
14030 #define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */
\r
14031 #define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */
\r
14032 #define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */
\r
14033 #define MDMA_CTCR_SINCOS_Pos (8U)
\r
14034 #define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */
\r
14035 #define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */
\r
14036 #define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */
\r
14037 #define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */
\r
14038 #define MDMA_CTCR_DINCOS_Pos (10U)
\r
14039 #define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */
\r
14040 #define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */
\r
14041 #define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */
\r
14042 #define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */
\r
14043 #define MDMA_CTCR_SBURST_Pos (12U)
\r
14044 #define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */
\r
14045 #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
\r
14046 #define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
\r
14047 #define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
\r
14048 #define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */
\r
14049 #define MDMA_CTCR_DBURST_Pos (15U)
\r
14050 #define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
\r
14051 #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
\r
14052 #define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */
\r
14053 #define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */
\r
14054 #define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */
\r
14055 #define MDMA_CTCR_TLEN_Pos (18U)
\r
14056 #define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */
\r
14057 #define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
\r
14058 #define MDMA_CTCR_PKE_Pos (25U)
\r
14059 #define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */
\r
14060 #define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
\r
14061 #define MDMA_CTCR_PAM_Pos (26U)
\r
14062 #define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
\r
14063 #define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
\r
14064 #define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
\r
14065 #define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
\r
14066 #define MDMA_CTCR_TRGM_Pos (28U)
\r
14067 #define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */
\r
14068 #define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */
\r
14069 #define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */
\r
14070 #define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */
\r
14071 #define MDMA_CTCR_SWRM_Pos (30U)
\r
14072 #define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */
\r
14073 #define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */
\r
14074 #define MDMA_CTCR_BWM_Pos (31U)
\r
14075 #define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */
\r
14076 #define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */
\r
14078 /******************** Bit definition for MDMA_CxBNDTR register ****************/
\r
14079 #define MDMA_CBNDTR_BNDT_Pos (0U)
\r
14080 #define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */
\r
14081 #define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */
\r
14082 #define MDMA_CBNDTR_BRSUM_Pos (18U)
\r
14083 #define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */
\r
14084 #define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */
\r
14085 #define MDMA_CBNDTR_BRDUM_Pos (19U)
\r
14086 #define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */
\r
14087 #define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */
\r
14088 #define MDMA_CBNDTR_BRC_Pos (20U)
\r
14089 #define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */
\r
14090 #define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */
\r
14092 /******************** Bit definition for MDMA_CxSAR register ****************/
\r
14093 #define MDMA_CSAR_SAR_Pos (0U)
\r
14094 #define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */
\r
14095 #define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */
\r
14097 /******************** Bit definition for MDMA_CxDAR register ****************/
\r
14098 #define MDMA_CDAR_DAR_Pos (0U)
\r
14099 #define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */
\r
14100 #define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */
\r
14102 /******************** Bit definition for MDMA_CxBRUR ************************/
\r
14103 #define MDMA_CBRUR_SUV_Pos (0U)
\r
14104 #define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */
\r
14105 #define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */
\r
14106 #define MDMA_CBRUR_DUV_Pos (16U)
\r
14107 #define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */
\r
14108 #define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */
\r
14110 /******************** Bit definition for MDMA_CxLAR *************************/
\r
14111 #define MDMA_CLAR_LAR_Pos (0U)
\r
14112 #define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */
\r
14113 #define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */
\r
14115 /******************** Bit definition for MDMA_CxTBR) ************************/
\r
14116 #define MDMA_CTBR_TSEL_Pos (0U)
\r
14117 #define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */
\r
14118 #define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */
\r
14119 #define MDMA_CTBR_SBUS_Pos (16U)
\r
14120 #define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */
\r
14121 #define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */
\r
14122 #define MDMA_CTBR_DBUS_Pos (17U)
\r
14123 #define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */
\r
14124 #define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */
\r
14126 /******************** Bit definition for MDMA_CxMAR) ************************/
\r
14127 #define MDMA_CMAR_MAR_Pos (0U)
\r
14128 #define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */
\r
14129 #define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */
\r
14131 /******************** Bit definition for MDMA_CxMDR) ************************/
\r
14132 #define MDMA_CMDR_MDR_Pos (0U)
\r
14133 #define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */
\r
14134 #define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask Data */
\r
14136 /******************************************************************************/
\r
14138 /* Operational Amplifier (OPAMP) */
\r
14140 /******************************************************************************/
\r
14141 /********************* Bit definition for OPAMPx_CSR register ***************/
\r
14142 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
\r
14143 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
\r
14144 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
\r
14145 #define OPAMP_CSR_FORCEVP_Pos (1U)
\r
14146 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
\r
14147 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
\r
14149 #define OPAMP_CSR_VPSEL_Pos (2U)
\r
14150 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
\r
14151 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
\r
14152 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
\r
14153 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
\r
14155 #define OPAMP_CSR_VMSEL_Pos (5U)
\r
14156 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
\r
14157 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
\r
14158 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
\r
14159 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
\r
14161 #define OPAMP_CSR_OPAHSM_Pos (8U)
\r
14162 #define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */
\r
14163 #define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */
\r
14164 #define OPAMP_CSR_CALON_Pos (11U)
\r
14165 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
\r
14166 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
\r
14168 #define OPAMP_CSR_CALSEL_Pos (12U)
\r
14169 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
\r
14170 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
\r
14171 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
\r
14172 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
\r
14174 #define OPAMP_CSR_PGGAIN_Pos (14U)
\r
14175 #define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
\r
14176 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
\r
14177 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
\r
14178 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
\r
14179 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
\r
14180 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
\r
14182 #define OPAMP_CSR_USERTRIM_Pos (18U)
\r
14183 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
\r
14184 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
\r
14185 #define OPAMP_CSR_TSTREF_Pos (29U)
\r
14186 #define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
\r
14187 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
\r
14188 #define OPAMP_CSR_CALOUT_Pos (30U)
\r
14189 #define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */
\r
14190 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */
\r
14192 /********************* Bit definition for OPAMP1_CSR register ***************/
\r
14193 #define OPAMP1_CSR_OPAEN_Pos (0U)
\r
14194 #define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
\r
14195 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
\r
14196 #define OPAMP1_CSR_FORCEVP_Pos (1U)
\r
14197 #define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
\r
14198 #define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
\r
14200 #define OPAMP1_CSR_VPSEL_Pos (2U)
\r
14201 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
\r
14202 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
\r
14203 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
\r
14204 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
\r
14206 #define OPAMP1_CSR_VMSEL_Pos (5U)
\r
14207 #define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
\r
14208 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
\r
14209 #define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
\r
14210 #define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
\r
14212 #define OPAMP1_CSR_OPAHSM_Pos (8U)
\r
14213 #define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */
\r
14214 #define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */
\r
14215 #define OPAMP1_CSR_CALON_Pos (11U)
\r
14216 #define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
\r
14217 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
\r
14219 #define OPAMP1_CSR_CALSEL_Pos (12U)
\r
14220 #define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
\r
14221 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
\r
14222 #define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
\r
14223 #define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
\r
14225 #define OPAMP1_CSR_PGGAIN_Pos (14U)
\r
14226 #define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
\r
14227 #define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
\r
14228 #define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
\r
14229 #define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
\r
14230 #define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
\r
14231 #define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
\r
14233 #define OPAMP1_CSR_USERTRIM_Pos (18U)
\r
14234 #define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
\r
14235 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
\r
14236 #define OPAMP1_CSR_TSTREF_Pos (29U)
\r
14237 #define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
\r
14238 #define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
\r
14239 #define OPAMP1_CSR_CALOUT_Pos (30U)
\r
14240 #define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */
\r
14241 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
\r
14243 /********************* Bit definition for OPAMP2_CSR register ***************/
\r
14244 #define OPAMP2_CSR_OPAEN_Pos (0U)
\r
14245 #define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
\r
14246 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
\r
14247 #define OPAMP2_CSR_FORCEVP_Pos (1U)
\r
14248 #define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
\r
14249 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
\r
14251 #define OPAMP2_CSR_VPSEL_Pos (2U)
\r
14252 #define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
\r
14253 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
\r
14254 #define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
\r
14255 #define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
\r
14257 #define OPAMP2_CSR_VMSEL_Pos (5U)
\r
14258 #define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
\r
14259 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
\r
14260 #define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
\r
14261 #define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
\r
14263 #define OPAMP2_CSR_OPAHSM_Pos (8U)
\r
14264 #define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */
\r
14265 #define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */
\r
14266 #define OPAMP2_CSR_CALON_Pos (11U)
\r
14267 #define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
\r
14268 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
\r
14270 #define OPAMP2_CSR_CALSEL_Pos (12U)
\r
14271 #define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
\r
14272 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
\r
14273 #define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
\r
14274 #define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
\r
14276 #define OPAMP2_CSR_PGGAIN_Pos (14U)
\r
14277 #define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
\r
14278 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
\r
14279 #define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
\r
14280 #define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
\r
14281 #define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
\r
14282 #define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
\r
14284 #define OPAMP2_CSR_USERTRIM_Pos (18U)
\r
14285 #define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
\r
14286 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
\r
14287 #define OPAMP2_CSR_TSTREF_Pos (29U)
\r
14288 #define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
\r
14289 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
\r
14290 #define OPAMP2_CSR_CALOUT_Pos (30U)
\r
14291 #define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */
\r
14292 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
\r
14294 /******************* Bit definition for OPAMP_OTR register ******************/
\r
14295 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
\r
14296 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
\r
14297 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
\r
14298 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
\r
14299 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
\r
14300 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
\r
14302 /******************* Bit definition for OPAMP1_OTR register ******************/
\r
14303 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
\r
14304 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
\r
14305 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
\r
14306 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
\r
14307 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
\r
14308 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
\r
14310 /******************* Bit definition for OPAMP2_OTR register ******************/
\r
14311 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
\r
14312 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
\r
14313 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
\r
14314 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
\r
14315 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
\r
14316 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
\r
14318 /******************* Bit definition for OPAMP_HSOTR register ****************/
\r
14319 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
\r
14320 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
\r
14321 #define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
\r
14322 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
\r
14323 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
\r
14324 #define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
\r
14326 /******************* Bit definition for OPAMP1_HSOTR register ****************/
\r
14327 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
\r
14328 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
\r
14329 #define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
\r
14330 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
\r
14331 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
\r
14332 #define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
\r
14334 /******************* Bit definition for OPAMP2_HSOTR register ****************/
\r
14335 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
\r
14336 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
\r
14337 #define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
\r
14338 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
\r
14339 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
\r
14340 #define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
\r
14342 /******************************************************************************/
\r
14344 /* Power Control */
\r
14346 /******************************************************************************/
\r
14348 /******************** Bit definition for PWR_CR1 register ********************/
\r
14349 #define PWR_CR1_ALS_Pos (17U)
\r
14350 #define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
\r
14351 #define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
\r
14352 #define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00020000 */
\r
14353 #define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00040000 */
\r
14354 #define PWR_CR1_AVDEN_Pos (16U)
\r
14355 #define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */
\r
14356 #define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */
\r
14357 #define PWR_CR1_SVOS_Pos (14U)
\r
14358 #define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */
\r
14359 #define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */
\r
14360 #define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */
\r
14361 #define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */
\r
14362 #define PWR_CR1_FLPS_Pos (9U)
\r
14363 #define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */
\r
14364 #define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in DSTOP */
\r
14365 #define PWR_CR1_DBP_Pos (8U)
\r
14366 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
\r
14367 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
\r
14368 #define PWR_CR1_PLS_Pos (5U)
\r
14369 #define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
\r
14370 #define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */
\r
14371 #define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
\r
14372 #define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
\r
14373 #define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
\r
14374 #define PWR_CR1_PVDEN_Pos (4U)
\r
14375 #define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
\r
14376 #define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable. */
\r
14377 #define PWR_CR1_LPDS_Pos (0U)
\r
14378 #define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
\r
14379 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */
\r
14381 /*!< PVD level configuration */
\r
14382 #define PWR_CR1_PLS_LEV0 (0UL) /*!< PVD level 0 */
\r
14383 #define PWR_CR1_PLS_LEV1_Pos (5U)
\r
14384 #define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
\r
14385 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
\r
14386 #define PWR_CR1_PLS_LEV2_Pos (6U)
\r
14387 #define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
\r
14388 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
\r
14389 #define PWR_CR1_PLS_LEV3_Pos (5U)
\r
14390 #define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
\r
14391 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
\r
14392 #define PWR_CR1_PLS_LEV4_Pos (7U)
\r
14393 #define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
\r
14394 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
\r
14395 #define PWR_CR1_PLS_LEV5_Pos (5U)
\r
14396 #define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
\r
14397 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
\r
14398 #define PWR_CR1_PLS_LEV6_Pos (6U)
\r
14399 #define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
\r
14400 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
\r
14401 #define PWR_CR1_PLS_LEV7_Pos (5U)
\r
14402 #define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
\r
14403 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
\r
14405 /*!< AVD level configuration */
\r
14406 #define PWR_CR1_ALS_LEV0 (0UL) /*!< AVD level 0 */
\r
14407 #define PWR_CR1_ALS_LEV1_Pos (17U)
\r
14408 #define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */
\r
14409 #define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */
\r
14410 #define PWR_CR1_ALS_LEV2_Pos (18U)
\r
14411 #define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */
\r
14412 #define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */
\r
14413 #define PWR_CR1_ALS_LEV3_Pos (17U)
\r
14414 #define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
\r
14415 #define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
\r
14417 /******************** Bit definition for PWR_CSR1 register ********************/
\r
14418 #define PWR_CSR1_AVDO_Pos (16U)
\r
14419 #define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
\r
14420 #define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */
\r
14421 #define PWR_CSR1_ACTVOS_Pos (14U)
\r
14422 #define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x0000C000 */
\r
14423 #define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk /*!< Current actual used VOS for VDD11 Voltage Scaling */
\r
14424 #define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00004000 */
\r
14425 #define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00008000 */
\r
14426 #define PWR_CSR1_ACTVOSRDY_Pos (13U)
\r
14427 #define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos) /*!< 0x00002000 */
\r
14428 #define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */
\r
14429 #define PWR_CSR1_PVDO_Pos (4U)
\r
14430 #define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
\r
14431 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
\r
14433 /******************** Bit definition for PWR_CR2 register ********************/
\r
14434 #define PWR_CR2_TEMPH_Pos (23U)
\r
14435 #define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */
\r
14436 #define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */
\r
14437 #define PWR_CR2_TEMPL_Pos (22U)
\r
14438 #define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos) /*!< 0x00400000 */
\r
14439 #define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level above low threshold */
\r
14440 #define PWR_CR2_VBATH_Pos (21U)
\r
14441 #define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
\r
14442 #define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level above high threshold */
\r
14443 #define PWR_CR2_VBATL_Pos (20U)
\r
14444 #define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
\r
14445 #define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level above low threshold */
\r
14446 #define PWR_CR2_BRRDY_Pos (16U)
\r
14447 #define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
\r
14448 #define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup regulator ready */
\r
14449 #define PWR_CR2_MONEN_Pos (4U)
\r
14450 #define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
\r
14451 #define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
\r
14452 #define PWR_CR2_BREN_Pos (0U)
\r
14453 #define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
\r
14454 #define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
\r
14456 /******************** Bit definition for PWR_CR3 register ********************/
\r
14457 #define PWR_CR3_USB33RDY_Pos (26U)
\r
14458 #define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
\r
14459 #define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */
\r
14460 #define PWR_CR3_USBREGEN_Pos (25U)
\r
14461 #define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos) /*!< 0x02000000 */
\r
14462 #define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk /*!< USB regulator enable */
\r
14463 #define PWR_CR3_USB33DEN_Pos (24U)
\r
14464 #define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
\r
14465 #define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
\r
14466 #define PWR_CR3_SMPSEXTRDY_Pos (16U)
\r
14467 #define PWR_CR3_SMPSEXTRDY_Msk (0x1UL << PWR_CR3_SMPSEXTRDY_Pos) /*!< 0x00010000 */
\r
14468 #define PWR_CR3_SMPSEXTRDY PWR_CR3_SMPSEXTRDY_Msk /*!< SMPS External supply ready */
\r
14469 #define PWR_CR3_VBRS_Pos (9U)
\r
14470 #define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
\r
14471 #define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
\r
14472 #define PWR_CR3_VBE_Pos (8U)
\r
14473 #define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
\r
14474 #define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
\r
14475 #define PWR_CR3_SMPSLEVEL_Pos (4U)
\r
14476 #define PWR_CR3_SMPSLEVEL_Msk (0x3UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000030 */
\r
14477 #define PWR_CR3_SMPSLEVEL PWR_CR3_SMPSLEVEL_Msk /*!< SMPS output Voltage */
\r
14478 #define PWR_CR3_SMPSLEVEL_0 (0x1UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000010 */
\r
14479 #define PWR_CR3_SMPSLEVEL_1 (0x2UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000020 */
\r
14480 #define PWR_CR3_SMPSEXTHP_Pos (3U)
\r
14481 #define PWR_CR3_SMPSEXTHP_Msk (0x1UL << PWR_CR3_SMPSEXTHP_Pos) /*!< 0x00000008 */
\r
14482 #define PWR_CR3_SMPSEXTHP PWR_CR3_SMPSEXTHP_Msk /*!< SMPS forced ON and in High Power MR mode */
\r
14483 #define PWR_CR3_SMPSEN_Pos (2U)
\r
14484 #define PWR_CR3_SMPSEN_Msk (0x1UL << PWR_CR3_SMPSEN_Pos) /*!< 0x00000004 */
\r
14485 #define PWR_CR3_SMPSEN PWR_CR3_SMPSEN_Msk /*!< SMPS Enable */
\r
14486 #define PWR_CR3_LDOEN_Pos (1U)
\r
14487 #define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */
\r
14488 #define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */
\r
14489 #define PWR_CR3_BYPASS_Pos (0U)
\r
14490 #define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */
\r
14491 #define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */
\r
14493 /******************** Bit definition for PWR_CPUCR register ********************/
\r
14494 #define PWR_CPUCR_RUN_D3_Pos (11U)
\r
14495 #define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */
\r
14496 #define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
\r
14497 #define PWR_CPUCR_HOLD2_Pos (10U)
\r
14498 #define PWR_CPUCR_HOLD2_Msk (0x1UL << PWR_CPUCR_HOLD2_Pos) /*!< 0x00000400 */
\r
14499 #define PWR_CPUCR_HOLD2 PWR_CPUCR_HOLD2_Msk /*!< Hold the CPU2 and allocated peripherals when exiting STOP mode */
\r
14500 #define PWR_CPUCR_CSSF_Pos (9U)
\r
14501 #define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000200 */
\r
14502 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
\r
14503 #define PWR_CPUCR_SBF_D2_Pos (8U)
\r
14504 #define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos) /*!< 0x00000100 */
\r
14505 #define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk /*!< D2 domain DSTANDBY Flag */
\r
14506 #define PWR_CPUCR_SBF_D1_Pos (7U)
\r
14507 #define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos) /*!< 0x00000080 */
\r
14508 #define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk /*!< D1 domain DSTANDBY Flag */
\r
14509 #define PWR_CPUCR_SBF_Pos (6U)
\r
14510 #define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000040 */
\r
14511 #define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System STANDBY Flag */
\r
14512 #define PWR_CPUCR_STOPF_Pos (5U)
\r
14513 #define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000020 */
\r
14514 #define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP Flag */
\r
14515 #define PWR_CPUCR_HOLD2F_Pos (4U)
\r
14516 #define PWR_CPUCR_HOLD2F_Msk (0x1UL << PWR_CPUCR_HOLD2F_Pos) /*!< 0x00000010 */
\r
14517 #define PWR_CPUCR_HOLD2F PWR_CPUCR_HOLD2F_Msk /*!< CPU2 in hold wakeup flag */
\r
14518 #define PWR_CPUCR_PDDS_D3_Pos (2U)
\r
14519 #define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos) /*!< 0x00000004 */
\r
14520 #define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk /*!< System D3 domain Power Down Deepsleep */
\r
14521 #define PWR_CPUCR_PDDS_D2_Pos (1U)
\r
14522 #define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos) /*!< 0x00000002 */
\r
14523 #define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk /*!< D2 domain Power Down Deepsleep */
\r
14524 #define PWR_CPUCR_PDDS_D1_Pos (0U)
\r
14525 #define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos) /*!< 0x00000001 */
\r
14526 #define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
\r
14528 /******************** Bit definition for PWR_CPU2CR register ********************/
\r
14529 #define PWR_CPU2CR_RUN_D3_Pos (11U)
\r
14530 #define PWR_CPU2CR_RUN_D3_Msk (0x1UL << PWR_CPU2CR_RUN_D3_Pos) /*!< 0x00000800 */
\r
14531 #define PWR_CPU2CR_RUN_D3 PWR_CPU2CR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
\r
14532 #define PWR_CPU2CR_HOLD1_Pos (10U)
\r
14533 #define PWR_CPU2CR_HOLD1_Msk (0x1UL << PWR_CPU2CR_HOLD1_Pos) /*!< 0x00000400 */
\r
14534 #define PWR_CPU2CR_HOLD1 PWR_CPU2CR_HOLD1_Msk /*!< Hold the CPU1 and allocated peripherals when exiting STOP mode */
\r
14535 #define PWR_CPU2CR_CSSF_Pos (9U)
\r
14536 #define PWR_CPU2CR_CSSF_Msk (0x1UL << PWR_CPU2CR_CSSF_Pos) /*!< 0x00000200 */
\r
14537 #define PWR_CPU2CR_CSSF PWR_CPU2CR_CSSF_Msk /*!< Clear D2 domain CPU2 STANDBY, STOP and HOLD flags */
\r
14538 #define PWR_CPU2CR_SBF_D2_Pos (8U)
\r
14539 #define PWR_CPU2CR_SBF_D2_Msk (0x1UL << PWR_CPU2CR_SBF_D2_Pos) /*!< 0x00000100 */
\r
14540 #define PWR_CPU2CR_SBF_D2 PWR_CPU2CR_SBF_D2_Msk /*!< D2 domain DSTANDBY Flag */
\r
14541 #define PWR_CPU2CR_SBF_D1_Pos (7U)
\r
14542 #define PWR_CPU2CR_SBF_D1_Msk (0x1UL << PWR_CPU2CR_SBF_D1_Pos) /*!< 0x00000080 */
\r
14543 #define PWR_CPU2CR_SBF_D1 PWR_CPU2CR_SBF_D1_Msk /*!< D1 domain DSTANDBY Flag */
\r
14544 #define PWR_CPU2CR_SBF_Pos (6U)
\r
14545 #define PWR_CPU2CR_SBF_Msk (0x1UL << PWR_CPU2CR_SBF_Pos) /*!< 0x00000040 */
\r
14546 #define PWR_CPU2CR_SBF PWR_CPU2CR_SBF_Msk /*!< System STANDBY Flag */
\r
14547 #define PWR_CPU2CR_STOPF_Pos (5U)
\r
14548 #define PWR_CPU2CR_STOPF_Msk (0x1UL << PWR_CPU2CR_STOPF_Pos) /*!< 0x00000020 */
\r
14549 #define PWR_CPU2CR_STOPF PWR_CPU2CR_STOPF_Msk /*!< STOP Flag */
\r
14550 #define PWR_CPU2CR_HOLD1F_Pos (4U)
\r
14551 #define PWR_CPU2CR_HOLD1F_Msk (0x1UL << PWR_CPU2CR_HOLD1F_Pos) /*!< 0x00000010 */
\r
14552 #define PWR_CPU2CR_HOLD1F PWR_CPU2CR_HOLD1F_Msk /*!< CPU1 in hold wakeup flag */
\r
14553 #define PWR_CPU2CR_PDDS_D3_Pos (2U)
\r
14554 #define PWR_CPU2CR_PDDS_D3_Msk (0x1UL << PWR_CPU2CR_PDDS_D3_Pos) /*!< 0x00000004 */
\r
14555 #define PWR_CPU2CR_PDDS_D3 PWR_CPU2CR_PDDS_D3_Msk /*!< System D3 domain Power Down Deepsleep */
\r
14556 #define PWR_CPU2CR_PDDS_D2_Pos (1U)
\r
14557 #define PWR_CPU2CR_PDDS_D2_Msk (0x1UL << PWR_CPU2CR_PDDS_D2_Pos) /*!< 0x00000002 */
\r
14558 #define PWR_CPU2CR_PDDS_D2 PWR_CPU2CR_PDDS_D2_Msk /*!< D2 domain Power Down Deepsleep */
\r
14559 #define PWR_CPU2CR_PDDS_D1_Pos (0U)
\r
14560 #define PWR_CPU2CR_PDDS_D1_Msk (0x1UL << PWR_CPU2CR_PDDS_D1_Pos) /*!< 0x00000001 */
\r
14561 #define PWR_CPU2CR_PDDS_D1 PWR_CPU2CR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
\r
14563 /******************** Bit definition for PWR_D3CR register ********************/
\r
14564 #define PWR_D3CR_VOS_Pos (14U)
\r
14565 #define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos) /*!< 0x0000C000 */
\r
14566 #define PWR_D3CR_VOS PWR_D3CR_VOS_Msk /*!< Voltage Scaling selection according performance */
\r
14567 #define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos) /*!< 0x00004000 */
\r
14568 #define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos) /*!< 0x00008000 */
\r
14569 #define PWR_D3CR_VOSRDY_Pos (13U)
\r
14570 #define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos) /*!< 0x00002000 */
\r
14571 #define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
\r
14573 /******************** Bit definition for PWR_WKUPCR register ********************/
\r
14574 #define PWR_WKUPCR_WKUPC6_Pos (5U)
\r
14575 #define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
\r
14576 #define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
\r
14577 #define PWR_WKUPCR_WKUPC5_Pos (4U)
\r
14578 #define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */
\r
14579 #define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */
\r
14580 #define PWR_WKUPCR_WKUPC4_Pos (3U)
\r
14581 #define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
\r
14582 #define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */
\r
14583 #define PWR_WKUPCR_WKUPC3_Pos (2U)
\r
14584 #define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
\r
14585 #define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */
\r
14586 #define PWR_WKUPCR_WKUPC2_Pos (1U)
\r
14587 #define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
\r
14588 #define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */
\r
14589 #define PWR_WKUPCR_WKUPC1_Pos (0U)
\r
14590 #define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
\r
14591 #define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
\r
14593 /******************** Bit definition for PWR_WKUPFR register ********************/
\r
14594 #define PWR_WKUPFR_WKUPF6_Pos (5U)
\r
14595 #define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
\r
14596 #define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
\r
14597 #define PWR_WKUPFR_WKUPF5_Pos (4U)
\r
14598 #define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */
\r
14599 #define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */
\r
14600 #define PWR_WKUPFR_WKUPF4_Pos (3U)
\r
14601 #define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */
\r
14602 #define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */
\r
14603 #define PWR_WKUPFR_WKUPF3_Pos (2U)
\r
14604 #define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */
\r
14605 #define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */
\r
14606 #define PWR_WKUPFR_WKUPF2_Pos (1U)
\r
14607 #define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */
\r
14608 #define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */
\r
14609 #define PWR_WKUPFR_WKUPF1_Pos (0U)
\r
14610 #define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
\r
14611 #define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
\r
14613 /******************** Bit definition for PWR_WKUPEPR register ********************/
\r
14614 #define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
\r
14615 #define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
\r
14616 #define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
\r
14617 #define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x04000000 */
\r
14618 #define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x08000000 */
\r
14619 #define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
\r
14620 #define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x03000000 */
\r
14621 #define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */
\r
14622 #define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x01000000 */
\r
14623 #define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x02000000 */
\r
14624 #define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
\r
14625 #define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
\r
14626 #define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */
\r
14627 #define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */
\r
14628 #define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */
\r
14629 #define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
\r
14630 #define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */
\r
14631 #define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */
\r
14632 #define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */
\r
14633 #define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */
\r
14634 #define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
\r
14635 #define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
\r
14636 #define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */
\r
14637 #define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */
\r
14638 #define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */
\r
14639 #define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
\r
14640 #define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */
\r
14641 #define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */
\r
14642 #define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */
\r
14643 #define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */
\r
14644 #define PWR_WKUPEPR_WKUPP6_Pos (13U)
\r
14645 #define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos) /*!< 0x00002000 */
\r
14646 #define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk /*!< Wakeup Pin Polarity for WKUP6 */
\r
14647 #define PWR_WKUPEPR_WKUPP5_Pos (12U)
\r
14648 #define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos) /*!< 0x00001000 */
\r
14649 #define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk /*!< Wakeup Pin Polarity for WKUP5 */
\r
14650 #define PWR_WKUPEPR_WKUPP4_Pos (11U)
\r
14651 #define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */
\r
14652 #define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */
\r
14653 #define PWR_WKUPEPR_WKUPP3_Pos (10U)
\r
14654 #define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */
\r
14655 #define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */
\r
14656 #define PWR_WKUPEPR_WKUPP2_Pos (9U)
\r
14657 #define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */
\r
14658 #define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */
\r
14659 #define PWR_WKUPEPR_WKUPP1_Pos (8U)
\r
14660 #define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */
\r
14661 #define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */
\r
14662 #define PWR_WKUPEPR_WKUPEN6_Pos (5U)
\r
14663 #define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos) /*!< 0x00000020 */
\r
14664 #define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk /*!< Enable Wakeup Pin WKUP6 */
\r
14665 #define PWR_WKUPEPR_WKUPEN5_Pos (4U)
\r
14666 #define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos) /*!< 0x00000010 */
\r
14667 #define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk /*!< Enable Wakeup Pin WKUP5 */
\r
14668 #define PWR_WKUPEPR_WKUPEN4_Pos (3U)
\r
14669 #define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */
\r
14670 #define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */
\r
14671 #define PWR_WKUPEPR_WKUPEN3_Pos (2U)
\r
14672 #define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */
\r
14673 #define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */
\r
14674 #define PWR_WKUPEPR_WKUPEN2_Pos (1U)
\r
14675 #define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */
\r
14676 #define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */
\r
14677 #define PWR_WKUPEPR_WKUPEN1_Pos (0U)
\r
14678 #define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */
\r
14679 #define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */
\r
14680 #define PWR_WKUPEPR_WKUPEN_Pos (0U)
\r
14681 #define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */
\r
14682 #define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */
\r
14684 /******************************************************************************/
\r
14686 /* Reset and Clock Control */
\r
14688 /******************************************************************************/
\r
14689 /******************** Bit definition for RCC_CR register ********************/
\r
14690 #define RCC_CR_HSION_Pos (0U)
\r
14691 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
\r
14692 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
\r
14693 #define RCC_CR_HSIKERON_Pos (1U)
\r
14694 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
\r
14695 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
\r
14696 #define RCC_CR_HSIRDY_Pos (2U)
\r
14697 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
\r
14698 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
\r
14699 #define RCC_CR_HSIDIV_Pos (3U)
\r
14700 #define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
\r
14701 #define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */
\r
14702 #define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000000 */
\r
14703 #define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */
\r
14704 #define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */
\r
14705 #define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
\r
14707 #define RCC_CR_HSIDIVF_Pos (5U)
\r
14708 #define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */
\r
14709 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */
\r
14710 #define RCC_CR_CSION_Pos (7U)
\r
14711 #define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */
\r
14712 #define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */
\r
14713 #define RCC_CR_CSIRDY_Pos (8U)
\r
14714 #define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */
\r
14715 #define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */
\r
14716 #define RCC_CR_CSIKERON_Pos (9U)
\r
14717 #define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */
\r
14718 #define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
\r
14719 #define RCC_CR_HSI48ON_Pos (12U)
\r
14720 #define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */
\r
14721 #define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */
\r
14722 #define RCC_CR_HSI48RDY_Pos (13U)
\r
14723 #define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */
\r
14724 #define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready */
\r
14726 #define RCC_CR_D1CKRDY_Pos (14U)
\r
14727 #define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos) /*!< 0x00004000 */
\r
14728 #define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk /*!< D1 domain clocks ready flag */
\r
14729 #define RCC_CR_D2CKRDY_Pos (15U)
\r
14730 #define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos) /*!< 0x00008000 */
\r
14731 #define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk /*!< D2 domain clocks ready flag */
\r
14733 #define RCC_CR_HSEON_Pos (16U)
\r
14734 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
\r
14735 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
\r
14736 #define RCC_CR_HSERDY_Pos (17U)
\r
14737 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
\r
14738 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
\r
14739 #define RCC_CR_HSEBYP_Pos (18U)
\r
14740 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
\r
14741 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
\r
14742 #define RCC_CR_CSSHSEON_Pos (19U)
\r
14743 #define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
\r
14744 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock security System enable */
\r
14747 #define RCC_CR_PLL1ON_Pos (24U)
\r
14748 #define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */
\r
14749 #define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */
\r
14750 #define RCC_CR_PLL1RDY_Pos (25U)
\r
14751 #define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */
\r
14752 #define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */
\r
14753 #define RCC_CR_PLL2ON_Pos (26U)
\r
14754 #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
\r
14755 #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */
\r
14756 #define RCC_CR_PLL2RDY_Pos (27U)
\r
14757 #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
\r
14758 #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready */
\r
14759 #define RCC_CR_PLL3ON_Pos (28U)
\r
14760 #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
\r
14761 #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */
\r
14762 #define RCC_CR_PLL3RDY_Pos (29U)
\r
14763 #define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
\r
14764 #define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready */
\r
14767 #define RCC_CR_PLLON_Pos (24U)
\r
14768 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
\r
14769 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
\r
14770 #define RCC_CR_PLLRDY_Pos (25U)
\r
14771 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
\r
14772 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
\r
14774 /******************** Bit definition for RCC_HSICFGR register ***************/
\r
14775 /*!< HSICAL configuration */
\r
14776 #define RCC_HSICFGR_HSICAL_Pos (0U)
\r
14777 #define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
\r
14778 #define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */
\r
14779 #define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
\r
14780 #define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
\r
14781 #define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
\r
14782 #define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
\r
14783 #define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
\r
14784 #define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
\r
14785 #define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
\r
14786 #define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
\r
14787 #define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
\r
14788 #define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
\r
14789 #define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
\r
14790 #define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
\r
14792 /*!< HSITRIM configuration */
\r
14793 #define RCC_HSICFGR_HSITRIM_Pos (24U)
\r
14794 #define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
\r
14795 #define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
\r
14796 #define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
\r
14797 #define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
\r
14798 #define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
\r
14799 #define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
\r
14800 #define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
\r
14801 #define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
\r
14802 #define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
\r
14805 /******************** Bit definition for RCC_CRRCR register *****************/
\r
14807 /*!< HSI48CAL configuration */
\r
14808 #define RCC_CRRCR_HSI48CAL_Pos (0U)
\r
14809 #define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
\r
14810 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */
\r
14811 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
\r
14812 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
\r
14813 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
\r
14814 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
\r
14815 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
\r
14816 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
\r
14817 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
\r
14818 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
\r
14819 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
\r
14820 #define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
\r
14823 /******************** Bit definition for RCC_CSICFGR register *****************/
\r
14824 /*!< CSICAL configuration */
\r
14825 #define RCC_CSICFGR_CSICAL_Pos (0U)
\r
14826 #define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
\r
14827 #define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */
\r
14828 #define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
\r
14829 #define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
\r
14830 #define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
\r
14831 #define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
\r
14832 #define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
\r
14833 #define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
\r
14834 #define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
\r
14835 #define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
\r
14837 /*!< CSITRIM configuration */
\r
14838 #define RCC_CSICFGR_CSITRIM_Pos (24U)
\r
14839 #define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
\r
14840 #define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */
\r
14841 #define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
\r
14842 #define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
\r
14843 #define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
\r
14844 #define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
\r
14845 #define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
\r
14846 #define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
\r
14848 /******************** Bit definition for RCC_CFGR register ******************/
\r
14849 /*!< SW configuration */
\r
14850 #define RCC_CFGR_SW_Pos (0U)
\r
14851 #define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
\r
14852 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
\r
14853 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
\r
14854 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
\r
14855 #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
\r
14857 #define RCC_CFGR_SW_HSI (0x00000000UL) /*!< HSI selection as system clock */
\r
14858 #define RCC_CFGR_SW_CSI (0x00000001UL) /*!< CSI selection as system clock */
\r
14859 #define RCC_CFGR_SW_HSE (0x00000002UL) /*!< HSE selection as system clock */
\r
14860 #define RCC_CFGR_SW_PLL1 (0x00000003UL) /*!< PLL1 selection as system clock */
\r
14862 /*!< SWS configuration */
\r
14863 #define RCC_CFGR_SWS_Pos (3U)
\r
14864 #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
\r
14865 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
\r
14866 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
\r
14867 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
\r
14868 #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
\r
14870 #define RCC_CFGR_SWS_HSI (0x00000000UL) /*!< HSI used as system clock */
\r
14871 #define RCC_CFGR_SWS_CSI (0x00000008UL) /*!< CSI used as system clock */
\r
14872 #define RCC_CFGR_SWS_HSE (0x00000010UL) /*!< HSE used as system clock */
\r
14873 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used as system clock */
\r
14875 #define RCC_CFGR_STOPWUCK_Pos (6U)
\r
14876 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */
\r
14877 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
\r
14879 #define RCC_CFGR_STOPKERWUCK_Pos (7U)
\r
14880 #define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */
\r
14881 #define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from STOP */
\r
14883 /*!< RTCPRE configuration */
\r
14884 #define RCC_CFGR_RTCPRE_Pos (8U)
\r
14885 #define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
\r
14886 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< 0x00003F00 */
\r
14887 #define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */
\r
14888 #define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */
\r
14889 #define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */
\r
14890 #define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */
\r
14891 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */
\r
14892 #define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */
\r
14894 /*!< HRTIMSEL configuration */
\r
14895 #define RCC_CFGR_HRTIMSEL_Pos (14U)
\r
14896 #define RCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
\r
14897 #define RCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk /*!< 0x00004000 */
\r
14899 /*!< TIMPRE configuration */
\r
14900 #define RCC_CFGR_TIMPRE_Pos (15U)
\r
14901 #define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
\r
14902 #define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< 0x00008000 */
\r
14904 /*!< MCO1 configuration */
\r
14905 #define RCC_CFGR_MCO1_Pos (22U)
\r
14906 #define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
\r
14907 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk /*!< 0x01C00000 */
\r
14908 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
\r
14909 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00800000 */
\r
14910 #define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos) /*!< 0x01000000 */
\r
14912 #define RCC_CFGR_MCO1PRE_Pos (18U)
\r
14913 #define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
\r
14914 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< 0x003C0000 */
\r
14915 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */
\r
14916 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */
\r
14917 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */
\r
14918 #define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */
\r
14920 #define RCC_CFGR_MCO2PRE_Pos (25U)
\r
14921 #define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
\r
14922 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< 0x1E000000 */
\r
14923 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */
\r
14924 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */
\r
14925 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
\r
14926 #define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
\r
14928 #define RCC_CFGR_MCO2_Pos (29U)
\r
14929 #define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
\r
14930 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk /*!< 0xE0000000 */
\r
14931 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x20000000 */
\r
14932 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
\r
14933 #define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
\r
14935 /******************** Bit definition for RCC_D1CFGR register ******************/
\r
14936 /*!< D1HPRE configuration */
\r
14937 #define RCC_D1CFGR_HPRE_Pos (0U)
\r
14938 #define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos) /*!< 0x0000000F */
\r
14939 #define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB3 prescaler) */
\r
14940 #define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000001 */
\r
14941 #define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000002 */
\r
14942 #define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000004 */
\r
14943 #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
\r
14946 #define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
\r
14947 #define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
\r
14948 #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
\r
14949 #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
\r
14950 #define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
\r
14951 #define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
\r
14952 #define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk /*!< AHB3 Clock divided by 4 */
\r
14953 #define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
\r
14954 #define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
\r
14955 #define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk /*!< AHB3 Clock divided by 8 */
\r
14956 #define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
\r
14957 #define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
\r
14958 #define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk /*!< AHB3 Clock divided by 16 */
\r
14959 #define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
\r
14960 #define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
\r
14961 #define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk /*!< AHB3 Clock divided by 64 */
\r
14962 #define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
\r
14963 #define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
\r
14964 #define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk /*!< AHB3 Clock divided by 128 */
\r
14965 #define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
\r
14966 #define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
\r
14967 #define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk /*!< AHB3 Clock divided by 256 */
\r
14968 #define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
\r
14969 #define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
\r
14970 #define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk /*!< AHB3 Clock divided by 512 */
\r
14972 /*!< D1PPRE configuration */
\r
14973 #define RCC_D1CFGR_D1PPRE_Pos (4U)
\r
14974 #define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
\r
14975 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits (APB3 prescaler) */
\r
14976 #define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
\r
14977 #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
\r
14978 #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
\r
14980 #define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
\r
14981 #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
\r
14982 #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
\r
14983 #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
\r
14984 #define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
\r
14985 #define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
\r
14986 #define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk /*!< APB3 clock divided by 4 */
\r
14987 #define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
\r
14988 #define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
\r
14989 #define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk /*!< APB3 clock divided by 8 */
\r
14990 #define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
\r
14991 #define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
\r
14992 #define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk /*!< APB3 clock divided by 16 */
\r
14994 #define RCC_D1CFGR_D1CPRE_Pos (8U)
\r
14995 #define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
\r
14996 #define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
\r
14997 #define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
\r
14998 #define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
\r
14999 #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
\r
15000 #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
\r
15002 #define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
\r
15003 #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
\r
15004 #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
\r
15005 #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
\r
15006 #define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
\r
15007 #define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
\r
15008 #define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk /*!< Domain 1 Core clock divided by 4 */
\r
15009 #define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
\r
15010 #define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
\r
15011 #define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk /*!< Domain 1 Core clock divided by 8 */
\r
15012 #define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
\r
15013 #define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
\r
15014 #define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk /*!< Domain 1 Core clock divided by 16 */
\r
15015 #define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
\r
15016 #define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
\r
15017 #define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk /*!< Domain 1 Core clock divided by 64 */
\r
15018 #define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
\r
15019 #define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
\r
15020 #define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk /*!< Domain 1 Core clock divided by 128 */
\r
15021 #define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
\r
15022 #define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
\r
15023 #define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk /*!< Domain 1 Core clock divided by 256 */
\r
15024 #define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
\r
15025 #define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
\r
15026 #define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk /*!< Domain 1 Core clock divided by 512 */
\r
15028 /******************** Bit definition for RCC_D2CFGR register ******************/
\r
15029 /*!< D2PPRE1 configuration */
\r
15030 #define RCC_D2CFGR_D2PPRE1_Pos (4U)
\r
15031 #define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
\r
15032 #define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
\r
15033 #define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
\r
15034 #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
\r
15035 #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
\r
15037 #define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
\r
15038 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
\r
15039 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
\r
15040 #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
\r
15041 #define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
\r
15042 #define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
\r
15043 #define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk /*!< APB1 clock divided by 4 */
\r
15044 #define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
\r
15045 #define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
\r
15046 #define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk /*!< APB1 clock divided by 8 */
\r
15047 #define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
\r
15048 #define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
\r
15049 #define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk /*!< APB1 clock divided by 16 */
\r
15051 /*!< D2PPRE2 configuration */
\r
15052 #define RCC_D2CFGR_D2PPRE2_Pos (8U)
\r
15053 #define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
\r
15054 #define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
\r
15055 #define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
\r
15056 #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
\r
15057 #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
\r
15059 #define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
\r
15060 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
\r
15061 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
\r
15062 #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
\r
15063 #define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
\r
15064 #define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
\r
15065 #define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk /*!< APB2 clock divided by 4 */
\r
15066 #define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
\r
15067 #define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
\r
15068 #define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk /*!< APB2 clock divided by 8 */
\r
15069 #define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
\r
15070 #define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
\r
15071 #define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk /*!< APB2 clock divided by 16 */
\r
15073 /******************** Bit definition for RCC_D3CFGR register ******************/
\r
15074 /*!< D3PPRE configuration */
\r
15075 #define RCC_D3CFGR_D3PPRE_Pos (4U)
\r
15076 #define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
\r
15077 #define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
\r
15078 #define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
\r
15079 #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
\r
15080 #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
\r
15082 #define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
\r
15083 #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
\r
15084 #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
\r
15085 #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
\r
15086 #define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
\r
15087 #define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
\r
15088 #define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk /*!< APB4 clock divided by 4 */
\r
15089 #define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
\r
15090 #define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
\r
15091 #define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk /*!< APB4 clock divided by 8 */
\r
15092 #define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
\r
15093 #define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
\r
15094 #define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk /*!< APB4 clock divided by 16 */
\r
15096 /******************** Bit definition for RCC_PLLCKSELR register *************/
\r
15098 #define RCC_PLLCKSELR_PLLSRC_Pos (0U)
\r
15099 #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
\r
15100 #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
\r
15102 #define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
\r
15103 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
\r
15104 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
\r
15105 #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
\r
15106 #define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
\r
15107 #define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
\r
15108 #define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
\r
15109 #define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
\r
15110 #define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
\r
15111 #define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk /*!< No source clock selected */
\r
15113 #define RCC_PLLCKSELR_DIVM1_Pos (4U)
\r
15114 #define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
\r
15115 #define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
\r
15116 #define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
\r
15117 #define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
\r
15118 #define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
\r
15119 #define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
\r
15120 #define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
\r
15121 #define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
\r
15123 #define RCC_PLLCKSELR_DIVM2_Pos (12U)
\r
15124 #define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
\r
15125 #define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
\r
15126 #define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
\r
15127 #define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
\r
15128 #define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
\r
15129 #define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
\r
15130 #define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
\r
15131 #define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
\r
15133 #define RCC_PLLCKSELR_DIVM3_Pos (20U)
\r
15134 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
\r
15135 #define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
\r
15136 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
\r
15137 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
\r
15138 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
\r
15139 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
\r
15140 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
\r
15141 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
\r
15143 /******************** Bit definition for RCC_PLLCFGR register ***************/
\r
15145 #define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
\r
15146 #define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
\r
15147 #define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
\r
15148 #define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
\r
15149 #define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
\r
15150 #define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
\r
15151 #define RCC_PLLCFGR_PLL1RGE_Pos (2U)
\r
15152 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
\r
15153 #define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
\r
15154 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
\r
15155 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
\r
15156 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
\r
15157 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
\r
15159 #define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
\r
15160 #define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
\r
15161 #define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
\r
15162 #define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
\r
15163 #define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
\r
15164 #define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
\r
15165 #define RCC_PLLCFGR_PLL2RGE_Pos (6U)
\r
15166 #define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
\r
15167 #define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
\r
15168 #define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
\r
15169 #define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
\r
15170 #define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
\r
15171 #define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
\r
15173 #define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
\r
15174 #define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
\r
15175 #define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
\r
15176 #define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
\r
15177 #define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
\r
15178 #define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
\r
15179 #define RCC_PLLCFGR_PLL3RGE_Pos (10U)
\r
15180 #define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
\r
15181 #define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
\r
15182 #define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
\r
15183 #define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
\r
15184 #define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
\r
15185 #define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
\r
15187 #define RCC_PLLCFGR_DIVP1EN_Pos (16U)
\r
15188 #define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
\r
15189 #define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
\r
15190 #define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
\r
15191 #define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
\r
15192 #define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
\r
15193 #define RCC_PLLCFGR_DIVR1EN_Pos (18U)
\r
15194 #define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
\r
15195 #define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
\r
15197 #define RCC_PLLCFGR_DIVP2EN_Pos (19U)
\r
15198 #define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
\r
15199 #define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
\r
15200 #define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
\r
15201 #define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
\r
15202 #define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
\r
15203 #define RCC_PLLCFGR_DIVR2EN_Pos (21U)
\r
15204 #define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
\r
15205 #define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
\r
15207 #define RCC_PLLCFGR_DIVP3EN_Pos (22U)
\r
15208 #define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
\r
15209 #define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
\r
15210 #define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
\r
15211 #define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
\r
15212 #define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
\r
15213 #define RCC_PLLCFGR_DIVR3EN_Pos (24U)
\r
15214 #define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
\r
15215 #define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
\r
15218 /******************** Bit definition for RCC_PLL1DIVR register ***************/
\r
15219 #define RCC_PLL1DIVR_N1_Pos (0U)
\r
15220 #define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
\r
15221 #define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
\r
15222 #define RCC_PLL1DIVR_P1_Pos (9U)
\r
15223 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
\r
15224 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
\r
15225 #define RCC_PLL1DIVR_Q1_Pos (16U)
\r
15226 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
\r
15227 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
\r
15228 #define RCC_PLL1DIVR_R1_Pos (24U)
\r
15229 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
\r
15230 #define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
\r
15232 /******************** Bit definition for RCC_PLL1FRACR register ***************/
\r
15233 #define RCC_PLL1FRACR_FRACN1_Pos (3U)
\r
15234 #define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
\r
15235 #define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
\r
15237 /******************** Bit definition for RCC_PLL2DIVR register ***************/
\r
15238 #define RCC_PLL2DIVR_N2_Pos (0U)
\r
15239 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
\r
15240 #define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
\r
15241 #define RCC_PLL2DIVR_P2_Pos (9U)
\r
15242 #define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
\r
15243 #define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
\r
15244 #define RCC_PLL2DIVR_Q2_Pos (16U)
\r
15245 #define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
\r
15246 #define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
\r
15247 #define RCC_PLL2DIVR_R2_Pos (24U)
\r
15248 #define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
\r
15249 #define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
\r
15251 /******************** Bit definition for RCC_PLL2FRACR register ***************/
\r
15252 #define RCC_PLL2FRACR_FRACN2_Pos (3U)
\r
15253 #define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
\r
15254 #define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
\r
15256 /******************** Bit definition for RCC_PLL3DIVR register ***************/
\r
15257 #define RCC_PLL3DIVR_N3_Pos (0U)
\r
15258 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
\r
15259 #define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
\r
15260 #define RCC_PLL3DIVR_P3_Pos (9U)
\r
15261 #define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
\r
15262 #define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
\r
15263 #define RCC_PLL3DIVR_Q3_Pos (16U)
\r
15264 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
\r
15265 #define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
\r
15266 #define RCC_PLL3DIVR_R3_Pos (24U)
\r
15267 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
\r
15268 #define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
\r
15270 /******************** Bit definition for RCC_PLL3FRACR register ***************/
\r
15271 #define RCC_PLL3FRACR_FRACN3_Pos (3U)
\r
15272 #define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
\r
15273 #define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
\r
15275 /******************** Bit definition for RCC_D1CCIPR register ***************/
\r
15276 #define RCC_D1CCIPR_FMCSEL_Pos (0U)
\r
15277 #define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
\r
15278 #define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
\r
15279 #define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
\r
15280 #define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
\r
15281 #define RCC_D1CCIPR_QSPISEL_Pos (4U)
\r
15282 #define RCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
\r
15283 #define RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk
\r
15284 #define RCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
\r
15285 #define RCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
\r
15286 #define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
\r
15287 #define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
\r
15288 #define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
\r
15289 #define RCC_D1CCIPR_CKPERSEL_Pos (28U)
\r
15290 #define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
\r
15291 #define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
\r
15292 #define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
\r
15293 #define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
\r
15295 /******************** Bit definition for RCC_D2CCIP1R register ***************/
\r
15296 #define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
\r
15297 #define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
\r
15298 #define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
\r
15299 #define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
\r
15300 #define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
\r
15301 #define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
\r
15303 #define RCC_D2CCIP1R_SAI23SEL_Pos (6U)
\r
15304 #define RCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
\r
15305 #define RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk
\r
15306 #define RCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
\r
15307 #define RCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
\r
15308 #define RCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
\r
15310 #define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
\r
15311 #define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
\r
15312 #define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
\r
15313 #define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
\r
15314 #define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
\r
15315 #define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
\r
15317 #define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
\r
15318 #define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
\r
15319 #define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
\r
15320 #define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
\r
15321 #define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
\r
15322 #define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
\r
15324 #define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
\r
15325 #define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
\r
15326 #define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
\r
15327 #define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
\r
15328 #define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
\r
15330 #define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
\r
15331 #define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
\r
15332 #define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
\r
15334 #define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
\r
15335 #define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
\r
15336 #define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
\r
15337 #define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
\r
15338 #define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
\r
15340 #define RCC_D2CCIP1R_SWPSEL_Pos (31U)
\r
15341 #define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
\r
15342 #define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
\r
15344 /******************** Bit definition for RCC_D2CCIP2R register ***************/
\r
15345 #define RCC_D2CCIP2R_USART16SEL_Pos (3U)
\r
15346 #define RCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
\r
15347 #define RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk
\r
15348 #define RCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
\r
15349 #define RCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
\r
15350 #define RCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
\r
15352 #define RCC_D2CCIP2R_USART28SEL_Pos (0U)
\r
15353 #define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
\r
15354 #define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
\r
15355 #define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
\r
15356 #define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
\r
15357 #define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
\r
15359 #define RCC_D2CCIP2R_RNGSEL_Pos (8U)
\r
15360 #define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
\r
15361 #define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
\r
15362 #define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
\r
15363 #define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
\r
15365 #define RCC_D2CCIP2R_I2C123SEL_Pos (12U)
\r
15366 #define RCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
\r
15367 #define RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk
\r
15368 #define RCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
\r
15369 #define RCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
\r
15371 #define RCC_D2CCIP2R_USBSEL_Pos (20U)
\r
15372 #define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
\r
15373 #define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
\r
15374 #define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
\r
15375 #define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
\r
15377 #define RCC_D2CCIP2R_CECSEL_Pos (22U)
\r
15378 #define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
\r
15379 #define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
\r
15380 #define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
\r
15381 #define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
\r
15383 #define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
\r
15384 #define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
\r
15385 #define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
\r
15386 #define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
\r
15387 #define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
\r
15388 #define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
\r
15390 /******************** Bit definition for RCC_D3CCIPR register ***************/
\r
15391 #define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
\r
15392 #define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
\r
15393 #define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
\r
15394 #define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
\r
15395 #define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
\r
15396 #define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
\r
15398 #define RCC_D3CCIPR_I2C4SEL_Pos (8U)
\r
15399 #define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
\r
15400 #define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
\r
15401 #define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
\r
15402 #define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
\r
15404 #define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
\r
15405 #define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
\r
15406 #define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
\r
15407 #define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
\r
15408 #define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
\r
15409 #define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
\r
15411 #define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
\r
15412 #define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
\r
15413 #define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
\r
15414 #define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
\r
15415 #define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
\r
15416 #define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
\r
15418 #define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
\r
15419 #define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
\r
15420 #define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
\r
15421 #define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
\r
15422 #define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
\r
15423 #define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
\r
15425 #define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
\r
15426 #define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
\r
15427 #define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
\r
15428 #define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
\r
15429 #define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
\r
15430 #define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
\r
15432 #define RCC_D3CCIPR_ADCSEL_Pos (16U)
\r
15433 #define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
\r
15434 #define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
\r
15435 #define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
\r
15436 #define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
\r
15438 #define RCC_D3CCIPR_SPI6SEL_Pos (28U)
\r
15439 #define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
\r
15440 #define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
\r
15441 #define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
\r
15442 #define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
\r
15443 #define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
\r
15444 /******************** Bit definition for RCC_CIER register ******************/
\r
15445 #define RCC_CIER_LSIRDYIE_Pos (0U)
\r
15446 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
\r
15447 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
\r
15448 #define RCC_CIER_LSERDYIE_Pos (1U)
\r
15449 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
\r
15450 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
\r
15451 #define RCC_CIER_HSIRDYIE_Pos (2U)
\r
15452 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
\r
15453 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
\r
15454 #define RCC_CIER_HSERDYIE_Pos (3U)
\r
15455 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
\r
15456 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
\r
15457 #define RCC_CIER_CSIRDYIE_Pos (4U)
\r
15458 #define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
\r
15459 #define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
\r
15460 #define RCC_CIER_HSI48RDYIE_Pos (5U)
\r
15461 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
\r
15462 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
\r
15463 #define RCC_CIER_PLL1RDYIE_Pos (6U)
\r
15464 #define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
\r
15465 #define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
\r
15466 #define RCC_CIER_PLL2RDYIE_Pos (7U)
\r
15467 #define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
\r
15468 #define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
\r
15469 #define RCC_CIER_PLL3RDYIE_Pos (8U)
\r
15470 #define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
\r
15471 #define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
\r
15472 #define RCC_CIER_LSECSSIE_Pos (9U)
\r
15473 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
\r
15474 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
\r
15476 /******************** Bit definition for RCC_CIFR register ******************/
\r
15477 #define RCC_CIFR_LSIRDYF_Pos (0U)
\r
15478 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
\r
15479 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
\r
15480 #define RCC_CIFR_LSERDYF_Pos (1U)
\r
15481 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
\r
15482 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
\r
15483 #define RCC_CIFR_HSIRDYF_Pos (2U)
\r
15484 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
\r
15485 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
\r
15486 #define RCC_CIFR_HSERDYF_Pos (3U)
\r
15487 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
\r
15488 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
\r
15489 #define RCC_CIFR_CSIRDYF_Pos (4U)
\r
15490 #define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
\r
15491 #define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
\r
15492 #define RCC_CIFR_HSI48RDYF_Pos (5U)
\r
15493 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
\r
15494 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
\r
15495 #define RCC_CIFR_PLLRDYF_Pos (6U)
\r
15496 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
\r
15497 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
\r
15498 #define RCC_CIFR_PLL2RDYF_Pos (7U)
\r
15499 #define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
\r
15500 #define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
\r
15501 #define RCC_CIFR_PLL3RDYF_Pos (8U)
\r
15502 #define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
\r
15503 #define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
\r
15504 #define RCC_CIFR_LSECSSF_Pos (9U)
\r
15505 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
\r
15506 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
\r
15507 #define RCC_CIFR_HSECSSF_Pos (10U)
\r
15508 #define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
\r
15509 #define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
\r
15511 /******************** Bit definition for RCC_CICR register ******************/
\r
15512 #define RCC_CICR_LSIRDYC_Pos (0U)
\r
15513 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
\r
15514 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
\r
15515 #define RCC_CICR_LSERDYC_Pos (1U)
\r
15516 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
\r
15517 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
\r
15518 #define RCC_CICR_HSIRDYC_Pos (2U)
\r
15519 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
\r
15520 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
\r
15521 #define RCC_CICR_HSERDYC_Pos (3U)
\r
15522 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
\r
15523 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
\r
15524 #define RCC_CICR_CSIRDYC_Pos (4U)
\r
15525 #define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
\r
15526 #define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
\r
15527 #define RCC_CICR_HSI48RDYC_Pos (5U)
\r
15528 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
\r
15529 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
\r
15530 #define RCC_CICR_PLLRDYC_Pos (6U)
\r
15531 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
\r
15532 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
\r
15533 #define RCC_CICR_PLL2RDYC_Pos (7U)
\r
15534 #define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
\r
15535 #define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
\r
15536 #define RCC_CICR_PLL3RDYC_Pos (8U)
\r
15537 #define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
\r
15538 #define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
\r
15539 #define RCC_CICR_LSECSSC_Pos (9U)
\r
15540 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
\r
15541 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
\r
15542 #define RCC_CICR_HSECSSC_Pos (10U)
\r
15543 #define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
\r
15544 #define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
\r
15546 /******************** Bit definition for RCC_BDCR register ******************/
\r
15547 #define RCC_BDCR_LSEON_Pos (0U)
\r
15548 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
\r
15549 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
\r
15550 #define RCC_BDCR_LSERDY_Pos (1U)
\r
15551 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
\r
15552 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
\r
15553 #define RCC_BDCR_LSEBYP_Pos (2U)
\r
15554 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
\r
15555 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
\r
15557 #define RCC_BDCR_LSEDRV_Pos (3U)
\r
15558 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
\r
15559 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
\r
15560 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
\r
15561 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
\r
15563 #define RCC_BDCR_LSECSSON_Pos (5U)
\r
15564 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
\r
15565 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
\r
15566 #define RCC_BDCR_LSECSSD_Pos (6U)
\r
15567 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
\r
15568 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
\r
15570 #define RCC_BDCR_RTCSEL_Pos (8U)
\r
15571 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
\r
15572 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
\r
15573 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
\r
15574 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
\r
15576 #define RCC_BDCR_RTCEN_Pos (15U)
\r
15577 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
\r
15578 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
\r
15579 #define RCC_BDCR_BDRST_Pos (16U)
\r
15580 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
\r
15581 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
\r
15582 /******************** Bit definition for RCC_CSR register *******************/
\r
15583 #define RCC_CSR_LSION_Pos (0U)
\r
15584 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
\r
15585 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
\r
15586 #define RCC_CSR_LSIRDY_Pos (1U)
\r
15587 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
\r
15588 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
\r
15591 /******************** Bit definition for RCC_AHB3ENR register **************/
\r
15592 #define RCC_AHB3ENR_MDMAEN_Pos (0U)
\r
15593 #define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos) /*!< 0x00000001 */
\r
15594 #define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
\r
15595 #define RCC_AHB3ENR_DMA2DEN_Pos (4U)
\r
15596 #define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos) /*!< 0x00000010 */
\r
15597 #define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
\r
15598 #define RCC_AHB3ENR_JPGDECEN_Pos (5U)
\r
15599 #define RCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
\r
15600 #define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
\r
15601 #define RCC_AHB3ENR_FMCEN_Pos (12U)
\r
15602 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
\r
15603 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
\r
15604 #define RCC_AHB3ENR_QSPIEN_Pos (14U)
\r
15605 #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00004000 */
\r
15606 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
\r
15607 #define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
\r
15608 #define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos) /*!< 0x00010000 */
\r
15609 #define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
\r
15610 #define RCC_AHB3ENR_FLASHEN_Pos (8U)
\r
15611 #define RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x00000100 */
\r
15612 #define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk
\r
15613 #define RCC_AHB3ENR_DTCM1EN_Pos (28U)
\r
15614 #define RCC_AHB3ENR_DTCM1EN_Msk (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos) /*!< 0x10000000 */
\r
15615 #define RCC_AHB3ENR_DTCM1EN RCC_AHB3ENR_DTCM1EN_Msk
\r
15616 #define RCC_AHB3ENR_DTCM2EN_Pos (29U)
\r
15617 #define RCC_AHB3ENR_DTCM2EN_Msk (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos) /*!< 0x20000000 */
\r
15618 #define RCC_AHB3ENR_DTCM2EN RCC_AHB3ENR_DTCM2EN_Msk
\r
15619 #define RCC_AHB3ENR_ITCMEN_Pos (30U)
\r
15620 #define RCC_AHB3ENR_ITCMEN_Msk (0x1UL << RCC_AHB3ENR_ITCMEN_Pos) /*!< 0x40000000 */
\r
15621 #define RCC_AHB3ENR_ITCMEN RCC_AHB3ENR_ITCMEN_Msk
\r
15622 #define RCC_AHB3ENR_AXISRAMEN_Pos (31U)
\r
15623 #define RCC_AHB3ENR_AXISRAMEN_Msk (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos) /*!< 0x80000000 */
\r
15624 #define RCC_AHB3ENR_AXISRAMEN RCC_AHB3ENR_AXISRAMEN_Msk
\r
15626 /* Legacy define */
\r
15627 #define RCC_AHB3ENR_D1SRAM1EN_Pos RCC_AHB3ENR_AXISRAMEN_Pos
\r
15628 #define RCC_AHB3ENR_D1SRAM1EN_Msk RCC_AHB3ENR_AXISRAMEN_Msk
\r
15629 #define RCC_AHB3ENR_D1SRAM1EN RCC_AHB3ENR_AXISRAMEN
\r
15631 /******************** Bit definition for RCC_AHB1ENR register ***************/
\r
15632 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
\r
15633 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
\r
15634 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
\r
15635 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
\r
15636 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
\r
15637 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
\r
15638 #define RCC_AHB1ENR_ADC12EN_Pos (5U)
\r
15639 #define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */
\r
15640 #define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
\r
15641 #define RCC_AHB1ENR_ARTEN_Pos (14U)
\r
15642 #define RCC_AHB1ENR_ARTEN_Msk (0x1UL << RCC_AHB1ENR_ARTEN_Pos) /*!< 0x00004000 */
\r
15643 #define RCC_AHB1ENR_ARTEN RCC_AHB1ENR_ARTEN_Msk
\r
15644 #define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
\r
15645 #define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */
\r
15646 #define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
\r
15647 #define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
\r
15648 #define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */
\r
15649 #define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
\r
15650 #define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
\r
15651 #define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */
\r
15652 #define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
\r
15653 #define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
\r
15654 #define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos) /*!< 0x02000000 */
\r
15655 #define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
\r
15656 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
\r
15657 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
\r
15658 #define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
\r
15659 #define RCC_AHB1ENR_USB2OTGFSEN_Pos (27U)
\r
15660 #define RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos) /*!< 0x08000000 */
\r
15661 #define RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk
\r
15662 #define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U)
\r
15663 #define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
\r
15664 #define RCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
\r
15666 /* Legacy define */
\r
15667 #define RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos
\r
15668 #define RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk
\r
15669 #define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN
\r
15670 #define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
\r
15671 #define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
\r
15672 #define RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN
\r
15675 /******************** Bit definition for RCC_AHB2ENR register ***************/
\r
15676 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
\r
15677 #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
\r
15678 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
\r
15679 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
\r
15680 #define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
\r
15681 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
\r
15682 #define RCC_AHB2ENR_HASHEN_Pos (5U)
\r
15683 #define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
\r
15684 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
\r
15685 #define RCC_AHB2ENR_RNGEN_Pos (6U)
\r
15686 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
\r
15687 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
\r
15688 #define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
\r
15689 #define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
\r
15690 #define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
\r
15691 #define RCC_AHB2ENR_D2SRAM1EN_Pos (29U)
\r
15692 #define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x20000000 */
\r
15693 #define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk
\r
15694 #define RCC_AHB2ENR_D2SRAM2EN_Pos (30U)
\r
15695 #define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */
\r
15696 #define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_D2SRAM2EN_Msk
\r
15697 #define RCC_AHB2ENR_D2SRAM3EN_Pos (31U)
\r
15698 #define RCC_AHB2ENR_D2SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM3EN_Pos) /*!< 0x80000000 */
\r
15699 #define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_D2SRAM3EN_Msk
\r
15702 /******************** Bit definition for RCC_AHB4ENR register ******************/
\r
15703 #define RCC_AHB4ENR_GPIOAEN_Pos (0U)
\r
15704 #define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */
\r
15705 #define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
\r
15706 #define RCC_AHB4ENR_GPIOBEN_Pos (1U)
\r
15707 #define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */
\r
15708 #define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
\r
15709 #define RCC_AHB4ENR_GPIOCEN_Pos (2U)
\r
15710 #define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */
\r
15711 #define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
\r
15712 #define RCC_AHB4ENR_GPIODEN_Pos (3U)
\r
15713 #define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */
\r
15714 #define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
\r
15715 #define RCC_AHB4ENR_GPIOEEN_Pos (4U)
\r
15716 #define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */
\r
15717 #define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
\r
15718 #define RCC_AHB4ENR_GPIOFEN_Pos (5U)
\r
15719 #define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */
\r
15720 #define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
\r
15721 #define RCC_AHB4ENR_GPIOGEN_Pos (6U)
\r
15722 #define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */
\r
15723 #define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
\r
15724 #define RCC_AHB4ENR_GPIOHEN_Pos (7U)
\r
15725 #define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */
\r
15726 #define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
\r
15727 #define RCC_AHB4ENR_GPIOIEN_Pos (8U)
\r
15728 #define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos) /*!< 0x00000100 */
\r
15729 #define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
\r
15730 #define RCC_AHB4ENR_GPIOJEN_Pos (9U)
\r
15731 #define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos) /*!< 0x00000200 */
\r
15732 #define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
\r
15733 #define RCC_AHB4ENR_GPIOKEN_Pos (10U)
\r
15734 #define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos) /*!< 0x00000400 */
\r
15735 #define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
\r
15736 #define RCC_AHB4ENR_CRCEN_Pos (19U)
\r
15737 #define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */
\r
15738 #define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
\r
15739 #define RCC_AHB4ENR_BDMAEN_Pos (21U)
\r
15740 #define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos) /*!< 0x00200000 */
\r
15741 #define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
\r
15742 #define RCC_AHB4ENR_ADC3EN_Pos (24U)
\r
15743 #define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos) /*!< 0x01000000 */
\r
15744 #define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
\r
15745 #define RCC_AHB4ENR_HSEMEN_Pos (25U)
\r
15746 #define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos) /*!< 0x02000000 */
\r
15747 #define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
\r
15748 #define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
\r
15749 #define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */
\r
15750 #define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
\r
15751 #define RCC_AHB4ENR_D3SRAM1EN_Pos (29U)
\r
15752 #define RCC_AHB4ENR_D3SRAM1EN_Msk (0x1UL << RCC_AHB4ENR_D3SRAM1EN_Pos) /*!< 0x20000000 */
\r
15753 #define RCC_AHB4ENR_D3SRAM1EN RCC_AHB4ENR_D3SRAM1EN_Msk
\r
15755 /******************** Bit definition for RCC_APB3ENR register ******************/
\r
15756 #define RCC_APB3ENR_LTDCEN_Pos (3U)
\r
15757 #define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
\r
15758 #define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
\r
15759 #define RCC_APB3ENR_WWDG1EN_Pos (6U)
\r
15760 #define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
\r
15761 #define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
\r
15763 /******************** Bit definition for RCC_APB1LENR register ******************/
\r
15765 #define RCC_APB1LENR_TIM2EN_Pos (0U)
\r
15766 #define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
\r
15767 #define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
\r
15768 #define RCC_APB1LENR_TIM3EN_Pos (1U)
\r
15769 #define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
\r
15770 #define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
\r
15771 #define RCC_APB1LENR_TIM4EN_Pos (2U)
\r
15772 #define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
\r
15773 #define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
\r
15774 #define RCC_APB1LENR_TIM5EN_Pos (3U)
\r
15775 #define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
\r
15776 #define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
\r
15777 #define RCC_APB1LENR_TIM6EN_Pos (4U)
\r
15778 #define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
\r
15779 #define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
\r
15780 #define RCC_APB1LENR_TIM7EN_Pos (5U)
\r
15781 #define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
\r
15782 #define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
\r
15783 #define RCC_APB1LENR_TIM12EN_Pos (6U)
\r
15784 #define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
\r
15785 #define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
\r
15786 #define RCC_APB1LENR_TIM13EN_Pos (7U)
\r
15787 #define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
\r
15788 #define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
\r
15789 #define RCC_APB1LENR_TIM14EN_Pos (8U)
\r
15790 #define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
\r
15791 #define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
\r
15792 #define RCC_APB1LENR_LPTIM1EN_Pos (9U)
\r
15793 #define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
\r
15794 #define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
\r
15796 #define RCC_APB1LENR_WWDG2EN_Pos (11U)
\r
15797 #define RCC_APB1LENR_WWDG2EN_Msk (0x1UL << RCC_APB1LENR_WWDG2EN_Pos) /*!< 0x00000800 */
\r
15798 #define RCC_APB1LENR_WWDG2EN RCC_APB1LENR_WWDG2EN_Msk
\r
15800 #define RCC_APB1LENR_SPI2EN_Pos (14U)
\r
15801 #define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
\r
15802 #define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
\r
15803 #define RCC_APB1LENR_SPI3EN_Pos (15U)
\r
15804 #define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
\r
15805 #define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
\r
15806 #define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
\r
15807 #define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
\r
15808 #define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
\r
15809 #define RCC_APB1LENR_USART2EN_Pos (17U)
\r
15810 #define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
\r
15811 #define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
\r
15812 #define RCC_APB1LENR_USART3EN_Pos (18U)
\r
15813 #define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
\r
15814 #define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
\r
15815 #define RCC_APB1LENR_UART4EN_Pos (19U)
\r
15816 #define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
\r
15817 #define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
\r
15818 #define RCC_APB1LENR_UART5EN_Pos (20U)
\r
15819 #define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
\r
15820 #define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
\r
15821 #define RCC_APB1LENR_I2C1EN_Pos (21U)
\r
15822 #define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
\r
15823 #define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
\r
15824 #define RCC_APB1LENR_I2C2EN_Pos (22U)
\r
15825 #define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
\r
15826 #define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
\r
15827 #define RCC_APB1LENR_I2C3EN_Pos (23U)
\r
15828 #define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
\r
15829 #define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
\r
15830 #define RCC_APB1LENR_CECEN_Pos (27U)
\r
15831 #define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
\r
15832 #define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
\r
15833 #define RCC_APB1LENR_DAC12EN_Pos (29U)
\r
15834 #define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
\r
15835 #define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
\r
15836 #define RCC_APB1LENR_UART7EN_Pos (30U)
\r
15837 #define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
\r
15838 #define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
\r
15839 #define RCC_APB1LENR_UART8EN_Pos (31U)
\r
15840 #define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
\r
15841 #define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
\r
15843 /******************** Bit definition for RCC_APB1HENR register ******************/
\r
15844 #define RCC_APB1HENR_CRSEN_Pos (1U)
\r
15845 #define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
\r
15846 #define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
\r
15847 #define RCC_APB1HENR_SWPMIEN_Pos (2U)
\r
15848 #define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
\r
15849 #define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
\r
15850 #define RCC_APB1HENR_OPAMPEN_Pos (4U)
\r
15851 #define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
\r
15852 #define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
\r
15853 #define RCC_APB1HENR_MDIOSEN_Pos (5U)
\r
15854 #define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
\r
15855 #define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
\r
15856 #define RCC_APB1HENR_FDCANEN_Pos (8U)
\r
15857 #define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
\r
15858 #define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
\r
15860 /******************** Bit definition for RCC_APB2ENR register ******************/
\r
15861 #define RCC_APB2ENR_TIM1EN_Pos (0U)
\r
15862 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
\r
15863 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
\r
15864 #define RCC_APB2ENR_TIM8EN_Pos (1U)
\r
15865 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
\r
15866 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
\r
15867 #define RCC_APB2ENR_USART1EN_Pos (4U)
\r
15868 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
\r
15869 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
\r
15870 #define RCC_APB2ENR_USART6EN_Pos (5U)
\r
15871 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
\r
15872 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
\r
15873 #define RCC_APB2ENR_SPI1EN_Pos (12U)
\r
15874 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
\r
15875 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
\r
15876 #define RCC_APB2ENR_SPI4EN_Pos (13U)
\r
15877 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
\r
15878 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
\r
15879 #define RCC_APB2ENR_TIM15EN_Pos (16U)
\r
15880 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
\r
15881 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
\r
15882 #define RCC_APB2ENR_TIM16EN_Pos (17U)
\r
15883 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
\r
15884 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
\r
15885 #define RCC_APB2ENR_TIM17EN_Pos (18U)
\r
15886 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
\r
15887 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
\r
15888 #define RCC_APB2ENR_SPI5EN_Pos (20U)
\r
15889 #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
\r
15890 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
\r
15891 #define RCC_APB2ENR_SAI1EN_Pos (22U)
\r
15892 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
\r
15893 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
\r
15894 #define RCC_APB2ENR_SAI2EN_Pos (23U)
\r
15895 #define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
\r
15896 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
\r
15897 #define RCC_APB2ENR_SAI3EN_Pos (24U)
\r
15898 #define RCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
\r
15899 #define RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk
\r
15900 #define RCC_APB2ENR_DFSDM1EN_Pos (28U)
\r
15901 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
\r
15902 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
\r
15903 #define RCC_APB2ENR_HRTIMEN_Pos (29U)
\r
15904 #define RCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
\r
15905 #define RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk
\r
15907 /******************** Bit definition for RCC_APB4ENR register ******************/
\r
15908 #define RCC_APB4ENR_SYSCFGEN_Pos (1U)
\r
15909 #define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
\r
15910 #define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
\r
15911 #define RCC_APB4ENR_LPUART1EN_Pos (3U)
\r
15912 #define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
\r
15913 #define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
\r
15914 #define RCC_APB4ENR_SPI6EN_Pos (5U)
\r
15915 #define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
\r
15916 #define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
\r
15917 #define RCC_APB4ENR_I2C4EN_Pos (7U)
\r
15918 #define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
\r
15919 #define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
\r
15920 #define RCC_APB4ENR_LPTIM2EN_Pos (9U)
\r
15921 #define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
\r
15922 #define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
\r
15923 #define RCC_APB4ENR_LPTIM3EN_Pos (10U)
\r
15924 #define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
\r
15925 #define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
\r
15926 #define RCC_APB4ENR_LPTIM4EN_Pos (11U)
\r
15927 #define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
\r
15928 #define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
\r
15929 #define RCC_APB4ENR_LPTIM5EN_Pos (12U)
\r
15930 #define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
\r
15931 #define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
\r
15932 #define RCC_APB4ENR_COMP12EN_Pos (14U)
\r
15933 #define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
\r
15934 #define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
\r
15935 #define RCC_APB4ENR_VREFEN_Pos (15U)
\r
15936 #define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
\r
15937 #define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
\r
15938 #define RCC_APB4ENR_RTCAPBEN_Pos (16U)
\r
15939 #define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
\r
15940 #define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
\r
15941 #define RCC_APB4ENR_SAI4EN_Pos (21U)
\r
15942 #define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
\r
15943 #define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
\r
15946 /******************** Bit definition for RCC_AHB3RSTR register ***************/
\r
15947 #define RCC_AHB3RSTR_MDMARST_Pos (0U)
\r
15948 #define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos) /*!< 0x00000001 */
\r
15949 #define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
\r
15950 #define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
\r
15951 #define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos) /*!< 0x00000010 */
\r
15952 #define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
\r
15953 #define RCC_AHB3RSTR_JPGDECRST_Pos (5U)
\r
15954 #define RCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos) /*!< 0x00000020 */
\r
15955 #define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk
\r
15956 #define RCC_AHB3RSTR_FMCRST_Pos (12U)
\r
15957 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00001000 */
\r
15958 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
\r
15959 #define RCC_AHB3RSTR_QSPIRST_Pos (14U)
\r
15960 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00004000 */
\r
15961 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
\r
15962 #define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
\r
15963 #define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos) /*!< 0x00010000 */
\r
15964 #define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
\r
15967 /******************** Bit definition for RCC_AHB1RSTR register ***************/
\r
15968 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
\r
15969 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
\r
15970 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
\r
15971 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
\r
15972 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
\r
15973 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
\r
15974 #define RCC_AHB1RSTR_ADC12RST_Pos (5U)
\r
15975 #define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */
\r
15976 #define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
\r
15977 #define RCC_AHB1RSTR_ARTRST_Pos (14U)
\r
15978 #define RCC_AHB1RSTR_ARTRST_Msk (0x1UL << RCC_AHB1RSTR_ARTRST_Pos) /*!< 0x00004000 */
\r
15979 #define RCC_AHB1RSTR_ARTRST RCC_AHB1RSTR_ARTRST_Msk
\r
15980 #define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
\r
15981 #define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos) /*!< 0x00008000 */
\r
15982 #define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
\r
15983 #define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
\r
15984 #define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
\r
15985 #define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
\r
15986 #define RCC_AHB1RSTR_USB2OTGFSRST_Pos (27U)
\r
15987 #define RCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
\r
15988 #define RCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk
\r
15990 /* Legacy define */
\r
15991 #define RCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos
\r
15992 #define RCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk
\r
15993 #define RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST
\r
15995 /******************** Bit definition for RCC_AHB2RSTR register ***************/
\r
15996 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
\r
15997 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
\r
15998 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
\r
15999 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
\r
16000 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
\r
16001 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
\r
16002 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
\r
16003 #define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
\r
16004 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
\r
16005 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
\r
16006 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
\r
16007 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
\r
16008 #define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
\r
16009 #define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */
\r
16010 #define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
\r
16012 /******************** Bit definition for RCC_AHB4RSTR register ******************/
\r
16013 #define RCC_AHB4RSTR_GPIOARST_Pos (0U)
\r
16014 #define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */
\r
16015 #define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
\r
16016 #define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
\r
16017 #define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
\r
16018 #define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
\r
16019 #define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
\r
16020 #define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
\r
16021 #define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
\r
16022 #define RCC_AHB4RSTR_GPIODRST_Pos (3U)
\r
16023 #define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */
\r
16024 #define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
\r
16025 #define RCC_AHB4RSTR_GPIOERST_Pos (4U)
\r
16026 #define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */
\r
16027 #define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
\r
16028 #define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
\r
16029 #define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
\r
16030 #define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
\r
16031 #define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
\r
16032 #define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
\r
16033 #define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
\r
16034 #define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
\r
16035 #define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
\r
16036 #define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
\r
16037 #define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
\r
16038 #define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
\r
16039 #define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
\r
16040 #define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
\r
16041 #define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
\r
16042 #define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
\r
16043 #define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
\r
16044 #define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
\r
16045 #define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
\r
16046 #define RCC_AHB4RSTR_CRCRST_Pos (19U)
\r
16047 #define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */
\r
16048 #define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
\r
16049 #define RCC_AHB4RSTR_BDMARST_Pos (21U)
\r
16050 #define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos) /*!< 0x00200000 */
\r
16051 #define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
\r
16052 #define RCC_AHB4RSTR_ADC3RST_Pos (24U)
\r
16053 #define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos) /*!< 0x01000000 */
\r
16054 #define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
\r
16055 #define RCC_AHB4RSTR_HSEMRST_Pos (25U)
\r
16056 #define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos) /*!< 0x02000000 */
\r
16057 #define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
\r
16060 /******************** Bit definition for RCC_APB3RSTR register ******************/
\r
16061 #define RCC_APB3RSTR_LTDCRST_Pos (3U)
\r
16062 #define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
\r
16063 #define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
\r
16065 /******************** Bit definition for RCC_APB1LRSTR register ******************/
\r
16067 #define RCC_APB1LRSTR_TIM2RST_Pos (0U)
\r
16068 #define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
\r
16069 #define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
\r
16070 #define RCC_APB1LRSTR_TIM3RST_Pos (1U)
\r
16071 #define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
\r
16072 #define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
\r
16073 #define RCC_APB1LRSTR_TIM4RST_Pos (2U)
\r
16074 #define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
\r
16075 #define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
\r
16076 #define RCC_APB1LRSTR_TIM5RST_Pos (3U)
\r
16077 #define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
\r
16078 #define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
\r
16079 #define RCC_APB1LRSTR_TIM6RST_Pos (4U)
\r
16080 #define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
\r
16081 #define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
\r
16082 #define RCC_APB1LRSTR_TIM7RST_Pos (5U)
\r
16083 #define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
\r
16084 #define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
\r
16085 #define RCC_APB1LRSTR_TIM12RST_Pos (6U)
\r
16086 #define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
\r
16087 #define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
\r
16088 #define RCC_APB1LRSTR_TIM13RST_Pos (7U)
\r
16089 #define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
\r
16090 #define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
\r
16091 #define RCC_APB1LRSTR_TIM14RST_Pos (8U)
\r
16092 #define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
\r
16093 #define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
\r
16094 #define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
\r
16095 #define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
\r
16096 #define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
\r
16097 #define RCC_APB1LRSTR_SPI2RST_Pos (14U)
\r
16098 #define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
\r
16099 #define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
\r
16100 #define RCC_APB1LRSTR_SPI3RST_Pos (15U)
\r
16101 #define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
\r
16102 #define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
\r
16103 #define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
\r
16104 #define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
\r
16105 #define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
\r
16106 #define RCC_APB1LRSTR_USART2RST_Pos (17U)
\r
16107 #define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
\r
16108 #define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
\r
16109 #define RCC_APB1LRSTR_USART3RST_Pos (18U)
\r
16110 #define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
\r
16111 #define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
\r
16112 #define RCC_APB1LRSTR_UART4RST_Pos (19U)
\r
16113 #define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
\r
16114 #define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
\r
16115 #define RCC_APB1LRSTR_UART5RST_Pos (20U)
\r
16116 #define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
\r
16117 #define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
\r
16118 #define RCC_APB1LRSTR_I2C1RST_Pos (21U)
\r
16119 #define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
\r
16120 #define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
\r
16121 #define RCC_APB1LRSTR_I2C2RST_Pos (22U)
\r
16122 #define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
\r
16123 #define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
\r
16124 #define RCC_APB1LRSTR_I2C3RST_Pos (23U)
\r
16125 #define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
\r
16126 #define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
\r
16127 #define RCC_APB1LRSTR_CECRST_Pos (27U)
\r
16128 #define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
\r
16129 #define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
\r
16130 #define RCC_APB1LRSTR_DAC12RST_Pos (29U)
\r
16131 #define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
\r
16132 #define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
\r
16133 #define RCC_APB1LRSTR_UART7RST_Pos (30U)
\r
16134 #define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
\r
16135 #define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
\r
16136 #define RCC_APB1LRSTR_UART8RST_Pos (31U)
\r
16137 #define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
\r
16138 #define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
\r
16140 /******************** Bit definition for RCC_APB1HRSTR register ******************/
\r
16141 #define RCC_APB1HRSTR_CRSRST_Pos (1U)
\r
16142 #define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
\r
16143 #define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
\r
16144 #define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
\r
16145 #define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
\r
16146 #define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
\r
16147 #define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
\r
16148 #define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
\r
16149 #define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
\r
16150 #define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
\r
16151 #define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
\r
16152 #define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
\r
16153 #define RCC_APB1HRSTR_FDCANRST_Pos (8U)
\r
16154 #define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
\r
16155 #define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
\r
16157 /******************** Bit definition for RCC_APB2RSTR register ******************/
\r
16158 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
\r
16159 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
\r
16160 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
\r
16161 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
\r
16162 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
\r
16163 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
\r
16164 #define RCC_APB2RSTR_USART1RST_Pos (4U)
\r
16165 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
\r
16166 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
\r
16167 #define RCC_APB2RSTR_USART6RST_Pos (5U)
\r
16168 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
\r
16169 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
\r
16170 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
\r
16171 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
\r
16172 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
\r
16173 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
\r
16174 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
\r
16175 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
\r
16176 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
\r
16177 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
\r
16178 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
\r
16179 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
\r
16180 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
\r
16181 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
\r
16182 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
\r
16183 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
\r
16184 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
\r
16185 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
\r
16186 #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
\r
16187 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
\r
16188 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
\r
16189 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
\r
16190 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
\r
16191 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
\r
16192 #define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
\r
16193 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
\r
16194 #define RCC_APB2RSTR_SAI3RST_Pos (24U)
\r
16195 #define RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
\r
16196 #define RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk
\r
16197 #define RCC_APB2RSTR_DFSDM1RST_Pos (28U)
\r
16198 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
\r
16199 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
\r
16200 #define RCC_APB2RSTR_HRTIMRST_Pos (29U)
\r
16201 #define RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
\r
16202 #define RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk
\r
16204 /******************** Bit definition for RCC_APB4RSTR register ******************/
\r
16205 #define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
\r
16206 #define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
\r
16207 #define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
\r
16208 #define RCC_APB4RSTR_LPUART1RST_Pos (3U)
\r
16209 #define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
\r
16210 #define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
\r
16211 #define RCC_APB4RSTR_SPI6RST_Pos (5U)
\r
16212 #define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
\r
16213 #define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
\r
16214 #define RCC_APB4RSTR_I2C4RST_Pos (7U)
\r
16215 #define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
\r
16216 #define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
\r
16217 #define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
\r
16218 #define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
\r
16219 #define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
\r
16220 #define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
\r
16221 #define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
\r
16222 #define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
\r
16223 #define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
\r
16224 #define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
\r
16225 #define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
\r
16226 #define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
\r
16227 #define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
\r
16228 #define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
\r
16229 #define RCC_APB4RSTR_COMP12RST_Pos (14U)
\r
16230 #define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
\r
16231 #define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
\r
16232 #define RCC_APB4RSTR_VREFRST_Pos (15U)
\r
16233 #define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
\r
16234 #define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
\r
16235 #define RCC_APB4RSTR_SAI4RST_Pos (21U)
\r
16236 #define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
\r
16237 #define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
\r
16240 /******************** Bit definition for RCC_GCR register ********************/
\r
16241 #define RCC_GCR_WW1RSC_Pos (0U)
\r
16242 #define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos) /*!< 0x00000001 */
\r
16243 #define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
\r
16244 #define RCC_GCR_WW2RSC_Pos (1U)
\r
16245 #define RCC_GCR_WW2RSC_Msk (0x1UL << RCC_GCR_WW2RSC_Pos) /*!< 0x00000002 */
\r
16246 #define RCC_GCR_WW2RSC RCC_GCR_WW2RSC_Msk
\r
16247 #define RCC_GCR_BOOT_C1_Pos (2U)
\r
16248 #define RCC_GCR_BOOT_C1_Msk (0x1UL << RCC_GCR_BOOT_C1_Pos) /*!< 0x00000004 */
\r
16249 #define RCC_GCR_BOOT_C1 RCC_GCR_BOOT_C1_Msk
\r
16250 #define RCC_GCR_BOOT_C2_Pos (3U)
\r
16251 #define RCC_GCR_BOOT_C2_Msk (0x1UL << RCC_GCR_BOOT_C2_Pos) /*!< 0x00000008 */
\r
16252 #define RCC_GCR_BOOT_C2 RCC_GCR_BOOT_C2_Msk
\r
16254 /******************** Bit definition for RCC_D3AMR register ********************/
\r
16255 #define RCC_D3AMR_BDMAAMEN_Pos (0U)
\r
16256 #define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
\r
16257 #define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
\r
16258 #define RCC_D3AMR_LPUART1AMEN_Pos (3U)
\r
16259 #define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
\r
16260 #define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
\r
16261 #define RCC_D3AMR_SPI6AMEN_Pos (5U)
\r
16262 #define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
\r
16263 #define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
\r
16264 #define RCC_D3AMR_I2C4AMEN_Pos (7U)
\r
16265 #define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
\r
16266 #define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
\r
16267 #define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
\r
16268 #define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
\r
16269 #define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
\r
16270 #define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
\r
16271 #define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
\r
16272 #define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
\r
16273 #define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
\r
16274 #define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
\r
16275 #define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
\r
16276 #define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
\r
16277 #define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
\r
16278 #define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
\r
16279 #define RCC_D3AMR_COMP12AMEN_Pos (14U)
\r
16280 #define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
\r
16281 #define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
\r
16282 #define RCC_D3AMR_VREFAMEN_Pos (15U)
\r
16283 #define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
\r
16284 #define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
\r
16285 #define RCC_D3AMR_RTCAMEN_Pos (16U)
\r
16286 #define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
\r
16287 #define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
\r
16288 #define RCC_D3AMR_CRCAMEN_Pos (19U)
\r
16289 #define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
\r
16290 #define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
\r
16291 #define RCC_D3AMR_SAI4AMEN_Pos (21U)
\r
16292 #define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
\r
16293 #define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
\r
16294 #define RCC_D3AMR_ADC3AMEN_Pos (24U)
\r
16295 #define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
\r
16296 #define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
\r
16299 #define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
\r
16300 #define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
\r
16301 #define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
\r
16302 #define RCC_D3AMR_SRAM4AMEN_Pos (29U)
\r
16303 #define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
\r
16304 #define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
\r
16305 /******************** Bit definition for RCC_AHB3LPENR register **************/
\r
16306 #define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
\r
16307 #define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos) /*!< 0x00000001 */
\r
16308 #define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
\r
16309 #define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
\r
16310 #define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos) /*!< 0x00000010 */
\r
16311 #define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
\r
16312 #define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)
\r
16313 #define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos) /*!< 0x00000020 */
\r
16314 #define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk
\r
16315 #define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
\r
16316 #define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */
\r
16317 #define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
\r
16318 #define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
\r
16319 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00001000 */
\r
16320 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
\r
16321 #define RCC_AHB3LPENR_QSPILPEN_Pos (14U)
\r
16322 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00004000 */
\r
16323 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
\r
16324 #define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
\r
16325 #define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
\r
16326 #define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
\r
16327 #define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
\r
16328 #define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */
\r
16329 #define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
\r
16330 #define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
\r
16331 #define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */
\r
16332 #define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
\r
16333 #define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
\r
16334 #define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */
\r
16335 #define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
\r
16336 #define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
\r
16337 #define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */
\r
16338 #define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
\r
16341 /******************** Bit definition for RCC_AHB1LPENR register ***************/
\r
16342 #define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
\r
16343 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
\r
16344 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
\r
16345 #define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
\r
16346 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
\r
16347 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
\r
16348 #define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
\r
16349 #define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
\r
16350 #define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
\r
16351 #define RCC_AHB1LPENR_ARTLPEN_Pos (14U)
\r
16352 #define RCC_AHB1LPENR_ARTLPEN_Msk (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos) /*!< 0x00004000 */
\r
16353 #define RCC_AHB1LPENR_ARTLPEN RCC_AHB1LPENR_ARTLPEN_Msk
\r
16354 #define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
\r
16355 #define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
\r
16356 #define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
\r
16357 #define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
\r
16358 #define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
\r
16359 #define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
\r
16360 #define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
\r
16361 #define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
\r
16362 #define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
\r
16363 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
\r
16364 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
\r
16365 #define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
\r
16366 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
\r
16367 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
\r
16368 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
\r
16369 #define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U)
\r
16370 #define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
\r
16371 #define RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
\r
16372 #define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U)
\r
16373 #define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
\r
16374 #define RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
\r
16376 /* Legacy define */
\r
16377 #define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
\r
16378 #define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
\r
16379 #define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN
\r
16380 #define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
\r
16381 #define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
\r
16382 #define RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN
\r
16384 /******************** Bit definition for RCC_AHB2LPENR register ***************/
\r
16385 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
\r
16386 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
\r
16387 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
\r
16388 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
\r
16389 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
\r
16390 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
\r
16391 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
\r
16392 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
\r
16393 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
\r
16394 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
\r
16395 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
\r
16396 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
\r
16397 #define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
\r
16398 #define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
\r
16399 #define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
\r
16400 #define RCC_AHB2LPENR_D2SRAM1LPEN_Pos (30U)
\r
16401 #define RCC_AHB2LPENR_D2SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM1LPEN_Pos) /*!< 0x40000000 */
\r
16402 #define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_D2SRAM1LPEN_Msk
\r
16403 #define RCC_AHB2LPENR_D2SRAM2LPEN_Pos (30U)
\r
16404 #define RCC_AHB2LPENR_D2SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM2LPEN_Pos) /*!< 0x40000000 */
\r
16405 #define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_D2SRAM2LPEN_Msk
\r
16406 #define RCC_AHB2LPENR_D2SRAM3LPEN_Pos (31U)
\r
16407 #define RCC_AHB2LPENR_D2SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM3LPEN_Pos) /*!< 0x80000000 */
\r
16408 #define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_D2SRAM3LPEN_Msk
\r
16411 /******************** Bit definition for RCC_AHB4LPENR register ******************/
\r
16412 #define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
\r
16413 #define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
\r
16414 #define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
\r
16415 #define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
\r
16416 #define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
\r
16417 #define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
\r
16418 #define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
\r
16419 #define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
\r
16420 #define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
\r
16421 #define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
\r
16422 #define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
\r
16423 #define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
\r
16424 #define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
\r
16425 #define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
\r
16426 #define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
\r
16427 #define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
\r
16428 #define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
\r
16429 #define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
\r
16430 #define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
\r
16431 #define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
\r
16432 #define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
\r
16433 #define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
\r
16434 #define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
\r
16435 #define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
\r
16436 #define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
\r
16437 #define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
\r
16438 #define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
\r
16439 #define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
\r
16440 #define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
\r
16441 #define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
\r
16442 #define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
\r
16443 #define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
\r
16444 #define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
\r
16445 #define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
\r
16446 #define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
\r
16447 #define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
\r
16448 #define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
\r
16449 #define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
\r
16450 #define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
\r
16451 #define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
\r
16452 #define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
\r
16453 #define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
\r
16454 #define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
\r
16455 #define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
\r
16456 #define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
\r
16457 #define RCC_AHB4LPENR_D3SRAM1LPEN_Pos (29U)
\r
16458 #define RCC_AHB4LPENR_D3SRAM1LPEN_Msk (0x1UL << RCC_AHB4LPENR_D3SRAM1LPEN_Pos) /*!< 0x20000000 */
\r
16459 #define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_D3SRAM1LPEN_Msk
\r
16461 /******************** Bit definition for RCC_APB3LPENR register ******************/
\r
16462 #define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
\r
16463 #define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
\r
16464 #define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
\r
16465 #define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
\r
16466 #define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
\r
16467 #define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
\r
16469 /******************** Bit definition for RCC_APB1LLPENR register ******************/
\r
16471 #define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
\r
16472 #define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
\r
16473 #define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
\r
16474 #define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
\r
16475 #define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
\r
16476 #define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
\r
16477 #define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
\r
16478 #define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
\r
16479 #define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
\r
16480 #define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
\r
16481 #define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
\r
16482 #define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
\r
16483 #define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
\r
16484 #define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
\r
16485 #define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
\r
16486 #define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
\r
16487 #define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
\r
16488 #define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
\r
16489 #define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
\r
16490 #define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
\r
16491 #define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
\r
16492 #define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
\r
16493 #define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
\r
16494 #define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
\r
16495 #define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
\r
16496 #define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
\r
16497 #define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
\r
16498 #define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
\r
16499 #define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
\r
16500 #define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
\r
16502 #define RCC_APB1LLPENR_WWDG2LPEN_Pos (11U)
\r
16503 #define RCC_APB1LLPENR_WWDG2LPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos) /*!< 0x00000800 */
\r
16504 #define RCC_APB1LLPENR_WWDG2LPEN RCC_APB1LLPENR_WWDG2LPEN_Msk
\r
16506 #define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
\r
16507 #define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
\r
16508 #define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
\r
16509 #define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
\r
16510 #define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
\r
16511 #define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
\r
16512 #define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
\r
16513 #define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
\r
16514 #define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
\r
16515 #define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
\r
16516 #define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
\r
16517 #define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
\r
16518 #define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
\r
16519 #define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
\r
16520 #define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
\r
16521 #define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
\r
16522 #define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
\r
16523 #define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
\r
16524 #define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
\r
16525 #define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
\r
16526 #define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
\r
16527 #define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
\r
16528 #define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
\r
16529 #define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
\r
16530 #define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
\r
16531 #define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
\r
16532 #define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
\r
16533 #define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
\r
16534 #define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
\r
16535 #define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
\r
16536 #define RCC_APB1LLPENR_CECLPEN_Pos (27U)
\r
16537 #define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
\r
16538 #define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
\r
16539 #define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
\r
16540 #define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
\r
16541 #define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
\r
16542 #define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
\r
16543 #define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
\r
16544 #define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
\r
16545 #define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
\r
16546 #define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
\r
16547 #define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
\r
16549 /******************** Bit definition for RCC_APB1HLPENR register ******************/
\r
16550 #define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
\r
16551 #define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
\r
16552 #define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
\r
16553 #define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
\r
16554 #define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
\r
16555 #define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
\r
16556 #define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
\r
16557 #define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
\r
16558 #define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
\r
16559 #define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
\r
16560 #define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
\r
16561 #define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
\r
16562 #define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
\r
16563 #define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
\r
16564 #define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
\r
16566 /******************** Bit definition for RCC_APB2LPENR register ******************/
\r
16567 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
\r
16568 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
\r
16569 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
\r
16570 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
\r
16571 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
\r
16572 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
\r
16573 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
\r
16574 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
\r
16575 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
\r
16576 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
\r
16577 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
\r
16578 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
\r
16579 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
\r
16580 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
\r
16581 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
\r
16582 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
\r
16583 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
\r
16584 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
\r
16585 #define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
\r
16586 #define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
\r
16587 #define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
\r
16588 #define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
\r
16589 #define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
\r
16590 #define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
\r
16591 #define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
\r
16592 #define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
\r
16593 #define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
\r
16594 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
\r
16595 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
\r
16596 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
\r
16597 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
\r
16598 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
\r
16599 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
\r
16600 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
\r
16601 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
\r
16602 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
\r
16603 #define RCC_APB2LPENR_SAI3LPEN_Pos (24U)
\r
16604 #define RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
\r
16605 #define RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk
\r
16606 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (28U)
\r
16607 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
\r
16608 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
\r
16609 #define RCC_APB2LPENR_HRTIMLPEN_Pos (29U)
\r
16610 #define RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
\r
16611 #define RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk
\r
16613 /******************** Bit definition for RCC_APB4LPENR register ******************/
\r
16614 #define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
\r
16615 #define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
\r
16616 #define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
\r
16617 #define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
\r
16618 #define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
\r
16619 #define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
\r
16620 #define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
\r
16621 #define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
\r
16622 #define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
\r
16623 #define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
\r
16624 #define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
\r
16625 #define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
\r
16626 #define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
\r
16627 #define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
\r
16628 #define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
\r
16629 #define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
\r
16630 #define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
\r
16631 #define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
\r
16632 #define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
\r
16633 #define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
\r
16634 #define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
\r
16635 #define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
\r
16636 #define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
\r
16637 #define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
\r
16638 #define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
\r
16639 #define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
\r
16640 #define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
\r
16641 #define RCC_APB4LPENR_VREFLPEN_Pos (15U)
\r
16642 #define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
\r
16643 #define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
\r
16644 #define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
\r
16645 #define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
\r
16646 #define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
\r
16647 #define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
\r
16648 #define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
\r
16649 #define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
\r
16652 /******************** Bit definition for RCC_RSR register *******************/
\r
16653 #define RCC_RSR_RMVF_Pos (16U)
\r
16654 #define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */
\r
16655 #define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
\r
16656 #define RCC_RSR_C1RSTF_Pos (17U)
\r
16657 #define RCC_RSR_C1RSTF_Msk (0x1UL << RCC_RSR_C1RSTF_Pos) /*!< 0x00020000 */
\r
16658 #define RCC_RSR_C1RSTF RCC_RSR_C1RSTF_Msk
\r
16659 #define RCC_RSR_D1RSTF_Pos (19U)
\r
16660 #define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos) /*!< 0x00080000 */
\r
16661 #define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
\r
16662 #define RCC_RSR_D2RSTF_Pos (20U)
\r
16663 #define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos) /*!< 0x00100000 */
\r
16664 #define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
\r
16665 #define RCC_RSR_BORRSTF_Pos (21U)
\r
16666 #define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */
\r
16667 #define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
\r
16668 #define RCC_RSR_PINRSTF_Pos (22U)
\r
16669 #define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */
\r
16670 #define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
\r
16671 #define RCC_RSR_PORRSTF_Pos (23U)
\r
16672 #define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */
\r
16673 #define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
\r
16674 #define RCC_RSR_SFT1RSTF_Pos (24U)
\r
16675 #define RCC_RSR_SFT1RSTF_Msk (0x1UL << RCC_RSR_SFT1RSTF_Pos) /*!< 0x01000000 */
\r
16676 #define RCC_RSR_SFT1RSTF RCC_RSR_SFT1RSTF_Msk
\r
16677 #define RCC_RSR_IWDG1RSTF_Pos (26U)
\r
16678 #define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
\r
16679 #define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
\r
16680 #define RCC_RSR_WWDG1RSTF_Pos (28U)
\r
16681 #define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
\r
16682 #define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
\r
16684 #define RCC_RSR_WWDG2RSTF_Pos (29U)
\r
16685 #define RCC_RSR_WWDG2RSTF_Msk (0x1UL << RCC_RSR_WWDG2RSTF_Pos) /*!< 0x20000000 */
\r
16686 #define RCC_RSR_WWDG2RSTF RCC_RSR_WWDG2RSTF_Msk
\r
16687 #define RCC_RSR_IWDG2RSTF_Pos (27U)
\r
16688 #define RCC_RSR_IWDG2RSTF_Msk (0x1UL << RCC_RSR_IWDG2RSTF_Pos) /*!< 0x08000000 */
\r
16689 #define RCC_RSR_IWDG2RSTF RCC_RSR_IWDG2RSTF_Msk
\r
16690 #define RCC_RSR_SFT2RSTF_Pos (25U)
\r
16691 #define RCC_RSR_SFT2RSTF_Msk (0x1UL << RCC_RSR_SFT2RSTF_Pos) /*!< 0x02000000 */
\r
16692 #define RCC_RSR_SFT2RSTF RCC_RSR_SFT2RSTF_Msk
\r
16693 #define RCC_RSR_C2RSTF_Pos (18U)
\r
16694 #define RCC_RSR_C2RSTF_Msk (0x1UL << RCC_RSR_C2RSTF_Pos) /*!< 0x00040000 */
\r
16695 #define RCC_RSR_C2RSTF RCC_RSR_C2RSTF_Msk
\r
16696 #define RCC_RSR_LPWR1RSTF_Pos (30U)
\r
16697 #define RCC_RSR_LPWR1RSTF_Msk (0x1UL << RCC_RSR_LPWR1RSTF_Pos) /*!< 0x40000000 */
\r
16698 #define RCC_RSR_LPWR1RSTF RCC_RSR_LPWR1RSTF_Msk
\r
16699 #define RCC_RSR_LPWR2RSTF_Pos (31U)
\r
16700 #define RCC_RSR_LPWR2RSTF_Msk (0x1UL << RCC_RSR_LPWR2RSTF_Pos) /*!< 0x80000000 */
\r
16701 #define RCC_RSR_LPWR2RSTF RCC_RSR_LPWR2RSTF_Msk
\r
16704 /******************************************************************************/
\r
16708 /******************************************************************************/
\r
16709 /******************** Bits definition for RNG_CR register *******************/
\r
16710 #define RNG_CR_RNGEN_Pos (2U)
\r
16711 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
\r
16712 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
\r
16713 #define RNG_CR_IE_Pos (3U)
\r
16714 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
\r
16715 #define RNG_CR_IE RNG_CR_IE_Msk
\r
16716 #define RNG_CR_CED_Pos (5U)
\r
16717 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
\r
16718 #define RNG_CR_CED RNG_CR_CED_Msk
\r
16720 /******************** Bits definition for RNG_SR register *******************/
\r
16721 #define RNG_SR_DRDY_Pos (0U)
\r
16722 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
\r
16723 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
\r
16724 #define RNG_SR_CECS_Pos (1U)
\r
16725 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
\r
16726 #define RNG_SR_CECS RNG_SR_CECS_Msk
\r
16727 #define RNG_SR_SECS_Pos (2U)
\r
16728 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
\r
16729 #define RNG_SR_SECS RNG_SR_SECS_Msk
\r
16730 #define RNG_SR_CEIS_Pos (5U)
\r
16731 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
\r
16732 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
\r
16733 #define RNG_SR_SEIS_Pos (6U)
\r
16734 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
\r
16735 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
\r
16737 /******************************************************************************/
\r
16739 /* Real-Time Clock (RTC) */
\r
16741 /******************************************************************************/
\r
16742 /******************** Bits definition for RTC_TR register *******************/
\r
16743 #define RTC_TR_PM_Pos (22U)
\r
16744 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
\r
16745 #define RTC_TR_PM RTC_TR_PM_Msk
\r
16746 #define RTC_TR_HT_Pos (20U)
\r
16747 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
\r
16748 #define RTC_TR_HT RTC_TR_HT_Msk
\r
16749 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
\r
16750 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
\r
16751 #define RTC_TR_HU_Pos (16U)
\r
16752 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
\r
16753 #define RTC_TR_HU RTC_TR_HU_Msk
\r
16754 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
\r
16755 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
\r
16756 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
\r
16757 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
\r
16758 #define RTC_TR_MNT_Pos (12U)
\r
16759 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
\r
16760 #define RTC_TR_MNT RTC_TR_MNT_Msk
\r
16761 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
\r
16762 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
\r
16763 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
\r
16764 #define RTC_TR_MNU_Pos (8U)
\r
16765 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
\r
16766 #define RTC_TR_MNU RTC_TR_MNU_Msk
\r
16767 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
\r
16768 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
\r
16769 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
\r
16770 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
\r
16771 #define RTC_TR_ST_Pos (4U)
\r
16772 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
\r
16773 #define RTC_TR_ST RTC_TR_ST_Msk
\r
16774 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
\r
16775 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
\r
16776 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
\r
16777 #define RTC_TR_SU_Pos (0U)
\r
16778 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
\r
16779 #define RTC_TR_SU RTC_TR_SU_Msk
\r
16780 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
\r
16781 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
\r
16782 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
\r
16783 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
\r
16785 /******************** Bits definition for RTC_DR register *******************/
\r
16786 #define RTC_DR_YT_Pos (20U)
\r
16787 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
\r
16788 #define RTC_DR_YT RTC_DR_YT_Msk
\r
16789 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
\r
16790 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
\r
16791 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
\r
16792 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
\r
16793 #define RTC_DR_YU_Pos (16U)
\r
16794 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
\r
16795 #define RTC_DR_YU RTC_DR_YU_Msk
\r
16796 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
\r
16797 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
\r
16798 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
\r
16799 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
\r
16800 #define RTC_DR_WDU_Pos (13U)
\r
16801 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
\r
16802 #define RTC_DR_WDU RTC_DR_WDU_Msk
\r
16803 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
\r
16804 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
\r
16805 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
\r
16806 #define RTC_DR_MT_Pos (12U)
\r
16807 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
\r
16808 #define RTC_DR_MT RTC_DR_MT_Msk
\r
16809 #define RTC_DR_MU_Pos (8U)
\r
16810 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
\r
16811 #define RTC_DR_MU RTC_DR_MU_Msk
\r
16812 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
\r
16813 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
\r
16814 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
\r
16815 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
\r
16816 #define RTC_DR_DT_Pos (4U)
\r
16817 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
\r
16818 #define RTC_DR_DT RTC_DR_DT_Msk
\r
16819 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
\r
16820 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
\r
16821 #define RTC_DR_DU_Pos (0U)
\r
16822 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
\r
16823 #define RTC_DR_DU RTC_DR_DU_Msk
\r
16824 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
\r
16825 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
\r
16826 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
\r
16827 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
\r
16829 /******************** Bits definition for RTC_CR register *******************/
\r
16830 #define RTC_CR_ITSE_Pos (24U)
\r
16831 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
\r
16832 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
\r
16833 #define RTC_CR_COE_Pos (23U)
\r
16834 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
\r
16835 #define RTC_CR_COE RTC_CR_COE_Msk
\r
16836 #define RTC_CR_OSEL_Pos (21U)
\r
16837 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
\r
16838 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
\r
16839 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
\r
16840 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
\r
16841 #define RTC_CR_POL_Pos (20U)
\r
16842 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
\r
16843 #define RTC_CR_POL RTC_CR_POL_Msk
\r
16844 #define RTC_CR_COSEL_Pos (19U)
\r
16845 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
\r
16846 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
\r
16847 #define RTC_CR_BKP_Pos (18U)
\r
16848 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
\r
16849 #define RTC_CR_BKP RTC_CR_BKP_Msk
\r
16850 #define RTC_CR_SUB1H_Pos (17U)
\r
16851 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
\r
16852 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
\r
16853 #define RTC_CR_ADD1H_Pos (16U)
\r
16854 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
\r
16855 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
\r
16856 #define RTC_CR_TSIE_Pos (15U)
\r
16857 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
\r
16858 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
\r
16859 #define RTC_CR_WUTIE_Pos (14U)
\r
16860 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
\r
16861 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
\r
16862 #define RTC_CR_ALRBIE_Pos (13U)
\r
16863 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
\r
16864 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
\r
16865 #define RTC_CR_ALRAIE_Pos (12U)
\r
16866 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
\r
16867 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
\r
16868 #define RTC_CR_TSE_Pos (11U)
\r
16869 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
\r
16870 #define RTC_CR_TSE RTC_CR_TSE_Msk
\r
16871 #define RTC_CR_WUTE_Pos (10U)
\r
16872 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
\r
16873 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
\r
16874 #define RTC_CR_ALRBE_Pos (9U)
\r
16875 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
\r
16876 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
\r
16877 #define RTC_CR_ALRAE_Pos (8U)
\r
16878 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
\r
16879 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
\r
16880 #define RTC_CR_FMT_Pos (6U)
\r
16881 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
\r
16882 #define RTC_CR_FMT RTC_CR_FMT_Msk
\r
16883 #define RTC_CR_BYPSHAD_Pos (5U)
\r
16884 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
\r
16885 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
\r
16886 #define RTC_CR_REFCKON_Pos (4U)
\r
16887 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
\r
16888 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
\r
16889 #define RTC_CR_TSEDGE_Pos (3U)
\r
16890 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
\r
16891 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
\r
16892 #define RTC_CR_WUCKSEL_Pos (0U)
\r
16893 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
\r
16894 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
\r
16895 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
\r
16896 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
\r
16897 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
\r
16899 /******************** Bits definition for RTC_ISR register ******************/
\r
16900 #define RTC_ISR_ITSF_Pos (17U)
\r
16901 #define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
\r
16902 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
\r
16903 #define RTC_ISR_RECALPF_Pos (16U)
\r
16904 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
\r
16905 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
\r
16906 #define RTC_ISR_TAMP3F_Pos (15U)
\r
16907 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
\r
16908 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
\r
16909 #define RTC_ISR_TAMP2F_Pos (14U)
\r
16910 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
\r
16911 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
\r
16912 #define RTC_ISR_TAMP1F_Pos (13U)
\r
16913 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
\r
16914 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
\r
16915 #define RTC_ISR_TSOVF_Pos (12U)
\r
16916 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
\r
16917 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
\r
16918 #define RTC_ISR_TSF_Pos (11U)
\r
16919 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
\r
16920 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
\r
16921 #define RTC_ISR_WUTF_Pos (10U)
\r
16922 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
\r
16923 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
\r
16924 #define RTC_ISR_ALRBF_Pos (9U)
\r
16925 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
\r
16926 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
\r
16927 #define RTC_ISR_ALRAF_Pos (8U)
\r
16928 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
\r
16929 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
\r
16930 #define RTC_ISR_INIT_Pos (7U)
\r
16931 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
\r
16932 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
\r
16933 #define RTC_ISR_INITF_Pos (6U)
\r
16934 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
\r
16935 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
\r
16936 #define RTC_ISR_RSF_Pos (5U)
\r
16937 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
\r
16938 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
\r
16939 #define RTC_ISR_INITS_Pos (4U)
\r
16940 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
\r
16941 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
\r
16942 #define RTC_ISR_SHPF_Pos (3U)
\r
16943 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
\r
16944 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
\r
16945 #define RTC_ISR_WUTWF_Pos (2U)
\r
16946 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
\r
16947 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
\r
16948 #define RTC_ISR_ALRBWF_Pos (1U)
\r
16949 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
\r
16950 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
\r
16951 #define RTC_ISR_ALRAWF_Pos (0U)
\r
16952 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
\r
16953 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
\r
16955 /******************** Bits definition for RTC_PRER register *****************/
\r
16956 #define RTC_PRER_PREDIV_A_Pos (16U)
\r
16957 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
\r
16958 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
\r
16959 #define RTC_PRER_PREDIV_S_Pos (0U)
\r
16960 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
\r
16961 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
\r
16963 /******************** Bits definition for RTC_WUTR register *****************/
\r
16964 #define RTC_WUTR_WUT_Pos (0U)
\r
16965 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
\r
16966 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
\r
16968 /******************** Bits definition for RTC_ALRMAR register ***************/
\r
16969 #define RTC_ALRMAR_MSK4_Pos (31U)
\r
16970 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
\r
16971 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
\r
16972 #define RTC_ALRMAR_WDSEL_Pos (30U)
\r
16973 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
\r
16974 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
\r
16975 #define RTC_ALRMAR_DT_Pos (28U)
\r
16976 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
\r
16977 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
\r
16978 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
\r
16979 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
\r
16980 #define RTC_ALRMAR_DU_Pos (24U)
\r
16981 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
\r
16982 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
\r
16983 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
\r
16984 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
\r
16985 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
\r
16986 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
\r
16987 #define RTC_ALRMAR_MSK3_Pos (23U)
\r
16988 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
\r
16989 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
\r
16990 #define RTC_ALRMAR_PM_Pos (22U)
\r
16991 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
\r
16992 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
\r
16993 #define RTC_ALRMAR_HT_Pos (20U)
\r
16994 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
\r
16995 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
\r
16996 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
\r
16997 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
\r
16998 #define RTC_ALRMAR_HU_Pos (16U)
\r
16999 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
\r
17000 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
\r
17001 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
\r
17002 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
\r
17003 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
\r
17004 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
\r
17005 #define RTC_ALRMAR_MSK2_Pos (15U)
\r
17006 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
\r
17007 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
\r
17008 #define RTC_ALRMAR_MNT_Pos (12U)
\r
17009 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
\r
17010 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
\r
17011 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
\r
17012 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
\r
17013 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
\r
17014 #define RTC_ALRMAR_MNU_Pos (8U)
\r
17015 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
\r
17016 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
\r
17017 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
\r
17018 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
\r
17019 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
\r
17020 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
\r
17021 #define RTC_ALRMAR_MSK1_Pos (7U)
\r
17022 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
\r
17023 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
\r
17024 #define RTC_ALRMAR_ST_Pos (4U)
\r
17025 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
\r
17026 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
\r
17027 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
\r
17028 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
\r
17029 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
\r
17030 #define RTC_ALRMAR_SU_Pos (0U)
\r
17031 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
\r
17032 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
\r
17033 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
\r
17034 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
\r
17035 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
\r
17036 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
\r
17038 /******************** Bits definition for RTC_ALRMBR register ***************/
\r
17039 #define RTC_ALRMBR_MSK4_Pos (31U)
\r
17040 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
\r
17041 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
\r
17042 #define RTC_ALRMBR_WDSEL_Pos (30U)
\r
17043 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
\r
17044 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
\r
17045 #define RTC_ALRMBR_DT_Pos (28U)
\r
17046 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
\r
17047 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
\r
17048 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
\r
17049 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
\r
17050 #define RTC_ALRMBR_DU_Pos (24U)
\r
17051 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
\r
17052 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
\r
17053 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
\r
17054 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
\r
17055 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
\r
17056 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
\r
17057 #define RTC_ALRMBR_MSK3_Pos (23U)
\r
17058 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
\r
17059 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
\r
17060 #define RTC_ALRMBR_PM_Pos (22U)
\r
17061 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
\r
17062 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
\r
17063 #define RTC_ALRMBR_HT_Pos (20U)
\r
17064 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
\r
17065 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
\r
17066 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
\r
17067 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
\r
17068 #define RTC_ALRMBR_HU_Pos (16U)
\r
17069 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
\r
17070 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
\r
17071 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
\r
17072 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
\r
17073 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
\r
17074 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
\r
17075 #define RTC_ALRMBR_MSK2_Pos (15U)
\r
17076 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
\r
17077 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
\r
17078 #define RTC_ALRMBR_MNT_Pos (12U)
\r
17079 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
\r
17080 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
\r
17081 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
\r
17082 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
\r
17083 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
\r
17084 #define RTC_ALRMBR_MNU_Pos (8U)
\r
17085 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
\r
17086 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
\r
17087 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
\r
17088 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
\r
17089 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
\r
17090 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
\r
17091 #define RTC_ALRMBR_MSK1_Pos (7U)
\r
17092 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
\r
17093 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
\r
17094 #define RTC_ALRMBR_ST_Pos (4U)
\r
17095 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
\r
17096 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
\r
17097 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
\r
17098 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
\r
17099 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
\r
17100 #define RTC_ALRMBR_SU_Pos (0U)
\r
17101 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
\r
17102 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
\r
17103 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
\r
17104 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
\r
17105 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
\r
17106 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
\r
17108 /******************** Bits definition for RTC_WPR register ******************/
\r
17109 #define RTC_WPR_KEY_Pos (0U)
\r
17110 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
\r
17111 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
\r
17113 /******************** Bits definition for RTC_SSR register ******************/
\r
17114 #define RTC_SSR_SS_Pos (0U)
\r
17115 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
\r
17116 #define RTC_SSR_SS RTC_SSR_SS_Msk
\r
17118 /******************** Bits definition for RTC_SHIFTR register ***************/
\r
17119 #define RTC_SHIFTR_SUBFS_Pos (0U)
\r
17120 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
\r
17121 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
\r
17122 #define RTC_SHIFTR_ADD1S_Pos (31U)
\r
17123 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
\r
17124 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
\r
17126 /******************** Bits definition for RTC_TSTR register *****************/
\r
17127 #define RTC_TSTR_PM_Pos (22U)
\r
17128 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
\r
17129 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
\r
17130 #define RTC_TSTR_HT_Pos (20U)
\r
17131 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
\r
17132 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
\r
17133 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
\r
17134 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
\r
17135 #define RTC_TSTR_HU_Pos (16U)
\r
17136 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
\r
17137 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
\r
17138 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
\r
17139 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
\r
17140 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
\r
17141 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
\r
17142 #define RTC_TSTR_MNT_Pos (12U)
\r
17143 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
\r
17144 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
\r
17145 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
\r
17146 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
\r
17147 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
\r
17148 #define RTC_TSTR_MNU_Pos (8U)
\r
17149 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
\r
17150 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
\r
17151 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
\r
17152 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
\r
17153 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
\r
17154 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
\r
17155 #define RTC_TSTR_ST_Pos (4U)
\r
17156 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
\r
17157 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
\r
17158 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
\r
17159 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
\r
17160 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
\r
17161 #define RTC_TSTR_SU_Pos (0U)
\r
17162 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
\r
17163 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
\r
17164 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
\r
17165 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
\r
17166 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
\r
17167 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
\r
17169 /******************** Bits definition for RTC_TSDR register *****************/
\r
17170 #define RTC_TSDR_WDU_Pos (13U)
\r
17171 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
\r
17172 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
\r
17173 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
\r
17174 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
\r
17175 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
\r
17176 #define RTC_TSDR_MT_Pos (12U)
\r
17177 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
\r
17178 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
\r
17179 #define RTC_TSDR_MU_Pos (8U)
\r
17180 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
\r
17181 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
\r
17182 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
\r
17183 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
\r
17184 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
\r
17185 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
\r
17186 #define RTC_TSDR_DT_Pos (4U)
\r
17187 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
\r
17188 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
\r
17189 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
\r
17190 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
\r
17191 #define RTC_TSDR_DU_Pos (0U)
\r
17192 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
\r
17193 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
\r
17194 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
\r
17195 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
\r
17196 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
\r
17197 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
\r
17199 /******************** Bits definition for RTC_TSSSR register ****************/
\r
17200 #define RTC_TSSSR_SS_Pos (0U)
\r
17201 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
\r
17202 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
\r
17204 /******************** Bits definition for RTC_CALR register *****************/
\r
17205 #define RTC_CALR_CALP_Pos (15U)
\r
17206 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
\r
17207 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
\r
17208 #define RTC_CALR_CALW8_Pos (14U)
\r
17209 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
\r
17210 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
\r
17211 #define RTC_CALR_CALW16_Pos (13U)
\r
17212 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
\r
17213 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
\r
17214 #define RTC_CALR_CALM_Pos (0U)
\r
17215 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
\r
17216 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
\r
17217 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
\r
17218 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
\r
17219 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
\r
17220 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
\r
17221 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
\r
17222 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
\r
17223 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
\r
17224 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
\r
17225 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
\r
17227 /******************** Bits definition for RTC_TAMPCR register ***************/
\r
17228 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
\r
17229 #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
\r
17230 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
\r
17231 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
\r
17232 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
\r
17233 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
\r
17234 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
\r
17235 #define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
\r
17236 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
\r
17237 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
\r
17238 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
\r
17239 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
\r
17240 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
\r
17241 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
\r
17242 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
\r
17243 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
\r
17244 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
\r
17245 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
\r
17246 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
\r
17247 #define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
\r
17248 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
\r
17249 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
\r
17250 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
\r
17251 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
\r
17252 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
\r
17253 #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
\r
17254 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
\r
17255 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
\r
17256 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
\r
17257 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
\r
17258 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
\r
17259 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
\r
17260 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
\r
17261 #define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
\r
17262 #define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
\r
17263 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
\r
17264 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
\r
17265 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
\r
17266 #define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
\r
17267 #define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
\r
17268 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
\r
17269 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
\r
17270 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
\r
17271 #define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
\r
17272 #define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
\r
17273 #define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
\r
17274 #define RTC_TAMPCR_TAMPTS_Pos (7U)
\r
17275 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
\r
17276 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
\r
17277 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
\r
17278 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
\r
17279 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
\r
17280 #define RTC_TAMPCR_TAMP3E_Pos (5U)
\r
17281 #define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
\r
17282 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
\r
17283 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
\r
17284 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
\r
17285 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
\r
17286 #define RTC_TAMPCR_TAMP2E_Pos (3U)
\r
17287 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
\r
17288 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
\r
17289 #define RTC_TAMPCR_TAMPIE_Pos (2U)
\r
17290 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
\r
17291 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
\r
17292 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
\r
17293 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
\r
17294 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
\r
17295 #define RTC_TAMPCR_TAMP1E_Pos (0U)
\r
17296 #define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
\r
17297 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
\r
17299 /******************** Bits definition for RTC_ALRMASSR register *************/
\r
17300 #define RTC_ALRMASSR_MASKSS_Pos (24U)
\r
17301 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
\r
17302 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
\r
17303 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
\r
17304 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
\r
17305 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
\r
17306 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
\r
17307 #define RTC_ALRMASSR_SS_Pos (0U)
\r
17308 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
\r
17309 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
\r
17311 /******************** Bits definition for RTC_ALRMBSSR register *************/
\r
17312 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
\r
17313 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
\r
17314 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
\r
17315 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
\r
17316 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
\r
17317 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
\r
17318 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
\r
17319 #define RTC_ALRMBSSR_SS_Pos (0U)
\r
17320 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
\r
17321 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
\r
17323 /******************** Bits definition for RTC_OR register *******************/
\r
17324 #define RTC_OR_OUT_RMP_Pos (1U)
\r
17325 #define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
\r
17326 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
\r
17327 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
\r
17328 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
\r
17329 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
\r
17331 /******************** Bits definition for RTC_BKP0R register ****************/
\r
17332 #define RTC_BKP0R_Pos (0U)
\r
17333 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
\r
17334 #define RTC_BKP0R RTC_BKP0R_Msk
\r
17336 /******************** Bits definition for RTC_BKP1R register ****************/
\r
17337 #define RTC_BKP1R_Pos (0U)
\r
17338 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
\r
17339 #define RTC_BKP1R RTC_BKP1R_Msk
\r
17341 /******************** Bits definition for RTC_BKP2R register ****************/
\r
17342 #define RTC_BKP2R_Pos (0U)
\r
17343 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
\r
17344 #define RTC_BKP2R RTC_BKP2R_Msk
\r
17346 /******************** Bits definition for RTC_BKP3R register ****************/
\r
17347 #define RTC_BKP3R_Pos (0U)
\r
17348 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
\r
17349 #define RTC_BKP3R RTC_BKP3R_Msk
\r
17351 /******************** Bits definition for RTC_BKP4R register ****************/
\r
17352 #define RTC_BKP4R_Pos (0U)
\r
17353 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
\r
17354 #define RTC_BKP4R RTC_BKP4R_Msk
\r
17356 /******************** Bits definition for RTC_BKP5R register ****************/
\r
17357 #define RTC_BKP5R_Pos (0U)
\r
17358 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
\r
17359 #define RTC_BKP5R RTC_BKP5R_Msk
\r
17361 /******************** Bits definition for RTC_BKP6R register ****************/
\r
17362 #define RTC_BKP6R_Pos (0U)
\r
17363 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
\r
17364 #define RTC_BKP6R RTC_BKP6R_Msk
\r
17366 /******************** Bits definition for RTC_BKP7R register ****************/
\r
17367 #define RTC_BKP7R_Pos (0U)
\r
17368 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
\r
17369 #define RTC_BKP7R RTC_BKP7R_Msk
\r
17371 /******************** Bits definition for RTC_BKP8R register ****************/
\r
17372 #define RTC_BKP8R_Pos (0U)
\r
17373 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
\r
17374 #define RTC_BKP8R RTC_BKP8R_Msk
\r
17376 /******************** Bits definition for RTC_BKP9R register ****************/
\r
17377 #define RTC_BKP9R_Pos (0U)
\r
17378 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
\r
17379 #define RTC_BKP9R RTC_BKP9R_Msk
\r
17381 /******************** Bits definition for RTC_BKP10R register ***************/
\r
17382 #define RTC_BKP10R_Pos (0U)
\r
17383 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
\r
17384 #define RTC_BKP10R RTC_BKP10R_Msk
\r
17386 /******************** Bits definition for RTC_BKP11R register ***************/
\r
17387 #define RTC_BKP11R_Pos (0U)
\r
17388 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
\r
17389 #define RTC_BKP11R RTC_BKP11R_Msk
\r
17391 /******************** Bits definition for RTC_BKP12R register ***************/
\r
17392 #define RTC_BKP12R_Pos (0U)
\r
17393 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
\r
17394 #define RTC_BKP12R RTC_BKP12R_Msk
\r
17396 /******************** Bits definition for RTC_BKP13R register ***************/
\r
17397 #define RTC_BKP13R_Pos (0U)
\r
17398 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
\r
17399 #define RTC_BKP13R RTC_BKP13R_Msk
\r
17401 /******************** Bits definition for RTC_BKP14R register ***************/
\r
17402 #define RTC_BKP14R_Pos (0U)
\r
17403 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
\r
17404 #define RTC_BKP14R RTC_BKP14R_Msk
\r
17406 /******************** Bits definition for RTC_BKP15R register ***************/
\r
17407 #define RTC_BKP15R_Pos (0U)
\r
17408 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
\r
17409 #define RTC_BKP15R RTC_BKP15R_Msk
\r
17411 /******************** Bits definition for RTC_BKP16R register ***************/
\r
17412 #define RTC_BKP16R_Pos (0U)
\r
17413 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
\r
17414 #define RTC_BKP16R RTC_BKP16R_Msk
\r
17416 /******************** Bits definition for RTC_BKP17R register ***************/
\r
17417 #define RTC_BKP17R_Pos (0U)
\r
17418 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
\r
17419 #define RTC_BKP17R RTC_BKP17R_Msk
\r
17421 /******************** Bits definition for RTC_BKP18R register ***************/
\r
17422 #define RTC_BKP18R_Pos (0U)
\r
17423 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
\r
17424 #define RTC_BKP18R RTC_BKP18R_Msk
\r
17426 /******************** Bits definition for RTC_BKP19R register ***************/
\r
17427 #define RTC_BKP19R_Pos (0U)
\r
17428 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
\r
17429 #define RTC_BKP19R RTC_BKP19R_Msk
\r
17431 /******************** Bits definition for RTC_BKP20R register ***************/
\r
17432 #define RTC_BKP20R_Pos (0U)
\r
17433 #define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
\r
17434 #define RTC_BKP20R RTC_BKP20R_Msk
\r
17436 /******************** Bits definition for RTC_BKP21R register ***************/
\r
17437 #define RTC_BKP21R_Pos (0U)
\r
17438 #define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
\r
17439 #define RTC_BKP21R RTC_BKP21R_Msk
\r
17441 /******************** Bits definition for RTC_BKP22R register ***************/
\r
17442 #define RTC_BKP22R_Pos (0U)
\r
17443 #define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
\r
17444 #define RTC_BKP22R RTC_BKP22R_Msk
\r
17446 /******************** Bits definition for RTC_BKP23R register ***************/
\r
17447 #define RTC_BKP23R_Pos (0U)
\r
17448 #define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
\r
17449 #define RTC_BKP23R RTC_BKP23R_Msk
\r
17451 /******************** Bits definition for RTC_BKP24R register ***************/
\r
17452 #define RTC_BKP24R_Pos (0U)
\r
17453 #define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
\r
17454 #define RTC_BKP24R RTC_BKP24R_Msk
\r
17456 /******************** Bits definition for RTC_BKP25R register ***************/
\r
17457 #define RTC_BKP25R_Pos (0U)
\r
17458 #define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
\r
17459 #define RTC_BKP25R RTC_BKP25R_Msk
\r
17461 /******************** Bits definition for RTC_BKP26R register ***************/
\r
17462 #define RTC_BKP26R_Pos (0U)
\r
17463 #define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
\r
17464 #define RTC_BKP26R RTC_BKP26R_Msk
\r
17466 /******************** Bits definition for RTC_BKP27R register ***************/
\r
17467 #define RTC_BKP27R_Pos (0U)
\r
17468 #define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
\r
17469 #define RTC_BKP27R RTC_BKP27R_Msk
\r
17471 /******************** Bits definition for RTC_BKP28R register ***************/
\r
17472 #define RTC_BKP28R_Pos (0U)
\r
17473 #define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
\r
17474 #define RTC_BKP28R RTC_BKP28R_Msk
\r
17476 /******************** Bits definition for RTC_BKP29R register ***************/
\r
17477 #define RTC_BKP29R_Pos (0U)
\r
17478 #define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
\r
17479 #define RTC_BKP29R RTC_BKP29R_Msk
\r
17481 /******************** Bits definition for RTC_BKP30R register ***************/
\r
17482 #define RTC_BKP30R_Pos (0U)
\r
17483 #define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
\r
17484 #define RTC_BKP30R RTC_BKP30R_Msk
\r
17486 /******************** Bits definition for RTC_BKP31R register ***************/
\r
17487 #define RTC_BKP31R_Pos (0U)
\r
17488 #define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
\r
17489 #define RTC_BKP31R RTC_BKP31R_Msk
\r
17491 /******************** Number of backup registers ******************************/
\r
17492 #define RTC_BKP_NUMBER_Pos (5U)
\r
17493 #define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos) /*!< 0x00000020 */
\r
17494 #define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
\r
17496 /******************************************************************************/
\r
17498 /* SPDIF-RX Interface */
\r
17500 /******************************************************************************/
\r
17501 /******************** Bit definition for SPDIF_CR register ******************/
\r
17502 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
\r
17503 #define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
\r
17504 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
\r
17505 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
\r
17506 #define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
\r
17507 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
\r
17508 #define SPDIFRX_CR_RXSTEO_Pos (3U)
\r
17509 #define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
\r
17510 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
\r
17511 #define SPDIFRX_CR_DRFMT_Pos (4U)
\r
17512 #define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
\r
17513 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
\r
17514 #define SPDIFRX_CR_PMSK_Pos (6U)
\r
17515 #define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
\r
17516 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
\r
17517 #define SPDIFRX_CR_VMSK_Pos (7U)
\r
17518 #define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
\r
17519 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
\r
17520 #define SPDIFRX_CR_CUMSK_Pos (8U)
\r
17521 #define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
\r
17522 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
\r
17523 #define SPDIFRX_CR_PTMSK_Pos (9U)
\r
17524 #define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
\r
17525 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
\r
17526 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
\r
17527 #define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
\r
17528 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
\r
17529 #define SPDIFRX_CR_CHSEL_Pos (11U)
\r
17530 #define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
\r
17531 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
\r
17532 #define SPDIFRX_CR_NBTR_Pos (12U)
\r
17533 #define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
\r
17534 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
\r
17535 #define SPDIFRX_CR_WFA_Pos (14U)
\r
17536 #define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
\r
17537 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
\r
17538 #define SPDIFRX_CR_INSEL_Pos (16U)
\r
17539 #define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
\r
17540 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
\r
17541 #define SPDIFRX_CR_CKSEN_Pos (20U)
\r
17542 #define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) /*!< 0x00100000 */
\r
17543 #define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk /*!<Symbol Clock Enable */
\r
17544 #define SPDIFRX_CR_CKSBKPEN_Pos (21U)
\r
17545 #define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) /*!< 0x00200000 */
\r
17546 #define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk /*!<Backup Symbol Clock Enable */
\r
17548 /******************* Bit definition for SPDIFRX_IMR register *******************/
\r
17549 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
\r
17550 #define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
\r
17551 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
\r
17552 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
\r
17553 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
\r
17554 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
\r
17555 #define SPDIFRX_IMR_PERRIE_Pos (2U)
\r
17556 #define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
\r
17557 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
\r
17558 #define SPDIFRX_IMR_OVRIE_Pos (3U)
\r
17559 #define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
\r
17560 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
\r
17561 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
\r
17562 #define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
\r
17563 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
\r
17564 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
\r
17565 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
\r
17566 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
\r
17567 #define SPDIFRX_IMR_IFEIE_Pos (6U)
\r
17568 #define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
\r
17569 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
\r
17571 /******************* Bit definition for SPDIFRX_SR register *******************/
\r
17572 #define SPDIFRX_SR_RXNE_Pos (0U)
\r
17573 #define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
\r
17574 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
\r
17575 #define SPDIFRX_SR_CSRNE_Pos (1U)
\r
17576 #define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
\r
17577 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
\r
17578 #define SPDIFRX_SR_PERR_Pos (2U)
\r
17579 #define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
\r
17580 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
\r
17581 #define SPDIFRX_SR_OVR_Pos (3U)
\r
17582 #define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
\r
17583 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
\r
17584 #define SPDIFRX_SR_SBD_Pos (4U)
\r
17585 #define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
\r
17586 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
\r
17587 #define SPDIFRX_SR_SYNCD_Pos (5U)
\r
17588 #define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
\r
17589 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
\r
17590 #define SPDIFRX_SR_FERR_Pos (6U)
\r
17591 #define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
\r
17592 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
\r
17593 #define SPDIFRX_SR_SERR_Pos (7U)
\r
17594 #define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
\r
17595 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
\r
17596 #define SPDIFRX_SR_TERR_Pos (8U)
\r
17597 #define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
\r
17598 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
\r
17599 #define SPDIFRX_SR_WIDTH5_Pos (16U)
\r
17600 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
\r
17601 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
\r
17603 /******************* Bit definition for SPDIFRX_IFCR register *******************/
\r
17604 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
\r
17605 #define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
\r
17606 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
\r
17607 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
\r
17608 #define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
\r
17609 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
\r
17610 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
\r
17611 #define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
\r
17612 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
\r
17613 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
\r
17614 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
\r
17615 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
\r
17617 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
\r
17618 #define SPDIFRX_DR0_DR_Pos (0U)
\r
17619 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
\r
17620 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
\r
17621 #define SPDIFRX_DR0_PE_Pos (24U)
\r
17622 #define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
\r
17623 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
\r
17624 #define SPDIFRX_DR0_V_Pos (25U)
\r
17625 #define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
\r
17626 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
\r
17627 #define SPDIFRX_DR0_U_Pos (26U)
\r
17628 #define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
\r
17629 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
\r
17630 #define SPDIFRX_DR0_C_Pos (27U)
\r
17631 #define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
\r
17632 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
\r
17633 #define SPDIFRX_DR0_PT_Pos (28U)
\r
17634 #define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
\r
17635 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
\r
17637 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
\r
17638 #define SPDIFRX_DR1_DR_Pos (8U)
\r
17639 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
\r
17640 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
\r
17641 #define SPDIFRX_DR1_PT_Pos (4U)
\r
17642 #define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
\r
17643 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
\r
17644 #define SPDIFRX_DR1_C_Pos (3U)
\r
17645 #define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
\r
17646 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
\r
17647 #define SPDIFRX_DR1_U_Pos (2U)
\r
17648 #define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
\r
17649 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
\r
17650 #define SPDIFRX_DR1_V_Pos (1U)
\r
17651 #define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
\r
17652 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
\r
17653 #define SPDIFRX_DR1_PE_Pos (0U)
\r
17654 #define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
\r
17655 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
\r
17657 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
\r
17658 #define SPDIFRX_DR1_DRNL1_Pos (16U)
\r
17659 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
\r
17660 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
\r
17661 #define SPDIFRX_DR1_DRNL2_Pos (0U)
\r
17662 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
\r
17663 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
\r
17665 /******************* Bit definition for SPDIFRX_CSR register *******************/
\r
17666 #define SPDIFRX_CSR_USR_Pos (0U)
\r
17667 #define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
\r
17668 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
\r
17669 #define SPDIFRX_CSR_CS_Pos (16U)
\r
17670 #define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
\r
17671 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
\r
17672 #define SPDIFRX_CSR_SOB_Pos (24U)
\r
17673 #define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
\r
17674 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
\r
17676 /******************* Bit definition for SPDIFRX_DIR register *******************/
\r
17677 #define SPDIFRX_DIR_THI_Pos (0U)
\r
17678 #define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
\r
17679 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
\r
17680 #define SPDIFRX_DIR_TLO_Pos (16U)
\r
17681 #define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
\r
17682 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
\r
17684 /******************* Bit definition for SPDIFRX_VERR register *******************/
\r
17685 #define SPDIFRX_VERR_MINREV_Pos (0U)
\r
17686 #define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */
\r
17687 #define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!<SPDIFRX Minor revision */
\r
17688 #define SPDIFRX_VERR_MAJREV_Pos (4U)
\r
17689 #define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
\r
17690 #define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!<SPDIFRX Major revision */
\r
17692 /******************* Bit definition for SPDIFRX_IDR register *******************/
\r
17693 #define SPDIFRX_IDR_ID_Pos (0U)
\r
17694 #define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos) /*!< 0xFFFFFFFF */
\r
17695 #define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk /*!<SPDIFRX identifier */
\r
17697 /******************* Bit definition for SPDIFRX_SIDR register *******************/
\r
17698 #define SPDIFRX_SIDR_SID_Pos (0U)
\r
17699 #define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
\r
17700 #define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!<Size of the memory region allocated to SPDIFRX registers */
\r
17702 /******************************************************************************/
\r
17704 /* Serial Audio Interface */
\r
17706 /******************************************************************************/
\r
17707 /******************************* SAI VERSION ********************************/
\r
17708 #define SAI_VER_V2_X
\r
17710 /******************** Bit definition for SAI_GCR register *******************/
\r
17711 #define SAI_GCR_SYNCIN_Pos (0U)
\r
17712 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
\r
17713 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
\r
17714 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
\r
17715 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
\r
17717 #define SAI_GCR_SYNCOUT_Pos (4U)
\r
17718 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
\r
17719 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
\r
17720 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
\r
17721 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
\r
17723 /******************* Bit definition for SAI_xCR1 register *******************/
\r
17724 #define SAI_xCR1_MODE_Pos (0U)
\r
17725 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
\r
17726 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
\r
17727 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
\r
17728 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
\r
17730 #define SAI_xCR1_PRTCFG_Pos (2U)
\r
17731 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
\r
17732 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
\r
17733 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
\r
17734 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
\r
17736 #define SAI_xCR1_DS_Pos (5U)
\r
17737 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
\r
17738 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
\r
17739 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
\r
17740 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
\r
17741 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
\r
17743 #define SAI_xCR1_LSBFIRST_Pos (8U)
\r
17744 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
\r
17745 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
\r
17746 #define SAI_xCR1_CKSTR_Pos (9U)
\r
17747 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
\r
17748 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
\r
17750 #define SAI_xCR1_SYNCEN_Pos (10U)
\r
17751 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
\r
17752 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
\r
17753 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
\r
17754 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
\r
17756 #define SAI_xCR1_MONO_Pos (12U)
\r
17757 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
\r
17758 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
\r
17759 #define SAI_xCR1_OUTDRIV_Pos (13U)
\r
17760 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
\r
17761 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
\r
17762 #define SAI_xCR1_SAIEN_Pos (16U)
\r
17763 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
\r
17764 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
\r
17765 #define SAI_xCR1_DMAEN_Pos (17U)
\r
17766 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
\r
17767 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
\r
17768 #define SAI_xCR1_NODIV_Pos (19U)
\r
17769 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
\r
17770 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
\r
17772 #define SAI_xCR1_MCKDIV_Pos (20U)
\r
17773 #define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
\r
17774 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
\r
17775 #define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
\r
17776 #define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
\r
17777 #define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
\r
17778 #define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
\r
17779 #define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */
\r
17780 #define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */
\r
17782 #define SAI_xCR1_MCKEN_Pos (27U)
\r
17783 #define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
\r
17784 #define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master ClocK enable */
\r
17786 #define SAI_xCR1_OSR_Pos (26U)
\r
17787 #define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
\r
17788 #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */
\r
17790 /* Legacy define */
\r
17791 #define SAI_xCR1_NOMCK SAI_xCR1_NODIV
\r
17793 /******************* Bit definition for SAI_xCR2 register *******************/
\r
17794 #define SAI_xCR2_FTH_Pos (0U)
\r
17795 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
\r
17796 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
\r
17797 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
\r
17798 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
\r
17799 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
\r
17801 #define SAI_xCR2_FFLUSH_Pos (3U)
\r
17802 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
\r
17803 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
\r
17804 #define SAI_xCR2_TRIS_Pos (4U)
\r
17805 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
\r
17806 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
\r
17807 #define SAI_xCR2_MUTE_Pos (5U)
\r
17808 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
\r
17809 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
\r
17810 #define SAI_xCR2_MUTEVAL_Pos (6U)
\r
17811 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
\r
17812 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
\r
17814 #define SAI_xCR2_MUTECNT_Pos (7U)
\r
17815 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
\r
17816 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
\r
17817 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
\r
17818 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
\r
17819 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
\r
17820 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
\r
17821 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
\r
17822 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
\r
17824 #define SAI_xCR2_CPL_Pos (13U)
\r
17825 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
\r
17826 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
\r
17828 #define SAI_xCR2_COMP_Pos (14U)
\r
17829 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
\r
17830 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
\r
17831 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
\r
17832 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
\r
17834 /****************** Bit definition for SAI_xFRCR register *******************/
\r
17835 #define SAI_xFRCR_FRL_Pos (0U)
\r
17836 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
\r
17837 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](FRame Length) */
\r
17838 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
\r
17839 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
\r
17840 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
\r
17841 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
\r
17842 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
\r
17843 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
\r
17844 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
\r
17845 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
\r
17847 #define SAI_xFRCR_FSALL_Pos (8U)
\r
17848 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
\r
17849 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */
\r
17850 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
\r
17851 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
\r
17852 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
\r
17853 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
\r
17854 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
\r
17855 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
\r
17856 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
\r
17858 #define SAI_xFRCR_FSDEF_Pos (16U)
\r
17859 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
\r
17860 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
\r
17861 #define SAI_xFRCR_FSPOL_Pos (17U)
\r
17862 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
\r
17863 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
\r
17864 #define SAI_xFRCR_FSOFF_Pos (18U)
\r
17865 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
\r
17866 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
\r
17868 /* Legacy define */
\r
17869 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
\r
17871 /****************** Bit definition for SAI_xSLOTR register *******************/
\r
17872 #define SAI_xSLOTR_FBOFF_Pos (0U)
\r
17873 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
\r
17874 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FBOFF[4:0](First Bit Offset) */
\r
17875 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
\r
17876 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
\r
17877 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
\r
17878 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
\r
17879 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
\r
17881 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
\r
17882 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
\r
17883 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
\r
17884 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
\r
17885 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
\r
17887 #define SAI_xSLOTR_NBSLOT_Pos (8U)
\r
17888 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
\r
17889 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
\r
17890 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
\r
17891 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
\r
17892 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
\r
17893 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
\r
17895 #define SAI_xSLOTR_SLOTEN_Pos (16U)
\r
17896 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
\r
17897 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
\r
17899 /******************* Bit definition for SAI_xIMR register *******************/
\r
17900 #define SAI_xIMR_OVRUDRIE_Pos (0U)
\r
17901 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
\r
17902 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
\r
17903 #define SAI_xIMR_MUTEDETIE_Pos (1U)
\r
17904 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
\r
17905 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
\r
17906 #define SAI_xIMR_WCKCFGIE_Pos (2U)
\r
17907 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
\r
17908 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
\r
17909 #define SAI_xIMR_FREQIE_Pos (3U)
\r
17910 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
\r
17911 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
\r
17912 #define SAI_xIMR_CNRDYIE_Pos (4U)
\r
17913 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
\r
17914 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
\r
17915 #define SAI_xIMR_AFSDETIE_Pos (5U)
\r
17916 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
\r
17917 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
\r
17918 #define SAI_xIMR_LFSDETIE_Pos (6U)
\r
17919 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
\r
17920 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
\r
17922 /******************** Bit definition for SAI_xSR register *******************/
\r
17923 #define SAI_xSR_OVRUDR_Pos (0U)
\r
17924 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
\r
17925 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
\r
17926 #define SAI_xSR_MUTEDET_Pos (1U)
\r
17927 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
\r
17928 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
\r
17929 #define SAI_xSR_WCKCFG_Pos (2U)
\r
17930 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
\r
17931 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
\r
17932 #define SAI_xSR_FREQ_Pos (3U)
\r
17933 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
\r
17934 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
\r
17935 #define SAI_xSR_CNRDY_Pos (4U)
\r
17936 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
\r
17937 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
\r
17938 #define SAI_xSR_AFSDET_Pos (5U)
\r
17939 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
\r
17940 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
\r
17941 #define SAI_xSR_LFSDET_Pos (6U)
\r
17942 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
\r
17943 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
\r
17945 #define SAI_xSR_FLVL_Pos (16U)
\r
17946 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
\r
17947 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
\r
17948 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
\r
17949 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
\r
17950 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
\r
17952 /****************** Bit definition for SAI_xCLRFR register ******************/
\r
17953 #define SAI_xCLRFR_COVRUDR_Pos (0U)
\r
17954 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
\r
17955 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
\r
17956 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
\r
17957 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
\r
17958 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
\r
17959 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
\r
17960 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
\r
17961 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
\r
17962 #define SAI_xCLRFR_CFREQ_Pos (3U)
\r
17963 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
\r
17964 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
\r
17965 #define SAI_xCLRFR_CCNRDY_Pos (4U)
\r
17966 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
\r
17967 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
\r
17968 #define SAI_xCLRFR_CAFSDET_Pos (5U)
\r
17969 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
\r
17970 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
\r
17971 #define SAI_xCLRFR_CLFSDET_Pos (6U)
\r
17972 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
\r
17973 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
\r
17975 /****************** Bit definition for SAI_xDR register *********************/
\r
17976 #define SAI_xDR_DATA_Pos (0U)
\r
17977 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
\r
17978 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
\r
17980 /******************* Bit definition for SAI_PDMCR register ******************/
\r
17981 #define SAI_PDMCR_PDMEN_Pos (0U)
\r
17982 #define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
\r
17983 #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM Enable */
\r
17985 #define SAI_PDMCR_MICNBR_Pos (4U)
\r
17986 #define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
\r
17987 #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<Number of microphones */
\r
17988 #define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
\r
17989 #define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
\r
17991 #define SAI_PDMCR_CKEN1_Pos (8U)
\r
17992 #define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
\r
17993 #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock enable of bitstream clock number 1 */
\r
17994 #define SAI_PDMCR_CKEN2_Pos (9U)
\r
17995 #define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
\r
17996 #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock enable of bitstream clock number 2 */
\r
17997 #define SAI_PDMCR_CKEN3_Pos (10U)
\r
17998 #define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
\r
17999 #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock enable of bitstream clock number 3 */
\r
18000 #define SAI_PDMCR_CKEN4_Pos (11U)
\r
18001 #define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
\r
18002 #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock enable of bitstream clock number 4 */
\r
18004 /****************** Bit definition for SAI_PDMDLY register ******************/
\r
18005 #define SAI_PDMDLY_DLYM1L_Pos (0U)
\r
18006 #define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
\r
18007 #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
\r
18008 #define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
\r
18009 #define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
\r
18010 #define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
\r
18012 #define SAI_PDMDLY_DLYM1R_Pos (4U)
\r
18013 #define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
\r
18014 #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
\r
18015 #define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
\r
18016 #define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
\r
18017 #define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
\r
18019 #define SAI_PDMDLY_DLYM2L_Pos (8U)
\r
18020 #define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
\r
18021 #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
\r
18022 #define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
\r
18023 #define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
\r
18024 #define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
\r
18026 #define SAI_PDMDLY_DLYM2R_Pos (12U)
\r
18027 #define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
\r
18028 #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
\r
18029 #define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
\r
18030 #define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
\r
18031 #define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
\r
18033 #define SAI_PDMDLY_DLYM3L_Pos (16U)
\r
18034 #define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
\r
18035 #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
\r
18036 #define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
\r
18037 #define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
\r
18038 #define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
\r
18040 #define SAI_PDMDLY_DLYM3R_Pos (20U)
\r
18041 #define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
\r
18042 #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
\r
18043 #define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
\r
18044 #define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
\r
18045 #define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
\r
18047 #define SAI_PDMDLY_DLYM4L_Pos (24U)
\r
18048 #define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
\r
18049 #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
\r
18050 #define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
\r
18051 #define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
\r
18052 #define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
\r
18054 #define SAI_PDMDLY_DLYM4R_Pos (28U)
\r
18055 #define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
\r
18056 #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
\r
18057 #define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
\r
18058 #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
\r
18059 #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
\r
18061 /******************************************************************************/
\r
18063 /* SDMMC Interface */
\r
18065 /******************************************************************************/
\r
18066 /****************** Bit definition for SDMMC_POWER register ******************/
\r
18067 #define SDMMC_POWER_PWRCTRL_Pos (0U)
\r
18068 #define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
\r
18069 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
\r
18070 #define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
\r
18071 #define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
\r
18072 #define SDMMC_POWER_VSWITCH_Pos (2U)
\r
18073 #define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
\r
18074 #define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
\r
18075 #define SDMMC_POWER_VSWITCHEN_Pos (3U)
\r
18076 #define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
\r
18077 #define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
\r
18078 #define SDMMC_POWER_DIRPOL_Pos (4U)
\r
18079 #define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
\r
18080 #define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
\r
18082 /****************** Bit definition for SDMMC_CLKCR register ******************/
\r
18083 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
\r
18084 #define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
\r
18085 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
\r
18086 #define SDMMC_CLKCR_PWRSAV_Pos (12U)
\r
18087 #define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
\r
18088 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
\r
18090 #define SDMMC_CLKCR_WIDBUS_Pos (14U)
\r
18091 #define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
\r
18092 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
\r
18093 #define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
\r
18094 #define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
\r
18096 #define SDMMC_CLKCR_NEGEDGE_Pos (16U)
\r
18097 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
\r
18098 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
\r
18099 #define SDMMC_CLKCR_HWFC_EN_Pos (17U)
\r
18100 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
\r
18101 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
\r
18102 #define SDMMC_CLKCR_DDR_Pos (18U)
\r
18103 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
\r
18104 #define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
\r
18105 #define SDMMC_CLKCR_BUSSPEED_Pos (19U)
\r
18106 #define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
\r
18107 #define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
\r
18108 #define SDMMC_CLKCR_SELCLKRX_Pos (20U)
\r
18109 #define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
\r
18110 #define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
\r
18111 #define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
\r
18112 #define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
\r
18114 /******************* Bit definition for SDMMC_ARG register *******************/
\r
18115 #define SDMMC_ARG_CMDARG_Pos (0U)
\r
18116 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
\r
18117 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
\r
18119 /******************* Bit definition for SDMMC_CMD register *******************/
\r
18120 #define SDMMC_CMD_CMDINDEX_Pos (0U)
\r
18121 #define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
\r
18122 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
\r
18123 #define SDMMC_CMD_CMDTRANS_Pos (6U)
\r
18124 #define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
\r
18125 #define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
\r
18126 #define SDMMC_CMD_CMDSTOP_Pos (7U)
\r
18127 #define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
\r
18128 #define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
\r
18130 #define SDMMC_CMD_WAITRESP_Pos (8U)
\r
18131 #define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
\r
18132 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
\r
18133 #define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
\r
18134 #define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
\r
18136 #define SDMMC_CMD_WAITINT_Pos (10U)
\r
18137 #define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
\r
18138 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
\r
18139 #define SDMMC_CMD_WAITPEND_Pos (11U)
\r
18140 #define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
\r
18141 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
\r
18142 #define SDMMC_CMD_CPSMEN_Pos (12U)
\r
18143 #define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
\r
18144 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
\r
18145 #define SDMMC_CMD_DTHOLD_Pos (13U)
\r
18146 #define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
\r
18147 #define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
\r
18148 #define SDMMC_CMD_BOOTMODE_Pos (14U)
\r
18149 #define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
\r
18150 #define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
\r
18151 #define SDMMC_CMD_BOOTEN_Pos (15U)
\r
18152 #define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
\r
18153 #define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
\r
18154 #define SDMMC_CMD_CMDSUSPEND_Pos (16U)
\r
18155 #define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
\r
18156 #define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
\r
18158 /***************** Bit definition for SDMMC_RESPCMD register *****************/
\r
18159 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
\r
18160 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
\r
18161 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
\r
18163 /****************** Bit definition for SDMMC_RESP0 register ******************/
\r
18164 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
\r
18165 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
\r
18166 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
\r
18168 /****************** Bit definition for SDMMC_RESP1 register ******************/
\r
18169 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
\r
18170 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
\r
18171 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
\r
18173 /****************** Bit definition for SDMMC_RESP2 register ******************/
\r
18174 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
\r
18175 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
\r
18176 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
\r
18178 /****************** Bit definition for SDMMC_RESP3 register ******************/
\r
18179 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
\r
18180 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
\r
18181 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
\r
18183 /****************** Bit definition for SDMMC_RESP4 register ******************/
\r
18184 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
\r
18185 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
\r
18186 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
\r
18188 /****************** Bit definition for SDMMC_DTIMER register *****************/
\r
18189 #define SDMMC_DTIMER_DATATIME_Pos (0U)
\r
18190 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
\r
18191 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
\r
18193 /****************** Bit definition for SDMMC_DLEN register *******************/
\r
18194 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
\r
18195 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
\r
18196 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
\r
18198 /****************** Bit definition for SDMMC_DCTRL register ******************/
\r
18199 #define SDMMC_DCTRL_DTEN_Pos (0U)
\r
18200 #define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
\r
18201 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
\r
18202 #define SDMMC_DCTRL_DTDIR_Pos (1U)
\r
18203 #define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
\r
18204 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
\r
18205 #define SDMMC_DCTRL_DTMODE_Pos (2U)
\r
18206 #define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
\r
18207 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
\r
18208 #define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
\r
18209 #define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
\r
18211 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
\r
18212 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
\r
18213 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
\r
18214 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
\r
18215 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
\r
18216 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
\r
18217 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
\r
18219 #define SDMMC_DCTRL_RWSTART_Pos (8U)
\r
18220 #define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
\r
18221 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
\r
18222 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
\r
18223 #define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
\r
18224 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
\r
18225 #define SDMMC_DCTRL_RWMOD_Pos (10U)
\r
18226 #define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
\r
18227 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
\r
18228 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
\r
18229 #define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
\r
18230 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
\r
18231 #define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
\r
18232 #define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
\r
18233 #define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
\r
18234 #define SDMMC_DCTRL_FIFORST_Pos (13U)
\r
18235 #define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
\r
18236 #define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
\r
18238 /****************** Bit definition for SDMMC_DCOUNT register *****************/
\r
18239 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
\r
18240 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
\r
18241 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
\r
18243 /****************** Bit definition for SDMMC_STA register ********************/
\r
18244 #define SDMMC_STA_CCRCFAIL_Pos (0U)
\r
18245 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
\r
18246 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
\r
18247 #define SDMMC_STA_DCRCFAIL_Pos (1U)
\r
18248 #define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
\r
18249 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
\r
18250 #define SDMMC_STA_CTIMEOUT_Pos (2U)
\r
18251 #define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
\r
18252 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
\r
18253 #define SDMMC_STA_DTIMEOUT_Pos (3U)
\r
18254 #define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
\r
18255 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
\r
18256 #define SDMMC_STA_TXUNDERR_Pos (4U)
\r
18257 #define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
\r
18258 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
\r
18259 #define SDMMC_STA_RXOVERR_Pos (5U)
\r
18260 #define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
\r
18261 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
\r
18262 #define SDMMC_STA_CMDREND_Pos (6U)
\r
18263 #define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
\r
18264 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
\r
18265 #define SDMMC_STA_CMDSENT_Pos (7U)
\r
18266 #define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
\r
18267 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
\r
18268 #define SDMMC_STA_DATAEND_Pos (8U)
\r
18269 #define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
\r
18270 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
\r
18271 #define SDMMC_STA_DHOLD_Pos (9U)
\r
18272 #define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
\r
18273 #define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
\r
18274 #define SDMMC_STA_DBCKEND_Pos (10U)
\r
18275 #define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
\r
18276 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
\r
18277 #define SDMMC_STA_DABORT_Pos (11U)
\r
18278 #define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
\r
18279 #define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
\r
18280 #define SDMMC_STA_DPSMACT_Pos (12U)
\r
18281 #define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */
\r
18282 #define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */
\r
18283 #define SDMMC_STA_CPSMACT_Pos (13U)
\r
18284 #define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */
\r
18285 #define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
\r
18286 #define SDMMC_STA_TXFIFOHE_Pos (14U)
\r
18287 #define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
\r
18288 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
\r
18289 #define SDMMC_STA_RXFIFOHF_Pos (15U)
\r
18290 #define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
\r
18291 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
\r
18292 #define SDMMC_STA_TXFIFOF_Pos (16U)
\r
18293 #define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
\r
18294 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
\r
18295 #define SDMMC_STA_RXFIFOF_Pos (17U)
\r
18296 #define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
\r
18297 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
\r
18298 #define SDMMC_STA_TXFIFOE_Pos (18U)
\r
18299 #define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
\r
18300 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
\r
18301 #define SDMMC_STA_RXFIFOE_Pos (19U)
\r
18302 #define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
\r
18303 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
\r
18304 #define SDMMC_STA_BUSYD0_Pos (20U)
\r
18305 #define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
\r
18306 #define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
\r
18307 #define SDMMC_STA_BUSYD0END_Pos (21U)
\r
18308 #define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
\r
18309 #define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
\r
18310 #define SDMMC_STA_SDIOIT_Pos (22U)
\r
18311 #define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
\r
18312 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
\r
18313 #define SDMMC_STA_ACKFAIL_Pos (23U)
\r
18314 #define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
\r
18315 #define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
\r
18316 #define SDMMC_STA_ACKTIMEOUT_Pos (24U)
\r
18317 #define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
\r
18318 #define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
\r
18319 #define SDMMC_STA_VSWEND_Pos (25U)
\r
18320 #define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
\r
18321 #define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
\r
18322 #define SDMMC_STA_CKSTOP_Pos (26U)
\r
18323 #define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
\r
18324 #define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
\r
18325 #define SDMMC_STA_IDMATE_Pos (27U)
\r
18326 #define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
\r
18327 #define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
\r
18328 #define SDMMC_STA_IDMABTC_Pos (28U)
\r
18329 #define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
\r
18330 #define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
\r
18332 /******************* Bit definition for SDMMC_ICR register *******************/
\r
18333 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
\r
18334 #define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
\r
18335 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
\r
18336 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
\r
18337 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
\r
18338 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
\r
18339 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
\r
18340 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
\r
18341 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
\r
18342 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
\r
18343 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
\r
18344 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
\r
18345 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
\r
18346 #define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
\r
18347 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
\r
18348 #define SDMMC_ICR_RXOVERRC_Pos (5U)
\r
18349 #define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
\r
18350 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
\r
18351 #define SDMMC_ICR_CMDRENDC_Pos (6U)
\r
18352 #define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
\r
18353 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
\r
18354 #define SDMMC_ICR_CMDSENTC_Pos (7U)
\r
18355 #define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
\r
18356 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
\r
18357 #define SDMMC_ICR_DATAENDC_Pos (8U)
\r
18358 #define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
\r
18359 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
\r
18360 #define SDMMC_ICR_DHOLDC_Pos (9U)
\r
18361 #define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
\r
18362 #define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
\r
18363 #define SDMMC_ICR_DBCKENDC_Pos (10U)
\r
18364 #define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
\r
18365 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
\r
18366 #define SDMMC_ICR_DABORTC_Pos (11U)
\r
18367 #define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
\r
18368 #define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
\r
18369 #define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
\r
18370 #define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
\r
18371 #define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
\r
18372 #define SDMMC_ICR_SDIOITC_Pos (22U)
\r
18373 #define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
\r
18374 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
\r
18375 #define SDMMC_ICR_ACKFAILC_Pos (23U)
\r
18376 #define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
\r
18377 #define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
\r
18378 #define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
\r
18379 #define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
\r
18380 #define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
\r
18381 #define SDMMC_ICR_VSWENDC_Pos (25U)
\r
18382 #define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
\r
18383 #define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
\r
18384 #define SDMMC_ICR_CKSTOPC_Pos (26U)
\r
18385 #define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
\r
18386 #define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
\r
18387 #define SDMMC_ICR_IDMATEC_Pos (27U)
\r
18388 #define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
\r
18389 #define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
\r
18390 #define SDMMC_ICR_IDMABTCC_Pos (28U)
\r
18391 #define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
\r
18392 #define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
\r
18394 /****************** Bit definition for SDMMC_MASK register *******************/
\r
18395 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
\r
18396 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
\r
18397 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
\r
18398 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
\r
18399 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
\r
18400 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
\r
18401 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
\r
18402 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
\r
18403 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
\r
18404 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
\r
18405 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
\r
18406 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
\r
18407 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
\r
18408 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
\r
18409 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
\r
18410 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
\r
18411 #define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
\r
18412 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
\r
18413 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
\r
18414 #define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
\r
18415 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
\r
18416 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
\r
18417 #define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
\r
18418 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
\r
18419 #define SDMMC_MASK_DATAENDIE_Pos (8U)
\r
18420 #define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
\r
18421 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
\r
18422 #define SDMMC_MASK_DHOLDIE_Pos (9U)
\r
18423 #define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
\r
18424 #define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
\r
18425 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
\r
18426 #define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
\r
18427 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
\r
18428 #define SDMMC_MASK_DABORTIE_Pos (11U)
\r
18429 #define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
\r
18430 #define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
\r
18432 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
\r
18433 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
\r
18434 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
\r
18435 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
\r
18436 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
\r
18437 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
\r
18439 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
\r
18440 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
\r
18441 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
\r
18442 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
\r
18443 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
\r
18444 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
\r
18446 #define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
\r
18447 #define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
\r
18448 #define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
\r
18449 #define SDMMC_MASK_SDIOITIE_Pos (22U)
\r
18450 #define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
\r
18451 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
\r
18452 #define SDMMC_MASK_ACKFAILIE_Pos (23U)
\r
18453 #define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
\r
18454 #define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
\r
18455 #define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
\r
18456 #define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
\r
18457 #define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
\r
18458 #define SDMMC_MASK_VSWENDIE_Pos (25U)
\r
18459 #define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
\r
18460 #define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
\r
18461 #define SDMMC_MASK_CKSTOPIE_Pos (26U)
\r
18462 #define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
\r
18463 #define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
\r
18464 #define SDMMC_MASK_IDMABTCIE_Pos (28U)
\r
18465 #define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
\r
18466 #define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
\r
18468 /***************** Bit definition for SDMMC_ACKTIME register *****************/
\r
18469 #define SDMMC_ACKTIME_ACKTIME_Pos (0U)
\r
18470 #define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
\r
18471 #define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */
\r
18473 /****************** Bit definition for SDMMC_FIFO register *******************/
\r
18474 #define SDMMC_FIFO_FIFODATA_Pos (0U)
\r
18475 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
\r
18476 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
\r
18478 /****************** Bit definition for SDMMC_IDMACTRL register ****************/
\r
18479 #define SDMMC_IDMA_IDMAEN_Pos (0U)
\r
18480 #define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
\r
18481 #define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
\r
18482 #define SDMMC_IDMA_IDMABMODE_Pos (1U)
\r
18483 #define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
\r
18484 #define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
\r
18485 #define SDMMC_IDMA_IDMABACT_Pos (2U)
\r
18486 #define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
\r
18487 #define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
\r
18489 /***************** Bit definition for SDMMC_IDMABSIZE register ***************/
\r
18490 #define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
\r
18491 #define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
\r
18492 #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
\r
18494 /***************** Bit definition for SDMMC_IDMABASE0 register ***************/
\r
18495 #define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
\r
18497 /***************** Bit definition for SDMMC_IDMABASE1 register ***************/
\r
18498 #define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
\r
18500 /******************************************************************************/
\r
18502 /* Delay Block Interface (DLYB) */
\r
18504 /******************************************************************************/
\r
18505 /******************* Bit definition for DLYB_CR register ********************/
\r
18506 #define DLYB_CR_DEN_Pos (0U)
\r
18507 #define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
\r
18508 #define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
\r
18509 #define DLYB_CR_SEN_Pos (1U)
\r
18510 #define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
\r
18511 #define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
\r
18514 /******************* Bit definition for DLYB_CFGR register ********************/
\r
18515 #define DLYB_CFGR_SEL_Pos (0U)
\r
18516 #define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
\r
18517 #define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
\r
18518 #define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
\r
18519 #define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
\r
18520 #define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
\r
18521 #define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
\r
18523 #define DLYB_CFGR_UNIT_Pos (8U)
\r
18524 #define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
\r
18525 #define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
\r
18526 #define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
\r
18527 #define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
\r
18528 #define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
\r
18529 #define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
\r
18530 #define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
\r
18531 #define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
\r
18532 #define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
\r
18534 #define DLYB_CFGR_LNG_Pos (16U)
\r
18535 #define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
\r
18536 #define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
\r
18537 #define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
\r
18538 #define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
\r
18539 #define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
\r
18540 #define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
\r
18541 #define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
\r
18542 #define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
\r
18543 #define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
\r
18544 #define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
\r
18545 #define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
\r
18546 #define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
\r
18547 #define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
\r
18548 #define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
\r
18550 #define DLYB_CFGR_LNGF_Pos (31U)
\r
18551 #define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
\r
18552 #define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
\r
18554 /******************************************************************************/
\r
18556 /* Serial Peripheral Interface (SPI/I2S) */
\r
18558 /******************************************************************************/
\r
18559 /******************* Bit definition for SPI_CR1 register ********************/
\r
18560 #define SPI_CR1_SPE_Pos (0U)
\r
18561 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
\r
18562 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
\r
18563 #define SPI_CR1_MASRX_Pos (8U)
\r
18564 #define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
\r
18565 #define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
\r
18566 #define SPI_CR1_CSTART_Pos (9U)
\r
18567 #define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
\r
18568 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
\r
18569 #define SPI_CR1_CSUSP_Pos (10U)
\r
18570 #define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
\r
18571 #define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
\r
18572 #define SPI_CR1_HDDIR_Pos (11U)
\r
18573 #define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
\r
18574 #define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
\r
18575 #define SPI_CR1_SSI_Pos (12U)
\r
18576 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
\r
18577 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
\r
18578 #define SPI_CR1_CRC33_17_Pos (13U)
\r
18579 #define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */
\r
18580 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */
\r
18581 #define SPI_CR1_RCRCINI_Pos (14U)
\r
18582 #define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
\r
18583 #define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC init pattern control for receiver */
\r
18584 #define SPI_CR1_TCRCINI_Pos (15U)
\r
18585 #define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
\r
18586 #define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC init pattern control for transmitter */
\r
18587 #define SPI_CR1_IOLOCK_Pos (16U)
\r
18588 #define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
\r
18589 #define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
\r
18591 /******************* Bit definition for SPI_CR2 register ********************/
\r
18592 #define SPI_CR2_TSER_Pos (16U)
\r
18593 #define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */
\r
18594 #define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */
\r
18595 #define SPI_CR2_TSIZE_Pos (0U)
\r
18596 #define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
\r
18597 #define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
\r
18599 /******************* Bit definition for SPI_CFG1 register ********************/
\r
18600 #define SPI_CFG1_DSIZE_Pos (0U)
\r
18601 #define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
\r
18602 #define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE[4:0]: Bits number in single SPI data frame */
\r
18603 #define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
\r
18604 #define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
\r
18605 #define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
\r
18606 #define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
\r
18607 #define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
\r
18609 #define SPI_CFG1_FTHLV_Pos (5U)
\r
18610 #define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
\r
18611 #define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
\r
18612 #define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
\r
18613 #define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
\r
18614 #define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
\r
18615 #define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
\r
18617 #define SPI_CFG1_UDRCFG_Pos (9U)
\r
18618 #define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
\r
18619 #define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
\r
18620 #define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */
\r
18621 #define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */
\r
18624 #define SPI_CFG1_UDRDET_Pos (11U)
\r
18625 #define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */
\r
18626 #define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET[1:0]: Detection of underrun condition */
\r
18627 #define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */
\r
18628 #define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */
\r
18630 #define SPI_CFG1_RXDMAEN_Pos (14U)
\r
18631 #define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
\r
18632 #define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
\r
18633 #define SPI_CFG1_TXDMAEN_Pos (15U)
\r
18634 #define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
\r
18635 #define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
\r
18637 #define SPI_CFG1_CRCSIZE_Pos (16U)
\r
18638 #define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
\r
18639 #define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/
\r
18640 #define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
\r
18641 #define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
\r
18642 #define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
\r
18643 #define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
\r
18644 #define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
\r
18646 #define SPI_CFG1_CRCEN_Pos (22U)
\r
18647 #define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
\r
18648 #define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
\r
18650 #define SPI_CFG1_MBR_Pos (28U)
\r
18651 #define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
\r
18652 #define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
\r
18653 #define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
\r
18654 #define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
\r
18655 #define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
\r
18657 /******************* Bit definition for SPI_CFG2 register ********************/
\r
18658 #define SPI_CFG2_MSSI_Pos (0U)
\r
18659 #define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
\r
18660 #define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
\r
18661 #define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
\r
18662 #define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
\r
18663 #define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
\r
18664 #define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
\r
18666 #define SPI_CFG2_MIDI_Pos (4U)
\r
18667 #define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
\r
18668 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
\r
18669 #define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
\r
18670 #define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
\r
18671 #define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
\r
18672 #define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
\r
18674 #define SPI_CFG2_IOSWP_Pos (15U)
\r
18675 #define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
\r
18676 #define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
\r
18678 #define SPI_CFG2_COMM_Pos (17U)
\r
18679 #define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
\r
18680 #define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
\r
18681 #define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
\r
18682 #define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
\r
18684 #define SPI_CFG2_SP_Pos (19U)
\r
18685 #define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
\r
18686 #define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
\r
18687 #define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
\r
18688 #define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
\r
18689 #define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
\r
18691 #define SPI_CFG2_MASTER_Pos (22U)
\r
18692 #define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
\r
18693 #define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
\r
18694 #define SPI_CFG2_LSBFRST_Pos (23U)
\r
18695 #define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
\r
18696 #define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
\r
18697 #define SPI_CFG2_CPHA_Pos (24U)
\r
18698 #define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
\r
18699 #define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
\r
18700 #define SPI_CFG2_CPOL_Pos (25U)
\r
18701 #define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
\r
18702 #define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
\r
18703 #define SPI_CFG2_SSM_Pos (26U)
\r
18704 #define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
\r
18705 #define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
\r
18707 #define SPI_CFG2_SSIOP_Pos (28U)
\r
18708 #define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
\r
18709 #define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
\r
18710 #define SPI_CFG2_SSOE_Pos (29U)
\r
18711 #define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
\r
18712 #define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
\r
18713 #define SPI_CFG2_SSOM_Pos (30U)
\r
18714 #define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
\r
18715 #define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
\r
18717 #define SPI_CFG2_AFCNTR_Pos (31U)
\r
18718 #define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
\r
18719 #define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
\r
18721 /******************* Bit definition for SPI_IER register ********************/
\r
18722 #define SPI_IER_RXPIE_Pos (0U)
\r
18723 #define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
\r
18724 #define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
\r
18725 #define SPI_IER_TXPIE_Pos (1U)
\r
18726 #define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
\r
18727 #define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
\r
18728 #define SPI_IER_DXPIE_Pos (2U)
\r
18729 #define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
\r
18730 #define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
\r
18731 #define SPI_IER_EOTIE_Pos (3U)
\r
18732 #define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
\r
18733 #define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
\r
18734 #define SPI_IER_TXTFIE_Pos (4U)
\r
18735 #define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
\r
18736 #define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
\r
18737 #define SPI_IER_UDRIE_Pos (5U)
\r
18738 #define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
\r
18739 #define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
\r
18740 #define SPI_IER_OVRIE_Pos (6U)
\r
18741 #define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
\r
18742 #define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
\r
18743 #define SPI_IER_CRCEIE_Pos (7U)
\r
18744 #define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */
\r
18745 #define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRCE interrupt enable */
\r
18746 #define SPI_IER_TIFREIE_Pos (8U)
\r
18747 #define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
\r
18748 #define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
\r
18749 #define SPI_IER_MODFIE_Pos (9U)
\r
18750 #define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
\r
18751 #define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
\r
18752 #define SPI_IER_TSERFIE_Pos (10U)
\r
18753 #define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos) /*!< 0x00000400 */
\r
18754 #define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk /*!<TSERF interrupt enable */
\r
18756 /******************* Bit definition for SPI_SR register ********************/
\r
18757 #define SPI_SR_RXP_Pos (0U)
\r
18758 #define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) /*!< 0x00000001 */
\r
18759 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
\r
18760 #define SPI_SR_TXP_Pos (1U)
\r
18761 #define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) /*!< 0x00000002 */
\r
18762 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
\r
18763 #define SPI_SR_DXP_Pos (2U)
\r
18764 #define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) /*!< 0x00000004 */
\r
18765 #define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
\r
18766 #define SPI_SR_EOT_Pos (3U)
\r
18767 #define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) /*!< 0x00000008 */
\r
18768 #define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
\r
18769 #define SPI_SR_TXTF_Pos (4U)
\r
18770 #define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
\r
18771 #define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
\r
18772 #define SPI_SR_UDR_Pos (5U)
\r
18773 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000020 */
\r
18774 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
\r
18775 #define SPI_SR_OVR_Pos (6U)
\r
18776 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
\r
18777 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
\r
18778 #define SPI_SR_CRCE_Pos (7U)
\r
18779 #define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
\r
18780 #define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
\r
18781 #define SPI_SR_TIFRE_Pos (8U)
\r
18782 #define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
\r
18783 #define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
\r
18784 #define SPI_SR_MODF_Pos (9U)
\r
18785 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000200 */
\r
18786 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
\r
18787 #define SPI_SR_TSERF_Pos (10U)
\r
18788 #define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos) /*!< 0x00000400 */
\r
18789 #define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Number of SPI data to be transacted reloaded */
\r
18790 #define SPI_SR_SUSP_Pos (11U)
\r
18791 #define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
\r
18792 #define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
\r
18793 #define SPI_SR_TXC_Pos (12U)
\r
18794 #define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) /*!< 0x00001000 */
\r
18795 #define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
\r
18796 #define SPI_SR_RXPLVL_Pos (13U)
\r
18797 #define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
\r
18798 #define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
\r
18799 #define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
\r
18800 #define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
\r
18801 #define SPI_SR_RXWNE_Pos (15U)
\r
18802 #define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
\r
18803 #define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
\r
18804 #define SPI_SR_CTSIZE_Pos (16U)
\r
18805 #define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
\r
18806 #define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
\r
18808 /******************* Bit definition for SPI_IFCR register ********************/
\r
18809 #define SPI_IFCR_EOTC_Pos (3U)
\r
18810 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
\r
18811 #define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
\r
18812 #define SPI_IFCR_TXTFC_Pos (4U)
\r
18813 #define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
\r
18814 #define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
\r
18815 #define SPI_IFCR_UDRC_Pos (5U)
\r
18816 #define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
\r
18817 #define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
\r
18818 #define SPI_IFCR_OVRC_Pos (6U)
\r
18819 #define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
\r
18820 #define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
\r
18821 #define SPI_IFCR_CRCEC_Pos (7U)
\r
18822 #define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
\r
18823 #define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
\r
18824 #define SPI_IFCR_TIFREC_Pos (8U)
\r
18825 #define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
\r
18826 #define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
\r
18827 #define SPI_IFCR_MODFC_Pos (9U)
\r
18828 #define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
\r
18829 #define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
\r
18830 #define SPI_IFCR_TSERFC_Pos (10U)
\r
18831 #define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */
\r
18832 #define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */
\r
18833 #define SPI_IFCR_SUSPC_Pos (11U)
\r
18834 #define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
\r
18835 #define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
\r
18837 /******************* Bit definition for SPI_TXDR register ********************/
\r
18838 #define SPI_TXDR_TXDR_Pos (0U)
\r
18839 #define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
\r
18840 #define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
\r
18842 /******************* Bit definition for SPI_RXDR register ********************/
\r
18843 #define SPI_RXDR_RXDR_Pos (0U)
\r
18844 #define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
\r
18845 #define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
\r
18847 /******************* Bit definition for SPI_CRCPOLY register ********************/
\r
18848 #define SPI_CRCPOLY_CRCPOLY_Pos (0U)
\r
18849 #define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
\r
18850 #define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
\r
18852 /******************* Bit definition for SPI_TXCRC register ********************/
\r
18853 #define SPI_TXCRC_TXCRC_Pos (0U)
\r
18854 #define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
\r
18855 #define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
\r
18857 /******************* Bit definition for SPI_RXCRC register ********************/
\r
18858 #define SPI_RXCRC_RXCRC_Pos (0U)
\r
18859 #define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
\r
18860 #define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
\r
18862 /******************* Bit definition for SPI_UDRDR register ********************/
\r
18863 #define SPI_UDRDR_UDRDR_Pos (0U)
\r
18864 #define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
\r
18865 #define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
\r
18867 /****************** Bit definition for SPI_I2SCFGR register *****************/
\r
18868 #define SPI_I2SCFGR_I2SMOD_Pos (0U)
\r
18869 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
\r
18870 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
\r
18871 #define SPI_I2SCFGR_I2SCFG_Pos (1U)
\r
18872 #define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
\r
18873 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[2:0] I2S configuration mode */
\r
18874 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
\r
18875 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
\r
18876 #define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
\r
18877 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
\r
18878 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
\r
18879 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
\r
18880 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
\r
18881 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
\r
18882 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
\r
18883 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
\r
18884 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
\r
18885 #define SPI_I2SCFGR_DATLEN_Pos (8U)
\r
18886 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
\r
18887 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
\r
18888 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
\r
18889 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
\r
18890 #define SPI_I2SCFGR_CHLEN_Pos (10U)
\r
18891 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
\r
18892 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
\r
18893 #define SPI_I2SCFGR_CKPOL_Pos (11U)
\r
18894 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
\r
18895 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */
\r
18896 #define SPI_I2SCFGR_FIXCH_Pos (12U)
\r
18897 #define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */
\r
18898 #define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
\r
18899 #define SPI_I2SCFGR_WSINV_Pos (13U)
\r
18900 #define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */
\r
18901 #define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
\r
18902 #define SPI_I2SCFGR_DATFMT_Pos (14U)
\r
18903 #define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00004000 */
\r
18904 #define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
\r
18905 #define SPI_I2SCFGR_I2SDIV_Pos (16U)
\r
18906 #define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
\r
18907 #define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
\r
18908 #define SPI_I2SCFGR_ODD_Pos (24U)
\r
18909 #define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
\r
18910 #define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
\r
18911 #define SPI_I2SCFGR_MCKOE_Pos (25U)
\r
18912 #define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
\r
18913 #define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
\r
18916 /******************************************************************************/
\r
18920 /******************************************************************************/
\r
18921 /***************** Bit definition for QUADSPI_CR register *******************/
\r
18922 #define QUADSPI_CR_EN_Pos (0U)
\r
18923 #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
\r
18924 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
\r
18925 #define QUADSPI_CR_ABORT_Pos (1U)
\r
18926 #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
\r
18927 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
\r
18928 #define QUADSPI_CR_DMAEN_Pos (2U)
\r
18929 #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
\r
18930 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
\r
18931 #define QUADSPI_CR_TCEN_Pos (3U)
\r
18932 #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
\r
18933 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
\r
18934 #define QUADSPI_CR_SSHIFT_Pos (4U)
\r
18935 #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
\r
18936 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
\r
18937 #define QUADSPI_CR_DFM_Pos (6U)
\r
18938 #define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
\r
18939 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
\r
18940 #define QUADSPI_CR_FSEL_Pos (7U)
\r
18941 #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
\r
18942 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
\r
18943 #define QUADSPI_CR_FTHRES_Pos (8U)
\r
18944 #define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
\r
18945 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
\r
18946 #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
\r
18947 #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
\r
18948 #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
\r
18949 #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
\r
18950 #define QUADSPI_CR_TEIE_Pos (16U)
\r
18951 #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
\r
18952 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
\r
18953 #define QUADSPI_CR_TCIE_Pos (17U)
\r
18954 #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
\r
18955 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
\r
18956 #define QUADSPI_CR_FTIE_Pos (18U)
\r
18957 #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
\r
18958 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
\r
18959 #define QUADSPI_CR_SMIE_Pos (19U)
\r
18960 #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
\r
18961 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
\r
18962 #define QUADSPI_CR_TOIE_Pos (20U)
\r
18963 #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
\r
18964 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
\r
18965 #define QUADSPI_CR_APMS_Pos (22U)
\r
18966 #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
\r
18967 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
\r
18968 #define QUADSPI_CR_PMM_Pos (23U)
\r
18969 #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
\r
18970 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
\r
18971 #define QUADSPI_CR_PRESCALER_Pos (24U)
\r
18972 #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
\r
18973 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
\r
18974 #define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
\r
18975 #define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
\r
18976 #define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
\r
18977 #define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
\r
18978 #define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
\r
18979 #define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
\r
18980 #define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
\r
18981 #define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
\r
18983 /***************** Bit definition for QUADSPI_DCR register ******************/
\r
18984 #define QUADSPI_DCR_CKMODE_Pos (0U)
\r
18985 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
\r
18986 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
\r
18987 #define QUADSPI_DCR_CSHT_Pos (8U)
\r
18988 #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
\r
18989 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
\r
18990 #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
\r
18991 #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
\r
18992 #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
\r
18993 #define QUADSPI_DCR_FSIZE_Pos (16U)
\r
18994 #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
\r
18995 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
\r
18996 #define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
\r
18997 #define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
\r
18998 #define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
\r
18999 #define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
\r
19000 #define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
\r
19002 /****************** Bit definition for QUADSPI_SR register *******************/
\r
19003 #define QUADSPI_SR_TEF_Pos (0U)
\r
19004 #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
\r
19005 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
\r
19006 #define QUADSPI_SR_TCF_Pos (1U)
\r
19007 #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
\r
19008 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
\r
19009 #define QUADSPI_SR_FTF_Pos (2U)
\r
19010 #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
\r
19011 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
\r
19012 #define QUADSPI_SR_SMF_Pos (3U)
\r
19013 #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
\r
19014 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
\r
19015 #define QUADSPI_SR_TOF_Pos (4U)
\r
19016 #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
\r
19017 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
\r
19018 #define QUADSPI_SR_BUSY_Pos (5U)
\r
19019 #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
\r
19020 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
\r
19021 #define QUADSPI_SR_FLEVEL_Pos (8U)
\r
19022 #define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
\r
19023 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
\r
19024 #define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
\r
19025 #define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
\r
19026 #define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
\r
19027 #define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
\r
19028 #define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
\r
19029 #define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
\r
19031 /****************** Bit definition for QUADSPI_FCR register ******************/
\r
19032 #define QUADSPI_FCR_CTEF_Pos (0U)
\r
19033 #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
\r
19034 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
\r
19035 #define QUADSPI_FCR_CTCF_Pos (1U)
\r
19036 #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
\r
19037 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
\r
19038 #define QUADSPI_FCR_CSMF_Pos (3U)
\r
19039 #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
\r
19040 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
\r
19041 #define QUADSPI_FCR_CTOF_Pos (4U)
\r
19042 #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
\r
19043 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
\r
19045 /****************** Bit definition for QUADSPI_DLR register ******************/
\r
19046 #define QUADSPI_DLR_DL_Pos (0U)
\r
19047 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
\r
19048 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
\r
19050 /****************** Bit definition for QUADSPI_CCR register ******************/
\r
19051 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
\r
19052 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
\r
19053 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
\r
19054 #define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
\r
19055 #define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
\r
19056 #define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
\r
19057 #define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
\r
19058 #define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
\r
19059 #define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
\r
19060 #define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
\r
19061 #define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
\r
19062 #define QUADSPI_CCR_IMODE_Pos (8U)
\r
19063 #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
\r
19064 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
\r
19065 #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
\r
19066 #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
\r
19067 #define QUADSPI_CCR_ADMODE_Pos (10U)
\r
19068 #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
\r
19069 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
\r
19070 #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
\r
19071 #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
\r
19072 #define QUADSPI_CCR_ADSIZE_Pos (12U)
\r
19073 #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
\r
19074 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
\r
19075 #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
\r
19076 #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
\r
19077 #define QUADSPI_CCR_ABMODE_Pos (14U)
\r
19078 #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
\r
19079 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
\r
19080 #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
\r
19081 #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
\r
19082 #define QUADSPI_CCR_ABSIZE_Pos (16U)
\r
19083 #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
\r
19084 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
\r
19085 #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
\r
19086 #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
\r
19087 #define QUADSPI_CCR_DCYC_Pos (18U)
\r
19088 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
\r
19089 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
\r
19090 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
\r
19091 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
\r
19092 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
\r
19093 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
\r
19094 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
\r
19095 #define QUADSPI_CCR_DMODE_Pos (24U)
\r
19096 #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
\r
19097 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
\r
19098 #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
\r
19099 #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
\r
19100 #define QUADSPI_CCR_FMODE_Pos (26U)
\r
19101 #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
\r
19102 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
\r
19103 #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
\r
19104 #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
\r
19105 #define QUADSPI_CCR_SIOO_Pos (28U)
\r
19106 #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
\r
19107 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
\r
19108 #define QUADSPI_CCR_DHHC_Pos (30U)
\r
19109 #define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
\r
19110 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */
\r
19111 #define QUADSPI_CCR_DDRM_Pos (31U)
\r
19112 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
\r
19113 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
\r
19115 /****************** Bit definition for QUADSPI_AR register *******************/
\r
19116 #define QUADSPI_AR_ADDRESS_Pos (0U)
\r
19117 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
\r
19118 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
\r
19120 /****************** Bit definition for QUADSPI_ABR register ******************/
\r
19121 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
\r
19122 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
\r
19123 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
\r
19125 /****************** Bit definition for QUADSPI_DR register *******************/
\r
19126 #define QUADSPI_DR_DATA_Pos (0U)
\r
19127 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
\r
19128 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
\r
19130 /****************** Bit definition for QUADSPI_PSMKR register ****************/
\r
19131 #define QUADSPI_PSMKR_MASK_Pos (0U)
\r
19132 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
\r
19133 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
\r
19135 /****************** Bit definition for QUADSPI_PSMAR register ****************/
\r
19136 #define QUADSPI_PSMAR_MATCH_Pos (0U)
\r
19137 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
\r
19138 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
\r
19140 /****************** Bit definition for QUADSPI_PIR register *****************/
\r
19141 #define QUADSPI_PIR_INTERVAL_Pos (0U)
\r
19142 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
\r
19143 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
\r
19145 /****************** Bit definition for QUADSPI_LPTR register *****************/
\r
19146 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
\r
19147 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
\r
19148 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
\r
19150 /******************************************************************************/
\r
19154 /******************************************************************************/
\r
19156 /****************** Bit definition for SYSCFG_PMCR register ******************/
\r
19157 #define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
\r
19158 #define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos) /*!< 0x00000001 */
\r
19159 #define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
\r
19160 #define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
\r
19161 #define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos) /*!< 0x00000002 */
\r
19162 #define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
\r
19163 #define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
\r
19164 #define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos) /*!< 0x00000004 */
\r
19165 #define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
\r
19166 #define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
\r
19167 #define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos) /*!< 0x00000008 */
\r
19168 #define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
\r
19169 #define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
\r
19170 #define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
\r
19171 #define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
\r
19172 #define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
\r
19173 #define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
\r
19174 #define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
\r
19175 #define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
\r
19176 #define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
\r
19177 #define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
\r
19178 #define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
\r
19179 #define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
\r
19180 #define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
\r
19181 #define SYSCFG_PMCR_BOOSTEN_Pos (8U)
\r
19182 #define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos) /*!< 0x00000100 */
\r
19183 #define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
\r
19185 #define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
\r
19186 #define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
\r
19187 #define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk /*!< Analog switch supply source selection : VDD/VDDA */
\r
19189 #define SYSCFG_PMCR_EPIS_SEL_Pos (21U)
\r
19190 #define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00E00000 */
\r
19191 #define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk /*!< Ethernet PHY Interface Selection */
\r
19192 #define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00200000 */
\r
19193 #define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00400000 */
\r
19194 #define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00800000 */
\r
19195 #define SYSCFG_PMCR_PA0SO_Pos (24U)
\r
19196 #define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos) /*!< 0x01000000 */
\r
19197 #define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk /*!< PA0 Switch Open */
\r
19198 #define SYSCFG_PMCR_PA1SO_Pos (25U)
\r
19199 #define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos) /*!< 0x02000000 */
\r
19200 #define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk /*!< PA1 Switch Open */
\r
19201 #define SYSCFG_PMCR_PC2SO_Pos (26U)
\r
19202 #define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos) /*!< 0x04000000 */
\r
19203 #define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk /*!< PC2 Switch Open */
\r
19204 #define SYSCFG_PMCR_PC3SO_Pos (27U)
\r
19205 #define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos) /*!< 0x08000000 */
\r
19206 #define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk /*!< PC3 Switch Open */
\r
19208 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
\r
19209 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
\r
19210 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
\r
19211 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
\r
19212 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
\r
19213 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
\r
19214 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
\r
19215 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
\r
19216 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
\r
19217 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
\r
19218 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
\r
19219 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
\r
19220 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
\r
19222 * @brief EXTI0 configuration
\r
19224 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
\r
19225 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
\r
19226 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
\r
19227 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
\r
19228 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
\r
19229 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
\r
19230 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
\r
19231 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
\r
19232 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
\r
19233 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
\r
19234 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
\r
19237 * @brief EXTI1 configuration
\r
19239 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
\r
19240 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
\r
19241 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
\r
19242 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
\r
19243 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
\r
19244 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
\r
19245 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
\r
19246 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
\r
19247 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
\r
19248 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
\r
19249 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
\r
19251 * @brief EXTI2 configuration
\r
19253 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
\r
19254 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
\r
19255 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
\r
19256 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
\r
19257 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
\r
19258 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
\r
19259 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
\r
19260 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
\r
19261 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
\r
19262 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
\r
19263 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
\r
19266 * @brief EXTI3 configuration
\r
19268 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
\r
19269 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
\r
19270 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
\r
19271 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
\r
19272 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
\r
19273 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
\r
19274 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
\r
19275 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
\r
19276 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
\r
19277 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
\r
19278 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
\r
19280 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
\r
19281 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
\r
19282 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
\r
19283 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
\r
19284 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
\r
19285 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
\r
19286 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
\r
19287 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
\r
19288 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
\r
19289 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
\r
19290 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
\r
19291 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
\r
19292 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
\r
19294 * @brief EXTI4 configuration
\r
19296 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
\r
19297 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
\r
19298 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
\r
19299 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
\r
19300 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
\r
19301 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
\r
19302 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
\r
19303 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
\r
19304 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
\r
19305 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
\r
19306 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
\r
19308 * @brief EXTI5 configuration
\r
19310 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
\r
19311 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
\r
19312 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
\r
19313 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
\r
19314 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
\r
19315 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
\r
19316 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
\r
19317 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
\r
19318 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
\r
19319 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
\r
19320 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
\r
19322 * @brief EXTI6 configuration
\r
19324 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
\r
19325 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
\r
19326 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
\r
19327 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
\r
19328 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
\r
19329 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
\r
19330 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
\r
19331 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
\r
19332 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
\r
19333 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
\r
19334 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
\r
19337 * @brief EXTI7 configuration
\r
19339 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
\r
19340 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
\r
19341 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
\r
19342 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
\r
19343 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
\r
19344 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
\r
19345 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
\r
19346 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
\r
19347 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
\r
19348 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
\r
19349 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
\r
19351 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
\r
19352 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
\r
19353 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
\r
19354 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
\r
19355 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
\r
19356 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
\r
19357 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
\r
19358 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
\r
19359 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
\r
19360 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
\r
19361 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
\r
19362 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
\r
19363 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
\r
19366 * @brief EXTI8 configuration
\r
19368 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
\r
19369 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
\r
19370 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
\r
19371 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
\r
19372 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
\r
19373 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
\r
19374 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
\r
19375 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
\r
19376 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
\r
19377 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
\r
19378 #define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
\r
19381 * @brief EXTI9 configuration
\r
19383 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
\r
19384 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
\r
19385 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
\r
19386 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
\r
19387 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
\r
19388 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
\r
19389 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
\r
19390 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
\r
19391 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
\r
19392 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
\r
19393 #define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
\r
19396 * @brief EXTI10 configuration
\r
19398 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
\r
19399 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
\r
19400 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
\r
19401 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
\r
19402 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
\r
19403 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
\r
19404 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
\r
19405 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
\r
19406 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
\r
19407 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
\r
19408 #define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
\r
19411 * @brief EXTI11 configuration
\r
19413 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
\r
19414 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
\r
19415 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
\r
19416 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
\r
19417 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
\r
19418 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
\r
19419 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
\r
19420 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
\r
19421 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
\r
19422 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
\r
19423 #define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
\r
19425 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
\r
19426 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
\r
19427 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
\r
19428 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
\r
19429 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
\r
19430 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
\r
19431 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
\r
19432 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
\r
19433 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
\r
19434 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
\r
19435 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
\r
19436 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
\r
19437 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
\r
19439 * @brief EXTI12 configuration
\r
19441 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
\r
19442 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
\r
19443 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
\r
19444 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
\r
19445 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
\r
19446 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
\r
19447 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
\r
19448 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
\r
19449 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
\r
19450 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
\r
19451 #define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
\r
19453 * @brief EXTI13 configuration
\r
19455 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
\r
19456 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
\r
19457 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
\r
19458 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
\r
19459 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
\r
19460 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
\r
19461 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
\r
19462 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
\r
19463 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
\r
19464 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
\r
19465 #define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
\r
19467 * @brief EXTI14 configuration
\r
19469 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
\r
19470 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
\r
19471 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
\r
19472 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
\r
19473 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
\r
19474 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
\r
19475 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
\r
19476 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
\r
19477 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
\r
19478 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
\r
19479 #define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
\r
19481 * @brief EXTI15 configuration
\r
19483 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
\r
19484 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
\r
19485 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
\r
19486 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
\r
19487 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
\r
19488 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
\r
19489 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
\r
19490 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
\r
19491 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
\r
19492 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
\r
19493 #define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
\r
19495 /****************** Bit definition for SYSCFG_CFGR register ******************/
\r
19496 #define SYSCFG_CFGR_CM4L_Pos (0U)
\r
19497 #define SYSCFG_CFGR_CM4L_Msk (0x1UL << SYSCFG_CFGR_CM4L_Pos) /*!< 0x00000001 */
\r
19498 #define SYSCFG_CFGR_CM4L SYSCFG_CFGR_CM4L_Msk /*!<Cortex-M4 LOCKUP (Hardfault) output enable bit */
\r
19499 #define SYSCFG_CFGR_PVDL_Pos (2U)
\r
19500 #define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos) /*!< 0x00000004 */
\r
19501 #define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk /*!<PVD lock enable bit */
\r
19502 #define SYSCFG_CFGR_FLASHL_Pos (3U)
\r
19503 #define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos) /*!< 0x00000008 */
\r
19504 #define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk /*!<FLASH double ECC error lock bit */
\r
19505 #define SYSCFG_CFGR_CM7L_Pos (6U)
\r
19506 #define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos) /*!< 0x00000040 */
\r
19507 #define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
\r
19508 #define SYSCFG_CFGR_BKRAML_Pos (7U)
\r
19509 #define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos) /*!< 0x00000080 */
\r
19510 #define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk /*!<Backup SRAM double ECC error lock bit */
\r
19511 #define SYSCFG_CFGR_SRAM4L_Pos (9U)
\r
19512 #define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos) /*!< 0x00000200 */
\r
19513 #define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk /*!<SRAM4 double ECC error lock bit */
\r
19514 #define SYSCFG_CFGR_SRAM3L_Pos (10U)
\r
19515 #define SYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos) /*!< 0x00000400 */
\r
19516 #define SYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk /*!<SRAM3 double ECC error lock bit */
\r
19517 #define SYSCFG_CFGR_SRAM2L_Pos (11U)
\r
19518 #define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos) /*!< 0x00000800 */
\r
19519 #define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk /*!<SRAM2 double ECC error lock bit */
\r
19520 #define SYSCFG_CFGR_SRAM1L_Pos (12U)
\r
19521 #define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos) /*!< 0x00001000 */
\r
19522 #define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk /*!<SRAM1 double ECC error lock bit */
\r
19523 #define SYSCFG_CFGR_DTCML_Pos (13U)
\r
19524 #define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos) /*!< 0x00002000 */
\r
19525 #define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk /*!<DTCM double ECC error lock bit */
\r
19526 #define SYSCFG_CFGR_ITCML_Pos (14U)
\r
19527 #define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos) /*!< 0x00004000 */
\r
19528 #define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk /*!<ITCM double ECC error lock bit */
\r
19529 #define SYSCFG_CFGR_AXISRAML_Pos (15U)
\r
19530 #define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos) /*!< 0x00008000 */
\r
19531 #define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk /*!<AXISRAM double ECC error lock bit */
\r
19533 /****************** Bit definition for SYSCFG_CCCSR register ******************/
\r
19534 #define SYSCFG_CCCSR_EN_Pos (0U)
\r
19535 #define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos) /*!< 0x00000001 */
\r
19536 #define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk /*!< I/O compensation cell enable */
\r
19537 #define SYSCFG_CCCSR_CS_Pos (1U)
\r
19538 #define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos) /*!< 0x00000002 */
\r
19539 #define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk /*!< I/O compensation cell code selection */
\r
19540 #define SYSCFG_CCCSR_READY_Pos (8U)
\r
19541 #define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos) /*!< 0x00000100 */
\r
19542 #define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk /*!< I/O compensation cell ready flag */
\r
19543 #define SYSCFG_CCCSR_HSLV_Pos (16U)
\r
19544 #define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos) /*!< 0x00010000 */
\r
19545 #define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk /*!< High-speed at low-voltage */
\r
19547 /****************** Bit definition for SYSCFG_CCVR register *******************/
\r
19548 #define SYSCFG_CCVR_NCV_Pos (0U)
\r
19549 #define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos) /*!< 0x0000000F */
\r
19550 #define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk /*!< NMOS compensation value */
\r
19551 #define SYSCFG_CCVR_PCV_Pos (4U)
\r
19552 #define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos) /*!< 0x000000F0 */
\r
19553 #define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk /*!< PMOS compensation value */
\r
19555 /****************** Bit definition for SYSCFG_CCCR register *******************/
\r
19556 #define SYSCFG_CCCR_NCC_Pos (0U)
\r
19557 #define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos) /*!< 0x0000000F */
\r
19558 #define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk /*!< NMOS compensation code */
\r
19559 #define SYSCFG_CCCR_PCC_Pos (4U)
\r
19560 #define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) /*!< 0x000000F0 */
\r
19561 #define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk /*!< PMOS compensation code */
\r
19562 /****************** Bit definition for SYSCFG_PWRCR register *******************/
\r
19563 #define SYSCFG_PWRCR_ODEN_Pos (0U)
\r
19564 #define SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos) /*!< 0x00000001 */
\r
19565 #define SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk /*!< PWR overdrive enable */
\r
19567 /****************** Bit definition for SYSCFG_PKGR register *******************/
\r
19568 #define SYSCFG_PKGR_PKG_Pos (0U)
\r
19569 #define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos) /*!< 0x0000000F */
\r
19570 #define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk /*!< Package type */
\r
19572 /****************** Bit definition for SYSCFG_UR0 register *******************/
\r
19573 #define SYSCFG_UR0_BKS_Pos (0U)
\r
19574 #define SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos) /*!< 0x00000001 */
\r
19575 #define SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk /*!< Bank Swap */
\r
19576 #define SYSCFG_UR0_RDP_Pos (16U)
\r
19577 #define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos) /*!< 0x00FF0000 */
\r
19578 #define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk /*!< Readout protection */
\r
19580 /****************** Bit definition for SYSCFG_UR1 register *******************/
\r
19581 #define SYSCFG_UR1_BCM4_Pos (0U)
\r
19582 #define SYSCFG_UR1_BCM4_Msk (0x1UL << SYSCFG_UR1_BCM4_Pos) /*!< 0x00000001 */
\r
19583 #define SYSCFG_UR1_BCM4 SYSCFG_UR1_BCM4_Msk /*!< Boot Cortex-M4 */
\r
19584 #define SYSCFG_UR1_BCM7_Pos (16U)
\r
19585 #define SYSCFG_UR1_BCM7_Msk (0x1UL << SYSCFG_UR1_BCM7_Pos) /*!< 0x00010000 */
\r
19586 #define SYSCFG_UR1_BCM7 SYSCFG_UR1_BCM7_Msk /*!< Boot Cortex-M7 */
\r
19587 /****************** Bit definition for SYSCFG_UR2 register *******************/
\r
19588 #define SYSCFG_UR2_BORH_Pos (0U)
\r
19589 #define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000003 */
\r
19590 #define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk /*!< Brown Out Reset High level */
\r
19591 #define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000001 */
\r
19592 #define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000002 */
\r
19593 #define SYSCFG_UR2_BCM7_ADD0_Pos (16U)
\r
19594 #define SYSCFG_UR2_BCM7_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos) /*!< 0xFFFF0000 */
\r
19595 #define SYSCFG_UR2_BCM7_ADD0 SYSCFG_UR2_BCM7_ADD0_Msk /*!< Boot Cortex-M7 Address 0 */
\r
19596 /****************** Bit definition for SYSCFG_UR3 register *******************/
\r
19597 #define SYSCFG_UR3_BCM7_ADD1_Pos (0U)
\r
19598 #define SYSCFG_UR3_BCM7_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos) /*!< 0x0000FFFF */
\r
19599 #define SYSCFG_UR3_BCM7_ADD1 SYSCFG_UR3_BCM7_ADD1_Msk /*!< Boot Cortex-M7 Address 1 */
\r
19601 #define SYSCFG_UR3_BCM4_ADD0_Pos (16U)
\r
19602 #define SYSCFG_UR3_BCM4_ADD0_Msk (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos) /*!< 0xFFFF0000 */
\r
19603 #define SYSCFG_UR3_BCM4_ADD0 SYSCFG_UR3_BCM4_ADD0_Msk /*!< Boot Cortex-M4 Address 0 */
\r
19605 /****************** Bit definition for SYSCFG_UR4 register *******************/
\r
19607 #define SYSCFG_UR4_BCM4_ADD1_Pos (0U)
\r
19608 #define SYSCFG_UR4_BCM4_ADD1_Msk (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos) /*!< 0x0000FFFF */
\r
19609 #define SYSCFG_UR4_BCM4_ADD1 SYSCFG_UR4_BCM4_ADD1_Msk /*!< Boot Cortex-M4 Address 1 */
\r
19611 #define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
\r
19612 #define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos) /*!< 0x00010000 */
\r
19613 #define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk /*!< Mass Erase Protected Area Disabled for bank 1 */
\r
19615 /****************** Bit definition for SYSCFG_UR5 register *******************/
\r
19616 #define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
\r
19617 #define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos) /*!< 0x00000001 */
\r
19618 #define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk /*!< Mass erase secured area disabled for bank 1 */
\r
19619 #define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
\r
19620 #define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos) /*!< 0x00FF0000 */
\r
19621 #define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk /*!< Write protection for flash bank 1 */
\r
19623 /****************** Bit definition for SYSCFG_UR6 register *******************/
\r
19624 #define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
\r
19625 #define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
\r
19626 #define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk /*!< Protected area start address for bank 1 */
\r
19627 #define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
\r
19628 #define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
\r
19629 #define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk /*!< Protected area end address for bank 1 */
\r
19631 /****************** Bit definition for SYSCFG_UR7 register *******************/
\r
19632 #define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
\r
19633 #define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
\r
19634 #define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk /*!< Secured area start address for bank 1 */
\r
19635 #define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
\r
19636 #define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
\r
19637 #define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk /*!< Secured area end address for bank 1 */
\r
19639 /****************** Bit definition for SYSCFG_UR8 register *******************/
\r
19640 #define SYSCFG_UR8_MEPAD_BANK2_Pos (0U)
\r
19641 #define SYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos) /*!< 0x00000001 */
\r
19642 #define SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk /*!< Mass erase Protected area disabled for bank 2 */
\r
19643 #define SYSCFG_UR8_MESAD_BANK2_Pos (16U)
\r
19644 #define SYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos) /*!< 0x00010000 */
\r
19645 #define SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk /*!< Mass Erase Secured Area Disabled for bank 2 */
\r
19647 /****************** Bit definition for SYSCFG_UR9 register *******************/
\r
19648 #define SYSCFG_UR9_WRPN_BANK2_Pos (0U)
\r
19649 #define SYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos) /*!< 0x000000FF */
\r
19650 #define SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk /*!< Write protection for flash bank 2 */
\r
19651 #define SYSCFG_UR9_PABEG_BANK2_Pos (16U)
\r
19652 #define SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
\r
19653 #define SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk /*!< Protected area start address for bank 2 */
\r
19655 /****************** Bit definition for SYSCFG_UR10 register *******************/
\r
19656 #define SYSCFG_UR10_PAEND_BANK2_Pos (0U)
\r
19657 #define SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
\r
19658 #define SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk /*!< Protected area end address for bank 2 */
\r
19659 #define SYSCFG_UR10_SABEG_BANK2_Pos (16U)
\r
19660 #define SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
\r
19661 #define SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk /*!< Secured area start address for bank 2 */
\r
19663 /****************** Bit definition for SYSCFG_UR11 register *******************/
\r
19664 #define SYSCFG_UR11_SAEND_BANK2_Pos (0U)
\r
19665 #define SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
\r
19666 #define SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk /*!< Secured area end address for bank 2 */
\r
19667 #define SYSCFG_UR11_IWDG1M_Pos (16U)
\r
19668 #define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos) /*!< 0x00010000 */
\r
19669 #define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk /*!< Independent Watchdog 1 mode (SW or HW) */
\r
19671 /****************** Bit definition for SYSCFG_UR12 register *******************/
\r
19672 #define SYSCFG_UR12_IWDG2M_Pos (0U)
\r
19673 #define SYSCFG_UR12_IWDG2M_Msk (0x1UL << SYSCFG_UR12_IWDG2M_Pos) /*!< 0x00000001 */
\r
19674 #define SYSCFG_UR12_IWDG2M SYSCFG_UR12_IWDG2M_Msk /*!< Independent Watchdog 2 mode (SW or HW) */
\r
19676 #define SYSCFG_UR12_SECURE_Pos (16U)
\r
19677 #define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos) /*!< 0x00010000 */
\r
19678 #define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk /*!< Secure mode status */
\r
19680 /****************** Bit definition for SYSCFG_UR13 register *******************/
\r
19681 #define SYSCFG_UR13_SDRS_Pos (0U)
\r
19682 #define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos) /*!< 0x00000003 */
\r
19683 #define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk /*!< Secured DTCM RAM Size */
\r
19684 #define SYSCFG_UR13_D1SBRST_Pos (16U)
\r
19685 #define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos) /*!< 0x00010000 */
\r
19686 #define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk /*!< D1 Standby reset */
\r
19688 /****************** Bit definition for SYSCFG_UR14 register *******************/
\r
19689 #define SYSCFG_UR14_D1STPRST_Pos (0U)
\r
19690 #define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos) /*!< 0x00000001 */
\r
19691 #define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk /*!< D1 Stop Reset */
\r
19692 #define SYSCFG_UR14_D2SBRST_Pos (16U)
\r
19693 #define SYSCFG_UR14_D2SBRST_Msk (0x1UL << SYSCFG_UR14_D2SBRST_Pos) /*!< 0x00010000 */
\r
19694 #define SYSCFG_UR14_D2SBRST SYSCFG_UR14_D2SBRST_Msk /*!< D2 Standby Reset */
\r
19696 /****************** Bit definition for SYSCFG_UR15 register *******************/
\r
19697 #define SYSCFG_UR15_D2STPRST_Pos (0U)
\r
19698 #define SYSCFG_UR15_D2STPRST_Msk (0x1UL << SYSCFG_UR15_D2STPRST_Pos) /*!< 0x00000001 */
\r
19699 #define SYSCFG_UR15_D2STPRST SYSCFG_UR15_D2STPRST_Msk /*!< D2 Stop Reset */
\r
19700 #define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
\r
19701 #define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos) /*!< 0x00010000 */
\r
19702 #define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk /*!< Freeze independent watchdogs in Standby mode */
\r
19704 /****************** Bit definition for SYSCFG_UR16 register *******************/
\r
19705 #define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
\r
19706 #define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos) /*!< 0x00000001 */
\r
19707 #define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk /*!< Freeze independent watchdogs in Stop mode */
\r
19708 #define SYSCFG_UR16_PKP_Pos (16U)
\r
19709 #define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos) /*!< 0x00010000 */
\r
19710 #define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk /*!< Private key programmed */
\r
19712 /****************** Bit definition for SYSCFG_UR17 register *******************/
\r
19713 #define SYSCFG_UR17_IOHSLV_Pos (0U)
\r
19714 #define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos) /*!< 0x00000001 */
\r
19715 #define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk /*!< I/O high speed / low voltage */
\r
19718 /******************************************************************************/
\r
19722 /******************************************************************************/
\r
19723 #define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
\r
19724 /******************* Bit definition for TIM_CR1 register ********************/
\r
19725 #define TIM_CR1_CEN_Pos (0U)
\r
19726 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
\r
19727 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
\r
19728 #define TIM_CR1_UDIS_Pos (1U)
\r
19729 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
\r
19730 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
\r
19731 #define TIM_CR1_URS_Pos (2U)
\r
19732 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
\r
19733 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
\r
19734 #define TIM_CR1_OPM_Pos (3U)
\r
19735 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
\r
19736 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
\r
19737 #define TIM_CR1_DIR_Pos (4U)
\r
19738 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
\r
19739 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
\r
19741 #define TIM_CR1_CMS_Pos (5U)
\r
19742 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
\r
19743 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
\r
19744 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
\r
19745 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
\r
19747 #define TIM_CR1_ARPE_Pos (7U)
\r
19748 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
\r
19749 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
\r
19751 #define TIM_CR1_CKD_Pos (8U)
\r
19752 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
\r
19753 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
\r
19754 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
\r
19755 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
\r
19757 #define TIM_CR1_UIFREMAP_Pos (11U)
\r
19758 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
\r
19759 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
\r
19761 /******************* Bit definition for TIM_CR2 register ********************/
\r
19762 #define TIM_CR2_CCPC_Pos (0U)
\r
19763 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
\r
19764 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
\r
19765 #define TIM_CR2_CCUS_Pos (2U)
\r
19766 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
\r
19767 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
\r
19768 #define TIM_CR2_CCDS_Pos (3U)
\r
19769 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
\r
19770 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
\r
19772 #define TIM_CR2_MMS_Pos (4U)
\r
19773 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
\r
19774 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
\r
19775 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
\r
19776 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
\r
19777 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
\r
19779 #define TIM_CR2_TI1S_Pos (7U)
\r
19780 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
\r
19781 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
\r
19782 #define TIM_CR2_OIS1_Pos (8U)
\r
19783 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
\r
19784 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
\r
19785 #define TIM_CR2_OIS1N_Pos (9U)
\r
19786 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
\r
19787 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
\r
19788 #define TIM_CR2_OIS2_Pos (10U)
\r
19789 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
\r
19790 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
\r
19791 #define TIM_CR2_OIS2N_Pos (11U)
\r
19792 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
\r
19793 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
\r
19794 #define TIM_CR2_OIS3_Pos (12U)
\r
19795 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
\r
19796 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
\r
19797 #define TIM_CR2_OIS3N_Pos (13U)
\r
19798 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
\r
19799 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
\r
19800 #define TIM_CR2_OIS4_Pos (14U)
\r
19801 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
\r
19802 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
\r
19803 #define TIM_CR2_OIS5_Pos (16U)
\r
19804 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
\r
19805 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
\r
19806 #define TIM_CR2_OIS6_Pos (17U)
\r
19807 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
\r
19808 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
\r
19810 #define TIM_CR2_MMS2_Pos (20U)
\r
19811 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
\r
19812 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
\r
19813 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
\r
19814 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
\r
19815 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
\r
19816 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
\r
19818 /******************* Bit definition for TIM_SMCR register *******************/
\r
19819 #define TIM_SMCR_SMS_Pos (0U)
\r
19820 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
\r
19821 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
\r
19822 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
\r
19823 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
\r
19824 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
\r
19825 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
\r
19827 #define TIM_SMCR_TS_Pos (4U)
\r
19828 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
\r
19829 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */
\r
19830 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
\r
19831 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
\r
19832 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
\r
19833 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
\r
19834 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
\r
19836 #define TIM_SMCR_MSM_Pos (7U)
\r
19837 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
\r
19838 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
\r
19840 #define TIM_SMCR_ETF_Pos (8U)
\r
19841 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
\r
19842 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
\r
19843 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
\r
19844 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
\r
19845 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
\r
19846 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
\r
19848 #define TIM_SMCR_ETPS_Pos (12U)
\r
19849 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
\r
19850 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
\r
19851 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
\r
19852 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
\r
19854 #define TIM_SMCR_ECE_Pos (14U)
\r
19855 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
\r
19856 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
\r
19857 #define TIM_SMCR_ETP_Pos (15U)
\r
19858 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
\r
19859 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
\r
19861 /******************* Bit definition for TIM_DIER register *******************/
\r
19862 #define TIM_DIER_UIE_Pos (0U)
\r
19863 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
\r
19864 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
\r
19865 #define TIM_DIER_CC1IE_Pos (1U)
\r
19866 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
\r
19867 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
\r
19868 #define TIM_DIER_CC2IE_Pos (2U)
\r
19869 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
\r
19870 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
\r
19871 #define TIM_DIER_CC3IE_Pos (3U)
\r
19872 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
\r
19873 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
\r
19874 #define TIM_DIER_CC4IE_Pos (4U)
\r
19875 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
\r
19876 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
\r
19877 #define TIM_DIER_COMIE_Pos (5U)
\r
19878 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
\r
19879 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
\r
19880 #define TIM_DIER_TIE_Pos (6U)
\r
19881 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
\r
19882 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
\r
19883 #define TIM_DIER_BIE_Pos (7U)
\r
19884 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
\r
19885 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
\r
19886 #define TIM_DIER_UDE_Pos (8U)
\r
19887 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
\r
19888 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
\r
19889 #define TIM_DIER_CC1DE_Pos (9U)
\r
19890 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
\r
19891 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
\r
19892 #define TIM_DIER_CC2DE_Pos (10U)
\r
19893 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
\r
19894 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
\r
19895 #define TIM_DIER_CC3DE_Pos (11U)
\r
19896 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
\r
19897 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
\r
19898 #define TIM_DIER_CC4DE_Pos (12U)
\r
19899 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
\r
19900 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
\r
19901 #define TIM_DIER_COMDE_Pos (13U)
\r
19902 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
\r
19903 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
\r
19904 #define TIM_DIER_TDE_Pos (14U)
\r
19905 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
\r
19906 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
\r
19908 /******************** Bit definition for TIM_SR register ********************/
\r
19909 #define TIM_SR_UIF_Pos (0U)
\r
19910 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
\r
19911 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
\r
19912 #define TIM_SR_CC1IF_Pos (1U)
\r
19913 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
\r
19914 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
\r
19915 #define TIM_SR_CC2IF_Pos (2U)
\r
19916 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
\r
19917 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
\r
19918 #define TIM_SR_CC3IF_Pos (3U)
\r
19919 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
\r
19920 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
\r
19921 #define TIM_SR_CC4IF_Pos (4U)
\r
19922 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
\r
19923 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
\r
19924 #define TIM_SR_COMIF_Pos (5U)
\r
19925 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
\r
19926 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
\r
19927 #define TIM_SR_TIF_Pos (6U)
\r
19928 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
\r
19929 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
\r
19930 #define TIM_SR_BIF_Pos (7U)
\r
19931 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
\r
19932 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
\r
19933 #define TIM_SR_B2IF_Pos (8U)
\r
19934 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
\r
19935 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
\r
19936 #define TIM_SR_CC1OF_Pos (9U)
\r
19937 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
\r
19938 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
\r
19939 #define TIM_SR_CC2OF_Pos (10U)
\r
19940 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
\r
19941 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
\r
19942 #define TIM_SR_CC3OF_Pos (11U)
\r
19943 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
\r
19944 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
\r
19945 #define TIM_SR_CC4OF_Pos (12U)
\r
19946 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
\r
19947 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
\r
19948 #define TIM_SR_CC5IF_Pos (16U)
\r
19949 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
\r
19950 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
\r
19951 #define TIM_SR_CC6IF_Pos (17U)
\r
19952 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
\r
19953 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
\r
19954 #define TIM_SR_SBIF_Pos (13U)
\r
19955 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
\r
19956 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */
\r
19958 /******************* Bit definition for TIM_EGR register ********************/
\r
19959 #define TIM_EGR_UG_Pos (0U)
\r
19960 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
\r
19961 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
\r
19962 #define TIM_EGR_CC1G_Pos (1U)
\r
19963 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
\r
19964 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
\r
19965 #define TIM_EGR_CC2G_Pos (2U)
\r
19966 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
\r
19967 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
\r
19968 #define TIM_EGR_CC3G_Pos (3U)
\r
19969 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
\r
19970 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
\r
19971 #define TIM_EGR_CC4G_Pos (4U)
\r
19972 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
\r
19973 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
\r
19974 #define TIM_EGR_COMG_Pos (5U)
\r
19975 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
\r
19976 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
\r
19977 #define TIM_EGR_TG_Pos (6U)
\r
19978 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
\r
19979 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
\r
19980 #define TIM_EGR_BG_Pos (7U)
\r
19981 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
\r
19982 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
\r
19983 #define TIM_EGR_B2G_Pos (8U)
\r
19984 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
\r
19985 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
\r
19988 /****************** Bit definition for TIM_CCMR1 register *******************/
\r
19989 #define TIM_CCMR1_CC1S_Pos (0U)
\r
19990 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
\r
19991 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
\r
19992 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
\r
19993 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
\r
19995 #define TIM_CCMR1_OC1FE_Pos (2U)
\r
19996 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
\r
19997 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
\r
19998 #define TIM_CCMR1_OC1PE_Pos (3U)
\r
19999 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
\r
20000 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
\r
20002 #define TIM_CCMR1_OC1M_Pos (4U)
\r
20003 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
\r
20004 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
\r
20005 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
\r
20006 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
\r
20007 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
\r
20008 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
\r
20010 #define TIM_CCMR1_OC1CE_Pos (7U)
\r
20011 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
\r
20012 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
\r
20014 #define TIM_CCMR1_CC2S_Pos (8U)
\r
20015 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
\r
20016 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
\r
20017 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
\r
20018 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
\r
20020 #define TIM_CCMR1_OC2FE_Pos (10U)
\r
20021 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
\r
20022 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
\r
20023 #define TIM_CCMR1_OC2PE_Pos (11U)
\r
20024 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
\r
20025 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
\r
20027 #define TIM_CCMR1_OC2M_Pos (12U)
\r
20028 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
\r
20029 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
\r
20030 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
\r
20031 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
\r
20032 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
\r
20033 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
\r
20035 #define TIM_CCMR1_OC2CE_Pos (15U)
\r
20036 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
\r
20037 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
\r
20039 /*----------------------------------------------------------------------------*/
\r
20041 #define TIM_CCMR1_IC1PSC_Pos (2U)
\r
20042 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
\r
20043 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
\r
20044 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
\r
20045 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
\r
20047 #define TIM_CCMR1_IC1F_Pos (4U)
\r
20048 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
\r
20049 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
\r
20050 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
\r
20051 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
\r
20052 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
\r
20053 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
\r
20055 #define TIM_CCMR1_IC2PSC_Pos (10U)
\r
20056 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
\r
20057 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
\r
20058 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
\r
20059 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
\r
20061 #define TIM_CCMR1_IC2F_Pos (12U)
\r
20062 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
\r
20063 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
\r
20064 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
\r
20065 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
\r
20066 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
\r
20067 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
\r
20069 /****************** Bit definition for TIM_CCMR2 register *******************/
\r
20070 #define TIM_CCMR2_CC3S_Pos (0U)
\r
20071 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
\r
20072 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
\r
20073 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
\r
20074 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
\r
20076 #define TIM_CCMR2_OC3FE_Pos (2U)
\r
20077 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
\r
20078 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
\r
20079 #define TIM_CCMR2_OC3PE_Pos (3U)
\r
20080 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
\r
20081 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
\r
20083 #define TIM_CCMR2_OC3M_Pos (4U)
\r
20084 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
\r
20085 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
\r
20086 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
\r
20087 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
\r
20088 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
\r
20089 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
\r
20091 #define TIM_CCMR2_OC3CE_Pos (7U)
\r
20092 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
\r
20093 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
\r
20095 #define TIM_CCMR2_CC4S_Pos (8U)
\r
20096 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
\r
20097 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
\r
20098 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
\r
20099 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
\r
20101 #define TIM_CCMR2_OC4FE_Pos (10U)
\r
20102 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
\r
20103 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
\r
20104 #define TIM_CCMR2_OC4PE_Pos (11U)
\r
20105 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
\r
20106 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
\r
20108 #define TIM_CCMR2_OC4M_Pos (12U)
\r
20109 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
\r
20110 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
\r
20111 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
\r
20112 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
\r
20113 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
\r
20114 #define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
\r
20116 #define TIM_CCMR2_OC4CE_Pos (15U)
\r
20117 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
\r
20118 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
\r
20120 /*----------------------------------------------------------------------------*/
\r
20122 #define TIM_CCMR2_IC3PSC_Pos (2U)
\r
20123 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
\r
20124 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
\r
20125 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
\r
20126 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
\r
20128 #define TIM_CCMR2_IC3F_Pos (4U)
\r
20129 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
\r
20130 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
\r
20131 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
\r
20132 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
\r
20133 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
\r
20134 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
\r
20136 #define TIM_CCMR2_IC4PSC_Pos (10U)
\r
20137 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
\r
20138 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
\r
20139 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
\r
20140 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
\r
20142 #define TIM_CCMR2_IC4F_Pos (12U)
\r
20143 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
\r
20144 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
\r
20145 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
\r
20146 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
\r
20147 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
\r
20148 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
\r
20150 /******************* Bit definition for TIM_CCER register *******************/
\r
20151 #define TIM_CCER_CC1E_Pos (0U)
\r
20152 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
\r
20153 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
\r
20154 #define TIM_CCER_CC1P_Pos (1U)
\r
20155 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
\r
20156 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
\r
20157 #define TIM_CCER_CC1NE_Pos (2U)
\r
20158 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
\r
20159 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
\r
20160 #define TIM_CCER_CC1NP_Pos (3U)
\r
20161 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
\r
20162 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
\r
20163 #define TIM_CCER_CC2E_Pos (4U)
\r
20164 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
\r
20165 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
\r
20166 #define TIM_CCER_CC2P_Pos (5U)
\r
20167 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
\r
20168 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
\r
20169 #define TIM_CCER_CC2NE_Pos (6U)
\r
20170 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
\r
20171 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
\r
20172 #define TIM_CCER_CC2NP_Pos (7U)
\r
20173 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
\r
20174 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
\r
20175 #define TIM_CCER_CC3E_Pos (8U)
\r
20176 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
\r
20177 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
\r
20178 #define TIM_CCER_CC3P_Pos (9U)
\r
20179 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
\r
20180 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
\r
20181 #define TIM_CCER_CC3NE_Pos (10U)
\r
20182 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
\r
20183 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
\r
20184 #define TIM_CCER_CC3NP_Pos (11U)
\r
20185 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
\r
20186 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
\r
20187 #define TIM_CCER_CC4E_Pos (12U)
\r
20188 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
\r
20189 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
\r
20190 #define TIM_CCER_CC4P_Pos (13U)
\r
20191 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
\r
20192 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
\r
20193 #define TIM_CCER_CC4NP_Pos (15U)
\r
20194 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
\r
20195 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
\r
20196 #define TIM_CCER_CC5E_Pos (16U)
\r
20197 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
\r
20198 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
\r
20199 #define TIM_CCER_CC5P_Pos (17U)
\r
20200 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
\r
20201 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
\r
20202 #define TIM_CCER_CC6E_Pos (20U)
\r
20203 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
\r
20204 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
\r
20205 #define TIM_CCER_CC6P_Pos (21U)
\r
20206 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
\r
20207 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
\r
20208 /******************* Bit definition for TIM_CNT register ********************/
\r
20209 #define TIM_CNT_CNT_Pos (0U)
\r
20210 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
\r
20211 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
\r
20212 #define TIM_CNT_UIFCPY_Pos (31U)
\r
20213 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
\r
20214 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
\r
20215 /******************* Bit definition for TIM_PSC register ********************/
\r
20216 #define TIM_PSC_PSC_Pos (0U)
\r
20217 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
\r
20218 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
\r
20220 /******************* Bit definition for TIM_ARR register ********************/
\r
20221 #define TIM_ARR_ARR_Pos (0U)
\r
20222 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
\r
20223 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
\r
20225 /******************* Bit definition for TIM_RCR register ********************/
\r
20226 #define TIM_RCR_REP_Pos (0U)
\r
20227 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
\r
20228 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
\r
20230 /******************* Bit definition for TIM_CCR1 register *******************/
\r
20231 #define TIM_CCR1_CCR1_Pos (0U)
\r
20232 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
\r
20233 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
\r
20235 /******************* Bit definition for TIM_CCR2 register *******************/
\r
20236 #define TIM_CCR2_CCR2_Pos (0U)
\r
20237 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
\r
20238 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
\r
20240 /******************* Bit definition for TIM_CCR3 register *******************/
\r
20241 #define TIM_CCR3_CCR3_Pos (0U)
\r
20242 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
\r
20243 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
\r
20245 /******************* Bit definition for TIM_CCR4 register *******************/
\r
20246 #define TIM_CCR4_CCR4_Pos (0U)
\r
20247 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
\r
20248 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
\r
20250 /******************* Bit definition for TIM_CCR5 register *******************/
\r
20251 #define TIM_CCR5_CCR5_Pos (0U)
\r
20252 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
\r
20253 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
\r
20254 #define TIM_CCR5_GC5C1_Pos (29U)
\r
20255 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
\r
20256 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
\r
20257 #define TIM_CCR5_GC5C2_Pos (30U)
\r
20258 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
\r
20259 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
\r
20260 #define TIM_CCR5_GC5C3_Pos (31U)
\r
20261 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
\r
20262 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
\r
20264 /******************* Bit definition for TIM_CCR6 register *******************/
\r
20265 #define TIM_CCR6_CCR6_Pos (0U)
\r
20266 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
\r
20267 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
\r
20269 /******************* Bit definition for TIM_BDTR register *******************/
\r
20270 #define TIM_BDTR_DTG_Pos (0U)
\r
20271 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
\r
20272 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
\r
20273 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
\r
20274 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
\r
20275 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
\r
20276 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
\r
20277 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
\r
20278 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
\r
20279 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
\r
20280 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
\r
20282 #define TIM_BDTR_LOCK_Pos (8U)
\r
20283 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
\r
20284 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
\r
20285 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
\r
20286 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
\r
20288 #define TIM_BDTR_OSSI_Pos (10U)
\r
20289 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
\r
20290 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
\r
20291 #define TIM_BDTR_OSSR_Pos (11U)
\r
20292 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
\r
20293 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
\r
20294 #define TIM_BDTR_BKE_Pos (12U)
\r
20295 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
\r
20296 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
\r
20297 #define TIM_BDTR_BKP_Pos (13U)
\r
20298 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
\r
20299 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
\r
20300 #define TIM_BDTR_AOE_Pos (14U)
\r
20301 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
\r
20302 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
\r
20303 #define TIM_BDTR_MOE_Pos (15U)
\r
20304 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
\r
20305 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
\r
20307 #define TIM_BDTR_BKF_Pos (16U)
\r
20308 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
\r
20309 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
\r
20310 #define TIM_BDTR_BK2F_Pos (20U)
\r
20311 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
\r
20312 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
\r
20314 #define TIM_BDTR_BK2E_Pos (24U)
\r
20315 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
\r
20316 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
\r
20317 #define TIM_BDTR_BK2P_Pos (25U)
\r
20318 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
\r
20319 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
\r
20321 /******************* Bit definition for TIM_DCR register ********************/
\r
20322 #define TIM_DCR_DBA_Pos (0U)
\r
20323 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
\r
20324 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
\r
20325 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
\r
20326 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
\r
20327 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
\r
20328 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
\r
20329 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
\r
20331 #define TIM_DCR_DBL_Pos (8U)
\r
20332 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
\r
20333 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
\r
20334 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
\r
20335 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
\r
20336 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
\r
20337 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
\r
20338 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
\r
20340 /******************* Bit definition for TIM_DMAR register *******************/
\r
20341 #define TIM_DMAR_DMAB_Pos (0U)
\r
20342 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
\r
20343 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
\r
20345 /****************** Bit definition for TIM_CCMR3 register *******************/
\r
20346 #define TIM_CCMR3_OC5FE_Pos (2U)
\r
20347 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
\r
20348 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
\r
20349 #define TIM_CCMR3_OC5PE_Pos (3U)
\r
20350 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
\r
20351 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
\r
20353 #define TIM_CCMR3_OC5M_Pos (4U)
\r
20354 #define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
\r
20355 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
\r
20356 #define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
\r
20357 #define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
\r
20358 #define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
\r
20359 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
\r
20361 #define TIM_CCMR3_OC5CE_Pos (7U)
\r
20362 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
\r
20363 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
\r
20365 #define TIM_CCMR3_OC6FE_Pos (10U)
\r
20366 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
\r
20367 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
\r
20368 #define TIM_CCMR3_OC6PE_Pos (11U)
\r
20369 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
\r
20370 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
\r
20372 #define TIM_CCMR3_OC6M_Pos (12U)
\r
20373 #define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
\r
20374 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
\r
20375 #define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
\r
20376 #define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
\r
20377 #define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
\r
20378 #define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
\r
20380 #define TIM_CCMR3_OC6CE_Pos (15U)
\r
20381 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
\r
20382 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
\r
20383 /******************* Bit definition for TIM1_AF1 register *********************/
\r
20384 #define TIM1_AF1_BKINE_Pos (0U)
\r
20385 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
\r
20386 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
\r
20387 #define TIM1_AF1_BKCMP1E_Pos (1U)
\r
20388 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
\r
20389 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
\r
20390 #define TIM1_AF1_BKCMP2E_Pos (2U)
\r
20391 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
\r
20392 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
\r
20393 #define TIM1_AF1_BKDF1BK0E_Pos (8U)
\r
20394 #define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) /*!< 0x00000100 */
\r
20395 #define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk /*!<BKDF1BK0E Break input DFSDM Break 0 */
\r
20396 #define TIM1_AF1_BKINP_Pos (9U)
\r
20397 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
\r
20398 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
\r
20399 #define TIM1_AF1_BKCMP1P_Pos (10U)
\r
20400 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
\r
20401 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
\r
20402 #define TIM1_AF1_BKCMP2P_Pos (11U)
\r
20403 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
\r
20404 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
\r
20406 #define TIM1_AF1_ETRSEL_Pos (14U)
\r
20407 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
\r
20408 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
\r
20409 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
\r
20410 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
\r
20411 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
\r
20412 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
\r
20414 /******************* Bit definition for TIM1_AF2 register *********************/
\r
20415 #define TIM1_AF2_BK2INE_Pos (0U)
\r
20416 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
\r
20417 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
\r
20418 #define TIM1_AF2_BK2CMP1E_Pos (1U)
\r
20419 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
\r
20420 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
\r
20421 #define TIM1_AF2_BK2CMP2E_Pos (2U)
\r
20422 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
\r
20423 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
\r
20424 #define TIM1_AF2_BK2DFBK1E_Pos (8U)
\r
20425 #define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos) /*!< 0x00000100 */
\r
20426 #define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
\r
20427 #define TIM1_AF2_BK2INP_Pos (9U)
\r
20428 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
\r
20429 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
\r
20430 #define TIM1_AF2_BK2CMP1P_Pos (10U)
\r
20431 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
\r
20432 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
\r
20433 #define TIM1_AF2_BK2CMP2P_Pos (11U)
\r
20434 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
\r
20435 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
\r
20437 /******************* Bit definition for TIM_TISEL register *********************/
\r
20438 #define TIM_TISEL_TI1SEL_Pos (0U)
\r
20439 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
\r
20440 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
\r
20441 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
\r
20442 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
\r
20443 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
\r
20444 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
\r
20446 #define TIM_TISEL_TI2SEL_Pos (8U)
\r
20447 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
\r
20448 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
\r
20449 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
\r
20450 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
\r
20451 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
\r
20452 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
\r
20454 #define TIM_TISEL_TI3SEL_Pos (16U)
\r
20455 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
\r
20456 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
\r
20457 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
\r
20458 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
\r
20459 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
\r
20460 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
\r
20462 #define TIM_TISEL_TI4SEL_Pos (24U)
\r
20463 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
\r
20464 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
\r
20465 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
\r
20466 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
\r
20467 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
\r
20468 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
\r
20470 /******************* Bit definition for TIM8_AF1 register *********************/
\r
20471 #define TIM8_AF1_BKINE_Pos (0U)
\r
20472 #define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
\r
20473 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
\r
20474 #define TIM8_AF1_BKCMP1E_Pos (1U)
\r
20475 #define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
\r
20476 #define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
\r
20477 #define TIM8_AF1_BKCMP2E_Pos (2U)
\r
20478 #define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
\r
20479 #define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
\r
20480 #define TIM8_AF1_BKDFBK2E_Pos (8U)
\r
20481 #define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */
\r
20482 #define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */
\r
20483 #define TIM8_AF1_BKINP_Pos (9U)
\r
20484 #define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
\r
20485 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
\r
20486 #define TIM8_AF1_BKCMP1P_Pos (10U)
\r
20487 #define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
\r
20488 #define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
\r
20489 #define TIM8_AF1_BKCMP2P_Pos (11U)
\r
20490 #define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
\r
20491 #define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
\r
20493 #define TIM8_AF1_ETRSEL_Pos (14U)
\r
20494 #define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
\r
20495 #define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
\r
20496 #define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00004000 */
\r
20497 #define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00008000 */
\r
20498 #define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00010000 */
\r
20499 #define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00020000 */
\r
20500 /******************* Bit definition for TIM8_AF2 register *********************/
\r
20501 #define TIM8_AF2_BK2INE_Pos (0U)
\r
20502 #define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
\r
20503 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
\r
20504 #define TIM8_AF2_BK2CMP1E_Pos (1U)
\r
20505 #define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
\r
20506 #define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
\r
20507 #define TIM8_AF2_BK2CMP2E_Pos (2U)
\r
20508 #define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
\r
20509 #define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
\r
20510 #define TIM8_AF2_BK2DFBK3E_Pos (8U)
\r
20511 #define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */
\r
20512 #define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
\r
20513 #define TIM8_AF2_BK2INP_Pos (9U)
\r
20514 #define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
\r
20515 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
\r
20516 #define TIM8_AF2_BK2CMP1P_Pos (10U)
\r
20517 #define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
\r
20518 #define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
\r
20519 #define TIM8_AF2_BK2CMP2P_Pos (11U)
\r
20520 #define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
\r
20521 #define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
\r
20523 /******************* Bit definition for TIM2_AF1 register *********************/
\r
20524 #define TIM2_AF1_ETRSEL_Pos (14U)
\r
20525 #define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
\r
20526 #define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
\r
20527 #define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
\r
20528 #define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
\r
20529 #define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
\r
20530 #define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
\r
20532 /******************* Bit definition for TIM3_AF1 register *********************/
\r
20533 #define TIM3_AF1_ETRSEL_Pos (14U)
\r
20534 #define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
\r
20535 #define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
\r
20536 #define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
\r
20537 #define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
\r
20538 #define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
\r
20539 #define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
\r
20541 /******************* Bit definition for TIM5_AF1 register *********************/
\r
20542 #define TIM5_AF1_ETRSEL_Pos (14U)
\r
20543 #define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
\r
20544 #define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
\r
20545 #define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00004000 */
\r
20546 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */
\r
20547 #define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00010000 */
\r
20548 #define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00020000 */
\r
20550 /******************* Bit definition for TIM15_AF1 register *********************/
\r
20551 #define TIM15_AF1_BKINE_Pos (0U)
\r
20552 #define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
\r
20553 #define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
\r
20554 #define TIM15_AF1_BKCMP1E_Pos (1U)
\r
20555 #define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
\r
20556 #define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
\r
20557 #define TIM15_AF1_BKCMP2E_Pos (2U)
\r
20558 #define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
\r
20559 #define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
\r
20560 #define TIM15_AF1_BKDF1BK2E_Pos (8U)
\r
20561 #define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
\r
20562 #define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */
\r
20563 #define TIM15_AF1_BKINP_Pos (9U)
\r
20564 #define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
\r
20565 #define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
\r
20566 #define TIM15_AF1_BKCMP1P_Pos (10U)
\r
20567 #define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
\r
20568 #define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
\r
20569 #define TIM15_AF1_BKCMP2P_Pos (11U)
\r
20570 #define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
\r
20571 #define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
\r
20573 /******************* Bit definition for TIM16_ register *********************/
\r
20574 #define TIM16_AF1_BKINE_Pos (0U)
\r
20575 #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
\r
20576 #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
\r
20577 #define TIM16_AF1_BKCMP1E_Pos (1U)
\r
20578 #define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
\r
20579 #define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
\r
20580 #define TIM16_AF1_BKCMP2E_Pos (2U)
\r
20581 #define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
\r
20582 #define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
\r
20583 #define TIM16_AF1_BKDF1BK2E_Pos (8U)
\r
20584 #define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
\r
20585 #define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */
\r
20586 #define TIM16_AF1_BKINP_Pos (9U)
\r
20587 #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
\r
20588 #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
\r
20589 #define TIM16_AF1_BKCMP1P_Pos (10U)
\r
20590 #define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
\r
20591 #define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
\r
20592 #define TIM16_AF1_BKCMP2P_Pos (11U)
\r
20593 #define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
\r
20594 #define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
\r
20596 /******************* Bit definition for TIM17_AF1 register *********************/
\r
20597 #define TIM17_AF1_BKINE_Pos (0U)
\r
20598 #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
\r
20599 #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
\r
20600 #define TIM17_AF1_BKCMP1E_Pos (1U)
\r
20601 #define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
\r
20602 #define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
\r
20603 #define TIM17_AF1_BKCMP2E_Pos (2U)
\r
20604 #define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
\r
20605 #define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
\r
20606 #define TIM17_AF1_BKDF1BK2E_Pos (8U)
\r
20607 #define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
\r
20608 #define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */
\r
20609 #define TIM17_AF1_BKINP_Pos (9U)
\r
20610 #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
\r
20611 #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
\r
20612 #define TIM17_AF1_BKCMP1P_Pos (10U)
\r
20613 #define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
\r
20614 #define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
\r
20615 #define TIM17_AF1_BKCMP2P_Pos (11U)
\r
20616 #define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
\r
20617 #define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
\r
20619 /******************************************************************************/
\r
20621 /* Low Power Timer (LPTTIM) */
\r
20623 /******************************************************************************/
\r
20624 /****************** Bit definition for LPTIM_ISR register *******************/
\r
20625 #define LPTIM_ISR_CMPM_Pos (0U)
\r
20626 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
\r
20627 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
\r
20628 #define LPTIM_ISR_ARRM_Pos (1U)
\r
20629 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
\r
20630 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
\r
20631 #define LPTIM_ISR_EXTTRIG_Pos (2U)
\r
20632 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
\r
20633 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
\r
20634 #define LPTIM_ISR_CMPOK_Pos (3U)
\r
20635 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
\r
20636 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
\r
20637 #define LPTIM_ISR_ARROK_Pos (4U)
\r
20638 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
\r
20639 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
\r
20640 #define LPTIM_ISR_UP_Pos (5U)
\r
20641 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
\r
20642 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
\r
20643 #define LPTIM_ISR_DOWN_Pos (6U)
\r
20644 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
\r
20645 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
\r
20647 /****************** Bit definition for LPTIM_ICR register *******************/
\r
20648 #define LPTIM_ICR_CMPMCF_Pos (0U)
\r
20649 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
\r
20650 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
\r
20651 #define LPTIM_ICR_ARRMCF_Pos (1U)
\r
20652 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
\r
20653 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
\r
20654 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
\r
20655 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
\r
20656 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
\r
20657 #define LPTIM_ICR_CMPOKCF_Pos (3U)
\r
20658 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
\r
20659 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
\r
20660 #define LPTIM_ICR_ARROKCF_Pos (4U)
\r
20661 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
\r
20662 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
\r
20663 #define LPTIM_ICR_UPCF_Pos (5U)
\r
20664 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
\r
20665 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
\r
20666 #define LPTIM_ICR_DOWNCF_Pos (6U)
\r
20667 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
\r
20668 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
\r
20670 /****************** Bit definition for LPTIM_IER register ********************/
\r
20671 #define LPTIM_IER_CMPMIE_Pos (0U)
\r
20672 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
\r
20673 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
\r
20674 #define LPTIM_IER_ARRMIE_Pos (1U)
\r
20675 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
\r
20676 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
\r
20677 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
\r
20678 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
\r
20679 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
\r
20680 #define LPTIM_IER_CMPOKIE_Pos (3U)
\r
20681 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
\r
20682 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
\r
20683 #define LPTIM_IER_ARROKIE_Pos (4U)
\r
20684 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
\r
20685 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
\r
20686 #define LPTIM_IER_UPIE_Pos (5U)
\r
20687 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
\r
20688 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
\r
20689 #define LPTIM_IER_DOWNIE_Pos (6U)
\r
20690 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
\r
20691 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
\r
20693 /****************** Bit definition for LPTIM_CFGR register *******************/
\r
20694 #define LPTIM_CFGR_CKSEL_Pos (0U)
\r
20695 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
\r
20696 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
\r
20698 #define LPTIM_CFGR_CKPOL_Pos (1U)
\r
20699 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
\r
20700 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
\r
20701 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
\r
20702 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
\r
20704 #define LPTIM_CFGR_CKFLT_Pos (3U)
\r
20705 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
\r
20706 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
\r
20707 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
\r
20708 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
\r
20710 #define LPTIM_CFGR_TRGFLT_Pos (6U)
\r
20711 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
\r
20712 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
\r
20713 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
\r
20714 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
\r
20716 #define LPTIM_CFGR_PRESC_Pos (9U)
\r
20717 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
\r
20718 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
\r
20719 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
\r
20720 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
\r
20721 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
\r
20723 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
\r
20724 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
\r
20725 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
\r
20726 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
\r
20727 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
\r
20728 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
\r
20730 #define LPTIM_CFGR_TRIGEN_Pos (17U)
\r
20731 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
\r
20732 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
\r
20733 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
\r
20734 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
\r
20736 #define LPTIM_CFGR_TIMOUT_Pos (19U)
\r
20737 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
\r
20738 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
\r
20739 #define LPTIM_CFGR_WAVE_Pos (20U)
\r
20740 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
\r
20741 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
\r
20742 #define LPTIM_CFGR_WAVPOL_Pos (21U)
\r
20743 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
\r
20744 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
\r
20745 #define LPTIM_CFGR_PRELOAD_Pos (22U)
\r
20746 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
\r
20747 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
\r
20748 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
\r
20749 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
\r
20750 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
\r
20751 #define LPTIM_CFGR_ENC_Pos (24U)
\r
20752 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
\r
20753 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
\r
20755 /****************** Bit definition for LPTIM_CR register ********************/
\r
20756 #define LPTIM_CR_ENABLE_Pos (0U)
\r
20757 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
\r
20758 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
\r
20759 #define LPTIM_CR_SNGSTRT_Pos (1U)
\r
20760 #define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00080002 */
\r
20761 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
\r
20762 #define LPTIM_CR_CNTSTRT_Pos (2U)
\r
20763 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
\r
20764 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
\r
20765 #define LPTIM_CR_COUNTRST_Pos (3U)
\r
20766 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
\r
20767 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/
\r
20768 #define LPTIM_CR_RSTARE_Pos (4U)
\r
20769 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
\r
20770 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/
\r
20773 /****************** Bit definition for LPTIM_CMP register *******************/
\r
20774 #define LPTIM_CMP_CMP_Pos (0U)
\r
20775 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
\r
20776 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
\r
20778 /****************** Bit definition for LPTIM_ARR register *******************/
\r
20779 #define LPTIM_ARR_ARR_Pos (0U)
\r
20780 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
\r
20781 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
\r
20783 /****************** Bit definition for LPTIM_CNT register *******************/
\r
20784 #define LPTIM_CNT_CNT_Pos (0U)
\r
20785 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
\r
20786 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
\r
20788 /****************** Bit definition for LPTIM_CFGR2 register *****************/
\r
20789 #define LPTIM_CFGR2_IN1SEL_Pos (0U)
\r
20790 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */
\r
20791 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bits (Remap selection) */
\r
20792 #define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */
\r
20793 #define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */
\r
20794 #define LPTIM_CFGR2_IN2SEL_Pos (4U)
\r
20795 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
\r
20796 #define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< IN2SEL[5:4] bits (Remap selection) */
\r
20797 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
\r
20798 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
\r
20800 /******************************************************************************/
\r
20802 /* Analog Comparators (COMP) */
\r
20804 /******************************************************************************/
\r
20806 /******************* Bit definition for COMP_SR register ********************/
\r
20807 #define COMP_SR_C1VAL_Pos (0U)
\r
20808 #define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */
\r
20809 #define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
\r
20810 #define COMP_SR_C2VAL_Pos (1U)
\r
20811 #define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */
\r
20812 #define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
\r
20813 #define COMP_SR_C1IF_Pos (16U)
\r
20814 #define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */
\r
20815 #define COMP_SR_C1IF COMP_SR_C1IF_Msk
\r
20816 #define COMP_SR_C2IF_Pos (17U)
\r
20817 #define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */
\r
20818 #define COMP_SR_C2IF COMP_SR_C2IF_Msk
\r
20819 /******************* Bit definition for COMP_ICFR register ********************/
\r
20820 #define COMP_ICFR_C1IF_Pos (16U)
\r
20821 #define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */
\r
20822 #define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
\r
20823 #define COMP_ICFR_C2IF_Pos (17U)
\r
20824 #define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */
\r
20825 #define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
\r
20826 /******************* Bit definition for COMP_OR register ********************/
\r
20827 #define COMP_OR_AFOPA6_Pos (0U)
\r
20828 #define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */
\r
20829 #define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
\r
20830 #define COMP_OR_AFOPA8_Pos (1U)
\r
20831 #define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */
\r
20832 #define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
\r
20833 #define COMP_OR_AFOPB12_Pos (2U)
\r
20834 #define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */
\r
20835 #define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
\r
20836 #define COMP_OR_AFOPE6_Pos (3U)
\r
20837 #define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */
\r
20838 #define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
\r
20839 #define COMP_OR_AFOPE15_Pos (4U)
\r
20840 #define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */
\r
20841 #define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
\r
20842 #define COMP_OR_AFOPG2_Pos (5U)
\r
20843 #define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */
\r
20844 #define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
\r
20845 #define COMP_OR_AFOPG3_Pos (6U)
\r
20846 #define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */
\r
20847 #define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
\r
20848 #define COMP_OR_AFOPG4_Pos (7U)
\r
20849 #define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */
\r
20850 #define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
\r
20851 #define COMP_OR_AFOPI1_Pos (8U)
\r
20852 #define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */
\r
20853 #define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
\r
20854 #define COMP_OR_AFOPI4_Pos (9U)
\r
20855 #define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */
\r
20856 #define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
\r
20857 #define COMP_OR_AFOPK2_Pos (10U)
\r
20858 #define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */
\r
20859 #define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
\r
20861 /*!< ****************** Bit definition for COMP_CFGRx register ********************/
\r
20862 #define COMP_CFGRx_EN_Pos (0U)
\r
20863 #define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */
\r
20864 #define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */
\r
20865 #define COMP_CFGRx_BRGEN_Pos (1U)
\r
20866 #define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */
\r
20867 #define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */
\r
20868 #define COMP_CFGRx_SCALEN_Pos (2U)
\r
20869 #define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */
\r
20870 #define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */
\r
20871 #define COMP_CFGRx_POLARITY_Pos (3U)
\r
20872 #define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */
\r
20873 #define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */
\r
20874 #define COMP_CFGRx_WINMODE_Pos (4U)
\r
20875 #define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */
\r
20876 #define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */
\r
20877 #define COMP_CFGRx_ITEN_Pos (6U)
\r
20878 #define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */
\r
20879 #define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */
\r
20880 #define COMP_CFGRx_HYST_Pos (8U)
\r
20881 #define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */
\r
20882 #define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */
\r
20883 #define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */
\r
20884 #define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */
\r
20885 #define COMP_CFGRx_PWRMODE_Pos (12U)
\r
20886 #define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */
\r
20887 #define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
\r
20888 #define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */
\r
20889 #define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */
\r
20890 #define COMP_CFGRx_INMSEL_Pos (16U)
\r
20891 #define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00070000 */
\r
20892 #define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */
\r
20893 #define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */
\r
20894 #define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */
\r
20895 #define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */
\r
20896 #define COMP_CFGRx_INPSEL_Pos (20U)
\r
20897 #define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */
\r
20898 #define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */
\r
20899 #define COMP_CFGRx_BLANKING_Pos (24U)
\r
20900 #define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */
\r
20901 #define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */
\r
20902 #define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */
\r
20903 #define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */
\r
20904 #define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */
\r
20905 #define COMP_CFGRx_LOCK_Pos (31U)
\r
20906 #define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */
\r
20907 #define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */
\r
20910 /******************************************************************************/
\r
20912 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
\r
20914 /******************************************************************************/
\r
20915 /****************** Bit definition for USART_CR1 register *******************/
\r
20916 #define USART_CR1_UE_Pos (0U)
\r
20917 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
\r
20918 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
\r
20919 #define USART_CR1_UESM_Pos (1U)
\r
20920 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
\r
20921 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
\r
20922 #define USART_CR1_RE_Pos (2U)
\r
20923 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
\r
20924 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
\r
20925 #define USART_CR1_TE_Pos (3U)
\r
20926 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
\r
20927 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
\r
20928 #define USART_CR1_IDLEIE_Pos (4U)
\r
20929 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
\r
20930 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
\r
20931 #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
\r
20932 #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
\r
20933 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
\r
20934 #define USART_CR1_TCIE_Pos (6U)
\r
20935 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
\r
20936 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
\r
20937 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
\r
20938 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
\r
20939 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
\r
20940 #define USART_CR1_PEIE_Pos (8U)
\r
20941 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
\r
20942 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
\r
20943 #define USART_CR1_PS_Pos (9U)
\r
20944 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
\r
20945 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
\r
20946 #define USART_CR1_PCE_Pos (10U)
\r
20947 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
\r
20948 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
\r
20949 #define USART_CR1_WAKE_Pos (11U)
\r
20950 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
\r
20951 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
\r
20952 #define USART_CR1_M_Pos (12U)
\r
20953 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
\r
20954 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
\r
20955 #define USART_CR1_M0_Pos (12U)
\r
20956 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
\r
20957 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
\r
20958 #define USART_CR1_MME_Pos (13U)
\r
20959 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
\r
20960 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
\r
20961 #define USART_CR1_CMIE_Pos (14U)
\r
20962 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
\r
20963 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
\r
20964 #define USART_CR1_OVER8_Pos (15U)
\r
20965 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
\r
20966 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
\r
20967 #define USART_CR1_DEDT_Pos (16U)
\r
20968 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
\r
20969 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
\r
20970 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
\r
20971 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
\r
20972 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
\r
20973 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
\r
20974 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
\r
20975 #define USART_CR1_DEAT_Pos (21U)
\r
20976 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
\r
20977 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
\r
20978 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
\r
20979 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
\r
20980 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
\r
20981 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
\r
20982 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
\r
20983 #define USART_CR1_RTOIE_Pos (26U)
\r
20984 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
\r
20985 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
\r
20986 #define USART_CR1_EOBIE_Pos (27U)
\r
20987 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
\r
20988 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
\r
20989 #define USART_CR1_M1_Pos (28U)
\r
20990 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
\r
20991 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
\r
20992 #define USART_CR1_FIFOEN_Pos (29U)
\r
20993 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
\r
20994 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
\r
20995 #define USART_CR1_TXFEIE_Pos (30U)
\r
20996 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
\r
20997 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
\r
20998 #define USART_CR1_RXFFIE_Pos (31U)
\r
20999 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
\r
21000 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
\r
21002 /* Legacy define */
\r
21003 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
\r
21004 #define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
\r
21006 /****************** Bit definition for USART_CR2 register *******************/
\r
21007 #define USART_CR2_SLVEN_Pos (0U)
\r
21008 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
\r
21009 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode Enable */
\r
21010 #define USART_CR2_DIS_NSS_Pos (3U)
\r
21011 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
\r
21012 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Negative Slave Select (NSS) pin management */
\r
21013 #define USART_CR2_ADDM7_Pos (4U)
\r
21014 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
\r
21015 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
\r
21016 #define USART_CR2_LBDL_Pos (5U)
\r
21017 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
\r
21018 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
\r
21019 #define USART_CR2_LBDIE_Pos (6U)
\r
21020 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
\r
21021 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
\r
21022 #define USART_CR2_LBCL_Pos (8U)
\r
21023 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
\r
21024 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
\r
21025 #define USART_CR2_CPHA_Pos (9U)
\r
21026 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
\r
21027 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
\r
21028 #define USART_CR2_CPOL_Pos (10U)
\r
21029 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
\r
21030 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
\r
21031 #define USART_CR2_CLKEN_Pos (11U)
\r
21032 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
\r
21033 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
\r
21034 #define USART_CR2_STOP_Pos (12U)
\r
21035 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
\r
21036 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
\r
21037 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
\r
21038 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
\r
21039 #define USART_CR2_LINEN_Pos (14U)
\r
21040 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
\r
21041 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
\r
21042 #define USART_CR2_SWAP_Pos (15U)
\r
21043 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
\r
21044 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
\r
21045 #define USART_CR2_RXINV_Pos (16U)
\r
21046 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
\r
21047 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
\r
21048 #define USART_CR2_TXINV_Pos (17U)
\r
21049 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
\r
21050 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
\r
21051 #define USART_CR2_DATAINV_Pos (18U)
\r
21052 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
\r
21053 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
\r
21054 #define USART_CR2_MSBFIRST_Pos (19U)
\r
21055 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
\r
21056 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
\r
21057 #define USART_CR2_ABREN_Pos (20U)
\r
21058 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
\r
21059 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
\r
21060 #define USART_CR2_ABRMODE_Pos (21U)
\r
21061 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
\r
21062 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
\r
21063 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
\r
21064 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
\r
21065 #define USART_CR2_RTOEN_Pos (23U)
\r
21066 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
\r
21067 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
\r
21068 #define USART_CR2_ADD_Pos (24U)
\r
21069 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
\r
21070 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
\r
21072 /****************** Bit definition for USART_CR3 register *******************/
\r
21073 #define USART_CR3_EIE_Pos (0U)
\r
21074 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
\r
21075 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
\r
21076 #define USART_CR3_IREN_Pos (1U)
\r
21077 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
\r
21078 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
\r
21079 #define USART_CR3_IRLP_Pos (2U)
\r
21080 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
\r
21081 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
\r
21082 #define USART_CR3_HDSEL_Pos (3U)
\r
21083 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
\r
21084 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
\r
21085 #define USART_CR3_NACK_Pos (4U)
\r
21086 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
\r
21087 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
\r
21088 #define USART_CR3_SCEN_Pos (5U)
\r
21089 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
\r
21090 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
\r
21091 #define USART_CR3_DMAR_Pos (6U)
\r
21092 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
\r
21093 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
\r
21094 #define USART_CR3_DMAT_Pos (7U)
\r
21095 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
\r
21096 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
\r
21097 #define USART_CR3_RTSE_Pos (8U)
\r
21098 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
\r
21099 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
\r
21100 #define USART_CR3_CTSE_Pos (9U)
\r
21101 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
\r
21102 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
\r
21103 #define USART_CR3_CTSIE_Pos (10U)
\r
21104 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
\r
21105 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
\r
21106 #define USART_CR3_ONEBIT_Pos (11U)
\r
21107 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
\r
21108 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
\r
21109 #define USART_CR3_OVRDIS_Pos (12U)
\r
21110 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
\r
21111 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
\r
21112 #define USART_CR3_DDRE_Pos (13U)
\r
21113 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
\r
21114 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
\r
21115 #define USART_CR3_DEM_Pos (14U)
\r
21116 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
\r
21117 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
\r
21118 #define USART_CR3_DEP_Pos (15U)
\r
21119 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
\r
21120 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
\r
21121 #define USART_CR3_SCARCNT_Pos (17U)
\r
21122 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
\r
21123 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
\r
21124 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
\r
21125 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
\r
21126 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
\r
21127 #define USART_CR3_WUS_Pos (20U)
\r
21128 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
\r
21129 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
\r
21130 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
\r
21131 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
\r
21132 #define USART_CR3_WUFIE_Pos (22U)
\r
21133 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
\r
21134 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
\r
21135 #define USART_CR3_TXFTIE_Pos (23U)
\r
21136 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
\r
21137 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
\r
21138 #define USART_CR3_TCBGTIE_Pos (24U)
\r
21139 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
\r
21140 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete before guard time, interrupt enable */
\r
21141 #define USART_CR3_RXFTCFG_Pos (25U)
\r
21142 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
\r
21143 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
\r
21144 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
\r
21145 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
\r
21146 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
\r
21147 #define USART_CR3_RXFTIE_Pos (28U)
\r
21148 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
\r
21149 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
\r
21150 #define USART_CR3_TXFTCFG_Pos (29U)
\r
21151 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
\r
21152 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO [2:0] threshold configuration */
\r
21153 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
\r
21154 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
\r
21155 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
\r
21157 /****************** Bit definition for USART_BRR register *******************/
\r
21158 #define USART_BRR_DIV_FRACTION_Pos (0U)
\r
21159 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
\r
21160 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
\r
21161 #define USART_BRR_DIV_MANTISSA_Pos (4U)
\r
21162 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
\r
21163 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
\r
21165 /****************** Bit definition for USART_GTPR register ******************/
\r
21166 #define USART_GTPR_PSC_Pos (0U)
\r
21167 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
\r
21168 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
\r
21169 #define USART_GTPR_GT_Pos (8U)
\r
21170 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
\r
21171 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
\r
21173 /******************* Bit definition for USART_RTOR register *****************/
\r
21174 #define USART_RTOR_RTO_Pos (0U)
\r
21175 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
\r
21176 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
\r
21177 #define USART_RTOR_BLEN_Pos (24U)
\r
21178 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
\r
21179 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
\r
21181 /******************* Bit definition for USART_RQR register ******************/
\r
21182 #define USART_RQR_ABRRQ_Pos (0U)
\r
21183 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
\r
21184 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
\r
21185 #define USART_RQR_SBKRQ_Pos (1U)
\r
21186 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
\r
21187 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
\r
21188 #define USART_RQR_MMRQ_Pos (2U)
\r
21189 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
\r
21190 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
\r
21191 #define USART_RQR_RXFRQ_Pos (3U)
\r
21192 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
\r
21193 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
\r
21194 #define USART_RQR_TXFRQ_Pos (4U)
\r
21195 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
\r
21196 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
\r
21198 /******************* Bit definition for USART_ISR register ******************/
\r
21199 #define USART_ISR_PE_Pos (0U)
\r
21200 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
\r
21201 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
\r
21202 #define USART_ISR_FE_Pos (1U)
\r
21203 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
\r
21204 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
\r
21205 #define USART_ISR_NE_Pos (2U)
\r
21206 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
\r
21207 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
\r
21208 #define USART_ISR_ORE_Pos (3U)
\r
21209 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
\r
21210 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
\r
21211 #define USART_ISR_IDLE_Pos (4U)
\r
21212 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
\r
21213 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
\r
21214 #define USART_ISR_RXNE_RXFNE_Pos (5U)
\r
21215 #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
\r
21216 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
\r
21217 #define USART_ISR_TC_Pos (6U)
\r
21218 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
\r
21219 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
\r
21220 #define USART_ISR_TXE_TXFNF_Pos (7U)
\r
21221 #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
\r
21222 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
\r
21223 #define USART_ISR_LBDF_Pos (8U)
\r
21224 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
\r
21225 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
\r
21226 #define USART_ISR_CTSIF_Pos (9U)
\r
21227 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
\r
21228 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
\r
21229 #define USART_ISR_CTS_Pos (10U)
\r
21230 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
\r
21231 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
\r
21232 #define USART_ISR_RTOF_Pos (11U)
\r
21233 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
\r
21234 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
\r
21235 #define USART_ISR_EOBF_Pos (12U)
\r
21236 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
\r
21237 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
\r
21238 #define USART_ISR_UDR_Pos (13U)
\r
21239 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
\r
21240 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
\r
21241 #define USART_ISR_ABRE_Pos (14U)
\r
21242 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
\r
21243 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
\r
21244 #define USART_ISR_ABRF_Pos (15U)
\r
21245 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
\r
21246 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
\r
21247 #define USART_ISR_BUSY_Pos (16U)
\r
21248 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
\r
21249 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
\r
21250 #define USART_ISR_CMF_Pos (17U)
\r
21251 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
\r
21252 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
\r
21253 #define USART_ISR_SBKF_Pos (18U)
\r
21254 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
\r
21255 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
\r
21256 #define USART_ISR_RWU_Pos (19U)
\r
21257 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
\r
21258 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
\r
21259 #define USART_ISR_WUF_Pos (20U)
\r
21260 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
\r
21261 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
\r
21262 #define USART_ISR_TEACK_Pos (21U)
\r
21263 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
\r
21264 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
\r
21265 #define USART_ISR_REACK_Pos (22U)
\r
21266 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
\r
21267 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
\r
21268 #define USART_ISR_TXFE_Pos (23U)
\r
21269 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
\r
21270 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
\r
21271 #define USART_ISR_RXFF_Pos (24U)
\r
21272 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
\r
21273 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
\r
21274 #define USART_ISR_TCBGT_Pos (25U)
\r
21275 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
\r
21276 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission complete before guard time Flag */
\r
21277 #define USART_ISR_RXFT_Pos (26U)
\r
21278 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
\r
21279 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold Flag */
\r
21280 #define USART_ISR_TXFT_Pos (27U)
\r
21281 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
\r
21282 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold Flag */
\r
21284 /******************* Bit definition for USART_ICR register ******************/
\r
21285 #define USART_ICR_PECF_Pos (0U)
\r
21286 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
\r
21287 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
\r
21288 #define USART_ICR_FECF_Pos (1U)
\r
21289 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
\r
21290 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
\r
21291 #define USART_ICR_NECF_Pos (2U)
\r
21292 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
\r
21293 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
\r
21294 #define USART_ICR_ORECF_Pos (3U)
\r
21295 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
\r
21296 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
\r
21297 #define USART_ICR_IDLECF_Pos (4U)
\r
21298 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
\r
21299 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
\r
21300 #define USART_ICR_TXFECF_Pos (5U)
\r
21301 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
\r
21302 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty clear flag */
\r
21303 #define USART_ICR_TCCF_Pos (6U)
\r
21304 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
\r
21305 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
\r
21306 #define USART_ICR_TCBGTCF_Pos (7U)
\r
21307 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
\r
21308 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission complete before guard time Clear Flag */
\r
21309 #define USART_ICR_LBDCF_Pos (8U)
\r
21310 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
\r
21311 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
\r
21312 #define USART_ICR_CTSCF_Pos (9U)
\r
21313 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
\r
21314 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
\r
21315 #define USART_ICR_RTOCF_Pos (11U)
\r
21316 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
\r
21317 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
\r
21318 #define USART_ICR_EOBCF_Pos (12U)
\r
21319 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
\r
21320 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
\r
21321 #define USART_ICR_UDRCF_Pos (13U)
\r
21322 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
\r
21323 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI slave underrun clear flag */
\r
21324 #define USART_ICR_CMCF_Pos (17U)
\r
21325 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
\r
21326 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
\r
21327 #define USART_ICR_WUCF_Pos (20U)
\r
21328 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
\r
21329 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
\r
21331 /******************* Bit definition for USART_RDR register ******************/
\r
21332 #define USART_RDR_RDR_Pos (0U)
\r
21333 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
\r
21334 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
\r
21336 /******************* Bit definition for USART_TDR register ******************/
\r
21337 #define USART_TDR_TDR_Pos (0U)
\r
21338 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
\r
21339 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
\r
21341 /******************* Bit definition for USART_PRESC register ******************/
\r
21342 #define USART_PRESC_PRESCALER_Pos (0U)
\r
21343 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
\r
21344 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
\r
21345 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
\r
21346 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
\r
21347 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
\r
21348 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
\r
21350 /******************************************************************************/
\r
21352 /* Single Wire Protocol Master Interface (SWPMI) */
\r
21354 /******************************************************************************/
\r
21356 /******************* Bit definition for SWPMI_CR register ********************/
\r
21357 #define SWPMI_CR_RXDMA_Pos (0U)
\r
21358 #define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
\r
21359 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
\r
21360 #define SWPMI_CR_TXDMA_Pos (1U)
\r
21361 #define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
\r
21362 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
\r
21363 #define SWPMI_CR_RXMODE_Pos (2U)
\r
21364 #define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
\r
21365 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
\r
21366 #define SWPMI_CR_TXMODE_Pos (3U)
\r
21367 #define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
\r
21368 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
\r
21369 #define SWPMI_CR_LPBK_Pos (4U)
\r
21370 #define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
\r
21371 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
\r
21372 #define SWPMI_CR_SWPACT_Pos (5U)
\r
21373 #define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
\r
21374 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
\r
21375 #define SWPMI_CR_DEACT_Pos (10U)
\r
21376 #define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
\r
21377 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
\r
21378 #define SWPMI_CR_SWPEN_Pos (11U)
\r
21379 #define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos) /*!< 0x00000800 */
\r
21380 #define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk /*!<Single wire protocol master transceiver enable */
\r
21382 /******************* Bit definition for SWPMI_BRR register ********************/
\r
21383 #define SWPMI_BRR_BR_Pos (0U)
\r
21384 #define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos) /*!< 0x000000FF */
\r
21385 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[7:0] bits (Bitrate prescaler) */
\r
21387 /******************* Bit definition for SWPMI_ISR register ********************/
\r
21388 #define SWPMI_ISR_RXBFF_Pos (0U)
\r
21389 #define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
\r
21390 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
\r
21391 #define SWPMI_ISR_TXBEF_Pos (1U)
\r
21392 #define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
\r
21393 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
\r
21394 #define SWPMI_ISR_RXBERF_Pos (2U)
\r
21395 #define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
\r
21396 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
\r
21397 #define SWPMI_ISR_RXOVRF_Pos (3U)
\r
21398 #define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
\r
21399 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
\r
21400 #define SWPMI_ISR_TXUNRF_Pos (4U)
\r
21401 #define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
\r
21402 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
\r
21403 #define SWPMI_ISR_RXNE_Pos (5U)
\r
21404 #define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
\r
21405 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
\r
21406 #define SWPMI_ISR_TXE_Pos (6U)
\r
21407 #define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
\r
21408 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
\r
21409 #define SWPMI_ISR_TCF_Pos (7U)
\r
21410 #define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
\r
21411 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
\r
21412 #define SWPMI_ISR_SRF_Pos (8U)
\r
21413 #define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
\r
21414 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
\r
21415 #define SWPMI_ISR_SUSP_Pos (9U)
\r
21416 #define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
\r
21417 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
\r
21418 #define SWPMI_ISR_DEACTF_Pos (10U)
\r
21419 #define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
\r
21420 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
\r
21421 #define SWPMI_ISR_RDYF_Pos (11U)
\r
21422 #define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos) /*!< 0x00000800 */
\r
21423 #define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk /*!<Transceiver ready flag */
\r
21425 /******************* Bit definition for SWPMI_ICR register ********************/
\r
21426 #define SWPMI_ICR_CRXBFF_Pos (0U)
\r
21427 #define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
\r
21428 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
\r
21429 #define SWPMI_ICR_CTXBEF_Pos (1U)
\r
21430 #define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
\r
21431 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
\r
21432 #define SWPMI_ICR_CRXBERF_Pos (2U)
\r
21433 #define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
\r
21434 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
\r
21435 #define SWPMI_ICR_CRXOVRF_Pos (3U)
\r
21436 #define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
\r
21437 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
\r
21438 #define SWPMI_ICR_CTXUNRF_Pos (4U)
\r
21439 #define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
\r
21440 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
\r
21441 #define SWPMI_ICR_CTCF_Pos (7U)
\r
21442 #define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
\r
21443 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
\r
21444 #define SWPMI_ICR_CSRF_Pos (8U)
\r
21445 #define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
\r
21446 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
\r
21447 #define SWPMI_ICR_CRDYF_Pos (11U)
\r
21448 #define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos) /*!< 0x00000800 */
\r
21449 #define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk /*!<Clear transceiver ready flag */
\r
21451 /******************* Bit definition for SWPMI_IER register ********************/
\r
21452 #define SWPMI_IER_RXBFIE_Pos (0U)
\r
21453 #define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
\r
21454 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
\r
21455 #define SWPMI_IER_TXBEIE_Pos (1U)
\r
21456 #define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
\r
21457 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
\r
21458 #define SWPMI_IER_RXBERIE_Pos (2U)
\r
21459 #define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
\r
21460 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
\r
21461 #define SWPMI_IER_RXOVRIE_Pos (3U)
\r
21462 #define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
\r
21463 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
\r
21464 #define SWPMI_IER_TXUNRIE_Pos (4U)
\r
21465 #define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
\r
21466 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
\r
21467 #define SWPMI_IER_RIE_Pos (5U)
\r
21468 #define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
\r
21469 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
\r
21470 #define SWPMI_IER_TIE_Pos (6U)
\r
21471 #define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
\r
21472 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
\r
21473 #define SWPMI_IER_TCIE_Pos (7U)
\r
21474 #define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
\r
21475 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
\r
21476 #define SWPMI_IER_SRIE_Pos (8U)
\r
21477 #define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
\r
21478 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
\r
21479 #define SWPMI_IER_RDYIE_Pos (11U)
\r
21480 #define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos) /*!< 0x00000800 */
\r
21481 #define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk /*!<Transceiver ready interrupt enable */
\r
21483 /******************* Bit definition for SWPMI_RFL register ********************/
\r
21484 #define SWPMI_RFL_RFL_Pos (0U)
\r
21485 #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
\r
21486 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
\r
21487 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
\r
21489 /******************* Bit definition for SWPMI_TDR register ********************/
\r
21490 #define SWPMI_TDR_TD_Pos (0U)
\r
21491 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
\r
21492 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
\r
21494 /******************* Bit definition for SWPMI_RDR register ********************/
\r
21495 #define SWPMI_RDR_RD_Pos (0U)
\r
21496 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
\r
21497 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
\r
21500 /******************* Bit definition for SWPMI_OR register ********************/
\r
21501 #define SWPMI_OR_TBYP_Pos (0U)
\r
21502 #define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
\r
21503 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
\r
21504 #define SWPMI_OR_CLASS_Pos (1U)
\r
21505 #define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
\r
21506 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP CLASS selection */
\r
21508 /******************************************************************************/
\r
21510 /* Window WATCHDOG */
\r
21512 /******************************************************************************/
\r
21513 /******************* Bit definition for WWDG_CR register ********************/
\r
21514 #define WWDG_CR_T_Pos (0U)
\r
21515 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
\r
21516 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
\r
21517 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
\r
21518 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
\r
21519 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
\r
21520 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
\r
21521 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
\r
21522 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
\r
21523 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
\r
21525 #define WWDG_CR_WDGA_Pos (7U)
\r
21526 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
\r
21527 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
\r
21529 /******************* Bit definition for WWDG_CFR register *******************/
\r
21530 #define WWDG_CFR_W_Pos (0U)
\r
21531 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
\r
21532 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
\r
21533 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
\r
21534 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
\r
21535 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
\r
21536 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
\r
21537 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
\r
21538 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
\r
21539 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
\r
21541 #define WWDG_CFR_EWI_Pos (9U)
\r
21542 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
\r
21543 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
\r
21545 #define WWDG_CFR_WDGTB_Pos (11U)
\r
21546 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
\r
21547 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
\r
21548 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
\r
21549 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
\r
21550 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
\r
21552 /******************* Bit definition for WWDG_SR register ********************/
\r
21553 #define WWDG_SR_EWIF_Pos (0U)
\r
21554 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
\r
21555 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
\r
21558 /******************************************************************************/
\r
21562 /******************************************************************************/
\r
21564 /******************** Bit definition for DBGMCU_IDCODE register *************/
\r
21565 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
\r
21566 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
\r
21567 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
\r
21568 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
\r
21569 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
\r
21570 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
\r
21572 /******************** Bit definition for DBGMCU_CR register *****************/
\r
21573 #define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
\r
21574 #define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
\r
21575 #define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
\r
21576 #define DBGMCU_CR_DBG_STOPD1_Pos (1U)
\r
21577 #define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos) /*!< 0x00000002 */
\r
21578 #define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
\r
21579 #define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
\r
21580 #define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
\r
21581 #define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
\r
21582 #define DBGMCU_CR_DBG_SLEEPD2_Pos (3U)
\r
21583 #define DBGMCU_CR_DBG_SLEEPD2_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos) /*!< 0x00000008 */
\r
21584 #define DBGMCU_CR_DBG_SLEEPD2 DBGMCU_CR_DBG_SLEEPD2_Msk
\r
21585 #define DBGMCU_CR_DBG_STOPD2_Pos (4U)
\r
21586 #define DBGMCU_CR_DBG_STOPD2_Msk (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos) /*!< 0x00000010 */
\r
21587 #define DBGMCU_CR_DBG_STOPD2 DBGMCU_CR_DBG_STOPD2_Msk
\r
21588 #define DBGMCU_CR_DBG_STANDBYD2_Pos (5U)
\r
21589 #define DBGMCU_CR_DBG_STANDBYD2_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */
\r
21590 #define DBGMCU_CR_DBG_STANDBYD2 DBGMCU_CR_DBG_STANDBYD2_Msk
\r
21591 #define DBGMCU_CR_DBG_STOPD3_Pos (7U)
\r
21592 #define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
\r
21593 #define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
\r
21594 #define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
\r
21595 #define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
\r
21596 #define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
\r
21597 #define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
\r
21598 #define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
\r
21599 #define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
\r
21600 #define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
\r
21601 #define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos) /*!< 0x00200000 */
\r
21602 #define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
\r
21603 #define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
\r
21604 #define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos) /*!< 0x00400000 */
\r
21605 #define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
\r
21606 #define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
\r
21607 #define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
\r
21608 #define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
\r
21610 /******************** Bit definition for APB3FZ1 register ************/
\r
21611 #define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
\r
21612 #define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
\r
21613 #define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
\r
21614 /******************** Bit definition for APB3FZ2 register ************/
\r
21615 #define DBGMCU_APB3FZ2_DBG_WWDG1_Pos (6U)
\r
21616 #define DBGMCU_APB3FZ2_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos) /*!< 0x00000040 */
\r
21617 #define DBGMCU_APB3FZ2_DBG_WWDG1 DBGMCU_APB3FZ2_DBG_WWDG1_Msk
\r
21618 /******************** Bit definition for APB1LFZ1 register ************/
\r
21619 #define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
\r
21620 #define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
\r
21621 #define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
\r
21622 #define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
\r
21623 #define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
\r
21624 #define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
\r
21625 #define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
\r
21626 #define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
\r
21627 #define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
\r
21628 #define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
\r
21629 #define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
\r
21630 #define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
\r
21631 #define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
\r
21632 #define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
\r
21633 #define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
\r
21634 #define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
\r
21635 #define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
\r
21636 #define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
\r
21637 #define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
\r
21638 #define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
\r
21639 #define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
\r
21640 #define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
\r
21641 #define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
\r
21642 #define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
\r
21643 #define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
\r
21644 #define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
\r
21645 #define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
\r
21646 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
\r
21647 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
\r
21648 #define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
\r
21649 #define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos (11U)
\r
21650 #define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos) /*!< 0x00000800 */
\r
21651 #define DBGMCU_APB1LFZ1_DBG_WWDG2 DBGMCU_APB1LFZ1_DBG_WWDG2_Msk
\r
21652 #define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
\r
21653 #define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
\r
21654 #define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
\r
21655 #define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
\r
21656 #define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
\r
21657 #define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
\r
21658 #define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
\r
21659 #define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
\r
21660 #define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
\r
21662 /******************** Bit definition for APB1LFZ2 register ************/
\r
21663 #define DBGMCU_APB1LFZ2_DBG_TIM2_Pos (0U)
\r
21664 #define DBGMCU_APB1LFZ2_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos) /*!< 0x00000001 */
\r
21665 #define DBGMCU_APB1LFZ2_DBG_TIM2 DBGMCU_APB1LFZ2_DBG_TIM2_Msk
\r
21666 #define DBGMCU_APB1LFZ2_DBG_TIM3_Pos (1U)
\r
21667 #define DBGMCU_APB1LFZ2_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos) /*!< 0x00000002 */
\r
21668 #define DBGMCU_APB1LFZ2_DBG_TIM3 DBGMCU_APB1LFZ2_DBG_TIM3_Msk
\r
21669 #define DBGMCU_APB1LFZ2_DBG_TIM4_Pos (2U)
\r
21670 #define DBGMCU_APB1LFZ2_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos) /*!< 0x00000004 */
\r
21671 #define DBGMCU_APB1LFZ2_DBG_TIM4 DBGMCU_APB1LFZ2_DBG_TIM4_Msk
\r
21672 #define DBGMCU_APB1LFZ2_DBG_TIM5_Pos (3U)
\r
21673 #define DBGMCU_APB1LFZ2_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos) /*!< 0x00000008 */
\r
21674 #define DBGMCU_APB1LFZ2_DBG_TIM5 DBGMCU_APB1LFZ2_DBG_TIM5_Msk
\r
21675 #define DBGMCU_APB1LFZ2_DBG_TIM6_Pos (4U)
\r
21676 #define DBGMCU_APB1LFZ2_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos) /*!< 0x00000010 */
\r
21677 #define DBGMCU_APB1LFZ2_DBG_TIM6 DBGMCU_APB1LFZ2_DBG_TIM6_Msk
\r
21678 #define DBGMCU_APB1LFZ2_DBG_TIM7_Pos (5U)
\r
21679 #define DBGMCU_APB1LFZ2_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos) /*!< 0x00000020 */
\r
21680 #define DBGMCU_APB1LFZ2_DBG_TIM7 DBGMCU_APB1LFZ2_DBG_TIM7_Msk
\r
21681 #define DBGMCU_APB1LFZ2_DBG_TIM12_Pos (6U)
\r
21682 #define DBGMCU_APB1LFZ2_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos) /*!< 0x00000040 */
\r
21683 #define DBGMCU_APB1LFZ2_DBG_TIM12 DBGMCU_APB1LFZ2_DBG_TIM12_Msk
\r
21684 #define DBGMCU_APB1LFZ2_DBG_TIM13_Pos (7U)
\r
21685 #define DBGMCU_APB1LFZ2_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos) /*!< 0x00000080 */
\r
21686 #define DBGMCU_APB1LFZ2_DBG_TIM13 DBGMCU_APB1LFZ2_DBG_TIM13_Msk
\r
21687 #define DBGMCU_APB1LFZ2_DBG_TIM14_Pos (8U)
\r
21688 #define DBGMCU_APB1LFZ2_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos) /*!< 0x00000100 */
\r
21689 #define DBGMCU_APB1LFZ2_DBG_TIM14 DBGMCU_APB1LFZ2_DBG_TIM14_Msk
\r
21690 #define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos (9U)
\r
21691 #define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos) /*!< 0x00000200 */
\r
21692 #define DBGMCU_APB1LFZ2_DBG_LPTIM1 DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk
\r
21693 #define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos (11U)
\r
21694 #define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos) /*!< 0x00000800 */
\r
21695 #define DBGMCU_APB1LFZ2_DBG_WWDG2 DBGMCU_APB1LFZ2_DBG_WWDG2_Msk
\r
21696 #define DBGMCU_APB1LFZ2_DBG_I2C1_Pos (21U)
\r
21697 #define DBGMCU_APB1LFZ2_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos) /*!< 0x00200000 */
\r
21698 #define DBGMCU_APB1LFZ2_DBG_I2C1 DBGMCU_APB1LFZ2_DBG_I2C1_Msk
\r
21699 #define DBGMCU_APB1LFZ2_DBG_I2C2_Pos (22U)
\r
21700 #define DBGMCU_APB1LFZ2_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos) /*!< 0x00400000 */
\r
21701 #define DBGMCU_APB1LFZ2_DBG_I2C2 DBGMCU_APB1LFZ2_DBG_I2C2_Msk
\r
21702 #define DBGMCU_APB1LFZ2_DBG_I2C3_Pos (23U)
\r
21703 #define DBGMCU_APB1LFZ2_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos) /*!< 0x00800000 */
\r
21704 #define DBGMCU_APB1LFZ2_DBG_I2C3 DBGMCU_APB1LFZ2_DBG_I2C3_Msk
\r
21705 /******************** Bit definition for APB1HFZ1 register ************/
\r
21706 #define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U)
\r
21707 #define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
\r
21708 #define DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
\r
21709 /******************** Bit definition for APB1HFZ2 register ************/
\r
21710 #define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos (8U)
\r
21711 #define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos) /*!< 0x00000100 */
\r
21712 #define DBGMCU_APB1HFZ2_DBG_FDCAN DBGMCU_APB1HFZ2_DBG_FDCAN_Msk
\r
21714 /******************** Bit definition for APB2FZ1 register ************/
\r
21715 #define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
\r
21716 #define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
\r
21717 #define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
\r
21718 #define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
\r
21719 #define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
\r
21720 #define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
\r
21721 #define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
\r
21722 #define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
\r
21723 #define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
\r
21724 #define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
\r
21725 #define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
\r
21726 #define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
\r
21727 #define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
\r
21728 #define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
\r
21729 #define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
\r
21730 #define DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U)
\r
21731 #define DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
\r
21732 #define DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk
\r
21734 /******************** Bit definition for APB2FZ2 register ************/
\r
21735 #define DBGMCU_APB2FZ2_DBG_TIM1_Pos (0U)
\r
21736 #define DBGMCU_APB2FZ2_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos) /*!< 0x00000001 */
\r
21737 #define DBGMCU_APB2FZ2_DBG_TIM1 DBGMCU_APB2FZ2_DBG_TIM1_Msk
\r
21738 #define DBGMCU_APB2FZ2_DBG_TIM8_Pos (1U)
\r
21739 #define DBGMCU_APB2FZ2_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos) /*!< 0x00000002 */
\r
21740 #define DBGMCU_APB2FZ2_DBG_TIM8 DBGMCU_APB2FZ2_DBG_TIM8_Msk
\r
21741 #define DBGMCU_APB2FZ2_DBG_TIM15_Pos (16U)
\r
21742 #define DBGMCU_APB2FZ2_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos) /*!< 0x00010000 */
\r
21743 #define DBGMCU_APB2FZ2_DBG_TIM15 DBGMCU_APB2FZ2_DBG_TIM15_Msk
\r
21744 #define DBGMCU_APB2FZ2_DBG_TIM16_Pos (17U)
\r
21745 #define DBGMCU_APB2FZ2_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos) /*!< 0x00020000 */
\r
21746 #define DBGMCU_APB2FZ2_DBG_TIM16 DBGMCU_APB2FZ2_DBG_TIM16_Msk
\r
21747 #define DBGMCU_APB2FZ2_DBG_TIM17_Pos (18U)
\r
21748 #define DBGMCU_APB2FZ2_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos) /*!< 0x00040000 */
\r
21749 #define DBGMCU_APB2FZ2_DBG_TIM17 DBGMCU_APB2FZ2_DBG_TIM17_Msk
\r
21750 #define DBGMCU_APB2FZ2_DBG_HRTIM_Pos (29U)
\r
21751 #define DBGMCU_APB2FZ2_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos) /*!< 0x20000000 */
\r
21752 #define DBGMCU_APB2FZ2_DBG_HRTIM DBGMCU_APB2FZ2_DBG_HRTIM_Msk
\r
21753 /******************** Bit definition for APB4FZ1 register ************/
\r
21754 #define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
\r
21755 #define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
\r
21756 #define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
\r
21757 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
\r
21758 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
\r
21759 #define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
\r
21760 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
\r
21761 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
\r
21762 #define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
\r
21763 #define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
\r
21764 #define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
\r
21765 #define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
\r
21766 #define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
\r
21767 #define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
\r
21768 #define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
\r
21769 #define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
\r
21770 #define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
\r
21771 #define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
\r
21772 #define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
\r
21773 #define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
\r
21774 #define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
\r
21775 #define DBGMCU_APB4FZ1_DBG_IWDG2_Pos (19U)
\r
21776 #define DBGMCU_APB4FZ1_DBG_IWDG2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos) /*!< 0x00080000 */
\r
21777 #define DBGMCU_APB4FZ1_DBG_IWDG2 DBGMCU_APB4FZ1_DBG_IWDG2_Msk
\r
21778 /******************** Bit definition for APB4FZ2 register ************/
\r
21779 #define DBGMCU_APB4FZ2_DBG_I2C4_Pos (7U)
\r
21780 #define DBGMCU_APB4FZ2_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos) /*!< 0x00000080 */
\r
21781 #define DBGMCU_APB4FZ2_DBG_I2C4 DBGMCU_APB4FZ2_DBG_I2C4_Msk
\r
21782 #define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos (9U)
\r
21783 #define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos) /*!< 0x00000200 */
\r
21784 #define DBGMCU_APB4FZ2_DBG_LPTIM2 DBGMCU_APB4FZ2_DBG_LPTIM2_Msk
\r
21785 #define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos (10U)
\r
21786 #define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos) /*!< 0x00000400 */
\r
21787 #define DBGMCU_APB4FZ2_DBG_LPTIM3 DBGMCU_APB4FZ2_DBG_LPTIM3_Msk
\r
21788 #define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos (11U)
\r
21789 #define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos) /*!< 0x00000800 */
\r
21790 #define DBGMCU_APB4FZ2_DBG_LPTIM4 DBGMCU_APB4FZ2_DBG_LPTIM4_Msk
\r
21791 #define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos (12U)
\r
21792 #define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos) /*!< 0x00001000 */
\r
21793 #define DBGMCU_APB4FZ2_DBG_LPTIM5 DBGMCU_APB4FZ2_DBG_LPTIM5_Msk
\r
21794 #define DBGMCU_APB4FZ2_DBG_RTC_Pos (16U)
\r
21795 #define DBGMCU_APB4FZ2_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos) /*!< 0x00010000 */
\r
21796 #define DBGMCU_APB4FZ2_DBG_RTC DBGMCU_APB4FZ2_DBG_RTC_Msk
\r
21797 #define DBGMCU_APB4FZ2_DBG_IWDG1_Pos (18U)
\r
21798 #define DBGMCU_APB4FZ2_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos) /*!< 0x00040000 */
\r
21799 #define DBGMCU_APB4FZ2_DBG_IWDG1 DBGMCU_APB4FZ2_DBG_IWDG1_Msk
\r
21800 #define DBGMCU_APB4FZ2_DBG_IWDG2_Pos (19U)
\r
21801 #define DBGMCU_APB4FZ2_DBG_IWDG2_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos) /*!< 0x00080000 */
\r
21802 #define DBGMCU_APB4FZ2_DBG_IWDG2 DBGMCU_APB4FZ2_DBG_IWDG2_Msk
\r
21803 /******************************************************************************/
\r
21805 /* High Resolution Timer (HRTIM) */
\r
21807 /******************************************************************************/
\r
21808 /******************** Master Timer control register ***************************/
\r
21809 #define HRTIM_MCR_CK_PSC_Pos (0U)
\r
21810 #define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */
\r
21811 #define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */
\r
21812 #define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */
\r
21813 #define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */
\r
21814 #define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */
\r
21816 #define HRTIM_MCR_CONT_Pos (3U)
\r
21817 #define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */
\r
21818 #define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */
\r
21819 #define HRTIM_MCR_RETRIG_Pos (4U)
\r
21820 #define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */
\r
21821 #define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */
\r
21822 #define HRTIM_MCR_HALF_Pos (5U)
\r
21823 #define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */
\r
21824 #define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */
\r
21826 #define HRTIM_MCR_SYNC_IN_Pos (8U)
\r
21827 #define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */
\r
21828 #define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */
\r
21829 #define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */
\r
21830 #define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */
\r
21831 #define HRTIM_MCR_SYNCRSTM_Pos (10U)
\r
21832 #define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */
\r
21833 #define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */
\r
21834 #define HRTIM_MCR_SYNCSTRTM_Pos (11U)
\r
21835 #define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */
\r
21836 #define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */
\r
21837 #define HRTIM_MCR_SYNC_OUT_Pos (12U)
\r
21838 #define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */
\r
21839 #define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */
\r
21840 #define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */
\r
21841 #define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */
\r
21842 #define HRTIM_MCR_SYNC_SRC_Pos (14U)
\r
21843 #define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */
\r
21844 #define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */
\r
21845 #define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */
\r
21846 #define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */
\r
21848 #define HRTIM_MCR_MCEN_Pos (16U)
\r
21849 #define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */
\r
21850 #define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */
\r
21851 #define HRTIM_MCR_TACEN_Pos (17U)
\r
21852 #define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */
\r
21853 #define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */
\r
21854 #define HRTIM_MCR_TBCEN_Pos (18U)
\r
21855 #define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */
\r
21856 #define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */
\r
21857 #define HRTIM_MCR_TCCEN_Pos (19U)
\r
21858 #define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */
\r
21859 #define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */
\r
21860 #define HRTIM_MCR_TDCEN_Pos (20U)
\r
21861 #define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */
\r
21862 #define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */
\r
21863 #define HRTIM_MCR_TECEN_Pos (21U)
\r
21864 #define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */
\r
21865 #define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */
\r
21867 #define HRTIM_MCR_DACSYNC_Pos (25U)
\r
21868 #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
\r
21869 #define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
\r
21870 #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
\r
21871 #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
\r
21873 #define HRTIM_MCR_PREEN_Pos (27U)
\r
21874 #define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */
\r
21875 #define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */
\r
21876 #define HRTIM_MCR_MREPU_Pos (29U)
\r
21877 #define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */
\r
21878 #define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */
\r
21880 #define HRTIM_MCR_BRSTDMA_Pos (30U)
\r
21881 #define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */
\r
21882 #define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */
\r
21883 #define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */
\r
21884 #define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */
\r
21886 /******************** Master Timer Interrupt status register ******************/
\r
21887 #define HRTIM_MISR_MCMP1_Pos (0U)
\r
21888 #define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */
\r
21889 #define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */
\r
21890 #define HRTIM_MISR_MCMP2_Pos (1U)
\r
21891 #define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */
\r
21892 #define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */
\r
21893 #define HRTIM_MISR_MCMP3_Pos (2U)
\r
21894 #define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */
\r
21895 #define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */
\r
21896 #define HRTIM_MISR_MCMP4_Pos (3U)
\r
21897 #define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */
\r
21898 #define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */
\r
21899 #define HRTIM_MISR_MREP_Pos (4U)
\r
21900 #define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */
\r
21901 #define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */
\r
21902 #define HRTIM_MISR_SYNC_Pos (5U)
\r
21903 #define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */
\r
21904 #define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */
\r
21905 #define HRTIM_MISR_MUPD_Pos (6U)
\r
21906 #define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */
\r
21907 #define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */
\r
21909 /******************** Master Timer Interrupt clear register *******************/
\r
21910 #define HRTIM_MICR_MCMP1_Pos (0U)
\r
21911 #define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */
\r
21912 #define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */
\r
21913 #define HRTIM_MICR_MCMP2_Pos (1U)
\r
21914 #define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */
\r
21915 #define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */
\r
21916 #define HRTIM_MICR_MCMP3_Pos (2U)
\r
21917 #define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */
\r
21918 #define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */
\r
21919 #define HRTIM_MICR_MCMP4_Pos (3U)
\r
21920 #define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */
\r
21921 #define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */
\r
21922 #define HRTIM_MICR_MREP_Pos (4U)
\r
21923 #define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */
\r
21924 #define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */
\r
21925 #define HRTIM_MICR_SYNC_Pos (5U)
\r
21926 #define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */
\r
21927 #define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */
\r
21928 #define HRTIM_MICR_MUPD_Pos (6U)
\r
21929 #define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */
\r
21930 #define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */
\r
21932 /******************** Master Timer DMA/Interrupt enable register **************/
\r
21933 #define HRTIM_MDIER_MCMP1IE_Pos (0U)
\r
21934 #define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */
\r
21935 #define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */
\r
21936 #define HRTIM_MDIER_MCMP2IE_Pos (1U)
\r
21937 #define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */
\r
21938 #define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */
\r
21939 #define HRTIM_MDIER_MCMP3IE_Pos (2U)
\r
21940 #define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */
\r
21941 #define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */
\r
21942 #define HRTIM_MDIER_MCMP4IE_Pos (3U)
\r
21943 #define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */
\r
21944 #define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */
\r
21945 #define HRTIM_MDIER_MREPIE_Pos (4U)
\r
21946 #define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */
\r
21947 #define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */
\r
21948 #define HRTIM_MDIER_SYNCIE_Pos (5U)
\r
21949 #define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */
\r
21950 #define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */
\r
21951 #define HRTIM_MDIER_MUPDIE_Pos (6U)
\r
21952 #define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */
\r
21953 #define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */
\r
21955 #define HRTIM_MDIER_MCMP1DE_Pos (16U)
\r
21956 #define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */
\r
21957 #define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */
\r
21958 #define HRTIM_MDIER_MCMP2DE_Pos (17U)
\r
21959 #define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */
\r
21960 #define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */
\r
21961 #define HRTIM_MDIER_MCMP3DE_Pos (18U)
\r
21962 #define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */
\r
21963 #define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */
\r
21964 #define HRTIM_MDIER_MCMP4DE_Pos (19U)
\r
21965 #define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */
\r
21966 #define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */
\r
21967 #define HRTIM_MDIER_MREPDE_Pos (20U)
\r
21968 #define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */
\r
21969 #define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */
\r
21970 #define HRTIM_MDIER_SYNCDE_Pos (21U)
\r
21971 #define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */
\r
21972 #define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */
\r
21973 #define HRTIM_MDIER_MUPDDE_Pos (22U)
\r
21974 #define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */
\r
21975 #define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */
\r
21977 /******************* Bit definition for HRTIM_MCNTR register ****************/
\r
21978 #define HRTIM_MCNTR_MCNTR_Pos (0U)
\r
21979 #define HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos) /*!< 0x0000FFFF */
\r
21980 #define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */
\r
21982 /******************* Bit definition for HRTIM_MPER register *****************/
\r
21983 #define HRTIM_MPER_MPER_Pos (0U)
\r
21984 #define HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos) /*!< 0x0000FFFF */
\r
21985 #define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */
\r
21987 /******************* Bit definition for HRTIM_MREP register *****************/
\r
21988 #define HRTIM_MREP_MREP_Pos (0U)
\r
21989 #define HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos) /*!< 0x000000FF */
\r
21990 #define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */
\r
21992 /******************* Bit definition for HRTIM_MCMP1R register *****************/
\r
21993 #define HRTIM_MCMP1R_MCMP1R_Pos (0U)
\r
21994 #define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos) /*!< 0x0000FFFF */
\r
21995 #define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */
\r
21997 /******************* Bit definition for HRTIM_MCMP2R register *****************/
\r
21998 #define HRTIM_MCMP1R_MCMP2R_Pos (0U)
\r
21999 #define HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos) /*!< 0x0000FFFF */
\r
22000 #define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk /*!<Compare Value */
\r
22002 /******************* Bit definition for HRTIM_MCMP3R register *****************/
\r
22003 #define HRTIM_MCMP1R_MCMP3R_Pos (0U)
\r
22004 #define HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos) /*!< 0x0000FFFF */
\r
22005 #define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk /*!<Compare Value */
\r
22007 /******************* Bit definition for HRTIM_MCMP4R register *****************/
\r
22008 #define HRTIM_MCMP1R_MCMP4R_Pos (0U)
\r
22009 #define HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos) /*!< 0x0000FFFF */
\r
22010 #define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk /*!<Compare Value */
\r
22012 /******************** Slave control register **********************************/
\r
22013 #define HRTIM_TIMCR_CK_PSC_Pos (0U)
\r
22014 #define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */
\r
22015 #define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/
\r
22016 #define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */
\r
22017 #define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */
\r
22018 #define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */
\r
22020 #define HRTIM_TIMCR_CONT_Pos (3U)
\r
22021 #define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */
\r
22022 #define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */
\r
22023 #define HRTIM_TIMCR_RETRIG_Pos (4U)
\r
22024 #define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */
\r
22025 #define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */
\r
22026 #define HRTIM_TIMCR_HALF_Pos (5U)
\r
22027 #define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */
\r
22028 #define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */
\r
22029 #define HRTIM_TIMCR_PSHPLL_Pos (6U)
\r
22030 #define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */
\r
22031 #define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */
\r
22033 #define HRTIM_TIMCR_SYNCRST_Pos (10U)
\r
22034 #define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */
\r
22035 #define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */
\r
22036 #define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
\r
22037 #define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */
\r
22038 #define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */
\r
22040 #define HRTIM_TIMCR_DELCMP2_Pos (12U)
\r
22041 #define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */
\r
22042 #define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */
\r
22043 #define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */
\r
22044 #define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */
\r
22045 #define HRTIM_TIMCR_DELCMP4_Pos (14U)
\r
22046 #define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */
\r
22047 #define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */
\r
22048 #define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */
\r
22049 #define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */
\r
22051 #define HRTIM_TIMCR_TREPU_Pos (17U)
\r
22052 #define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */
\r
22053 #define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */
\r
22054 #define HRTIM_TIMCR_TRSTU_Pos (18U)
\r
22055 #define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */
\r
22056 #define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */
\r
22057 #define HRTIM_TIMCR_TAU_Pos (19U)
\r
22058 #define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */
\r
22059 #define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */
\r
22060 #define HRTIM_TIMCR_TBU_Pos (20U)
\r
22061 #define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */
\r
22062 #define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */
\r
22063 #define HRTIM_TIMCR_TCU_Pos (21U)
\r
22064 #define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */
\r
22065 #define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */
\r
22066 #define HRTIM_TIMCR_TDU_Pos (22U)
\r
22067 #define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */
\r
22068 #define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */
\r
22069 #define HRTIM_TIMCR_TEU_Pos (23U)
\r
22070 #define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */
\r
22071 #define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */
\r
22072 #define HRTIM_TIMCR_MSTU_Pos (24U)
\r
22073 #define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos) /*!< 0x01000000 */
\r
22074 #define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */
\r
22076 #define HRTIM_TIMCR_DACSYNC_Pos (25U)
\r
22077 #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
\r
22078 #define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
\r
22079 #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
\r
22080 #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
\r
22081 #define HRTIM_TIMCR_PREEN_Pos (27U)
\r
22082 #define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */
\r
22083 #define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */
\r
22085 #define HRTIM_TIMCR_UPDGAT_Pos (28U)
\r
22086 #define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */
\r
22087 #define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */
\r
22088 #define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */
\r
22089 #define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */
\r
22090 #define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */
\r
22091 #define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */
\r
22093 /******************** Slave Interrupt status register **************************/
\r
22094 #define HRTIM_TIMISR_CMP1_Pos (0U)
\r
22095 #define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */
\r
22096 #define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */
\r
22097 #define HRTIM_TIMISR_CMP2_Pos (1U)
\r
22098 #define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */
\r
22099 #define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */
\r
22100 #define HRTIM_TIMISR_CMP3_Pos (2U)
\r
22101 #define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */
\r
22102 #define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */
\r
22103 #define HRTIM_TIMISR_CMP4_Pos (3U)
\r
22104 #define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */
\r
22105 #define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */
\r
22106 #define HRTIM_TIMISR_REP_Pos (4U)
\r
22107 #define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */
\r
22108 #define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */
\r
22109 #define HRTIM_TIMISR_UPD_Pos (6U)
\r
22110 #define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */
\r
22111 #define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */
\r
22112 #define HRTIM_TIMISR_CPT1_Pos (7U)
\r
22113 #define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */
\r
22114 #define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */
\r
22115 #define HRTIM_TIMISR_CPT2_Pos (8U)
\r
22116 #define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */
\r
22117 #define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */
\r
22118 #define HRTIM_TIMISR_SET1_Pos (9U)
\r
22119 #define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */
\r
22120 #define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */
\r
22121 #define HRTIM_TIMISR_RST1_Pos (10U)
\r
22122 #define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */
\r
22123 #define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */
\r
22124 #define HRTIM_TIMISR_SET2_Pos (11U)
\r
22125 #define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */
\r
22126 #define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */
\r
22127 #define HRTIM_TIMISR_RST2_Pos (12U)
\r
22128 #define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */
\r
22129 #define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */
\r
22130 #define HRTIM_TIMISR_RST_Pos (13U)
\r
22131 #define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */
\r
22132 #define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */
\r
22133 #define HRTIM_TIMISR_DLYPRT_Pos (14U)
\r
22134 #define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */
\r
22135 #define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */
\r
22136 #define HRTIM_TIMISR_CPPSTAT_Pos (16U)
\r
22137 #define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */
\r
22138 #define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
\r
22139 #define HRTIM_TIMISR_IPPSTAT_Pos (17U)
\r
22140 #define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */
\r
22141 #define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
\r
22142 #define HRTIM_TIMISR_O1STAT_Pos (18U)
\r
22143 #define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */
\r
22144 #define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */
\r
22145 #define HRTIM_TIMISR_O2STAT_Pos (19U)
\r
22146 #define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */
\r
22147 #define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */
\r
22148 #define HRTIM_TIMISR_O1CPY_Pos (20U)
\r
22149 #define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */
\r
22150 #define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */
\r
22151 #define HRTIM_TIMISR_O2CPY_Pos (21U)
\r
22152 #define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */
\r
22153 #define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */
\r
22155 /******************** Slave Interrupt clear register **************************/
\r
22156 #define HRTIM_TIMICR_CMP1C_Pos (0U)
\r
22157 #define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */
\r
22158 #define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */
\r
22159 #define HRTIM_TIMICR_CMP2C_Pos (1U)
\r
22160 #define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */
\r
22161 #define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */
\r
22162 #define HRTIM_TIMICR_CMP3C_Pos (2U)
\r
22163 #define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */
\r
22164 #define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */
\r
22165 #define HRTIM_TIMICR_CMP4C_Pos (3U)
\r
22166 #define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */
\r
22167 #define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */
\r
22168 #define HRTIM_TIMICR_REPC_Pos (4U)
\r
22169 #define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */
\r
22170 #define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */
\r
22171 #define HRTIM_TIMICR_UPDC_Pos (6U)
\r
22172 #define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */
\r
22173 #define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */
\r
22174 #define HRTIM_TIMICR_CPT1C_Pos (7U)
\r
22175 #define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */
\r
22176 #define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */
\r
22177 #define HRTIM_TIMICR_CPT2C_Pos (8U)
\r
22178 #define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */
\r
22179 #define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */
\r
22180 #define HRTIM_TIMICR_SET1C_Pos (9U)
\r
22181 #define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */
\r
22182 #define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */
\r
22183 #define HRTIM_TIMICR_RST1C_Pos (10U)
\r
22184 #define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */
\r
22185 #define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */
\r
22186 #define HRTIM_TIMICR_SET2C_Pos (11U)
\r
22187 #define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */
\r
22188 #define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */
\r
22189 #define HRTIM_TIMICR_RST2C_Pos (12U)
\r
22190 #define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */
\r
22191 #define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */
\r
22192 #define HRTIM_TIMICR_RSTC_Pos (13U)
\r
22193 #define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */
\r
22194 #define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */
\r
22195 #define HRTIM_TIMICR_DLYPRTC_Pos (14U)
\r
22196 #define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos) /*!< 0x00004000 */
\r
22197 #define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk /*!< Slave output 1 delay protection clear flag */
\r
22199 /******************** Slave DMA/Interrupt enable register *********************/
\r
22200 #define HRTIM_TIMDIER_CMP1IE_Pos (0U)
\r
22201 #define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */
\r
22202 #define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */
\r
22203 #define HRTIM_TIMDIER_CMP2IE_Pos (1U)
\r
22204 #define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */
\r
22205 #define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */
\r
22206 #define HRTIM_TIMDIER_CMP3IE_Pos (2U)
\r
22207 #define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */
\r
22208 #define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */
\r
22209 #define HRTIM_TIMDIER_CMP4IE_Pos (3U)
\r
22210 #define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */
\r
22211 #define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */
\r
22212 #define HRTIM_TIMDIER_REPIE_Pos (4U)
\r
22213 #define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */
\r
22214 #define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */
\r
22215 #define HRTIM_TIMDIER_UPDIE_Pos (6U)
\r
22216 #define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */
\r
22217 #define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */
\r
22218 #define HRTIM_TIMDIER_CPT1IE_Pos (7U)
\r
22219 #define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */
\r
22220 #define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */
\r
22221 #define HRTIM_TIMDIER_CPT2IE_Pos (8U)
\r
22222 #define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */
\r
22223 #define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */
\r
22224 #define HRTIM_TIMDIER_SET1IE_Pos (9U)
\r
22225 #define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */
\r
22226 #define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */
\r
22227 #define HRTIM_TIMDIER_RST1IE_Pos (10U)
\r
22228 #define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */
\r
22229 #define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */
\r
22230 #define HRTIM_TIMDIER_SET2IE_Pos (11U)
\r
22231 #define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */
\r
22232 #define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */
\r
22233 #define HRTIM_TIMDIER_RST2IE_Pos (12U)
\r
22234 #define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */
\r
22235 #define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */
\r
22236 #define HRTIM_TIMDIER_RSTIE_Pos (13U)
\r
22237 #define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */
\r
22238 #define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */
\r
22239 #define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
\r
22240 #define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */
\r
22241 #define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */
\r
22243 #define HRTIM_TIMDIER_CMP1DE_Pos (16U)
\r
22244 #define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */
\r
22245 #define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */
\r
22246 #define HRTIM_TIMDIER_CMP2DE_Pos (17U)
\r
22247 #define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */
\r
22248 #define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */
\r
22249 #define HRTIM_TIMDIER_CMP3DE_Pos (18U)
\r
22250 #define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */
\r
22251 #define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */
\r
22252 #define HRTIM_TIMDIER_CMP4DE_Pos (19U)
\r
22253 #define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */
\r
22254 #define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */
\r
22255 #define HRTIM_TIMDIER_REPDE_Pos (20U)
\r
22256 #define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */
\r
22257 #define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */
\r
22258 #define HRTIM_TIMDIER_UPDDE_Pos (22U)
\r
22259 #define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */
\r
22260 #define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */
\r
22261 #define HRTIM_TIMDIER_CPT1DE_Pos (23U)
\r
22262 #define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */
\r
22263 #define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */
\r
22264 #define HRTIM_TIMDIER_CPT2DE_Pos (24U)
\r
22265 #define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */
\r
22266 #define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */
\r
22267 #define HRTIM_TIMDIER_SET1DE_Pos (25U)
\r
22268 #define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */
\r
22269 #define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */
\r
22270 #define HRTIM_TIMDIER_RST1DE_Pos (26U)
\r
22271 #define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */
\r
22272 #define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */
\r
22273 #define HRTIM_TIMDIER_SET2DE_Pos (27U)
\r
22274 #define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */
\r
22275 #define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */
\r
22276 #define HRTIM_TIMDIER_RST2DE_Pos (28U)
\r
22277 #define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */
\r
22278 #define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */
\r
22279 #define HRTIM_TIMDIER_RSTDE_Pos (29U)
\r
22280 #define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */
\r
22281 #define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */
\r
22282 #define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
\r
22283 #define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */
\r
22284 #define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */
\r
22286 /****************** Bit definition for HRTIM_CNTR register ****************/
\r
22287 #define HRTIM_CNTR_CNTR_Pos (0U)
\r
22288 #define HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos) /*!< 0x0000FFFF */
\r
22289 #define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */
\r
22291 /******************* Bit definition for HRTIM_PER register *****************/
\r
22292 #define HRTIM_PER_PER_Pos (0U)
\r
22293 #define HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos) /*!< 0x0000FFFF */
\r
22294 #define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */
\r
22296 /******************* Bit definition for HRTIM_REP register *****************/
\r
22297 #define HRTIM_REP_REP_Pos (0U)
\r
22298 #define HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos) /*!< 0x000000FF */
\r
22299 #define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */
\r
22301 /******************* Bit definition for HRTIM_CMP1R register *****************/
\r
22302 #define HRTIM_CMP1R_CMP1R_Pos (0U)
\r
22303 #define HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos) /*!< 0x0000FFFF */
\r
22304 #define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */
\r
22306 /******************* Bit definition for HRTIM_CMP1CR register *****************/
\r
22307 #define HRTIM_CMP1CR_CMP1CR_Pos (0U)
\r
22308 #define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
\r
22309 #define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */
\r
22311 /******************* Bit definition for HRTIM_CMP2R register *****************/
\r
22312 #define HRTIM_CMP2R_CMP2R_Pos (0U)
\r
22313 #define HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos) /*!< 0x0000FFFF */
\r
22314 #define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */
\r
22316 /******************* Bit definition for HRTIM_CMP3R register *****************/
\r
22317 #define HRTIM_CMP3R_CMP3R_Pos (0U)
\r
22318 #define HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos) /*!< 0x0000FFFF */
\r
22319 #define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */
\r
22321 /******************* Bit definition for HRTIM_CMP4R register *****************/
\r
22322 #define HRTIM_CMP4R_CMP4R_Pos (0U)
\r
22323 #define HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos) /*!< 0x0000FFFF */
\r
22324 #define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */
\r
22326 /******************* Bit definition for HRTIM_CPT1R register ****************/
\r
22327 #define HRTIM_CPT1R_CPT1R_Pos (0U)
\r
22328 #define HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos) /*!< 0x0000FFFF */
\r
22329 #define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture Value */
\r
22331 /******************* Bit definition for HRTIM_CPT2R register ****************/
\r
22332 #define HRTIM_CPT2R_CPT2R_Pos (0U)
\r
22333 #define HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */
\r
22334 #define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture Value */
\r
22336 /******************** Bit definition for Slave Deadtime register **************/
\r
22337 #define HRTIM_DTR_DTR_Pos (0U)
\r
22338 #define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */
\r
22339 #define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */
\r
22340 #define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */
\r
22341 #define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */
\r
22342 #define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */
\r
22343 #define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */
\r
22344 #define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */
\r
22345 #define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */
\r
22346 #define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */
\r
22347 #define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */
\r
22348 #define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */
\r
22349 #define HRTIM_DTR_SDTR_Pos (9U)
\r
22350 #define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */
\r
22351 #define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */
\r
22352 #define HRTIM_DTR_DTPRSC_Pos (10U)
\r
22353 #define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */
\r
22354 #define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */
\r
22355 #define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */
\r
22356 #define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */
\r
22357 #define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */
\r
22358 #define HRTIM_DTR_DTRSLK_Pos (14U)
\r
22359 #define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */
\r
22360 #define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */
\r
22361 #define HRTIM_DTR_DTRLK_Pos (15U)
\r
22362 #define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */
\r
22363 #define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */
\r
22364 #define HRTIM_DTR_DTF_Pos (16U)
\r
22365 #define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */
\r
22366 #define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */
\r
22367 #define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */
\r
22368 #define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */
\r
22369 #define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */
\r
22370 #define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */
\r
22371 #define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */
\r
22372 #define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */
\r
22373 #define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */
\r
22374 #define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */
\r
22375 #define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */
\r
22376 #define HRTIM_DTR_SDTF_Pos (25U)
\r
22377 #define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */
\r
22378 #define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */
\r
22379 #define HRTIM_DTR_DTFSLK_Pos (30U)
\r
22380 #define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */
\r
22381 #define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */
\r
22382 #define HRTIM_DTR_DTFLK_Pos (31U)
\r
22383 #define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */
\r
22384 #define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */
\r
22386 /**** Bit definition for Slave Output 1 set register **************************/
\r
22387 #define HRTIM_SET1R_SST_Pos (0U)
\r
22388 #define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */
\r
22389 #define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */
\r
22390 #define HRTIM_SET1R_RESYNC_Pos (1U)
\r
22391 #define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */
\r
22392 #define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */
\r
22393 #define HRTIM_SET1R_PER_Pos (2U)
\r
22394 #define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */
\r
22395 #define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */
\r
22396 #define HRTIM_SET1R_CMP1_Pos (3U)
\r
22397 #define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */
\r
22398 #define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */
\r
22399 #define HRTIM_SET1R_CMP2_Pos (4U)
\r
22400 #define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */
\r
22401 #define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */
\r
22402 #define HRTIM_SET1R_CMP3_Pos (5U)
\r
22403 #define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */
\r
22404 #define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */
\r
22405 #define HRTIM_SET1R_CMP4_Pos (6U)
\r
22406 #define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */
\r
22407 #define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */
\r
22409 #define HRTIM_SET1R_MSTPER_Pos (7U)
\r
22410 #define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */
\r
22411 #define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */
\r
22412 #define HRTIM_SET1R_MSTCMP1_Pos (8U)
\r
22413 #define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */
\r
22414 #define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */
\r
22415 #define HRTIM_SET1R_MSTCMP2_Pos (9U)
\r
22416 #define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */
\r
22417 #define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */
\r
22418 #define HRTIM_SET1R_MSTCMP3_Pos (10U)
\r
22419 #define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */
\r
22420 #define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */
\r
22421 #define HRTIM_SET1R_MSTCMP4_Pos (11U)
\r
22422 #define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */
\r
22423 #define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */
\r
22425 #define HRTIM_SET1R_TIMEVNT1_Pos (12U)
\r
22426 #define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */
\r
22427 #define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */
\r
22428 #define HRTIM_SET1R_TIMEVNT2_Pos (13U)
\r
22429 #define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */
\r
22430 #define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */
\r
22431 #define HRTIM_SET1R_TIMEVNT3_Pos (14U)
\r
22432 #define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */
\r
22433 #define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */
\r
22434 #define HRTIM_SET1R_TIMEVNT4_Pos (15U)
\r
22435 #define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */
\r
22436 #define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */
\r
22437 #define HRTIM_SET1R_TIMEVNT5_Pos (16U)
\r
22438 #define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */
\r
22439 #define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */
\r
22440 #define HRTIM_SET1R_TIMEVNT6_Pos (17U)
\r
22441 #define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */
\r
22442 #define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */
\r
22443 #define HRTIM_SET1R_TIMEVNT7_Pos (18U)
\r
22444 #define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */
\r
22445 #define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */
\r
22446 #define HRTIM_SET1R_TIMEVNT8_Pos (19U)
\r
22447 #define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */
\r
22448 #define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */
\r
22449 #define HRTIM_SET1R_TIMEVNT9_Pos (20U)
\r
22450 #define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */
\r
22451 #define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */
\r
22453 #define HRTIM_SET1R_EXTVNT1_Pos (21U)
\r
22454 #define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */
\r
22455 #define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */
\r
22456 #define HRTIM_SET1R_EXTVNT2_Pos (22U)
\r
22457 #define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */
\r
22458 #define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */
\r
22459 #define HRTIM_SET1R_EXTVNT3_Pos (23U)
\r
22460 #define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */
\r
22461 #define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */
\r
22462 #define HRTIM_SET1R_EXTVNT4_Pos (24U)
\r
22463 #define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */
\r
22464 #define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */
\r
22465 #define HRTIM_SET1R_EXTVNT5_Pos (25U)
\r
22466 #define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */
\r
22467 #define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */
\r
22468 #define HRTIM_SET1R_EXTVNT6_Pos (26U)
\r
22469 #define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */
\r
22470 #define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */
\r
22471 #define HRTIM_SET1R_EXTVNT7_Pos (27U)
\r
22472 #define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */
\r
22473 #define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */
\r
22474 #define HRTIM_SET1R_EXTVNT8_Pos (28U)
\r
22475 #define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */
\r
22476 #define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */
\r
22477 #define HRTIM_SET1R_EXTVNT9_Pos (29U)
\r
22478 #define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */
\r
22479 #define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */
\r
22480 #define HRTIM_SET1R_EXTVNT10_Pos (30U)
\r
22481 #define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */
\r
22482 #define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */
\r
22484 #define HRTIM_SET1R_UPDATE_Pos (31U)
\r
22485 #define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */
\r
22486 #define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
\r
22488 /**** Bit definition for Slave Output 1 reset register ************************/
\r
22489 #define HRTIM_RST1R_SRT_Pos (0U)
\r
22490 #define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */
\r
22491 #define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */
\r
22492 #define HRTIM_RST1R_RESYNC_Pos (1U)
\r
22493 #define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */
\r
22494 #define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */
\r
22495 #define HRTIM_RST1R_PER_Pos (2U)
\r
22496 #define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */
\r
22497 #define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */
\r
22498 #define HRTIM_RST1R_CMP1_Pos (3U)
\r
22499 #define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */
\r
22500 #define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */
\r
22501 #define HRTIM_RST1R_CMP2_Pos (4U)
\r
22502 #define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */
\r
22503 #define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */
\r
22504 #define HRTIM_RST1R_CMP3_Pos (5U)
\r
22505 #define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */
\r
22506 #define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */
\r
22507 #define HRTIM_RST1R_CMP4_Pos (6U)
\r
22508 #define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */
\r
22509 #define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */
\r
22511 #define HRTIM_RST1R_MSTPER_Pos (7U)
\r
22512 #define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */
\r
22513 #define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */
\r
22514 #define HRTIM_RST1R_MSTCMP1_Pos (8U)
\r
22515 #define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */
\r
22516 #define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */
\r
22517 #define HRTIM_RST1R_MSTCMP2_Pos (9U)
\r
22518 #define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */
\r
22519 #define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */
\r
22520 #define HRTIM_RST1R_MSTCMP3_Pos (10U)
\r
22521 #define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */
\r
22522 #define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */
\r
22523 #define HRTIM_RST1R_MSTCMP4_Pos (11U)
\r
22524 #define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */
\r
22525 #define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */
\r
22527 #define HRTIM_RST1R_TIMEVNT1_Pos (12U)
\r
22528 #define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */
\r
22529 #define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */
\r
22530 #define HRTIM_RST1R_TIMEVNT2_Pos (13U)
\r
22531 #define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */
\r
22532 #define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */
\r
22533 #define HRTIM_RST1R_TIMEVNT3_Pos (14U)
\r
22534 #define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */
\r
22535 #define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */
\r
22536 #define HRTIM_RST1R_TIMEVNT4_Pos (15U)
\r
22537 #define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */
\r
22538 #define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */
\r
22539 #define HRTIM_RST1R_TIMEVNT5_Pos (16U)
\r
22540 #define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */
\r
22541 #define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */
\r
22542 #define HRTIM_RST1R_TIMEVNT6_Pos (17U)
\r
22543 #define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */
\r
22544 #define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */
\r
22545 #define HRTIM_RST1R_TIMEVNT7_Pos (18U)
\r
22546 #define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */
\r
22547 #define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */
\r
22548 #define HRTIM_RST1R_TIMEVNT8_Pos (19U)
\r
22549 #define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */
\r
22550 #define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */
\r
22551 #define HRTIM_RST1R_TIMEVNT9_Pos (20U)
\r
22552 #define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */
\r
22553 #define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */
\r
22555 #define HRTIM_RST1R_EXTVNT1_Pos (21U)
\r
22556 #define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */
\r
22557 #define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */
\r
22558 #define HRTIM_RST1R_EXTVNT2_Pos (22U)
\r
22559 #define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */
\r
22560 #define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */
\r
22561 #define HRTIM_RST1R_EXTVNT3_Pos (23U)
\r
22562 #define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */
\r
22563 #define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */
\r
22564 #define HRTIM_RST1R_EXTVNT4_Pos (24U)
\r
22565 #define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */
\r
22566 #define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */
\r
22567 #define HRTIM_RST1R_EXTVNT5_Pos (25U)
\r
22568 #define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */
\r
22569 #define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */
\r
22570 #define HRTIM_RST1R_EXTVNT6_Pos (26U)
\r
22571 #define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */
\r
22572 #define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */
\r
22573 #define HRTIM_RST1R_EXTVNT7_Pos (27U)
\r
22574 #define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */
\r
22575 #define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */
\r
22576 #define HRTIM_RST1R_EXTVNT8_Pos (28U)
\r
22577 #define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */
\r
22578 #define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */
\r
22579 #define HRTIM_RST1R_EXTVNT9_Pos (29U)
\r
22580 #define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */
\r
22581 #define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */
\r
22582 #define HRTIM_RST1R_EXTVNT10_Pos (30U)
\r
22583 #define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */
\r
22584 #define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */
\r
22586 #define HRTIM_RST1R_UPDATE_Pos (31U)
\r
22587 #define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */
\r
22588 #define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
\r
22591 /**** Bit definition for Slave Output 2 set register **************************/
\r
22592 #define HRTIM_SET2R_SST_Pos (0U)
\r
22593 #define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */
\r
22594 #define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */
\r
22595 #define HRTIM_SET2R_RESYNC_Pos (1U)
\r
22596 #define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */
\r
22597 #define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */
\r
22598 #define HRTIM_SET2R_PER_Pos (2U)
\r
22599 #define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */
\r
22600 #define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */
\r
22601 #define HRTIM_SET2R_CMP1_Pos (3U)
\r
22602 #define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */
\r
22603 #define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */
\r
22604 #define HRTIM_SET2R_CMP2_Pos (4U)
\r
22605 #define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */
\r
22606 #define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */
\r
22607 #define HRTIM_SET2R_CMP3_Pos (5U)
\r
22608 #define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */
\r
22609 #define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */
\r
22610 #define HRTIM_SET2R_CMP4_Pos (6U)
\r
22611 #define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */
\r
22612 #define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */
\r
22614 #define HRTIM_SET2R_MSTPER_Pos (7U)
\r
22615 #define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */
\r
22616 #define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */
\r
22617 #define HRTIM_SET2R_MSTCMP1_Pos (8U)
\r
22618 #define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */
\r
22619 #define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */
\r
22620 #define HRTIM_SET2R_MSTCMP2_Pos (9U)
\r
22621 #define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */
\r
22622 #define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */
\r
22623 #define HRTIM_SET2R_MSTCMP3_Pos (10U)
\r
22624 #define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */
\r
22625 #define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */
\r
22626 #define HRTIM_SET2R_MSTCMP4_Pos (11U)
\r
22627 #define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */
\r
22628 #define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */
\r
22630 #define HRTIM_SET2R_TIMEVNT1_Pos (12U)
\r
22631 #define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */
\r
22632 #define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */
\r
22633 #define HRTIM_SET2R_TIMEVNT2_Pos (13U)
\r
22634 #define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */
\r
22635 #define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */
\r
22636 #define HRTIM_SET2R_TIMEVNT3_Pos (14U)
\r
22637 #define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */
\r
22638 #define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */
\r
22639 #define HRTIM_SET2R_TIMEVNT4_Pos (15U)
\r
22640 #define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */
\r
22641 #define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */
\r
22642 #define HRTIM_SET2R_TIMEVNT5_Pos (16U)
\r
22643 #define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */
\r
22644 #define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */
\r
22645 #define HRTIM_SET2R_TIMEVNT6_Pos (17U)
\r
22646 #define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */
\r
22647 #define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */
\r
22648 #define HRTIM_SET2R_TIMEVNT7_Pos (18U)
\r
22649 #define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */
\r
22650 #define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */
\r
22651 #define HRTIM_SET2R_TIMEVNT8_Pos (19U)
\r
22652 #define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */
\r
22653 #define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */
\r
22654 #define HRTIM_SET2R_TIMEVNT9_Pos (20U)
\r
22655 #define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */
\r
22656 #define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */
\r
22658 #define HRTIM_SET2R_EXTVNT1_Pos (21U)
\r
22659 #define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */
\r
22660 #define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */
\r
22661 #define HRTIM_SET2R_EXTVNT2_Pos (22U)
\r
22662 #define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */
\r
22663 #define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */
\r
22664 #define HRTIM_SET2R_EXTVNT3_Pos (23U)
\r
22665 #define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */
\r
22666 #define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */
\r
22667 #define HRTIM_SET2R_EXTVNT4_Pos (24U)
\r
22668 #define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */
\r
22669 #define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */
\r
22670 #define HRTIM_SET2R_EXTVNT5_Pos (25U)
\r
22671 #define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */
\r
22672 #define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */
\r
22673 #define HRTIM_SET2R_EXTVNT6_Pos (26U)
\r
22674 #define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */
\r
22675 #define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */
\r
22676 #define HRTIM_SET2R_EXTVNT7_Pos (27U)
\r
22677 #define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */
\r
22678 #define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */
\r
22679 #define HRTIM_SET2R_EXTVNT8_Pos (28U)
\r
22680 #define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */
\r
22681 #define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */
\r
22682 #define HRTIM_SET2R_EXTVNT9_Pos (29U)
\r
22683 #define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */
\r
22684 #define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */
\r
22685 #define HRTIM_SET2R_EXTVNT10_Pos (30U)
\r
22686 #define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */
\r
22687 #define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */
\r
22689 #define HRTIM_SET2R_UPDATE_Pos (31U)
\r
22690 #define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */
\r
22691 #define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
\r
22693 /**** Bit definition for Slave Output 2 reset register ************************/
\r
22694 #define HRTIM_RST2R_SRT_Pos (0U)
\r
22695 #define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */
\r
22696 #define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */
\r
22697 #define HRTIM_RST2R_RESYNC_Pos (1U)
\r
22698 #define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */
\r
22699 #define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */
\r
22700 #define HRTIM_RST2R_PER_Pos (2U)
\r
22701 #define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */
\r
22702 #define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */
\r
22703 #define HRTIM_RST2R_CMP1_Pos (3U)
\r
22704 #define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */
\r
22705 #define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */
\r
22706 #define HRTIM_RST2R_CMP2_Pos (4U)
\r
22707 #define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */
\r
22708 #define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */
\r
22709 #define HRTIM_RST2R_CMP3_Pos (5U)
\r
22710 #define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */
\r
22711 #define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */
\r
22712 #define HRTIM_RST2R_CMP4_Pos (6U)
\r
22713 #define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */
\r
22714 #define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */
\r
22716 #define HRTIM_RST2R_MSTPER_Pos (7U)
\r
22717 #define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */
\r
22718 #define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */
\r
22719 #define HRTIM_RST2R_MSTCMP1_Pos (8U)
\r
22720 #define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */
\r
22721 #define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */
\r
22722 #define HRTIM_RST2R_MSTCMP2_Pos (9U)
\r
22723 #define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */
\r
22724 #define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */
\r
22725 #define HRTIM_RST2R_MSTCMP3_Pos (10U)
\r
22726 #define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */
\r
22727 #define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */
\r
22728 #define HRTIM_RST2R_MSTCMP4_Pos (11U)
\r
22729 #define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */
\r
22730 #define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */
\r
22732 #define HRTIM_RST2R_TIMEVNT1_Pos (12U)
\r
22733 #define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */
\r
22734 #define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */
\r
22735 #define HRTIM_RST2R_TIMEVNT2_Pos (13U)
\r
22736 #define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */
\r
22737 #define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */
\r
22738 #define HRTIM_RST2R_TIMEVNT3_Pos (14U)
\r
22739 #define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */
\r
22740 #define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */
\r
22741 #define HRTIM_RST2R_TIMEVNT4_Pos (15U)
\r
22742 #define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */
\r
22743 #define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */
\r
22744 #define HRTIM_RST2R_TIMEVNT5_Pos (16U)
\r
22745 #define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */
\r
22746 #define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */
\r
22747 #define HRTIM_RST2R_TIMEVNT6_Pos (17U)
\r
22748 #define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */
\r
22749 #define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */
\r
22750 #define HRTIM_RST2R_TIMEVNT7_Pos (18U)
\r
22751 #define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */
\r
22752 #define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */
\r
22753 #define HRTIM_RST2R_TIMEVNT8_Pos (19U)
\r
22754 #define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */
\r
22755 #define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */
\r
22756 #define HRTIM_RST2R_TIMEVNT9_Pos (20U)
\r
22757 #define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */
\r
22758 #define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */
\r
22760 #define HRTIM_RST2R_EXTVNT1_Pos (21U)
\r
22761 #define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */
\r
22762 #define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */
\r
22763 #define HRTIM_RST2R_EXTVNT2_Pos (22U)
\r
22764 #define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */
\r
22765 #define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */
\r
22766 #define HRTIM_RST2R_EXTVNT3_Pos (23U)
\r
22767 #define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */
\r
22768 #define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */
\r
22769 #define HRTIM_RST2R_EXTVNT4_Pos (24U)
\r
22770 #define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */
\r
22771 #define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */
\r
22772 #define HRTIM_RST2R_EXTVNT5_Pos (25U)
\r
22773 #define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */
\r
22774 #define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */
\r
22775 #define HRTIM_RST2R_EXTVNT6_Pos (26U)
\r
22776 #define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */
\r
22777 #define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */
\r
22778 #define HRTIM_RST2R_EXTVNT7_Pos (27U)
\r
22779 #define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */
\r
22780 #define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */
\r
22781 #define HRTIM_RST2R_EXTVNT8_Pos (28U)
\r
22782 #define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */
\r
22783 #define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */
\r
22784 #define HRTIM_RST2R_EXTVNT9_Pos (29U)
\r
22785 #define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */
\r
22786 #define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */
\r
22787 #define HRTIM_RST2R_EXTVNT10_Pos (30U)
\r
22788 #define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */
\r
22789 #define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */
\r
22791 #define HRTIM_RST2R_UPDATE_Pos (31U)
\r
22792 #define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */
\r
22793 #define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
\r
22795 /**** Bit definition for Slave external event filtering register 1 ***********/
\r
22796 #define HRTIM_EEFR1_EE1LTCH_Pos (0U)
\r
22797 #define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */
\r
22798 #define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */
\r
22799 #define HRTIM_EEFR1_EE1FLTR_Pos (1U)
\r
22800 #define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */
\r
22801 #define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */
\r
22802 #define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */
\r
22803 #define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */
\r
22804 #define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */
\r
22805 #define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */
\r
22807 #define HRTIM_EEFR1_EE2LTCH_Pos (6U)
\r
22808 #define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */
\r
22809 #define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */
\r
22810 #define HRTIM_EEFR1_EE2FLTR_Pos (7U)
\r
22811 #define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */
\r
22812 #define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */
\r
22813 #define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */
\r
22814 #define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */
\r
22815 #define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */
\r
22816 #define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */
\r
22818 #define HRTIM_EEFR1_EE3LTCH_Pos (12U)
\r
22819 #define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */
\r
22820 #define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */
\r
22821 #define HRTIM_EEFR1_EE3FLTR_Pos (13U)
\r
22822 #define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */
\r
22823 #define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */
\r
22824 #define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */
\r
22825 #define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */
\r
22826 #define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */
\r
22827 #define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */
\r
22829 #define HRTIM_EEFR1_EE4LTCH_Pos (18U)
\r
22830 #define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */
\r
22831 #define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */
\r
22832 #define HRTIM_EEFR1_EE4FLTR_Pos (19U)
\r
22833 #define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */
\r
22834 #define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */
\r
22835 #define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */
\r
22836 #define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */
\r
22837 #define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */
\r
22838 #define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */
\r
22840 #define HRTIM_EEFR1_EE5LTCH_Pos (24U)
\r
22841 #define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */
\r
22842 #define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */
\r
22843 #define HRTIM_EEFR1_EE5FLTR_Pos (25U)
\r
22844 #define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */
\r
22845 #define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */
\r
22846 #define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */
\r
22847 #define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */
\r
22848 #define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */
\r
22849 #define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */
\r
22851 /**** Bit definition for Slave external event filtering register 2 ***********/
\r
22852 #define HRTIM_EEFR2_EE6LTCH_Pos (0U)
\r
22853 #define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */
\r
22854 #define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */
\r
22855 #define HRTIM_EEFR2_EE6FLTR_Pos (1U)
\r
22856 #define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */
\r
22857 #define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */
\r
22858 #define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */
\r
22859 #define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */
\r
22860 #define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */
\r
22861 #define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */
\r
22863 #define HRTIM_EEFR2_EE7LTCH_Pos (6U)
\r
22864 #define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */
\r
22865 #define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */
\r
22866 #define HRTIM_EEFR2_EE7FLTR_Pos (7U)
\r
22867 #define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */
\r
22868 #define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */
\r
22869 #define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */
\r
22870 #define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */
\r
22871 #define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */
\r
22872 #define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */
\r
22874 #define HRTIM_EEFR2_EE8LTCH_Pos (12U)
\r
22875 #define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */
\r
22876 #define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */
\r
22877 #define HRTIM_EEFR2_EE8FLTR_Pos (13U)
\r
22878 #define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */
\r
22879 #define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */
\r
22880 #define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */
\r
22881 #define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */
\r
22882 #define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */
\r
22883 #define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */
\r
22885 #define HRTIM_EEFR2_EE9LTCH_Pos (18U)
\r
22886 #define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */
\r
22887 #define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */
\r
22888 #define HRTIM_EEFR2_EE9FLTR_Pos (19U)
\r
22889 #define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */
\r
22890 #define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */
\r
22891 #define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */
\r
22892 #define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */
\r
22893 #define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */
\r
22894 #define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */
\r
22896 #define HRTIM_EEFR2_EE10LTCH_Pos (24U)
\r
22897 #define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */
\r
22898 #define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */
\r
22899 #define HRTIM_EEFR2_EE10FLTR_Pos (25U)
\r
22900 #define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */
\r
22901 #define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */
\r
22902 #define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */
\r
22903 #define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */
\r
22904 #define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */
\r
22905 #define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */
\r
22907 /**** Bit definition for Slave Timer reset register ***************************/
\r
22908 #define HRTIM_RSTR_UPDATE_Pos (1U)
\r
22909 #define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */
\r
22910 #define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */
\r
22911 #define HRTIM_RSTR_CMP2_Pos (2U)
\r
22912 #define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */
\r
22913 #define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */
\r
22914 #define HRTIM_RSTR_CMP4_Pos (3U)
\r
22915 #define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */
\r
22916 #define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */
\r
22918 #define HRTIM_RSTR_MSTPER_Pos (4U)
\r
22919 #define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */
\r
22920 #define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */
\r
22921 #define HRTIM_RSTR_MSTCMP1_Pos (5U)
\r
22922 #define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */
\r
22923 #define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */
\r
22924 #define HRTIM_RSTR_MSTCMP2_Pos (6U)
\r
22925 #define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */
\r
22926 #define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */
\r
22927 #define HRTIM_RSTR_MSTCMP3_Pos (7U)
\r
22928 #define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */
\r
22929 #define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */
\r
22930 #define HRTIM_RSTR_MSTCMP4_Pos (8U)
\r
22931 #define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */
\r
22932 #define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */
\r
22934 #define HRTIM_RSTR_EXTEVNT1_Pos (9U)
\r
22935 #define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */
\r
22936 #define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */
\r
22937 #define HRTIM_RSTR_EXTEVNT2_Pos (10U)
\r
22938 #define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */
\r
22939 #define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */
\r
22940 #define HRTIM_RSTR_EXTEVNT3_Pos (11U)
\r
22941 #define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */
\r
22942 #define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */
\r
22943 #define HRTIM_RSTR_EXTEVNT4_Pos (12U)
\r
22944 #define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */
\r
22945 #define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */
\r
22946 #define HRTIM_RSTR_EXTEVNT5_Pos (13U)
\r
22947 #define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */
\r
22948 #define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */
\r
22949 #define HRTIM_RSTR_EXTEVNT6_Pos (14U)
\r
22950 #define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */
\r
22951 #define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */
\r
22952 #define HRTIM_RSTR_EXTEVNT7_Pos (15U)
\r
22953 #define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */
\r
22954 #define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */
\r
22955 #define HRTIM_RSTR_EXTEVNT8_Pos (16U)
\r
22956 #define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */
\r
22957 #define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */
\r
22958 #define HRTIM_RSTR_EXTEVNT9_Pos (17U)
\r
22959 #define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */
\r
22960 #define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */
\r
22961 #define HRTIM_RSTR_EXTEVNT10_Pos (18U)
\r
22962 #define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
\r
22963 #define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
\r
22965 #define HRTIM_RSTR_TIMBCMP1_Pos (19U)
\r
22966 #define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
\r
22967 #define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
\r
22968 #define HRTIM_RSTR_TIMBCMP2_Pos (20U)
\r
22969 #define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */
\r
22970 #define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */
\r
22971 #define HRTIM_RSTR_TIMBCMP4_Pos (21U)
\r
22972 #define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
\r
22973 #define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
\r
22975 #define HRTIM_RSTR_TIMCCMP1_Pos (22U)
\r
22976 #define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
\r
22977 #define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
\r
22978 #define HRTIM_RSTR_TIMCCMP2_Pos (23U)
\r
22979 #define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */
\r
22980 #define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */
\r
22981 #define HRTIM_RSTR_TIMCCMP4_Pos (24U)
\r
22982 #define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
\r
22983 #define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
\r
22985 #define HRTIM_RSTR_TIMDCMP1_Pos (25U)
\r
22986 #define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
\r
22987 #define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
\r
22988 #define HRTIM_RSTR_TIMDCMP2_Pos (26U)
\r
22989 #define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */
\r
22990 #define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */
\r
22991 #define HRTIM_RSTR_TIMDCMP4_Pos (27U)
\r
22992 #define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
\r
22993 #define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
\r
22995 #define HRTIM_RSTR_TIMECMP1_Pos (28U)
\r
22996 #define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
\r
22997 #define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
\r
22998 #define HRTIM_RSTR_TIMECMP2_Pos (29U)
\r
22999 #define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */
\r
23000 #define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */
\r
23001 #define HRTIM_RSTR_TIMECMP4_Pos (30U)
\r
23002 #define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
\r
23003 #define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
\r
23005 /**** Bit definition for Slave Timer Chopper register *************************/
\r
23006 #define HRTIM_CHPR_CARFRQ_Pos (0U)
\r
23007 #define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
\r
23008 #define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */
\r
23009 #define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */
\r
23010 #define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */
\r
23011 #define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */
\r
23012 #define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */
\r
23014 #define HRTIM_CHPR_CARDTY_Pos (4U)
\r
23015 #define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */
\r
23016 #define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */
\r
23017 #define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */
\r
23018 #define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */
\r
23019 #define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */
\r
23021 #define HRTIM_CHPR_STRPW_Pos (7U)
\r
23022 #define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */
\r
23023 #define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */
\r
23024 #define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */
\r
23025 #define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */
\r
23026 #define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */
\r
23027 #define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */
\r
23029 /**** Bit definition for Slave Timer Capture 1 control register ***************/
\r
23030 #define HRTIM_CPT1CR_SWCPT_Pos (0U)
\r
23031 #define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */
\r
23032 #define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */
\r
23033 #define HRTIM_CPT1CR_UPDCPT_Pos (1U)
\r
23034 #define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */
\r
23035 #define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */
\r
23036 #define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
\r
23037 #define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */
\r
23038 #define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */
\r
23039 #define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
\r
23040 #define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */
\r
23041 #define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */
\r
23042 #define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
\r
23043 #define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */
\r
23044 #define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */
\r
23045 #define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
\r
23046 #define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */
\r
23047 #define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */
\r
23048 #define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
\r
23049 #define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */
\r
23050 #define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */
\r
23051 #define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
\r
23052 #define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */
\r
23053 #define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */
\r
23054 #define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
\r
23055 #define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */
\r
23056 #define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */
\r
23057 #define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
\r
23058 #define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */
\r
23059 #define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */
\r
23060 #define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
\r
23061 #define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */
\r
23062 #define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */
\r
23063 #define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
\r
23064 #define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */
\r
23065 #define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */
\r
23067 #define HRTIM_CPT1CR_TA1SET_Pos (12U)
\r
23068 #define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */
\r
23069 #define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */
\r
23070 #define HRTIM_CPT1CR_TA1RST_Pos (13U)
\r
23071 #define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */
\r
23072 #define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */
\r
23073 #define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
\r
23074 #define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */
\r
23075 #define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */
\r
23076 #define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
\r
23077 #define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */
\r
23078 #define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */
\r
23080 #define HRTIM_CPT1CR_TB1SET_Pos (16U)
\r
23081 #define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */
\r
23082 #define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */
\r
23083 #define HRTIM_CPT1CR_TB1RST_Pos (17U)
\r
23084 #define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */
\r
23085 #define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */
\r
23086 #define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
\r
23087 #define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */
\r
23088 #define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
\r
23089 #define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
\r
23090 #define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */
\r
23091 #define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
\r
23093 #define HRTIM_CPT1CR_TC1SET_Pos (20U)
\r
23094 #define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */
\r
23095 #define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */
\r
23096 #define HRTIM_CPT1CR_TC1RST_Pos (21U)
\r
23097 #define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */
\r
23098 #define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */
\r
23099 #define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
\r
23100 #define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */
\r
23101 #define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
\r
23102 #define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
\r
23103 #define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */
\r
23104 #define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
\r
23106 #define HRTIM_CPT1CR_TD1SET_Pos (24U)
\r
23107 #define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */
\r
23108 #define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */
\r
23109 #define HRTIM_CPT1CR_TD1RST_Pos (25U)
\r
23110 #define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */
\r
23111 #define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */
\r
23112 #define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
\r
23113 #define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */
\r
23114 #define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
\r
23115 #define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
\r
23116 #define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */
\r
23117 #define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
\r
23119 #define HRTIM_CPT1CR_TE1SET_Pos (28U)
\r
23120 #define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */
\r
23121 #define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */
\r
23122 #define HRTIM_CPT1CR_TE1RST_Pos (29U)
\r
23123 #define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */
\r
23124 #define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */
\r
23125 #define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
\r
23126 #define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */
\r
23127 #define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */
\r
23128 #define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
\r
23129 #define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */
\r
23130 #define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */
\r
23132 /**** Bit definition for Slave Timer Capture 2 control register ***************/
\r
23133 #define HRTIM_CPT2CR_SWCPT_Pos (0U)
\r
23134 #define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */
\r
23135 #define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */
\r
23136 #define HRTIM_CPT2CR_UPDCPT_Pos (1U)
\r
23137 #define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */
\r
23138 #define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */
\r
23139 #define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
\r
23140 #define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */
\r
23141 #define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */
\r
23142 #define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
\r
23143 #define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */
\r
23144 #define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */
\r
23145 #define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
\r
23146 #define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */
\r
23147 #define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */
\r
23148 #define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
\r
23149 #define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */
\r
23150 #define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */
\r
23151 #define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
\r
23152 #define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */
\r
23153 #define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */
\r
23154 #define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
\r
23155 #define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */
\r
23156 #define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */
\r
23157 #define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
\r
23158 #define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */
\r
23159 #define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */
\r
23160 #define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
\r
23161 #define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */
\r
23162 #define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */
\r
23163 #define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
\r
23164 #define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */
\r
23165 #define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */
\r
23166 #define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
\r
23167 #define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */
\r
23168 #define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */
\r
23170 #define HRTIM_CPT2CR_TA1SET_Pos (12U)
\r
23171 #define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */
\r
23172 #define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */
\r
23173 #define HRTIM_CPT2CR_TA1RST_Pos (13U)
\r
23174 #define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */
\r
23175 #define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */
\r
23176 #define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
\r
23177 #define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */
\r
23178 #define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */
\r
23179 #define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
\r
23180 #define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */
\r
23181 #define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */
\r
23183 #define HRTIM_CPT2CR_TB1SET_Pos (16U)
\r
23184 #define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */
\r
23185 #define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */
\r
23186 #define HRTIM_CPT2CR_TB1RST_Pos (17U)
\r
23187 #define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */
\r
23188 #define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */
\r
23189 #define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
\r
23190 #define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */
\r
23191 #define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
\r
23192 #define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
\r
23193 #define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */
\r
23194 #define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
\r
23196 #define HRTIM_CPT2CR_TC1SET_Pos (20U)
\r
23197 #define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */
\r
23198 #define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */
\r
23199 #define HRTIM_CPT2CR_TC1RST_Pos (21U)
\r
23200 #define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */
\r
23201 #define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */
\r
23202 #define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
\r
23203 #define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */
\r
23204 #define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
\r
23205 #define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
\r
23206 #define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */
\r
23207 #define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
\r
23209 #define HRTIM_CPT2CR_TD1SET_Pos (24U)
\r
23210 #define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */
\r
23211 #define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */
\r
23212 #define HRTIM_CPT2CR_TD1RST_Pos (25U)
\r
23213 #define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */
\r
23214 #define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */
\r
23215 #define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
\r
23216 #define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */
\r
23217 #define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
\r
23218 #define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
\r
23219 #define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */
\r
23220 #define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
\r
23222 #define HRTIM_CPT2CR_TE1SET_Pos (28U)
\r
23223 #define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */
\r
23224 #define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */
\r
23225 #define HRTIM_CPT2CR_TE1RST_Pos (29U)
\r
23226 #define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */
\r
23227 #define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */
\r
23228 #define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
\r
23229 #define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */
\r
23230 #define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */
\r
23231 #define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
\r
23232 #define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */
\r
23233 #define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */
\r
23235 /**** Bit definition for Slave Timer Output register **************************/
\r
23236 #define HRTIM_OUTR_POL1_Pos (1U)
\r
23237 #define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */
\r
23238 #define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */
\r
23239 #define HRTIM_OUTR_IDLM1_Pos (2U)
\r
23240 #define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */
\r
23241 #define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */
\r
23242 #define HRTIM_OUTR_IDLES1_Pos (3U)
\r
23243 #define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */
\r
23244 #define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */
\r
23245 #define HRTIM_OUTR_FAULT1_Pos (4U)
\r
23246 #define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */
\r
23247 #define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */
\r
23248 #define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */
\r
23249 #define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */
\r
23250 #define HRTIM_OUTR_CHP1_Pos (6U)
\r
23251 #define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */
\r
23252 #define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */
\r
23253 #define HRTIM_OUTR_DIDL1_Pos (7U)
\r
23254 #define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */
\r
23255 #define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */
\r
23257 #define HRTIM_OUTR_DTEN_Pos (8U)
\r
23258 #define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */
\r
23259 #define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */
\r
23260 #define HRTIM_OUTR_DLYPRTEN_Pos (9U)
\r
23261 #define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */
\r
23262 #define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */
\r
23263 #define HRTIM_OUTR_DLYPRT_Pos (10U)
\r
23264 #define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */
\r
23265 #define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */
\r
23266 #define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */
\r
23267 #define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */
\r
23268 #define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */
\r
23270 #define HRTIM_OUTR_POL2_Pos (17U)
\r
23271 #define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */
\r
23272 #define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */
\r
23273 #define HRTIM_OUTR_IDLM2_Pos (18U)
\r
23274 #define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */
\r
23275 #define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */
\r
23276 #define HRTIM_OUTR_IDLES2_Pos (19U)
\r
23277 #define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */
\r
23278 #define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */
\r
23279 #define HRTIM_OUTR_FAULT2_Pos (20U)
\r
23280 #define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */
\r
23281 #define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */
\r
23282 #define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */
\r
23283 #define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */
\r
23284 #define HRTIM_OUTR_CHP2_Pos (22U)
\r
23285 #define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */
\r
23286 #define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */
\r
23287 #define HRTIM_OUTR_DIDL2_Pos (23U)
\r
23288 #define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */
\r
23289 #define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */
\r
23291 /**** Bit definition for Slave Timer Fault register ***************************/
\r
23292 #define HRTIM_FLTR_FLT1EN_Pos (0U)
\r
23293 #define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */
\r
23294 #define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */
\r
23295 #define HRTIM_FLTR_FLT2EN_Pos (1U)
\r
23296 #define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */
\r
23297 #define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */
\r
23298 #define HRTIM_FLTR_FLT3EN_Pos (2U)
\r
23299 #define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */
\r
23300 #define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */
\r
23301 #define HRTIM_FLTR_FLT4EN_Pos (3U)
\r
23302 #define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */
\r
23303 #define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */
\r
23304 #define HRTIM_FLTR_FLT5EN_Pos (4U)
\r
23305 #define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */
\r
23306 #define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */
\r
23307 #define HRTIM_FLTR_FLTLCK_Pos (31U)
\r
23308 #define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */
\r
23309 #define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */
\r
23311 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
\r
23312 #define HRTIM_CR1_MUDIS_Pos (0U)
\r
23313 #define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */
\r
23314 #define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/
\r
23315 #define HRTIM_CR1_TAUDIS_Pos (1U)
\r
23316 #define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */
\r
23317 #define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/
\r
23318 #define HRTIM_CR1_TBUDIS_Pos (2U)
\r
23319 #define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */
\r
23320 #define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/
\r
23321 #define HRTIM_CR1_TCUDIS_Pos (3U)
\r
23322 #define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */
\r
23323 #define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/
\r
23324 #define HRTIM_CR1_TDUDIS_Pos (4U)
\r
23325 #define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */
\r
23326 #define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/
\r
23327 #define HRTIM_CR1_TEUDIS_Pos (5U)
\r
23328 #define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */
\r
23329 #define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/
\r
23330 #define HRTIM_CR1_ADC1USRC_Pos (16U)
\r
23331 #define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */
\r
23332 #define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */
\r
23333 #define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */
\r
23334 #define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */
\r
23335 #define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */
\r
23336 #define HRTIM_CR1_ADC2USRC_Pos (19U)
\r
23337 #define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */
\r
23338 #define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */
\r
23339 #define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */
\r
23340 #define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */
\r
23341 #define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */
\r
23342 #define HRTIM_CR1_ADC3USRC_Pos (22U)
\r
23343 #define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */
\r
23344 #define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */
\r
23345 #define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */
\r
23346 #define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */
\r
23347 #define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */
\r
23348 #define HRTIM_CR1_ADC4USRC_Pos (25U)
\r
23349 #define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */
\r
23350 #define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */
\r
23351 #define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */
\r
23352 #define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */
\r
23353 #define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */
\r
23355 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
\r
23356 #define HRTIM_CR2_MSWU_Pos (0U)
\r
23357 #define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */
\r
23358 #define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */
\r
23359 #define HRTIM_CR2_TASWU_Pos (1U)
\r
23360 #define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */
\r
23361 #define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */
\r
23362 #define HRTIM_CR2_TBSWU_Pos (2U)
\r
23363 #define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */
\r
23364 #define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */
\r
23365 #define HRTIM_CR2_TCSWU_Pos (3U)
\r
23366 #define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */
\r
23367 #define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */
\r
23368 #define HRTIM_CR2_TDSWU_Pos (4U)
\r
23369 #define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */
\r
23370 #define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */
\r
23371 #define HRTIM_CR2_TESWU_Pos (5U)
\r
23372 #define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */
\r
23373 #define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */
\r
23374 #define HRTIM_CR2_MRST_Pos (8U)
\r
23375 #define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */
\r
23376 #define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */
\r
23377 #define HRTIM_CR2_TARST_Pos (9U)
\r
23378 #define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */
\r
23379 #define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */
\r
23380 #define HRTIM_CR2_TBRST_Pos (10U)
\r
23381 #define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */
\r
23382 #define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */
\r
23383 #define HRTIM_CR2_TCRST_Pos (11U)
\r
23384 #define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */
\r
23385 #define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */
\r
23386 #define HRTIM_CR2_TDRST_Pos (12U)
\r
23387 #define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */
\r
23388 #define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */
\r
23389 #define HRTIM_CR2_TERST_Pos (13U)
\r
23390 #define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */
\r
23391 #define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */
\r
23393 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
\r
23394 #define HRTIM_ISR_FLT1_Pos (0U)
\r
23395 #define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */
\r
23396 #define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */
\r
23397 #define HRTIM_ISR_FLT2_Pos (1U)
\r
23398 #define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */
\r
23399 #define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */
\r
23400 #define HRTIM_ISR_FLT3_Pos (2U)
\r
23401 #define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */
\r
23402 #define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */
\r
23403 #define HRTIM_ISR_FLT4_Pos (3U)
\r
23404 #define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */
\r
23405 #define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */
\r
23406 #define HRTIM_ISR_FLT5_Pos (4U)
\r
23407 #define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */
\r
23408 #define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */
\r
23409 #define HRTIM_ISR_SYSFLT_Pos (5U)
\r
23410 #define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */
\r
23411 #define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */
\r
23412 #define HRTIM_ISR_BMPER_Pos (17U)
\r
23413 #define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */
\r
23414 #define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */
\r
23416 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
\r
23417 #define HRTIM_ICR_FLT1C_Pos (0U)
\r
23418 #define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */
\r
23419 #define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */
\r
23420 #define HRTIM_ICR_FLT2C_Pos (1U)
\r
23421 #define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */
\r
23422 #define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */
\r
23423 #define HRTIM_ICR_FLT3C_Pos (2U)
\r
23424 #define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */
\r
23425 #define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */
\r
23426 #define HRTIM_ICR_FLT4C_Pos (3U)
\r
23427 #define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */
\r
23428 #define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */
\r
23429 #define HRTIM_ICR_FLT5C_Pos (4U)
\r
23430 #define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */
\r
23431 #define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */
\r
23432 #define HRTIM_ICR_SYSFLTC_Pos (5U)
\r
23433 #define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */
\r
23434 #define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */
\r
23435 #define HRTIM_ICR_BMPERC_Pos (17U)
\r
23436 #define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */
\r
23437 #define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */
\r
23439 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
\r
23440 #define HRTIM_IER_FLT1_Pos (0U)
\r
23441 #define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */
\r
23442 #define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */
\r
23443 #define HRTIM_IER_FLT2_Pos (1U)
\r
23444 #define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */
\r
23445 #define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */
\r
23446 #define HRTIM_IER_FLT3_Pos (2U)
\r
23447 #define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */
\r
23448 #define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */
\r
23449 #define HRTIM_IER_FLT4_Pos (3U)
\r
23450 #define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */
\r
23451 #define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */
\r
23452 #define HRTIM_IER_FLT5_Pos (4U)
\r
23453 #define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */
\r
23454 #define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */
\r
23455 #define HRTIM_IER_SYSFLT_Pos (5U)
\r
23456 #define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */
\r
23457 #define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */
\r
23458 #define HRTIM_IER_BMPER_Pos (17U)
\r
23459 #define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */
\r
23460 #define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */
\r
23462 /**** Bit definition for Common HRTIM Timer output enable register ************/
\r
23463 #define HRTIM_OENR_TA1OEN_Pos (0U)
\r
23464 #define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */
\r
23465 #define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */
\r
23466 #define HRTIM_OENR_TA2OEN_Pos (1U)
\r
23467 #define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */
\r
23468 #define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */
\r
23469 #define HRTIM_OENR_TB1OEN_Pos (2U)
\r
23470 #define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */
\r
23471 #define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */
\r
23472 #define HRTIM_OENR_TB2OEN_Pos (3U)
\r
23473 #define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */
\r
23474 #define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */
\r
23475 #define HRTIM_OENR_TC1OEN_Pos (4U)
\r
23476 #define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */
\r
23477 #define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */
\r
23478 #define HRTIM_OENR_TC2OEN_Pos (5U)
\r
23479 #define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */
\r
23480 #define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */
\r
23481 #define HRTIM_OENR_TD1OEN_Pos (6U)
\r
23482 #define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */
\r
23483 #define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */
\r
23484 #define HRTIM_OENR_TD2OEN_Pos (7U)
\r
23485 #define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */
\r
23486 #define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */
\r
23487 #define HRTIM_OENR_TE1OEN_Pos (8U)
\r
23488 #define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */
\r
23489 #define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */
\r
23490 #define HRTIM_OENR_TE2OEN_Pos (9U)
\r
23491 #define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */
\r
23492 #define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */
\r
23494 /**** Bit definition for Common HRTIM Timer output disable register ***********/
\r
23495 #define HRTIM_ODISR_TA1ODIS_Pos (0U)
\r
23496 #define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */
\r
23497 #define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */
\r
23498 #define HRTIM_ODISR_TA2ODIS_Pos (1U)
\r
23499 #define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */
\r
23500 #define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */
\r
23501 #define HRTIM_ODISR_TB1ODIS_Pos (2U)
\r
23502 #define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */
\r
23503 #define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */
\r
23504 #define HRTIM_ODISR_TB2ODIS_Pos (3U)
\r
23505 #define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */
\r
23506 #define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */
\r
23507 #define HRTIM_ODISR_TC1ODIS_Pos (4U)
\r
23508 #define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */
\r
23509 #define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */
\r
23510 #define HRTIM_ODISR_TC2ODIS_Pos (5U)
\r
23511 #define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */
\r
23512 #define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */
\r
23513 #define HRTIM_ODISR_TD1ODIS_Pos (6U)
\r
23514 #define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */
\r
23515 #define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */
\r
23516 #define HRTIM_ODISR_TD2ODIS_Pos (7U)
\r
23517 #define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */
\r
23518 #define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */
\r
23519 #define HRTIM_ODISR_TE1ODIS_Pos (8U)
\r
23520 #define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */
\r
23521 #define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */
\r
23522 #define HRTIM_ODISR_TE2ODIS_Pos (9U)
\r
23523 #define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */
\r
23524 #define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */
\r
23526 /**** Bit definition for Common HRTIM Timer output disable status register *****/
\r
23527 #define HRTIM_ODSR_TA1ODS_Pos (0U)
\r
23528 #define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */
\r
23529 #define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */
\r
23530 #define HRTIM_ODSR_TA2ODS_Pos (1U)
\r
23531 #define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */
\r
23532 #define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */
\r
23533 #define HRTIM_ODSR_TB1ODS_Pos (2U)
\r
23534 #define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */
\r
23535 #define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */
\r
23536 #define HRTIM_ODSR_TB2ODS_Pos (3U)
\r
23537 #define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */
\r
23538 #define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */
\r
23539 #define HRTIM_ODSR_TC1ODS_Pos (4U)
\r
23540 #define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */
\r
23541 #define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */
\r
23542 #define HRTIM_ODSR_TC2ODS_Pos (5U)
\r
23543 #define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */
\r
23544 #define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */
\r
23545 #define HRTIM_ODSR_TD1ODS_Pos (6U)
\r
23546 #define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */
\r
23547 #define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */
\r
23548 #define HRTIM_ODSR_TD2ODS_Pos (7U)
\r
23549 #define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */
\r
23550 #define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */
\r
23551 #define HRTIM_ODSR_TE1ODS_Pos (8U)
\r
23552 #define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */
\r
23553 #define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */
\r
23554 #define HRTIM_ODSR_TE2ODS_Pos (9U)
\r
23555 #define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */
\r
23556 #define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */
\r
23558 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
\r
23559 #define HRTIM_BMCR_BME_Pos (0U)
\r
23560 #define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
\r
23561 #define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
\r
23562 #define HRTIM_BMCR_BMOM_Pos (1U)
\r
23563 #define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
\r
23564 #define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
\r
23565 #define HRTIM_BMCR_BMCLK_Pos (2U)
\r
23566 #define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */
\r
23567 #define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */
\r
23568 #define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */
\r
23569 #define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */
\r
23570 #define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */
\r
23571 #define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */
\r
23572 #define HRTIM_BMCR_BMPRSC_Pos (6U)
\r
23573 #define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */
\r
23574 #define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */
\r
23575 #define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */
\r
23576 #define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */
\r
23577 #define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */
\r
23578 #define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */
\r
23579 #define HRTIM_BMCR_BMPREN_Pos (10U)
\r
23580 #define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */
\r
23581 #define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */
\r
23582 #define HRTIM_BMCR_MTBM_Pos (16U)
\r
23583 #define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */
\r
23584 #define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */
\r
23585 #define HRTIM_BMCR_TABM_Pos (17U)
\r
23586 #define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */
\r
23587 #define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */
\r
23588 #define HRTIM_BMCR_TBBM_Pos (18U)
\r
23589 #define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */
\r
23590 #define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */
\r
23591 #define HRTIM_BMCR_TCBM_Pos (19U)
\r
23592 #define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */
\r
23593 #define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */
\r
23594 #define HRTIM_BMCR_TDBM_Pos (20U)
\r
23595 #define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */
\r
23596 #define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */
\r
23597 #define HRTIM_BMCR_TEBM_Pos (21U)
\r
23598 #define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */
\r
23599 #define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */
\r
23600 #define HRTIM_BMCR_BMSTAT_Pos (31U)
\r
23601 #define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */
\r
23602 #define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */
\r
23604 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
\r
23605 #define HRTIM_BMTRGR_SW_Pos (0U)
\r
23606 #define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */
\r
23607 #define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */
\r
23608 #define HRTIM_BMTRGR_MSTRST_Pos (1U)
\r
23609 #define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */
\r
23610 #define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */
\r
23611 #define HRTIM_BMTRGR_MSTREP_Pos (2U)
\r
23612 #define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */
\r
23613 #define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */
\r
23614 #define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
\r
23615 #define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */
\r
23616 #define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */
\r
23617 #define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
\r
23618 #define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */
\r
23619 #define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */
\r
23620 #define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
\r
23621 #define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */
\r
23622 #define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */
\r
23623 #define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
\r
23624 #define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */
\r
23625 #define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */
\r
23626 #define HRTIM_BMTRGR_TARST_Pos (7U)
\r
23627 #define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */
\r
23628 #define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */
\r
23629 #define HRTIM_BMTRGR_TAREP_Pos (8U)
\r
23630 #define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */
\r
23631 #define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */
\r
23632 #define HRTIM_BMTRGR_TACMP1_Pos (9U)
\r
23633 #define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */
\r
23634 #define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */
\r
23635 #define HRTIM_BMTRGR_TACMP2_Pos (10U)
\r
23636 #define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */
\r
23637 #define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */
\r
23638 #define HRTIM_BMTRGR_TBRST_Pos (11U)
\r
23639 #define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */
\r
23640 #define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */
\r
23641 #define HRTIM_BMTRGR_TBREP_Pos (12U)
\r
23642 #define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */
\r
23643 #define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */
\r
23644 #define HRTIM_BMTRGR_TBCMP1_Pos (13U)
\r
23645 #define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */
\r
23646 #define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */
\r
23647 #define HRTIM_BMTRGR_TBCMP2_Pos (14U)
\r
23648 #define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */
\r
23649 #define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */
\r
23650 #define HRTIM_BMTRGR_TCRST_Pos (15U)
\r
23651 #define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */
\r
23652 #define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */
\r
23653 #define HRTIM_BMTRGR_TCREP_Pos (16U)
\r
23654 #define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */
\r
23655 #define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */
\r
23656 #define HRTIM_BMTRGR_TCCMP1_Pos (17U)
\r
23657 #define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */
\r
23658 #define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */
\r
23659 #define HRTIM_BMTRGR_TCCMP2_Pos (18U)
\r
23660 #define HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos) /*!< 0x00040000 */
\r
23661 #define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk /*!< Timer C compare 2 */
\r
23662 #define HRTIM_BMTRGR_TDRST_Pos (19U)
\r
23663 #define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */
\r
23664 #define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */
\r
23665 #define HRTIM_BMTRGR_TDREP_Pos (20U)
\r
23666 #define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */
\r
23667 #define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */
\r
23668 #define HRTIM_BMTRGR_TDCMP1_Pos (21U)
\r
23669 #define HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos) /*!< 0x00200000 */
\r
23670 #define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk /*!< Timer D compare 1 */
\r
23671 #define HRTIM_BMTRGR_TDCMP2_Pos (22U)
\r
23672 #define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */
\r
23673 #define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */
\r
23674 #define HRTIM_BMTRGR_TERST_Pos (23U)
\r
23675 #define HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos) /*!< 0x00800000 */
\r
23676 #define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk /*!< Timer E reset */
\r
23677 #define HRTIM_BMTRGR_TEREP_Pos (24U)
\r
23678 #define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */
\r
23679 #define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */
\r
23680 #define HRTIM_BMTRGR_TECMP1_Pos (25U)
\r
23681 #define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */
\r
23682 #define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */
\r
23683 #define HRTIM_BMTRGR_TECMP2_Pos (26U)
\r
23684 #define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */
\r
23685 #define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */
\r
23686 #define HRTIM_BMTRGR_TAEEV7_Pos (27U)
\r
23687 #define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */
\r
23688 #define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */
\r
23689 #define HRTIM_BMTRGR_TDEEV8_Pos (28U)
\r
23690 #define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */
\r
23691 #define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */
\r
23692 #define HRTIM_BMTRGR_EEV7_Pos (29U)
\r
23693 #define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */
\r
23694 #define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */
\r
23695 #define HRTIM_BMTRGR_EEV8_Pos (30U)
\r
23696 #define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */
\r
23697 #define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */
\r
23698 #define HRTIM_BMTRGR_OCHPEV_Pos (31U)
\r
23699 #define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */
\r
23700 #define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
\r
23702 /******************* Bit definition for HRTIM_BMCMPR register ***************/
\r
23703 #define HRTIM_BMCMPR_BMCMPR_Pos (0U)
\r
23704 #define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */
\r
23705 #define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */
\r
23707 /******************* Bit definition for HRTIM_BMPER register ****************/
\r
23708 #define HRTIM_BMPER_BMPER_Pos (0U)
\r
23709 #define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */
\r
23710 #define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */
\r
23712 /******************* Bit definition for HRTIM_EECR1 register ****************/
\r
23713 #define HRTIM_EECR1_EE1SRC_Pos (0U)
\r
23714 #define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */
\r
23715 #define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */
\r
23716 #define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */
\r
23717 #define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */
\r
23718 #define HRTIM_EECR1_EE1POL_Pos (2U)
\r
23719 #define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */
\r
23720 #define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */
\r
23721 #define HRTIM_EECR1_EE1SNS_Pos (3U)
\r
23722 #define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */
\r
23723 #define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */
\r
23724 #define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */
\r
23725 #define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */
\r
23726 #define HRTIM_EECR1_EE1FAST_Pos (5U)
\r
23727 #define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */
\r
23728 #define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
\r
23730 #define HRTIM_EECR1_EE2SRC_Pos (6U)
\r
23731 #define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */
\r
23732 #define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */
\r
23733 #define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */
\r
23734 #define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */
\r
23735 #define HRTIM_EECR1_EE2POL_Pos (8U)
\r
23736 #define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */
\r
23737 #define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */
\r
23738 #define HRTIM_EECR1_EE2SNS_Pos (9U)
\r
23739 #define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */
\r
23740 #define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */
\r
23741 #define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */
\r
23742 #define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */
\r
23743 #define HRTIM_EECR1_EE2FAST_Pos (11U)
\r
23744 #define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */
\r
23745 #define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
\r
23747 #define HRTIM_EECR1_EE3SRC_Pos (12U)
\r
23748 #define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */
\r
23749 #define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */
\r
23750 #define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */
\r
23751 #define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */
\r
23752 #define HRTIM_EECR1_EE3POL_Pos (14U)
\r
23753 #define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */
\r
23754 #define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */
\r
23755 #define HRTIM_EECR1_EE3SNS_Pos (15U)
\r
23756 #define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */
\r
23757 #define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */
\r
23758 #define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */
\r
23759 #define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */
\r
23760 #define HRTIM_EECR1_EE3FAST_Pos (17U)
\r
23761 #define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */
\r
23762 #define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
\r
23764 #define HRTIM_EECR1_EE4SRC_Pos (18U)
\r
23765 #define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */
\r
23766 #define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */
\r
23767 #define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */
\r
23768 #define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */
\r
23769 #define HRTIM_EECR1_EE4POL_Pos (20U)
\r
23770 #define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */
\r
23771 #define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */
\r
23772 #define HRTIM_EECR1_EE4SNS_Pos (21U)
\r
23773 #define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */
\r
23774 #define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */
\r
23775 #define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */
\r
23776 #define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */
\r
23777 #define HRTIM_EECR1_EE4FAST_Pos (23U)
\r
23778 #define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */
\r
23779 #define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
\r
23781 #define HRTIM_EECR1_EE5SRC_Pos (24U)
\r
23782 #define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */
\r
23783 #define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */
\r
23784 #define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */
\r
23785 #define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */
\r
23786 #define HRTIM_EECR1_EE5POL_Pos (26U)
\r
23787 #define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */
\r
23788 #define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */
\r
23789 #define HRTIM_EECR1_EE5SNS_Pos (27U)
\r
23790 #define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */
\r
23791 #define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */
\r
23792 #define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */
\r
23793 #define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */
\r
23794 #define HRTIM_EECR1_EE5FAST_Pos (29U)
\r
23795 #define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */
\r
23796 #define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
\r
23798 /******************* Bit definition for HRTIM_EECR2 register ****************/
\r
23799 #define HRTIM_EECR2_EE6SRC_Pos (0U)
\r
23800 #define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */
\r
23801 #define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */
\r
23802 #define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */
\r
23803 #define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */
\r
23804 #define HRTIM_EECR2_EE6POL_Pos (2U)
\r
23805 #define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */
\r
23806 #define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */
\r
23807 #define HRTIM_EECR2_EE6SNS_Pos (3U)
\r
23808 #define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */
\r
23809 #define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */
\r
23810 #define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */
\r
23811 #define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */
\r
23813 #define HRTIM_EECR2_EE7SRC_Pos (6U)
\r
23814 #define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */
\r
23815 #define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */
\r
23816 #define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */
\r
23817 #define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */
\r
23818 #define HRTIM_EECR2_EE7POL_Pos (8U)
\r
23819 #define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */
\r
23820 #define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */
\r
23821 #define HRTIM_EECR2_EE7SNS_Pos (9U)
\r
23822 #define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */
\r
23823 #define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */
\r
23824 #define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */
\r
23825 #define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */
\r
23827 #define HRTIM_EECR2_EE8SRC_Pos (12U)
\r
23828 #define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */
\r
23829 #define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */
\r
23830 #define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */
\r
23831 #define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */
\r
23832 #define HRTIM_EECR2_EE8POL_Pos (14U)
\r
23833 #define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */
\r
23834 #define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */
\r
23835 #define HRTIM_EECR2_EE8SNS_Pos (15U)
\r
23836 #define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */
\r
23837 #define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */
\r
23838 #define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */
\r
23839 #define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */
\r
23841 #define HRTIM_EECR2_EE9SRC_Pos (18U)
\r
23842 #define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */
\r
23843 #define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */
\r
23844 #define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */
\r
23845 #define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */
\r
23846 #define HRTIM_EECR2_EE9POL_Pos (20U)
\r
23847 #define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */
\r
23848 #define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */
\r
23849 #define HRTIM_EECR2_EE9SNS_Pos (21U)
\r
23850 #define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */
\r
23851 #define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */
\r
23852 #define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */
\r
23853 #define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */
\r
23855 #define HRTIM_EECR2_EE10SRC_Pos (24U)
\r
23856 #define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */
\r
23857 #define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */
\r
23858 #define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */
\r
23859 #define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */
\r
23860 #define HRTIM_EECR2_EE10POL_Pos (26U)
\r
23861 #define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */
\r
23862 #define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */
\r
23863 #define HRTIM_EECR2_EE10SNS_Pos (27U)
\r
23864 #define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */
\r
23865 #define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */
\r
23866 #define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */
\r
23867 #define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */
\r
23869 /******************* Bit definition for HRTIM_EECR3 register ****************/
\r
23870 #define HRTIM_EECR3_EE6F_Pos (0U)
\r
23871 #define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */
\r
23872 #define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */
\r
23873 #define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */
\r
23874 #define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */
\r
23875 #define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */
\r
23876 #define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */
\r
23877 #define HRTIM_EECR3_EE7F_Pos (6U)
\r
23878 #define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */
\r
23879 #define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */
\r
23880 #define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */
\r
23881 #define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */
\r
23882 #define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */
\r
23883 #define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */
\r
23884 #define HRTIM_EECR3_EE8F_Pos (12U)
\r
23885 #define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */
\r
23886 #define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */
\r
23887 #define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */
\r
23888 #define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */
\r
23889 #define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */
\r
23890 #define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */
\r
23891 #define HRTIM_EECR3_EE9F_Pos (18U)
\r
23892 #define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */
\r
23893 #define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */
\r
23894 #define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */
\r
23895 #define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */
\r
23896 #define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */
\r
23897 #define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */
\r
23898 #define HRTIM_EECR3_EE10F_Pos (24U)
\r
23899 #define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */
\r
23900 #define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */
\r
23901 #define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */
\r
23902 #define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */
\r
23903 #define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */
\r
23904 #define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */
\r
23905 #define HRTIM_EECR3_EEVSD_Pos (30U)
\r
23906 #define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */
\r
23907 #define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */
\r
23908 #define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */
\r
23909 #define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */
\r
23911 /******************* Bit definition for HRTIM_ADC1R register ****************/
\r
23912 #define HRTIM_ADC1R_AD1MC1_Pos (0U)
\r
23913 #define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */
\r
23914 #define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */
\r
23915 #define HRTIM_ADC1R_AD1MC2_Pos (1U)
\r
23916 #define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */
\r
23917 #define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */
\r
23918 #define HRTIM_ADC1R_AD1MC3_Pos (2U)
\r
23919 #define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */
\r
23920 #define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */
\r
23921 #define HRTIM_ADC1R_AD1MC4_Pos (3U)
\r
23922 #define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */
\r
23923 #define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */
\r
23924 #define HRTIM_ADC1R_AD1MPER_Pos (4U)
\r
23925 #define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */
\r
23926 #define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */
\r
23927 #define HRTIM_ADC1R_AD1EEV1_Pos (5U)
\r
23928 #define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */
\r
23929 #define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */
\r
23930 #define HRTIM_ADC1R_AD1EEV2_Pos (6U)
\r
23931 #define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */
\r
23932 #define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */
\r
23933 #define HRTIM_ADC1R_AD1EEV3_Pos (7U)
\r
23934 #define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */
\r
23935 #define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */
\r
23936 #define HRTIM_ADC1R_AD1EEV4_Pos (8U)
\r
23937 #define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */
\r
23938 #define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */
\r
23939 #define HRTIM_ADC1R_AD1EEV5_Pos (9U)
\r
23940 #define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */
\r
23941 #define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */
\r
23942 #define HRTIM_ADC1R_AD1TAC2_Pos (10U)
\r
23943 #define HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos) /*!< 0x00000400 */
\r
23944 #define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk /*!< ADC Trigger 1 on Timer A compare 2 */
\r
23945 #define HRTIM_ADC1R_AD1TAC3_Pos (11U)
\r
23946 #define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */
\r
23947 #define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */
\r
23948 #define HRTIM_ADC1R_AD1TAC4_Pos (12U)
\r
23949 #define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */
\r
23950 #define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */
\r
23951 #define HRTIM_ADC1R_AD1TAPER_Pos (13U)
\r
23952 #define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */
\r
23953 #define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */
\r
23954 #define HRTIM_ADC1R_AD1TARST_Pos (14U)
\r
23955 #define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */
\r
23956 #define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */
\r
23957 #define HRTIM_ADC1R_AD1TBC2_Pos (15U)
\r
23958 #define HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos) /*!< 0x00008000 */
\r
23959 #define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk /*!< ADC Trigger 1 on Timer B compare 2 */
\r
23960 #define HRTIM_ADC1R_AD1TBC3_Pos (16U)
\r
23961 #define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */
\r
23962 #define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */
\r
23963 #define HRTIM_ADC1R_AD1TBC4_Pos (17U)
\r
23964 #define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */
\r
23965 #define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */
\r
23966 #define HRTIM_ADC1R_AD1TBPER_Pos (18U)
\r
23967 #define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */
\r
23968 #define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */
\r
23969 #define HRTIM_ADC1R_AD1TBRST_Pos (19U)
\r
23970 #define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */
\r
23971 #define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */
\r
23972 #define HRTIM_ADC1R_AD1TCC2_Pos (20U)
\r
23973 #define HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos) /*!< 0x00100000 */
\r
23974 #define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk /*!< ADC Trigger 1 on Timer C compare 2 */
\r
23975 #define HRTIM_ADC1R_AD1TCC3_Pos (21U)
\r
23976 #define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */
\r
23977 #define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */
\r
23978 #define HRTIM_ADC1R_AD1TCC4_Pos (22U)
\r
23979 #define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */
\r
23980 #define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */
\r
23981 #define HRTIM_ADC1R_AD1TCPER_Pos (23U)
\r
23982 #define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */
\r
23983 #define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */
\r
23984 #define HRTIM_ADC1R_AD1TDC2_Pos (24U)
\r
23985 #define HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos) /*!< 0x01000000 */
\r
23986 #define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk /*!< ADC Trigger 1 on Timer D compare 2 */
\r
23987 #define HRTIM_ADC1R_AD1TDC3_Pos (25U)
\r
23988 #define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */
\r
23989 #define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */
\r
23990 #define HRTIM_ADC1R_AD1TDC4_Pos (26U)
\r
23991 #define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */
\r
23992 #define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */
\r
23993 #define HRTIM_ADC1R_AD1TDPER_Pos (27U)
\r
23994 #define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */
\r
23995 #define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */
\r
23996 #define HRTIM_ADC1R_AD1TEC2_Pos (28U)
\r
23997 #define HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos) /*!< 0x10000000 */
\r
23998 #define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk /*!< ADC Trigger 1 on Timer E compare 2 */
\r
23999 #define HRTIM_ADC1R_AD1TEC3_Pos (29U)
\r
24000 #define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */
\r
24001 #define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */
\r
24002 #define HRTIM_ADC1R_AD1TEC4_Pos (30U)
\r
24003 #define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */
\r
24004 #define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */
\r
24005 #define HRTIM_ADC1R_AD1TEPER_Pos (31U)
\r
24006 #define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */
\r
24007 #define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E period */
\r
24009 /******************* Bit definition for HRTIM_ADC2R register ****************/
\r
24010 #define HRTIM_ADC2R_AD2MC1_Pos (0U)
\r
24011 #define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */
\r
24012 #define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */
\r
24013 #define HRTIM_ADC2R_AD2MC2_Pos (1U)
\r
24014 #define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */
\r
24015 #define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */
\r
24016 #define HRTIM_ADC2R_AD2MC3_Pos (2U)
\r
24017 #define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */
\r
24018 #define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */
\r
24019 #define HRTIM_ADC2R_AD2MC4_Pos (3U)
\r
24020 #define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */
\r
24021 #define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */
\r
24022 #define HRTIM_ADC2R_AD2MPER_Pos (4U)
\r
24023 #define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */
\r
24024 #define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */
\r
24025 #define HRTIM_ADC2R_AD2EEV6_Pos (5U)
\r
24026 #define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */
\r
24027 #define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */
\r
24028 #define HRTIM_ADC2R_AD2EEV7_Pos (6U)
\r
24029 #define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */
\r
24030 #define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */
\r
24031 #define HRTIM_ADC2R_AD2EEV8_Pos (7U)
\r
24032 #define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */
\r
24033 #define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */
\r
24034 #define HRTIM_ADC2R_AD2EEV9_Pos (8U)
\r
24035 #define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */
\r
24036 #define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */
\r
24037 #define HRTIM_ADC2R_AD2EEV10_Pos (9U)
\r
24038 #define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */
\r
24039 #define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */
\r
24040 #define HRTIM_ADC2R_AD2TAC2_Pos (10U)
\r
24041 #define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */
\r
24042 #define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */
\r
24043 #define HRTIM_ADC2R_AD2TAC3_Pos (11U)
\r
24044 #define HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos) /*!< 0x00000800 */
\r
24045 #define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk /*!< ADC Trigger 2 on Timer A compare 3 */
\r
24046 #define HRTIM_ADC2R_AD2TAC4_Pos (12U)
\r
24047 #define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */
\r
24048 #define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/
\r
24049 #define HRTIM_ADC2R_AD2TAPER_Pos (13U)
\r
24050 #define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */
\r
24051 #define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */
\r
24052 #define HRTIM_ADC2R_AD2TBC2_Pos (14U)
\r
24053 #define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */
\r
24054 #define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */
\r
24055 #define HRTIM_ADC2R_AD2TBC3_Pos (15U)
\r
24056 #define HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos) /*!< 0x00008000 */
\r
24057 #define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk /*!< ADC Trigger 2 on Timer B compare 3 */
\r
24058 #define HRTIM_ADC2R_AD2TBC4_Pos (16U)
\r
24059 #define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */
\r
24060 #define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */
\r
24061 #define HRTIM_ADC2R_AD2TBPER_Pos (17U)
\r
24062 #define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */
\r
24063 #define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */
\r
24064 #define HRTIM_ADC2R_AD2TCC2_Pos (18U)
\r
24065 #define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */
\r
24066 #define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */
\r
24067 #define HRTIM_ADC2R_AD2TCC3_Pos (19U)
\r
24068 #define HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos) /*!< 0x00080000 */
\r
24069 #define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk /*!< ADC Trigger 2 on Timer C compare 3 */
\r
24070 #define HRTIM_ADC2R_AD2TCC4_Pos (20U)
\r
24071 #define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */
\r
24072 #define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */
\r
24073 #define HRTIM_ADC2R_AD2TCPER_Pos (21U)
\r
24074 #define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */
\r
24075 #define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */
\r
24076 #define HRTIM_ADC2R_AD2TCRST_Pos (22U)
\r
24077 #define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */
\r
24078 #define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */
\r
24079 #define HRTIM_ADC2R_AD2TDC2_Pos (23U)
\r
24080 #define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */
\r
24081 #define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */
\r
24082 #define HRTIM_ADC2R_AD2TDC3_Pos (24U)
\r
24083 #define HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos) /*!< 0x01000000 */
\r
24084 #define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk /*!< ADC Trigger 2 on Timer D compare 3 */
\r
24085 #define HRTIM_ADC2R_AD2TDC4_Pos (25U)
\r
24086 #define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */
\r
24087 #define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/
\r
24088 #define HRTIM_ADC2R_AD2TDPER_Pos (26U)
\r
24089 #define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */
\r
24090 #define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */
\r
24091 #define HRTIM_ADC2R_AD2TDRST_Pos (27U)
\r
24092 #define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */
\r
24093 #define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */
\r
24094 #define HRTIM_ADC2R_AD2TEC2_Pos (28U)
\r
24095 #define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */
\r
24096 #define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */
\r
24097 #define HRTIM_ADC2R_AD2TEC3_Pos (29U)
\r
24098 #define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */
\r
24099 #define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */
\r
24100 #define HRTIM_ADC2R_AD2TEC4_Pos (30U)
\r
24101 #define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */
\r
24102 #define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */
\r
24103 #define HRTIM_ADC2R_AD2TERST_Pos (31U)
\r
24104 #define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */
\r
24105 #define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */
\r
24107 /******************* Bit definition for HRTIM_ADC3R register ****************/
\r
24108 #define HRTIM_ADC3R_AD3MC1_Pos (0U)
\r
24109 #define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */
\r
24110 #define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */
\r
24111 #define HRTIM_ADC3R_AD3MC2_Pos (1U)
\r
24112 #define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */
\r
24113 #define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */
\r
24114 #define HRTIM_ADC3R_AD3MC3_Pos (2U)
\r
24115 #define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */
\r
24116 #define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */
\r
24117 #define HRTIM_ADC3R_AD3MC4_Pos (3U)
\r
24118 #define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */
\r
24119 #define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */
\r
24120 #define HRTIM_ADC3R_AD3MPER_Pos (4U)
\r
24121 #define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */
\r
24122 #define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */
\r
24123 #define HRTIM_ADC3R_AD3EEV1_Pos (5U)
\r
24124 #define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */
\r
24125 #define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */
\r
24126 #define HRTIM_ADC3R_AD3EEV2_Pos (6U)
\r
24127 #define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */
\r
24128 #define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */
\r
24129 #define HRTIM_ADC3R_AD3EEV3_Pos (7U)
\r
24130 #define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */
\r
24131 #define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */
\r
24132 #define HRTIM_ADC3R_AD3EEV4_Pos (8U)
\r
24133 #define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */
\r
24134 #define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */
\r
24135 #define HRTIM_ADC3R_AD3EEV5_Pos (9U)
\r
24136 #define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */
\r
24137 #define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */
\r
24138 #define HRTIM_ADC3R_AD3TAC2_Pos (10U)
\r
24139 #define HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos) /*!< 0x00000400 */
\r
24140 #define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk /*!< ADC Trigger 3 on Timer A compare 2 */
\r
24141 #define HRTIM_ADC3R_AD3TAC3_Pos (11U)
\r
24142 #define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */
\r
24143 #define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */
\r
24144 #define HRTIM_ADC3R_AD3TAC4_Pos (12U)
\r
24145 #define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */
\r
24146 #define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */
\r
24147 #define HRTIM_ADC3R_AD3TAPER_Pos (13U)
\r
24148 #define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */
\r
24149 #define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */
\r
24150 #define HRTIM_ADC3R_AD3TARST_Pos (14U)
\r
24151 #define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */
\r
24152 #define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */
\r
24153 #define HRTIM_ADC3R_AD3TBC2_Pos (15U)
\r
24154 #define HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos) /*!< 0x00008000 */
\r
24155 #define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk /*!< ADC Trigger 3 on Timer B compare 2 */
\r
24156 #define HRTIM_ADC3R_AD3TBC3_Pos (16U)
\r
24157 #define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */
\r
24158 #define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */
\r
24159 #define HRTIM_ADC3R_AD3TBC4_Pos (17U)
\r
24160 #define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */
\r
24161 #define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */
\r
24162 #define HRTIM_ADC3R_AD3TBPER_Pos (18U)
\r
24163 #define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */
\r
24164 #define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */
\r
24165 #define HRTIM_ADC3R_AD3TBRST_Pos (19U)
\r
24166 #define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */
\r
24167 #define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */
\r
24168 #define HRTIM_ADC3R_AD3TCC2_Pos (20U)
\r
24169 #define HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos) /*!< 0x00100000 */
\r
24170 #define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk /*!< ADC Trigger 3 on Timer C compare 2 */
\r
24171 #define HRTIM_ADC3R_AD3TCC3_Pos (21U)
\r
24172 #define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */
\r
24173 #define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */
\r
24174 #define HRTIM_ADC3R_AD3TCC4_Pos (22U)
\r
24175 #define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */
\r
24176 #define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */
\r
24177 #define HRTIM_ADC3R_AD3TCPER_Pos (23U)
\r
24178 #define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */
\r
24179 #define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */
\r
24180 #define HRTIM_ADC3R_AD3TDC2_Pos (24U)
\r
24181 #define HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos) /*!< 0x01000000 */
\r
24182 #define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk /*!< ADC Trigger 3 on Timer D compare 2 */
\r
24183 #define HRTIM_ADC3R_AD3TDC3_Pos (25U)
\r
24184 #define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */
\r
24185 #define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */
\r
24186 #define HRTIM_ADC3R_AD3TDC4_Pos (26U)
\r
24187 #define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */
\r
24188 #define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */
\r
24189 #define HRTIM_ADC3R_AD3TDPER_Pos (27U)
\r
24190 #define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */
\r
24191 #define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */
\r
24192 #define HRTIM_ADC3R_AD3TEC2_Pos (28U)
\r
24193 #define HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos) /*!< 0x10000000 */
\r
24194 #define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk /*!< ADC Trigger 3 on Timer E compare 2 */
\r
24195 #define HRTIM_ADC3R_AD3TEC3_Pos (29U)
\r
24196 #define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */
\r
24197 #define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */
\r
24198 #define HRTIM_ADC3R_AD3TEC4_Pos (30U)
\r
24199 #define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */
\r
24200 #define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */
\r
24201 #define HRTIM_ADC3R_AD3TEPER_Pos (31U)
\r
24202 #define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */
\r
24203 #define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */
\r
24205 /******************* Bit definition for HRTIM_ADC4R register ****************/
\r
24206 #define HRTIM_ADC4R_AD4MC1_Pos (0U)
\r
24207 #define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */
\r
24208 #define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */
\r
24209 #define HRTIM_ADC4R_AD4MC2_Pos (1U)
\r
24210 #define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */
\r
24211 #define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */
\r
24212 #define HRTIM_ADC4R_AD4MC3_Pos (2U)
\r
24213 #define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */
\r
24214 #define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */
\r
24215 #define HRTIM_ADC4R_AD4MC4_Pos (3U)
\r
24216 #define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */
\r
24217 #define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */
\r
24218 #define HRTIM_ADC4R_AD4MPER_Pos (4U)
\r
24219 #define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */
\r
24220 #define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */
\r
24221 #define HRTIM_ADC4R_AD4EEV6_Pos (5U)
\r
24222 #define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */
\r
24223 #define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */
\r
24224 #define HRTIM_ADC4R_AD4EEV7_Pos (6U)
\r
24225 #define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */
\r
24226 #define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */
\r
24227 #define HRTIM_ADC4R_AD4EEV8_Pos (7U)
\r
24228 #define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */
\r
24229 #define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */
\r
24230 #define HRTIM_ADC4R_AD4EEV9_Pos (8U)
\r
24231 #define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */
\r
24232 #define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */
\r
24233 #define HRTIM_ADC4R_AD4EEV10_Pos (9U)
\r
24234 #define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */
\r
24235 #define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */
\r
24236 #define HRTIM_ADC4R_AD4TAC2_Pos (10U)
\r
24237 #define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */
\r
24238 #define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */
\r
24239 #define HRTIM_ADC4R_AD4TAC3_Pos (11U)
\r
24240 #define HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos) /*!< 0x00000800 */
\r
24241 #define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk /*!< ADC Trigger 4 on Timer A compare 3 */
\r
24242 #define HRTIM_ADC4R_AD4TAC4_Pos (12U)
\r
24243 #define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */
\r
24244 #define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/
\r
24245 #define HRTIM_ADC4R_AD4TAPER_Pos (13U)
\r
24246 #define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */
\r
24247 #define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */
\r
24248 #define HRTIM_ADC4R_AD4TBC2_Pos (14U)
\r
24249 #define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */
\r
24250 #define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */
\r
24251 #define HRTIM_ADC4R_AD4TBC3_Pos (15U)
\r
24252 #define HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos) /*!< 0x00008000 */
\r
24253 #define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk /*!< ADC Trigger 4 on Timer B compare 3 */
\r
24254 #define HRTIM_ADC4R_AD4TBC4_Pos (16U)
\r
24255 #define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */
\r
24256 #define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */
\r
24257 #define HRTIM_ADC4R_AD4TBPER_Pos (17U)
\r
24258 #define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */
\r
24259 #define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */
\r
24260 #define HRTIM_ADC4R_AD4TCC2_Pos (18U)
\r
24261 #define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */
\r
24262 #define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */
\r
24263 #define HRTIM_ADC4R_AD4TCC3_Pos (19U)
\r
24264 #define HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos) /*!< 0x00080000 */
\r
24265 #define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk /*!< ADC Trigger 4 on Timer C compare 3 */
\r
24266 #define HRTIM_ADC4R_AD4TCC4_Pos (20U)
\r
24267 #define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */
\r
24268 #define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */
\r
24269 #define HRTIM_ADC4R_AD4TCPER_Pos (21U)
\r
24270 #define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */
\r
24271 #define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */
\r
24272 #define HRTIM_ADC4R_AD4TCRST_Pos (22U)
\r
24273 #define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */
\r
24274 #define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */
\r
24275 #define HRTIM_ADC4R_AD4TDC2_Pos (23U)
\r
24276 #define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */
\r
24277 #define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */
\r
24278 #define HRTIM_ADC4R_AD4TDC3_Pos (24U)
\r
24279 #define HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos) /*!< 0x01000000 */
\r
24280 #define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk /*!< ADC Trigger 4 on Timer D compare 3 */
\r
24281 #define HRTIM_ADC4R_AD4TDC4_Pos (25U)
\r
24282 #define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */
\r
24283 #define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/
\r
24284 #define HRTIM_ADC4R_AD4TDPER_Pos (26U)
\r
24285 #define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */
\r
24286 #define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */
\r
24287 #define HRTIM_ADC4R_AD4TDRST_Pos (27U)
\r
24288 #define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */
\r
24289 #define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */
\r
24290 #define HRTIM_ADC4R_AD4TEC2_Pos (28U)
\r
24291 #define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */
\r
24292 #define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */
\r
24293 #define HRTIM_ADC4R_AD4TEC3_Pos (29U)
\r
24294 #define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */
\r
24295 #define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */
\r
24296 #define HRTIM_ADC4R_AD4TEC4_Pos (30U)
\r
24297 #define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */
\r
24298 #define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */
\r
24299 #define HRTIM_ADC4R_AD4TERST_Pos (31U)
\r
24300 #define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */
\r
24301 #define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */
\r
24303 /******************* Bit definition for HRTIM_FLTINR1 register ***************/
\r
24304 #define HRTIM_FLTINR1_FLT1E_Pos (0U)
\r
24305 #define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */
\r
24306 #define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */
\r
24307 #define HRTIM_FLTINR1_FLT1P_Pos (1U)
\r
24308 #define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */
\r
24309 #define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */
\r
24310 #define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
\r
24311 #define HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos) /*!< 0x00000004 */
\r
24312 #define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk /*!< Fault 1 source */
\r
24313 #define HRTIM_FLTINR1_FLT1F_Pos (3U)
\r
24314 #define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */
\r
24315 #define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */
\r
24316 #define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */
\r
24317 #define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */
\r
24318 #define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */
\r
24319 #define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */
\r
24320 #define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
\r
24321 #define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */
\r
24322 #define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */
\r
24324 #define HRTIM_FLTINR1_FLT2E_Pos (8U)
\r
24325 #define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */
\r
24326 #define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */
\r
24327 #define HRTIM_FLTINR1_FLT2P_Pos (9U)
\r
24328 #define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */
\r
24329 #define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */
\r
24330 #define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
\r
24331 #define HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos) /*!< 0x00000400 */
\r
24332 #define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk /*!< Fault 2 source */
\r
24333 #define HRTIM_FLTINR1_FLT2F_Pos (11U)
\r
24334 #define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */
\r
24335 #define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */
\r
24336 #define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */
\r
24337 #define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */
\r
24338 #define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */
\r
24339 #define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */
\r
24340 #define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
\r
24341 #define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */
\r
24342 #define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */
\r
24344 #define HRTIM_FLTINR1_FLT3E_Pos (16U)
\r
24345 #define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */
\r
24346 #define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */
\r
24347 #define HRTIM_FLTINR1_FLT3P_Pos (17U)
\r
24348 #define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */
\r
24349 #define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */
\r
24350 #define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
\r
24351 #define HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos) /*!< 0x00040000 */
\r
24352 #define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk /*!< Fault 3 source */
\r
24353 #define HRTIM_FLTINR1_FLT3F_Pos (19U)
\r
24354 #define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */
\r
24355 #define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */
\r
24356 #define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */
\r
24357 #define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */
\r
24358 #define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */
\r
24359 #define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */
\r
24360 #define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
\r
24361 #define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */
\r
24362 #define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */
\r
24364 #define HRTIM_FLTINR1_FLT4E_Pos (24U)
\r
24365 #define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */
\r
24366 #define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */
\r
24367 #define HRTIM_FLTINR1_FLT4P_Pos (25U)
\r
24368 #define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */
\r
24369 #define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */
\r
24370 #define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
\r
24371 #define HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos) /*!< 0x04000000 */
\r
24372 #define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk /*!< Fault 4 source */
\r
24373 #define HRTIM_FLTINR1_FLT4F_Pos (27U)
\r
24374 #define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */
\r
24375 #define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */
\r
24376 #define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */
\r
24377 #define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */
\r
24378 #define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */
\r
24379 #define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */
\r
24380 #define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
\r
24381 #define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */
\r
24382 #define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */
\r
24384 /******************* Bit definition for HRTIM_FLTINR2 register ***************/
\r
24385 #define HRTIM_FLTINR2_FLT5E_Pos (0U)
\r
24386 #define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */
\r
24387 #define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */
\r
24388 #define HRTIM_FLTINR2_FLT5P_Pos (1U)
\r
24389 #define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */
\r
24390 #define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */
\r
24391 #define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
\r
24392 #define HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos) /*!< 0x00000004 */
\r
24393 #define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk /*!< Fault 5 source */
\r
24394 #define HRTIM_FLTINR2_FLT5F_Pos (3U)
\r
24395 #define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */
\r
24396 #define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */
\r
24397 #define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */
\r
24398 #define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */
\r
24399 #define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */
\r
24400 #define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */
\r
24401 #define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
\r
24402 #define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */
\r
24403 #define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */
\r
24404 #define HRTIM_FLTINR2_FLTSD_Pos (24U)
\r
24405 #define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */
\r
24406 #define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */
\r
24407 #define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */
\r
24408 #define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */
\r
24410 /******************* Bit definition for HRTIM_BDMUPR register ***************/
\r
24411 #define HRTIM_BDMUPR_MCR_Pos (0U)
\r
24412 #define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */
\r
24413 #define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */
\r
24414 #define HRTIM_BDMUPR_MICR_Pos (1U)
\r
24415 #define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */
\r
24416 #define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */
\r
24417 #define HRTIM_BDMUPR_MDIER_Pos (2U)
\r
24418 #define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */
\r
24419 #define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */
\r
24420 #define HRTIM_BDMUPR_MCNT_Pos (3U)
\r
24421 #define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */
\r
24422 #define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */
\r
24423 #define HRTIM_BDMUPR_MPER_Pos (4U)
\r
24424 #define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */
\r
24425 #define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */
\r
24426 #define HRTIM_BDMUPR_MREP_Pos (5U)
\r
24427 #define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */
\r
24428 #define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */
\r
24429 #define HRTIM_BDMUPR_MCMP1_Pos (6U)
\r
24430 #define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */
\r
24431 #define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */
\r
24432 #define HRTIM_BDMUPR_MCMP2_Pos (7U)
\r
24433 #define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */
\r
24434 #define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */
\r
24435 #define HRTIM_BDMUPR_MCMP3_Pos (8U)
\r
24436 #define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */
\r
24437 #define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */
\r
24438 #define HRTIM_BDMUPR_MCMP4_Pos (9U)
\r
24439 #define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */
\r
24440 #define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */
\r
24442 /******************* Bit definition for HRTIM_BDTUPR register ***************/
\r
24443 #define HRTIM_BDTUPR_TIMCR_Pos (0U)
\r
24444 #define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */
\r
24445 #define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */
\r
24446 #define HRTIM_BDTUPR_TIMICR_Pos (1U)
\r
24447 #define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */
\r
24448 #define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */
\r
24449 #define HRTIM_BDTUPR_TIMDIER_Pos (2U)
\r
24450 #define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */
\r
24451 #define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */
\r
24452 #define HRTIM_BDTUPR_TIMCNT_Pos (3U)
\r
24453 #define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */
\r
24454 #define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */
\r
24455 #define HRTIM_BDTUPR_TIMPER_Pos (4U)
\r
24456 #define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */
\r
24457 #define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */
\r
24458 #define HRTIM_BDTUPR_TIMREP_Pos (5U)
\r
24459 #define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */
\r
24460 #define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */
\r
24461 #define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
\r
24462 #define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */
\r
24463 #define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */
\r
24464 #define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
\r
24465 #define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */
\r
24466 #define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */
\r
24467 #define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
\r
24468 #define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */
\r
24469 #define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */
\r
24470 #define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
\r
24471 #define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */
\r
24472 #define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */
\r
24473 #define HRTIM_BDTUPR_TIMDTR_Pos (10U)
\r
24474 #define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */
\r
24475 #define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */
\r
24476 #define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
\r
24477 #define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */
\r
24478 #define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */
\r
24479 #define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
\r
24480 #define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */
\r
24481 #define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */
\r
24482 #define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
\r
24483 #define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */
\r
24484 #define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */
\r
24485 #define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
\r
24486 #define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */
\r
24487 #define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */
\r
24488 #define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
\r
24489 #define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */
\r
24490 #define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */
\r
24491 #define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
\r
24492 #define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */
\r
24493 #define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */
\r
24494 #define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
\r
24495 #define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */
\r
24496 #define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */
\r
24497 #define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
\r
24498 #define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */
\r
24499 #define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */
\r
24500 #define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
\r
24501 #define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */
\r
24502 #define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */
\r
24503 #define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
\r
24504 #define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */
\r
24505 #define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */
\r
24507 /******************* Bit definition for HRTIM_BDMADR register ***************/
\r
24508 #define HRTIM_BDMADR_BDMADR_Pos (0U)
\r
24509 #define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
\r
24510 #define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */
\r
24512 /******************************************************************************/
\r
24514 /* RAM ECC monitoring */
\r
24516 /******************************************************************************/
\r
24517 /****************** Bit definition for RAMECC_IER register ******************/
\r
24518 #define RAMECC_IER_GECCDEBWIE_Pos (3U)
\r
24519 #define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */
\r
24520 #define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */
\r
24521 #define RAMECC_IER_GECCDEIE_Pos (2U)
\r
24522 #define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */
\r
24523 #define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */
\r
24524 #define RAMECC_IER_GECCSEIE_Pos (1U)
\r
24525 #define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */
\r
24526 #define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */
\r
24527 #define RAMECC_IER_GIE_Pos (0U)
\r
24528 #define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */
\r
24529 #define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */
\r
24531 /******************* Bit definition for RAMECC_CR register ******************/
\r
24532 #define RAMECC_CR_ECCELEN_Pos (5U)
\r
24533 #define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */
\r
24534 #define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */
\r
24535 #define RAMECC_CR_ECCDEBWIE_Pos (4U)
\r
24536 #define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */
\r
24537 #define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */
\r
24538 #define RAMECC_CR_ECCDEIE_Pos (3U)
\r
24539 #define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */
\r
24540 #define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */
\r
24541 #define RAMECC_CR_ECCSEIE_Pos (2U)
\r
24542 #define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */
\r
24543 #define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */
\r
24545 /******************* Bit definition for RAMECC_SR register ******************/
\r
24546 #define RAMECC_SR_DEBWDF_Pos (2U)
\r
24547 #define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */
\r
24548 #define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */
\r
24549 #define RAMECC_SR_DEDF_Pos (1U)
\r
24550 #define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */
\r
24551 #define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */
\r
24552 #define RAMECC_SR_SEDCF_Pos (0U)
\r
24553 #define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */
\r
24554 #define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */
\r
24556 /****************** Bit definition for RAMECC_FAR register ******************/
\r
24557 #define RAMECC_FAR_FADD_Pos (0U)
\r
24558 #define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */
\r
24559 #define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */
\r
24561 /****************** Bit definition for RAMECC_FDRL register *****************/
\r
24562 #define RAMECC_FAR_FDATAL_Pos (0U)
\r
24563 #define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
\r
24564 #define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk /*!< ECC error failing address */
\r
24566 /****************** Bit definition for RAMECC_FDRH register *****************/
\r
24567 #define RAMECC_FAR_FDATAH_Pos (0U)
\r
24568 #define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
\r
24569 #define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
\r
24571 /***************** Bit definition for RAMECC_FECR register ******************/
\r
24572 #define RAMECC_FECR_FEC_Pos (0U)
\r
24573 #define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */
\r
24574 #define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */
\r
24576 /******************************************************************************/
\r
24580 /******************************************************************************/
\r
24581 /******************** Bit definition for MDIOS_CR register *******************/
\r
24582 #define MDIOS_CR_EN_Pos (0U)
\r
24583 #define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
\r
24584 #define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
\r
24585 #define MDIOS_CR_WRIE_Pos (1U)
\r
24586 #define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
\r
24587 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
\r
24588 #define MDIOS_CR_RDIE_Pos (2U)
\r
24589 #define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
\r
24590 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
\r
24591 #define MDIOS_CR_EIE_Pos (3U)
\r
24592 #define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
\r
24593 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
\r
24594 #define MDIOS_CR_DPC_Pos (7U)
\r
24595 #define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
\r
24596 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
\r
24597 #define MDIOS_CR_PORT_ADDRESS_Pos (8U)
\r
24598 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
\r
24599 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
\r
24600 #define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
\r
24601 #define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
\r
24602 #define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
\r
24603 #define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
\r
24604 #define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
\r
24606 /******************** Bit definition for MDIOS_SR register *******************/
\r
24607 #define MDIOS_SR_PERF_Pos (0U)
\r
24608 #define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
\r
24609 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
\r
24610 #define MDIOS_SR_SERF_Pos (1U)
\r
24611 #define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
\r
24612 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
\r
24613 #define MDIOS_SR_TERF_Pos (2U)
\r
24614 #define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
\r
24615 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
\r
24617 /******************** Bit definition for MDIOS_CLRFR register *******************/
\r
24618 #define MDIOS_SR_CPERF_Pos (0U)
\r
24619 #define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
\r
24620 #define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
\r
24621 #define MDIOS_SR_CSERF_Pos (1U)
\r
24622 #define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
\r
24623 #define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
\r
24624 #define MDIOS_SR_CTERF_Pos (2U)
\r
24625 #define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
\r
24626 #define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
\r
24628 /******************************************************************************/
\r
24632 /******************************************************************************/
\r
24633 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
\r
24634 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
\r
24635 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
\r
24636 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
\r
24637 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
\r
24638 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
\r
24639 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
\r
24640 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
\r
24641 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
\r
24642 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
\r
24643 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
\r
24644 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
\r
24645 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
\r
24646 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
\r
24647 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
\r
24648 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
\r
24649 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
\r
24650 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
\r
24651 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
\r
24652 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
\r
24653 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
\r
24654 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
\r
24655 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
\r
24656 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
\r
24657 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
\r
24658 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
\r
24659 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
\r
24660 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
\r
24661 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
\r
24662 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
\r
24663 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
\r
24664 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
\r
24665 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
\r
24666 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
\r
24667 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
\r
24668 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
\r
24669 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
\r
24670 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
\r
24671 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
\r
24672 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
\r
24673 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
\r
24674 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
\r
24675 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
\r
24676 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
\r
24677 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
\r
24678 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
\r
24679 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
\r
24680 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
\r
24681 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
\r
24682 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
\r
24683 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
\r
24684 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
\r
24685 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
\r
24686 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
\r
24687 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
\r
24689 /******************** Bit definition forUSB_OTG_HCFG register ********************/
\r
24691 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
\r
24692 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
\r
24693 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
\r
24694 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
\r
24695 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
\r
24696 #define USB_OTG_HCFG_FSLSS_Pos (2U)
\r
24697 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
\r
24698 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
\r
24700 /******************** Bit definition forUSB_OTG_DCFG register ********************/
\r
24702 #define USB_OTG_DCFG_DSPD_Pos (0U)
\r
24703 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
\r
24704 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
\r
24705 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
\r
24706 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
\r
24707 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
\r
24708 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
\r
24709 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
\r
24711 #define USB_OTG_DCFG_DAD_Pos (4U)
\r
24712 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
\r
24713 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
\r
24714 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
\r
24715 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
\r
24716 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
\r
24717 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
\r
24718 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
\r
24719 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
\r
24720 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
\r
24722 #define USB_OTG_DCFG_PFIVL_Pos (11U)
\r
24723 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
\r
24724 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
\r
24725 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
\r
24726 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
\r
24728 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
\r
24729 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
\r
24730 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
\r
24731 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
\r
24732 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
\r
24734 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
\r
24735 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
\r
24736 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
\r
24737 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
\r
24738 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
\r
24739 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
\r
24740 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
\r
24741 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
\r
24742 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
\r
24743 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
\r
24745 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
\r
24746 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
\r
24747 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
\r
24748 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
\r
24749 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
\r
24750 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
\r
24751 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
\r
24752 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
\r
24753 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
\r
24754 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
\r
24755 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
\r
24756 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
\r
24757 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
\r
24758 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
\r
24759 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
\r
24760 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
\r
24761 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
\r
24762 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
\r
24763 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
\r
24765 /******************** Bit definition forUSB_OTG_DCTL register ********************/
\r
24766 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
\r
24767 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
\r
24768 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
\r
24769 #define USB_OTG_DCTL_SDIS_Pos (1U)
\r
24770 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
\r
24771 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
\r
24772 #define USB_OTG_DCTL_GINSTS_Pos (2U)
\r
24773 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
\r
24774 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
\r
24775 #define USB_OTG_DCTL_GONSTS_Pos (3U)
\r
24776 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
\r
24777 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
\r
24779 #define USB_OTG_DCTL_TCTL_Pos (4U)
\r
24780 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
\r
24781 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
\r
24782 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
\r
24783 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
\r
24784 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
\r
24785 #define USB_OTG_DCTL_SGINAK_Pos (7U)
\r
24786 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
\r
24787 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
\r
24788 #define USB_OTG_DCTL_CGINAK_Pos (8U)
\r
24789 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
\r
24790 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
\r
24791 #define USB_OTG_DCTL_SGONAK_Pos (9U)
\r
24792 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
\r
24793 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
\r
24794 #define USB_OTG_DCTL_CGONAK_Pos (10U)
\r
24795 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
\r
24796 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
\r
24797 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
\r
24798 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
\r
24799 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
\r
24801 /******************** Bit definition forUSB_OTG_HFIR register ********************/
\r
24802 #define USB_OTG_HFIR_FRIVL_Pos (0U)
\r
24803 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
\r
24804 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
\r
24806 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
\r
24807 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
\r
24808 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
\r
24809 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
\r
24810 #define USB_OTG_HFNUM_FTREM_Pos (16U)
\r
24811 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
\r
24812 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
\r
24814 /******************** Bit definition forUSB_OTG_DSTS register ********************/
\r
24815 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
\r
24816 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
\r
24817 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
\r
24819 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
\r
24820 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
\r
24821 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
\r
24822 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
\r
24823 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
\r
24824 #define USB_OTG_DSTS_EERR_Pos (3U)
\r
24825 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
\r
24826 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
\r
24827 #define USB_OTG_DSTS_FNSOF_Pos (8U)
\r
24828 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
\r
24829 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
\r
24831 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
\r
24832 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
\r
24833 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
\r
24834 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
\r
24836 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
\r
24837 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
\r
24838 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
\r
24839 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
\r
24840 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
\r
24841 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
\r
24842 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
\r
24843 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
\r
24844 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
\r
24845 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
\r
24846 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
\r
24847 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
\r
24848 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
\r
24849 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
\r
24850 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
\r
24851 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
\r
24853 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
\r
24855 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
\r
24856 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
\r
24857 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
\r
24858 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
\r
24859 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
\r
24860 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
\r
24861 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
\r
24862 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
\r
24863 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
\r
24864 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
\r
24865 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
\r
24866 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
\r
24867 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
\r
24868 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
\r
24869 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
\r
24871 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
\r
24872 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
\r
24873 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
\r
24874 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
\r
24875 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
\r
24876 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
\r
24877 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
\r
24878 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
\r
24879 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
\r
24880 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
\r
24881 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
\r
24882 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
\r
24883 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
\r
24884 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
\r
24885 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
\r
24886 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
\r
24887 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
\r
24888 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
\r
24889 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
\r
24890 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
\r
24891 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
\r
24892 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
\r
24893 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
\r
24894 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
\r
24895 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
\r
24896 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
\r
24897 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
\r
24898 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
\r
24899 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
\r
24900 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
\r
24901 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
\r
24902 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
\r
24903 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
\r
24904 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
\r
24905 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
\r
24906 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
\r
24907 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
\r
24908 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
\r
24909 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
\r
24910 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
\r
24911 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
\r
24912 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
\r
24913 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
\r
24914 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
\r
24915 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
\r
24916 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
\r
24918 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
\r
24919 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
\r
24920 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
\r
24921 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
\r
24922 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
\r
24923 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
\r
24924 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
\r
24925 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
\r
24926 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
\r
24927 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
\r
24928 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
\r
24929 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
\r
24930 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
\r
24931 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
\r
24932 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
\r
24933 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
\r
24935 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
\r
24936 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
\r
24937 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
\r
24938 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
\r
24939 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
\r
24940 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
\r
24941 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
\r
24942 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
\r
24943 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
\r
24944 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
\r
24945 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
\r
24946 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
\r
24947 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
\r
24948 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
\r
24950 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
\r
24951 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
\r
24952 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
\r
24953 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
\r
24954 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
\r
24955 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
\r
24956 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
\r
24957 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
\r
24958 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
\r
24959 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
\r
24960 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
\r
24961 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
\r
24962 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
\r
24963 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
\r
24964 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
\r
24965 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
\r
24966 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
\r
24967 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
\r
24968 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
\r
24969 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
\r
24970 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
\r
24971 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
\r
24972 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
\r
24973 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
\r
24974 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
\r
24976 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
\r
24977 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
\r
24978 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
\r
24979 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
\r
24981 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
\r
24982 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
\r
24983 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
\r
24984 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
\r
24985 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
\r
24986 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
\r
24987 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
\r
24988 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
\r
24989 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
\r
24990 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
\r
24991 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
\r
24993 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
\r
24994 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
\r
24995 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
\r
24996 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
\r
24997 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
\r
24998 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
\r
24999 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
\r
25000 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
\r
25001 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
\r
25002 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
\r
25003 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
\r
25005 /******************** Bit definition forUSB_OTG_HAINT register ********************/
\r
25006 #define USB_OTG_HAINT_HAINT_Pos (0U)
\r
25007 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
\r
25008 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
\r
25010 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
\r
25011 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
\r
25012 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
\r
25013 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
\r
25014 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
\r
25015 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
\r
25016 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
\r
25017 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
\r
25018 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
\r
25019 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
\r
25020 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
\r
25021 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
\r
25022 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
\r
25023 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
\r
25024 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
\r
25025 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
\r
25026 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
\r
25027 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
\r
25028 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
\r
25029 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
\r
25030 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
\r
25031 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
\r
25032 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
\r
25033 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
\r
25034 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
\r
25036 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
\r
25037 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
\r
25038 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
\r
25039 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
\r
25040 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
\r
25041 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
\r
25042 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
\r
25043 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
\r
25044 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
\r
25045 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
\r
25046 #define USB_OTG_GINTSTS_SOF_Pos (3U)
\r
25047 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
\r
25048 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
\r
25049 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
\r
25050 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
\r
25051 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
\r
25052 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
\r
25053 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
\r
25054 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
\r
25055 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
\r
25056 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
\r
25057 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
\r
25058 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
\r
25059 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
\r
25060 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
\r
25061 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
\r
25062 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
\r
25063 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
\r
25064 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
\r
25065 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
\r
25066 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
\r
25067 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
\r
25068 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
\r
25069 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
\r
25070 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
\r
25071 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
\r
25072 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
\r
25073 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
\r
25074 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
\r
25075 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
\r
25076 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
\r
25077 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
\r
25078 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
\r
25079 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
\r
25080 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
\r
25081 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
\r
25082 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
\r
25083 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
\r
25084 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
\r
25085 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
\r
25086 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
\r
25087 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
\r
25088 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
\r
25089 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
\r
25090 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
\r
25091 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
\r
25092 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
\r
25093 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
\r
25094 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
\r
25095 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
\r
25096 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
\r
25097 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
\r
25098 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
\r
25099 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
\r
25100 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
\r
25101 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
\r
25102 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
\r
25103 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
\r
25104 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
\r
25105 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
\r
25106 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
\r
25107 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
\r
25108 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
\r
25109 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
\r
25110 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
\r
25111 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
\r
25112 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
\r
25113 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
\r
25114 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
\r
25115 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
\r
25116 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
\r
25117 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
\r
25118 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
\r
25119 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
\r
25120 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
\r
25122 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
\r
25123 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
\r
25124 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
\r
25125 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
\r
25126 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
\r
25127 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
\r
25128 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
\r
25129 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
\r
25130 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
\r
25131 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
\r
25132 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
\r
25133 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
\r
25134 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
\r
25135 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
\r
25136 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
\r
25137 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
\r
25138 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
\r
25139 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
\r
25140 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
\r
25141 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
\r
25142 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
\r
25143 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
\r
25144 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
\r
25145 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
\r
25146 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
\r
25147 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
\r
25148 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
\r
25149 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
\r
25150 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
\r
25151 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
\r
25152 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
\r
25153 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
\r
25154 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
\r
25155 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
\r
25156 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
\r
25157 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
\r
25158 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
\r
25159 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
\r
25160 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
\r
25161 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
\r
25162 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
\r
25163 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
\r
25164 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
\r
25165 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
\r
25166 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
\r
25167 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
\r
25168 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
\r
25169 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
\r
25170 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
\r
25171 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
\r
25172 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
\r
25173 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
\r
25174 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
\r
25175 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
\r
25176 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
\r
25177 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
\r
25178 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
\r
25179 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
\r
25180 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
\r
25181 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
\r
25182 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
\r
25183 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
\r
25184 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
\r
25185 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
\r
25186 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
\r
25187 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
\r
25188 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
\r
25189 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
\r
25190 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
\r
25191 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
\r
25192 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
\r
25193 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
\r
25194 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
\r
25195 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
\r
25196 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
\r
25197 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
\r
25198 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
\r
25199 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
\r
25200 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
\r
25201 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
\r
25202 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
\r
25203 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
\r
25204 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
\r
25205 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
\r
25206 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
\r
25208 /******************** Bit definition forUSB_OTG_DAINT register ********************/
\r
25209 #define USB_OTG_DAINT_IEPINT_Pos (0U)
\r
25210 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
\r
25211 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
\r
25212 #define USB_OTG_DAINT_OEPINT_Pos (16U)
\r
25213 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
\r
25214 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
\r
25216 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
\r
25217 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
\r
25218 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
\r
25219 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
\r
25221 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
\r
25222 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
\r
25223 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
\r
25224 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
\r
25225 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
\r
25226 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
\r
25227 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
\r
25228 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
\r
25229 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
\r
25230 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
\r
25231 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
\r
25232 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
\r
25233 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
\r
25235 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
\r
25236 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
\r
25237 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
\r
25238 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
\r
25239 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
\r
25240 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
\r
25241 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
\r
25243 /******************** Bit definition for OTG register ********************/
\r
25245 #define USB_OTG_CHNUM_Pos (0U)
\r
25246 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
\r
25247 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
\r
25248 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
\r
25249 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
\r
25250 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
\r
25251 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
\r
25252 #define USB_OTG_BCNT_Pos (4U)
\r
25253 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
\r
25254 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
\r
25256 #define USB_OTG_DPID_Pos (15U)
\r
25257 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
\r
25258 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
\r
25259 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
\r
25260 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
\r
25262 #define USB_OTG_PKTSTS_Pos (17U)
\r
25263 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
\r
25264 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
\r
25265 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
\r
25266 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
\r
25267 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
\r
25268 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
\r
25270 #define USB_OTG_EPNUM_Pos (0U)
\r
25271 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
\r
25272 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
\r
25273 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
\r
25274 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
\r
25275 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
\r
25276 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
\r
25278 #define USB_OTG_FRMNUM_Pos (21U)
\r
25279 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
\r
25280 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
\r
25281 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
\r
25282 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
\r
25283 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
\r
25284 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
\r
25286 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
\r
25287 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
\r
25288 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
\r
25289 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
\r
25291 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
\r
25292 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
\r
25293 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
\r
25294 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
\r
25296 /******************** Bit definition for OTG register ********************/
\r
25297 #define USB_OTG_NPTXFSA_Pos (0U)
\r
25298 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
\r
25299 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
\r
25300 #define USB_OTG_NPTXFD_Pos (16U)
\r
25301 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
\r
25302 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
\r
25303 #define USB_OTG_TX0FSA_Pos (0U)
\r
25304 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
\r
25305 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
\r
25306 #define USB_OTG_TX0FD_Pos (16U)
\r
25307 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
\r
25308 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
\r
25310 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
\r
25311 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
\r
25312 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
\r
25313 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
\r
25315 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
\r
25316 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
\r
25317 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
\r
25318 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
\r
25320 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
\r
25321 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
\r
25322 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
\r
25323 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
\r
25324 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
\r
25325 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
\r
25326 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
\r
25327 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
\r
25328 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
\r
25329 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
\r
25330 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
\r
25332 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
\r
25333 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
\r
25334 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
\r
25335 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
\r
25336 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
\r
25337 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
\r
25338 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
\r
25339 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
\r
25340 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
\r
25341 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
\r
25343 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
\r
25344 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
\r
25345 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
\r
25346 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
\r
25347 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
\r
25348 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
\r
25349 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
\r
25351 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
\r
25352 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
\r
25353 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
\r
25354 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
\r
25355 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
\r
25356 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
\r
25357 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
\r
25358 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
\r
25359 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
\r
25360 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
\r
25361 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
\r
25362 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
\r
25363 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
\r
25364 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
\r
25365 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
\r
25367 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
\r
25368 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
\r
25369 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
\r
25370 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
\r
25371 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
\r
25372 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
\r
25373 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
\r
25374 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
\r
25375 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
\r
25376 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
\r
25377 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
\r
25378 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
\r
25379 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
\r
25380 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
\r
25381 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
\r
25383 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
\r
25384 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
\r
25385 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
\r
25386 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
\r
25388 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
\r
25389 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
\r
25390 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
\r
25391 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
\r
25392 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
\r
25393 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
\r
25394 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
\r
25396 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
\r
25397 #define USB_OTG_GCCFG_DCDET_Pos (0U)
\r
25398 #define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
\r
25399 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
\r
25400 #define USB_OTG_GCCFG_PDET_Pos (1U)
\r
25401 #define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
\r
25402 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
\r
25403 #define USB_OTG_GCCFG_SDET_Pos (2U)
\r
25404 #define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
\r
25405 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
\r
25406 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
\r
25407 #define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
\r
25408 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
\r
25409 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
\r
25410 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
\r
25411 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
\r
25412 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
\r
25413 #define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
\r
25414 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
\r
25415 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
\r
25416 #define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
\r
25417 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
\r
25418 #define USB_OTG_GCCFG_PDEN_Pos (19U)
\r
25419 #define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
\r
25420 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
\r
25421 #define USB_OTG_GCCFG_SDEN_Pos (20U)
\r
25422 #define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
\r
25423 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
\r
25424 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
\r
25425 #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
\r
25426 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
\r
25428 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
\r
25429 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
\r
25430 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
\r
25431 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
\r
25432 #define USB_OTG_GPWRDN_ADPIF_Pos (23U)
\r
25433 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
\r
25434 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
\r
25436 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
\r
25437 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
\r
25438 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
\r
25439 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
\r
25440 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
\r
25441 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
\r
25442 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
\r
25444 /******************** Bit definition forUSB_OTG_CID register ********************/
\r
25445 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
\r
25446 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
\r
25447 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
\r
25449 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
\r
25450 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
\r
25451 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
\r
25452 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
\r
25453 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
\r
25454 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
\r
25455 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
\r
25456 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
\r
25457 #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
\r
25458 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
\r
25459 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
\r
25460 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
\r
25461 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
\r
25462 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
\r
25463 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
\r
25464 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
\r
25465 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
\r
25466 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
\r
25467 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
\r
25468 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
\r
25469 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
\r
25470 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
\r
25471 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
\r
25472 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
\r
25473 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
\r
25474 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
\r
25475 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
\r
25476 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
\r
25477 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
\r
25478 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
\r
25479 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
\r
25480 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
\r
25481 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
\r
25482 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
\r
25483 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
\r
25484 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
\r
25485 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
\r
25486 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
\r
25487 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
\r
25488 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
\r
25489 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
\r
25490 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
\r
25491 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
\r
25492 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
\r
25493 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
\r
25494 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
\r
25496 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
\r
25497 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
\r
25498 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
\r
25499 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
\r
25500 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
\r
25501 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
\r
25502 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
\r
25503 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
\r
25504 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
\r
25505 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
\r
25506 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
\r
25507 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
\r
25508 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
\r
25509 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
\r
25510 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
\r
25511 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
\r
25512 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
\r
25513 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
\r
25514 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
\r
25515 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
\r
25516 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
\r
25517 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
\r
25518 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
\r
25519 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
\r
25520 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
\r
25521 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
\r
25522 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
\r
25523 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
\r
25525 /******************** Bit definition forUSB_OTG_HPRT register ********************/
\r
25526 #define USB_OTG_HPRT_PCSTS_Pos (0U)
\r
25527 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
\r
25528 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
\r
25529 #define USB_OTG_HPRT_PCDET_Pos (1U)
\r
25530 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
\r
25531 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
\r
25532 #define USB_OTG_HPRT_PENA_Pos (2U)
\r
25533 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
\r
25534 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
\r
25535 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
\r
25536 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
\r
25537 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
\r
25538 #define USB_OTG_HPRT_POCA_Pos (4U)
\r
25539 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
\r
25540 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
\r
25541 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
\r
25542 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
\r
25543 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
\r
25544 #define USB_OTG_HPRT_PRES_Pos (6U)
\r
25545 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
\r
25546 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
\r
25547 #define USB_OTG_HPRT_PSUSP_Pos (7U)
\r
25548 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
\r
25549 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
\r
25550 #define USB_OTG_HPRT_PRST_Pos (8U)
\r
25551 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
\r
25552 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
\r
25554 #define USB_OTG_HPRT_PLSTS_Pos (10U)
\r
25555 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
\r
25556 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
\r
25557 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
\r
25558 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
\r
25559 #define USB_OTG_HPRT_PPWR_Pos (12U)
\r
25560 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
\r
25561 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
\r
25563 #define USB_OTG_HPRT_PTCTL_Pos (13U)
\r
25564 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
\r
25565 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
\r
25566 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
\r
25567 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
\r
25568 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
\r
25569 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
\r
25571 #define USB_OTG_HPRT_PSPD_Pos (17U)
\r
25572 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
\r
25573 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
\r
25574 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
\r
25575 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
\r
25577 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
\r
25578 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
\r
25579 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
\r
25580 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
\r
25581 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
\r
25582 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
\r
25583 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
\r
25584 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
\r
25585 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
\r
25586 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
\r
25587 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
\r
25588 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
\r
25589 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
\r
25590 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
\r
25591 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
\r
25592 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
\r
25593 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
\r
25594 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
\r
25595 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
\r
25596 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
\r
25597 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
\r
25598 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
\r
25599 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
\r
25600 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
\r
25601 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
\r
25602 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
\r
25603 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
\r
25604 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
\r
25605 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
\r
25606 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
\r
25607 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
\r
25608 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
\r
25609 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
\r
25610 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
\r
25612 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
\r
25613 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
\r
25614 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
\r
25615 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
\r
25616 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
\r
25617 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
\r
25618 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
\r
25620 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
\r
25621 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
\r
25622 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
\r
25623 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
\r
25624 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
\r
25625 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
\r
25626 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
\r
25627 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
\r
25628 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
\r
25629 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
\r
25630 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
\r
25631 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
\r
25632 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
\r
25634 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
\r
25635 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
\r
25636 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
\r
25637 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
\r
25638 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
\r
25639 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
\r
25640 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
\r
25641 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
\r
25643 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
\r
25644 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
\r
25645 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
\r
25646 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
\r
25647 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
\r
25648 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
\r
25649 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
\r
25650 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
\r
25651 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
\r
25652 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
\r
25653 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
\r
25654 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
\r
25655 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
\r
25656 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
\r
25657 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
\r
25658 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
\r
25659 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
\r
25660 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
\r
25661 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
\r
25662 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
\r
25663 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
\r
25664 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
\r
25665 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
\r
25666 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
\r
25667 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
\r
25669 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
\r
25670 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
\r
25671 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
\r
25672 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
\r
25674 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
\r
25675 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
\r
25676 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
\r
25677 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
\r
25678 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
\r
25679 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
\r
25680 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
\r
25681 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
\r
25682 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
\r
25683 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
\r
25684 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
\r
25685 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
\r
25686 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
\r
25688 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
\r
25689 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
\r
25690 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
\r
25691 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
\r
25692 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
\r
25694 #define USB_OTG_HCCHAR_MC_Pos (20U)
\r
25695 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
\r
25696 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
\r
25697 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
\r
25698 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
\r
25700 #define USB_OTG_HCCHAR_DAD_Pos (22U)
\r
25701 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
\r
25702 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
\r
25703 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
\r
25704 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
\r
25705 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
\r
25706 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
\r
25707 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
\r
25708 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
\r
25709 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
\r
25710 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
\r
25711 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
\r
25712 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
\r
25713 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
\r
25714 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
\r
25715 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
\r
25716 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
\r
25717 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
\r
25718 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
\r
25720 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
\r
25722 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
\r
25723 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
\r
25724 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
\r
25725 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
\r
25726 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
\r
25727 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
\r
25728 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
\r
25729 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
\r
25730 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
\r
25731 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
\r
25733 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
\r
25734 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
\r
25735 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
\r
25736 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
\r
25737 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
\r
25738 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
\r
25739 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
\r
25740 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
\r
25741 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
\r
25742 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
\r
25744 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
\r
25745 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
\r
25746 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
\r
25747 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
\r
25748 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
\r
25749 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
\r
25750 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
\r
25751 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
\r
25752 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
\r
25753 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
\r
25754 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
\r
25756 /******************** Bit definition forUSB_OTG_HCINT register ********************/
\r
25757 #define USB_OTG_HCINT_XFRC_Pos (0U)
\r
25758 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
\r
25759 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
\r
25760 #define USB_OTG_HCINT_CHH_Pos (1U)
\r
25761 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
\r
25762 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
\r
25763 #define USB_OTG_HCINT_AHBERR_Pos (2U)
\r
25764 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
\r
25765 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
\r
25766 #define USB_OTG_HCINT_STALL_Pos (3U)
\r
25767 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
\r
25768 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
\r
25769 #define USB_OTG_HCINT_NAK_Pos (4U)
\r
25770 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
\r
25771 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
\r
25772 #define USB_OTG_HCINT_ACK_Pos (5U)
\r
25773 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
\r
25774 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
\r
25775 #define USB_OTG_HCINT_NYET_Pos (6U)
\r
25776 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
\r
25777 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
\r
25778 #define USB_OTG_HCINT_TXERR_Pos (7U)
\r
25779 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
\r
25780 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
\r
25781 #define USB_OTG_HCINT_BBERR_Pos (8U)
\r
25782 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
\r
25783 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
\r
25784 #define USB_OTG_HCINT_FRMOR_Pos (9U)
\r
25785 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
\r
25786 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
\r
25787 #define USB_OTG_HCINT_DTERR_Pos (10U)
\r
25788 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
\r
25789 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
\r
25791 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
\r
25792 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
\r
25793 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
\r
25794 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
\r
25795 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
\r
25796 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
\r
25797 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
\r
25798 #define USB_OTG_DIEPINT_TOC_Pos (3U)
\r
25799 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
\r
25800 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
\r
25801 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
\r
25802 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
\r
25803 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
\r
25804 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
\r
25805 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
\r
25806 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
\r
25807 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
\r
25808 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
\r
25809 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
\r
25810 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
\r
25811 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
\r
25812 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
\r
25813 #define USB_OTG_DIEPINT_BNA_Pos (9U)
\r
25814 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
\r
25815 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
\r
25816 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
\r
25817 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
\r
25818 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
\r
25819 #define USB_OTG_DIEPINT_BERR_Pos (12U)
\r
25820 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
\r
25821 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
\r
25822 #define USB_OTG_DIEPINT_NAK_Pos (13U)
\r
25823 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
\r
25824 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
\r
25826 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
\r
25827 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
\r
25828 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
\r
25829 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
\r
25830 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
\r
25831 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
\r
25832 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
\r
25833 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
\r
25834 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
\r
25835 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
\r
25836 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
\r
25837 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
\r
25838 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
\r
25839 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
\r
25840 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
\r
25841 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
\r
25842 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
\r
25843 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
\r
25844 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
\r
25845 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
\r
25846 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
\r
25847 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
\r
25848 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
\r
25849 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
\r
25850 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
\r
25851 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
\r
25852 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
\r
25853 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
\r
25854 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
\r
25855 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
\r
25856 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
\r
25857 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
\r
25858 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
\r
25859 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
\r
25861 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
\r
25863 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
\r
25864 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
\r
25865 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
\r
25866 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
\r
25867 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
\r
25868 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
\r
25869 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
\r
25870 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
\r
25871 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
\r
25872 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
\r
25873 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
\r
25874 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
\r
25875 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
\r
25876 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
\r
25877 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
\r
25878 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
\r
25879 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
\r
25880 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
\r
25881 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
\r
25882 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
\r
25883 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
\r
25884 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
\r
25885 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
\r
25886 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
\r
25888 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
\r
25889 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
\r
25890 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
\r
25891 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
\r
25893 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
\r
25894 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
\r
25895 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
\r
25896 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
\r
25898 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
\r
25899 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
\r
25900 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
\r
25901 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
\r
25903 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
\r
25904 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
\r
25905 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
\r
25906 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
\r
25907 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
\r
25908 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
\r
25909 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
\r
25911 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
\r
25913 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
\r
25914 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
\r
25915 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
\r
25916 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
\r
25917 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
\r
25918 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
\r
25919 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
\r
25920 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
\r
25921 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
\r
25922 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
\r
25923 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
\r
25924 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
\r
25925 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
\r
25926 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
\r
25927 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
\r
25928 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
\r
25929 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
\r
25930 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
\r
25931 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
\r
25932 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
\r
25933 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
\r
25934 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
\r
25935 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
\r
25936 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
\r
25937 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
\r
25938 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
\r
25939 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
\r
25940 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
\r
25941 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
\r
25942 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
\r
25943 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
\r
25944 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
\r
25945 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
\r
25946 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
\r
25947 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
\r
25948 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
\r
25949 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
\r
25950 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
\r
25952 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
\r
25953 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
\r
25954 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
\r
25955 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
\r
25956 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
\r
25957 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
\r
25958 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
\r
25959 #define USB_OTG_DOEPINT_STUP_Pos (3U)
\r
25960 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
\r
25961 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
\r
25962 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
\r
25963 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
\r
25964 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
\r
25965 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
\r
25966 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
\r
25967 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
\r
25968 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
\r
25969 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
\r
25970 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
\r
25971 #define USB_OTG_DOEPINT_NYET_Pos (14U)
\r
25972 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
\r
25973 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
\r
25975 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
\r
25977 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
\r
25978 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
\r
25979 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
\r
25980 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
\r
25981 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
\r
25982 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
\r
25984 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
\r
25985 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
\r
25986 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
\r
25987 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
\r
25988 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
\r
25990 /******************** Bit definition for PCGCCTL register ********************/
\r
25991 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
\r
25992 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
\r
25993 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
\r
25994 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
\r
25995 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
\r
25996 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
\r
25997 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
\r
25998 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
\r
25999 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
\r
26009 /** @addtogroup Exported_macros
\r
26013 /******************************* ADC Instances ********************************/
\r
26014 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
\r
26015 ((INSTANCE) == ADC2) || \
\r
26016 ((INSTANCE) == ADC3))
\r
26018 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
\r
26020 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
\r
26021 ((INSTANCE) == ADC3_COMMON))
\r
26023 /******************************** COMP Instances ******************************/
\r
26024 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
\r
26025 ((INSTANCE) == COMP2))
\r
26027 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
\r
26028 /******************** COMP Instances with window mode capability **************/
\r
26029 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
\r
26032 /******************************* CRC Instances ********************************/
\r
26033 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
\r
26035 /******************************* DAC Instances ********************************/
\r
26036 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
\r
26037 /******************************* DCMI Instances *******************************/
\r
26038 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
\r
26040 /******************************* DELAYBLOCK Instances *******************************/
\r
26041 #define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
\r
26042 ((INSTANCE) == DLYB_SDMMC2) || \
\r
26043 ((INSTANCE) == DLYB_QUADSPI))
\r
26044 /****************************** DFSDM Instances *******************************/
\r
26045 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
\r
26046 ((INSTANCE) == DFSDM1_Filter1) || \
\r
26047 ((INSTANCE) == DFSDM1_Filter2) || \
\r
26048 ((INSTANCE) == DFSDM1_Filter3))
\r
26050 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
\r
26051 ((INSTANCE) == DFSDM1_Channel1) || \
\r
26052 ((INSTANCE) == DFSDM1_Channel2) || \
\r
26053 ((INSTANCE) == DFSDM1_Channel3) || \
\r
26054 ((INSTANCE) == DFSDM1_Channel4) || \
\r
26055 ((INSTANCE) == DFSDM1_Channel5) || \
\r
26056 ((INSTANCE) == DFSDM1_Channel6) || \
\r
26057 ((INSTANCE) == DFSDM1_Channel7))
\r
26058 /****************************** RAMECC Instances ******************************/
\r
26059 #define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \
\r
26060 ((INSTANCE) == RAMECC1_Monitor2) || \
\r
26061 ((INSTANCE) == RAMECC1_Monitor3) || \
\r
26062 ((INSTANCE) == RAMECC1_Monitor4) || \
\r
26063 ((INSTANCE) == RAMECC1_Monitor5) || \
\r
26064 ((INSTANCE) == RAMECC2_Monitor1) || \
\r
26065 ((INSTANCE) == RAMECC2_Monitor2) || \
\r
26066 ((INSTANCE) == RAMECC2_Monitor3) || \
\r
26067 ((INSTANCE) == RAMECC2_Monitor4) || \
\r
26068 ((INSTANCE) == RAMECC2_Monitor5) || \
\r
26069 ((INSTANCE) == RAMECC3_Monitor1) || \
\r
26070 ((INSTANCE) == RAMECC3_Monitor2))
\r
26072 /******************************** DMA Instances *******************************/
\r
26073 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
\r
26074 ((INSTANCE) == DMA1_Stream1) || \
\r
26075 ((INSTANCE) == DMA1_Stream2) || \
\r
26076 ((INSTANCE) == DMA1_Stream3) || \
\r
26077 ((INSTANCE) == DMA1_Stream4) || \
\r
26078 ((INSTANCE) == DMA1_Stream5) || \
\r
26079 ((INSTANCE) == DMA1_Stream6) || \
\r
26080 ((INSTANCE) == DMA1_Stream7) || \
\r
26081 ((INSTANCE) == DMA2_Stream0) || \
\r
26082 ((INSTANCE) == DMA2_Stream1) || \
\r
26083 ((INSTANCE) == DMA2_Stream2) || \
\r
26084 ((INSTANCE) == DMA2_Stream3) || \
\r
26085 ((INSTANCE) == DMA2_Stream4) || \
\r
26086 ((INSTANCE) == DMA2_Stream5) || \
\r
26087 ((INSTANCE) == DMA2_Stream6) || \
\r
26088 ((INSTANCE) == DMA2_Stream7) || \
\r
26089 ((INSTANCE) == BDMA_Channel0) || \
\r
26090 ((INSTANCE) == BDMA_Channel1) || \
\r
26091 ((INSTANCE) == BDMA_Channel2) || \
\r
26092 ((INSTANCE) == BDMA_Channel3) || \
\r
26093 ((INSTANCE) == BDMA_Channel4) || \
\r
26094 ((INSTANCE) == BDMA_Channel5) || \
\r
26095 ((INSTANCE) == BDMA_Channel6) || \
\r
26096 ((INSTANCE) == BDMA_Channel7))
\r
26098 /****************************** BDMA CHANNEL Instances ***************************/
\r
26099 #define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
\r
26100 ((INSTANCE) == BDMA_Channel1) || \
\r
26101 ((INSTANCE) == BDMA_Channel2) || \
\r
26102 ((INSTANCE) == BDMA_Channel3) || \
\r
26103 ((INSTANCE) == BDMA_Channel4) || \
\r
26104 ((INSTANCE) == BDMA_Channel5) || \
\r
26105 ((INSTANCE) == BDMA_Channel6) || \
\r
26106 ((INSTANCE) == BDMA_Channel7))
\r
26108 /****************************** DMA DMAMUX ALL Instances ***************************/
\r
26109 #define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
\r
26110 ((INSTANCE) == DMA1_Stream1) || \
\r
26111 ((INSTANCE) == DMA1_Stream2) || \
\r
26112 ((INSTANCE) == DMA1_Stream3) || \
\r
26113 ((INSTANCE) == DMA1_Stream4) || \
\r
26114 ((INSTANCE) == DMA1_Stream5) || \
\r
26115 ((INSTANCE) == DMA1_Stream6) || \
\r
26116 ((INSTANCE) == DMA1_Stream7) || \
\r
26117 ((INSTANCE) == DMA2_Stream0) || \
\r
26118 ((INSTANCE) == DMA2_Stream1) || \
\r
26119 ((INSTANCE) == DMA2_Stream2) || \
\r
26120 ((INSTANCE) == DMA2_Stream3) || \
\r
26121 ((INSTANCE) == DMA2_Stream4) || \
\r
26122 ((INSTANCE) == DMA2_Stream5) || \
\r
26123 ((INSTANCE) == DMA2_Stream6) || \
\r
26124 ((INSTANCE) == DMA2_Stream7) || \
\r
26125 ((INSTANCE) == BDMA_Channel0) || \
\r
26126 ((INSTANCE) == BDMA_Channel1) || \
\r
26127 ((INSTANCE) == BDMA_Channel2) || \
\r
26128 ((INSTANCE) == BDMA_Channel3) || \
\r
26129 ((INSTANCE) == BDMA_Channel4) || \
\r
26130 ((INSTANCE) == BDMA_Channel5) || \
\r
26131 ((INSTANCE) == BDMA_Channel6) || \
\r
26132 ((INSTANCE) == BDMA_Channel7))
\r
26134 /****************************** BDMA DMAMUX Instances ***************************/
\r
26135 #define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
\r
26136 ((INSTANCE) == BDMA_Channel1) || \
\r
26137 ((INSTANCE) == BDMA_Channel2) || \
\r
26138 ((INSTANCE) == BDMA_Channel3) || \
\r
26139 ((INSTANCE) == BDMA_Channel4) || \
\r
26140 ((INSTANCE) == BDMA_Channel5) || \
\r
26141 ((INSTANCE) == BDMA_Channel6) || \
\r
26142 ((INSTANCE) == BDMA_Channel7))
\r
26144 /****************************** DMA STREAM Instances ***************************/
\r
26145 #define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
\r
26146 ((INSTANCE) == DMA1_Stream1) || \
\r
26147 ((INSTANCE) == DMA1_Stream2) || \
\r
26148 ((INSTANCE) == DMA1_Stream3) || \
\r
26149 ((INSTANCE) == DMA1_Stream4) || \
\r
26150 ((INSTANCE) == DMA1_Stream5) || \
\r
26151 ((INSTANCE) == DMA1_Stream6) || \
\r
26152 ((INSTANCE) == DMA1_Stream7) || \
\r
26153 ((INSTANCE) == DMA2_Stream0) || \
\r
26154 ((INSTANCE) == DMA2_Stream1) || \
\r
26155 ((INSTANCE) == DMA2_Stream2) || \
\r
26156 ((INSTANCE) == DMA2_Stream3) || \
\r
26157 ((INSTANCE) == DMA2_Stream4) || \
\r
26158 ((INSTANCE) == DMA2_Stream5) || \
\r
26159 ((INSTANCE) == DMA2_Stream6) || \
\r
26160 ((INSTANCE) == DMA2_Stream7))
\r
26162 /****************************** DMA DMAMUX Instances ***************************/
\r
26163 #define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
\r
26164 ((INSTANCE) == DMA1_Stream1) || \
\r
26165 ((INSTANCE) == DMA1_Stream2) || \
\r
26166 ((INSTANCE) == DMA1_Stream3) || \
\r
26167 ((INSTANCE) == DMA1_Stream4) || \
\r
26168 ((INSTANCE) == DMA1_Stream5) || \
\r
26169 ((INSTANCE) == DMA1_Stream6) || \
\r
26170 ((INSTANCE) == DMA1_Stream7) || \
\r
26171 ((INSTANCE) == DMA2_Stream0) || \
\r
26172 ((INSTANCE) == DMA2_Stream1) || \
\r
26173 ((INSTANCE) == DMA2_Stream2) || \
\r
26174 ((INSTANCE) == DMA2_Stream3) || \
\r
26175 ((INSTANCE) == DMA2_Stream4) || \
\r
26176 ((INSTANCE) == DMA2_Stream5) || \
\r
26177 ((INSTANCE) == DMA2_Stream6) || \
\r
26178 ((INSTANCE) == DMA2_Stream7))
\r
26180 /******************************** DMA Request Generator Instances **************/
\r
26181 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
\r
26182 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
\r
26183 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
\r
26184 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
\r
26185 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
\r
26186 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
\r
26187 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
\r
26188 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
\r
26189 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
\r
26190 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
\r
26191 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
\r
26192 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
\r
26193 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
\r
26194 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
\r
26195 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
\r
26196 ((INSTANCE) == DMAMUX2_RequestGenerator7))
\r
26198 /******************************* DMA2D Instances *******************************/
\r
26199 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
\r
26201 /******************************** MDMA Request Generator Instances **************/
\r
26202 #define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
\r
26203 ((INSTANCE) == MDMA_Channel1) || \
\r
26204 ((INSTANCE) == MDMA_Channel2) || \
\r
26205 ((INSTANCE) == MDMA_Channel3) || \
\r
26206 ((INSTANCE) == MDMA_Channel4) || \
\r
26207 ((INSTANCE) == MDMA_Channel5) || \
\r
26208 ((INSTANCE) == MDMA_Channel6) || \
\r
26209 ((INSTANCE) == MDMA_Channel7) || \
\r
26210 ((INSTANCE) == MDMA_Channel8) || \
\r
26211 ((INSTANCE) == MDMA_Channel9) || \
\r
26212 ((INSTANCE) == MDMA_Channel10) || \
\r
26213 ((INSTANCE) == MDMA_Channel11) || \
\r
26214 ((INSTANCE) == MDMA_Channel12) || \
\r
26215 ((INSTANCE) == MDMA_Channel13) || \
\r
26216 ((INSTANCE) == MDMA_Channel14) || \
\r
26217 ((INSTANCE) == MDMA_Channel15))
\r
26219 /******************************* QUADSPI Instances *******************************/
\r
26220 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
\r
26222 /******************************* FDCAN Instances ******************************/
\r
26223 #define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
\r
26224 ((__INSTANCE__) == FDCAN2))
\r
26226 #define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
\r
26228 /******************************* GPIO Instances *******************************/
\r
26229 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
\r
26230 ((INSTANCE) == GPIOB) || \
\r
26231 ((INSTANCE) == GPIOC) || \
\r
26232 ((INSTANCE) == GPIOD) || \
\r
26233 ((INSTANCE) == GPIOE) || \
\r
26234 ((INSTANCE) == GPIOF) || \
\r
26235 ((INSTANCE) == GPIOG) || \
\r
26236 ((INSTANCE) == GPIOH) || \
\r
26237 ((INSTANCE) == GPIOI) || \
\r
26238 ((INSTANCE) == GPIOJ) || \
\r
26239 ((INSTANCE) == GPIOK))
\r
26241 /******************************* GPIO AF Instances ****************************/
\r
26242 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
\r
26244 /**************************** GPIO Lock Instances *****************************/
\r
26245 /* On H7, all GPIO Bank support the Lock mechanism */
\r
26246 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
\r
26248 /******************************** HSEM Instances *******************************/
\r
26249 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
\r
26250 /******************** Bit definition for HSEM_CR register *****************/
\r
26251 #define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
\r
26252 #define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */
\r
26253 #if defined(CORE_CM4)
\r
26254 #define HSEM_CR_COREID_CURRENT (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
\r
26255 #else /* CORE_CM7 */
\r
26256 #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
\r
26257 #endif /* CORE_CM4 */
\r
26259 #define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
\r
26260 #define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
\r
26262 #define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
\r
26263 #define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
\r
26265 #define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
\r
26266 #define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
\r
26268 /******************************** I2C Instances *******************************/
\r
26269 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
\r
26270 ((INSTANCE) == I2C2) || \
\r
26271 ((INSTANCE) == I2C3) || \
\r
26272 ((INSTANCE) == I2C4))
\r
26273 /************** I2C Instances : wakeup capability from stop modes *************/
\r
26274 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
\r
26276 /****************************** SMBUS Instances *******************************/
\r
26277 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
\r
26278 ((INSTANCE) == I2C2) || \
\r
26279 ((INSTANCE) == I2C3) || \
\r
26280 ((INSTANCE) == I2C4))
\r
26281 /******************************** I2S Instances *******************************/
\r
26282 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
\r
26283 ((INSTANCE) == SPI2) || \
\r
26284 ((INSTANCE) == SPI3))
\r
26286 /****************************** LTDC Instances ********************************/
\r
26287 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
\r
26289 /******************************* RNG Instances ********************************/
\r
26290 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
\r
26292 /****************************** RTC Instances *********************************/
\r
26293 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
\r
26295 /****************************** SDMMC Instances *********************************/
\r
26296 #define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
\r
26297 ((_INSTANCE_) == SDMMC2))
\r
26299 /******************************** SMBUS Instances *****************************/
\r
26300 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
\r
26302 /******************************** SPI Instances *******************************/
\r
26303 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
\r
26304 ((INSTANCE) == SPI2) || \
\r
26305 ((INSTANCE) == SPI3) || \
\r
26306 ((INSTANCE) == SPI4) || \
\r
26307 ((INSTANCE) == SPI5) || \
\r
26308 ((INSTANCE) == SPI6))
\r
26310 #define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
\r
26311 ((INSTANCE) == SPI2) || \
\r
26312 ((INSTANCE) == SPI3))
\r
26314 /******************************** SWPMI Instances *****************************/
\r
26315 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
\r
26317 /****************** LPTIM Instances : All supported instances *****************/
\r
26318 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
\r
26319 ((INSTANCE) == LPTIM2) || \
\r
26320 ((INSTANCE) == LPTIM3) || \
\r
26321 ((INSTANCE) == LPTIM4) || \
\r
26322 ((INSTANCE) == LPTIM5))
\r
26324 /****************** LPTIM Instances : supporting encoder interface **************/
\r
26325 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
\r
26326 ((INSTANCE) == LPTIM2))
\r
26328 /****************** TIM Instances : All supported instances *******************/
\r
26329 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26330 ((INSTANCE) == TIM2) || \
\r
26331 ((INSTANCE) == TIM3) || \
\r
26332 ((INSTANCE) == TIM4) || \
\r
26333 ((INSTANCE) == TIM5) || \
\r
26334 ((INSTANCE) == TIM6) || \
\r
26335 ((INSTANCE) == TIM7) || \
\r
26336 ((INSTANCE) == TIM8) || \
\r
26337 ((INSTANCE) == TIM12) || \
\r
26338 ((INSTANCE) == TIM13) || \
\r
26339 ((INSTANCE) == TIM14) || \
\r
26340 ((INSTANCE) == TIM15) || \
\r
26341 ((INSTANCE) == TIM16) || \
\r
26342 ((INSTANCE) == TIM17))
\r
26343 /************* TIM Instances : at least 1 capture/compare channel *************/
\r
26344 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26345 ((INSTANCE) == TIM2) || \
\r
26346 ((INSTANCE) == TIM3) || \
\r
26347 ((INSTANCE) == TIM4) || \
\r
26348 ((INSTANCE) == TIM5) || \
\r
26349 ((INSTANCE) == TIM8) || \
\r
26350 ((INSTANCE) == TIM12) || \
\r
26351 ((INSTANCE) == TIM13) || \
\r
26352 ((INSTANCE) == TIM14) || \
\r
26353 ((INSTANCE) == TIM15) || \
\r
26354 ((INSTANCE) == TIM16) || \
\r
26355 ((INSTANCE) == TIM17))
\r
26356 /************ TIM Instances : at least 2 capture/compare channels *************/
\r
26357 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26358 ((INSTANCE) == TIM2) || \
\r
26359 ((INSTANCE) == TIM3) || \
\r
26360 ((INSTANCE) == TIM4) || \
\r
26361 ((INSTANCE) == TIM5) || \
\r
26362 ((INSTANCE) == TIM8) || \
\r
26363 ((INSTANCE) == TIM12) || \
\r
26364 ((INSTANCE) == TIM15))
\r
26365 /************ TIM Instances : at least 3 capture/compare channels *************/
\r
26366 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26367 ((INSTANCE) == TIM2) || \
\r
26368 ((INSTANCE) == TIM3) || \
\r
26369 ((INSTANCE) == TIM4) || \
\r
26370 ((INSTANCE) == TIM5) || \
\r
26371 ((INSTANCE) == TIM8))
\r
26373 /************ TIM Instances : at least 4 capture/compare channels *************/
\r
26374 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26375 ((INSTANCE) == TIM2) || \
\r
26376 ((INSTANCE) == TIM3) || \
\r
26377 ((INSTANCE) == TIM4) || \
\r
26378 ((INSTANCE) == TIM5) || \
\r
26379 ((INSTANCE) == TIM8))
\r
26380 /************ TIM Instances : at least 5 capture/compare channels *************/
\r
26381 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26382 ((INSTANCE) == TIM8))
\r
26383 /************ TIM Instances : at least 6 capture/compare channels *************/
\r
26384 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26385 ((INSTANCE) == TIM8))
\r
26387 /******************** TIM Instances : Advanced-control timers *****************/
\r
26388 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
26389 ((__INSTANCE__) == TIM8))
\r
26391 /******************** TIM Instances : Advanced-control timers *****************/
\r
26393 /******************* TIM Instances : Timer input XOR function *****************/
\r
26394 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26395 ((INSTANCE) == TIM2) || \
\r
26396 ((INSTANCE) == TIM3) || \
\r
26397 ((INSTANCE) == TIM4) || \
\r
26398 ((INSTANCE) == TIM5) || \
\r
26399 ((INSTANCE) == TIM8) || \
\r
26400 ((INSTANCE) == TIM15))
\r
26402 /****************** TIM Instances : DMA requests generation (UDE) *************/
\r
26403 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26404 ((INSTANCE) == TIM2) || \
\r
26405 ((INSTANCE) == TIM3) || \
\r
26406 ((INSTANCE) == TIM4) || \
\r
26407 ((INSTANCE) == TIM5) || \
\r
26408 ((INSTANCE) == TIM6) || \
\r
26409 ((INSTANCE) == TIM7) || \
\r
26410 ((INSTANCE) == TIM8) || \
\r
26411 ((INSTANCE) == TIM15) || \
\r
26412 ((INSTANCE) == TIM16) || \
\r
26413 ((INSTANCE) == TIM17))
\r
26415 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
\r
26416 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26417 ((INSTANCE) == TIM2) || \
\r
26418 ((INSTANCE) == TIM3) || \
\r
26419 ((INSTANCE) == TIM4) || \
\r
26420 ((INSTANCE) == TIM5) || \
\r
26421 ((INSTANCE) == TIM8) || \
\r
26422 ((INSTANCE) == TIM15) || \
\r
26423 ((INSTANCE) == TIM16) || \
\r
26424 ((INSTANCE) == TIM17))
\r
26426 /************ TIM Instances : DMA requests generation (COMDE) *****************/
\r
26427 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26428 ((INSTANCE) == TIM2) || \
\r
26429 ((INSTANCE) == TIM3) || \
\r
26430 ((INSTANCE) == TIM4) || \
\r
26431 ((INSTANCE) == TIM5) || \
\r
26432 ((INSTANCE) == TIM8) || \
\r
26433 ((INSTANCE) == TIM15))
\r
26435 /******************** TIM Instances : DMA burst feature ***********************/
\r
26436 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26437 ((INSTANCE) == TIM2) || \
\r
26438 ((INSTANCE) == TIM3) || \
\r
26439 ((INSTANCE) == TIM4) || \
\r
26440 ((INSTANCE) == TIM5) || \
\r
26441 ((INSTANCE) == TIM8))
\r
26443 /*************** TIM Instances : external trigger reamp input available *******/
\r
26444 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26445 ((INSTANCE) == TIM2) || \
\r
26446 ((INSTANCE) == TIM3) || \
\r
26447 ((INSTANCE) == TIM4) || \
\r
26448 ((INSTANCE) == TIM5) || \
\r
26449 ((INSTANCE) == TIM8))
\r
26450 /****************** TIM Instances : remapping capability **********************/
\r
26451 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
26452 ((__INSTANCE__) == TIM2) || \
\r
26453 ((__INSTANCE__) == TIM3) || \
\r
26454 ((__INSTANCE__) == TIM5) || \
\r
26455 ((__INSTANCE__) == TIM16) || \
\r
26456 ((__INSTANCE__) == TIM17))
\r
26458 /*************** TIM Instances : external trigger reamp input available *******/
\r
26459 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26460 ((INSTANCE) == TIM2) || \
\r
26461 ((INSTANCE) == TIM3) || \
\r
26462 ((INSTANCE) == TIM5) || \
\r
26463 ((INSTANCE) == TIM8))
\r
26465 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
\r
26466 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26467 ((INSTANCE) == TIM2) || \
\r
26468 ((INSTANCE) == TIM3) || \
\r
26469 ((INSTANCE) == TIM4) || \
\r
26470 ((INSTANCE) == TIM5) || \
\r
26471 ((INSTANCE) == TIM6) || \
\r
26472 ((INSTANCE) == TIM7) || \
\r
26473 ((INSTANCE) == TIM8) || \
\r
26474 ((INSTANCE) == TIM15))
\r
26475 /****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
\r
26476 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26477 ((INSTANCE) == TIM2) || \
\r
26478 ((INSTANCE) == TIM3) || \
\r
26479 ((INSTANCE) == TIM4) || \
\r
26480 ((INSTANCE) == TIM5) || \
\r
26481 ((INSTANCE) == TIM8) || \
\r
26482 ((INSTANCE) == TIM12))
\r
26484 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
\r
26485 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26486 ((INSTANCE) == TIM8))
\r
26488 /****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
\r
26489 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26490 ((INSTANCE) == TIM2) || \
\r
26491 ((INSTANCE) == TIM3) || \
\r
26492 ((INSTANCE) == TIM4) || \
\r
26493 ((INSTANCE) == TIM5) || \
\r
26494 ((INSTANCE) == TIM8) || \
\r
26495 ((INSTANCE) == TIM15) || \
\r
26496 ((INSTANCE) == TIM16) || \
\r
26497 ((INSTANCE) == TIM17))
\r
26499 /****************** TIM Instances : supporting commutation event *************/
\r
26500 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26501 ((INSTANCE) == TIM8) || \
\r
26502 ((INSTANCE) == TIM15) || \
\r
26503 ((INSTANCE) == TIM16) || \
\r
26504 ((INSTANCE) == TIM17))
\r
26506 /****************** TIM Instances : supporting encoder interface **************/
\r
26507 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
26508 ((__INSTANCE__) == TIM2) || \
\r
26509 ((__INSTANCE__) == TIM3) || \
\r
26510 ((__INSTANCE__) == TIM4) || \
\r
26511 ((__INSTANCE__) == TIM5) || \
\r
26512 ((__INSTANCE__) == TIM8))
\r
26514 /****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
\r
26515 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26516 ((INSTANCE) == TIM8))
\r
26517 /******************* TIM Instances : output(s) available **********************/
\r
26518 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
\r
26519 ((((INSTANCE) == TIM1) && \
\r
26520 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
26521 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
26522 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
26523 ((CHANNEL) == TIM_CHANNEL_4) || \
\r
26524 ((CHANNEL) == TIM_CHANNEL_5) || \
\r
26525 ((CHANNEL) == TIM_CHANNEL_6))) \
\r
26527 (((INSTANCE) == TIM2) && \
\r
26528 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
26529 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
26530 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
26531 ((CHANNEL) == TIM_CHANNEL_4))) \
\r
26533 (((INSTANCE) == TIM3) && \
\r
26534 (((CHANNEL) == TIM_CHANNEL_1)|| \
\r
26535 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
26536 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
26537 ((CHANNEL) == TIM_CHANNEL_4))) \
\r
26539 (((INSTANCE) == TIM4) && \
\r
26540 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
26541 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
26542 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
26543 ((CHANNEL) == TIM_CHANNEL_4))) \
\r
26545 (((INSTANCE) == TIM5) && \
\r
26546 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
26547 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
26548 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
26549 ((CHANNEL) == TIM_CHANNEL_4))) \
\r
26551 (((INSTANCE) == TIM8) && \
\r
26552 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
26553 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
26554 ((CHANNEL) == TIM_CHANNEL_3) || \
\r
26555 ((CHANNEL) == TIM_CHANNEL_4) || \
\r
26556 ((CHANNEL) == TIM_CHANNEL_5) || \
\r
26557 ((CHANNEL) == TIM_CHANNEL_6))) \
\r
26559 (((INSTANCE) == TIM12) && \
\r
26560 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
26561 ((CHANNEL) == TIM_CHANNEL_2))) \
\r
26563 (((INSTANCE) == TIM13) && \
\r
26564 (((CHANNEL) == TIM_CHANNEL_1))) \
\r
26566 (((INSTANCE) == TIM14) && \
\r
26567 (((CHANNEL) == TIM_CHANNEL_1))) \
\r
26569 (((INSTANCE) == TIM15) && \
\r
26570 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
26571 ((CHANNEL) == TIM_CHANNEL_2))) \
\r
26573 (((INSTANCE) == TIM16) && \
\r
26574 (((CHANNEL) == TIM_CHANNEL_1))) \
\r
26576 (((INSTANCE) == TIM17) && \
\r
26577 (((CHANNEL) == TIM_CHANNEL_1))))
\r
26579 /****************** TIM Instances : supporting the break function *************/
\r
26580 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
\r
26581 (((INSTANCE) == TIM1) || \
\r
26582 ((INSTANCE) == TIM8) || \
\r
26583 ((INSTANCE) == TIM15) || \
\r
26584 ((INSTANCE) == TIM16) || \
\r
26585 ((INSTANCE) == TIM17))
\r
26587 /************** TIM Instances : supporting Break source selection *************/
\r
26588 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
\r
26589 ((INSTANCE) == TIM8))
\r
26591 /****************** TIM Instances : supporting complementary output(s) ********/
\r
26592 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
\r
26593 ((((INSTANCE) == TIM1) && \
\r
26594 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
26595 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
26596 ((CHANNEL) == TIM_CHANNEL_3))) \
\r
26598 (((INSTANCE) == TIM8) && \
\r
26599 (((CHANNEL) == TIM_CHANNEL_1) || \
\r
26600 ((CHANNEL) == TIM_CHANNEL_2) || \
\r
26601 ((CHANNEL) == TIM_CHANNEL_3))) \
\r
26603 (((INSTANCE) == TIM15) && \
\r
26604 ((CHANNEL) == TIM_CHANNEL_1)) \
\r
26606 (((INSTANCE) == TIM16) && \
\r
26607 ((CHANNEL) == TIM_CHANNEL_1)) \
\r
26609 (((INSTANCE) == TIM17) && \
\r
26610 ((CHANNEL) == TIM_CHANNEL_1)))
\r
26612 /****************** TIM Instances : supporting counting mode selection ********/
\r
26613 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
\r
26614 (((INSTANCE) == TIM1) || \
\r
26615 ((INSTANCE) == TIM2) || \
\r
26616 ((INSTANCE) == TIM3) || \
\r
26617 ((INSTANCE) == TIM4) || \
\r
26618 ((INSTANCE) == TIM5) || \
\r
26619 ((INSTANCE) == TIM8))
\r
26621 /****************** TIM Instances : supporting repetition counter *************/
\r
26622 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
\r
26623 (((INSTANCE) == TIM1) || \
\r
26624 ((INSTANCE) == TIM8) || \
\r
26625 ((INSTANCE) == TIM15) || \
\r
26626 ((INSTANCE) == TIM16) || \
\r
26627 ((INSTANCE) == TIM17))
\r
26629 /****************** TIM Instances : supporting synchronization ****************/
\r
26630 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
\r
26631 (((__INSTANCE__) == TIM1) || \
\r
26632 ((__INSTANCE__) == TIM2) || \
\r
26633 ((__INSTANCE__) == TIM3) || \
\r
26634 ((__INSTANCE__) == TIM4) || \
\r
26635 ((__INSTANCE__) == TIM5) || \
\r
26636 ((__INSTANCE__) == TIM8) || \
\r
26637 ((__INSTANCE__) == TIM12) || \
\r
26638 ((__INSTANCE__) == TIM15))
\r
26640 /****************** TIM Instances : supporting clock division *****************/
\r
26641 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
\r
26642 (((INSTANCE) == TIM1) || \
\r
26643 ((INSTANCE) == TIM2) || \
\r
26644 ((INSTANCE) == TIM3) || \
\r
26645 ((INSTANCE) == TIM4) || \
\r
26646 ((INSTANCE) == TIM5) || \
\r
26647 ((INSTANCE) == TIM8) || \
\r
26648 ((INSTANCE) == TIM15) || \
\r
26649 ((INSTANCE) == TIM16) || \
\r
26650 ((INSTANCE) == TIM17))
\r
26651 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
\r
26652 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
\r
26653 (((INSTANCE) == TIM1) || \
\r
26654 ((INSTANCE) == TIM2) || \
\r
26655 ((INSTANCE) == TIM3) || \
\r
26656 ((INSTANCE) == TIM4) || \
\r
26657 ((INSTANCE) == TIM5) || \
\r
26658 ((INSTANCE) == TIM8))
\r
26660 /****************** TIM Instances : supporting external clock mode 2 **********/
\r
26661 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
\r
26662 (((INSTANCE) == TIM1) || \
\r
26663 ((INSTANCE) == TIM2) || \
\r
26664 ((INSTANCE) == TIM3) || \
\r
26665 ((INSTANCE) == TIM4) || \
\r
26666 ((INSTANCE) == TIM5) || \
\r
26667 ((INSTANCE) == TIM8))
\r
26668 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
\r
26669 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
\r
26670 (((INSTANCE) == TIM1) || \
\r
26671 ((INSTANCE) == TIM2) || \
\r
26672 ((INSTANCE) == TIM3) || \
\r
26673 ((INSTANCE) == TIM4) || \
\r
26674 ((INSTANCE) == TIM5) || \
\r
26675 ((INSTANCE) == TIM8) || \
\r
26676 ((INSTANCE) == TIM15))
\r
26678 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
\r
26679 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
\r
26680 (((INSTANCE) == TIM1) || \
\r
26681 ((INSTANCE) == TIM2) || \
\r
26682 ((INSTANCE) == TIM3) || \
\r
26683 ((INSTANCE) == TIM4) || \
\r
26684 ((INSTANCE) == TIM5) || \
\r
26685 ((INSTANCE) == TIM8) || \
\r
26686 ((INSTANCE) == TIM15))
\r
26688 /****************** TIM Instances : supporting OCxREF clear *******************/
\r
26689 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
\r
26690 (((INSTANCE) == TIM1) || \
\r
26691 ((INSTANCE) == TIM2) || \
\r
26692 ((INSTANCE) == TIM3))
\r
26693 /****************** TIM Instances : TIM_32B_COUNTER ***************************/
\r
26694 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
\r
26695 (((INSTANCE) == TIM2) || \
\r
26696 ((INSTANCE) == TIM5))
\r
26698 /****************** TIM Instances : TIM_BKIN2 ***************************/
\r
26699 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
\r
26700 (((INSTANCE) == TIM1) || \
\r
26701 ((INSTANCE) == TIM8))
\r
26703 /****************** TIM Instances : supporting Hall sensor interface **********/
\r
26704 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
\r
26705 ((__INSTANCE__) == TIM2) || \
\r
26706 ((__INSTANCE__) == TIM3) || \
\r
26707 ((__INSTANCE__) == TIM4) || \
\r
26708 ((__INSTANCE__) == TIM5) || \
\r
26709 ((__INSTANCE__) == TIM15) || \
\r
26710 ((__INSTANCE__) == TIM8))
\r
26712 /****************************** HRTIM Instances *******************************/
\r
26713 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
\r
26715 /******************** USART Instances : Synchronous mode **********************/
\r
26716 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26717 ((INSTANCE) == USART2) || \
\r
26718 ((INSTANCE) == USART3) || \
\r
26719 ((INSTANCE) == USART6))
\r
26721 /******************** USART Instances : SPI slave mode ************************/
\r
26722 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26723 ((INSTANCE) == USART2) || \
\r
26724 ((INSTANCE) == USART3) || \
\r
26725 ((INSTANCE) == USART6))
\r
26727 /******************** UART Instances : Asynchronous mode **********************/
\r
26728 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26729 ((INSTANCE) == USART2) || \
\r
26730 ((INSTANCE) == USART3) || \
\r
26731 ((INSTANCE) == UART4) || \
\r
26732 ((INSTANCE) == UART5) || \
\r
26733 ((INSTANCE) == USART6) || \
\r
26734 ((INSTANCE) == UART7) || \
\r
26735 ((INSTANCE) == UART8))
\r
26737 /******************** UART Instances : FIFO mode.******************************/
\r
26738 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26739 ((INSTANCE) == USART2) || \
\r
26740 ((INSTANCE) == USART3) || \
\r
26741 ((INSTANCE) == UART4) || \
\r
26742 ((INSTANCE) == UART5) || \
\r
26743 ((INSTANCE) == USART6) || \
\r
26744 ((INSTANCE) == UART7) || \
\r
26745 ((INSTANCE) == UART8))
\r
26747 /****************** UART Instances : Auto Baud Rate detection *****************/
\r
26748 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26749 ((INSTANCE) == USART2) || \
\r
26750 ((INSTANCE) == USART3) || \
\r
26751 ((INSTANCE) == UART4) || \
\r
26752 ((INSTANCE) == UART5) || \
\r
26753 ((INSTANCE) == USART6) || \
\r
26754 ((INSTANCE) == UART7) || \
\r
26755 ((INSTANCE) == UART8))
\r
26757 /*********************** UART Instances : Driver Enable ***********************/
\r
26758 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26759 ((INSTANCE) == USART2) || \
\r
26760 ((INSTANCE) == USART3) || \
\r
26761 ((INSTANCE) == UART4) || \
\r
26762 ((INSTANCE) == UART5) || \
\r
26763 ((INSTANCE) == USART6) || \
\r
26764 ((INSTANCE) == UART7) || \
\r
26765 ((INSTANCE) == UART8) || \
\r
26766 ((INSTANCE) == LPUART1))
\r
26768 /********************* UART Instances : Half-Duplex mode **********************/
\r
26769 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26770 ((INSTANCE) == USART2) || \
\r
26771 ((INSTANCE) == USART3) || \
\r
26772 ((INSTANCE) == UART4) || \
\r
26773 ((INSTANCE) == UART5) || \
\r
26774 ((INSTANCE) == USART6) || \
\r
26775 ((INSTANCE) == UART7) || \
\r
26776 ((INSTANCE) == UART8) || \
\r
26777 ((INSTANCE) == LPUART1))
\r
26779 /******************* UART Instances : Hardware Flow control *******************/
\r
26780 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26781 ((INSTANCE) == USART2) || \
\r
26782 ((INSTANCE) == USART3) || \
\r
26783 ((INSTANCE) == UART4) || \
\r
26784 ((INSTANCE) == UART5) || \
\r
26785 ((INSTANCE) == USART6) || \
\r
26786 ((INSTANCE) == UART7) || \
\r
26787 ((INSTANCE) == UART8) || \
\r
26788 ((INSTANCE) == LPUART1))
\r
26790 /************************* UART Instances : LIN mode **************************/
\r
26791 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26792 ((INSTANCE) == USART2) || \
\r
26793 ((INSTANCE) == USART3) || \
\r
26794 ((INSTANCE) == UART4) || \
\r
26795 ((INSTANCE) == UART5) || \
\r
26796 ((INSTANCE) == USART6) || \
\r
26797 ((INSTANCE) == UART7) || \
\r
26798 ((INSTANCE) == UART8))
\r
26800 /****************** UART Instances : Wake-up from Stop mode *******************/
\r
26801 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26802 ((INSTANCE) == USART2) || \
\r
26803 ((INSTANCE) == USART3) || \
\r
26804 ((INSTANCE) == UART4) || \
\r
26805 ((INSTANCE) == UART5) || \
\r
26806 ((INSTANCE) == USART6) || \
\r
26807 ((INSTANCE) == UART7) || \
\r
26808 ((INSTANCE) == UART8) || \
\r
26809 ((INSTANCE) == LPUART1))
\r
26811 /************************* UART Instances : IRDA mode *************************/
\r
26812 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26813 ((INSTANCE) == USART2) || \
\r
26814 ((INSTANCE) == USART3) || \
\r
26815 ((INSTANCE) == UART4) || \
\r
26816 ((INSTANCE) == UART5) || \
\r
26817 ((INSTANCE) == USART6) || \
\r
26818 ((INSTANCE) == UART7) || \
\r
26819 ((INSTANCE) == UART8))
\r
26821 /********************* USART Instances : Smard card mode **********************/
\r
26822 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
\r
26823 ((INSTANCE) == USART2) || \
\r
26824 ((INSTANCE) == USART3) || \
\r
26825 ((INSTANCE) == USART6))
\r
26827 /****************************** LPUART Instance *******************************/
\r
26828 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
\r
26830 /****************************** IWDG Instances ********************************/
\r
26831 #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))
\r
26832 /****************************** USB Instances ********************************/
\r
26833 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
\r
26835 /****************************** WWDG Instances ********************************/
\r
26836 #define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG1) || \
\r
26837 ((INSTANCE) == WWDG2))
\r
26838 /****************************** MDIOS Instances ********************************/
\r
26839 #define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
\r
26841 /****************************** CEC Instances *********************************/
\r
26842 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
\r
26844 /****************************** SAI Instances ********************************/
\r
26845 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
\r
26846 ((INSTANCE) == SAI1_Block_B) || \
\r
26847 ((INSTANCE) == SAI2_Block_A) || \
\r
26848 ((INSTANCE) == SAI2_Block_B) || \
\r
26849 ((INSTANCE) == SAI3_Block_A) || \
\r
26850 ((INSTANCE) == SAI3_Block_B) || \
\r
26851 ((INSTANCE) == SAI4_Block_A) || \
\r
26852 ((INSTANCE) == SAI4_Block_B))
\r
26854 /****************************** SPDIFRX Instances ********************************/
\r
26855 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
\r
26857 /****************************** OPAMP Instances *******************************/
\r
26858 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
\r
26859 ((INSTANCE) == OPAMP2))
\r
26861 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
\r
26863 /*********************** USB OTG PCD Instances ********************************/
\r
26864 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
\r
26865 ((INSTANCE) == USB_OTG_HS))
\r
26867 /*********************** USB OTG HCD Instances ********************************/
\r
26868 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
\r
26869 ((INSTANCE) == USB_OTG_HS))
\r
26871 /******************************************************************************/
\r
26872 /* For a painless codes migration between the STM32H7xx device product */
\r
26873 /* lines, or with STM32F7xx devices the aliases defined below are put */
\r
26874 /* in place to overcome the differences in the interrupt handlers and IRQn */
\r
26875 /* definitions. No need to update developed interrupt code when moving */
\r
26876 /* across product lines within the same STM32H7 Family */
\r
26877 /******************************************************************************/
\r
26879 /* Aliases for __IRQn */
\r
26880 #define HASH_RNG_IRQn RNG_IRQn
\r
26881 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
\r
26882 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
\r
26883 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
\r
26884 #define PVD_IRQn PVD_AVD_IRQn
\r
26887 /* Aliases for __IRQHandler */
\r
26888 #define HASH_RNG_IRQHandler RNG_IRQHandler
\r
26889 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
\r
26890 #define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
\r
26891 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
\r
26892 #define PVD_IRQHandler PVD_AVD_IRQHandler
\r
26897 /****************************** Product define *********************************/
\r
26898 #define FLASH_SIZE 0x200000UL /* 2 MB */
\r
26899 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
\r
26900 #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
\r
26901 #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
\r
26913 #ifdef __cplusplus
\r
26915 #endif /* __cplusplus */
\r
26917 #endif /* STM32H745xx_H */
\r
26919 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r
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